From 5e49e6c1a5a4ed950db9266262ebe37671922b27 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 15:04:09 +0100 Subject: [PATCH 01/92] Parse `asm` template --- src/parser.cpp | 374 +++++++++++++++++++++++++++++++++++---------- src/parser.hpp | 41 +++++ src/parser_pos.cpp | 42 +++++ 3 files changed, 378 insertions(+), 79 deletions(-) diff --git a/src/parser.cpp b/src/parser.cpp index d981491dd..0e2f77a93 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -520,8 +520,37 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->MatrixType.column_count = clone_ast(n->MatrixType.column_count, f); n->MatrixType.elem = clone_ast(n->MatrixType.elem, f); break; - } + case Ast_AsmTemplate: + n->AsmTemplate.signature = clone_ast(n->AsmTemplate.signature, f); + n->AsmTemplate.specs = clone_ast_array(n->AsmTemplate.specs, f); + n->AsmTemplate.clobbers = clone_ast_array(n->AsmTemplate.clobbers, f); + n->AsmTemplate.instructions = clone_ast_array(n->AsmTemplate.instructions, f); + break; + case Ast_AsmRegister: + break; + case Ast_AsmSpec: + n->AsmSpec.name = clone_ast(n->AsmSpec.name, f); + n->AsmSpec.tied_name = clone_ast(n->AsmSpec.tied_name, f); + n->AsmSpec.type = clone_ast(n->AsmSpec.type, f); + n->AsmSpec.value = clone_ast(n->AsmSpec.value, f); + break; + case Ast_AsmClobber: + n->AsmClobber.value = clone_ast(n->AsmClobber.value, f); + break; + case Ast_AsmLabelDecl: + n->AsmLabelDecl.name = clone_ast(n->AsmLabelDecl.name, f); + break; + case Ast_AsmInstruction: + n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); + break; + case Ast_AsmMemoryOperand: + n->AsmMemoryOperand.base = clone_ast(n->AsmMemoryOperand.base, f); + n->AsmMemoryOperand.index = clone_ast(n->AsmMemoryOperand.index, f); + n->AsmMemoryOperand.scale = clone_ast(n->AsmMemoryOperand.scale, f); + n->AsmMemoryOperand.disp = clone_ast(n->AsmMemoryOperand.disp, f); + break; + } return n; } @@ -1727,7 +1756,7 @@ gb_internal Token expect_operator(AstFile *f) { syntax_error(prev, "'..' for ranges are not allowed, did you mean '..<' or '..='?"); f->tokens[f->curr_token_index].flags |= TokenFlag_Replace; } - + advance_token(f); return prev; } @@ -2379,6 +2408,268 @@ gb_internal void parser_check_polymorphic_record_parameters(AstFile *f, Ast *pol } +gb_internal Ast *parse_asm_register(AstFile *f) { + Token token = expect_token(f, Token_Mod); + Token name = expect_token(f, Token_Ident); + Ast *reg = alloc_ast_node(f, Ast_AsmRegister); + reg->AsmRegister.token = token; + reg->AsmRegister.name = name; + return reg; +} +gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { + switch (f->curr_token.kind) { + case Token_Period: + { + Token token = expect_token(f, Token_Period); + Ast *name = parse_ident(f); + Ast *label_decl = alloc_ast_node(f, Ast_AsmLabelDecl); + label_decl->AsmLabelDecl.token = token; + label_decl->AsmLabelDecl.name = name; + return label_decl; + } + case Token_Ident: + return parse_ident(f); + case Token_Mod: + return parse_asm_register(f); + case Token_Integer: + case Token_Float: + case Token_Rune: + return ast_basic_lit(f, advance_token(f)); + case Token_OpenBracket: + if (allow_memory_operand) { + Token open = expect_token(f, Token_OpenBracket); + Ast *base = nullptr; + Ast *index = nullptr; + Ast *scale = nullptr; + Ast *disp = nullptr; + + base = parse_asm_operand(f, false); + + if (allow_token(f, Token_Add)) { + Ast *possible_index = parse_asm_operand(f, false); + if (allow_token(f, Token_Mul)) { + index = possible_index; + scale = parse_asm_operand(f, false); + if (allow_token(f, Token_Add)) { + disp = parse_asm_operand(f, false); + } + } else { + disp = possible_index; + } + } + + Token close = expect_token(f, Token_CloseBracket); + + Ast *mem = alloc_ast_node(f, Ast_AsmMemoryOperand); + mem->AsmMemoryOperand.open = open; + mem->AsmMemoryOperand.base = base; + mem->AsmMemoryOperand.index = index; + mem->AsmMemoryOperand.scale = scale; + mem->AsmMemoryOperand.disp = disp; + mem->AsmMemoryOperand.close = close; + + return mem; + } + break; + } + + syntax_error(f->curr_token, "Invalid asm operand, found '%.*s'", LIT(f->curr_token.string)); + advance_token(f); + return nullptr; +} + +gb_internal Slice parse_asm_operands(AstFile *f) { + Array operands = {}; + operands.allocator = heap_allocator(); + + while (f->curr_token.kind != Token_Semicolon && + f->curr_token.kind != Token_EOF) { + Ast *operand = parse_asm_operand(f, true); + if (operand != nullptr) { + array_add(&operands, operand); + } + if (!allow_token(f, Token_Comma)) { + break; + } + } + + if (allow_token(f, Token_Semicolon)) { + // okay + } + + return slice_from_array(operands); +} + +gb_internal Ast *parse_asm_instruction(AstFile *f) { + if (allow_token(f, Token_Semicolon)) { + return nullptr; + } + switch (f->curr_token.kind) { + default: + if (!token_is_keyword(f->curr_token.kind)) { + break; + } + /*fallthrough*/ + case Token_Ident: + { + Token name = advance_token(f); + auto operands = parse_asm_operands(f); + Ast *instruction = alloc_ast_node(f, Ast_AsmInstruction); + instruction->AsmInstruction.name = name; + instruction->AsmInstruction.operands = operands; + return instruction; + } + case Token_Period: + { + Token token = expect_token(f, Token_Period); + Ast *name = parse_ident(f); + expect_token(f, Token_Colon); + Ast *label_decl = alloc_ast_node(f, Ast_AsmLabelDecl); + label_decl->AsmLabelDecl.token = token; + label_decl->AsmLabelDecl.name = name; + return label_decl; + } + } + syntax_error(f->curr_token, "Expected an asm instruction, got '%.*s'", LIT(f->curr_token.string)); + advance_token(f); + return nullptr; +} + + +gb_internal Ast *parse_asm_template(AstFile *f) { + Token token = expect_token(f, Token_asm); + + bool has_side_effects = false; + bool is_align_stack = false; + + while (f->curr_token.kind == Token_Hash) { + advance_token(f); + if (f->curr_token.kind == Token_Ident) { + Token token = advance_token(f); + String name = token.string; + if (name == "side_effects") { + if (has_side_effects) { + syntax_error(token, "Duplicate directive on inline asm expression: '#side_effects'"); + } + has_side_effects = true; + } else if (name == "align_stack") { + if (is_align_stack) { + syntax_error(token, "Duplicate directive on inline asm expression: '#align_stack'"); + } + is_align_stack = true; + } else { + syntax_error(token, "Invalid directive on inline asm expression: '#%.*s'", LIT(token.string)); + } + } else { + syntax_error(f->curr_token, "Expected an identifier after hash"); + } + } + + + Ast *signature = parse_proc_type(f, token); + + Slice asm_specs = {}; + Slice asm_clobbers = {}; + + if (f->curr_token.kind == Token_OpenBracket) { + Array specs = {}; + specs.allocator = heap_allocator(); + + Array clobbers = {}; + clobbers.allocator = heap_allocator(); + + Token open = expect_token(f, Token_OpenBracket); + while (f->curr_token.kind != Token_CloseBracket && + f->curr_token.kind != Token_EOF) { + Ast *spec = nullptr; + if (f->curr_token.kind == Token_Ident) { + Ast *name = parse_ident(f); + Ast *tied_name = nullptr; + Ast *type = nullptr; + Ast *value = nullptr; + if (allow_token(f, Token_ArrowRight)) { + tied_name = parse_ident(f); + } + if (allow_token(f, Token_Colon)) { + type = parse_type(f); + } + if (allow_token(f, Token_Eq)) { + value = parse_asm_register(f); + } + + if (type == nullptr && value == nullptr) { + syntax_error(f->curr_token, "An asm specification must specify at least either a type or a value"); + } + + spec = alloc_ast_node(f, Ast_AsmSpec); + spec->AsmSpec.name = name; + spec->AsmSpec.tied_name = tied_name; + spec->AsmSpec.type = type; + spec->AsmSpec.value = value; + } else if (f->curr_token.kind == Token_Hash) { + Token hash = expect_token(f, Token_Hash); + Token clobber_token = expect_token(f, Token_Ident); + if (clobber_token.string != "clobber") { + syntax_error(clobber_token, "Expected #clobber, got '%.*s'", LIT(clobber_token.string)); + } else { + Ast *value = parse_asm_operand(f, false); + Ast *clobber = alloc_ast_node(f, Ast_AsmClobber); + clobber->AsmClobber.token = hash; + clobber->AsmClobber.value = value; + array_add(&clobbers, clobber); + } + } else { + syntax_error(f->curr_token, "Expected am asm specification which begins with a identifier, got '%.*s'", LIT(f->curr_token.string)); + advance_token(f); + } + if (spec != nullptr) { + array_add(&specs, spec); + } + if (!allow_token(f, Token_Comma)) { + break; + } + } + Token close = expect_token(f, Token_CloseBracket); + + asm_specs = slice_from_array(specs); + asm_clobbers = slice_from_array(clobbers); + } + + Slice asm_instructions = {}; + + if (!allow_token(f, Token_OpenBrace)) { + syntax_error(f->curr_token, "Expected a body for an asm template"); + advance_token(f); + } else { + Array instructions = {}; + instructions.allocator = heap_allocator(); + + while (f->curr_token.kind != Token_CloseBrace && + f->curr_token.kind != Token_EOF) { + Ast *instruction = parse_asm_instruction(f); + if (instruction != nullptr) { + array_add(&instructions, instruction); + } + } + + Token close = expect_token(f, Token_CloseBrace); + + asm_instructions = slice_from_array(instructions); + } + + Ast *asm_template = alloc_ast_node(f, Ast_AsmTemplate); + asm_template->AsmTemplate.token = token; + asm_template->AsmTemplate.has_side_effects = has_side_effects; + asm_template->AsmTemplate.is_align_stack = is_align_stack; + asm_template->AsmTemplate.signature = signature; + asm_template->AsmTemplate.specs = asm_specs; + asm_template->AsmTemplate.clobbers = asm_clobbers; + asm_template->AsmTemplate.instructions = asm_instructions; + asm_template->AsmTemplate.end = f->prev_token; + return asm_template; +} + + gb_internal Ast *parse_operand(AstFile *f, bool lhs) { Ast *operand = nullptr; // Operand switch (f->curr_token.kind) { @@ -3105,83 +3396,8 @@ gb_internal Ast *parse_operand(AstFile *f, bool lhs) { return ast_bit_set_type(f, token, elem, underlying); } - case Token_asm: { - Token token = expect_token(f, Token_asm); - - Array param_types = {}; - Ast *return_type = nullptr; - if (allow_token(f, Token_OpenParen)) { - param_types = array_make(ast_allocator(f)); - while (f->curr_token.kind != Token_CloseParen && f->curr_token.kind != Token_EOF) { - Ast *t = parse_type(f); - array_add(¶m_types, t); - if (f->curr_token.kind != Token_Comma || - f->curr_token.kind == Token_EOF) { - break; - } - advance_token(f); - } - expect_token(f, Token_CloseParen); - - if (allow_token(f, Token_ArrowRight)) { - return_type = parse_type(f); - } - } - - bool has_side_effects = false; - bool is_align_stack = false; - InlineAsmDialectKind dialect = InlineAsmDialect_Default; - - while (f->curr_token.kind == Token_Hash) { - advance_token(f); - if (f->curr_token.kind == Token_Ident) { - Token token = advance_token(f); - String name = token.string; - if (name == "side_effects") { - if (has_side_effects) { - syntax_error(token, "Duplicate directive on inline asm expression: '#side_effects'"); - } - has_side_effects = true; - } else if (name == "align_stack") { - if (is_align_stack) { - syntax_error(token, "Duplicate directive on inline asm expression: '#align_stack'"); - } - is_align_stack = true; - } else if (name == "att") { - if (dialect == InlineAsmDialect_ATT) { - syntax_error(token, "Duplicate directive on inline asm expression: '#att'"); - } else if (dialect != InlineAsmDialect_Default) { - syntax_error(token, "Conflicting asm dialects"); - } else { - dialect = InlineAsmDialect_ATT; - } - } else if (name == "intel") { - if (dialect == InlineAsmDialect_Intel) { - syntax_error(token, "Duplicate directive on inline asm expression: '#intel'"); - } else if (dialect != InlineAsmDialect_Default) { - syntax_error(token, "Conflicting asm dialects"); - } else { - dialect = InlineAsmDialect_Intel; - } - } else { - syntax_error(token, "Invalid directive on inline asm expression: '#%.*s'", LIT(token.string)); - } - } else { - syntax_error(f->curr_token, "Expected an identifier after hash"); - } - } - - skip_possible_newline_for_literal(f); - Token open = expect_token(f, Token_OpenBrace); - Ast *asm_string = parse_expr(f, false); - expect_token(f, Token_Comma); - Ast *constraints_string = parse_expr(f, false); - allow_token(f, Token_Comma); - Token close = expect_closing_brace_of_field_list(f); - - return ast_inline_asm_expr(f, token, open, close, param_types, return_type, asm_string, constraints_string, has_side_effects, is_align_stack, dialect); - } - + case Token_asm: + return parse_asm_template(f); } return nullptr; diff --git a/src/parser.hpp b/src/parser.hpp index e423cb9b2..af8c3af09 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -468,6 +468,47 @@ struct AstSplitArgs { i64 max_count; \ Ast *tag; \ }) \ + AST_KIND(AsmTemplate, "asm template", struct { \ + Token token; \ + bool has_side_effects; \ + bool is_align_stack; \ + Ast * signature; \ + Slice specs; \ + Slice clobbers; \ + Slice instructions; \ + Token end; \ + }) \ + AST_KIND(AsmRegister, "asm register", struct { \ + Token token; \ + Token name; \ + }) \ + AST_KIND(AsmSpec, "asm specification", struct { \ + Ast *name; \ + Ast *tied_name; \ + Ast *type; \ + Ast *value; \ + bool is_temporary_decl; \ + }) \ + AST_KIND(AsmClobber, "asm clobber", struct { \ + Token token; \ + Ast * value; \ + }) \ + AST_KIND(AsmLabelDecl, "asm label declaration", struct { \ + Token token; \ + Ast * name; \ + }) \ + AST_KIND(AsmInstruction, "asm instruction", struct { \ + Token name; \ + Slice operands; \ + }) \ + AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ + Token open; \ + Ast * base; \ + Ast * index; \ + Ast * scale; \ + Ast * disp; \ + Token close; \ + }) \ AST_KIND(_ExprBegin, "", bool) \ AST_KIND(BadExpr, "bad expression", struct { Token begin, end; }) \ AST_KIND(TagExpr, "tag expression", struct { Token token, name; Ast *expr; }) \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 1d2b5090a..0fe27d2cc 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -13,6 +13,21 @@ gb_internal Token ast_token(Ast *node) { } return node->CompoundLit.open; + case Ast_AsmTemplate: + return node->AsmTemplate.token; + case Ast_AsmRegister: + return node->AsmRegister.token; + case Ast_AsmSpec: + return ast_token(node->AsmSpec.name); + case Ast_AsmClobber: + return node->AsmClobber.token; + case Ast_AsmLabelDecl: + return node->AsmLabelDecl.token; + case Ast_AsmInstruction: + return node->AsmInstruction.name; + case Ast_AsmMemoryOperand: + return node->AsmMemoryOperand.open; + case Ast_TagExpr: return node->TagExpr.token; case Ast_BadExpr: return node->BadExpr.begin; case Ast_UnaryExpr: return node->UnaryExpr.op; @@ -156,6 +171,33 @@ Token ast_end_token(Ast *node) { case Ast_CompoundLit: return node->CompoundLit.close; + case Ast_AsmTemplate: + return node->AsmTemplate.end; + case Ast_AsmRegister: + return node->AsmRegister.name; + case Ast_AsmSpec: + if (node->AsmSpec.value) { + return ast_end_token(node->AsmSpec.value); + } + if (node->AsmSpec.type) { + return ast_end_token(node->AsmSpec.type); + } + if (node->AsmSpec.tied_name) { + return ast_end_token(node->AsmSpec.tied_name); + } + return ast_end_token(node->AsmSpec.name); + case Ast_AsmClobber: + return ast_end_token(node->AsmClobber.value); + case Ast_AsmLabelDecl: + return ast_end_token(node->AsmLabelDecl.name); + case Ast_AsmInstruction: + if (node->AsmInstruction.operands.count > 0) { + return ast_end_token(node->AsmInstruction.operands[node->AsmInstruction.operands.count-1]); + } + return node->AsmInstruction.name; + case Ast_AsmMemoryOperand: + return node->AsmMemoryOperand.close; + case Ast_BadExpr: return node->BadExpr.end; case Ast_TagExpr: if (node->TagExpr.expr) { From 5ac28cdecdbf38824cc6179add56f2c09234aa32 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 18:24:56 +0100 Subject: [PATCH 02/92] Begin work on semantically type checking `asm` templates --- src/check_decl.cpp | 513 +++++++++++++++++++++++++++++++++++++++++++- src/check_expr.cpp | 137 ++++++++++++ src/checker.cpp | 14 ++ src/entity.cpp | 48 ++++- src/exact_value.cpp | 29 +-- src/parser.cpp | 42 +++- src/parser.hpp | 11 +- src/parser_pos.cpp | 4 +- 8 files changed, 769 insertions(+), 29 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index edb9f4883..f1ab06a52 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -1983,10 +1983,515 @@ gb_internal void check_proc_group_decl(CheckerContext *ctx, Entity *pg_entity, D AttributeContext ac = {}; check_decl_attributes(ctx, d->attributes, proc_group_attribute, &ac); check_objc_methods(ctx, pg_entity, ac); - - } +gb_internal bool is_valid_asm_parameter_type(Type *type) { + if (is_type_integer(type)) { + return true; + } + if (is_type_float(type)) { + return true; + } + if (is_type_boolean(type)) { + return true; + } + if (is_type_pointer(type) || is_type_multi_pointer(type)) { + return true; + } + if (is_type_simd_vector(type)) { + return true; + } + return false; +} + +gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { + Type *tuple = alloc_type_tuple(); + if (_params == nullptr) { + return tuple; + } + ast_node(field_list, FieldList, _params); + Slice params = field_list->list; + + Array variables = {}; + variables.allocator = heap_allocator(); + + for (Ast *param : params) { + ast_node(field, Field, param); + + bool prev = ctx->allow_polymorphic_types; + ctx->allow_polymorphic_types = false; + Type *type = check_type(ctx, field->type); + ctx->allow_polymorphic_types = prev; + + if (!is_valid_asm_parameter_type(type)) { + gbString s = type_to_string(type); + error(field->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + gb_string_free(s); + continue; + } + + for_array(j, field->names) { + Ast *name = field->names[j]; + + bool is_poly_name = false; + + switch (name->kind) { + case Ast_Ident: + break; + case Ast_PolyType: + GB_ASSERT(name->PolyType.specialization == nullptr); + is_poly_name = true; + name = name->PolyType.type; + break; + } + + if (!ast_node_expect(name, Ast_Ident)) { + continue; + } + + if (is_blank_ident(name)) { + error(name, "All parameters must have a name in an asm template"); + continue; + } + Token name_token = name->Ident.token; + + Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); + entity->flags |= EntityFlag_Used; + if (is_poly_name) { + entity->flags |= EntityFlag_PolyConst; + if (is_type_internally_pointer_like(type)) { + error(name, "Parameters with a pointer-like type cannot be used as $ immediates"); + } + } + + Entity *found = scope_insert(scope, entity); + if (found == nullptr) { + array_add(&variables, entity); + + AsmTemplateEntityDecl ed = {}; + ed.entity = entity; + ed.kind = AsmTemplateEntityDecl_Register; + if (is_type_internally_pointer_like(type)) { + ed.kind = AsmTemplateEntityDecl_Memory; + } + if (is_poly_name) { + ed.kind = AsmTemplateEntityDecl_Immediate; + } + if (input_parameters) { + ed.param_group = AsmTemplateEntityDeclParamGroup_Input; + } else { + ed.param_group = AsmTemplateEntityDeclParamGroup_Output; + } + + array_add(asm_template_entity_decls, ed); + } else { + TokenPos pos = found->token.pos; + error(name_token, + "Redeclaration of '%.*s' in this scope\n" + "\tat %s", + LIT(name_token.string), token_pos_to_string(pos)); + entity = found; + } + } + } + + tuple->Tuple.variables = slice_from_array(variables); + + return tuple; +} + +gb_internal AsmTemplateEntityDeclParamGroup check_asm_find_group(Entity *entity, Array const &asm_template_entity_decls) { + for (auto const &ed : asm_template_entity_decls) { + if (ed.entity == entity) { + return ed.param_group; + } + } + return AsmTemplateEntityDeclParamGroup_Unknown; +}; + +gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array const &asm_template_entity_decls) { + for (auto const &ed : asm_template_entity_decls) { + if (ed.entity == entity) { + return ed.kind; + } + } + return AsmTemplateEntityDecl_Invalid; +}; + + +gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { + + for (Ast *spec_ : specs) { + if (spec_->kind != Ast_AsmSpec) { + continue; + } + ast_node(spec, AsmSpec, spec_); + + GB_ASSERT(spec->name->kind == Ast_Ident); + + Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); + + bool must_check_value = false; + + if (spec->tied_name == nullptr) { + if (spec->type != nullptr) { + Type *type = check_type(ctx, spec->type); + if (!is_valid_asm_parameter_type(type)) { + gbString s = type_to_string(type); + error(spec->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + gb_string_free(s); + continue; + } + + Token name_token = spec->name->Ident.token; + + Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); + entity->flags |= EntityFlag_Used; + + Entity *found = scope_insert(scope, entity); + if (found == nullptr) { + AsmTemplateEntityDecl ed = {}; + ed.entity = entity; + ed.kind = AsmTemplateEntityDecl_Register; + if (is_type_internally_pointer_like(type)) { + ed.kind = AsmTemplateEntityDecl_Memory; + } + ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; + + array_add(asm_template_entity_decls, ed); + } else { + TokenPos pos = found->token.pos; + error(name_token, + "Redeclaration of '%.*s' in this scope\n" + "\tat %s", + LIT(name_token.string), token_pos_to_string(pos)); + entity = found; + continue; + } + } else if (input == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } + + } else { + GB_ASSERT(spec->tied_name->kind == Ast_Ident); + + if (spec->type != nullptr) { + error(spec->type, "Tied register definitions cannot have a defined type since the values are already defined"); + } + + if (input == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } + Entity *output = scope_lookup(scope, spec->tied_name->Ident.interned, spec->tied_name->Ident.hash); + if (output == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } + + auto input_group = check_asm_find_group(input, *asm_template_entity_decls); + auto output_group = check_asm_find_group(output, *asm_template_entity_decls); + if (input_group != AsmTemplateEntityDeclParamGroup_Input) { + error(input->token, "Parameter tied with '%.*s' must be an input parameter", LIT(output->token.string)); + continue; + } + if (output_group != AsmTemplateEntityDeclParamGroup_Output) { + error(output->token, "Parameter tied with '%.*s' must be an output parameter", LIT(input->token.string)); + continue; + } + + must_check_value = true; + } + + if (spec->value != nullptr) { + // TODO(bill): check registers + } + + } +} + +gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { + if (expr == nullptr) { + return; + } + + operand->expr = expr; + operand->mode = Addressing_Invalid; + operand->type = t_invalid; + + GB_ASSERT(entity->kind == Entity_AsmTemplate); + auto *ate = &entity->AsmTemplate; + + Scope *param_scope = ate->param_scope; + Scope *label_scope = ate->label_scope; + gb_unused(param_scope); + gb_unused(label_scope); + + switch (expr->kind) { + case_ast_node(i, Ident, expr); + Entity *found = scope_lookup(param_scope, i->interned, i->hash); + if (found == nullptr) { + error(expr, "Undeclared asm parameter '%.*s'", LIT(i->token.string)); + return; + } + i->entity = found; + operand->mode = Addressing_Value; + operand->type = found->type; + return; + case_end; + case_ast_node(bl, BasicLit, expr); + check_expr(ctx, operand, expr); + return; + case_end; + case_ast_node(i, AsmRegister, expr); + // TODO(bill): Check asm register + return; + case_end; + case_ast_node(mem_op, AsmMemoryOperand, expr); + if (!allow_memory_operands) { + break; + } + Operand base = {}; + Operand index = {}; + Operand scale = {}; + Operand disp = {}; + check_asm_instruction_operand(ctx, entity, &base, mem_op->base, false); + check_asm_instruction_operand(ctx, entity, &index, mem_op->index, false); + check_asm_instruction_operand(ctx, entity, &scale, mem_op->scale, false); + check_asm_instruction_operand(ctx, entity, &disp, mem_op->disp, false); + + for (int i = 0; base.expr && i == 0; i++) { + if (base.expr->kind == Ast_AsmRegister) { + // Okay for now + } else { + Entity *param_entity = entity_of_node(base.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(base.expr); + error(base.expr, "A base value must a memory parameter, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + if (kind != AsmTemplateEntityDecl_Memory) { + gbString s = expr_to_string(base.expr); + error(base.expr, "A scale must be a memory parameter, got %s", s); + gb_string_free(s); + break; + } + } + } + + for (int i = 0; index.expr && i == 0; i++) { + if (index.expr->kind == Ast_AsmRegister) { + // Okay for now + } else { + Entity *param_entity = entity_of_node(index.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(index.expr); + error(index.expr, "An index value must an integer, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + // okay: + break; + default: + { + gbString s = expr_to_string(index.expr); + error(index.expr, "An index must be an integer value, got %s", s); + gb_string_free(s); + } + break; + } + } + } + + for (int i = 0; scale.expr && i == 0; i++) { + if (!is_type_integer(scale.type)) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + if (scale.mode == Addressing_Constant) { + if (scale.value.kind != ExactValue_Integer) { + gbString s = exact_value_to_string(scale.value); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + } else { + Entity *param_entity = entity_of_node(scale.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + if (kind != AsmTemplateEntityDecl_Immediate) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + } + } + + for (int i = 0; disp.expr && i == 0; i++) { + if (disp.expr->kind == Ast_AsmRegister) { + // Okay for now + } else { + Entity *param_entity = entity_of_node(disp.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(disp.expr); + error(disp.expr, "An displacement value must an integer, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + // okay: + break; + default: + { + gbString s = expr_to_string(disp.expr); + error(disp.expr, "An displacement must be an integer value, got %s", s); + gb_string_free(s); + } + break; + } + } + } + + return; + case_end; + case_ast_node(label, AsmLabelDecl, expr); + ast_node(name, Ident, label->name); + Entity *found = scope_lookup(label_scope, name->interned, name->hash); + if (found == nullptr) { + error(expr, "Undeclared asm label '.%.*s'", LIT(name->token.string)); + } + name->entity = found; + return; + case_end; + } + + { + gbString s = expr_to_string(expr); + error(expr, "Invalid asm operand, got %s", s); + gb_string_free(s); + } + return; +} + + +gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInfo *d) { + GB_ASSERT(entity->kind == Entity_AsmTemplate); + auto *ate = &entity->AsmTemplate; + + String asm_template_name = entity->token.string; + gb_unused(asm_template_name); + + ast_node(at, AsmTemplate, d->init_expr); + + GB_ASSERT(at->signature != nullptr); + if (at->signature->kind != Ast_ProcType) { + error(at->signature, "Expected a valid signature, got %.*s", LIT(ast_strings[at->signature->kind])); + return; + } + AstProcType *pt = &at->signature->ProcType; + + ate->param_scope = create_scope(nullptr, nullptr); + ate->label_scope = create_scope(nullptr, nullptr); + + ate->decls.allocator = heap_allocator(); + + Type *params = check_asm_template_signature_params(ctx, ate->param_scope, pt->params, true, &ate->decls); + Type *results = check_asm_template_signature_params(ctx, ate->param_scope, pt->results, false, &ate->decls); + + Type *type = alloc_type_proc(ate->param_scope, params, params->Tuple.variables.count, results, results->Tuple.variables.count, false, pt->calling_convention); + type->Proc.diverging = pt->diverging; + + check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); + { // check clobbers + for (Ast *clobber_ : at->clobbers) { + ast_node(clobber, AsmClobber, clobber_); + switch (clobber->value->kind) { + case Ast_AsmRegister: + // TODO(bill): register check + break; + case Ast_Ident: + { + String str = clobber->value->Ident.token.string; + if (str == "cc") { + // okay + } else if (str == "memory") { + // okay + } else { + error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); + } + break; + } + default: + error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification"); + break; + } + } + } + + // collect label decls + for (Ast *instruction_ : at->instructions) { + switch (instruction_->kind) { + case_ast_node(label, AsmLabelDecl, instruction_); + GB_ASSERT(label->name->kind == Ast_Ident); + Ast *name = label->name; + if (is_blank_ident(name)) { + error(name, "Asm label definition cannot be '_'"); + continue; + } + Entity *label_entity = alloc_entity_label(ate->label_scope, name->Ident.token, nullptr, instruction_, nullptr); + Entity *found = scope_insert(ate->label_scope, label_entity); + if (found != nullptr) { + TokenPos pos = found->token.pos; + error(name, + "Redeclaration of the label '%.*s' in this scope\n" + "\tat %s", + LIT(name->Ident.token.string), token_pos_to_string(pos)); + continue; + } + name->Ident.entity = label_entity; + case_end; + } + } + + + for (Ast *instruction_ : at->instructions) { + switch (instruction_->kind) { + case_ast_node(instr, AsmInstruction, instruction_); + GB_ASSERT(instr->name->kind == Ast_Ident); + for (Ast *expr : instr->operands) { + Operand operand = {}; + check_asm_instruction_operand(ctx, entity, &operand, expr, /*allow_memory_operands*/true); + } + case_end; + case_ast_node(label, AsmLabelDecl, instruction_); + // already done + case_end; + default: + error(instruction_, "Unexpected instruction in asm template"); + break; + } + } +} + + gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, Type *named_type) { if (e->state == EntityState_Resolved) { return; @@ -2062,6 +2567,10 @@ gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, case Entity_ProcGroup: check_proc_group_decl(&c, e, d); break; + + case Entity_AsmTemplate: + check_asm_template(&c, e, d); + break; } e->state = EntityState_Resolved; diff --git a/src/check_expr.cpp b/src/check_expr.cpp index e73ec65c4..566a0ff28 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -361,6 +361,7 @@ gb_internal void check_scope_decls(CheckerContext *c, Slice const &nodes, case Entity_Constant: case Entity_TypeName: case Entity_Procedure: + case Entity_AsmTemplate: break; default: continue; @@ -2067,6 +2068,10 @@ gb_internal Entity *check_ident(CheckerContext *c, Operand *o, Ast *n, Type *nam o->mode = Addressing_Value; break; + case Entity_AsmTemplate: + o->mode = Addressing_Value; + break; + default: compiler_error("Unknown EntityKind %.*s", LIT(entity_strings[e->kind])); break; @@ -12340,6 +12345,11 @@ gb_internal ExprKind check_expr_base_internal(CheckerContext *c, Operand *o, Ast return kind; case_end; + case_ast_node(asm_template, AsmTemplate, node); + error(node, "Illegal use of an asm template outside of a named constant value declaration"); + o->mode = Addressing_Invalid; + case_end; + case_ast_node(i, Implicit, node); switch (i->kind) { case Token_context: @@ -13585,6 +13595,133 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan } str = gb_string_appendc(str, "}"); case_end; + + case_ast_node(at, AsmTemplate, node); + str = gb_string_appendc(str, "asm"); + { + ast_node(pt, ProcType, at->signature); + + str = gb_string_appendc(str, "("); + str = write_expr_to_string(str, pt->params, shorthand); + str = gb_string_appendc(str, ")"); + if (pt->results != nullptr) { + str = gb_string_appendc(str, " -> "); + + bool parens_needed = false; + if (pt->results && pt->results->kind == Ast_FieldList) { + for (Ast *field : pt->results->FieldList.list) { + ast_node(f, Field, field); + if (f->names.count != 0) { + parens_needed = true; + break; + } + } + } + + if (parens_needed) { + str = gb_string_append_rune(str, '('); + } + str = write_expr_to_string(str, pt->results, shorthand); + if (parens_needed) { + str = gb_string_append_rune(str, ')'); + } + } + } + + if (at->has_side_effects) { + str = gb_string_appendc(str, " #side_effects"); + } + if (at->is_align_stack) { + str = gb_string_appendc(str, " #align_stack"); + } + if (at->specs.count) { + str = gb_string_append_rune(str, '['); + for_array(j, at->specs) { + if (j > 0) { + str = gb_string_appendc(str, ", "); + } + Ast *spec = at->specs[j]; + str = write_expr_to_string(str, spec, shorthand); + } + str = gb_string_append_rune(str, ']'); + } + str = gb_string_append_rune(str, '{'); + for_array(j, at->instructions) { + if (j > 0) { + str = gb_string_appendc(str, "; "); + } + Ast *instr = at->instructions[j]; + str = write_expr_to_string(str, instr, shorthand); + if (instr->kind == Ast_AsmLabelDecl) { + str = gb_string_appendc(str, ":"); + } + } + str = gb_string_append_rune(str, '}'); + case_end; + + case_ast_node(ar, AsmRegister, node); + str = gb_string_appendc(str, "%"); + str = gb_string_append_length(str, ar->name.string.text, ar->name.string.len); + case_end; + + case_ast_node(spec, AsmSpec, node); + if (spec->name) { + str = write_expr_to_string(str, spec->name, shorthand); + if (spec->tied_name) { + str = gb_string_appendc(str, " -> "); + str = write_expr_to_string(str, spec->tied_name, shorthand); + } + } + if (spec->type) { + str = gb_string_appendc(str, ": "); + str = write_expr_to_string(str, spec->type, shorthand); + } + if (spec->value) { + str = gb_string_appendc(str, " = "); + str = write_expr_to_string(str, spec->value, shorthand); + } + case_end; + + case_ast_node(clobber, AsmClobber, node); + str = gb_string_appendc(str, "#clobber "); + str = write_expr_to_string(str, clobber->value, shorthand); + case_end; + + case_ast_node(label, AsmLabelDecl, node); + str = gb_string_appendc(str, "."); + str = write_expr_to_string(str, label->name, shorthand); + case_end; + + case_ast_node(instr, AsmInstruction, node); + str = write_expr_to_string(str, instr->name, shorthand); + for_array(j, instr->operands) { + if (j == 0) { + str = gb_string_appendc(str, " "); + } else { + str = gb_string_appendc(str, ", "); + } + Ast *operand = instr->operands[j]; + str = write_expr_to_string(str, operand, shorthand); + } + case_end; + + case_ast_node(op, AsmMemoryOperand, node); + str = gb_string_appendc(str, "["); + str = write_expr_to_string(str, op->base, shorthand); + if (op->index) { + str = gb_string_appendc(str, " + "); + str = write_expr_to_string(str, op->index, shorthand); + if (op->scale) { + str = gb_string_appendc(str, "*"); + str = write_expr_to_string(str, op->scale, shorthand); + } + } + if (op->disp) { + str = gb_string_appendc(str, " + "); + str = write_expr_to_string(str, op->disp, shorthand); + } + str = gb_string_appendc(str, "]"); + case_end; } return str; diff --git a/src/checker.cpp b/src/checker.cpp index 23ac59a3e..0d8c6a841 100644 --- a/src/checker.cpp +++ b/src/checker.cpp @@ -1834,6 +1834,9 @@ retry:; expr = we->cond->tav.value.value_bool ? we->x : we->y; goto retry; case_end; + case_ast_node(label, AsmLabelDecl, expr); + return entity_of_node(label->name); + case_end; } return nullptr; } @@ -5060,6 +5063,17 @@ gb_internal void check_collect_value_decl(CheckerContext *c, Ast *decl) { if (fl != nullptr) { error(name, "Procedure groups are not allowed within a foreign block"); } + } else if (init->kind == Ast_AsmTemplate) { + if (c->scope->flags&ScopeFlag_Type) { + error(name, "Asm templates are not allowed within a struct"); + continue; + } + ast_node(at, AsmTemplate, init); + e = alloc_entity_asm_template(d->scope, token, nullptr, init); + if (fl != nullptr) { + error(name, "Asm templates are not allowed within a foreign block"); + } + d->init_expr = init; } else { e = alloc_entity_constant(d->scope, token, nullptr, empty_exact_value); } diff --git a/src/entity.cpp b/src/entity.cpp index d3170c823..c439404b6 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -15,7 +15,8 @@ struct DeclInfo; ENTITY_KIND(ImportName) \ ENTITY_KIND(LibraryName) \ ENTITY_KIND(Nil) \ - ENTITY_KIND(Label) + ENTITY_KIND(Label) \ + ENTITY_KIND(AsmTemplate) enum EntityKind { #define ENTITY_KIND(k) GB_JOIN2(Entity_, k), @@ -159,6 +160,32 @@ gb_internal TypeNameObjCMetadata *create_type_name_obj_c_metadata() { return md; } +enum AsmTemplateEntityDeclKind : u8 { + AsmTemplateEntityDecl_Invalid, + AsmTemplateEntityDecl_Register, + AsmTemplateEntityDecl_Memory, + AsmTemplateEntityDecl_Immediate, + + AsmTemplateEntityDecl_COUNT +}; + +enum AsmTemplateEntityDeclParamGroup : u8 { + AsmTemplateEntityDeclParamGroup_Unknown, + AsmTemplateEntityDeclParamGroup_Input, + AsmTemplateEntityDeclParamGroup_Output, + AsmTemplateEntityDeclParamGroup_Scratch, + + AsmTemplateEntityDeclParamGroup_COUNT +}; + +struct AsmTemplateEntityDecl { + Entity * entity; + Entity * tied_entity; + AsmTemplateEntityDeclKind kind; + AsmTemplateEntityDeclParamGroup param_group; + u16 register_map; +}; + // An Entity is a named "thing" in the language struct Entity { EntityKind kind; @@ -300,6 +327,15 @@ struct Entity { Ast *node; Ast *parent; } Label; + struct { + Ast *node; + bool has_side_effects; + bool is_align_stack; + Scope *param_scope; + Scope *label_scope; + + Array decls; + } AsmTemplate; }; }; @@ -477,8 +513,14 @@ gb_internal Entity *alloc_entity_library_name(Scope *scope, Token token, Type *t } - - +gb_internal Entity *alloc_entity_asm_template(Scope *scope, Token token, Type *type, Ast *node) { + GB_ASSERT(node->kind == Ast_AsmTemplate); + Entity *entity = alloc_entity(Entity_AsmTemplate, scope, token, type); + entity->AsmTemplate.node = node; + entity->AsmTemplate.has_side_effects = node->AsmTemplate.has_side_effects; + entity->AsmTemplate.is_align_stack = node->AsmTemplate.is_align_stack; + return entity; +} gb_internal Entity *alloc_entity_nil(String name, Type *type) { Entity *entity = alloc_entity(Entity_Nil, nullptr, make_token_ident(name), type); diff --git a/src/exact_value.cpp b/src/exact_value.cpp index 2f82a52cf..2895f7e59 100644 --- a/src/exact_value.cpp +++ b/src/exact_value.cpp @@ -15,19 +15,20 @@ struct Quaternion256 { }; enum ExactValueKind { - ExactValue_Invalid = 0, + ExactValue_Invalid = 0, - ExactValue_Bool = 1, - ExactValue_String = 2, - ExactValue_Integer = 3, - ExactValue_Float = 4, - ExactValue_Complex = 5, - ExactValue_Quaternion = 6, - ExactValue_Pointer = 7, - ExactValue_Compound = 8, - ExactValue_Procedure = 9, - ExactValue_Typeid = 10, - ExactValue_String16 = 11, + ExactValue_Bool = 1, + ExactValue_String = 2, + ExactValue_Integer = 3, + ExactValue_Float = 4, + ExactValue_Complex = 5, + ExactValue_Quaternion = 6, + ExactValue_Pointer = 7, + ExactValue_Compound = 8, + ExactValue_Procedure = 9, + ExactValue_Typeid = 10, + ExactValue_String16 = 11, + ExactValue_AsmTemplate = 12, ExactValue_Count, }; @@ -62,6 +63,7 @@ struct ExactValue { Ast * value_procedure; Type * value_typeid; String16 value_string16; + Ast * value_asm_template; }; }; @@ -107,6 +109,9 @@ gb_internal uintptr hash_exact_value(ExactValue v) { case ExactValue_Procedure: res = ptr_map_hash_key(v.value_procedure); break; + case ExactValue_AsmTemplate: + res = ptr_map_hash_key(v.value_asm_template); + break; case ExactValue_Typeid: res = ptr_map_hash_key(v.value_typeid); break; diff --git a/src/parser.cpp b/src/parser.cpp index 0e2f77a93..39d87669d 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -542,6 +542,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmLabelDecl.name = clone_ast(n->AsmLabelDecl.name, f); break; case Ast_AsmInstruction: + n->AsmInstruction.name = clone_ast(n->AsmInstruction.name, f); n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); break; case Ast_AsmMemoryOperand: @@ -2512,7 +2513,7 @@ gb_internal Ast *parse_asm_instruction(AstFile *f) { /*fallthrough*/ case Token_Ident: { - Token name = advance_token(f); + Ast *name = parse_ident(f); auto operands = parse_asm_operands(f); Ast *instruction = alloc_ast_node(f, Ast_AsmInstruction); instruction->AsmInstruction.name = name; @@ -2535,6 +2536,33 @@ gb_internal Ast *parse_asm_instruction(AstFile *f) { return nullptr; } +gb_internal Ast *parse_results(AstFile *f, bool *diverging); +gb_internal bool is_field_list_generic(AstFieldList *field_list, bool check_names); +gb_internal Ast *parse_asm_signature(AstFile *f, Token asm_token) { + Ast *params = nullptr; + Ast *results = nullptr; + bool diverging = false; + + ProcCallingConvention cc = ProcCC_InlineAsm; + + expect_token(f, Token_OpenParen); + f->expr_level += 1; + params = parse_field_list(f, nullptr, FieldFlag_Signature, Token_CloseParen, false, false); + if (file_allow_newline(f)) { + skip_possible_newline(f); + } + f->expr_level -= 1; + expect_token_after(f, Token_CloseParen, "asm template parameter list"); + results = parse_results(f, &diverging); + + u64 tags = 0; + bool is_generic = is_field_list_generic(¶ms->FieldList, true); + if (!is_generic && (results != nullptr)) { + is_generic = is_field_list_generic(&results->FieldList, false); + } + + return ast_proc_type(f, asm_token, params, results, tags, cc, is_generic, diverging); +} gb_internal Ast *parse_asm_template(AstFile *f) { Token token = expect_token(f, Token_asm); @@ -2542,6 +2570,8 @@ gb_internal Ast *parse_asm_template(AstFile *f) { bool has_side_effects = false; bool is_align_stack = false; + Ast *signature = parse_asm_signature(f, token); + while (f->curr_token.kind == Token_Hash) { advance_token(f); if (f->curr_token.kind == Token_Ident) { @@ -2565,12 +2595,13 @@ gb_internal Ast *parse_asm_template(AstFile *f) { } } - - Ast *signature = parse_proc_type(f, token); - Slice asm_specs = {}; Slice asm_clobbers = {}; + if (file_allow_newline(f)) { + skip_possible_newline(f); + } + if (f->curr_token.kind == Token_OpenBracket) { Array specs = {}; specs.allocator = heap_allocator(); @@ -2630,6 +2661,9 @@ gb_internal Ast *parse_asm_template(AstFile *f) { } } Token close = expect_token(f, Token_CloseBracket); + if (file_allow_newline(f)) { + skip_possible_newline(f); + } asm_specs = slice_from_array(specs); asm_clobbers = slice_from_array(clobbers); diff --git a/src/parser.hpp b/src/parser.hpp index af8c3af09..0390937c0 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -483,11 +483,10 @@ struct AstSplitArgs { Token name; \ }) \ AST_KIND(AsmSpec, "asm specification", struct { \ - Ast *name; \ - Ast *tied_name; \ - Ast *type; \ - Ast *value; \ - bool is_temporary_decl; \ + Ast *name; \ + Ast *tied_name; \ + Ast *type; \ + Ast *value; \ }) \ AST_KIND(AsmClobber, "asm clobber", struct { \ Token token; \ @@ -498,7 +497,7 @@ struct AstSplitArgs { Ast * name; \ }) \ AST_KIND(AsmInstruction, "asm instruction", struct { \ - Token name; \ + Ast * name; \ Slice operands; \ }) \ AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 0fe27d2cc..3313d831d 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -24,7 +24,7 @@ gb_internal Token ast_token(Ast *node) { case Ast_AsmLabelDecl: return node->AsmLabelDecl.token; case Ast_AsmInstruction: - return node->AsmInstruction.name; + return ast_token(node->AsmInstruction.name); case Ast_AsmMemoryOperand: return node->AsmMemoryOperand.open; @@ -194,7 +194,7 @@ Token ast_end_token(Ast *node) { if (node->AsmInstruction.operands.count > 0) { return ast_end_token(node->AsmInstruction.operands[node->AsmInstruction.operands.count-1]); } - return node->AsmInstruction.name; + return ast_end_token(node->AsmInstruction.name); case Ast_AsmMemoryOperand: return node->AsmMemoryOperand.close; From 25ce7e87de16402ca672f4109152cb46c750257e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 18:52:57 +0100 Subject: [PATCH 03/92] Correctly type check `asm` template parameters --- src/check_decl.cpp | 2 ++ src/check_expr.cpp | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index f1ab06a52..ea35e96c5 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2419,6 +2419,8 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf Type *type = alloc_type_proc(ate->param_scope, params, params->Tuple.variables.count, results, results->Tuple.variables.count, false, pt->calling_convention); type->Proc.diverging = pt->diverging; + entity->type = type; + check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); { // check clobbers for (Ast *clobber_ : at->clobbers) { diff --git a/src/check_expr.cpp b/src/check_expr.cpp index 566a0ff28..cf6c45d05 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -5933,7 +5933,8 @@ gb_internal Entity *check_selector(CheckerContext *c, Operand *operand, Ast *nod add_entity_use(c, op_expr, e); expr_entity = e; - if (e != nullptr && (e->kind == Entity_Procedure || e->kind == Entity_ProcGroup) && selector->kind == Ast_Ident) { + if (e != nullptr && (e->kind == Entity_Procedure || e->kind == Entity_ProcGroup || e->kind == Entity_AsmTemplate) && + selector->kind == Ast_Ident) { gbString sel_str = expr_to_string(selector); error(node, "'%s' is not declared by '%.*s'", sel_str, LIT(e->token.string)); gb_string_free(sel_str); @@ -6304,6 +6305,10 @@ gb_internal Entity *check_selector(CheckerContext *c, Operand *operand, Ast *nod case Entity_Nil: operand->mode = Addressing_Value; break; + + case Entity_AsmTemplate: + operand->mode = Addressing_Value; + break; } add_type_and_value(c, operand->expr, operand->mode, operand->type, operand->value); From 036e38442bd7b5fa18063e06e79f1076dbc31516 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 21:55:36 +0100 Subject: [PATCH 04/92] Begin work on `lb_emit_asm_template_call` --- src/llvm_backend.cpp | 1 + src/llvm_backend.hpp | 2 ++ src/llvm_backend_asm.cpp | 43 +++++++++++++++++++++++++++++++++++++++ src/llvm_backend_proc.cpp | 24 ++++++++++++++++++---- src/parser.cpp | 2 +- 5 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 src/llvm_backend_asm.cpp diff --git a/src/llvm_backend.cpp b/src/llvm_backend.cpp index 8b1474fb6..0021d5b76 100644 --- a/src/llvm_backend.cpp +++ b/src/llvm_backend.cpp @@ -29,6 +29,7 @@ #include "llvm_backend_expr.cpp" #include "llvm_backend_stmt.cpp" #include "llvm_backend_proc.cpp" +#include "llvm_backend_asm.cpp" gb_internal String get_default_microarchitecture() { String default_march = str_lit("generic"); diff --git a/src/llvm_backend.hpp b/src/llvm_backend.hpp index a38f67d86..563f854d7 100644 --- a/src/llvm_backend.hpp +++ b/src/llvm_backend.hpp @@ -467,6 +467,8 @@ gb_internal lbValue lb_emit_call(lbProcedure *p, lbValue value, Array c gb_internal lbValue lb_emit_conv(lbProcedure *p, lbValue value, Type *t); gb_internal lbValue lb_emit_comp_against_nil(lbProcedure *p, TokenKind op_kind, lbValue x); +gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args); + gb_internal void lb_emit_jump(lbProcedure *p, lbBlock *target_block); gb_internal void lb_emit_if(lbProcedure *p, lbValue cond, lbBlock *true_block, lbBlock *false_block); gb_internal void lb_start_block(lbProcedure *p, lbBlock *b); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp new file mode 100644 index 000000000..ad8e54a0e --- /dev/null +++ b/src/llvm_backend_asm.cpp @@ -0,0 +1,43 @@ +gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args) { + GB_ASSERT(entity->kind == Entity_AsmTemplate); + + // GB_PANIC("TODO(bill): lb_emit_asm_template_call"); + gbString asm_string = gb_string_make(heap_allocator(), ""); + gbString constraints = gb_string_make(heap_allocator(), ""); + + auto *ate = &entity->AsmTemplate; + GB_ASSERT(ate->node->kind == Ast_AsmTemplate); + auto *node = &ate->node->AsmTemplate; + + for_array(i, node->instructions) { + auto *instruction = node->instructions[i]; + gb_unused(instruction); + } + // asm_string = gb_string_appendc(asm_string, "lock cmpxchg16b $3"); + // asm_string = gb_string_appendc(asm_string, "\\0A\\09"); + // asm_string = gb_string_appendc(asm_string, "setz $2"); + + // constraints = gb_string_appendc(constraints, "*m,={ax},={dx},=r,{ax},{dx},{bx},{cx},~{cc},~{memory}"); + + Type *proc_type = base_type(entity->type); + GB_ASSERT(proc_type->kind == Type_Proc); + + LLVMTypeRef llvm_type = lb_type_internal_for_procedures_raw(p->module, proc_type); + gb_printf_err("%s\n", LLVMPrintTypeToString(llvm_type)); + + LLVMValueRef fn = LLVMGetInlineAsm(llvm_type, asm_string, gb_string_length(asm_string), + constraints, gb_string_length(constraints), + entity->AsmTemplate.has_side_effects, + entity->AsmTemplate.is_align_stack, + LLVMInlineAsmDialectATT, /*CanThrow*/false); + + LLVMValueRef *llvm_args = gb_alloc_array(heap_allocator(), LLVMValueRef, args.count); + for_array(i, args) { + llvm_args[i] = args[i].value; + } + LLVMValueRef result = LLVMBuildCall2(p->builder, llvm_type, fn, llvm_args, cast(unsigned)args.count, ""); + Type *result_type = reduce_tuple_to_single_type(proc_type->Proc.results); + + gb_printf_err("%s\n", LLVMPrintValueToString(result)); + return {result, result_type}; +} \ No newline at end of file diff --git a/src/llvm_backend_proc.cpp b/src/llvm_backend_proc.cpp index b528980ec..607dafde2 100644 --- a/src/llvm_backend_proc.cpp +++ b/src/llvm_backend_proc.cpp @@ -5023,6 +5023,7 @@ gb_internal lbValue lb_build_call_expr_internal(lbProcedure *p, Ast *expr, lbVal // NOTE(bill): Regular call lbValue value = {}; + Entity *asm_template = nullptr; if (proc_entity != nullptr) { if (proc_entity->flags & EntityFlag_Disabled) { @@ -5056,15 +5057,25 @@ gb_internal lbValue lb_build_call_expr_internal(lbProcedure *p, Ast *expr, lbVal } } } + Type *proc_value_type = nullptr; if (is_objc_call) { value.type = proc_tv.type; + proc_value_type = value.type; } else if (value.value == nullptr) { - value = lb_build_expr(p, proc_expr); + Entity *found = entity_of_node(proc_expr); + if (found && found->kind == Entity_AsmTemplate) { + asm_template = found; + proc_value_type = asm_template->type; + } else { + value = lb_build_expr(p, proc_expr); + proc_value_type = value.type; + } } - GB_ASSERT(value.value != nullptr || is_objc_call); - Type *proc_type_ = base_type(value.type); + + GB_ASSERT(value.value != nullptr || is_objc_call || asm_template != nullptr); + Type *proc_type_ = base_type(proc_value_type); GB_ASSERT(proc_type_->kind == Type_Proc); TypeProc *pt = &proc_type_->Proc; @@ -5283,6 +5294,11 @@ gb_internal lbValue lb_build_call_expr_internal(lbProcedure *p, Ast *expr, lbVal } } - return lb_emit_call(p, value, call_args, inlining, tailing, sret_dst); + if (asm_template != nullptr) { + GB_ASSERT(value.value == nullptr); + return lb_emit_asm_template_call(p, asm_template, call_args); + } else { + return lb_emit_call(p, value, call_args, inlining, tailing, sret_dst); + } } diff --git a/src/parser.cpp b/src/parser.cpp index 39d87669d..10d2e7cdd 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2547,7 +2547,7 @@ gb_internal Ast *parse_asm_signature(AstFile *f, Token asm_token) { expect_token(f, Token_OpenParen); f->expr_level += 1; - params = parse_field_list(f, nullptr, FieldFlag_Signature, Token_CloseParen, false, false); + params = parse_field_list(f, nullptr, FieldFlag_Signature, Token_CloseParen, false, true); if (file_allow_newline(f)) { skip_possible_newline(f); } From 22f2e2ac7869348c66ddf8debea70ad2d9a075b6 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 23:38:36 +0100 Subject: [PATCH 05/92] Try to lower to LLVM IR from Odin's `asm` template syntax --- src/check_decl.cpp | 65 +++++-- src/entity.cpp | 42 ++++- src/llvm_backend_asm.cpp | 378 +++++++++++++++++++++++++++++++++++---- 3 files changed, 434 insertions(+), 51 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index ea35e96c5..77095b7ac 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2004,6 +2004,25 @@ gb_internal bool is_valid_asm_parameter_type(Type *type) { return false; } +gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { + if (is_type_integer(type)) { + return AsmRegClass_Integer; + } + if (is_type_float(type)) { + return AsmRegClass_Float; + } + if (is_type_boolean(type)) { + return AsmRegClass_Integer; + } + if (is_type_pointer(type) || is_type_multi_pointer(type)) { + return AsmRegClass_Integer; + } + if (is_type_simd_vector(type)) { + return AsmRegClass_Vector; + } + return AsmRegClass_Unknown; +} + gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { Type *tuple = alloc_type_tuple(); if (_params == nullptr) { @@ -2015,6 +2034,7 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope Array variables = {}; variables.allocator = heap_allocator(); + i32 param_index = 0; for (Ast *param : params) { ast_node(field, Field, param); @@ -2068,21 +2088,21 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope if (found == nullptr) { array_add(&variables, entity); - AsmTemplateEntityDecl ed = {}; - ed.entity = entity; - ed.kind = AsmTemplateEntityDecl_Register; - if (is_type_internally_pointer_like(type)) { - ed.kind = AsmTemplateEntityDecl_Memory; - } + AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); if (is_poly_name) { ed.kind = AsmTemplateEntityDecl_Immediate; } if (input_parameters) { ed.param_group = AsmTemplateEntityDeclParamGroup_Input; + ed.param_index = param_index++; + ed.result_index = -1; } else { ed.param_group = AsmTemplateEntityDeclParamGroup_Output; + ed.param_index = -1; + ed.result_index = param_index++; } + ed.total_index = cast(i32)asm_template_entity_decls->count; array_add(asm_template_entity_decls, ed); } else { TokenPos pos = found->token.pos; @@ -2100,12 +2120,15 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope return tuple; } -gb_internal AsmTemplateEntityDeclParamGroup check_asm_find_group(Entity *entity, Array const &asm_template_entity_decls) { - for (auto const &ed : asm_template_entity_decls) { +gb_internal AsmTemplateEntityDeclParamGroup check_asm_find_group(Entity *entity, Array const &asm_template_entity_decls, i32 *index_) { + for_array(i, asm_template_entity_decls) { + auto const &ed = asm_template_entity_decls[i]; if (ed.entity == entity) { + if (index_) *index_ = cast(i32)i; return ed.param_group; } } + if (index_) *index_ = -1; return AsmTemplateEntityDeclParamGroup_Unknown; }; @@ -2120,7 +2143,6 @@ gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array< gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { - for (Ast *spec_ : specs) { if (spec_->kind != Ast_AsmSpec) { continue; @@ -2150,14 +2172,9 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice Entity *found = scope_insert(scope, entity); if (found == nullptr) { - AsmTemplateEntityDecl ed = {}; - ed.entity = entity; - ed.kind = AsmTemplateEntityDecl_Register; - if (is_type_internally_pointer_like(type)) { - ed.kind = AsmTemplateEntityDecl_Memory; - } + AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; - + ed.total_index = cast(i32)asm_template_entity_decls->count; array_add(asm_template_entity_decls, ed); } else { TokenPos pos = found->token.pos; @@ -2190,8 +2207,11 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice continue; } - auto input_group = check_asm_find_group(input, *asm_template_entity_decls); - auto output_group = check_asm_find_group(output, *asm_template_entity_decls); + i32 input_index = -1; + i32 output_index = -1; + + auto input_group = check_asm_find_group(input, *asm_template_entity_decls, &input_index); + auto output_group = check_asm_find_group(output, *asm_template_entity_decls, &output_index); if (input_group != AsmTemplateEntityDeclParamGroup_Input) { error(input->token, "Parameter tied with '%.*s' must be an input parameter", LIT(output->token.string)); continue; @@ -2201,6 +2221,15 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice continue; } + GB_ASSERT(input_index >= 0); + GB_ASSERT(output_index >= 0); + + auto *i = &(*asm_template_entity_decls)[input_index]; + auto *o = &(*asm_template_entity_decls)[output_index]; + + i->tie = output_index; + o->tie = input_index; + must_check_value = true; } diff --git a/src/entity.cpp b/src/entity.cpp index c439404b6..f2a3f3add 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -169,6 +169,14 @@ enum AsmTemplateEntityDeclKind : u8 { AsmTemplateEntityDecl_COUNT }; +enum AsmRegClass : u8 { + AsmRegClass_Unknown, + AsmRegClass_Integer, + AsmRegClass_Float, + AsmRegClass_Vector, + AsmRegClass_Mask, +}; + enum AsmTemplateEntityDeclParamGroup : u8 { AsmTemplateEntityDeclParamGroup_Unknown, AsmTemplateEntityDeclParamGroup_Input, @@ -183,7 +191,15 @@ struct AsmTemplateEntityDecl { Entity * tied_entity; AsmTemplateEntityDeclKind kind; AsmTemplateEntityDeclParamGroup param_group; - u16 register_map; + AsmRegClass reg_class; + + String pin; + + i32 total_index; + + i32 param_index; // index into the Proc signature's params (inputs), else -1 + i32 result_index; // index into results (outputs), else -1 + i32 tie; // InOut: index into operands[] of the tied output; else -1 }; // An Entity is a named "thing" in the language @@ -333,12 +349,16 @@ struct Entity { bool is_align_stack; Scope *param_scope; Scope *label_scope; - Array decls; + } AsmTemplate; }; }; + +gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type); +gb_internal bool is_type_internally_pointer_like(Type *t); + gb_internal InternedString entity_interned_name(Entity *entity) { auto name = entity->interned_name.load(); if (name.value == 0) { @@ -349,6 +369,24 @@ gb_internal InternedString entity_interned_name(Entity *entity) { return name; } + +gb_internal AsmTemplateEntityDecl asm_template_entity_decl_default(Entity *entity) { + AsmTemplateEntityDecl ed = {}; + ed.kind = AsmTemplateEntityDecl_Register; + if (is_type_internally_pointer_like(entity->type)) { + ed.kind = AsmTemplateEntityDecl_Memory; + } + ed.reg_class = check_asm_reg_class_from_type(entity->type); + ed.entity = entity; + ed.total_index = -1; + ed.param_index = -1; + ed.result_index = -1; + ed.tie = -1; + + return ed; +} + + gb_internal bool is_entity_kind_exported(EntityKind kind, bool allow_builtin = false) { switch (kind) { case Entity_Builtin: diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index ad8e54a0e..eaae31320 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -1,43 +1,359 @@ +gb_internal AsmTemplateEntityDecl *lb_asm_entity_decl(Array *decls, Entity *e) { + for (AsmTemplateEntityDecl &op : *decls) { + if (op.entity == e) { + return &op; + } + } + GB_PANIC("Could not find asm entity %s", LIT(e->token.string)); + return nullptr; +}; + +gb_internal gbString lb_asm_write_label_name(gbString asm_string, AstIdent *label_ident) { + String name = label_ident->token.string; + asm_string = gb_string_appendc(asm_string, ".L"); + asm_string = gb_string_append_length(asm_string, name.text, name.len); + // ${:uid} expands to a per-instantiation unique integer, so repeated + // inlining of the same template can't collide on the label symbol. + asm_string = gb_string_appendc(asm_string, "${:uid}"); + return asm_string; +} + +gb_internal gbString lb_asm_write_operand(gbString asm_string, Array op_number, Array *decls, Ast *op, bool print_prefixes=true) { + switch (op->kind) { + case_ast_node(i, Ident, op); + Entity *e = entity_of_node(op); + auto *ed = lb_asm_entity_decl(decls, e); + + i32 idx = op_number[ed->total_index]; + GB_ASSERT(idx >= 0); + asm_string = gb_string_append_fmt(asm_string, "$%d", idx); + case_end; + case_ast_node(mem_op, AsmMemoryOperand, op); + if (mem_op->disp) { + asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->disp, /*print_prefixes*/false); + } + asm_string = gb_string_appendc(asm_string, "("); + GB_ASSERT(mem_op->base != nullptr); + asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->base); + if (mem_op->index) { + asm_string = gb_string_appendc(asm_string, ","); + asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->index); + if (mem_op->scale) { + asm_string = gb_string_appendc(asm_string, ","); + asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->scale, /*print_prefixes*/false); + } + } + asm_string = gb_string_appendc(asm_string, ")"); + case_end; + + case_ast_node(bl, BasicLit, op); + ExactValue ev = op->tav.value; + GB_ASSERT(ev.kind != ExactValue_Invalid); + switch (ev.kind) { + case ExactValue_Integer: { + String s = big_int_to_string(heap_allocator(), &ev.value_integer, 10); + if (print_prefixes) { + asm_string = gb_string_appendc(asm_string, "$$"); + } + asm_string = gb_string_append_length(asm_string, s.text, s.len); + gb_free(heap_allocator(), s.text); + break; + } + default: + GB_PANIC("Unsupported asm immediate literal %s", expr_to_string(op)); + break; + } + case_end; + + case_ast_node(label, AsmLabelDecl, op); + String name = label->name->Ident.token.string; + asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); + case_end; + default: + GB_PANIC("TODO %s", expr_to_string(op)); + break; + } + return asm_string; +} + + gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args) { - GB_ASSERT(entity->kind == Entity_AsmTemplate); + GB_ASSERT(entity != nullptr); + lbModule *m = p->module; + LLVMContextRef ctx = m->ctx; - // GB_PANIC("TODO(bill): lb_emit_asm_template_call"); - gbString asm_string = gb_string_make(heap_allocator(), ""); - gbString constraints = gb_string_make(heap_allocator(), ""); + // Assumed frontend accessor: template string, flags, dialect, and the operand table. + auto &tmpl = entity->AsmTemplate; + Array &ops = tmpl.decls; - auto *ate = &entity->AsmTemplate; - GB_ASSERT(ate->node->kind == Ast_AsmTemplate); - auto *node = &ate->node->AsmTemplate; + TEMPORARY_ALLOCATOR_GUARD(); + gbString asm_string = gb_string_make_reserve(temporary_allocator(), 64); + gbString constraints = gb_string_make_reserve(temporary_allocator(), 64); + + auto param_types = array_make(temporary_allocator(), 0, ops.count); + auto call_args = array_make(temporary_allocator(), 0, ops.count); + auto ret_types = array_make(temporary_allocator(), 0, ops.count); + + // Per-operand bookkeeping, indexed the same as `ops`. + auto op_number = array_make(temporary_allocator(), ops.count, ops.count); // $N, or -1 for clobbers + auto ret_slot = array_make(temporary_allocator(), ops.count, ops.count); // return-struct index, or -1 + for_array(i, ops) { + op_number[i] = -1; + ret_slot[i] = -1; + } + + // elementtype() attrs to attach after the call is built (indirect/memory operands). + struct ElemAttr { + unsigned arg_pos; + LLVMTypeRef elem; + }; + auto elem_attrs = array_make(temporary_allocator(), 0, ops.count); + + i32 next_op = 0; // running $N counter (outputs first, then inputs) + + auto sep = [&]() { + if (gb_string_length(constraints) != 0) { + constraints = gb_string_appendc(constraints, ","); + } + }; + auto raw = [&](char const *s) { + constraints = gb_string_appendc(constraints, s); + }; + auto put = [&](String s) { + constraints = gb_string_append_length(constraints, s.text, s.len); + }; + + auto class_letter = [&](AsmRegClass rc) -> char const * { + switch (rc) { + case AsmRegClass_Integer: return "r"; + case AsmRegClass_Float: return "x"; // TODO(bill): target-dependent + case AsmRegClass_Vector: return "x"; // TODO(bill): target-dependent + case AsmRegClass_Mask: return "^Yk"; // AVX-512 k-regs + default: GB_PANIC("asm: unknown reg class"); return "r"; + } + }; + + // LLVM type of a returned register output, taken from the proc signature's results. + auto output_llvm_type = [&](AsmTemplateEntityDecl const &e) -> LLVMTypeRef { + Type *pt = base_type(entity->type); + Type *rt = pt->Proc.results->Tuple.variables[e.result_index]->type; + return lb_type(m, rt); + }; + + auto add_arg = [&](LLVMValueRef v) -> unsigned { + unsigned pos = cast(unsigned)call_args.count; + array_add(¶m_types, LLVMTypeOf(v)); + array_add(&call_args, v); + return pos; + }; + + for_array(i, ops) { + AsmTemplateEntityDecl const &e = ops[i]; + + bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; + bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch + && e.kind == AsmTemplateEntityDecl_Register + && e.pin.len == 0; + if (!is_output && !is_alloc_scratch) { + continue; + } + + sep(); + + if (e.kind == AsmTemplateEntityDecl_Memory) { + // Indirect memory output: writes through a pointer, so it takes an arg + // and contributes nothing to the return type. + raw("=*m"); + lbValue ptr = args[e.param_index]; + unsigned pos = add_arg(ptr.value); + array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(ptr.type))}); + op_number[i] = next_op++; + } else { + // Register output: '=' ['&'] ( '{pin}' | class-letter ) + raw("="); + if (is_alloc_scratch) raw("&"); // early-clobber: keep scratch off any input reg + if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } + else raw(class_letter(e.reg_class)); + + LLVMTypeRef ty = is_alloc_scratch + ? lb_type(m, t_uintptr) // TODO: pick a register-width type per reg_class + : output_llvm_type(e); + + ret_slot[i] = cast(i32)ret_types.count; + array_add(&ret_types, ty); + op_number[i] = next_op++; + } + } + + // ---- Pass 2: inputs ------------------------------------------------------ + for (isize i = 0; i < ops.count; i++) { + AsmTemplateEntityDecl const &e = ops[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) continue; + + sep(); + lbValue v = args[e.param_index]; + + if (e.tie >= 0) { + // Tied read-write input: a matching constraint referencing the tied + // output's operand number (e.g. "0"). + i32 n = op_number[e.tie]; + GB_ASSERT(n >= 0); + constraints = gb_string_append_fmt(constraints, "%d", n); + add_arg(v.value); + } else { + switch (e.kind) { + case AsmTemplateEntityDecl_Register: + if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } + else raw(class_letter(e.reg_class)); + add_arg(v.value); + break; + case AsmTemplateEntityDecl_Memory: { + raw("*m"); // indirect + unsigned pos = add_arg(v.value); + array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); + break; + } + case AsmTemplateEntityDecl_Immediate: + raw("i"); // TODO: "n" if a known-constant integer is required + add_arg(v.value); + break; + default: + GB_PANIC("asm: invalid input operand kind"); + } + } + op_number[i] = next_op++; + } + + GB_ASSERT(tmpl.node->kind = Ast_AsmTemplate); + auto *node = &tmpl.node->AsmTemplate; for_array(i, node->instructions) { - auto *instruction = node->instructions[i]; - gb_unused(instruction); + if (i > 0) { + asm_string = gb_string_appendc(asm_string, "\n"); + } + Ast *instr_ = node->instructions[i]; + switch (instr_->kind) { + case_ast_node(instr, AsmInstruction, instr_); + asm_string = gb_string_appendc(asm_string, "\t"); + String name = instr->name->Ident.token.string; + asm_string = gb_string_append_length(asm_string, name.text, name.len); + asm_string = gb_string_appendc(asm_string, " "); + for (isize j = instr->operands.count-1; j >= 0; j -= 1) { + Ast *op = instr->operands[j]; + if (j < instr->operands.count-1) { + asm_string = gb_string_appendc(asm_string, ", "); + } + asm_string = lb_asm_write_operand(asm_string, op_number, &ops, op); + } + + + case_end; + case_ast_node(label, AsmLabelDecl, instr_); + asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); + asm_string = gb_string_appendc(asm_string, ":"); + case_end; + default: + GB_PANIC("Invalid asm instruction"); + break; + } } - // asm_string = gb_string_appendc(asm_string, "lock cmpxchg16b $3"); - // asm_string = gb_string_appendc(asm_string, "\\0A\\09"); - // asm_string = gb_string_appendc(asm_string, "setz $2"); - // constraints = gb_string_appendc(constraints, "*m,={ax},={dx},=r,{ax},{dx},{bx},{cx},~{cc},~{memory}"); + gb_printf_err("%s\n", asm_string); - Type *proc_type = base_type(entity->type); - GB_ASSERT(proc_type->kind == Type_Proc); + // ---- Pass 3: clobbers ---------------------------------------------------- + // Only the Scratch group. Unpinned register scratch was already emitted as an + // output in Pass 1, so it is skipped here. + for (isize i = 0; i < ops.count; i++) { + AsmTemplateEntityDecl const &e = ops[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Scratch) { + continue; + } + if (e.kind == AsmTemplateEntityDecl_Register && e.pin.len == 0) { + continue; + } - LLVMTypeRef llvm_type = lb_type_internal_for_procedures_raw(p->module, proc_type); - gb_printf_err("%s\n", LLVMPrintTypeToString(llvm_type)); - - LLVMValueRef fn = LLVMGetInlineAsm(llvm_type, asm_string, gb_string_length(asm_string), - constraints, gb_string_length(constraints), - entity->AsmTemplate.has_side_effects, - entity->AsmTemplate.is_align_stack, - LLVMInlineAsmDialectATT, /*CanThrow*/false); - - LLVMValueRef *llvm_args = gb_alloc_array(heap_allocator(), LLVMValueRef, args.count); - for_array(i, args) { - llvm_args[i] = args[i].value; + sep(); + switch (e.kind) { + case AsmTemplateEntityDecl_Register: // pinned -> real clobber + GB_ASSERT(e.pin.len != 0); + raw("~{"); put(e.pin); raw("}"); + break; + case AsmTemplateEntityDecl_Memory: // general memory clobber + raw("~{memory}"); + break; + default: + GB_PANIC("asm: invalid scratch operand kind"); + } } - LLVMValueRef result = LLVMBuildCall2(p->builder, llvm_type, fn, llvm_args, cast(unsigned)args.count, ""); - Type *result_type = reduce_tuple_to_single_type(proc_type->Proc.results); - gb_printf_err("%s\n", LLVMPrintValueToString(result)); - return {result, result_type}; + LLVMTypeRef ret_ty = nullptr; + if (ret_types.count == 0) { + ret_ty = LLVMVoidTypeInContext(ctx); + } else if (ret_types.count == 1) { + ret_ty = ret_types[0]; + } else { + ret_ty = LLVMStructTypeInContext(ctx, ret_types.data, cast(unsigned)ret_types.count, /*packed*/false); + } + + LLVMTypeRef fn_ty = LLVMFunctionType(ret_ty, param_types.data, cast(unsigned)param_types.count, /*vararg*/false); + + LLVMValueRef ia = LLVMGetInlineAsm( + fn_ty, + asm_string, cast(size_t)gb_string_length(asm_string), + constraints, cast(size_t)gb_string_length(constraints), + /*HasSideEffects*/ tmpl.has_side_effects, + /*IsAlignStack*/ tmpl.is_align_stack, + LLVMInlineAsmDialectATT, + /*CanThrow*/ false); + + LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); + + gb_printf_err("%s\n", LLVMPrintValueToString(call)); + + // Attach elementtype() to every indirect operand's pointer arg (opaque-pointer requirement). + unsigned et_kind = LLVMGetEnumAttributeKindForName("elementtype", 11); + for (isize k = 0; k < elem_attrs.count; k++) { + LLVMAttributeRef attr = LLVMCreateTypeAttribute(ctx, et_kind, elem_attrs[k].elem); + LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attrs[k].arg_pos + 1), attr); + } + + // ---- Repackage results in Odin result order ------------------------------ + Type *pt = base_type(entity->type); + isize result_count = (pt->Proc.results != nullptr) ? pt->Proc.results->Tuple.variables.count : 0; + if (result_count == 0) { + return lbValue{}; // void asm (memory outputs already wrote through their pointers) + } + + // The LLVM return struct is ordered by operand, and includes scratch slots; + // pull out only the real register outputs and index them by result_index. + auto result_vals = array_make(temporary_allocator(), result_count, result_count); + for (isize i = 0; i < result_count; i++) result_vals[i] = nullptr; + + for (isize i = 0; i < ops.count; i++) { + AsmTemplateEntityDecl const &e = ops[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) continue; + if (e.result_index < 0) continue; // memory output: not a returned value + GB_ASSERT(ret_slot[i] >= 0); + + LLVMValueRef v = (ret_types.count == 1) + ? call // single-element return is not a struct + : LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); + result_vals[e.result_index] = v; + } + + if (result_count == 1) { + Type *rt = pt->Proc.results->Tuple.variables[0]->type; + return lbValue{result_vals[0], rt}; + } + + // Multiple results -> assemble Odin's result aggregate in result order. + Type *results_type = pt->Proc.results; + LLVMValueRef agg = LLVMGetUndef(lb_type(m, results_type)); + for (isize i = 0; i < result_count; i++) { + GB_ASSERT(result_vals[i] != nullptr); + agg = LLVMBuildInsertValue(p->builder, agg, result_vals[i], cast(unsigned)i, ""); + } + + + return lbValue{agg, results_type}; } \ No newline at end of file From b4da67c6afd4579e74f533c9e17e4445857944d7 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Sun, 9 Aug 2026 23:51:14 +0100 Subject: [PATCH 06/92] Ignore the `AsmTemplateEntityDecl_Memory` parameters for the time being --- src/llvm_backend_asm.cpp | 48 +++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index eaae31320..2b5141dfa 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -6,7 +6,7 @@ gb_internal AsmTemplateEntityDecl *lb_asm_entity_decl(Arraytoken.string)); return nullptr; -}; +} gb_internal gbString lb_asm_write_label_name(gbString asm_string, AstIdent *label_ident) { String name = label_ident->token.string; @@ -66,7 +66,6 @@ gb_internal gbString lb_asm_write_operand(gbString asm_string, Array op_num case_end; case_ast_node(label, AsmLabelDecl, op); - String name = label->name->Ident.token.string; asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); case_end; default: @@ -95,7 +94,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar auto call_args = array_make(temporary_allocator(), 0, ops.count); auto ret_types = array_make(temporary_allocator(), 0, ops.count); - // Per-operand bookkeeping, indexed the same as `ops`. + // Per-operand bookkeeping, indexed the same as `ops` (via total_index). auto op_number = array_make(temporary_allocator(), ops.count, ops.count); // $N, or -1 for clobbers auto ret_slot = array_make(temporary_allocator(), ops.count, ops.count); // return-struct index, or -1 for_array(i, ops) { @@ -120,7 +119,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar auto raw = [&](char const *s) { constraints = gb_string_appendc(constraints, s); }; - auto put = [&](String s) { + auto put = [&](String s) { constraints = gb_string_append_length(constraints, s.text, s.len); }; @@ -148,6 +147,9 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar return pos; }; + // ---- Pass 1: outputs ----------------------------------------------------- + // Real outputs plus *unpinned* register scratch (modeled as discarded + // early-clobber outputs, since a clobber can only name a fixed register). for_array(i, ops) { AsmTemplateEntityDecl const &e = ops[i]; @@ -161,7 +163,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar sep(); - if (e.kind == AsmTemplateEntityDecl_Memory) { + if (false && e.kind == AsmTemplateEntityDecl_Memory) { // Indirect memory output: writes through a pointer, so it takes an arg // and contributes nothing to the return type. raw("=*m"); @@ -176,8 +178,10 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } else raw(class_letter(e.reg_class)); + // Use the entity's real declared type so the return-struct slot matches + // the constraint's width/class (e.g. <4 x float> for a #simd[4]f32 scratch). LLVMTypeRef ty = is_alloc_scratch - ? lb_type(m, t_uintptr) // TODO: pick a register-width type per reg_class + ? lb_type(m, e.entity->type) : output_llvm_type(e); ret_slot[i] = cast(i32)ret_types.count; @@ -204,16 +208,17 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } else { switch (e.kind) { case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Memory: if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } else raw(class_letter(e.reg_class)); add_arg(v.value); break; - case AsmTemplateEntityDecl_Memory: { - raw("*m"); // indirect - unsigned pos = add_arg(v.value); - array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); - break; - } + // case AsmTemplateEntityDecl_Memory: { + // raw("*m"); // indirect + // unsigned pos = add_arg(v.value); + // array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); + // break; + // } case AsmTemplateEntityDecl_Immediate: raw("i"); // TODO: "n" if a known-constant integer is required add_arg(v.value); @@ -225,7 +230,8 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar op_number[i] = next_op++; } - GB_ASSERT(tmpl.node->kind = Ast_AsmTemplate); + // ---- Build the template text --------------------------------------------- + GB_ASSERT(tmpl.node->kind == Ast_AsmTemplate); auto *node = &tmpl.node->AsmTemplate; for_array(i, node->instructions) { if (i > 0) { @@ -238,6 +244,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar String name = instr->name->Ident.token.string; asm_string = gb_string_append_length(asm_string, name.text, name.len); asm_string = gb_string_appendc(asm_string, " "); + // Intel-source operand order reversed to AT&T (src, ..., dst). for (isize j = instr->operands.count-1; j >= 0; j -= 1) { Ast *op = instr->operands[j]; if (j < instr->operands.count-1) { @@ -245,8 +252,6 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } asm_string = lb_asm_write_operand(asm_string, op_number, &ops, op); } - - case_end; case_ast_node(label, AsmLabelDecl, instr_); asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); @@ -258,8 +263,6 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } } - gb_printf_err("%s\n", asm_string); - // ---- Pass 3: clobbers ---------------------------------------------------- // Only the Scratch group. Unpinned register scratch was already emitted as an // output in Pass 1, so it is skipped here. @@ -286,6 +289,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } } + // ---- Build the callee type ----------------------------------------------- LLVMTypeRef ret_ty = nullptr; if (ret_types.count == 0) { ret_ty = LLVMVoidTypeInContext(ctx); @@ -308,7 +312,12 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - gb_printf_err("%s\n", LLVMPrintValueToString(call)); + { + gb_printf_err("%s\n", asm_string); + char *ir = LLVMPrintValueToString(call); + gb_printf_err("%s\n", ir); + LLVMDisposeMessage(ir); + } // Attach elementtype() to every indirect operand's pointer arg (opaque-pointer requirement). unsigned et_kind = LLVMGetEnumAttributeKindForName("elementtype", 11); @@ -324,7 +333,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar return lbValue{}; // void asm (memory outputs already wrote through their pointers) } - // The LLVM return struct is ordered by operand, and includes scratch slots; + // The LLVM return struct is ordered by operand and includes scratch slots; // pull out only the real register outputs and index them by result_index. auto result_vals = array_make(temporary_allocator(), result_count, result_count); for (isize i = 0; i < result_count; i++) result_vals[i] = nullptr; @@ -354,6 +363,5 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar agg = LLVMBuildInsertValue(p->builder, agg, result_vals[i], cast(unsigned)i, ""); } - return lbValue{agg, results_type}; } \ No newline at end of file From cee5bd79e06219be31c0e1eca037fc57c9ab97b2 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 10 Aug 2026 12:06:28 +0100 Subject: [PATCH 07/92] Fix pinning logic for asm registers --- src/check_decl.cpp | 37 ++++++++++++++--- src/llvm_backend_asm.cpp | 87 ++++++++++++++++++++++------------------ src/parser.cpp | 9 ++++- src/parser.hpp | 1 + 4 files changed, 89 insertions(+), 45 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 77095b7ac..2783e982d 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2155,6 +2155,22 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice bool must_check_value = false; + String pin = {}; + if (spec->value != nullptr) { + if (spec->value->kind != Ast_AsmRegister) { + gbString s = expr_to_string(spec->value); + error(spec->value, "Expected an asm register, got %s", s); + gb_string_free(s); + continue; + } + + ast_node(reg, AsmRegister, spec->value); + pin = reg->name.string; + if (pin == "any") { + pin = {}; + } + } + if (spec->tied_name == nullptr) { if (spec->type != nullptr) { Type *type = check_type(ctx, spec->type); @@ -2175,6 +2191,7 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; ed.total_index = cast(i32)asm_template_entity_decls->count; + ed.pin = pin; array_add(asm_template_entity_decls, ed); } else { TokenPos pos = found->token.pos; @@ -2188,6 +2205,17 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } else if (input == nullptr) { error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); continue; + } else { + i32 index = -1; + auto group = check_asm_find_group(input, *asm_template_entity_decls, &index); + gb_unused(group); + GB_ASSERT(index >= 0); + auto *i = &(*asm_template_entity_decls)[index]; + if (i->pin.len == 0) { + i->pin = pin; + } else { + error(spec_, "Asm register has already been pinned"); + } } } else { @@ -2230,13 +2258,12 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice i->tie = output_index; o->tie = input_index; + i->pin = pin; + o->pin = pin; + + must_check_value = true; } - - if (spec->value != nullptr) { - // TODO(bill): check registers - } - } } diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 2b5141dfa..cc08841ff 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -147,7 +147,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar return pos; }; - // ---- Pass 1: outputs ----------------------------------------------------- + // Pass 1: outputs // Real outputs plus *unpinned* register scratch (modeled as discarded // early-clobber outputs, since a clobber can only name a fixed register). for_array(i, ops) { @@ -163,37 +163,32 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar sep(); - if (false && e.kind == AsmTemplateEntityDecl_Memory) { - // Indirect memory output: writes through a pointer, so it takes an arg - // and contributes nothing to the return type. - raw("=*m"); - lbValue ptr = args[e.param_index]; - unsigned pos = add_arg(ptr.value); - array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(ptr.type))}); - op_number[i] = next_op++; - } else { - // Register output: '=' ['&'] ( '{pin}' | class-letter ) - raw("="); - if (is_alloc_scratch) raw("&"); // early-clobber: keep scratch off any input reg - if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } - else raw(class_letter(e.reg_class)); - - // Use the entity's real declared type so the return-struct slot matches - // the constraint's width/class (e.g. <4 x float> for a #simd[4]f32 scratch). - LLVMTypeRef ty = is_alloc_scratch - ? lb_type(m, e.entity->type) - : output_llvm_type(e); - - ret_slot[i] = cast(i32)ret_types.count; - array_add(&ret_types, ty); - op_number[i] = next_op++; + // Register output: '=' ['&'] ( '{pin}' | class-letter ) + raw("="); + if (is_alloc_scratch) { // early-clobber: keep scratch off any input reg + raw("&"); } + if (e.pin.len != 0) { + raw("{"); put(e.pin); raw("}"); + } else { + raw(class_letter(e.reg_class)); + } + + // Use the entity's real declared type so the return-struct slot matches + // the constraint's width/class (e.g. <4 x float> for a #simd[4]f32 scratch). + LLVMTypeRef ty = is_alloc_scratch ? lb_type(m, e.entity->type) : output_llvm_type(e); + + ret_slot[i] = cast(i32)ret_types.count; + array_add(&ret_types, ty); + op_number[i] = next_op++; } - // ---- Pass 2: inputs ------------------------------------------------------ + // Pass 2: inputs for (isize i = 0; i < ops.count; i++) { AsmTemplateEntityDecl const &e = ops[i]; - if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) continue; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) { + continue; + } sep(); lbValue v = args[e.param_index]; @@ -209,8 +204,11 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar switch (e.kind) { case AsmTemplateEntityDecl_Register: case AsmTemplateEntityDecl_Memory: - if (e.pin.len != 0) { raw("{"); put(e.pin); raw("}"); } - else raw(class_letter(e.reg_class)); + if (e.pin.len != 0) { + raw("{"); put(e.pin); raw("}"); + } else { + raw(class_letter(e.reg_class)); + } add_arg(v.value); break; // case AsmTemplateEntityDecl_Memory: { @@ -230,7 +228,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar op_number[i] = next_op++; } - // ---- Build the template text --------------------------------------------- + // Build the template text GB_ASSERT(tmpl.node->kind == Ast_AsmTemplate); auto *node = &tmpl.node->AsmTemplate; for_array(i, node->instructions) { @@ -263,7 +261,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } } - // ---- Pass 3: clobbers ---------------------------------------------------- + // Pass 3: clobbers // Only the Scratch group. Unpinned register scratch was already emitted as an // output in Pass 1, so it is skipped here. for (isize i = 0; i < ops.count; i++) { @@ -289,7 +287,10 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } } - // ---- Build the callee type ----------------------------------------------- + // Build the callee type + // NOTE(bill): Even though the user has given a signature, this might not actually match what + // LLVM requires it to be due to the scratch parameters and more, so many of the results might + // need to be completely ignored to match the user's given signature. LLVMTypeRef ret_ty = nullptr; if (ret_types.count == 0) { ret_ty = LLVMVoidTypeInContext(ctx); @@ -301,21 +302,27 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar LLVMTypeRef fn_ty = LLVMFunctionType(ret_ty, param_types.data, cast(unsigned)param_types.count, /*vararg*/false); + // TODO(bill): determine all the cases when side-effects happen + bool has_side_effects = tmpl.has_side_effects; + LLVMValueRef ia = LLVMGetInlineAsm( fn_ty, asm_string, cast(size_t)gb_string_length(asm_string), constraints, cast(size_t)gb_string_length(constraints), - /*HasSideEffects*/ tmpl.has_side_effects, + /*HasSideEffects*/ has_side_effects, /*IsAlignStack*/ tmpl.is_align_stack, LLVMInlineAsmDialectATT, /*CanThrow*/ false); LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - { + { // DEBUG PRINT!!! + // DEBUG PRINT!!! + // DEBUG PRINT!!! + // DEBUG PRINT!!! gb_printf_err("%s\n", asm_string); char *ir = LLVMPrintValueToString(call); - gb_printf_err("%s\n", ir); + gb_printf_err("%s\n\n", ir); LLVMDisposeMessage(ir); } @@ -326,7 +333,7 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attrs[k].arg_pos + 1), attr); } - // ---- Repackage results in Odin result order ------------------------------ + // Repackage results in Odin result order Type *pt = base_type(entity->type); isize result_count = (pt->Proc.results != nullptr) ? pt->Proc.results->Tuple.variables.count : 0; if (result_count == 0) { @@ -340,8 +347,12 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar for (isize i = 0; i < ops.count; i++) { AsmTemplateEntityDecl const &e = ops[i]; - if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) continue; - if (e.result_index < 0) continue; // memory output: not a returned value + if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) { + continue; + } + if (e.result_index < 0) { + continue; // memory output: not a returned value + } GB_ASSERT(ret_slot[i] >= 0); LLVMValueRef v = (ret_types.count == 1) diff --git a/src/parser.cpp b/src/parser.cpp index 10d2e7cdd..48e933c63 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -542,6 +542,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmLabelDecl.name = clone_ast(n->AsmLabelDecl.name, f); break; case Ast_AsmInstruction: + n->AsmInstruction.prefix = clone_ast(n->AsmInstruction.prefix, f); n->AsmInstruction.name = clone_ast(n->AsmInstruction.name, f); n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); break; @@ -2628,8 +2629,12 @@ gb_internal Ast *parse_asm_template(AstFile *f) { value = parse_asm_register(f); } - if (type == nullptr && value == nullptr) { - syntax_error(f->curr_token, "An asm specification must specify at least either a type or a value"); + if (tied_name != nullptr) { + if (type != nullptr) { + syntax_error(f->curr_token, "An asm specification for tied values cannot declare a type"); + } + } else if (type == nullptr && value == nullptr) { + syntax_error(f->curr_token, "An asm specification must specify at least either a type or a value if the value is not tied"); } spec = alloc_ast_node(f, Ast_AsmSpec); diff --git a/src/parser.hpp b/src/parser.hpp index 0390937c0..22ddc0938 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -497,6 +497,7 @@ struct AstSplitArgs { Ast * name; \ }) \ AST_KIND(AsmInstruction, "asm instruction", struct { \ + Ast * prefix; /*optional*/ \ Ast * name; \ Slice operands; \ }) \ From 768fedcff414dd98981df234c4922b292a37cb40 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 10 Aug 2026 13:21:14 +0100 Subject: [PATCH 08/92] Minor fixes to labels; restrict to amd64 usage --- src/llvm_backend_asm.cpp | 22 ++++++++++++---------- src/name_canonicalization.cpp | 4 +++- src/parser.cpp | 4 ++++ 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index cc08841ff..c80e195a3 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -8,9 +8,11 @@ gb_internal AsmTemplateEntityDecl *lb_asm_entity_decl(Arraytoken.string; - asm_string = gb_string_appendc(asm_string, ".L"); + asm_string = gb_string_appendc(asm_string, ".L_"); + asm_string = gb_string_append_length(asm_string, tmpl_entity->token.string.text, tmpl_entity->token.string.len); + asm_string = gb_string_appendc(asm_string, "_"); asm_string = gb_string_append_length(asm_string, name.text, name.len); // ${:uid} expands to a per-instantiation unique integer, so repeated // inlining of the same template can't collide on the label symbol. @@ -18,7 +20,7 @@ gb_internal gbString lb_asm_write_label_name(gbString asm_string, AstIdent *labe return asm_string; } -gb_internal gbString lb_asm_write_operand(gbString asm_string, Array op_number, Array *decls, Ast *op, bool print_prefixes=true) { +gb_internal gbString lb_asm_write_operand(gbString asm_string, Entity *tmpl_entity, Array op_number, Array *decls, Ast *op, bool print_prefixes=true) { switch (op->kind) { case_ast_node(i, Ident, op); Entity *e = entity_of_node(op); @@ -30,17 +32,17 @@ gb_internal gbString lb_asm_write_operand(gbString asm_string, Array op_num case_end; case_ast_node(mem_op, AsmMemoryOperand, op); if (mem_op->disp) { - asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->disp, /*print_prefixes*/false); + asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->disp, /*print_prefixes*/false); } asm_string = gb_string_appendc(asm_string, "("); GB_ASSERT(mem_op->base != nullptr); - asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->base); + asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->base); if (mem_op->index) { asm_string = gb_string_appendc(asm_string, ","); - asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->index); + asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->index); if (mem_op->scale) { asm_string = gb_string_appendc(asm_string, ","); - asm_string = lb_asm_write_operand(asm_string, op_number, decls, mem_op->scale, /*print_prefixes*/false); + asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->scale, /*print_prefixes*/false); } } asm_string = gb_string_appendc(asm_string, ")"); @@ -66,7 +68,7 @@ gb_internal gbString lb_asm_write_operand(gbString asm_string, Array op_num case_end; case_ast_node(label, AsmLabelDecl, op); - asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); + asm_string = lb_asm_write_label_name(asm_string, tmpl_entity, &label->name->Ident); case_end; default: GB_PANIC("TODO %s", expr_to_string(op)); @@ -248,11 +250,11 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar if (j < instr->operands.count-1) { asm_string = gb_string_appendc(asm_string, ", "); } - asm_string = lb_asm_write_operand(asm_string, op_number, &ops, op); + asm_string = lb_asm_write_operand(asm_string, entity, op_number, &ops, op); } case_end; case_ast_node(label, AsmLabelDecl, instr_); - asm_string = lb_asm_write_label_name(asm_string, &label->name->Ident); + asm_string = lb_asm_write_label_name(asm_string, entity, &label->name->Ident); asm_string = gb_string_appendc(asm_string, ":"); case_end; default: diff --git a/src/name_canonicalization.cpp b/src/name_canonicalization.cpp index 13fa01830..1e615d7c8 100644 --- a/src/name_canonicalization.cpp +++ b/src/name_canonicalization.cpp @@ -573,7 +573,8 @@ gb_internal gbString string_canonical_entity_name(gbAllocator allocator, Entity gb_internal void write_canonical_parent_prefix(TypeWriter *w, Entity *e) { GB_ASSERT(e != nullptr); - if (e->kind == Entity_Procedure || e->kind == Entity_TypeName || e->kind == Entity_Variable) { + if (e->kind == Entity_Procedure || e->kind == Entity_AsmTemplate || + e->kind == Entity_TypeName || e->kind == Entity_Variable) { if (e->kind == Entity_Procedure && (e->Procedure.is_export || e->Procedure.is_foreign)) { // no prefix return; @@ -740,6 +741,7 @@ write_base_name: // For debug symbols only /*fallthrough*/ case Entity_Procedure: + case Entity_AsmTemplate: case Entity_Variable: type_writer_append(w, e->token.string.text, e->token.string.len); if (is_type_polymorphic(e->type)) { diff --git a/src/parser.cpp b/src/parser.cpp index 48e933c63..d63c60585 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2696,6 +2696,10 @@ gb_internal Ast *parse_asm_template(AstFile *f) { asm_instructions = slice_from_array(instructions); } + if (build_context.metrics.arch != TargetArch_amd64) { + syntax_error(token, "asm templates are currently only supported on -target:amd64"); + } + Ast *asm_template = alloc_ast_node(f, Ast_AsmTemplate); asm_template->AsmTemplate.token = token; asm_template->AsmTemplate.has_side_effects = has_side_effects; From 6b534a318ee0d747975cfb9b6570ff9ea7c29774 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 10 Aug 2026 13:41:58 +0100 Subject: [PATCH 09/92] Begin abstracting out the platform specific code into a class I know... a class. If only C++ had a nice way to package different things like Odin itself. --- src/llvm_backend_asm.cpp | 679 ++++++++++++++++++++------------------- 1 file changed, 354 insertions(+), 325 deletions(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index c80e195a3..24a6daef9 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -1,131 +1,83 @@ -gb_internal AsmTemplateEntityDecl *lb_asm_entity_decl(Array *decls, Entity *e) { - for (AsmTemplateEntityDecl &op : *decls) { - if (op.entity == e) { - return &op; - } +struct lbAsmGenerate { + Entity * tmpl_entity; + AstAsmTemplate * tmpl_node; + Array *ops; + + void init(Entity *entity) { + this->tmpl_entity = entity; + GB_ASSERT(this->tmpl_entity != nullptr); + GB_ASSERT(this->tmpl_entity->kind == Entity_AsmTemplate); + this->ops = &this->tmpl_entity->AsmTemplate.decls; + GB_ASSERT(this->tmpl_entity->AsmTemplate.node->kind == Ast_AsmTemplate); + this->tmpl_node = &this->tmpl_entity->AsmTemplate.node->AsmTemplate; } - GB_PANIC("Could not find asm entity %s", LIT(e->token.string)); - return nullptr; -} -gb_internal gbString lb_asm_write_label_name(gbString asm_string, Entity *tmpl_entity, AstIdent *label_ident) { - String name = label_ident->token.string; - asm_string = gb_string_appendc(asm_string, ".L_"); - asm_string = gb_string_append_length(asm_string, tmpl_entity->token.string.text, tmpl_entity->token.string.len); - asm_string = gb_string_appendc(asm_string, "_"); - asm_string = gb_string_append_length(asm_string, name.text, name.len); - // ${:uid} expands to a per-instantiation unique integer, so repeated - // inlining of the same template can't collide on the label symbol. - asm_string = gb_string_appendc(asm_string, "${:uid}"); - return asm_string; -} + gbString write_label(gbString asm_string, AstIdent *label_ident) { + String name = label_ident->token.string; + asm_string = gb_string_appendc(asm_string, ".L_"); + asm_string = gb_string_append_length(asm_string, tmpl_entity->token.string.text, tmpl_entity->token.string.len); + asm_string = gb_string_appendc(asm_string, "_"); + asm_string = gb_string_append_length(asm_string, name.text, name.len); + // ${:uid} expands to a per-instantiation unique integer, so repeated + // inlining of the same template can't collide on the label symbol. + asm_string = gb_string_appendc(asm_string, "${:uid}"); + return asm_string; + } -gb_internal gbString lb_asm_write_operand(gbString asm_string, Entity *tmpl_entity, Array op_number, Array *decls, Ast *op, bool print_prefixes=true) { - switch (op->kind) { - case_ast_node(i, Ident, op); - Entity *e = entity_of_node(op); - auto *ed = lb_asm_entity_decl(decls, e); - - i32 idx = op_number[ed->total_index]; - GB_ASSERT(idx >= 0); - asm_string = gb_string_append_fmt(asm_string, "$%d", idx); - case_end; - case_ast_node(mem_op, AsmMemoryOperand, op); - if (mem_op->disp) { - asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->disp, /*print_prefixes*/false); - } - asm_string = gb_string_appendc(asm_string, "("); - GB_ASSERT(mem_op->base != nullptr); - asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->base); - if (mem_op->index) { - asm_string = gb_string_appendc(asm_string, ","); - asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->index); - if (mem_op->scale) { - asm_string = gb_string_appendc(asm_string, ","); - asm_string = lb_asm_write_operand(asm_string, tmpl_entity, op_number, decls, mem_op->scale, /*print_prefixes*/false); + AsmTemplateEntityDecl *entity_op(Entity *parameter) { + for (AsmTemplateEntityDecl &op : *ops) { + if (op.entity == parameter) { + return &op; } } - asm_string = gb_string_appendc(asm_string, ")"); - case_end; + GB_PANIC("Could not find asm entity %s", LIT(parameter->token.string)); + return nullptr; + } - case_ast_node(bl, BasicLit, op); - ExactValue ev = op->tav.value; - GB_ASSERT(ev.kind != ExactValue_Invalid); - switch (ev.kind) { - case ExactValue_Integer: { - String s = big_int_to_string(heap_allocator(), &ev.value_integer, 10); - if (print_prefixes) { - asm_string = gb_string_appendc(asm_string, "$$"); + gbString write_operand(gbString asm_string, Array op_number, Ast *op, bool print_prefixes=true) { + switch (op->kind) { + case_ast_node(i, Ident, op); + Entity *e = entity_of_node(op); + auto *ed = entity_op(e); + + i32 idx = op_number[ed->total_index]; + GB_ASSERT(idx >= 0); + asm_string = gb_string_append_fmt(asm_string, "$%d", idx); + case_end; + case_ast_node(mem_op, AsmMemoryOperand, op); + asm_string = this->write_memory_operand(asm_string, op_number, mem_op, false); + case_end; + + case_ast_node(bl, BasicLit, op); + ExactValue ev = op->tav.value; + GB_ASSERT(ev.kind != ExactValue_Invalid); + switch (ev.kind) { + case ExactValue_Integer: { + String s = big_int_to_string(heap_allocator(), &ev.value_integer, 10); + if (print_prefixes) { + asm_string = gb_string_appendc(asm_string, "$$"); + } + asm_string = gb_string_append_length(asm_string, s.text, s.len); + gb_free(heap_allocator(), s.text); + break; } - asm_string = gb_string_append_length(asm_string, s.text, s.len); - gb_free(heap_allocator(), s.text); - break; - } + default: + GB_PANIC("Unsupported asm immediate literal %s", expr_to_string(op)); + break; + } + case_end; + + case_ast_node(label, AsmLabelDecl, op); + asm_string = write_label(asm_string, &label->name->Ident); + case_end; default: - GB_PANIC("Unsupported asm immediate literal %s", expr_to_string(op)); + GB_PANIC("TODO %s", expr_to_string(op)); break; } - case_end; - - case_ast_node(label, AsmLabelDecl, op); - asm_string = lb_asm_write_label_name(asm_string, tmpl_entity, &label->name->Ident); - case_end; - default: - GB_PANIC("TODO %s", expr_to_string(op)); - break; - } - return asm_string; -} - - -gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args) { - GB_ASSERT(entity != nullptr); - lbModule *m = p->module; - LLVMContextRef ctx = m->ctx; - - // Assumed frontend accessor: template string, flags, dialect, and the operand table. - auto &tmpl = entity->AsmTemplate; - Array &ops = tmpl.decls; - - TEMPORARY_ALLOCATOR_GUARD(); - - gbString asm_string = gb_string_make_reserve(temporary_allocator(), 64); - gbString constraints = gb_string_make_reserve(temporary_allocator(), 64); - - auto param_types = array_make(temporary_allocator(), 0, ops.count); - auto call_args = array_make(temporary_allocator(), 0, ops.count); - auto ret_types = array_make(temporary_allocator(), 0, ops.count); - - // Per-operand bookkeeping, indexed the same as `ops` (via total_index). - auto op_number = array_make(temporary_allocator(), ops.count, ops.count); // $N, or -1 for clobbers - auto ret_slot = array_make(temporary_allocator(), ops.count, ops.count); // return-struct index, or -1 - for_array(i, ops) { - op_number[i] = -1; - ret_slot[i] = -1; + return asm_string; } - // elementtype() attrs to attach after the call is built (indirect/memory operands). - struct ElemAttr { - unsigned arg_pos; - LLVMTypeRef elem; - }; - auto elem_attrs = array_make(temporary_allocator(), 0, ops.count); - - i32 next_op = 0; // running $N counter (outputs first, then inputs) - - auto sep = [&]() { - if (gb_string_length(constraints) != 0) { - constraints = gb_string_appendc(constraints, ","); - } - }; - auto raw = [&](char const *s) { - constraints = gb_string_appendc(constraints, s); - }; - auto put = [&](String s) { - constraints = gb_string_append_length(constraints, s.text, s.len); - }; - - auto class_letter = [&](AsmRegClass rc) -> char const * { + char const *class_letter(AsmRegClass rc) { switch (rc) { case AsmRegClass_Integer: return "r"; case AsmRegClass_Float: return "x"; // TODO(bill): target-dependent @@ -135,246 +87,323 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar } }; + // LLVM type of a returned register output, taken from the proc signature's results. - auto output_llvm_type = [&](AsmTemplateEntityDecl const &e) -> LLVMTypeRef { - Type *pt = base_type(entity->type); + LLVMTypeRef output_llvm_type(lbModule *m, AsmTemplateEntityDecl const &e) { + Type *pt = base_type(tmpl_entity->type); Type *rt = pt->Proc.results->Tuple.variables[e.result_index]->type; return lb_type(m, rt); }; - auto add_arg = [&](LLVMValueRef v) -> unsigned { - unsigned pos = cast(unsigned)call_args.count; - array_add(¶m_types, LLVMTypeOf(v)); - array_add(&call_args, v); - return pos; - }; - // Pass 1: outputs - // Real outputs plus *unpinned* register scratch (modeled as discarded - // early-clobber outputs, since a clobber can only name a fixed register). - for_array(i, ops) { - AsmTemplateEntityDecl const &e = ops[i]; + virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, bool print_prefixes=true) = 0; + virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; +}; - bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; - bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch - && e.kind == AsmTemplateEntityDecl_Register - && e.pin.len == 0; - if (!is_output && !is_alloc_scratch) { - continue; +struct lbAsmGenerate_amd64 : lbAsmGenerate { + gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, bool print_prefixes=true) override { + if (mem_op->disp) { + asm_string = this->write_operand(asm_string, op_number, mem_op->disp, /*print_prefixes*/false); } - - sep(); - - // Register output: '=' ['&'] ( '{pin}' | class-letter ) - raw("="); - if (is_alloc_scratch) { // early-clobber: keep scratch off any input reg - raw("&"); + asm_string = gb_string_appendc(asm_string, "("); + GB_ASSERT(mem_op->base != nullptr); + asm_string = this->write_operand(asm_string, op_number, mem_op->base); + if (mem_op->index) { + asm_string = gb_string_appendc(asm_string, ","); + asm_string = this->write_operand(asm_string, op_number, mem_op->index); + if (mem_op->scale) { + asm_string = gb_string_appendc(asm_string, ","); + asm_string = this->write_operand(asm_string, op_number, mem_op->scale, /*print_prefixes*/false); + } } - if (e.pin.len != 0) { - raw("{"); put(e.pin); raw("}"); - } else { - raw(class_letter(e.reg_class)); - } - - // Use the entity's real declared type so the return-struct slot matches - // the constraint's width/class (e.g. <4 x float> for a #simd[4]f32 scratch). - LLVMTypeRef ty = is_alloc_scratch ? lb_type(m, e.entity->type) : output_llvm_type(e); - - ret_slot[i] = cast(i32)ret_types.count; - array_add(&ret_types, ty); - op_number[i] = next_op++; + asm_string = gb_string_appendc(asm_string, ")"); + return asm_string; } - // Pass 2: inputs - for (isize i = 0; i < ops.count; i++) { - AsmTemplateEntityDecl const &e = ops[i]; - if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) { - continue; + lbValue emit_call(lbProcedure *p, Array const &args) override { + lbModule *m = p->module; + LLVMContextRef ctx = m->ctx; + + // Assumed frontend accessor: template string, flags, dialect, and the operand table. + TEMPORARY_ALLOCATOR_GUARD(); + + gbString asm_string = gb_string_make_reserve(temporary_allocator(), 64); + gbString constraints = gb_string_make_reserve(temporary_allocator(), 64); + + auto param_types = array_make(temporary_allocator(), 0, ops->count); + auto call_args = array_make(temporary_allocator(), 0, ops->count); + auto ret_types = array_make(temporary_allocator(), 0, ops->count); + + // Per-operand bookkeeping, indexed the same as `ops` (via total_index). + auto op_number = array_make(temporary_allocator(), ops->count, ops->count); // $N, or -1 for clobbers + auto ret_slot = array_make(temporary_allocator(), ops->count, ops->count); // return-struct index, or -1 + for_array(i, *ops) { + op_number[i] = -1; + ret_slot[i] = -1; } - sep(); - lbValue v = args[e.param_index]; + // elementtype() attrs to attach after the call is built (indirect/memory operands). + struct ElemAttr { + unsigned arg_pos; + LLVMTypeRef elem; + }; + auto elem_attrs = array_make(temporary_allocator(), 0, ops->count); - if (e.tie >= 0) { - // Tied read-write input: a matching constraint referencing the tied - // output's operand number (e.g. "0"). - i32 n = op_number[e.tie]; - GB_ASSERT(n >= 0); - constraints = gb_string_append_fmt(constraints, "%d", n); - add_arg(v.value); - } else { - switch (e.kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Memory: - if (e.pin.len != 0) { - raw("{"); put(e.pin); raw("}"); - } else { - raw(class_letter(e.reg_class)); + i32 next_op = 0; // running $N counter (outputs first, then inputs) + + auto sep = [&]() { + if (gb_string_length(constraints) != 0) { + constraints = gb_string_appendc(constraints, ","); + } + }; + auto raw = [&](char const *s) { + constraints = gb_string_appendc(constraints, s); + }; + auto put = [&](String s) { + constraints = gb_string_append_length(constraints, s.text, s.len); + }; + + auto add_arg = [&](LLVMValueRef v) -> unsigned { + unsigned pos = cast(unsigned)call_args.count; + array_add(¶m_types, LLVMTypeOf(v)); + array_add(&call_args, v); + return pos; + }; + + // Pass 1: outputs + // Real outputs plus *unpinned* register scratch (modeled as discarded + // early-clobber outputs, since a clobber can only name a fixed register). + for_array(i, *ops) { + AsmTemplateEntityDecl const &e = (*ops)[i]; + + bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; + bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch + && e.kind == AsmTemplateEntityDecl_Register + && e.pin.len == 0; + if (!is_output && !is_alloc_scratch) { + continue; + } + + sep(); + + // Register output: '=' ['&'] ( '{pin}' | class-letter ) + raw("="); + if (is_alloc_scratch) { // early-clobber: keep scratch off any input reg + raw("&"); + } + if (e.pin.len != 0) { + raw("{"); put(e.pin); raw("}"); + } else { + raw(this->class_letter(e.reg_class)); + } + + // Use the entity's real declared type so the return-struct slot matches + // the constraint's width/class (e.g. <4 x float> for a #simd[4]f32 scratch). + LLVMTypeRef ty = is_alloc_scratch ? lb_type(m, e.entity->type) : this->output_llvm_type(m, e); + + ret_slot[i] = cast(i32)ret_types.count; + array_add(&ret_types, ty); + op_number[i] = next_op++; + } + + // Pass 2: inputs + for (isize i = 0; i < ops->count; i++) { + AsmTemplateEntityDecl const &e = (*ops)[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) { + continue; + } + + sep(); + lbValue v = args[e.param_index]; + + if (e.tie >= 0) { + // Tied read-write input: a matching constraint referencing the tied + // output's operand number (e.g. "0"). + i32 n = op_number[e.tie]; + GB_ASSERT(n >= 0); + constraints = gb_string_append_fmt(constraints, "%d", n); + add_arg(v.value); + } else { + switch (e.kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Memory: + if (e.pin.len != 0) { + raw("{"); put(e.pin); raw("}"); + } else { + raw(this->class_letter(e.reg_class)); + } + add_arg(v.value); + break; + // case AsmTemplateEntityDecl_Memory: { + // raw("*m"); // indirect + // unsigned pos = add_arg(v.value); + // array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); + // break; + // } + case AsmTemplateEntityDecl_Immediate: + raw("i"); // TODO: "n" if a known-constant integer is required + add_arg(v.value); + break; + default: + GB_PANIC("asm: invalid input operand kind"); } - add_arg(v.value); + } + op_number[i] = next_op++; + } + + // Build the template text + for_array(i, tmpl_node->instructions) { + if (i > 0) { + asm_string = gb_string_appendc(asm_string, "\n"); + } + Ast *instr_ = tmpl_node->instructions[i]; + switch (instr_->kind) { + case_ast_node(instr, AsmInstruction, instr_); + asm_string = gb_string_appendc(asm_string, "\t"); + String name = instr->name->Ident.token.string; + asm_string = gb_string_append_length(asm_string, name.text, name.len); + asm_string = gb_string_appendc(asm_string, " "); + // Intel-source operand order reversed to AT&T (src, ..., dst). + for (isize j = instr->operands.count-1; j >= 0; j -= 1) { + Ast *op = instr->operands[j]; + if (j < instr->operands.count-1) { + asm_string = gb_string_appendc(asm_string, ", "); + } + asm_string = this->write_operand(asm_string, op_number, op); + } + case_end; + case_ast_node(label, AsmLabelDecl, instr_); + asm_string = this->write_label(asm_string, &label->name->Ident); + asm_string = gb_string_appendc(asm_string, ":"); + case_end; + default: + GB_PANIC("Invalid asm instruction"); break; - // case AsmTemplateEntityDecl_Memory: { - // raw("*m"); // indirect - // unsigned pos = add_arg(v.value); - // array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); - // break; - // } - case AsmTemplateEntityDecl_Immediate: - raw("i"); // TODO: "n" if a known-constant integer is required - add_arg(v.value); + } + } + + // Pass 3: clobbers + // Only the Scratch group. Unpinned register scratch was already emitted as an + // output in Pass 1, so it is skipped here. + for (isize i = 0; i < ops->count; i++) { + AsmTemplateEntityDecl const &e = (*ops)[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Scratch) { + continue; + } + if (e.kind == AsmTemplateEntityDecl_Register && e.pin.len == 0) { + continue; + } + + sep(); + switch (e.kind) { + case AsmTemplateEntityDecl_Register: // pinned -> real clobber + GB_ASSERT(e.pin.len != 0); + raw("~{"); put(e.pin); raw("}"); + break; + case AsmTemplateEntityDecl_Memory: // general memory clobber + raw("~{memory}"); break; default: - GB_PANIC("asm: invalid input operand kind"); + GB_PANIC("asm: invalid scratch operand kind"); } } - op_number[i] = next_op++; - } - // Build the template text - GB_ASSERT(tmpl.node->kind == Ast_AsmTemplate); - auto *node = &tmpl.node->AsmTemplate; - for_array(i, node->instructions) { - if (i > 0) { - asm_string = gb_string_appendc(asm_string, "\n"); + // Build the callee type + // NOTE(bill): Even though the user has given a signature, this might not actually match what + // LLVM requires it to be due to the scratch parameters and more, so many of the results might + // need to be completely ignored to match the user's given signature. + LLVMTypeRef ret_ty = nullptr; + if (ret_types.count == 0) { + ret_ty = LLVMVoidTypeInContext(ctx); + } else if (ret_types.count == 1) { + ret_ty = ret_types[0]; + } else { + ret_ty = LLVMStructTypeInContext(ctx, ret_types.data, cast(unsigned)ret_types.count, /*packed*/false); } - Ast *instr_ = node->instructions[i]; - switch (instr_->kind) { - case_ast_node(instr, AsmInstruction, instr_); - asm_string = gb_string_appendc(asm_string, "\t"); - String name = instr->name->Ident.token.string; - asm_string = gb_string_append_length(asm_string, name.text, name.len); - asm_string = gb_string_appendc(asm_string, " "); - // Intel-source operand order reversed to AT&T (src, ..., dst). - for (isize j = instr->operands.count-1; j >= 0; j -= 1) { - Ast *op = instr->operands[j]; - if (j < instr->operands.count-1) { - asm_string = gb_string_appendc(asm_string, ", "); - } - asm_string = lb_asm_write_operand(asm_string, entity, op_number, &ops, op); + + LLVMTypeRef fn_ty = LLVMFunctionType(ret_ty, param_types.data, cast(unsigned)param_types.count, /*vararg*/false); + + // TODO(bill): determine all the cases when side-effects happen + bool has_side_effects = tmpl_node->has_side_effects; + + LLVMValueRef ia = LLVMGetInlineAsm( + fn_ty, + asm_string, cast(size_t)gb_string_length(asm_string), + constraints, cast(size_t)gb_string_length(constraints), + /*HasSideEffects*/ has_side_effects, + /*IsAlignStack*/ tmpl_node->is_align_stack, + LLVMInlineAsmDialectATT, + /*CanThrow*/ false); + + LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); + + if (false) { + // DEBUG PRINT!!! + // DEBUG PRINT!!! + // DEBUG PRINT!!! + gb_printf_err("%s\n", asm_string); + char *ir = LLVMPrintValueToString(call); + gb_printf_err("%s\n\n", ir); + LLVMDisposeMessage(ir); + } + + // Attach elementtype() to every indirect operand's pointer arg (opaque-pointer requirement). + unsigned et_kind = LLVMGetEnumAttributeKindForName("elementtype", 11); + for (isize k = 0; k < elem_attrs.count; k++) { + LLVMAttributeRef attr = LLVMCreateTypeAttribute(ctx, et_kind, elem_attrs[k].elem); + LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attrs[k].arg_pos + 1), attr); + } + + // Repackage results in Odin result order + Type *pt = base_type(tmpl_entity->type); + isize result_count = (pt->Proc.results != nullptr) ? pt->Proc.results->Tuple.variables.count : 0; + if (result_count == 0) { + return lbValue{}; // void asm (memory outputs already wrote through their pointers) + } + + // The LLVM return struct is ordered by operand and includes scratch slots; + // pull out only the real register outputs and index them by result_index. + auto result_vals = array_make(temporary_allocator(), result_count, result_count); + for (isize i = 0; i < result_count; i++) { + result_vals[i] = nullptr; + } + + for (isize i = 0; i < ops->count; i++) { + AsmTemplateEntityDecl const &e = (*ops)[i]; + if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) { + continue; } - case_end; - case_ast_node(label, AsmLabelDecl, instr_); - asm_string = lb_asm_write_label_name(asm_string, entity, &label->name->Ident); - asm_string = gb_string_appendc(asm_string, ":"); - case_end; - default: - GB_PANIC("Invalid asm instruction"); - break; - } - } + if (e.result_index < 0) { + continue; // memory output: not a returned value + } + GB_ASSERT(ret_slot[i] >= 0); - // Pass 3: clobbers - // Only the Scratch group. Unpinned register scratch was already emitted as an - // output in Pass 1, so it is skipped here. - for (isize i = 0; i < ops.count; i++) { - AsmTemplateEntityDecl const &e = ops[i]; - if (e.param_group != AsmTemplateEntityDeclParamGroup_Scratch) { - continue; - } - if (e.kind == AsmTemplateEntityDecl_Register && e.pin.len == 0) { - continue; + LLVMValueRef v = (ret_types.count == 1) + ? call // single-element return is not a struct + : LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); + result_vals[e.result_index] = v; } - sep(); - switch (e.kind) { - case AsmTemplateEntityDecl_Register: // pinned -> real clobber - GB_ASSERT(e.pin.len != 0); - raw("~{"); put(e.pin); raw("}"); - break; - case AsmTemplateEntityDecl_Memory: // general memory clobber - raw("~{memory}"); - break; - default: - GB_PANIC("asm: invalid scratch operand kind"); + if (result_count == 1) { + Type *rt = pt->Proc.results->Tuple.variables[0]->type; + return lbValue{result_vals[0], rt}; } - } - // Build the callee type - // NOTE(bill): Even though the user has given a signature, this might not actually match what - // LLVM requires it to be due to the scratch parameters and more, so many of the results might - // need to be completely ignored to match the user's given signature. - LLVMTypeRef ret_ty = nullptr; - if (ret_types.count == 0) { - ret_ty = LLVMVoidTypeInContext(ctx); - } else if (ret_types.count == 1) { - ret_ty = ret_types[0]; - } else { - ret_ty = LLVMStructTypeInContext(ctx, ret_types.data, cast(unsigned)ret_types.count, /*packed*/false); - } - - LLVMTypeRef fn_ty = LLVMFunctionType(ret_ty, param_types.data, cast(unsigned)param_types.count, /*vararg*/false); - - // TODO(bill): determine all the cases when side-effects happen - bool has_side_effects = tmpl.has_side_effects; - - LLVMValueRef ia = LLVMGetInlineAsm( - fn_ty, - asm_string, cast(size_t)gb_string_length(asm_string), - constraints, cast(size_t)gb_string_length(constraints), - /*HasSideEffects*/ has_side_effects, - /*IsAlignStack*/ tmpl.is_align_stack, - LLVMInlineAsmDialectATT, - /*CanThrow*/ false); - - LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - - { // DEBUG PRINT!!! - // DEBUG PRINT!!! - // DEBUG PRINT!!! - // DEBUG PRINT!!! - gb_printf_err("%s\n", asm_string); - char *ir = LLVMPrintValueToString(call); - gb_printf_err("%s\n\n", ir); - LLVMDisposeMessage(ir); - } - - // Attach elementtype() to every indirect operand's pointer arg (opaque-pointer requirement). - unsigned et_kind = LLVMGetEnumAttributeKindForName("elementtype", 11); - for (isize k = 0; k < elem_attrs.count; k++) { - LLVMAttributeRef attr = LLVMCreateTypeAttribute(ctx, et_kind, elem_attrs[k].elem); - LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attrs[k].arg_pos + 1), attr); - } - - // Repackage results in Odin result order - Type *pt = base_type(entity->type); - isize result_count = (pt->Proc.results != nullptr) ? pt->Proc.results->Tuple.variables.count : 0; - if (result_count == 0) { - return lbValue{}; // void asm (memory outputs already wrote through their pointers) - } - - // The LLVM return struct is ordered by operand and includes scratch slots; - // pull out only the real register outputs and index them by result_index. - auto result_vals = array_make(temporary_allocator(), result_count, result_count); - for (isize i = 0; i < result_count; i++) result_vals[i] = nullptr; - - for (isize i = 0; i < ops.count; i++) { - AsmTemplateEntityDecl const &e = ops[i]; - if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) { - continue; + // Multiple results -> assemble Odin's result aggregate in result order. + Type *results_type = pt->Proc.results; + LLVMValueRef agg = LLVMGetUndef(lb_type(m, results_type)); + for (isize i = 0; i < result_count; i++) { + GB_ASSERT(result_vals[i] != nullptr); + agg = LLVMBuildInsertValue(p->builder, agg, result_vals[i], cast(unsigned)i, ""); } - if (e.result_index < 0) { - continue; // memory output: not a returned value - } - GB_ASSERT(ret_slot[i] >= 0); - LLVMValueRef v = (ret_types.count == 1) - ? call // single-element return is not a struct - : LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); - result_vals[e.result_index] = v; + return lbValue{agg, results_type}; } +}; - if (result_count == 1) { - Type *rt = pt->Proc.results->Tuple.variables[0]->type; - return lbValue{result_vals[0], rt}; - } - // Multiple results -> assemble Odin's result aggregate in result order. - Type *results_type = pt->Proc.results; - LLVMValueRef agg = LLVMGetUndef(lb_type(m, results_type)); - for (isize i = 0; i < result_count; i++) { - GB_ASSERT(result_vals[i] != nullptr); - agg = LLVMBuildInsertValue(p->builder, agg, result_vals[i], cast(unsigned)i, ""); - } - - return lbValue{agg, results_type}; +gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args) { + lbAsmGenerate_amd64 generator = {}; + generator.init(entity); + return generator.emit_call(p, args); } \ No newline at end of file From ebc21aad727bef8c80ba9162d90d54e403dfcd3d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 10 Aug 2026 13:50:15 +0100 Subject: [PATCH 10/92] Fix displacement check --- src/check_decl.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 2783e982d..51226c6ab 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2403,7 +2403,12 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti // Okay for now } else { Entity *param_entity = entity_of_node(disp.expr); - if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + if (disp.mode == Addressing_Constant) { + if (is_type_integer(disp.type)) { + break; + } + } + if (param_entity == nullptr) { gbString s = expr_to_string(disp.expr); error(disp.expr, "An displacement value must an integer, got %s", s); gb_string_free(s); @@ -2413,12 +2418,16 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti switch (kind) { case AsmTemplateEntityDecl_Register: case AsmTemplateEntityDecl_Immediate: - // okay: - break; + if (is_type_integer(disp.type)) { + break; + } + /*fallthrough*/ default: { gbString s = expr_to_string(disp.expr); - error(disp.expr, "An displacement must be an integer value, got %s", s); + gbString t = type_to_string(disp.type); + error(disp.expr, "An displacement must be an integer value, got %s of type %s", s, t); + gb_string_free(t); gb_string_free(s); } break; From 3f3e69897ad3c2ed283581847d2a005e26391241 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 10 Aug 2026 15:03:17 +0100 Subject: [PATCH 11/92] Check for duplicate register pinning --- src/check_decl.cpp | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 51226c6ab..8f6412b31 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2143,6 +2143,10 @@ gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array< gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { + StringSet pin_set = {}; + string_set_init(&pin_set, specs.count); + defer (string_set_destroy(&pin_set)); + for (Ast *spec_ : specs) { if (spec_->kind != Ast_AsmSpec) { continue; @@ -2169,6 +2173,11 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice if (pin == "any") { pin = {}; } + if (pin.len != 0) { + if (string_set_update(&pin_set, pin)) { + error(spec->value, "Pinned register %%%.*s has already be assigned", LIT(pin)); + } + } } if (spec->tied_name == nullptr) { @@ -2488,19 +2497,38 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); { // check clobbers + StringSet reg_set = {}; + string_set_init(®_set, 16); + defer (string_set_destroy(®_set)); + + bool clobber_cc = false; + bool clobber_memory = false; + for (Ast *clobber_ : at->clobbers) { ast_node(clobber, AsmClobber, clobber_); switch (clobber->value->kind) { case Ast_AsmRegister: - // TODO(bill): register check + { + String reg = clobber->value->AsmRegister.name.string; + if (string_set_update(®_set, reg)) { + error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); + } + // TODO(bill): register check for validity + } break; case Ast_Ident: { String str = clobber->value->Ident.token.string; if (str == "cc") { - // okay + if (clobber_cc) { + error(clobber->value, "#clobber cc has already been defined"); + } + clobber_cc = true; } else if (str == "memory") { - // okay + if (clobber_memory) { + error(clobber->value, "#clobber memory has already been defined"); + } + clobber_memory = true; } else { error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); } From d827be77cde75325ac7a7a05503b850af89837dd Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 10:02:23 +0100 Subject: [PATCH 12/92] Begin work on generating the AMD64 asm tables for C++ --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 780 ++++++++++++ src/array.cpp | 14 + src/asm_tables_amd64.cpp | 1067 +++++++++++++++++ src/main.cpp | 2 + 4 files changed, 1863 insertions(+) create mode 100644 core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin create mode 100644 src/asm_tables_amd64.cpp diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin new file mode 100644 index 000000000..3eb57294a --- /dev/null +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -0,0 +1,780 @@ +package cpp_gen + +import "base:intrinsics" +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:rexcode/isa/x86" + +import gen ".." + +ISA_NAME :: "amd64" + +main :: proc() { + raw_encode_runs := #load("../../tables/x86.encode_runs.bin", []x86.Encode_Run) + raw_encode_forms := #load("../../tables/x86.encode_forms.bin", []u8) + + sb := strings.builder_make() + + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Produces a C++ equivalent of the encoding table from core:rexcode written in Odin\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "// odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals\n") + strings.write_string(&sb, "//\n\n\n") + + + // strings.write_string(&sb, "struct Asm_a + fmt.sbprintf(&sb, "struct Asm_%s {{\n", ISA_NAME) + { + strings.write_string(&sb, "\tenum Mnemonic : u16 {\n") + defer strings.write_string(&sb, "\t};\n"); + + iota := 0 + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + assert(int(mnemonic) == iota) + fmt.sbprintf(&sb, "M_%s, ", mnemonic) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + iota += 1 + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n\n"); + strings.write_string(&sb, "\t\tMNEMONIC_COUNT\n"); + } + + strings.write_string(&sb, "\tstatic String const mnemonic_strings[MNEMONIC_COUNT];\n") + + { + strings.write_string(&sb, "\n"); + strings.write_string(&sb, "\t// Register classes (upper byte)\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_NONE = 0x000;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR64 = 0x100;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR32 = 0x200;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR16 = 0x300;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR8 = 0x400;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_XMM = 0x600;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_YMM = 0x700;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_ZMM = 0x800;\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_K = 0x900; // opmask\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_SEG = 0xA00; // segment\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_CR = 0xB00; // control\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_DR = 0xC00; // debug\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_BND = 0xD00; // bound\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_MM = 0xE00; // MMX\n") + strings.write_string(&sb, "\tstatic const u16 REG_CLASS_ST = 0xF00; // x87 FPU\n") + strings.write_string(&sb, "\n"); + { + count := uint(0) + ROW_COUNT :: 16 + strings.write_string(&sb, "\tenum Register : u16 {\n") + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + fmt.sbprintf(&sb, "REG_%s, ", reg) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\t\tREG_COUNT\n") + strings.write_string(&sb, "\t};\n") + } + } + + + strings.write_string(&sb, "\tstatic u16 const register_codes[REG_COUNT];\n") + strings.write_string(&sb, "\tstatic String const register_names[REG_COUNT];\n") + + strings.write_string(&sb, "\n\n") + { + strings.write_string(&sb, "\tenum OperandType : u8 {\n") + defer strings.write_string(&sb, "\t};\n") + for op in type_of(gen.Encoding{}.ops[0]) { + fmt.sbprintf(&sb, "\t\tOP_%s,\n", op) + } + + } + strings.write_string(&sb, "\n\n") + { + strings.write_string(&sb, "\tenum OperandEncoding : u8 {\n") + defer strings.write_string(&sb, "\t};\n") + for op in type_of(gen.Encoding{}.enc[0]) { + fmt.sbprintf(&sb, "\t\tENC_%s,\n", op) + } + + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\ttypedef u32 EncodingFlags; // cannot use a C++ bit field to due lack of portability\n") + strings.write_string(&sb, "\n") + { + defer strings.write_string(&sb, "\tGB_STATIC_ASSERT(gb_size_of(Encoding) == 16);\n") + + strings.write_string(&sb, "\t#pragma pack(push, 1)\n") + defer strings.write_string(&sb, "\t#pragma pack(pop)\n") + strings.write_string(&sb, "\tstruct Encoding {\n") + defer strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, "\t\tMnemonic mnemonic;\n") + strings.write_string(&sb, "\t\tOperandType ops[4];\n") + strings.write_string(&sb, "\t\tOperandEncoding enc[4];\n") + strings.write_string(&sb, "\t\tu8 opcode;\n") + strings.write_string(&sb, "\t\tu8 ext;\n") + strings.write_string(&sb, "\t\tEncodingFlags flags;\n") + + + strings.write_string(&sb, "\n") + Encoding_Flags :: type_of(gen.Encoding{}.flags) + + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "has_implicit") + strings.write_string(&sb, "\t\tbool has_implicit () const { ") + fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) + strings.write_string(&sb, " }\n") + } + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "explicit_count") + bit_size := intrinsics.type_field_bit_offset(Encoding_Flags, "explicit_count") + strings.write_string(&sb, "\t\tu8 explicit_count() const { ") + fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) + strings.write_string(&sb, " }\n") + } + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "op_count") + bit_size := intrinsics.type_field_bit_offset(Encoding_Flags, "op_count") + strings.write_string(&sb, "\t\tu8 op_count () const { ") + fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) + strings.write_string(&sb, " }\n") + } + } + strings.write_string(&sb, "\n\n") + { + strings.write_string(&sb, "\t// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.\n") + strings.write_string(&sb, "\tstruct EncodeRun {\n") + strings.write_string(&sb, "\t\tu32 start; // start index in ENCODE_FORMS\n") + strings.write_string(&sb, "\t\tu32 count; // number of forms for this mnemonic\n") + strings.write_string(&sb, "\t};\n") + } + + strings.write_string(&sb, "\n\n") + fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs[%d];\n", len(raw_encode_runs)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms[%d];\n", len(raw_encode_forms)) + + strings.write_string(&sb, "\tStringMap mnemonic_map;\n") + strings.write_string(&sb, "\tStringMap register_map;\n") + strings.write_string(&sb, "\tSlice ENCODE_RUNS;\n") + strings.write_string(&sb, "\tSlice ENCODE_FORMS;\n") + + { + strings.write_string(&sb, "\tbool init() {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tstring_map_init(&mnemonic_map, MNEMONIC_COUNT*2);\n") + strings.write_string(&sb, "\t\tfor (u16 m = M_INVALID; m < MNEMONIC_COUNT; m++) {\n") + strings.write_string(&sb, "\t\t\tstring_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m);\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\tstring_map_init(®ister_map, REG_COUNT*2);\n") + strings.write_string(&sb, "\t\tfor (u16 r = REG_INVALID; r < REG_COUNT; r++) {\n") + strings.write_string(&sb, "\t\t\tstring_map_set(®ister_map, register_names[r], cast(Register)r);\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn true;\n") + } + { + strings.write_string(&sb, "\tMnemonic lookup(String const &name) {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tMnemonic *found = string_map_get(&mnemonic_map, name);\n") + strings.write_string(&sb, "\t\treturn found ? *found : M_INVALID;\n") + } + { + strings.write_string(&sb, "\tSlice encoding_forms(Mnemonic m) const {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tEncodeRun r = ENCODE_RUNS[m];\n") + strings.write_string(&sb, "\t\treturn slice_lower_and_count(ENCODE_FORMS, r.start, r.count);\n") + } + { + strings.write_string(&sb, "\tu16 reg_class(Register r) const {\n") + strings.write_string(&sb, "\t\treturn 0xFF00 & cast(u16)r;\n") + strings.write_string(&sb, "\t}\n") + } + { + strings.write_string(&sb, "\t// size in bits for register\n") + strings.write_string(&sb, "\tu16 reg_size(Register r) const {\n") + strings.write_string(&sb, "\t\tswitch (reg_class(r)) {\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_GPR64: return 64;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_GPR32: return 32;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_GPR16: return 16;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_GPR8: return 8;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_GPR8H: return 8;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_XMM: return 128;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_YMM: return 256;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_ZMM: return 512;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_K: return 64;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_MM: return 64;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_ST: return 80;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_SEG: return 16;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_CR: return 64;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_DR: return 64;\n") + strings.write_string(&sb, "\t\tcase REG_CLASS_BND: return 128;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn 0;\n") + strings.write_string(&sb, "\t}\n") + } + + + + strings.write_string(&sb, "};\n") + + strings.write_string(&sb, "\n\n\n") + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::mnemonic_strings[Asm_{0:s}::MNEMONIC_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + iota := 0 + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if mnemonic == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else if mnemonic == .MOVSD_SSE { + strings.write_string(&sb, "str_lit(\"movsd\"), ") + } else { + str := strings.to_lower(reflect.enum_string(mnemonic)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + iota += 1 + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n"); + } + + { + fmt.sbprintf(&sb, "u16 const Asm_{0:s}::register_codes[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + fmt.sbprintf(&sb, "%d, ", REG_CODES[reg]) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n"); + } + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::register_names[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if reg == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else { + str := strings.to_lower(reflect.enum_string(reg)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n"); + } + + { + fmt.sbprintf(&sb, "Asm_{0:s}::EncodeRun const Asm_{0:s}::raw_encode_runs[{1:d}] = {{\n", ISA_NAME, len(raw_encode_runs)) + defer strings.write_string(&sb, "};\n"); + + ROW_COUNT :: 16 + count := 0 + for run in raw_encode_runs { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "{{% 4d, % 2d}}, ", run.start, run.count) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n"); + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_encode_forms[%d] = {{\n", ISA_NAME, len(raw_encode_forms)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_encode_forms { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n"); + } + + + + path := fmt.tprintf("%s/src/asm_tables_%s.cpp", ODIN_ROOT, ISA_NAME) + + if err := os.write_entire_file(path, strings.to_string(sb)); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", path, err) + os.exit(1) + } +} + + + + + +Register :: enum u16 { + INVALID, + RAX, + RCX, + RDX, + RBX, + RSP, + RBP, + RSI, + RDI, + R8, + R9, + R10, + R11, + R12, + R13, + R14, + R15, + EAX, + ECX, + EDX, + EBX, + ESP, + EBP, + ESI, + EDI, + R8D, + R9D, + R10D, + R11D, + R12D, + R13D, + R14D, + R15D, + AX, + CX, + DX, + BX, + SP, + BP, + SI, + DI, + R8W, + R9W, + R10W, + R11W, + R12W, + R13W, + R14W, + R15W, + AL, + CL, + DL, + BL, + SPL, + BPL, + SIL, + DIL, + R8B, + R9B, + R10B, + R11B, + R12B, + R13B, + R14B, + R15B, + AH, + CH, + DH, + BH, + XMM0, + XMM1, + XMM2, + XMM3, + XMM4, + XMM5, + XMM6, + XMM7, + XMM8, + XMM9, + XMM10, + XMM11, + XMM12, + XMM13, + XMM14, + XMM15, + XMM16, + XMM17, + XMM18, + XMM19, + XMM20, + XMM21, + XMM22, + XMM23, + XMM24, + XMM25, + XMM26, + XMM27, + XMM28, + XMM29, + XMM30, + XMM31, + YMM0, + YMM1, + YMM2, + YMM3, + YMM4, + YMM5, + YMM6, + YMM7, + YMM8, + YMM9, + YMM10, + YMM11, + YMM12, + YMM13, + YMM14, + YMM15, + YMM16, + YMM17, + YMM18, + YMM19, + YMM20, + YMM21, + YMM22, + YMM23, + YMM24, + YMM25, + YMM26, + YMM27, + YMM28, + YMM29, + YMM30, + YMM31, + ZMM0, + ZMM1, + ZMM2, + ZMM3, + ZMM4, + ZMM5, + ZMM6, + ZMM7, + ZMM8, + ZMM9, + ZMM10, + ZMM11, + ZMM12, + ZMM13, + ZMM14, + ZMM15, + ZMM16, + ZMM17, + ZMM18, + ZMM19, + ZMM20, + ZMM21, + ZMM22, + ZMM23, + ZMM24, + ZMM25, + ZMM26, + ZMM27, + ZMM28, + ZMM29, + ZMM30, + ZMM31, + K0, + K1, + K2, + K3, + K4, + K5, + K6, + K7, + ES, + CS, + SS, + DS, + FS, + GS, + CR0, + CR2, + CR3, + CR4, + CR8, + DR0, + DR1, + DR2, + DR3, + DR6, + DR7, + BND0, + BND1, + BND2, + BND3, + MM0, + MM1, + MM2, + MM3, + MM4, + MM5, + MM6, + MM7, + ST0, + ST1, + ST2, + ST3, + ST4, + ST5, + ST6, + ST7, + RIP, + +} + +@(rodata) +REG_CODES := [Register]x86.Register{ + .INVALID = 0, + + // GPR 64-bit + .RAX = x86.Register(x86.REG_GPR64 | 0), .RCX = x86.Register(x86.REG_GPR64 | 1), + .RDX = x86.Register(x86.REG_GPR64 | 2), .RBX = x86.Register(x86.REG_GPR64 | 3), + .RSP = x86.Register(x86.REG_GPR64 | 4), .RBP = x86.Register(x86.REG_GPR64 | 5), + .RSI = x86.Register(x86.REG_GPR64 | 6), .RDI = x86.Register(x86.REG_GPR64 | 7), + .R8 = x86.Register(x86.REG_GPR64 | 8), .R9 = x86.Register(x86.REG_GPR64 | 9), + .R10 = x86.Register(x86.REG_GPR64 | 10), .R11 = x86.Register(x86.REG_GPR64 | 11), + .R12 = x86.Register(x86.REG_GPR64 | 12), .R13 = x86.Register(x86.REG_GPR64 | 13), + .R14 = x86.Register(x86.REG_GPR64 | 14), .R15 = x86.Register(x86.REG_GPR64 | 15), + + // ----------------------------------------------------------------------------- + // SECTION: 1.3 GPR 32-bit Registers (EAX-R15D) + // ----------------------------------------------------------------------------- + + // GPR 32-bit + .EAX = x86.Register(x86.REG_GPR32 | 0), .ECX = x86.Register(x86.REG_GPR32 | 1), + .EDX = x86.Register(x86.REG_GPR32 | 2), .EBX = x86.Register(x86.REG_GPR32 | 3), + .ESP = x86.Register(x86.REG_GPR32 | 4), .EBP = x86.Register(x86.REG_GPR32 | 5), + .ESI = x86.Register(x86.REG_GPR32 | 6), .EDI = x86.Register(x86.REG_GPR32 | 7), + .R8D = x86.Register(x86.REG_GPR32 | 8), .R9D = x86.Register(x86.REG_GPR32 | 9), + .R10D = x86.Register(x86.REG_GPR32 | 10), .R11D = x86.Register(x86.REG_GPR32 | 11), + .R12D = x86.Register(x86.REG_GPR32 | 12), .R13D = x86.Register(x86.REG_GPR32 | 13), + .R14D = x86.Register(x86.REG_GPR32 | 14), .R15D = x86.Register(x86.REG_GPR32 | 15), + + // ----------------------------------------------------------------------------- + // SECTION: 1.4 GPR 16-bit Registers (AX-R15W) + // ----------------------------------------------------------------------------- + + // GPR 16-bit + .AX = x86.Register(x86.REG_GPR16 | 0), .CX = x86.Register(x86.REG_GPR16 | 1), + .DX = x86.Register(x86.REG_GPR16 | 2), .BX = x86.Register(x86.REG_GPR16 | 3), + .SP = x86.Register(x86.REG_GPR16 | 4), .BP = x86.Register(x86.REG_GPR16 | 5), + .SI = x86.Register(x86.REG_GPR16 | 6), .DI = x86.Register(x86.REG_GPR16 | 7), + .R8W = x86.Register(x86.REG_GPR16 | 8), .R9W = x86.Register(x86.REG_GPR16 | 9), + .R10W = x86.Register(x86.REG_GPR16 | 10), .R11W = x86.Register(x86.REG_GPR16 | 11), + .R12W = x86.Register(x86.REG_GPR16 | 12), .R13W = x86.Register(x86.REG_GPR16 | 13), + .R14W = x86.Register(x86.REG_GPR16 | 14), .R15W = x86.Register(x86.REG_GPR16 | 15), + + // ----------------------------------------------------------------------------- + // SECTION: 1.5 GPR 8-bit Registers (AL-R15B, AH-BH) + // ----------------------------------------------------------------------------- + + // GPR 8-bit (low) + .AL = x86.Register(x86.REG_GPR8 | 0), .CL = x86.Register(x86.REG_GPR8 | 1), + .DL = x86.Register(x86.REG_GPR8 | 2), .BL = x86.Register(x86.REG_GPR8 | 3), + .SPL = x86.Register(x86.REG_GPR8 | 4), .BPL = x86.Register(x86.REG_GPR8 | 5), + .SIL = x86.Register(x86.REG_GPR8 | 6), .DIL = x86.Register(x86.REG_GPR8 | 7), + .R8B = x86.Register(x86.REG_GPR8 | 8), .R9B = x86.Register(x86.REG_GPR8 | 9), + .R10B = x86.Register(x86.REG_GPR8 | 10), .R11B = x86.Register(x86.REG_GPR8 | 11), + .R12B = x86.Register(x86.REG_GPR8 | 12), .R13B = x86.Register(x86.REG_GPR8 | 13), + .R14B = x86.Register(x86.REG_GPR8 | 14), .R15B = x86.Register(x86.REG_GPR8 | 15), + + // GPR 8-bit (high) - no REX allowed with these + .AH = x86.Register(x86.REG_GPR8H | 4), .CH = x86.Register(x86.REG_GPR8H | 5), + .DH = x86.Register(x86.REG_GPR8H | 6), .BH = x86.Register(x86.REG_GPR8H | 7), + + // ----------------------------------------------------------------------------- + // SECTION: 1.6 XMM Registers (XMM0-XMM31) + // ----------------------------------------------------------------------------- + + // XMM (0-31) + .XMM0 = x86.Register(x86.REG_XMM | 0), .XMM1 = x86.Register(x86.REG_XMM | 1), + .XMM2 = x86.Register(x86.REG_XMM | 2), .XMM3 = x86.Register(x86.REG_XMM | 3), + .XMM4 = x86.Register(x86.REG_XMM | 4), .XMM5 = x86.Register(x86.REG_XMM | 5), + .XMM6 = x86.Register(x86.REG_XMM | 6), .XMM7 = x86.Register(x86.REG_XMM | 7), + .XMM8 = x86.Register(x86.REG_XMM | 8), .XMM9 = x86.Register(x86.REG_XMM | 9), + .XMM10 = x86.Register(x86.REG_XMM | 10), .XMM11 = x86.Register(x86.REG_XMM | 11), + .XMM12 = x86.Register(x86.REG_XMM | 12), .XMM13 = x86.Register(x86.REG_XMM | 13), + .XMM14 = x86.Register(x86.REG_XMM | 14), .XMM15 = x86.Register(x86.REG_XMM | 15), + .XMM16 = x86.Register(x86.REG_XMM | 16), .XMM17 = x86.Register(x86.REG_XMM | 17), + .XMM18 = x86.Register(x86.REG_XMM | 18), .XMM19 = x86.Register(x86.REG_XMM | 19), + .XMM20 = x86.Register(x86.REG_XMM | 20), .XMM21 = x86.Register(x86.REG_XMM | 21), + .XMM22 = x86.Register(x86.REG_XMM | 22), .XMM23 = x86.Register(x86.REG_XMM | 23), + .XMM24 = x86.Register(x86.REG_XMM | 24), .XMM25 = x86.Register(x86.REG_XMM | 25), + .XMM26 = x86.Register(x86.REG_XMM | 26), .XMM27 = x86.Register(x86.REG_XMM | 27), + .XMM28 = x86.Register(x86.REG_XMM | 28), .XMM29 = x86.Register(x86.REG_XMM | 29), + .XMM30 = x86.Register(x86.REG_XMM | 30), .XMM31 = x86.Register(x86.REG_XMM | 31), + + // ----------------------------------------------------------------------------- + // SECTION: 1.7 YMM Registers (YMM0-YMM31) + // ----------------------------------------------------------------------------- + + // YMM (0-31) + .YMM0 = x86.Register(x86.REG_YMM | 0), .YMM1 = x86.Register(x86.REG_YMM | 1), + .YMM2 = x86.Register(x86.REG_YMM | 2), .YMM3 = x86.Register(x86.REG_YMM | 3), + .YMM4 = x86.Register(x86.REG_YMM | 4), .YMM5 = x86.Register(x86.REG_YMM | 5), + .YMM6 = x86.Register(x86.REG_YMM | 6), .YMM7 = x86.Register(x86.REG_YMM | 7), + .YMM8 = x86.Register(x86.REG_YMM | 8), .YMM9 = x86.Register(x86.REG_YMM | 9), + .YMM10 = x86.Register(x86.REG_YMM | 10), .YMM11 = x86.Register(x86.REG_YMM | 11), + .YMM12 = x86.Register(x86.REG_YMM | 12), .YMM13 = x86.Register(x86.REG_YMM | 13), + .YMM14 = x86.Register(x86.REG_YMM | 14), .YMM15 = x86.Register(x86.REG_YMM | 15), + .YMM16 = x86.Register(x86.REG_YMM | 16), .YMM17 = x86.Register(x86.REG_YMM | 17), + .YMM18 = x86.Register(x86.REG_YMM | 18), .YMM19 = x86.Register(x86.REG_YMM | 19), + .YMM20 = x86.Register(x86.REG_YMM | 20), .YMM21 = x86.Register(x86.REG_YMM | 21), + .YMM22 = x86.Register(x86.REG_YMM | 22), .YMM23 = x86.Register(x86.REG_YMM | 23), + .YMM24 = x86.Register(x86.REG_YMM | 24), .YMM25 = x86.Register(x86.REG_YMM | 25), + .YMM26 = x86.Register(x86.REG_YMM | 26), .YMM27 = x86.Register(x86.REG_YMM | 27), + .YMM28 = x86.Register(x86.REG_YMM | 28), .YMM29 = x86.Register(x86.REG_YMM | 29), + .YMM30 = x86.Register(x86.REG_YMM | 30), .YMM31 = x86.Register(x86.REG_YMM | 31), + + // ----------------------------------------------------------------------------- + // SECTION: 1.8 ZMM Registers (ZMM0-ZMM31) + // ----------------------------------------------------------------------------- + + // ZMM (0-31) + .ZMM0 = x86.Register(x86.REG_ZMM | 0), .ZMM1 = x86.Register(x86.REG_ZMM | 1), + .ZMM2 = x86.Register(x86.REG_ZMM | 2), .ZMM3 = x86.Register(x86.REG_ZMM | 3), + .ZMM4 = x86.Register(x86.REG_ZMM | 4), .ZMM5 = x86.Register(x86.REG_ZMM | 5), + .ZMM6 = x86.Register(x86.REG_ZMM | 6), .ZMM7 = x86.Register(x86.REG_ZMM | 7), + .ZMM8 = x86.Register(x86.REG_ZMM | 8), .ZMM9 = x86.Register(x86.REG_ZMM | 9), + .ZMM10 = x86.Register(x86.REG_ZMM | 10), .ZMM11 = x86.Register(x86.REG_ZMM | 11), + .ZMM12 = x86.Register(x86.REG_ZMM | 12), .ZMM13 = x86.Register(x86.REG_ZMM | 13), + .ZMM14 = x86.Register(x86.REG_ZMM | 14), .ZMM15 = x86.Register(x86.REG_ZMM | 15), + .ZMM16 = x86.Register(x86.REG_ZMM | 16), .ZMM17 = x86.Register(x86.REG_ZMM | 17), + .ZMM18 = x86.Register(x86.REG_ZMM | 18), .ZMM19 = x86.Register(x86.REG_ZMM | 19), + .ZMM20 = x86.Register(x86.REG_ZMM | 20), .ZMM21 = x86.Register(x86.REG_ZMM | 21), + .ZMM22 = x86.Register(x86.REG_ZMM | 22), .ZMM23 = x86.Register(x86.REG_ZMM | 23), + .ZMM24 = x86.Register(x86.REG_ZMM | 24), .ZMM25 = x86.Register(x86.REG_ZMM | 25), + .ZMM26 = x86.Register(x86.REG_ZMM | 26), .ZMM27 = x86.Register(x86.REG_ZMM | 27), + .ZMM28 = x86.Register(x86.REG_ZMM | 28), .ZMM29 = x86.Register(x86.REG_ZMM | 29), + .ZMM30 = x86.Register(x86.REG_ZMM | 30), .ZMM31 = x86.Register(x86.REG_ZMM | 31), + + // ----------------------------------------------------------------------------- + // SECTION: 1.9 Opmask Registers (K0-K7) + // ----------------------------------------------------------------------------- + + // Opmask registers + .K0 = x86.Register(x86.REG_K | 0), .K1 = x86.Register(x86.REG_K | 1), + .K2 = x86.Register(x86.REG_K | 2), .K3 = x86.Register(x86.REG_K | 3), + .K4 = x86.Register(x86.REG_K | 4), .K5 = x86.Register(x86.REG_K | 5), + .K6 = x86.Register(x86.REG_K | 6), .K7 = x86.Register(x86.REG_K | 7), + + // ----------------------------------------------------------------------------- + // SECTION: 1.10 Segment Registers (ES-GS) + // ----------------------------------------------------------------------------- + + // Segment registers + .ES = x86.Register(x86.REG_SEG | 0), .CS = x86.Register(x86.REG_SEG | 1), + .SS = x86.Register(x86.REG_SEG | 2), .DS = x86.Register(x86.REG_SEG | 3), + .FS = x86.Register(x86.REG_SEG | 4), .GS = x86.Register(x86.REG_SEG | 5), + + // ----------------------------------------------------------------------------- + // SECTION: 1.11 Control and Debug Registers + // ----------------------------------------------------------------------------- + + // Control registers + .CR0 = x86.Register(x86.REG_CR | 0), .CR2 = x86.Register(x86.REG_CR | 2), + .CR3 = x86.Register(x86.REG_CR | 3), .CR4 = x86.Register(x86.REG_CR | 4), + .CR8 = x86.Register(x86.REG_CR | 8), + + // Debug registers + .DR0 = x86.Register(x86.REG_DR | 0), .DR1 = x86.Register(x86.REG_DR | 1), + .DR2 = x86.Register(x86.REG_DR | 2), .DR3 = x86.Register(x86.REG_DR | 3), + .DR6 = x86.Register(x86.REG_DR | 6), .DR7 = x86.Register(x86.REG_DR | 7), + + // ----------------------------------------------------------------------------- + // SECTION: 1.12 Other Registers (BND, MM, ST) + // ----------------------------------------------------------------------------- + + // Bound registers (MPX) + .BND0 = x86.Register(x86.REG_BND | 0), .BND1 = x86.Register(x86.REG_BND | 1), + .BND2 = x86.Register(x86.REG_BND | 2), .BND3 = x86.Register(x86.REG_BND | 3), + + // MMX registers + .MM0 = x86.Register(x86.REG_MM | 0), .MM1 = x86.Register(x86.REG_MM | 1), + .MM2 = x86.Register(x86.REG_MM | 2), .MM3 = x86.Register(x86.REG_MM | 3), + .MM4 = x86.Register(x86.REG_MM | 4), .MM5 = x86.Register(x86.REG_MM | 5), + .MM6 = x86.Register(x86.REG_MM | 6), .MM7 = x86.Register(x86.REG_MM | 7), + + // x87 FPU registers + .ST0 = x86.Register(x86.REG_ST | 0), .ST1 = x86.Register(x86.REG_ST | 1), + .ST2 = x86.Register(x86.REG_ST | 2), .ST3 = x86.Register(x86.REG_ST | 3), + .ST4 = x86.Register(x86.REG_ST | 4), .ST5 = x86.Register(x86.REG_ST | 5), + .ST6 = x86.Register(x86.REG_ST | 6), .ST7 = x86.Register(x86.REG_ST | 7), + + // Special: RIP for RIP-relative addressing + .RIP = x86.Register(0xFFFE), +} \ No newline at end of file diff --git a/src/array.cpp b/src/array.cpp index 9cf7c6ce3..5176f2511 100644 --- a/src/array.cpp +++ b/src/array.cpp @@ -187,6 +187,20 @@ gb_internal gb_inline Slice slice(Array const &array, isize lo, isize hi) return out; } +template +gb_internal gb_inline Slice slice_lower_and_count(Slice const &array, isize lo, isize count) { + GB_ASSERT(0 <= lo); + GB_ASSERT(0 <= count); + GB_ASSERT((array.count-lo) <= count); + Slice out = {}; + if (count > 0) { + out.data = array.data+lo; + out.count = count; + } + return out; +} + + template gb_internal void slice_ordered_remove(Slice *array, isize index) { diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp new file mode 100644 index 000000000..7dfcad374 --- /dev/null +++ b/src/asm_tables_amd64.cpp @@ -0,0 +1,1067 @@ +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Produces a C++ equivalent of the encoding table from core:rexcode written in Odin +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals +// + + +struct Asm_amd64 { + enum Mnemonic : u16 { + M_INVALID, M_MOV, M_MOVABS, M_MOVZX, M_MOVSX, M_MOVSXD, M_XCHG, M_PUSH, M_POP, M_LEA, M_ADD, M_ADC, M_SUB, M_SBB, M_MUL, M_IMUL, + M_DIV, M_IDIV, M_INC, M_DEC, M_NEG, M_CMP, M_AND, M_OR, M_XOR, M_NOT, M_TEST, M_SHL, M_SHR, M_SAR, M_ROL, M_ROR, + M_RCL, M_RCR, M_SHLD, M_SHRD, M_BT, M_BTS, M_BTR, M_BTC, M_BSF, M_BSR, M_POPCNT, M_LZCNT, M_TZCNT, M_JMP, M_JA, M_JAE, + M_JB, M_JBE, M_JC, M_JE, M_JZ, M_JG, M_JGE, M_JL, M_JLE, M_JNA, M_JNAE, M_JNB, M_JNBE, M_JNC, M_JNE, M_JNZ, + M_JNG, M_JNGE, M_JNL, M_JNLE, M_JNO, M_JNP, M_JNS, M_JO, M_JP, M_JPE, M_JPO, M_JS, M_JCXZ, M_JECXZ, M_JRCXZ, M_LOOP, + M_LOOPE, M_LOOPNE, M_CALL, M_RET, M_IRET, M_IRETD, M_IRETQ, M_INT, M_INT3, M_INTO, M_SYSCALL, M_SYSRET, M_SYSENTER, M_SYSEXIT, M_SETA, M_SETAE, + M_SETB, M_SETBE, M_SETC, M_SETE, M_SETG, M_SETGE, M_SETL, M_SETLE, M_SETNA, M_SETNAE, M_SETNB, M_SETNBE, M_SETNC, M_SETNE, M_SETNG, M_SETNGE, + M_SETNL, M_SETNLE, M_SETNO, M_SETNP, M_SETNS, M_SETNZ, M_SETO, M_SETP, M_SETPE, M_SETPO, M_SETS, M_SETZ, M_CMOVA, M_CMOVAE, M_CMOVB, M_CMOVBE, + M_CMOVC, M_CMOVE, M_CMOVG, M_CMOVGE, M_CMOVL, M_CMOVLE, M_CMOVNA, M_CMOVNAE, M_CMOVNB, M_CMOVNBE, M_CMOVNC, M_CMOVNE, M_CMOVNG, M_CMOVNGE, M_CMOVNL, M_CMOVNLE, + M_CMOVNO, M_CMOVNP, M_CMOVNS, M_CMOVNZ, M_CMOVO, M_CMOVP, M_CMOVPE, M_CMOVPO, M_CMOVS, M_CMOVZ, M_MOVS, M_MOVSB, M_MOVSW, M_MOVSD, M_MOVSQ, M_CMPS, + M_CMPSB, M_CMPSW, M_CMPSD, M_CMPSQ, M_SCAS, M_SCASB, M_SCASW, M_SCASD, M_SCASQ, M_LODS, M_LODSB, M_LODSW, M_LODSD, M_LODSQ, M_STOS, M_STOSB, + M_STOSW, M_STOSD, M_STOSQ, M_CLC, M_STC, M_CMC, M_CLD, M_STD, M_CLI, M_STI, M_LAHF, M_SAHF, M_PUSHF, M_PUSHFD, M_PUSHFQ, M_POPF, + M_POPFD, M_POPFQ, M_NOP, M_HLT, M_WAIT, M_LOCK, M_UD0, M_UD1, M_UD2, M_CPUID, M_RDTSC, M_RDTSCP, M_RDPMC, M_XGETBV, M_XSETBV, M_CBW, + M_CWDE, M_CDQE, M_CWD, M_CDQ, M_CQO, M_ANDN, M_BEXTR, M_BLSI, M_BLSMSK, M_BLSR, M_BZHI, M_PDEP, M_PEXT, M_RORX, M_SARX, M_SHLX, + M_SHRX, M_MULX, M_ADCX, M_ADOX, M_MOVAPS, M_MOVUPS, M_MOVAPD, M_MOVUPD, M_MOVSS, M_MOVSD_SSE, M_MOVDQA, M_MOVDQU, M_MOVQ, M_MOVD, M_MOVLPS, M_MOVHPS, + M_MOVLPD, M_MOVHPD, M_MOVLHPS, M_MOVHLPS, M_MOVMSKPS, M_MOVMSKPD, M_MOVNTPS, M_MOVNTPD, M_MOVNTDQ, M_MOVNTDQA, M_ADDPS, M_ADDPD, M_ADDSS, M_ADDSD, M_SUBPS, M_SUBPD, + M_SUBSS, M_SUBSD, M_MULPS, M_MULPD, M_MULSS, M_MULSD, M_DIVPS, M_DIVPD, M_DIVSS, M_DIVSD, M_SQRTPS, M_SQRTPD, M_SQRTSS, M_SQRTSD, M_RCPPS, M_RCPSS, + M_RSQRTPS, M_RSQRTSS, M_MAXPS, M_MAXPD, M_MAXSS, M_MAXSD, M_MINPS, M_MINPD, M_MINSS, M_MINSD, M_ANDPS, M_ANDPD, M_ANDNPS, M_ANDNPD, M_ORPS, M_ORPD, + M_XORPS, M_XORPD, M_CMPPS, M_CMPPD, M_CMPSS, M_CMPSD_SSE, M_COMISS, M_COMISD, M_UCOMISS, M_UCOMISD, M_SHUFPS, M_SHUFPD, M_UNPCKLPS, M_UNPCKHPS, M_UNPCKLPD, M_UNPCKHPD, + M_CVTPS2PD, M_CVTPD2PS, M_CVTSS2SD, M_CVTSD2SS, M_CVTPS2DQ, M_CVTPD2DQ, M_CVTDQ2PS, M_CVTDQ2PD, M_CVTSS2SI, M_CVTSD2SI, M_CVTSI2SS, M_CVTSI2SD, M_CVTTPS2DQ, M_CVTTPD2DQ, M_CVTTSS2SI, M_CVTTSD2SI, + M_PADDB, M_PADDW, M_PADDD, M_PADDQ, M_PSUBB, M_PSUBW, M_PSUBD, M_PSUBQ, M_PADDSB, M_PADDSW, M_PADDUSB, M_PADDUSW, M_PSUBSB, M_PSUBSW, M_PSUBUSB, M_PSUBUSW, + M_PMULLW, M_PMULHW, M_PMULHUW, M_PMULUDQ, M_PMADDWD, M_PAND, M_PANDN, M_POR, M_PXOR, M_PSLLW, M_PSLLD, M_PSLLQ, M_PSRLW, M_PSRLD, M_PSRLQ, M_PSRAW, + M_PSRAD, M_PCMPEQB, M_PCMPEQW, M_PCMPEQD, M_PCMPGTB, M_PCMPGTW, M_PCMPGTD, M_PACKSSWB, M_PACKSSDW, M_PACKUSWB, M_PUNPCKLBW, M_PUNPCKLWD, M_PUNPCKLDQ, M_PUNPCKLQDQ, M_PUNPCKHBW, M_PUNPCKHWD, + M_PUNPCKHDQ, M_PUNPCKHQDQ, M_PSHUFD, M_PSHUFHW, M_PSHUFLW, M_PSHUFW, M_PEXTRW, M_PINSRW, M_PMOVMSKB, M_PAVGB, M_PAVGW, M_PMAXUB, M_PMAXSW, M_PMINUB, M_PMINSW, M_PSADBW, + M_MASKMOVDQU, M_LFENCE, M_SFENCE, M_MFENCE, M_PAUSE, M_CLFLUSH, M_ADDSUBPS, M_ADDSUBPD, M_HADDPS, M_HADDPD, M_HSUBPS, M_HSUBPD, M_MOVDDUP, M_MOVSLDUP, M_MOVSHDUP, M_LDDQU, + M_PSHUFB, M_PHADDW, M_PHADDD, M_PHADDSW, M_PHSUBW, M_PHSUBD, M_PHSUBSW, M_PMADDUBSW, M_PMULHRSW, M_PSIGNB, M_PSIGNW, M_PSIGND, M_PABSB, M_PABSW, M_PABSD, M_PALIGNR, + M_BLENDPS, M_BLENDPD, M_BLENDVPS, M_BLENDVPD, M_PBLENDW, M_PBLENDVB, M_DPPS, M_DPPD, M_EXTRACTPS, M_INSERTPS, M_MPSADBW, M_PACKUSDW, M_PEXTRB, M_PEXTRD, M_PEXTRQ, M_PHMINPOSUW, + M_PINSRB, M_PINSRD, M_PINSRQ, M_PMAXSB, M_PMAXSD, M_PMAXUW, M_PMAXUD, M_PMINSB, M_PMINSD, M_PMINUW, M_PMINUD, M_PMOVSXBW, M_PMOVSXBD, M_PMOVSXBQ, M_PMOVSXWD, M_PMOVSXWQ, + M_PMOVSXDQ, M_PMOVZXBW, M_PMOVZXBD, M_PMOVZXBQ, M_PMOVZXWD, M_PMOVZXWQ, M_PMOVZXDQ, M_PMULDQ, M_PMULLD, M_PTEST, M_ROUNDPS, M_ROUNDPD, M_ROUNDSS, M_ROUNDSD, M_PCMPEQQ, M_CRC32, + M_PCMPESTRI, M_PCMPESTRM, M_PCMPISTRI, M_PCMPISTRM, M_PCMPGTQ, M_PCLMULQDQ, M_AESDEC, M_AESDECLAST, M_AESENC, M_AESENCLAST, M_AESIMC, M_AESKEYGENASSIST, M_SHA1MSG1, M_SHA1MSG2, M_SHA1NEXTE, M_SHA1RNDS4, + M_SHA256MSG1, M_SHA256MSG2, M_SHA256RNDS2, M_VADDPS, M_VADDPD, M_VADDSS, M_VADDSD, M_VSUBPS, M_VSUBPD, M_VSUBSS, M_VSUBSD, M_VMULPS, M_VMULPD, M_VMULSS, M_VMULSD, M_VDIVPS, + M_VDIVPD, M_VDIVSS, M_VDIVSD, M_VSQRTPS, M_VSQRTPD, M_VSQRTSS, M_VSQRTSD, M_VRCPPS, M_VRCPSS, M_VRSQRTPS, M_VRSQRTSS, M_VMAXPS, M_VMAXPD, M_VMAXSS, M_VMAXSD, M_VMINPS, + M_VMINPD, M_VMINSS, M_VMINSD, M_VANDPS, M_VANDPD, M_VANDNPS, M_VANDNPD, M_VORPS, M_VORPD, M_VXORPS, M_VXORPD, M_VCMPPS, M_VCMPPD, M_VCMPSS, M_VCMPSD, M_VCOMISS, + M_VCOMISD, M_VUCOMISS, M_VUCOMISD, M_VSHUFPS, M_VSHUFPD, M_VUNPCKLPS, M_VUNPCKHPS, M_VUNPCKLPD, M_VUNPCKHPD, M_VBLENDPS, M_VBLENDPD, M_VBLENDVPS, M_VBLENDVPD, M_VDPPS, M_VDPPD, M_VROUNDPS, + M_VROUNDPD, M_VROUNDSS, M_VROUNDSD, M_VEXTRACTPS, M_VINSERTPS, M_VMOVAPS, M_VMOVUPS, M_VMOVAPD, M_VMOVUPD, M_VMOVSS, M_VMOVSD, M_VMOVDQA, M_VMOVDQU, M_VMOVQ, M_VMOVD, M_VMOVLPS, + M_VMOVHPS, M_VMOVLPD, M_VMOVHPD, M_VMOVLHPS, M_VMOVHLPS, M_VMOVMSKPS, M_VMOVMSKPD, M_VMOVNTPS, M_VMOVNTPD, M_VMOVNTDQ, M_VMOVNTDQA, M_VCVTPS2PD, M_VCVTPD2PS, M_VCVTSS2SD, M_VCVTSD2SS, M_VCVTPS2DQ, + M_VCVTPD2DQ, M_VCVTDQ2PS, M_VCVTDQ2PD, M_VCVTSS2SI, M_VCVTSD2SI, M_VCVTSI2SS, M_VCVTSI2SD, M_VCVTTPS2DQ, M_VCVTTPD2DQ, M_VCVTTSS2SI, M_VCVTTSD2SI, M_VPADDB, M_VPADDW, M_VPADDD, M_VPADDQ, M_VPSUBB, + M_VPSUBW, M_VPSUBD, M_VPSUBQ, M_VPMULLW, M_VPMULHW, M_VPMULHUW, M_VPMULUDQ, M_VPMADDWD, M_VPAND, M_VPANDN, M_VPOR, M_VPXOR, M_VPSLLW, M_VPSLLD, M_VPSLLQ, M_VPSRLW, + M_VPSRLD, M_VPSRLQ, M_VPSRAW, M_VPSRAD, M_VPCMPEQB, M_VPCMPEQW, M_VPCMPEQD, M_VPCMPEQQ, M_VPCMPGTB, M_VPCMPGTW, M_VPCMPGTD, M_VPCMPGTQ, M_VPACKSSWB, M_VPACKSSDW, M_VPACKUSWB, M_VPACKUSDW, + M_VPUNPCKLBW, M_VPUNPCKLWD, M_VPUNPCKLDQ, M_VPUNPCKLQDQ, M_VPUNPCKHBW, M_VPUNPCKHWD, M_VPUNPCKHDQ, M_VPUNPCKHQDQ, M_VPSHUFD, M_VPSHUFHW, M_VPSHUFLW, M_VPEXTRB, M_VPEXTRW, M_VPEXTRD, M_VPEXTRQ, M_VPINSRB, + M_VPINSRW, M_VPINSRD, M_VPINSRQ, M_VPMOVMSKB, M_VPTEST, M_VPSHUFB, M_VPHADDW, M_VPHADDD, M_VPHADDSW, M_VPHSUBW, M_VPHSUBD, M_VPHSUBSW, M_VPMADDUBSW, M_VPMULHRSW, M_VPSIGNB, M_VPSIGNW, + M_VPSIGND, M_VPABSB, M_VPABSW, M_VPABSD, M_VPALIGNR, M_VPBLENDW, M_VPBLENDVB, M_VMPSADBW, M_VPHMINPOSUW, M_VPMAXSB, M_VPMAXSD, M_VPMAXUW, M_VPMAXUD, M_VPMINSB, M_VPMINSD, M_VPMINUW, + M_VPMINUD, M_VPMOVSXBW, M_VPMOVSXBD, M_VPMOVSXBQ, M_VPMOVSXWD, M_VPMOVSXWQ, M_VPMOVSXDQ, M_VPMOVZXBW, M_VPMOVZXBD, M_VPMOVZXBQ, M_VPMOVZXWD, M_VPMOVZXWQ, M_VPMOVZXDQ, M_VPMULDQ, M_VPMULLD, M_VMASKMOVDQU, + M_VPCLMULQDQ, M_VAESDEC, M_VAESDECLAST, M_VAESENC, M_VAESENCLAST, M_VAESIMC, M_VAESKEYGENASSIST, M_VBROADCASTSS, M_VBROADCASTSD, M_VBROADCASTF128, M_VEXTRACTF128, M_VINSERTF128, M_VPERM2F128, M_VMASKMOVPS, M_VMASKMOVPD, M_VTESTPS, + M_VTESTPD, M_VZEROALL, M_VZEROUPPER, M_VBROADCASTI128, M_VEXTRACTI128, M_VINSERTI128, M_VPERM2I128, M_VPERMD, M_VPERMPS, M_VPERMQ, M_VPERMPD, M_VPBLENDD, M_VPSLLVD, M_VPSLLVQ, M_VPSRLVD, M_VPSRLVQ, + M_VPSRAVD, M_VPMASKMOVD, M_VPMASKMOVQ, M_VGATHERDPS, M_VGATHERDPD, M_VGATHERQPS, M_VGATHERQPD, M_VPGATHERDD, M_VPGATHERDQ, M_VPGATHERQD, M_VPGATHERQQ, M_VFMADD132PS, M_VFMADD213PS, M_VFMADD231PS, M_VFMADD132PD, M_VFMADD213PD, + M_VFMADD231PD, M_VFMADD132SS, M_VFMADD213SS, M_VFMADD231SS, M_VFMADD132SD, M_VFMADD213SD, M_VFMADD231SD, M_VFMSUB132PS, M_VFMSUB213PS, M_VFMSUB231PS, M_VFMSUB132PD, M_VFMSUB213PD, M_VFMSUB231PD, M_VFMSUB132SS, M_VFMSUB213SS, M_VFMSUB231SS, + M_VFMSUB132SD, M_VFMSUB213SD, M_VFMSUB231SD, M_VFNMADD132PS, M_VFNMADD213PS, M_VFNMADD231PS, M_VFNMADD132PD, M_VFNMADD213PD, M_VFNMADD231PD, M_VFNMADD132SS, M_VFNMADD213SS, M_VFNMADD231SS, M_VFNMADD132SD, M_VFNMADD213SD, M_VFNMADD231SD, M_VFNMSUB132PS, + M_VFNMSUB213PS, M_VFNMSUB231PS, M_VFNMSUB132PD, M_VFNMSUB213PD, M_VFNMSUB231PD, M_VFNMSUB132SS, M_VFNMSUB213SS, M_VFNMSUB231SS, M_VFNMSUB132SD, M_VFNMSUB213SD, M_VFNMSUB231SD, M_VFMADDSUB132PS, M_VFMADDSUB213PS, M_VFMADDSUB231PS, M_VFMADDSUB132PD, M_VFMADDSUB213PD, + M_VFMADDSUB231PD, M_VFMSUBADD132PS, M_VFMSUBADD213PS, M_VFMSUBADD231PS, M_VFMSUBADD132PD, M_VFMSUBADD213PD, M_VFMSUBADD231PD, M_VCVTPH2PS, M_VCVTPS2PH, M_VMOVDQA32, M_VMOVDQA64, M_VMOVDQU8, M_VMOVDQU16, M_VMOVDQU32, M_VMOVDQU64, M_VPBLENDMB, + M_VPBLENDMW, M_VPBLENDMD, M_VPBLENDMQ, M_VBLENDMPS, M_VBLENDMPD, M_VPCMPB, M_VPCMPUB, M_VPCMPW, M_VPCMPUW, M_VPCMPD, M_VPCMPUD, M_VPCMPQ, M_VPCMPUQ, M_VPTESTMB, M_VPTESTMW, M_VPTESTMD, + M_VPTESTMQ, M_VPTESTNMB, M_VPTESTNMW, M_VPTESTNMD, M_VPTESTNMQ, M_VPCOMPRESSD, M_VPCOMPRESSQ, M_VCOMPRESSPS, M_VCOMPRESSPD, M_VPEXPANDD, M_VPEXPANDQ, M_VEXPANDPS, M_VEXPANDPD, M_VPCONFLICTD, M_VPCONFLICTQ, M_VPLZCNTD, + M_VPLZCNTQ, M_VPERMI2B, M_VPERMI2W, M_VPERMI2D, M_VPERMI2Q, M_VPERMI2PS, M_VPERMI2PD, M_VPERMT2B, M_VPERMT2W, M_VPERMT2D, M_VPERMT2Q, M_VPERMT2PS, M_VPERMT2PD, M_VPERMB, M_VPERMW, M_VPMOVB2M, + M_VPMOVW2M, M_VPMOVD2M, M_VPMOVQ2M, M_VPMOVM2B, M_VPMOVM2W, M_VPMOVM2D, M_VPMOVM2Q, M_VPMOVQB, M_VPMOVSQB, M_VPMOVUSQB, M_VPMOVQW, M_VPMOVSQW, M_VPMOVUSQW, M_VPMOVQD, M_VPMOVSQD, M_VPMOVUSQD, + M_VPMOVDB, M_VPMOVSDB, M_VPMOVUSDB, M_VPMOVDW, M_VPMOVSDW, M_VPMOVUSDW, M_VPMOVWB, M_VPMOVSWB, M_VPMOVUSWB, M_VPROLD, M_VPROLQ, M_VPROLVD, M_VPROLVQ, M_VPRORD, M_VPRORQ, M_VPRORVD, + M_VPRORVQ, M_VPSCATTERDD, M_VPSCATTERDQ, M_VPSCATTERQD, M_VPSCATTERQQ, M_VSCATTERDPS, M_VSCATTERDPD, M_VSCATTERQPS, M_VSCATTERQPD, M_VPSRAVQ, M_VPSRAVW, M_VPSLLVW, M_VPSRLVW, M_VRANGEPS, M_VRANGEPD, M_VRANGESS, + M_VRANGESD, M_VREDUCEPS, M_VREDUCEPD, M_VREDUCESS, M_VREDUCESD, M_VRNDSCALEPS, M_VRNDSCALEPD, M_VRNDSCALESS, M_VRNDSCALESD, M_VRSQRT14PS, M_VRSQRT14PD, M_VRSQRT14SS, M_VRSQRT14SD, M_VRCP14PS, M_VRCP14PD, M_VRCP14SS, + M_VRCP14SD, M_VSCALEFPS, M_VSCALEFPD, M_VSCALEFSS, M_VSCALEFSD, M_VGETEXPPS, M_VGETEXPPD, M_VGETEXPSS, M_VGETEXPSD, M_VGETMANTPS, M_VGETMANTPD, M_VGETMANTSS, M_VGETMANTSD, M_VFIXUPIMMPS, M_VFIXUPIMMPD, M_VFIXUPIMMSS, + M_VFIXUPIMMSD, M_VFPCLASSPS, M_VFPCLASSPD, M_VFPCLASSSS, M_VFPCLASSSD, M_VALIGNQ, M_VALIGND, M_VDBPSADBW, M_VPTERNLOGD, M_VPTERNLOGQ, M_VPMULTISHIFTQB, M_KADDW, M_KADDB, M_KADDQ, M_KADDD, M_KANDW, + M_KANDB, M_KANDQ, M_KANDD, M_KANDNW, M_KANDNB, M_KANDNQ, M_KANDND, M_KMOVW, M_KMOVB, M_KMOVQ, M_KMOVD, M_KNOTW, M_KNOTB, M_KNOTQ, M_KNOTD, M_KORW, + M_KORB, M_KORQ, M_KORD, M_KORTESTW, M_KORTESTB, M_KORTESTQ, M_KORTESTD, M_KSHIFTLW, M_KSHIFTLB, M_KSHIFTLQ, M_KSHIFTLD, M_KSHIFTRW, M_KSHIFTRB, M_KSHIFTRQ, M_KSHIFTRD, M_KTESTW, + M_KTESTB, M_KTESTQ, M_KTESTD, M_KUNPCKBW, M_KUNPCKWD, M_KUNPCKDQ, M_KXNORW, M_KXNORB, M_KXNORQ, M_KXNORD, M_KXORW, M_KXORB, M_KXORQ, M_KXORD, M_FADD, M_FADDP, + M_FIADD, M_FSUB, M_FSUBP, M_FISUB, M_FSUBR, M_FSUBRP, M_FISUBR, M_FMUL, M_FMULP, M_FIMUL, M_FDIV, M_FDIVP, M_FIDIV, M_FDIVR, M_FDIVRP, M_FIDIVR, + M_FSQRT, M_FABS, M_FCHS, M_FPREM, M_FPREM1, M_FRNDINT, M_FSCALE, M_FXTRACT, M_FXAM, M_FLD, M_FILD, M_FBLD, M_FST, M_FSTP, M_FIST, M_FISTP, + M_FISTTP, M_FBSTP, M_FXCH, M_FCMOVB, M_FCMOVE, M_FCMOVBE, M_FCMOVU, M_FCMOVNB, M_FCMOVNE, M_FCMOVNBE, M_FCMOVNU, M_FCOM, M_FCOMP, M_FCOMPP, M_FICOM, M_FICOMP, + M_FCOMI, M_FCOMIP, M_FUCOMI, M_FUCOMIP, M_FUCOM, M_FUCOMP, M_FUCOMPP, M_FTST, M_FLDZ, M_FLD1, M_FLDPI, M_FLDL2T, M_FLDL2E, M_FLDLG2, M_FLDLN2, M_FSIN, + M_FCOS, M_FSINCOS, M_FPTAN, M_FPATAN, M_F2XM1, M_FYL2X, M_FYL2XP1, M_FINIT, M_FNINIT, M_FINCSTP, M_FDECSTP, M_FFREE, M_FFREEP, M_FNOP, M_FWAIT, M_FCLEX, + M_FNCLEX, M_FSTCW, M_FNSTCW, M_FLDCW, M_FSTENV, M_FNSTENV, M_FLDENV, M_FSAVE, M_FNSAVE, M_FRSTOR, M_FSTSW, M_FNSTSW, M_FXSAVE, M_FXSAVE64, M_FXRSTOR, M_FXRSTOR64, + M_LGDT, M_SGDT, M_LIDT, M_SIDT, M_LLDT, M_SLDT, M_LTR, M_STR, M_LMSW, M_SMSW, M_CLTS, M_ARPL, M_LAR, M_LSL, M_VERR, M_VERW, + M_INVD, M_WBINVD, M_INVLPG, M_INVPCID, M_RSM, M_RDMSR, M_WRMSR, M_VMCALL, M_VMLAUNCH, M_VMRESUME, M_VMXOFF, M_VMXON, M_VMCLEAR, M_VMPTRLD, M_VMPTRST, M_VMREAD, + M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, M_RSTORSSP, M_WRSSD, + M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, M_XSAVEC64, M_XSAVES, + M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, M_CMPXCHG16B, M_XADD, + M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, + + MNEMONIC_COUNT + }; + static String const mnemonic_strings[MNEMONIC_COUNT]; + + // Register classes (upper byte) + static const u16 REG_CLASS_NONE = 0x000; + static const u16 REG_CLASS_GPR64 = 0x100; + static const u16 REG_CLASS_GPR32 = 0x200; + static const u16 REG_CLASS_GPR16 = 0x300; + static const u16 REG_CLASS_GPR8 = 0x400; + static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs + static const u16 REG_CLASS_XMM = 0x600; + static const u16 REG_CLASS_YMM = 0x700; + static const u16 REG_CLASS_ZMM = 0x800; + static const u16 REG_CLASS_K = 0x900; // opmask + static const u16 REG_CLASS_SEG = 0xA00; // segment + static const u16 REG_CLASS_CR = 0xB00; // control + static const u16 REG_CLASS_DR = 0xC00; // debug + static const u16 REG_CLASS_BND = 0xD00; // bound + static const u16 REG_CLASS_MM = 0xE00; // MMX + static const u16 REG_CLASS_ST = 0xF00; // x87 FPU + + enum Register : u16 { + REG_INVALID, REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, + REG_R15, REG_EAX, REG_ECX, REG_EDX, REG_EBX, REG_ESP, REG_EBP, REG_ESI, REG_EDI, REG_R8D, REG_R9D, REG_R10D, REG_R11D, REG_R12D, REG_R13D, REG_R14D, + REG_R15D, REG_AX, REG_CX, REG_DX, REG_BX, REG_SP, REG_BP, REG_SI, REG_DI, REG_R8W, REG_R9W, REG_R10W, REG_R11W, REG_R12W, REG_R13W, REG_R14W, + REG_R15W, REG_AL, REG_CL, REG_DL, REG_BL, REG_SPL, REG_BPL, REG_SIL, REG_DIL, REG_R8B, REG_R9B, REG_R10B, REG_R11B, REG_R12B, REG_R13B, REG_R14B, + REG_R15B, REG_AH, REG_CH, REG_DH, REG_BH, REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7, REG_XMM8, REG_XMM9, REG_XMM10, + REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15, REG_XMM16, REG_XMM17, REG_XMM18, REG_XMM19, REG_XMM20, REG_XMM21, REG_XMM22, REG_XMM23, REG_XMM24, REG_XMM25, REG_XMM26, + REG_XMM27, REG_XMM28, REG_XMM29, REG_XMM30, REG_XMM31, REG_YMM0, REG_YMM1, REG_YMM2, REG_YMM3, REG_YMM4, REG_YMM5, REG_YMM6, REG_YMM7, REG_YMM8, REG_YMM9, REG_YMM10, + REG_YMM11, REG_YMM12, REG_YMM13, REG_YMM14, REG_YMM15, REG_YMM16, REG_YMM17, REG_YMM18, REG_YMM19, REG_YMM20, REG_YMM21, REG_YMM22, REG_YMM23, REG_YMM24, REG_YMM25, REG_YMM26, + REG_YMM27, REG_YMM28, REG_YMM29, REG_YMM30, REG_YMM31, REG_ZMM0, REG_ZMM1, REG_ZMM2, REG_ZMM3, REG_ZMM4, REG_ZMM5, REG_ZMM6, REG_ZMM7, REG_ZMM8, REG_ZMM9, REG_ZMM10, + REG_ZMM11, REG_ZMM12, REG_ZMM13, REG_ZMM14, REG_ZMM15, REG_ZMM16, REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20, REG_ZMM21, REG_ZMM22, REG_ZMM23, REG_ZMM24, REG_ZMM25, REG_ZMM26, + REG_ZMM27, REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31, REG_K0, REG_K1, REG_K2, REG_K3, REG_K4, REG_K5, REG_K6, REG_K7, REG_ES, REG_CS, REG_SS, + REG_DS, REG_FS, REG_GS, REG_CR0, REG_CR2, REG_CR3, REG_CR4, REG_CR8, REG_DR0, REG_DR1, REG_DR2, REG_DR3, REG_DR6, REG_DR7, REG_BND0, REG_BND1, + REG_BND2, REG_BND3, REG_MM0, REG_MM1, REG_MM2, REG_MM3, REG_MM4, REG_MM5, REG_MM6, REG_MM7, REG_ST0, REG_ST1, REG_ST2, REG_ST3, REG_ST4, REG_ST5, + REG_ST6, REG_ST7, REG_RIP, + REG_COUNT + }; + static u16 const register_codes[REG_COUNT]; + static String const register_names[REG_COUNT]; + + + enum OperandType : u8 { + OP_NONE, + OP_R8, + OP_R16, + OP_R32, + OP_R64, + OP_RM8, + OP_RM16, + OP_RM32, + OP_RM64, + OP_M, + OP_M8, + OP_M16, + OP_M32, + OP_M64, + OP_M80, + OP_M128, + OP_M256, + OP_M512, + OP_IMM8, + OP_IMM16, + OP_IMM32, + OP_IMM64, + OP_IMM8SX, + OP_REL8, + OP_REL32, + OP_AL_IMPL, + OP_AX_IMPL, + OP_EAX_IMPL, + OP_RAX_IMPL, + OP_CL_IMPL, + OP_DX_IMPL, + OP_ONE_IMPL, + OP_SREG, + OP_CR, + OP_DR, + OP_XMM, + OP_YMM, + OP_ZMM, + OP_XMM_M32, + OP_XMM_M64, + OP_XMM_M128, + OP_YMM_M256, + OP_ZMM_M512, + OP_MM, + OP_MM_M64, + OP_ST0_IMPL, + OP_STI, + OP_XMM0_IMPL, + OP_K, + OP_K_M8, + OP_K_M16, + OP_K_M32, + OP_K_M64, + OP_MOFFS8, + OP_MOFFS16, + OP_MOFFS32, + OP_MOFFS64, + OP_PTR16_16, + OP_PTR16_32, + OP_PTR16_64, + OP_M16_16, + OP_M16_32, + OP_M16_64, + }; + + + enum OperandEncoding : u8 { + ENC_NONE, + ENC_MR, + ENC_REG, + ENC_VVVV, + ENC_OP_R, + ENC_IB, + ENC_IW, + ENC_ID, + ENC_IQ, + ENC_IMPL, + ENC_IS4, + ENC_AAA, + }; + + typedef u32 EncodingFlags; // cannot use a C++ bit field to due lack of portability + + #pragma pack(push, 1) + struct Encoding { + Mnemonic mnemonic; + OperandType ops[4]; + OperandEncoding enc[4]; + u8 opcode; + u8 ext; + EncodingFlags flags; + + bool has_implicit () const { return ((flags>>21u)&1) != 0; } + u8 explicit_count() const { return cast(u8)((flags>>18u)&((1u<<18)-1)); } + u8 op_count () const { return cast(u8)((flags>>22u)&((1u<<22)-1)); } + }; + #pragma pack(pop) + GB_STATIC_ASSERT(gb_size_of(Encoding) == 16); + + + // Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. + struct EncodeRun { + u32 start; // start index in ENCODE_FORMS + u32 count; // number of forms for this mnemonic + }; + + + static EncodeRun const raw_encode_runs[1176]; + static u8 const raw_encode_forms[37680]; + StringMap mnemonic_map; + StringMap register_map; + Slice ENCODE_RUNS; + Slice ENCODE_FORMS; + bool init() { + string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); + for (u16 m = M_INVALID; m < MNEMONIC_COUNT; m++) { + string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); + } + string_map_init(®ister_map, REG_COUNT*2); + for (u16 r = REG_INVALID; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_names[r], cast(Register)r); + } + return true; + } + Mnemonic lookup(String const &name) { + Mnemonic *found = string_map_get(&mnemonic_map, name); + return found ? *found : M_INVALID; + } + Slice encoding_forms(Mnemonic m) const { + EncodeRun r = ENCODE_RUNS[m]; + return slice_lower_and_count(ENCODE_FORMS, r.start, r.count); + } + u16 reg_class(Register r) const { + return 0xFF00 & cast(u16)r; + } + // size in bits for register + u16 reg_size(Register r) const { + switch (reg_class(r)) { + case REG_CLASS_GPR64: return 64; + case REG_CLASS_GPR32: return 32; + case REG_CLASS_GPR16: return 16; + case REG_CLASS_GPR8: return 8; + case REG_CLASS_GPR8H: return 8; + case REG_CLASS_XMM: return 128; + case REG_CLASS_YMM: return 256; + case REG_CLASS_ZMM: return 512; + case REG_CLASS_K: return 64; + case REG_CLASS_MM: return 64; + case REG_CLASS_ST: return 80; + case REG_CLASS_SEG: return 16; + case REG_CLASS_CR: return 64; + case REG_CLASS_DR: return 64; + case REG_CLASS_BND: return 128; + } + return 0; + } +}; + + + +String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { + str_lit(""), str_lit("mov"), str_lit("movabs"), str_lit("movzx"), str_lit("movsx"), str_lit("movsxd"), str_lit("xchg"), str_lit("push"), str_lit("pop"), str_lit("lea"), str_lit("add"), str_lit("adc"), str_lit("sub"), str_lit("sbb"), str_lit("mul"), str_lit("imul"), + str_lit("div"), str_lit("idiv"), str_lit("inc"), str_lit("dec"), str_lit("neg"), str_lit("cmp"), str_lit("and"), str_lit("or"), str_lit("xor"), str_lit("not"), str_lit("test"), str_lit("shl"), str_lit("shr"), str_lit("sar"), str_lit("rol"), str_lit("ror"), + str_lit("rcl"), str_lit("rcr"), str_lit("shld"), str_lit("shrd"), str_lit("bt"), str_lit("bts"), str_lit("btr"), str_lit("btc"), str_lit("bsf"), str_lit("bsr"), str_lit("popcnt"), str_lit("lzcnt"), str_lit("tzcnt"), str_lit("jmp"), str_lit("ja"), str_lit("jae"), + str_lit("jb"), str_lit("jbe"), str_lit("jc"), str_lit("je"), str_lit("jz"), str_lit("jg"), str_lit("jge"), str_lit("jl"), str_lit("jle"), str_lit("jna"), str_lit("jnae"), str_lit("jnb"), str_lit("jnbe"), str_lit("jnc"), str_lit("jne"), str_lit("jnz"), + str_lit("jng"), str_lit("jnge"), str_lit("jnl"), str_lit("jnle"), str_lit("jno"), str_lit("jnp"), str_lit("jns"), str_lit("jo"), str_lit("jp"), str_lit("jpe"), str_lit("jpo"), str_lit("js"), str_lit("jcxz"), str_lit("jecxz"), str_lit("jrcxz"), str_lit("loop"), + str_lit("loope"), str_lit("loopne"), str_lit("call"), str_lit("ret"), str_lit("iret"), str_lit("iretd"), str_lit("iretq"), str_lit("int"), str_lit("int3"), str_lit("into"), str_lit("syscall"), str_lit("sysret"), str_lit("sysenter"), str_lit("sysexit"), str_lit("seta"), str_lit("setae"), + str_lit("setb"), str_lit("setbe"), str_lit("setc"), str_lit("sete"), str_lit("setg"), str_lit("setge"), str_lit("setl"), str_lit("setle"), str_lit("setna"), str_lit("setnae"), str_lit("setnb"), str_lit("setnbe"), str_lit("setnc"), str_lit("setne"), str_lit("setng"), str_lit("setnge"), + str_lit("setnl"), str_lit("setnle"), str_lit("setno"), str_lit("setnp"), str_lit("setns"), str_lit("setnz"), str_lit("seto"), str_lit("setp"), str_lit("setpe"), str_lit("setpo"), str_lit("sets"), str_lit("setz"), str_lit("cmova"), str_lit("cmovae"), str_lit("cmovb"), str_lit("cmovbe"), + str_lit("cmovc"), str_lit("cmove"), str_lit("cmovg"), str_lit("cmovge"), str_lit("cmovl"), str_lit("cmovle"), str_lit("cmovna"), str_lit("cmovnae"), str_lit("cmovnb"), str_lit("cmovnbe"), str_lit("cmovnc"), str_lit("cmovne"), str_lit("cmovng"), str_lit("cmovnge"), str_lit("cmovnl"), str_lit("cmovnle"), + str_lit("cmovno"), str_lit("cmovnp"), str_lit("cmovns"), str_lit("cmovnz"), str_lit("cmovo"), str_lit("cmovp"), str_lit("cmovpe"), str_lit("cmovpo"), str_lit("cmovs"), str_lit("cmovz"), str_lit("movs"), str_lit("movsb"), str_lit("movsw"), str_lit("movsd"), str_lit("movsq"), str_lit("cmps"), + str_lit("cmpsb"), str_lit("cmpsw"), str_lit("cmpsd"), str_lit("cmpsq"), str_lit("scas"), str_lit("scasb"), str_lit("scasw"), str_lit("scasd"), str_lit("scasq"), str_lit("lods"), str_lit("lodsb"), str_lit("lodsw"), str_lit("lodsd"), str_lit("lodsq"), str_lit("stos"), str_lit("stosb"), + str_lit("stosw"), str_lit("stosd"), str_lit("stosq"), str_lit("clc"), str_lit("stc"), str_lit("cmc"), str_lit("cld"), str_lit("std"), str_lit("cli"), str_lit("sti"), str_lit("lahf"), str_lit("sahf"), str_lit("pushf"), str_lit("pushfd"), str_lit("pushfq"), str_lit("popf"), + str_lit("popfd"), str_lit("popfq"), str_lit("nop"), str_lit("hlt"), str_lit("wait"), str_lit("lock"), str_lit("ud0"), str_lit("ud1"), str_lit("ud2"), str_lit("cpuid"), str_lit("rdtsc"), str_lit("rdtscp"), str_lit("rdpmc"), str_lit("xgetbv"), str_lit("xsetbv"), str_lit("cbw"), + str_lit("cwde"), str_lit("cdqe"), str_lit("cwd"), str_lit("cdq"), str_lit("cqo"), str_lit("andn"), str_lit("bextr"), str_lit("blsi"), str_lit("blsmsk"), str_lit("blsr"), str_lit("bzhi"), str_lit("pdep"), str_lit("pext"), str_lit("rorx"), str_lit("sarx"), str_lit("shlx"), + str_lit("shrx"), str_lit("mulx"), str_lit("adcx"), str_lit("adox"), str_lit("movaps"), str_lit("movups"), str_lit("movapd"), str_lit("movupd"), str_lit("movss"), str_lit("movsd"), str_lit("movdqa"), str_lit("movdqu"), str_lit("movq"), str_lit("movd"), str_lit("movlps"), str_lit("movhps"), + str_lit("movlpd"), str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), + str_lit("subss"), str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), + str_lit("rsqrtps"), str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), + str_lit("xorps"), str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("cmpsd_sse"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), + str_lit("cvtps2pd"), str_lit("cvtpd2ps"), str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), + str_lit("paddb"), str_lit("paddw"), str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), + str_lit("pmullw"), str_lit("pmulhw"), str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), + str_lit("psrad"), str_lit("pcmpeqb"), str_lit("pcmpeqw"), str_lit("pcmpeqd"), str_lit("pcmpgtb"), str_lit("pcmpgtw"), str_lit("pcmpgtd"), str_lit("packsswb"), str_lit("packssdw"), str_lit("packuswb"), str_lit("punpcklbw"), str_lit("punpcklwd"), str_lit("punpckldq"), str_lit("punpcklqdq"), str_lit("punpckhbw"), str_lit("punpckhwd"), + str_lit("punpckhdq"), str_lit("punpckhqdq"), str_lit("pshufd"), str_lit("pshufhw"), str_lit("pshuflw"), str_lit("pshufw"), str_lit("pextrw"), str_lit("pinsrw"), str_lit("pmovmskb"), str_lit("pavgb"), str_lit("pavgw"), str_lit("pmaxub"), str_lit("pmaxsw"), str_lit("pminub"), str_lit("pminsw"), str_lit("psadbw"), + str_lit("maskmovdqu"), str_lit("lfence"), str_lit("sfence"), str_lit("mfence"), str_lit("pause"), str_lit("clflush"), str_lit("addsubps"), str_lit("addsubpd"), str_lit("haddps"), str_lit("haddpd"), str_lit("hsubps"), str_lit("hsubpd"), str_lit("movddup"), str_lit("movsldup"), str_lit("movshdup"), str_lit("lddqu"), + str_lit("pshufb"), str_lit("phaddw"), str_lit("phaddd"), str_lit("phaddsw"), str_lit("phsubw"), str_lit("phsubd"), str_lit("phsubsw"), str_lit("pmaddubsw"), str_lit("pmulhrsw"), str_lit("psignb"), str_lit("psignw"), str_lit("psignd"), str_lit("pabsb"), str_lit("pabsw"), str_lit("pabsd"), str_lit("palignr"), + str_lit("blendps"), str_lit("blendpd"), str_lit("blendvps"), str_lit("blendvpd"), str_lit("pblendw"), str_lit("pblendvb"), str_lit("dpps"), str_lit("dppd"), str_lit("extractps"), str_lit("insertps"), str_lit("mpsadbw"), str_lit("packusdw"), str_lit("pextrb"), str_lit("pextrd"), str_lit("pextrq"), str_lit("phminposuw"), + str_lit("pinsrb"), str_lit("pinsrd"), str_lit("pinsrq"), str_lit("pmaxsb"), str_lit("pmaxsd"), str_lit("pmaxuw"), str_lit("pmaxud"), str_lit("pminsb"), str_lit("pminsd"), str_lit("pminuw"), str_lit("pminud"), str_lit("pmovsxbw"), str_lit("pmovsxbd"), str_lit("pmovsxbq"), str_lit("pmovsxwd"), str_lit("pmovsxwq"), + str_lit("pmovsxdq"), str_lit("pmovzxbw"), str_lit("pmovzxbd"), str_lit("pmovzxbq"), str_lit("pmovzxwd"), str_lit("pmovzxwq"), str_lit("pmovzxdq"), str_lit("pmuldq"), str_lit("pmulld"), str_lit("ptest"), str_lit("roundps"), str_lit("roundpd"), str_lit("roundss"), str_lit("roundsd"), str_lit("pcmpeqq"), str_lit("crc32"), + str_lit("pcmpestri"), str_lit("pcmpestrm"), str_lit("pcmpistri"), str_lit("pcmpistrm"), str_lit("pcmpgtq"), str_lit("pclmulqdq"), str_lit("aesdec"), str_lit("aesdeclast"), str_lit("aesenc"), str_lit("aesenclast"), str_lit("aesimc"), str_lit("aeskeygenassist"), str_lit("sha1msg1"), str_lit("sha1msg2"), str_lit("sha1nexte"), str_lit("sha1rnds4"), + str_lit("sha256msg1"), str_lit("sha256msg2"), str_lit("sha256rnds2"), str_lit("vaddps"), str_lit("vaddpd"), str_lit("vaddss"), str_lit("vaddsd"), str_lit("vsubps"), str_lit("vsubpd"), str_lit("vsubss"), str_lit("vsubsd"), str_lit("vmulps"), str_lit("vmulpd"), str_lit("vmulss"), str_lit("vmulsd"), str_lit("vdivps"), + str_lit("vdivpd"), str_lit("vdivss"), str_lit("vdivsd"), str_lit("vsqrtps"), str_lit("vsqrtpd"), str_lit("vsqrtss"), str_lit("vsqrtsd"), str_lit("vrcpps"), str_lit("vrcpss"), str_lit("vrsqrtps"), str_lit("vrsqrtss"), str_lit("vmaxps"), str_lit("vmaxpd"), str_lit("vmaxss"), str_lit("vmaxsd"), str_lit("vminps"), + str_lit("vminpd"), str_lit("vminss"), str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), + str_lit("vcomisd"), str_lit("vucomiss"), str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), + str_lit("vroundpd"), str_lit("vroundss"), str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), + str_lit("vmovhps"), str_lit("vmovlpd"), str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), + str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), str_lit("vpaddq"), str_lit("vpsubb"), + str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), str_lit("vpsllq"), str_lit("vpsrlw"), + str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), str_lit("vpackuswb"), str_lit("vpackusdw"), + str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), str_lit("vpextrq"), str_lit("vpinsrb"), + str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), str_lit("vpsignb"), str_lit("vpsignw"), + str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), str_lit("vpminsd"), str_lit("vpminuw"), + str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), str_lit("vpmulld"), str_lit("vmaskmovdqu"), + str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), str_lit("vmaskmovpd"), str_lit("vtestps"), + str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), str_lit("vpsrlvd"), str_lit("vpsrlvq"), + str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), + str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), + str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), + str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), + str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), str_lit("vmovdqu64"), str_lit("vpblendmb"), + str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), str_lit("vptestmw"), str_lit("vptestmd"), + str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), str_lit("vpconflictq"), str_lit("vplzcntd"), + str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), str_lit("vpermw"), str_lit("vpmovb2m"), + str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), str_lit("vpmovsqd"), str_lit("vpmovusqd"), + str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), str_lit("vprorq"), str_lit("vprorvd"), + str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), str_lit("vrangepd"), str_lit("vrangess"), + str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), str_lit("vrcp14pd"), str_lit("vrcp14ss"), + str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), str_lit("vfixupimmpd"), str_lit("vfixupimmss"), + str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), str_lit("kaddd"), str_lit("kandw"), + str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), str_lit("knotd"), str_lit("korw"), + str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), str_lit("kshiftrd"), str_lit("ktestw"), + str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), str_lit("fadd"), str_lit("faddp"), + str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), str_lit("fdivrp"), str_lit("fidivr"), + str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), str_lit("fist"), str_lit("fistp"), + str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), str_lit("ficom"), str_lit("ficomp"), + str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), str_lit("fldln2"), str_lit("fsin"), + str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), str_lit("fwait"), str_lit("fclex"), + str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), str_lit("fxrstor"), str_lit("fxrstor64"), + str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), str_lit("verr"), str_lit("verw"), + str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), str_lit("vmptrst"), str_lit("vmread"), + str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), str_lit("wrssd"), + str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), str_lit("xsaves"), + str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"), + str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), +}; +u16 const Asm_amd64::register_codes[Asm_amd64::REG_COUNT] { + 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, + 271, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, + 527, 768, 769, 770, 771, 772, 773, 774, 775, 776, 777, 778, 779, 780, 781, 782, + 783, 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, + 1039, 1284, 1285, 1286, 1287, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1546, + 1547, 1548, 1549, 1550, 1551, 1552, 1553, 1554, 1555, 1556, 1557, 1558, 1559, 1560, 1561, 1562, + 1563, 1564, 1565, 1566, 1567, 1792, 1793, 1794, 1795, 1796, 1797, 1798, 1799, 1800, 1801, 1802, + 1803, 1804, 1805, 1806, 1807, 1808, 1809, 1810, 1811, 1812, 1813, 1814, 1815, 1816, 1817, 1818, + 1819, 1820, 1821, 1822, 1823, 2048, 2049, 2050, 2051, 2052, 2053, 2054, 2055, 2056, 2057, 2058, + 2059, 2060, 2061, 2062, 2063, 2064, 2065, 2066, 2067, 2068, 2069, 2070, 2071, 2072, 2073, 2074, + 2075, 2076, 2077, 2078, 2079, 2304, 2305, 2306, 2307, 2308, 2309, 2310, 2311, 2560, 2561, 2562, + 2563, 2564, 2565, 2816, 2818, 2819, 2820, 2824, 3072, 3073, 3074, 3075, 3078, 3079, 3328, 3329, + 3330, 3331, 3584, 3585, 3586, 3587, 3588, 3589, 3590, 3591, 3840, 3841, 3842, 3843, 3844, 3845, + 3846, 3847, 65534, +}; +String const Asm_amd64::register_names[Asm_amd64::REG_COUNT] { + str_lit(""), str_lit("rax"), str_lit("rcx"), str_lit("rdx"), str_lit("rbx"), str_lit("rsp"), str_lit("rbp"), str_lit("rsi"), str_lit("rdi"), str_lit("r8"), str_lit("r9"), str_lit("r10"), str_lit("r11"), str_lit("r12"), str_lit("r13"), str_lit("r14"), + str_lit("r15"), str_lit("eax"), str_lit("ecx"), str_lit("edx"), str_lit("ebx"), str_lit("esp"), str_lit("ebp"), str_lit("esi"), str_lit("edi"), str_lit("r8d"), str_lit("r9d"), str_lit("r10d"), str_lit("r11d"), str_lit("r12d"), str_lit("r13d"), str_lit("r14d"), + str_lit("r15d"), str_lit("ax"), str_lit("cx"), str_lit("dx"), str_lit("bx"), str_lit("sp"), str_lit("bp"), str_lit("si"), str_lit("di"), str_lit("r8w"), str_lit("r9w"), str_lit("r10w"), str_lit("r11w"), str_lit("r12w"), str_lit("r13w"), str_lit("r14w"), + str_lit("r15w"), str_lit("al"), str_lit("cl"), str_lit("dl"), str_lit("bl"), str_lit("spl"), str_lit("bpl"), str_lit("sil"), str_lit("dil"), str_lit("r8b"), str_lit("r9b"), str_lit("r10b"), str_lit("r11b"), str_lit("r12b"), str_lit("r13b"), str_lit("r14b"), + str_lit("r15b"), str_lit("ah"), str_lit("ch"), str_lit("dh"), str_lit("bh"), str_lit("xmm0"), str_lit("xmm1"), str_lit("xmm2"), str_lit("xmm3"), str_lit("xmm4"), str_lit("xmm5"), str_lit("xmm6"), str_lit("xmm7"), str_lit("xmm8"), str_lit("xmm9"), str_lit("xmm10"), + str_lit("xmm11"), str_lit("xmm12"), str_lit("xmm13"), str_lit("xmm14"), str_lit("xmm15"), str_lit("xmm16"), str_lit("xmm17"), str_lit("xmm18"), str_lit("xmm19"), str_lit("xmm20"), str_lit("xmm21"), str_lit("xmm22"), str_lit("xmm23"), str_lit("xmm24"), str_lit("xmm25"), str_lit("xmm26"), + str_lit("xmm27"), str_lit("xmm28"), str_lit("xmm29"), str_lit("xmm30"), str_lit("xmm31"), str_lit("ymm0"), str_lit("ymm1"), str_lit("ymm2"), str_lit("ymm3"), str_lit("ymm4"), str_lit("ymm5"), str_lit("ymm6"), str_lit("ymm7"), str_lit("ymm8"), str_lit("ymm9"), str_lit("ymm10"), + str_lit("ymm11"), str_lit("ymm12"), str_lit("ymm13"), str_lit("ymm14"), str_lit("ymm15"), str_lit("ymm16"), str_lit("ymm17"), str_lit("ymm18"), str_lit("ymm19"), str_lit("ymm20"), str_lit("ymm21"), str_lit("ymm22"), str_lit("ymm23"), str_lit("ymm24"), str_lit("ymm25"), str_lit("ymm26"), + str_lit("ymm27"), str_lit("ymm28"), str_lit("ymm29"), str_lit("ymm30"), str_lit("ymm31"), str_lit("zmm0"), str_lit("zmm1"), str_lit("zmm2"), str_lit("zmm3"), str_lit("zmm4"), str_lit("zmm5"), str_lit("zmm6"), str_lit("zmm7"), str_lit("zmm8"), str_lit("zmm9"), str_lit("zmm10"), + str_lit("zmm11"), str_lit("zmm12"), str_lit("zmm13"), str_lit("zmm14"), str_lit("zmm15"), str_lit("zmm16"), str_lit("zmm17"), str_lit("zmm18"), str_lit("zmm19"), str_lit("zmm20"), str_lit("zmm21"), str_lit("zmm22"), str_lit("zmm23"), str_lit("zmm24"), str_lit("zmm25"), str_lit("zmm26"), + str_lit("zmm27"), str_lit("zmm28"), str_lit("zmm29"), str_lit("zmm30"), str_lit("zmm31"), str_lit("k0"), str_lit("k1"), str_lit("k2"), str_lit("k3"), str_lit("k4"), str_lit("k5"), str_lit("k6"), str_lit("k7"), str_lit("es"), str_lit("cs"), str_lit("ss"), + str_lit("ds"), str_lit("fs"), str_lit("gs"), str_lit("cr0"), str_lit("cr2"), str_lit("cr3"), str_lit("cr4"), str_lit("cr8"), str_lit("dr0"), str_lit("dr1"), str_lit("dr2"), str_lit("dr3"), str_lit("dr6"), str_lit("dr7"), str_lit("bnd0"), str_lit("bnd1"), + str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"), + str_lit("st6"), str_lit("st7"), str_lit("rip"), +}; +Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1176] = { + { 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13}, + { 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12}, + { 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2}, + { 431, 2}, { 433, 2}, { 435, 2}, { 437, 2}, { 439, 2}, { 441, 2}, { 443, 2}, { 445, 2}, { 447, 2}, { 449, 2}, { 451, 2}, { 453, 2}, { 455, 2}, { 457, 2}, { 459, 2}, { 461, 2}, + { 463, 2}, { 465, 2}, { 467, 2}, { 469, 2}, { 471, 2}, { 473, 2}, { 475, 2}, { 477, 2}, { 479, 2}, { 481, 2}, { 483, 2}, { 485, 2}, { 487, 1}, { 488, 1}, { 489, 1}, { 490, 1}, + { 491, 1}, { 492, 1}, { 493, 5}, { 498, 2}, { 500, 1}, { 501, 1}, { 502, 1}, { 503, 1}, { 504, 1}, { 505, 1}, { 506, 1}, { 507, 1}, { 508, 1}, { 509, 1}, { 510, 1}, { 511, 1}, + { 512, 1}, { 513, 1}, { 514, 1}, { 515, 1}, { 516, 1}, { 517, 1}, { 518, 1}, { 519, 1}, { 520, 1}, { 521, 1}, { 522, 1}, { 523, 1}, { 524, 1}, { 525, 1}, { 526, 1}, { 527, 1}, + { 528, 1}, { 529, 1}, { 530, 1}, { 531, 1}, { 532, 1}, { 533, 1}, { 534, 1}, { 535, 1}, { 536, 1}, { 537, 1}, { 538, 1}, { 539, 1}, { 540, 3}, { 543, 3}, { 546, 3}, { 549, 3}, + { 552, 3}, { 555, 3}, { 558, 3}, { 561, 3}, { 564, 3}, { 567, 3}, { 570, 3}, { 573, 3}, { 576, 3}, { 579, 3}, { 582, 3}, { 585, 3}, { 588, 3}, { 591, 3}, { 594, 3}, { 597, 3}, + { 600, 3}, { 603, 3}, { 606, 3}, { 609, 3}, { 612, 3}, { 615, 3}, { 618, 3}, { 621, 3}, { 624, 3}, { 627, 3}, { 630, 1}, { 631, 1}, { 632, 1}, { 633, 1}, { 634, 1}, { 635, 1}, + { 636, 1}, { 637, 1}, { 638, 1}, { 639, 1}, { 640, 1}, { 641, 1}, { 642, 1}, { 643, 1}, { 644, 1}, { 645, 1}, { 646, 1}, { 647, 1}, { 648, 1}, { 649, 1}, { 650, 1}, { 651, 1}, + { 652, 1}, { 653, 1}, { 654, 1}, { 655, 1}, { 656, 1}, { 657, 1}, { 658, 1}, { 659, 1}, { 660, 1}, { 661, 1}, { 662, 1}, { 663, 1}, { 664, 1}, { 665, 1}, { 666, 1}, { 667, 1}, + { 668, 1}, { 669, 1}, { 670, 4}, { 674, 1}, { 675, 1}, { 676, 1}, { 677, 1}, { 678, 1}, { 679, 1}, { 680, 1}, { 681, 1}, { 682, 1}, { 683, 1}, { 684, 1}, { 685, 1}, { 686, 1}, + { 687, 1}, { 688, 1}, { 689, 1}, { 690, 1}, { 691, 1}, { 692, 2}, { 694, 2}, { 696, 2}, { 698, 2}, { 700, 2}, { 702, 2}, { 704, 2}, { 706, 2}, { 708, 2}, { 710, 2}, { 712, 2}, + { 714, 2}, { 716, 2}, { 718, 2}, { 720, 2}, { 722, 2}, { 724, 2}, { 726, 2}, { 728, 2}, { 730, 2}, { 732, 2}, { 734, 2}, { 736, 2}, { 738, 6}, { 744, 4}, { 748, 2}, { 750, 2}, + { 752, 2}, { 754, 2}, { 756, 1}, { 757, 1}, { 758, 2}, { 760, 2}, { 762, 1}, { 763, 1}, { 764, 1}, { 765, 1}, { 766, 1}, { 767, 1}, { 768, 1}, { 769, 1}, { 770, 1}, { 771, 1}, + { 772, 1}, { 773, 1}, { 774, 1}, { 775, 1}, { 776, 1}, { 777, 1}, { 778, 1}, { 779, 1}, { 780, 1}, { 781, 1}, { 782, 1}, { 783, 1}, { 784, 1}, { 785, 1}, { 786, 1}, { 787, 1}, + { 788, 1}, { 789, 1}, { 790, 1}, { 791, 1}, { 792, 1}, { 793, 1}, { 794, 1}, { 795, 1}, { 796, 1}, { 797, 1}, { 798, 1}, { 799, 1}, { 800, 1}, { 801, 1}, { 802, 1}, { 803, 1}, + { 804, 1}, { 805, 1}, { 806, 1}, { 807, 1}, { 808, 1}, { 809, 1}, { 810, 1}, { 811, 1}, { 812, 1}, { 813, 1}, { 814, 1}, { 815, 1}, { 816, 1}, { 817, 1}, { 818, 1}, { 819, 1}, + { 820, 1}, { 821, 1}, { 822, 1}, { 823, 1}, { 824, 1}, { 825, 1}, { 826, 1}, { 827, 1}, { 828, 2}, { 830, 2}, { 832, 2}, { 834, 2}, { 836, 1}, { 837, 1}, { 838, 2}, { 840, 2}, + { 842, 1}, { 843, 1}, { 844, 1}, { 845, 1}, { 846, 1}, { 847, 1}, { 848, 1}, { 849, 1}, { 850, 1}, { 851, 1}, { 852, 1}, { 853, 1}, { 854, 1}, { 855, 1}, { 856, 1}, { 857, 1}, + { 858, 1}, { 859, 1}, { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, { 865, 1}, { 866, 1}, { 867, 2}, { 869, 2}, { 871, 2}, { 873, 2}, { 875, 2}, { 877, 2}, { 879, 2}, + { 881, 2}, { 883, 1}, { 884, 1}, { 885, 1}, { 886, 1}, { 887, 1}, { 888, 1}, { 889, 1}, { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 1}, { 897, 1}, + { 898, 1}, { 899, 1}, { 900, 1}, { 901, 1}, { 902, 1}, { 903, 1}, { 904, 2}, { 906, 2}, { 908, 2}, { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, + { 917, 1}, { 918, 1}, { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, { 930, 1}, { 931, 1}, { 932, 1}, + { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, { 942, 1}, { 943, 1}, { 944, 1}, { 945, 1}, { 946, 1}, { 947, 1}, { 948, 1}, + { 949, 1}, { 950, 1}, { 951, 1}, { 952, 1}, { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, { 959, 1}, { 960, 1}, { 961, 1}, { 962, 1}, { 963, 1}, { 964, 1}, + { 965, 1}, { 966, 1}, { 967, 1}, { 968, 1}, { 969, 1}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, { 975, 1}, { 976, 1}, { 977, 1}, { 978, 1}, { 979, 1}, { 980, 1}, + { 981, 1}, { 982, 1}, { 983, 1}, { 984, 1}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 1}, { 991, 1}, { 992, 1}, { 993, 1}, { 994, 1}, { 995, 1}, { 996, 5}, + {1001, 1}, {1002, 1}, {1003, 1}, {1004, 1}, {1005, 1}, {1006, 1}, {1007, 1}, {1008, 1}, {1009, 1}, {1010, 1}, {1011, 1}, {1012, 1}, {1013, 1}, {1014, 1}, {1015, 1}, {1016, 1}, + {1017, 1}, {1018, 1}, {1019, 1}, {1020, 2}, {1022, 2}, {1024, 1}, {1025, 1}, {1026, 2}, {1028, 2}, {1030, 1}, {1031, 1}, {1032, 2}, {1034, 2}, {1036, 1}, {1037, 1}, {1038, 2}, + {1040, 2}, {1042, 1}, {1043, 1}, {1044, 2}, {1046, 2}, {1048, 1}, {1049, 1}, {1050, 2}, {1052, 1}, {1053, 2}, {1055, 1}, {1056, 2}, {1058, 2}, {1060, 1}, {1061, 1}, {1062, 2}, + {1064, 2}, {1066, 1}, {1067, 1}, {1068, 2}, {1070, 2}, {1072, 2}, {1074, 2}, {1076, 2}, {1078, 2}, {1080, 2}, {1082, 2}, {1084, 2}, {1086, 2}, {1088, 1}, {1089, 1}, {1090, 1}, + {1091, 1}, {1092, 1}, {1093, 1}, {1094, 2}, {1096, 2}, {1098, 2}, {1100, 2}, {1102, 2}, {1104, 2}, {1106, 2}, {1108, 2}, {1110, 2}, {1112, 2}, {1114, 2}, {1116, 1}, {1117, 2}, + {1119, 2}, {1121, 1}, {1122, 1}, {1123, 1}, {1124, 1}, {1125, 4}, {1129, 4}, {1133, 4}, {1137, 4}, {1141, 3}, {1144, 3}, {1147, 4}, {1151, 4}, {1155, 4}, {1159, 2}, {1161, 2}, + {1163, 2}, {1165, 2}, {1167, 2}, {1169, 1}, {1170, 1}, {1171, 2}, {1173, 2}, {1175, 2}, {1177, 2}, {1179, 2}, {1181, 2}, {1183, 2}, {1185, 2}, {1187, 1}, {1188, 1}, {1189, 2}, + {1191, 2}, {1193, 2}, {1195, 2}, {1197, 2}, {1199, 2}, {1201, 2}, {1203, 2}, {1205, 2}, {1207, 2}, {1209, 2}, {1211, 2}, {1213, 2}, {1215, 2}, {1217, 2}, {1219, 2}, {1221, 2}, + {1223, 2}, {1225, 2}, {1227, 2}, {1229, 2}, {1231, 2}, {1233, 2}, {1235, 2}, {1237, 2}, {1239, 2}, {1241, 2}, {1243, 2}, {1245, 2}, {1247, 4}, {1251, 4}, {1255, 4}, {1259, 4}, + {1263, 4}, {1267, 4}, {1271, 4}, {1275, 4}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 2}, {1289, 2}, {1291, 2}, {1293, 2}, {1295, 2}, {1297, 2}, {1299, 2}, {1301, 2}, + {1303, 2}, {1305, 2}, {1307, 2}, {1309, 2}, {1311, 2}, {1313, 2}, {1315, 2}, {1317, 2}, {1319, 2}, {1321, 2}, {1323, 2}, {1325, 1}, {1326, 2}, {1328, 1}, {1329, 1}, {1330, 1}, + {1331, 1}, {1332, 1}, {1333, 1}, {1334, 2}, {1336, 2}, {1338, 2}, {1340, 2}, {1342, 2}, {1344, 2}, {1346, 2}, {1348, 2}, {1350, 2}, {1352, 2}, {1354, 2}, {1356, 2}, {1358, 2}, + {1360, 2}, {1362, 2}, {1364, 2}, {1366, 2}, {1368, 2}, {1370, 2}, {1372, 2}, {1374, 2}, {1376, 1}, {1377, 2}, {1379, 2}, {1381, 2}, {1383, 2}, {1385, 2}, {1387, 2}, {1389, 2}, + {1391, 2}, {1393, 2}, {1395, 2}, {1397, 2}, {1399, 2}, {1401, 2}, {1403, 2}, {1405, 2}, {1407, 2}, {1409, 2}, {1411, 2}, {1413, 2}, {1415, 2}, {1417, 2}, {1419, 2}, {1421, 1}, + {1422, 2}, {1424, 1}, {1425, 1}, {1426, 1}, {1427, 1}, {1428, 1}, {1429, 1}, {1430, 4}, {1434, 2}, {1436, 1}, {1437, 1}, {1438, 1}, {1439, 1}, {1440, 4}, {1444, 4}, {1448, 2}, + {1450, 2}, {1452, 1}, {1453, 1}, {1454, 1}, {1455, 1}, {1456, 1}, {1457, 1}, {1458, 1}, {1459, 1}, {1460, 1}, {1461, 1}, {1462, 2}, {1464, 2}, {1466, 2}, {1468, 2}, {1470, 2}, + {1472, 2}, {1474, 4}, {1478, 4}, {1482, 2}, {1484, 2}, {1486, 2}, {1488, 2}, {1490, 2}, {1492, 2}, {1494, 2}, {1496, 2}, {1498, 2}, {1500, 2}, {1502, 2}, {1504, 2}, {1506, 2}, + {1508, 2}, {1510, 1}, {1511, 1}, {1512, 1}, {1513, 1}, {1514, 1}, {1515, 1}, {1516, 2}, {1518, 2}, {1520, 2}, {1522, 2}, {1524, 2}, {1526, 2}, {1528, 1}, {1529, 1}, {1530, 1}, + {1531, 1}, {1532, 1}, {1533, 1}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, {1544, 2}, {1546, 1}, {1547, 1}, {1548, 1}, {1549, 1}, {1550, 1}, {1551, 1}, {1552, 2}, + {1554, 2}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 2}, {1564, 1}, {1565, 1}, {1566, 1}, {1567, 1}, {1568, 1}, {1569, 1}, {1570, 2}, {1572, 2}, {1574, 2}, {1576, 2}, {1578, 2}, + {1580, 2}, {1582, 2}, {1584, 2}, {1586, 2}, {1588, 2}, {1590, 2}, {1592, 2}, {1594, 3}, {1597, 3}, {1600, 6}, {1606, 6}, {1612, 6}, {1618, 6}, {1624, 6}, {1630, 6}, {1636, 3}, + {1639, 3}, {1642, 3}, {1645, 3}, {1648, 3}, {1651, 3}, {1654, 3}, {1657, 3}, {1660, 3}, {1663, 3}, {1666, 3}, {1669, 3}, {1672, 3}, {1675, 3}, {1678, 3}, {1681, 3}, {1684, 3}, + {1687, 3}, {1690, 3}, {1693, 3}, {1696, 3}, {1699, 3}, {1702, 3}, {1705, 3}, {1708, 3}, {1711, 3}, {1714, 3}, {1717, 3}, {1720, 3}, {1723, 3}, {1726, 3}, {1729, 3}, {1732, 3}, + {1735, 3}, {1738, 3}, {1741, 3}, {1744, 3}, {1747, 3}, {1750, 3}, {1753, 3}, {1756, 3}, {1759, 3}, {1762, 3}, {1765, 3}, {1768, 3}, {1771, 3}, {1774, 3}, {1777, 3}, {1780, 3}, + {1783, 3}, {1786, 3}, {1789, 3}, {1792, 3}, {1795, 3}, {1798, 3}, {1801, 3}, {1804, 3}, {1807, 3}, {1810, 3}, {1813, 3}, {1816, 3}, {1819, 3}, {1822, 3}, {1825, 3}, {1828, 3}, + {1831, 3}, {1834, 3}, {1837, 3}, {1840, 3}, {1843, 3}, {1846, 3}, {1849, 3}, {1852, 3}, {1855, 3}, {1858, 3}, {1861, 3}, {1864, 3}, {1867, 3}, {1870, 3}, {1873, 3}, {1876, 3}, + {1879, 3}, {1882, 3}, {1885, 3}, {1888, 3}, {1891, 3}, {1894, 3}, {1897, 3}, {1900, 3}, {1903, 3}, {1906, 3}, {1909, 3}, {1912, 3}, {1915, 3}, {1918, 3}, {1921, 3}, {1924, 1}, + {1925, 1}, {1926, 3}, {1929, 3}, {1932, 1}, {1933, 1}, {1934, 3}, {1937, 3}, {1940, 1}, {1941, 1}, {1942, 3}, {1945, 3}, {1948, 1}, {1949, 1}, {1950, 3}, {1953, 3}, {1956, 1}, + {1957, 1}, {1958, 3}, {1961, 3}, {1964, 1}, {1965, 1}, {1966, 3}, {1969, 3}, {1972, 1}, {1973, 1}, {1974, 3}, {1977, 3}, {1980, 1}, {1981, 1}, {1982, 3}, {1985, 3}, {1988, 1}, + {1989, 1}, {1990, 3}, {1993, 3}, {1996, 1}, {1997, 1}, {1998, 3}, {2001, 3}, {2004, 3}, {2007, 3}, {2010, 3}, {2013, 3}, {2016, 1}, {2017, 1}, {2018, 1}, {2019, 1}, {2020, 1}, + {2021, 1}, {2022, 1}, {2023, 1}, {2024, 1}, {2025, 1}, {2026, 1}, {2027, 1}, {2028, 4}, {2032, 4}, {2036, 4}, {2040, 4}, {2044, 1}, {2045, 1}, {2046, 1}, {2047, 1}, {2048, 1}, + {2049, 1}, {2050, 1}, {2051, 1}, {2052, 1}, {2053, 1}, {2054, 1}, {2055, 1}, {2056, 1}, {2057, 1}, {2058, 1}, {2059, 1}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, + {2065, 1}, {2066, 1}, {2067, 1}, {2068, 1}, {2069, 1}, {2070, 1}, {2071, 1}, {2072, 1}, {2073, 1}, {2074, 1}, {2075, 1}, {2076, 1}, {2077, 1}, {2078, 1}, {2079, 4}, {2083, 2}, + {2085, 2}, {2087, 4}, {2091, 2}, {2093, 2}, {2095, 4}, {2099, 2}, {2101, 2}, {2103, 4}, {2107, 2}, {2109, 2}, {2111, 4}, {2115, 2}, {2117, 2}, {2119, 4}, {2123, 2}, {2125, 2}, + {2127, 1}, {2128, 1}, {2129, 1}, {2130, 1}, {2131, 1}, {2132, 1}, {2133, 1}, {2134, 1}, {2135, 1}, {2136, 4}, {2140, 3}, {2143, 1}, {2144, 3}, {2147, 4}, {2151, 2}, {2153, 3}, + {2156, 3}, {2159, 1}, {2160, 2}, {2162, 1}, {2163, 1}, {2164, 1}, {2165, 1}, {2166, 1}, {2167, 1}, {2168, 1}, {2169, 1}, {2170, 4}, {2174, 4}, {2178, 1}, {2179, 2}, {2181, 2}, + {2183, 1}, {2184, 1}, {2185, 1}, {2186, 1}, {2187, 2}, {2189, 2}, {2191, 1}, {2192, 1}, {2193, 1}, {2194, 1}, {2195, 1}, {2196, 1}, {2197, 1}, {2198, 1}, {2199, 1}, {2200, 1}, + {2201, 1}, {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 1}, {2207, 1}, {2208, 1}, {2209, 1}, {2210, 1}, {2211, 1}, {2212, 1}, {2213, 1}, {2214, 1}, {2215, 1}, {2216, 1}, + {2217, 1}, {2218, 1}, {2219, 1}, {2220, 1}, {2221, 1}, {2222, 1}, {2223, 1}, {2224, 1}, {2225, 1}, {2226, 1}, {2227, 2}, {2229, 2}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, + {2235, 2}, {2237, 2}, {2239, 2}, {2241, 2}, {2243, 1}, {2244, 3}, {2247, 1}, {2248, 3}, {2251, 1}, {2252, 3}, {2255, 1}, {2256, 1}, {2257, 3}, {2260, 3}, {2263, 1}, {2264, 1}, + {2265, 1}, {2266, 1}, {2267, 1}, {2268, 2}, {2270, 1}, {2271, 1}, {2272, 1}, {2273, 1}, {2274, 1}, {2275, 1}, {2276, 1}, {2277, 1}, {2278, 1}, {2279, 1}, {2280, 1}, {2281, 1}, + {2282, 1}, {2283, 1}, {2284, 1}, {2285, 1}, {2286, 1}, {2287, 1}, {2288, 1}, {2289, 1}, {2290, 1}, {2291, 1}, {2292, 1}, {2293, 1}, {2294, 1}, {2295, 1}, {2296, 1}, {2297, 1}, + {2298, 1}, {2299, 1}, {2300, 1}, {2301, 1}, {2302, 1}, {2303, 1}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 1}, {2309, 1}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, + {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 1}, {2319, 1}, {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, {2324, 1}, {2325, 2}, {2327, 4}, {2331, 1}, {2332, 1}, {2333, 4}, + {2337, 2}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 6}, {2349, 3}, {2352, 3}, +}; +u8 const Asm_amd64::raw_encode_forms[37680] = { + 0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00, + 0x01, 0x00, 0x01, 0x05, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x08, 0x08, 0x00, + 0x01, 0x00, 0x01, 0x12, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x13, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x14, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x15, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x08, 0x08, 0x00, + 0x01, 0x00, 0x05, 0x12, 0x00, 0x00, 0x01, 0x05, 0x00, 0x00, 0xc6, 0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 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0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0x96, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0x96, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x08, 0x05, 0x00, + 0x97, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0x97, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0x97, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, +}; diff --git a/src/main.cpp b/src/main.cpp index 74900587f..d3e4c2b60 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -68,6 +68,8 @@ gb_global Timings global_timings = {0}; #include "parser.hpp" #include "checker.hpp" +#include "asm_tables_amd64.cpp" + #include "parser.cpp" #include "checker.cpp" #include "docs.cpp" From 70ca5c0936638db8812d74b103e88a4654fe5737 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 10:44:34 +0100 Subject: [PATCH 13/92] Validate the names of mnemonics, prefixes, and registers for amd64 --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 105 ++- src/asm_tables_amd64.cpp | 38 +- src/check_asm.cpp | 643 ++++++++++++++++++ src/check_decl.cpp | 601 +--------------- src/main.cpp | 5 + 5 files changed, 776 insertions(+), 616 deletions(-) create mode 100644 src/check_asm.cpp diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 3eb57294a..89c3cf596 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -57,7 +57,30 @@ main :: proc() { strings.write_string(&sb, "\t\tMNEMONIC_COUNT\n"); } + { + strings.write_string(&sb, "\tenum Prefix : u8 {\n") + defer strings.write_string(&sb, "\t};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for prefix in Prefix { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + fmt.sbprintf(&sb, "PREFIX_%s, ", prefix) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n\n"); + strings.write_string(&sb, "\t\tPREFIX_COUNT\n"); + } + strings.write_string(&sb, "\tstatic String const mnemonic_strings[MNEMONIC_COUNT];\n") + strings.write_string(&sb, "\tstatic String const prefix_strings[PREFIX_COUNT];\n") { strings.write_string(&sb, "\n"); @@ -102,7 +125,7 @@ main :: proc() { strings.write_string(&sb, "\tstatic u16 const register_codes[REG_COUNT];\n") - strings.write_string(&sb, "\tstatic String const register_names[REG_COUNT];\n") + strings.write_string(&sb, "\tstatic String const register_strings[REG_COUNT];\n") strings.write_string(&sb, "\n\n") { @@ -178,6 +201,7 @@ main :: proc() { fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms[%d];\n", len(raw_encode_forms)) strings.write_string(&sb, "\tStringMap mnemonic_map;\n") + strings.write_string(&sb, "\tStringMap prefix_map;\n") strings.write_string(&sb, "\tStringMap register_map;\n") strings.write_string(&sb, "\tSlice ENCODE_RUNS;\n") strings.write_string(&sb, "\tSlice ENCODE_FORMS;\n") @@ -187,22 +211,40 @@ main :: proc() { defer strings.write_string(&sb, "\t}\n") strings.write_string(&sb, "\t\tstring_map_init(&mnemonic_map, MNEMONIC_COUNT*2);\n") - strings.write_string(&sb, "\t\tfor (u16 m = M_INVALID; m < MNEMONIC_COUNT; m++) {\n") + strings.write_string(&sb, "\t\tfor (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) {\n") strings.write_string(&sb, "\t\t\tstring_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m);\n") strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\tstring_map_init(&prefix_map, PREFIX_COUNT*2);\n") + strings.write_string(&sb, "\t\tfor (u8 r = PREFIX_INVALID+1; r < PREFIX_COUNT; r++) {\n") + strings.write_string(&sb, "\t\t\tstring_map_set(&prefix_map, prefix_strings[r], cast(Prefix)r);\n") + strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t\tstring_map_init(®ister_map, REG_COUNT*2);\n") - strings.write_string(&sb, "\t\tfor (u16 r = REG_INVALID; r < REG_COUNT; r++) {\n") - strings.write_string(&sb, "\t\t\tstring_map_set(®ister_map, register_names[r], cast(Register)r);\n") + strings.write_string(&sb, "\t\tfor (u16 r = REG_INVALID+1; r < REG_COUNT; r++) {\n") + strings.write_string(&sb, "\t\t\tstring_map_set(®ister_map, register_strings[r], cast(Register)r);\n") strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t\treturn true;\n") } { - strings.write_string(&sb, "\tMnemonic lookup(String const &name) {\n") + strings.write_string(&sb, "\tMnemonic mnemonic_lookup(String const &name) {\n") defer strings.write_string(&sb, "\t}\n") strings.write_string(&sb, "\t\tMnemonic *found = string_map_get(&mnemonic_map, name);\n") strings.write_string(&sb, "\t\treturn found ? *found : M_INVALID;\n") } + { + strings.write_string(&sb, "\tPrefix prefix_lookup(String const &name) {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tPrefix *found = string_map_get(&prefix_map, name);\n") + strings.write_string(&sb, "\t\treturn found ? *found : PREFIX_INVALID;\n") + } + { + strings.write_string(&sb, "\tRegister register_lookup(String const &name) {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tRegister *found = string_map_get(®ister_map, name);\n") + strings.write_string(&sb, "\t\treturn found ? *found : REG_INVALID;\n") + } { strings.write_string(&sb, "\tSlice encoding_forms(Mnemonic m) const {\n") defer strings.write_string(&sb, "\t}\n") @@ -244,12 +286,15 @@ main :: proc() { strings.write_string(&sb, "};\n") strings.write_string(&sb, "\n\n\n") + + fmt.sbprintf(&sb, "gb_internal Asm_{0:s} g_asm_{0:s};\n", ISA_NAME) + + strings.write_string(&sb, "\n\n\n") + { fmt.sbprintf(&sb, "String const Asm_{0:s}::mnemonic_strings[Asm_{0:s}::MNEMONIC_COUNT] {{\n", ISA_NAME) defer strings.write_string(&sb, "};\n"); - iota := 0 - count := uint(0) ROW_COUNT :: 16 for mnemonic in gen.Mnemonic { @@ -271,7 +316,33 @@ main :: proc() { strings.write_string(&sb, "\n") } - iota += 1 + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n"); + } + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::prefix_strings[Asm_{0:s}::PREFIX_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for prefix in Prefix { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if prefix == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else { + str := strings.to_lower(reflect.enum_string(prefix)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + count = (count + 1) % ROW_COUNT } strings.write_string(&sb, "\n"); @@ -300,7 +371,7 @@ main :: proc() { } { - fmt.sbprintf(&sb, "String const Asm_{0:s}::register_names[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + fmt.sbprintf(&sb, "String const Asm_{0:s}::register_strings[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) defer strings.write_string(&sb, "};\n"); count := uint(0) @@ -377,7 +448,21 @@ main :: proc() { } } - +Prefix :: enum u8 { + INVALID, + ES, + CS, + SS, + DS, + REX, + EVEX, + FS, + GS, + VEX, + LOCK, + REPNE, + REP, +} diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 7dfcad374..2d8ba1557 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -88,7 +88,13 @@ struct Asm_amd64 { MNEMONIC_COUNT }; + enum Prefix : u8 { + PREFIX_INVALID, PREFIX_ES, PREFIX_CS, PREFIX_SS, PREFIX_DS, PREFIX_REX, PREFIX_EVEX, PREFIX_FS, PREFIX_GS, PREFIX_VEX, PREFIX_LOCK, PREFIX_REPNE, PREFIX_REP, + + PREFIX_COUNT + }; static String const mnemonic_strings[MNEMONIC_COUNT]; + static String const prefix_strings[PREFIX_COUNT]; // Register classes (upper byte) static const u16 REG_CLASS_NONE = 0x000; @@ -126,7 +132,7 @@ struct Asm_amd64 { REG_COUNT }; static u16 const register_codes[REG_COUNT]; - static String const register_names[REG_COUNT]; + static String const register_strings[REG_COUNT]; enum OperandType : u8 { @@ -240,24 +246,37 @@ struct Asm_amd64 { static EncodeRun const raw_encode_runs[1176]; static u8 const raw_encode_forms[37680]; StringMap mnemonic_map; + StringMap prefix_map; StringMap register_map; Slice ENCODE_RUNS; Slice ENCODE_FORMS; bool init() { string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); - for (u16 m = M_INVALID; m < MNEMONIC_COUNT; m++) { + for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); } + string_map_init(&prefix_map, PREFIX_COUNT*2); + for (u8 r = PREFIX_INVALID+1; r < PREFIX_COUNT; r++) { + string_map_set(&prefix_map, prefix_strings[r], cast(Prefix)r); + } string_map_init(®ister_map, REG_COUNT*2); - for (u16 r = REG_INVALID; r < REG_COUNT; r++) { - string_map_set(®ister_map, register_names[r], cast(Register)r); + for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_strings[r], cast(Register)r); } return true; } - Mnemonic lookup(String const &name) { + Mnemonic mnemonic_lookup(String const &name) { Mnemonic *found = string_map_get(&mnemonic_map, name); return found ? *found : M_INVALID; } + Prefix prefix_lookup(String const &name) { + Prefix *found = string_map_get(&prefix_map, name); + return found ? *found : PREFIX_INVALID; + } + Register register_lookup(String const &name) { + Register *found = string_map_get(®ister_map, name); + return found ? *found : REG_INVALID; + } Slice encoding_forms(Mnemonic m) const { EncodeRun r = ENCODE_RUNS[m]; return slice_lower_and_count(ENCODE_FORMS, r.start, r.count); @@ -290,6 +309,10 @@ struct Asm_amd64 { +gb_internal Asm_amd64 g_asm_amd64; + + + String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit(""), str_lit("mov"), str_lit("movabs"), str_lit("movzx"), str_lit("movsx"), str_lit("movsxd"), str_lit("xchg"), str_lit("push"), str_lit("pop"), str_lit("lea"), str_lit("add"), str_lit("adc"), str_lit("sub"), str_lit("sbb"), str_lit("mul"), str_lit("imul"), str_lit("div"), str_lit("idiv"), str_lit("inc"), str_lit("dec"), str_lit("neg"), str_lit("cmp"), str_lit("and"), str_lit("or"), str_lit("xor"), str_lit("not"), str_lit("test"), str_lit("shl"), str_lit("shr"), str_lit("sar"), str_lit("rol"), str_lit("ror"), @@ -366,6 +389,9 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"), str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), }; +String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] { + str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"), +}; u16 const Asm_amd64::register_codes[Asm_amd64::REG_COUNT] { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, @@ -382,7 +408,7 @@ u16 const Asm_amd64::register_codes[Asm_amd64::REG_COUNT] { 3330, 3331, 3584, 3585, 3586, 3587, 3588, 3589, 3590, 3591, 3840, 3841, 3842, 3843, 3844, 3845, 3846, 3847, 65534, }; -String const Asm_amd64::register_names[Asm_amd64::REG_COUNT] { +String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] { str_lit(""), str_lit("rax"), str_lit("rcx"), str_lit("rdx"), str_lit("rbx"), str_lit("rsp"), str_lit("rbp"), str_lit("rsi"), str_lit("rdi"), str_lit("r8"), str_lit("r9"), str_lit("r10"), str_lit("r11"), str_lit("r12"), str_lit("r13"), str_lit("r14"), str_lit("r15"), str_lit("eax"), str_lit("ecx"), str_lit("edx"), str_lit("ebx"), str_lit("esp"), str_lit("ebp"), str_lit("esi"), str_lit("edi"), str_lit("r8d"), str_lit("r9d"), str_lit("r10d"), str_lit("r11d"), str_lit("r12d"), str_lit("r13d"), str_lit("r14d"), str_lit("r15d"), str_lit("ax"), str_lit("cx"), str_lit("dx"), str_lit("bx"), str_lit("sp"), str_lit("bp"), str_lit("si"), str_lit("di"), str_lit("r8w"), str_lit("r9w"), str_lit("r10w"), str_lit("r11w"), str_lit("r12w"), str_lit("r13w"), str_lit("r14w"), diff --git a/src/check_asm.cpp b/src/check_asm.cpp new file mode 100644 index 000000000..828d6af93 --- /dev/null +++ b/src/check_asm.cpp @@ -0,0 +1,643 @@ + +gb_internal bool is_valid_asm_parameter_type(Type *type) { + if (is_type_integer(type)) { + return true; + } + if (is_type_float(type)) { + return true; + } + if (is_type_boolean(type)) { + return true; + } + if (is_type_pointer(type) || is_type_multi_pointer(type)) { + return true; + } + if (is_type_simd_vector(type)) { + return true; + } + return false; +} + +gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { + if (is_type_integer(type)) { + return AsmRegClass_Integer; + } + if (is_type_float(type)) { + return AsmRegClass_Float; + } + if (is_type_boolean(type)) { + return AsmRegClass_Integer; + } + if (is_type_pointer(type) || is_type_multi_pointer(type)) { + return AsmRegClass_Integer; + } + if (is_type_simd_vector(type)) { + return AsmRegClass_Vector; + } + return AsmRegClass_Unknown; +} + +gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { + Type *tuple = alloc_type_tuple(); + if (_params == nullptr) { + return tuple; + } + ast_node(field_list, FieldList, _params); + Slice params = field_list->list; + + Array variables = {}; + variables.allocator = heap_allocator(); + + i32 param_index = 0; + for (Ast *param : params) { + ast_node(field, Field, param); + + bool prev = ctx->allow_polymorphic_types; + ctx->allow_polymorphic_types = false; + Type *type = check_type(ctx, field->type); + ctx->allow_polymorphic_types = prev; + + if (!is_valid_asm_parameter_type(type)) { + gbString s = type_to_string(type); + error(field->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + gb_string_free(s); + continue; + } + + for_array(j, field->names) { + Ast *name = field->names[j]; + + bool is_poly_name = false; + + switch (name->kind) { + case Ast_Ident: + break; + case Ast_PolyType: + GB_ASSERT(name->PolyType.specialization == nullptr); + is_poly_name = true; + name = name->PolyType.type; + break; + } + + if (!ast_node_expect(name, Ast_Ident)) { + continue; + } + + if (is_blank_ident(name)) { + error(name, "All parameters must have a name in an asm template"); + continue; + } + Token name_token = name->Ident.token; + + Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); + entity->flags |= EntityFlag_Used; + if (is_poly_name) { + entity->flags |= EntityFlag_PolyConst; + if (is_type_internally_pointer_like(type)) { + error(name, "Parameters with a pointer-like type cannot be used as $ immediates"); + } + } + + Entity *found = scope_insert(scope, entity); + if (found == nullptr) { + array_add(&variables, entity); + + AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); + if (is_poly_name) { + ed.kind = AsmTemplateEntityDecl_Immediate; + } + if (input_parameters) { + ed.param_group = AsmTemplateEntityDeclParamGroup_Input; + ed.param_index = param_index++; + ed.result_index = -1; + } else { + ed.param_group = AsmTemplateEntityDeclParamGroup_Output; + ed.param_index = -1; + ed.result_index = param_index++; + } + + ed.total_index = cast(i32)asm_template_entity_decls->count; + array_add(asm_template_entity_decls, ed); + } else { + TokenPos pos = found->token.pos; + error(name_token, + "Redeclaration of '%.*s' in this scope\n" + "\tat %s", + LIT(name_token.string), token_pos_to_string(pos)); + entity = found; + } + } + } + + tuple->Tuple.variables = slice_from_array(variables); + + return tuple; +} + +gb_internal AsmTemplateEntityDeclParamGroup check_asm_find_group(Entity *entity, Array const &asm_template_entity_decls, i32 *index_) { + for_array(i, asm_template_entity_decls) { + auto const &ed = asm_template_entity_decls[i]; + if (ed.entity == entity) { + if (index_) *index_ = cast(i32)i; + return ed.param_group; + } + } + if (index_) *index_ = -1; + return AsmTemplateEntityDeclParamGroup_Unknown; +}; + +gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array const &asm_template_entity_decls) { + for (auto const &ed : asm_template_entity_decls) { + if (ed.entity == entity) { + return ed.kind; + } + } + return AsmTemplateEntityDecl_Invalid; +}; + + +gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { + StringSet pin_set = {}; + string_set_init(&pin_set, specs.count); + defer (string_set_destroy(&pin_set)); + + for (Ast *spec_ : specs) { + if (spec_->kind != Ast_AsmSpec) { + continue; + } + ast_node(spec, AsmSpec, spec_); + + GB_ASSERT(spec->name->kind == Ast_Ident); + + Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); + + bool must_check_value = false; + + String pin = {}; + if (spec->value != nullptr) { + if (spec->value->kind != Ast_AsmRegister) { + gbString s = expr_to_string(spec->value); + error(spec->value, "Expected an asm register, got %s", s); + gb_string_free(s); + continue; + } + + ast_node(reg, AsmRegister, spec->value); + pin = reg->name.string; + if (pin == "any") { + pin = {}; + } + if (pin.len != 0) { + if (string_set_update(&pin_set, pin)) { + error(spec->value, "Pinned register %%%.*s has already be assigned", LIT(pin)); + } + } + } + + if (spec->tied_name == nullptr) { + if (spec->type != nullptr) { + Type *type = check_type(ctx, spec->type); + if (!is_valid_asm_parameter_type(type)) { + gbString s = type_to_string(type); + error(spec->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + gb_string_free(s); + continue; + } + + Token name_token = spec->name->Ident.token; + + Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); + entity->flags |= EntityFlag_Used; + + Entity *found = scope_insert(scope, entity); + if (found == nullptr) { + AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); + ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; + ed.total_index = cast(i32)asm_template_entity_decls->count; + ed.pin = pin; + array_add(asm_template_entity_decls, ed); + } else { + TokenPos pos = found->token.pos; + error(name_token, + "Redeclaration of '%.*s' in this scope\n" + "\tat %s", + LIT(name_token.string), token_pos_to_string(pos)); + entity = found; + continue; + } + } else if (input == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } else { + i32 index = -1; + auto group = check_asm_find_group(input, *asm_template_entity_decls, &index); + gb_unused(group); + GB_ASSERT(index >= 0); + auto *i = &(*asm_template_entity_decls)[index]; + if (i->pin.len == 0) { + i->pin = pin; + } else { + error(spec_, "Asm register has already been pinned"); + } + } + + } else { + GB_ASSERT(spec->tied_name->kind == Ast_Ident); + + if (spec->type != nullptr) { + error(spec->type, "Tied register definitions cannot have a defined type since the values are already defined"); + } + + if (input == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } + Entity *output = scope_lookup(scope, spec->tied_name->Ident.interned, spec->tied_name->Ident.hash); + if (output == nullptr) { + error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); + continue; + } + + i32 input_index = -1; + i32 output_index = -1; + + auto input_group = check_asm_find_group(input, *asm_template_entity_decls, &input_index); + auto output_group = check_asm_find_group(output, *asm_template_entity_decls, &output_index); + if (input_group != AsmTemplateEntityDeclParamGroup_Input) { + error(input->token, "Parameter tied with '%.*s' must be an input parameter", LIT(output->token.string)); + continue; + } + if (output_group != AsmTemplateEntityDeclParamGroup_Output) { + error(output->token, "Parameter tied with '%.*s' must be an output parameter", LIT(input->token.string)); + continue; + } + + GB_ASSERT(input_index >= 0); + GB_ASSERT(output_index >= 0); + + auto *i = &(*asm_template_entity_decls)[input_index]; + auto *o = &(*asm_template_entity_decls)[output_index]; + + i->tie = output_index; + o->tie = input_index; + + i->pin = pin; + o->pin = pin; + + + must_check_value = true; + } + } +} + +gb_internal bool check_register(CheckerContext *ctx, AstAsmRegister *asm_reg) { + String name = asm_reg->name.string; + auto r = g_asm_amd64.register_lookup(name); + if (r) { + return true; + } + error(asm_reg->name, "Unknown register for this target platform: %%%.*s", LIT(name)); + return false; +} + +enum CheckMnemomicResult { + CheckMnemomic_Invalid, + CheckMnemomic_Mnemonic, + CheckMnemomic_Prefix, +}; + +gb_internal CheckMnemomicResult check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instruction) { + String name = instruction->name->Ident.token.string; + auto m = g_asm_amd64.mnemonic_lookup(name); + if (m) { + return CheckMnemomic_Mnemonic; + } + auto p = g_asm_amd64.prefix_lookup(name); + if (p) { + return CheckMnemomic_Prefix; + } + + if (instruction->operands.count == 0) { + error(instruction->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); + } else { + error(instruction->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); + } + return CheckMnemomic_Invalid; +} + + +gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { + if (expr == nullptr) { + return; + } + + operand->expr = expr; + operand->mode = Addressing_Invalid; + operand->type = t_invalid; + + GB_ASSERT(entity->kind == Entity_AsmTemplate); + auto *ate = &entity->AsmTemplate; + + Scope *param_scope = ate->param_scope; + Scope *label_scope = ate->label_scope; + gb_unused(param_scope); + gb_unused(label_scope); + + switch (expr->kind) { + case_ast_node(i, Ident, expr); + Entity *found = scope_lookup(param_scope, i->interned, i->hash); + if (found == nullptr) { + error(expr, "Undeclared asm parameter '%.*s'", LIT(i->token.string)); + return; + } + i->entity = found; + operand->mode = Addressing_Value; + operand->type = found->type; + return; + case_end; + case_ast_node(bl, BasicLit, expr); + check_expr(ctx, operand, expr); + return; + case_end; + case_ast_node(asm_reg, AsmRegister, expr); + check_register(ctx, asm_reg); + return; + case_end; + case_ast_node(mem_op, AsmMemoryOperand, expr); + if (!allow_memory_operands) { + break; + } + Operand base = {}; + Operand index = {}; + Operand scale = {}; + Operand disp = {}; + check_asm_instruction_operand(ctx, entity, &base, mem_op->base, false); + check_asm_instruction_operand(ctx, entity, &index, mem_op->index, false); + check_asm_instruction_operand(ctx, entity, &scale, mem_op->scale, false); + check_asm_instruction_operand(ctx, entity, &disp, mem_op->disp, false); + + for (int i = 0; base.expr && i == 0; i++) { + if (base.expr->kind == Ast_AsmRegister) { + check_register(ctx, &base.expr->AsmRegister); + } else { + Entity *param_entity = entity_of_node(base.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(base.expr); + error(base.expr, "A base value must a memory parameter, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + if (kind != AsmTemplateEntityDecl_Memory) { + gbString s = expr_to_string(base.expr); + error(base.expr, "A scale must be a memory parameter, got %s", s); + gb_string_free(s); + break; + } + } + } + + for (int i = 0; index.expr && i == 0; i++) { + if (index.expr->kind == Ast_AsmRegister) { + check_register(ctx, &index.expr->AsmRegister); + } else { + Entity *param_entity = entity_of_node(index.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(index.expr); + error(index.expr, "An index value must an integer, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + // okay: + break; + default: + { + gbString s = expr_to_string(index.expr); + error(index.expr, "An index must be an integer value, got %s", s); + gb_string_free(s); + } + break; + } + } + } + + for (int i = 0; scale.expr && i == 0; i++) { + if (!is_type_integer(scale.type)) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + if (scale.mode == Addressing_Constant) { + if (scale.value.kind != ExactValue_Integer) { + gbString s = exact_value_to_string(scale.value); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + } else { + Entity *param_entity = entity_of_node(scale.expr); + if (param_entity == nullptr || param_entity->kind != Entity_Variable) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + if (kind != AsmTemplateEntityDecl_Immediate) { + gbString s = expr_to_string(scale.expr); + error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); + gb_string_free(s); + break; + } + } + } + + for (int i = 0; disp.expr && i == 0; i++) { + if (disp.expr->kind == Ast_AsmRegister) { + check_register(ctx, &disp.expr->AsmRegister); + } else { + Entity *param_entity = entity_of_node(disp.expr); + if (disp.mode == Addressing_Constant) { + if (is_type_integer(disp.type)) { + break; + } + } + if (param_entity == nullptr) { + gbString s = expr_to_string(disp.expr); + error(disp.expr, "An displacement value must an integer, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + if (is_type_integer(disp.type)) { + break; + } + /*fallthrough*/ + default: + { + gbString s = expr_to_string(disp.expr); + gbString t = type_to_string(disp.type); + error(disp.expr, "An displacement must be an integer value, got %s of type %s", s, t); + gb_string_free(t); + gb_string_free(s); + } + break; + } + } + } + + return; + case_end; + case_ast_node(label, AsmLabelDecl, expr); + ast_node(name, Ident, label->name); + Entity *found = scope_lookup(label_scope, name->interned, name->hash); + if (found == nullptr) { + error(expr, "Undeclared asm label '.%.*s'", LIT(name->token.string)); + } + name->entity = found; + return; + case_end; + } + + { + gbString s = expr_to_string(expr); + error(expr, "Invalid asm operand, got %s", s); + gb_string_free(s); + } + return; +} + + +gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInfo *d) { + GB_ASSERT(entity->kind == Entity_AsmTemplate); + auto *ate = &entity->AsmTemplate; + + String asm_template_name = entity->token.string; + gb_unused(asm_template_name); + + ast_node(at, AsmTemplate, d->init_expr); + + GB_ASSERT(at->signature != nullptr); + if (at->signature->kind != Ast_ProcType) { + error(at->signature, "Expected a valid signature, got %.*s", LIT(ast_strings[at->signature->kind])); + return; + } + AstProcType *pt = &at->signature->ProcType; + + ate->param_scope = create_scope(nullptr, nullptr); + ate->label_scope = create_scope(nullptr, nullptr); + + ate->decls.allocator = heap_allocator(); + + Type *params = check_asm_template_signature_params(ctx, ate->param_scope, pt->params, true, &ate->decls); + Type *results = check_asm_template_signature_params(ctx, ate->param_scope, pt->results, false, &ate->decls); + + Type *type = alloc_type_proc(ate->param_scope, params, params->Tuple.variables.count, results, results->Tuple.variables.count, false, pt->calling_convention); + type->Proc.diverging = pt->diverging; + + entity->type = type; + + check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); + { // check clobbers + StringSet reg_set = {}; + string_set_init(®_set, 16); + defer (string_set_destroy(®_set)); + + bool clobber_cc = false; + bool clobber_memory = false; + + for (Ast *clobber_ : at->clobbers) { + ast_node(clobber, AsmClobber, clobber_); + switch (clobber->value->kind) { + case_ast_node(asm_reg, AsmRegister, clobber->value) + String reg = asm_reg->name.string; + if (check_register(ctx, asm_reg)) { + if (string_set_update(®_set, reg)) { + error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); + } + } + case_end; + case_ast_node(ident, Ident, clobber->value); + String str = ident->token.string; + if (str == "cc") { + if (clobber_cc) { + error(clobber->value, "#clobber cc has already been defined"); + } + clobber_cc = true; + } else if (str == "memory") { + if (clobber_memory) { + error(clobber->value, "#clobber memory has already been defined"); + } + clobber_memory = true; + } else { + error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); + } + case_end; + default: + error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification"); + break; + } + } + } + + // collect label decls + for (Ast *instruction_ : at->instructions) { + switch (instruction_->kind) { + case_ast_node(label, AsmLabelDecl, instruction_); + GB_ASSERT(label->name->kind == Ast_Ident); + Ast *name = label->name; + if (is_blank_ident(name)) { + error(name, "Asm label definition cannot be '_'"); + continue; + } + Entity *label_entity = alloc_entity_label(ate->label_scope, name->Ident.token, nullptr, instruction_, nullptr); + Entity *found = scope_insert(ate->label_scope, label_entity); + if (found != nullptr) { + TokenPos pos = found->token.pos; + error(name, + "Redeclaration of the label '%.*s' in this scope\n" + "\tat %s", + LIT(name->Ident.token.string), token_pos_to_string(pos)); + continue; + } + name->Ident.entity = label_entity; + case_end; + } + } + + + for (Ast *instruction_ : at->instructions) { + switch (instruction_->kind) { + case_ast_node(instr, AsmInstruction, instruction_); + GB_ASSERT(instr->name->kind == Ast_Ident); + + CheckMnemomicResult res = check_mnemonic(ctx, instr); + + for (Ast *expr : instr->operands) { + Operand operand = {}; + check_asm_instruction_operand(ctx, entity, &operand, expr, /*allow_memory_operands*/true); + } + if (res == CheckMnemomic_Prefix) { + if (instr->operands.count != 0) { + error(instr->name, "A prefix must not have any operands, and be separate from the instruction it is prefixing"); + } + } + + case_end; + case_ast_node(label, AsmLabelDecl, instruction_); + // already done + case_end; + default: + error(instruction_, "Unexpected instruction in asm template"); + break; + } + } +} \ No newline at end of file diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 8f6412b31..c70672036 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -1985,606 +1985,7 @@ gb_internal void check_proc_group_decl(CheckerContext *ctx, Entity *pg_entity, D check_objc_methods(ctx, pg_entity, ac); } -gb_internal bool is_valid_asm_parameter_type(Type *type) { - if (is_type_integer(type)) { - return true; - } - if (is_type_float(type)) { - return true; - } - if (is_type_boolean(type)) { - return true; - } - if (is_type_pointer(type) || is_type_multi_pointer(type)) { - return true; - } - if (is_type_simd_vector(type)) { - return true; - } - return false; -} - -gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { - if (is_type_integer(type)) { - return AsmRegClass_Integer; - } - if (is_type_float(type)) { - return AsmRegClass_Float; - } - if (is_type_boolean(type)) { - return AsmRegClass_Integer; - } - if (is_type_pointer(type) || is_type_multi_pointer(type)) { - return AsmRegClass_Integer; - } - if (is_type_simd_vector(type)) { - return AsmRegClass_Vector; - } - return AsmRegClass_Unknown; -} - -gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { - Type *tuple = alloc_type_tuple(); - if (_params == nullptr) { - return tuple; - } - ast_node(field_list, FieldList, _params); - Slice params = field_list->list; - - Array variables = {}; - variables.allocator = heap_allocator(); - - i32 param_index = 0; - for (Ast *param : params) { - ast_node(field, Field, param); - - bool prev = ctx->allow_polymorphic_types; - ctx->allow_polymorphic_types = false; - Type *type = check_type(ctx, field->type); - ctx->allow_polymorphic_types = prev; - - if (!is_valid_asm_parameter_type(type)) { - gbString s = type_to_string(type); - error(field->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); - gb_string_free(s); - continue; - } - - for_array(j, field->names) { - Ast *name = field->names[j]; - - bool is_poly_name = false; - - switch (name->kind) { - case Ast_Ident: - break; - case Ast_PolyType: - GB_ASSERT(name->PolyType.specialization == nullptr); - is_poly_name = true; - name = name->PolyType.type; - break; - } - - if (!ast_node_expect(name, Ast_Ident)) { - continue; - } - - if (is_blank_ident(name)) { - error(name, "All parameters must have a name in an asm template"); - continue; - } - Token name_token = name->Ident.token; - - Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); - entity->flags |= EntityFlag_Used; - if (is_poly_name) { - entity->flags |= EntityFlag_PolyConst; - if (is_type_internally_pointer_like(type)) { - error(name, "Parameters with a pointer-like type cannot be used as $ immediates"); - } - } - - Entity *found = scope_insert(scope, entity); - if (found == nullptr) { - array_add(&variables, entity); - - AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); - if (is_poly_name) { - ed.kind = AsmTemplateEntityDecl_Immediate; - } - if (input_parameters) { - ed.param_group = AsmTemplateEntityDeclParamGroup_Input; - ed.param_index = param_index++; - ed.result_index = -1; - } else { - ed.param_group = AsmTemplateEntityDeclParamGroup_Output; - ed.param_index = -1; - ed.result_index = param_index++; - } - - ed.total_index = cast(i32)asm_template_entity_decls->count; - array_add(asm_template_entity_decls, ed); - } else { - TokenPos pos = found->token.pos; - error(name_token, - "Redeclaration of '%.*s' in this scope\n" - "\tat %s", - LIT(name_token.string), token_pos_to_string(pos)); - entity = found; - } - } - } - - tuple->Tuple.variables = slice_from_array(variables); - - return tuple; -} - -gb_internal AsmTemplateEntityDeclParamGroup check_asm_find_group(Entity *entity, Array const &asm_template_entity_decls, i32 *index_) { - for_array(i, asm_template_entity_decls) { - auto const &ed = asm_template_entity_decls[i]; - if (ed.entity == entity) { - if (index_) *index_ = cast(i32)i; - return ed.param_group; - } - } - if (index_) *index_ = -1; - return AsmTemplateEntityDeclParamGroup_Unknown; -}; - -gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array const &asm_template_entity_decls) { - for (auto const &ed : asm_template_entity_decls) { - if (ed.entity == entity) { - return ed.kind; - } - } - return AsmTemplateEntityDecl_Invalid; -}; - - -gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { - StringSet pin_set = {}; - string_set_init(&pin_set, specs.count); - defer (string_set_destroy(&pin_set)); - - for (Ast *spec_ : specs) { - if (spec_->kind != Ast_AsmSpec) { - continue; - } - ast_node(spec, AsmSpec, spec_); - - GB_ASSERT(spec->name->kind == Ast_Ident); - - Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); - - bool must_check_value = false; - - String pin = {}; - if (spec->value != nullptr) { - if (spec->value->kind != Ast_AsmRegister) { - gbString s = expr_to_string(spec->value); - error(spec->value, "Expected an asm register, got %s", s); - gb_string_free(s); - continue; - } - - ast_node(reg, AsmRegister, spec->value); - pin = reg->name.string; - if (pin == "any") { - pin = {}; - } - if (pin.len != 0) { - if (string_set_update(&pin_set, pin)) { - error(spec->value, "Pinned register %%%.*s has already be assigned", LIT(pin)); - } - } - } - - if (spec->tied_name == nullptr) { - if (spec->type != nullptr) { - Type *type = check_type(ctx, spec->type); - if (!is_valid_asm_parameter_type(type)) { - gbString s = type_to_string(type); - error(spec->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); - gb_string_free(s); - continue; - } - - Token name_token = spec->name->Ident.token; - - Entity *entity = alloc_entity_param(scope, name_token, type, false, /*is_value*/true); - entity->flags |= EntityFlag_Used; - - Entity *found = scope_insert(scope, entity); - if (found == nullptr) { - AsmTemplateEntityDecl ed = asm_template_entity_decl_default(entity); - ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; - ed.total_index = cast(i32)asm_template_entity_decls->count; - ed.pin = pin; - array_add(asm_template_entity_decls, ed); - } else { - TokenPos pos = found->token.pos; - error(name_token, - "Redeclaration of '%.*s' in this scope\n" - "\tat %s", - LIT(name_token.string), token_pos_to_string(pos)); - entity = found; - continue; - } - } else if (input == nullptr) { - error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); - continue; - } else { - i32 index = -1; - auto group = check_asm_find_group(input, *asm_template_entity_decls, &index); - gb_unused(group); - GB_ASSERT(index >= 0); - auto *i = &(*asm_template_entity_decls)[index]; - if (i->pin.len == 0) { - i->pin = pin; - } else { - error(spec_, "Asm register has already been pinned"); - } - } - - } else { - GB_ASSERT(spec->tied_name->kind == Ast_Ident); - - if (spec->type != nullptr) { - error(spec->type, "Tied register definitions cannot have a defined type since the values are already defined"); - } - - if (input == nullptr) { - error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); - continue; - } - Entity *output = scope_lookup(scope, spec->tied_name->Ident.interned, spec->tied_name->Ident.hash); - if (output == nullptr) { - error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); - continue; - } - - i32 input_index = -1; - i32 output_index = -1; - - auto input_group = check_asm_find_group(input, *asm_template_entity_decls, &input_index); - auto output_group = check_asm_find_group(output, *asm_template_entity_decls, &output_index); - if (input_group != AsmTemplateEntityDeclParamGroup_Input) { - error(input->token, "Parameter tied with '%.*s' must be an input parameter", LIT(output->token.string)); - continue; - } - if (output_group != AsmTemplateEntityDeclParamGroup_Output) { - error(output->token, "Parameter tied with '%.*s' must be an output parameter", LIT(input->token.string)); - continue; - } - - GB_ASSERT(input_index >= 0); - GB_ASSERT(output_index >= 0); - - auto *i = &(*asm_template_entity_decls)[input_index]; - auto *o = &(*asm_template_entity_decls)[output_index]; - - i->tie = output_index; - o->tie = input_index; - - i->pin = pin; - o->pin = pin; - - - must_check_value = true; - } - } -} - -gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { - if (expr == nullptr) { - return; - } - - operand->expr = expr; - operand->mode = Addressing_Invalid; - operand->type = t_invalid; - - GB_ASSERT(entity->kind == Entity_AsmTemplate); - auto *ate = &entity->AsmTemplate; - - Scope *param_scope = ate->param_scope; - Scope *label_scope = ate->label_scope; - gb_unused(param_scope); - gb_unused(label_scope); - - switch (expr->kind) { - case_ast_node(i, Ident, expr); - Entity *found = scope_lookup(param_scope, i->interned, i->hash); - if (found == nullptr) { - error(expr, "Undeclared asm parameter '%.*s'", LIT(i->token.string)); - return; - } - i->entity = found; - operand->mode = Addressing_Value; - operand->type = found->type; - return; - case_end; - case_ast_node(bl, BasicLit, expr); - check_expr(ctx, operand, expr); - return; - case_end; - case_ast_node(i, AsmRegister, expr); - // TODO(bill): Check asm register - return; - case_end; - case_ast_node(mem_op, AsmMemoryOperand, expr); - if (!allow_memory_operands) { - break; - } - Operand base = {}; - Operand index = {}; - Operand scale = {}; - Operand disp = {}; - check_asm_instruction_operand(ctx, entity, &base, mem_op->base, false); - check_asm_instruction_operand(ctx, entity, &index, mem_op->index, false); - check_asm_instruction_operand(ctx, entity, &scale, mem_op->scale, false); - check_asm_instruction_operand(ctx, entity, &disp, mem_op->disp, false); - - for (int i = 0; base.expr && i == 0; i++) { - if (base.expr->kind == Ast_AsmRegister) { - // Okay for now - } else { - Entity *param_entity = entity_of_node(base.expr); - if (param_entity == nullptr || param_entity->kind != Entity_Variable) { - gbString s = expr_to_string(base.expr); - error(base.expr, "A base value must a memory parameter, got %s", s); - gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - if (kind != AsmTemplateEntityDecl_Memory) { - gbString s = expr_to_string(base.expr); - error(base.expr, "A scale must be a memory parameter, got %s", s); - gb_string_free(s); - break; - } - } - } - - for (int i = 0; index.expr && i == 0; i++) { - if (index.expr->kind == Ast_AsmRegister) { - // Okay for now - } else { - Entity *param_entity = entity_of_node(index.expr); - if (param_entity == nullptr || param_entity->kind != Entity_Variable) { - gbString s = expr_to_string(index.expr); - error(index.expr, "An index value must an integer, got %s", s); - gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - switch (kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Immediate: - // okay: - break; - default: - { - gbString s = expr_to_string(index.expr); - error(index.expr, "An index must be an integer value, got %s", s); - gb_string_free(s); - } - break; - } - } - } - - for (int i = 0; scale.expr && i == 0; i++) { - if (!is_type_integer(scale.type)) { - gbString s = expr_to_string(scale.expr); - error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); - gb_string_free(s); - break; - } - if (scale.mode == Addressing_Constant) { - if (scale.value.kind != ExactValue_Integer) { - gbString s = exact_value_to_string(scale.value); - error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); - gb_string_free(s); - break; - } - } else { - Entity *param_entity = entity_of_node(scale.expr); - if (param_entity == nullptr || param_entity->kind != Entity_Variable) { - gbString s = expr_to_string(scale.expr); - error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); - gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - if (kind != AsmTemplateEntityDecl_Immediate) { - gbString s = expr_to_string(scale.expr); - error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); - gb_string_free(s); - break; - } - } - } - - for (int i = 0; disp.expr && i == 0; i++) { - if (disp.expr->kind == Ast_AsmRegister) { - // Okay for now - } else { - Entity *param_entity = entity_of_node(disp.expr); - if (disp.mode == Addressing_Constant) { - if (is_type_integer(disp.type)) { - break; - } - } - if (param_entity == nullptr) { - gbString s = expr_to_string(disp.expr); - error(disp.expr, "An displacement value must an integer, got %s", s); - gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - switch (kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Immediate: - if (is_type_integer(disp.type)) { - break; - } - /*fallthrough*/ - default: - { - gbString s = expr_to_string(disp.expr); - gbString t = type_to_string(disp.type); - error(disp.expr, "An displacement must be an integer value, got %s of type %s", s, t); - gb_string_free(t); - gb_string_free(s); - } - break; - } - } - } - - return; - case_end; - case_ast_node(label, AsmLabelDecl, expr); - ast_node(name, Ident, label->name); - Entity *found = scope_lookup(label_scope, name->interned, name->hash); - if (found == nullptr) { - error(expr, "Undeclared asm label '.%.*s'", LIT(name->token.string)); - } - name->entity = found; - return; - case_end; - } - - { - gbString s = expr_to_string(expr); - error(expr, "Invalid asm operand, got %s", s); - gb_string_free(s); - } - return; -} - - -gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInfo *d) { - GB_ASSERT(entity->kind == Entity_AsmTemplate); - auto *ate = &entity->AsmTemplate; - - String asm_template_name = entity->token.string; - gb_unused(asm_template_name); - - ast_node(at, AsmTemplate, d->init_expr); - - GB_ASSERT(at->signature != nullptr); - if (at->signature->kind != Ast_ProcType) { - error(at->signature, "Expected a valid signature, got %.*s", LIT(ast_strings[at->signature->kind])); - return; - } - AstProcType *pt = &at->signature->ProcType; - - ate->param_scope = create_scope(nullptr, nullptr); - ate->label_scope = create_scope(nullptr, nullptr); - - ate->decls.allocator = heap_allocator(); - - Type *params = check_asm_template_signature_params(ctx, ate->param_scope, pt->params, true, &ate->decls); - Type *results = check_asm_template_signature_params(ctx, ate->param_scope, pt->results, false, &ate->decls); - - Type *type = alloc_type_proc(ate->param_scope, params, params->Tuple.variables.count, results, results->Tuple.variables.count, false, pt->calling_convention); - type->Proc.diverging = pt->diverging; - - entity->type = type; - - check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); - { // check clobbers - StringSet reg_set = {}; - string_set_init(®_set, 16); - defer (string_set_destroy(®_set)); - - bool clobber_cc = false; - bool clobber_memory = false; - - for (Ast *clobber_ : at->clobbers) { - ast_node(clobber, AsmClobber, clobber_); - switch (clobber->value->kind) { - case Ast_AsmRegister: - { - String reg = clobber->value->AsmRegister.name.string; - if (string_set_update(®_set, reg)) { - error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); - } - // TODO(bill): register check for validity - } - break; - case Ast_Ident: - { - String str = clobber->value->Ident.token.string; - if (str == "cc") { - if (clobber_cc) { - error(clobber->value, "#clobber cc has already been defined"); - } - clobber_cc = true; - } else if (str == "memory") { - if (clobber_memory) { - error(clobber->value, "#clobber memory has already been defined"); - } - clobber_memory = true; - } else { - error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); - } - break; - } - default: - error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification"); - break; - } - } - } - - // collect label decls - for (Ast *instruction_ : at->instructions) { - switch (instruction_->kind) { - case_ast_node(label, AsmLabelDecl, instruction_); - GB_ASSERT(label->name->kind == Ast_Ident); - Ast *name = label->name; - if (is_blank_ident(name)) { - error(name, "Asm label definition cannot be '_'"); - continue; - } - Entity *label_entity = alloc_entity_label(ate->label_scope, name->Ident.token, nullptr, instruction_, nullptr); - Entity *found = scope_insert(ate->label_scope, label_entity); - if (found != nullptr) { - TokenPos pos = found->token.pos; - error(name, - "Redeclaration of the label '%.*s' in this scope\n" - "\tat %s", - LIT(name->Ident.token.string), token_pos_to_string(pos)); - continue; - } - name->Ident.entity = label_entity; - case_end; - } - } - - - for (Ast *instruction_ : at->instructions) { - switch (instruction_->kind) { - case_ast_node(instr, AsmInstruction, instruction_); - GB_ASSERT(instr->name->kind == Ast_Ident); - for (Ast *expr : instr->operands) { - Operand operand = {}; - check_asm_instruction_operand(ctx, entity, &operand, expr, /*allow_memory_operands*/true); - } - case_end; - case_ast_node(label, AsmLabelDecl, instruction_); - // already done - case_end; - default: - error(instruction_, "Unexpected instruction in asm template"); - break; - } - } -} +#include "check_asm.cpp" gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, Type *named_type) { diff --git a/src/main.cpp b/src/main.cpp index d3e4c2b60..6afaf08df 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -4313,6 +4313,11 @@ int main(int arg_count, char const **arg_ptr) { Checker *checker = permanent_alloc_item(); bool failed_to_cache_parsing = false; + TIME_SECTION("init asm tables"); + { + g_asm_amd64.init(); + } + MAIN_TIME_SECTION("parse files"); if (!init_parser(parser)) { From 5ca7638bb21710d1d3e8f97fca66652df13c2d7d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 11:11:53 +0100 Subject: [PATCH 14/92] Check asm instruction operand count --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 17 ++--- src/asm_tables_amd64.cpp | 17 ++--- src/check_asm.cpp | 73 ++++++++++++++++--- 3 files changed, 77 insertions(+), 30 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 89c3cf596..8418b99b4 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -174,14 +174,14 @@ main :: proc() { } { bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "explicit_count") - bit_size := intrinsics.type_field_bit_offset(Encoding_Flags, "explicit_count") + bit_size := intrinsics.type_field_bit_size(Encoding_Flags, "explicit_count") strings.write_string(&sb, "\t\tu8 explicit_count() const { ") fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) strings.write_string(&sb, " }\n") } { bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "op_count") - bit_size := intrinsics.type_field_bit_offset(Encoding_Flags, "op_count") + bit_size := intrinsics.type_field_bit_size(Encoding_Flags, "op_count") strings.write_string(&sb, "\t\tu8 op_count () const { ") fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) strings.write_string(&sb, " }\n") @@ -203,8 +203,6 @@ main :: proc() { strings.write_string(&sb, "\tStringMap mnemonic_map;\n") strings.write_string(&sb, "\tStringMap prefix_map;\n") strings.write_string(&sb, "\tStringMap register_map;\n") - strings.write_string(&sb, "\tSlice ENCODE_RUNS;\n") - strings.write_string(&sb, "\tSlice ENCODE_FORMS;\n") { strings.write_string(&sb, "\tbool init() {\n") @@ -246,15 +244,16 @@ main :: proc() { strings.write_string(&sb, "\t\treturn found ? *found : REG_INVALID;\n") } { - strings.write_string(&sb, "\tSlice encoding_forms(Mnemonic m) const {\n") + strings.write_string(&sb, "\tSlice encoding_forms(/*Mnemonic*/ u16 m) const {\n") defer strings.write_string(&sb, "\t}\n") - strings.write_string(&sb, "\t\tEncodeRun r = ENCODE_RUNS[m];\n") - strings.write_string(&sb, "\t\treturn slice_lower_and_count(ENCODE_FORMS, r.start, r.count);\n") + strings.write_string(&sb, "\t\tEncodeRun r = raw_encode_runs[m];\n") + strings.write_string(&sb, "\t\tEncoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms;\n") + strings.write_string(&sb, "\t\treturn Slice{ENCODE_FORMS+r.start, r.count};\n") } { - strings.write_string(&sb, "\tu16 reg_class(Register r) const {\n") - strings.write_string(&sb, "\t\treturn 0xFF00 & cast(u16)r;\n") + strings.write_string(&sb, "\tu16 reg_class(/*Register*/ u16 r) const {\n") + strings.write_string(&sb, "\t\treturn 0xFF00 & r;\n") strings.write_string(&sb, "\t}\n") } { diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 2d8ba1557..2c8848ba0 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -229,8 +229,8 @@ struct Asm_amd64 { EncodingFlags flags; bool has_implicit () const { return ((flags>>21u)&1) != 0; } - u8 explicit_count() const { return cast(u8)((flags>>18u)&((1u<<18)-1)); } - u8 op_count () const { return cast(u8)((flags>>22u)&((1u<<22)-1)); } + u8 explicit_count() const { return cast(u8)((flags>>18u)&((1u<<3)-1)); } + u8 op_count () const { return cast(u8)((flags>>22u)&((1u<<3)-1)); } }; #pragma pack(pop) GB_STATIC_ASSERT(gb_size_of(Encoding) == 16); @@ -248,8 +248,6 @@ struct Asm_amd64 { StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; - Slice ENCODE_RUNS; - Slice ENCODE_FORMS; bool init() { string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { @@ -277,12 +275,13 @@ struct Asm_amd64 { Register *found = string_map_get(®ister_map, name); return found ? *found : REG_INVALID; } - Slice encoding_forms(Mnemonic m) const { - EncodeRun r = ENCODE_RUNS[m]; - return slice_lower_and_count(ENCODE_FORMS, r.start, r.count); + Slice encoding_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; + return Slice{ENCODE_FORMS+r.start, r.count}; } - u16 reg_class(Register r) const { - return 0xFF00 & cast(u16)r; + u16 reg_class(/*Register*/ u16 r) const { + return 0xFF00 & r; } // size in bits for register u16 reg_size(Register r) const { diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 828d6af93..3b73d5114 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -290,7 +290,7 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } } -gb_internal bool check_register(CheckerContext *ctx, AstAsmRegister *asm_reg) { +gb_internal bool check_register(AstAsmRegister *asm_reg) { String name = asm_reg->name.string; auto r = g_asm_amd64.register_lookup(name); if (r) { @@ -306,10 +306,11 @@ enum CheckMnemomicResult { CheckMnemomic_Prefix, }; -gb_internal CheckMnemomicResult check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instruction) { - String name = instruction->name->Ident.token.string; +gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u16 *mnemonic_) { + String name = instr->name->Ident.token.string; auto m = g_asm_amd64.mnemonic_lookup(name); if (m) { + if (mnemonic_) *mnemonic_ = cast(u16)m; return CheckMnemomic_Mnemonic; } auto p = g_asm_amd64.prefix_lookup(name); @@ -317,14 +318,50 @@ gb_internal CheckMnemomicResult check_mnemonic(CheckerContext *ctx, AstAsmInstru return CheckMnemomic_Prefix; } - if (instruction->operands.count == 0) { - error(instruction->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); + if (instr->operands.count == 0) { + error(instr->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); } else { - error(instruction->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); + error(instr->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); } return CheckMnemomic_Invalid; } +gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands) { + GB_ASSERT(mnemonic > 0); + auto forms = g_asm_amd64.encoding_forms(mnemonic); + String name = g_asm_amd64.mnemonic_strings[mnemonic]; + + int min_count = I32_MAX; + int max_count = -1; + + bool ok = false; + + for (auto form : forms) { + int explicit_count = cast(int)form.explicit_count(); + min_count = gb_min(min_count, explicit_count); + max_count = gb_max(min_count, explicit_count); + if (operands.count != explicit_count) { + continue; + } + ok = true; // pretend for the time being + } + + if (operands.count < min_count || operands.count > max_count) { + if (min_count == max_count) { + error(instr->name, "The asm instruction '%.*s' expects %d operands, got %d", LIT(name), max_count, operands.count); + } else { + error(instr->name, "The asm instruction '%.*s' expects %d..=%d operands, got %d", LIT(name), min_count, max_count, operands.count); + } + return; + } + if (ok) { + return; + } + + error(instr->name, "The operands to '%.*s' matched non of the expected encoding forms", LIT(name)); +} + + gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { if (expr == nullptr) { @@ -360,7 +397,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti return; case_end; case_ast_node(asm_reg, AsmRegister, expr); - check_register(ctx, asm_reg); + check_register(asm_reg); return; case_end; case_ast_node(mem_op, AsmMemoryOperand, expr); @@ -378,7 +415,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; base.expr && i == 0; i++) { if (base.expr->kind == Ast_AsmRegister) { - check_register(ctx, &base.expr->AsmRegister); + check_register(&base.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(base.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -399,7 +436,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; index.expr && i == 0; i++) { if (index.expr->kind == Ast_AsmRegister) { - check_register(ctx, &index.expr->AsmRegister); + check_register(&index.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(index.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -459,7 +496,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; disp.expr && i == 0; i++) { if (disp.expr->kind == Ast_AsmRegister) { - check_register(ctx, &disp.expr->AsmRegister); + check_register(&disp.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(disp.expr); if (disp.mode == Addressing_Constant) { @@ -559,7 +596,7 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf switch (clobber->value->kind) { case_ast_node(asm_reg, AsmRegister, clobber->value) String reg = asm_reg->name.string; - if (check_register(ctx, asm_reg)) { + if (check_register(asm_reg)) { if (string_set_update(®_set, reg)) { error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); } @@ -614,21 +651,33 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf } + Array operands = {}; + operands.allocator = heap_allocator(); + array_reserve(&operands, 16); + defer (array_free(&operands)); + for (Ast *instruction_ : at->instructions) { switch (instruction_->kind) { case_ast_node(instr, AsmInstruction, instruction_); GB_ASSERT(instr->name->kind == Ast_Ident); - CheckMnemomicResult res = check_mnemonic(ctx, instr); + u16 mnemonic = 0; + CheckMnemomicResult res = check_mnemonic_name(instr, &mnemonic); + + + array_clear(&operands); for (Ast *expr : instr->operands) { Operand operand = {}; check_asm_instruction_operand(ctx, entity, &operand, expr, /*allow_memory_operands*/true); + array_add(&operands, operand); } if (res == CheckMnemomic_Prefix) { if (instr->operands.count != 0) { error(instr->name, "A prefix must not have any operands, and be separate from the instruction it is prefixing"); } + } else if (res == CheckMnemomic_Mnemonic) { + check_mnemonic(ctx, instr, mnemonic, slice_from_array(operands)); } case_end; From 400203c344ba376b64fe58a36cb8aa368062d78e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 11:47:48 +0100 Subject: [PATCH 15/92] Verify the asm instruction operands against the `Encoding.ops` --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 67 +++++++++++++- src/asm_tables.cpp | 10 +++ src/asm_tables_amd64.cpp | 33 +++++++ src/check_asm.cpp | 90 +++++++++++++++++-- src/main.cpp | 2 +- 5 files changed, 194 insertions(+), 8 deletions(-) create mode 100644 src/asm_tables.cpp diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 8418b99b4..bd60c3f18 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -140,7 +140,7 @@ main :: proc() { { strings.write_string(&sb, "\tenum OperandEncoding : u8 {\n") defer strings.write_string(&sb, "\t};\n") - for op in type_of(gen.Encoding{}.enc[0]) { + for op in Operand_Encoding { fmt.sbprintf(&sb, "\t\tENC_%s,\n", op) } @@ -279,7 +279,41 @@ main :: proc() { strings.write_string(&sb, "\t\treturn 0;\n") strings.write_string(&sb, "\t}\n") } - + { + strings.write_string(&sb, "\tAsmOperandKind kind_from_operand_type(OperandType type) {\n") + strings.write_string(&sb, "\t\tswitch (type) {\n") + strings.write_string(&sb, "\t\tcase OP_R8: case OP_R16: case OP_R32: case OP_R64:\n") + strings.write_string(&sb, "\t\tcase OP_SREG: case OP_CR: case OP_DR:\n") + strings.write_string(&sb, "\t\tcase OP_XMM: case OP_YMM: case OP_ZMM:\n") + strings.write_string(&sb, "\t\tcase OP_MM: case OP_K: case OP_STI:\n") + strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_ST0_IMPL: case OP_XMM0_IMPL:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Register;\n") + strings.write_string(&sb, "\t\tcase OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64:\n") + strings.write_string(&sb, "\t\tcase OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128:\n") + strings.write_string(&sb, "\t\tcase OP_YMM_M256: case OP_ZMM_M512:\n") + strings.write_string(&sb, "\t\tcase OP_MM_M64:\n") + strings.write_string(&sb, "\t\tcase OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Register_Or_Memory;\n") + strings.write_string(&sb, "\t\tcase OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64:\n") + strings.write_string(&sb, "\t\tcase OP_M80: case OP_M128: case OP_M256: case OP_M512:\n") + strings.write_string(&sb, "\t\tcase OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64:\n") + strings.write_string(&sb, "\t\tcase OP_M16_16: case OP_M16_32: case OP_M16_64:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Memory;\n") + strings.write_string(&sb, "\t\tcase OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64:\n") + strings.write_string(&sb, "\t\tcase OP_IMM8SX:\n") + strings.write_string(&sb, "\t\tcase OP_ONE_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Immediate;\n") + strings.write_string(&sb, "\t\tcase OP_REL8: case OP_REL32:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Label;\n") + strings.write_string(&sb, "\t\tcase OP_NONE:\n") + strings.write_string(&sb, "\t\tdefault:\n") + strings.write_string(&sb, "\t\t\treturn AsmOperand_Invalid;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t}\n") + } strings.write_string(&sb, "};\n") @@ -447,6 +481,35 @@ main :: proc() { } } +Operand_Encoding :: type_of(gen.Encoding{}.enc[0]) + +Asm_Operand_Kind :: enum u8 { + Invalid, + Register, + Memory, + Register_Or_Memory, + Immediate, + Label, +} + + +@(rodata) +operand_encoding_to_kind := [Operand_Encoding]Asm_Operand_Kind{ + .NONE = .Invalid, + .MR = .Register_Or_Memory, + .REG = .Register, + .VVVV = .Register, + .OP_R = .Register, + .IS4 = .Register, + .AAA = .Register, + .IMPL = .Register, + .IB = .Immediate, + .IW = .Immediate, + .ID = .Immediate, + .IQ = .Immediate, +} + + Prefix :: enum u8 { INVALID, ES, diff --git a/src/asm_tables.cpp b/src/asm_tables.cpp new file mode 100644 index 000000000..335efe4d9 --- /dev/null +++ b/src/asm_tables.cpp @@ -0,0 +1,10 @@ +enum AsmOperandKind : u8 { + AsmOperand_Invalid, + AsmOperand_Register, + AsmOperand_Memory, + AsmOperand_Register_Or_Memory, + AsmOperand_Immediate, + AsmOperand_Label, +}; + +#include "asm_tables_amd64.cpp" \ No newline at end of file diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 2c8848ba0..5d236e91f 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -304,6 +304,39 @@ struct Asm_amd64 { } return 0; } + AsmOperandKind kind_from_operand_type(OperandType type) { + switch (type) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_SREG: case OP_CR: case OP_DR: + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_MM: case OP_K: case OP_STI: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + case OP_ST0_IMPL: case OP_XMM0_IMPL: + return AsmOperand_Register; + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_MM_M64: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmOperand_Register_Or_Memory; + case OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64: + case OP_M80: case OP_M128: case OP_M256: case OP_M512: + case OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64: + case OP_M16_16: case OP_M16_32: case OP_M16_64: + return AsmOperand_Memory; + case OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64: + case OP_IMM8SX: + case OP_ONE_IMPL: + case OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64: + return AsmOperand_Immediate; + case OP_REL8: case OP_REL32: + return AsmOperand_Label; + case OP_NONE: + default: + return AsmOperand_Invalid; + } + } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 3b73d5114..6e0891793 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -315,6 +315,7 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 } auto p = g_asm_amd64.prefix_lookup(name); if (p) { + if (mnemonic_) *mnemonic_ = cast(u16)p; return CheckMnemomic_Prefix; } @@ -326,7 +327,38 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 return CheckMnemomic_Invalid; } -gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands) { +gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { + if (operand->mode == Addressing_Constant) { + return AsmOperand_Immediate; + } + Ast *expr = operand->expr; + switch (expr->kind) { + case_ast_node(label, AsmLabelDecl, expr); + return AsmOperand_Label; + case_end; + case_ast_node(reg, AsmRegister, expr); + return AsmOperand_Register; + case_end; + case_ast_node(reg, AsmMemoryOperand, expr); + return AsmOperand_Memory; + case_end; + case_ast_node(ident, Ident, expr); + // TODO(bill): Is this correct? + if (expr->tav.mode == Addressing_Constant) { + return AsmOperand_Immediate; + } + Entity *e = entity_of_node(expr); + if (e != nullptr && e->kind == Entity_Variable && (e->flags & EntityFlag_PolyConst) != 0) { + return AsmOperand_Immediate; + } + return AsmOperand_Register; + case_end; + } + return AsmOperand_Invalid; +} + + +gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix) { GB_ASSERT(mnemonic > 0); auto forms = g_asm_amd64.encoding_forms(mnemonic); String name = g_asm_amd64.mnemonic_strings[mnemonic]; @@ -334,8 +366,20 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u int min_count = I32_MAX; int max_count = -1; - bool ok = false; + for (auto form : forms) { + int explicit_count = cast(int)form.explicit_count(); + min_count = gb_min(min_count, explicit_count); + max_count = gb_max(min_count, explicit_count); + } + min_count = gb_max(min_count, 0); + max_count = gb_max(max_count, 0); + isize valid_form_index = -1; + + auto valid_spots = slice_make(heap_allocator(), max_count); + defer (slice_free(&valid_spots, heap_allocator())); + + bool ok = true; for (auto form : forms) { int explicit_count = cast(int)form.explicit_count(); min_count = gb_min(min_count, explicit_count); @@ -343,7 +387,29 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u if (operands.count != explicit_count) { continue; } - ok = true; // pretend for the time being + + ok = true; + for_array(i, operands) { + auto type = form.ops[i]; + Operand const *operand = &operands[i]; + AsmOperandKind dst_kind = g_asm_amd64.kind_from_operand_type(type); + AsmOperandKind src_kind = determine_asm_operand_kind(operand); + if (dst_kind == src_kind) { + valid_spots[i] = true; + continue; + } + if (dst_kind == AsmOperand_Register_Or_Memory && + (src_kind == AsmOperand_Register || src_kind == AsmOperand_Memory)) { + valid_spots[i] = true; + continue; + } + ok = false; + break; + } + if (ok) { + // the result has been found to be correct + break; + } } if (operands.count < min_count || operands.count > max_count) { @@ -355,10 +421,21 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u return; } if (ok) { + if (valid_form_index >= 0 && previous_prefix > 0) { + // TODO(bill): validate the prefix for the selected form + } + return; } - error(instr->name, "The operands to '%.*s' matched non of the expected encoding forms", LIT(name)); + { + error(instr->name, "The operands to '%.*s' matched non of the expected encoding forms", LIT(name)); + for_array(i, valid_spots) { + if (!valid_spots[i] && i < operands.count) { + error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s'", LIT(name)); + } + } + } } @@ -657,6 +734,8 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf defer (array_free(&operands)); for (Ast *instruction_ : at->instructions) { + u8 previous_prefix = 0; + switch (instruction_->kind) { case_ast_node(instr, AsmInstruction, instruction_); GB_ASSERT(instr->name->kind == Ast_Ident); @@ -676,8 +755,9 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf if (instr->operands.count != 0) { error(instr->name, "A prefix must not have any operands, and be separate from the instruction it is prefixing"); } + previous_prefix = cast(u8)mnemonic; } else if (res == CheckMnemomic_Mnemonic) { - check_mnemonic(ctx, instr, mnemonic, slice_from_array(operands)); + check_mnemonic(ctx, instr, mnemonic, slice_from_array(operands), previous_prefix); } case_end; diff --git a/src/main.cpp b/src/main.cpp index 6afaf08df..aeefd09b6 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -68,7 +68,7 @@ gb_global Timings global_timings = {0}; #include "parser.hpp" #include "checker.hpp" -#include "asm_tables_amd64.cpp" +#include "asm_tables.cpp" #include "parser.cpp" #include "checker.cpp" From b0364d2c6092fa027fc71256d8eacfd8775edc36 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 11:56:03 +0100 Subject: [PATCH 16/92] Improve error message for invalid operand kinds --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 2 +- src/asm_tables.cpp | 20 +++++++++++++++++++ src/asm_tables_amd64.cpp | 2 +- src/check_asm.cpp | 16 +++++++++++++-- 4 files changed, 36 insertions(+), 4 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index bd60c3f18..db7064914 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -320,7 +320,7 @@ main :: proc() { strings.write_string(&sb, "\n\n\n") - fmt.sbprintf(&sb, "gb_internal Asm_{0:s} g_asm_{0:s};\n", ISA_NAME) + fmt.sbprintf(&sb, "gb_global Asm_{0:s} g_asm_{0:s};\n", ISA_NAME) strings.write_string(&sb, "\n\n\n") diff --git a/src/asm_tables.cpp b/src/asm_tables.cpp index 335efe4d9..df68ce1b8 100644 --- a/src/asm_tables.cpp +++ b/src/asm_tables.cpp @@ -5,6 +5,26 @@ enum AsmOperandKind : u8 { AsmOperand_Register_Or_Memory, AsmOperand_Immediate, AsmOperand_Label, + + AsmOperand_COUNT +}; + +gb_global String const asm_operand_kind_strings[AsmOperand_COUNT] = { + str_lit(""), + str_lit("register"), + str_lit("memory"), + str_lit("register or memory"), + str_lit("immediate"), + str_lit("label"), +}; + +gb_global String const asm_operand_kind_expected_strings[AsmOperand_COUNT] = { + str_lit(""), + str_lit("a register"), + str_lit("a memory"), + str_lit("a register or memory"), + str_lit("an immediate"), + str_lit("a label"), }; #include "asm_tables_amd64.cpp" \ No newline at end of file diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 5d236e91f..e7853bd31 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -341,7 +341,7 @@ struct Asm_amd64 { -gb_internal Asm_amd64 g_asm_amd64; +gb_global Asm_amd64 g_asm_amd64; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 6e0891793..bbdeb34c3 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -379,6 +379,9 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u auto valid_spots = slice_make(heap_allocator(), max_count); defer (slice_free(&valid_spots, heap_allocator())); + auto possible_kinds = slice_make(heap_allocator(), max_count); + defer (slice_free(&possible_kinds, heap_allocator())); + bool ok = true; for (auto form : forms) { int explicit_count = cast(int)form.explicit_count(); @@ -394,6 +397,11 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u Operand const *operand = &operands[i]; AsmOperandKind dst_kind = g_asm_amd64.kind_from_operand_type(type); AsmOperandKind src_kind = determine_asm_operand_kind(operand); + + // TODO(bill): Is this even correct logic for determine the best error message for the possible operand kinds? + // for partially correct forms of the instruction? + possible_kinds[i] = dst_kind; + if (dst_kind == src_kind) { valid_spots[i] = true; continue; @@ -404,7 +412,6 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u continue; } ok = false; - break; } if (ok) { // the result has been found to be correct @@ -432,7 +439,12 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u error(instr->name, "The operands to '%.*s' matched non of the expected encoding forms", LIT(name)); for_array(i, valid_spots) { if (!valid_spots[i] && i < operands.count) { - error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s'", LIT(name)); + auto kind = possible_kinds[i]; + if (kind) { + error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s', expected %.*s operand", LIT(name), LIT(asm_operand_kind_expected_strings[kind])); + } else { + error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s'", LIT(name)); + } } } } From 098945c358fc1614a23e3ad7ad66030e7487fd4c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 12:10:32 +0100 Subject: [PATCH 17/92] Fix some bugs and add "Did you mean" for the mnemonics --- src/check_asm.cpp | 55 +++++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index bbdeb34c3..4a6d6e40d 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -322,7 +322,15 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 if (instr->operands.count == 0) { error(instr->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); } else { + ERROR_BLOCK(); error(instr->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); + auto dym = did_you_mean_make(heap_allocator(), g_asm_amd64.MNEMONIC_COUNT, name); + defer (did_you_mean_destroy(&dym)); + for (String const &str : g_asm_amd64.mnemonic_strings) { + did_you_mean_append(&dym, str); + } + check_did_you_mean_print(&dym); + } return CheckMnemomic_Invalid; } @@ -369,12 +377,11 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u for (auto form : forms) { int explicit_count = cast(int)form.explicit_count(); min_count = gb_min(min_count, explicit_count); - max_count = gb_max(min_count, explicit_count); + max_count = gb_max(max_count, explicit_count); } min_count = gb_max(min_count, 0); max_count = gb_max(max_count, 0); - isize valid_form_index = -1; auto valid_spots = slice_make(heap_allocator(), max_count); defer (slice_free(&valid_spots, heap_allocator())); @@ -382,16 +389,18 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u auto possible_kinds = slice_make(heap_allocator(), max_count); defer (slice_free(&possible_kinds, heap_allocator())); - bool ok = true; - for (auto form : forms) { - int explicit_count = cast(int)form.explicit_count(); - min_count = gb_min(min_count, explicit_count); - max_count = gb_max(min_count, explicit_count); - if (operands.count != explicit_count) { + bool matched = false; + isize valid_form_index = -1; + isize best_form = -1; + int best_score = -1; + + for_array(form_index, forms) { + auto &form = forms[form_index]; + if (operands.count != cast(int)form.explicit_count()) { continue; } - ok = true; + int score = 0; for_array(i, operands) { auto type = form.ops[i]; Operand const *operand = &operands[i]; @@ -402,32 +411,36 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u // for partially correct forms of the instruction? possible_kinds[i] = dst_kind; - if (dst_kind == src_kind) { + bool spot_ok = (dst_kind == src_kind) || + (dst_kind == AsmOperand_Register_Or_Memory && + (src_kind == AsmOperand_Register || src_kind == AsmOperand_Memory)); + + if (spot_ok) { + score += 1; valid_spots[i] = true; - continue; } - if (dst_kind == AsmOperand_Register_Or_Memory && - (src_kind == AsmOperand_Register || src_kind == AsmOperand_Memory)) { - valid_spots[i] = true; - continue; - } - ok = false; } - if (ok) { + if (score == operands.count) { // the result has been found to be correct + matched = true; + valid_form_index = form_index; break; } + if (score > best_score) { + best_score = score; + best_form = form_index; + } } if (operands.count < min_count || operands.count > max_count) { if (min_count == max_count) { - error(instr->name, "The asm instruction '%.*s' expects %d operands, got %d", LIT(name), max_count, operands.count); + error(instr->name, "The asm instruction '%.*s' expects %d operands, got %td", LIT(name), max_count, operands.count); } else { - error(instr->name, "The asm instruction '%.*s' expects %d..=%d operands, got %d", LIT(name), min_count, max_count, operands.count); + error(instr->name, "The asm instruction '%.*s' expects %d..=%d operands, got %td", LIT(name), min_count, max_count, operands.count); } return; } - if (ok) { + if (matched) { if (valid_form_index >= 0 && previous_prefix > 0) { // TODO(bill): validate the prefix for the selected form } From 76808ab97f7a7a5544fe2886e4c0c49f7aa4ecf9 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 12:14:31 +0100 Subject: [PATCH 18/92] Improve did you mean for asm mnemonics and prefixes --- src/check_asm.cpp | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 4a6d6e40d..17637a3ad 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -319,19 +319,26 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 return CheckMnemomic_Prefix; } + ERROR_BLOCK(); if (instr->operands.count == 0) { error(instr->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); } else { - ERROR_BLOCK(); error(instr->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); - auto dym = did_you_mean_make(heap_allocator(), g_asm_amd64.MNEMONIC_COUNT, name); - defer (did_you_mean_destroy(&dym)); - for (String const &str : g_asm_amd64.mnemonic_strings) { - did_you_mean_append(&dym, str); - } - check_did_you_mean_print(&dym); } + auto dym = did_you_mean_make(heap_allocator(), g_asm_amd64.MNEMONIC_COUNT, name); + defer (did_you_mean_destroy(&dym)); + for (u16 i = g_asm_amd64.M_INVALID+1; i < g_asm_amd64.MNEMONIC_COUNT; i++) { + String str = g_asm_amd64.mnemonic_strings[i]; + did_you_mean_append(&dym, str); + } + if (instr->operands.count == 0) { + for (u16 i = g_asm_amd64.PREFIX_INVALID+1; i < g_asm_amd64.PREFIX_COUNT; i++) { + String str = g_asm_amd64.prefix_strings[i]; + did_you_mean_append(&dym, str); + } + } + check_did_you_mean_print(&dym); return CheckMnemomic_Invalid; } From 72867df848f000350f8073d39687df71f98d6d45 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 12:23:26 +0100 Subject: [PATCH 19/92] Fix typos and bugs. --- src/check_asm.cpp | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 17637a3ad..ea807fe97 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -59,7 +59,7 @@ gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope if (!is_valid_asm_parameter_type(type)) { gbString s = type_to_string(type); - error(field->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + error(field->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", s); gb_string_free(s); continue; } @@ -171,8 +171,6 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); - bool must_check_value = false; - String pin = {}; if (spec->value != nullptr) { if (spec->value->kind != Ast_AsmRegister) { @@ -189,7 +187,7 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } if (pin.len != 0) { if (string_set_update(&pin_set, pin)) { - error(spec->value, "Pinned register %%%.*s has already be assigned", LIT(pin)); + error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); } } } @@ -283,9 +281,6 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice i->pin = pin; o->pin = pin; - - - must_check_value = true; } } } @@ -321,9 +316,9 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 ERROR_BLOCK(); if (instr->operands.count == 0) { - error(instr->name, "Unknown mnemonic/prefix for this target platform: %%%.*s", LIT(name)); + error(instr->name, "Unknown mnemonic/prefix for this target platform: %.*s", LIT(name)); } else { - error(instr->name, "Unknown mnemonic for this target platform: %%%.*s", LIT(name)); + error(instr->name, "Unknown mnemonic for this target platform: %.*s", LIT(name)); } auto dym = did_you_mean_make(heap_allocator(), g_asm_amd64.MNEMONIC_COUNT, name); @@ -411,16 +406,11 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u for_array(i, operands) { auto type = form.ops[i]; Operand const *operand = &operands[i]; - AsmOperandKind dst_kind = g_asm_amd64.kind_from_operand_type(type); - AsmOperandKind src_kind = determine_asm_operand_kind(operand); + AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(type); + AsmOperandKind src = determine_asm_operand_kind(operand); - // TODO(bill): Is this even correct logic for determine the best error message for the possible operand kinds? - // for partially correct forms of the instruction? - possible_kinds[i] = dst_kind; - - bool spot_ok = (dst_kind == src_kind) || - (dst_kind == AsmOperand_Register_Or_Memory && - (src_kind == AsmOperand_Register || src_kind == AsmOperand_Memory)); + bool spot_ok = (dst == src) || + (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); if (spot_ok) { score += 1; @@ -455,8 +445,20 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u return; } + // failure path + if (best_form >= 0) { + auto &form = forms[best_form]; + for_array(i, operands) { + AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(form.ops[i]); + AsmOperandKind src = determine_asm_operand_kind(&operands[i]); + possible_kinds[i] = dst; + valid_spots[i] = (dst == src) || + (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + } + } + { - error(instr->name, "The operands to '%.*s' matched non of the expected encoding forms", LIT(name)); + error(instr->name, "The operands to '%.*s' matched none of the expected encoding forms", LIT(name)); for_array(i, valid_spots) { if (!valid_spots[i] && i < operands.count) { auto kind = possible_kinds[i]; @@ -529,14 +531,14 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti Entity *param_entity = entity_of_node(base.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { gbString s = expr_to_string(base.expr); - error(base.expr, "A base value must a memory parameter, got %s", s); + error(base.expr, "A base value must be a memory parameter, got %s", s); gb_string_free(s); break; } auto kind = check_asm_find_kind(param_entity, ate->decls); if (kind != AsmTemplateEntityDecl_Memory) { gbString s = expr_to_string(base.expr); - error(base.expr, "A scale must be a memory parameter, got %s", s); + error(base.expr, "A base value must be a memory parameter, got %s", s); gb_string_free(s); break; } From c717cb4ae96653d5de7ed31020b2c59d27c5b849 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 13:08:39 +0100 Subject: [PATCH 20/92] Implement `check_asm_operand_size_class` --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 53 ++++- src/asm_tables.cpp | 9 + src/asm_tables_amd64.cpp | 47 +++- src/check_asm.cpp | 225 ++++++++++++++++-- src/entity.cpp | 8 - 5 files changed, 315 insertions(+), 27 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index db7064914..8129f4fbc 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -259,7 +259,7 @@ main :: proc() { { strings.write_string(&sb, "\t// size in bits for register\n") strings.write_string(&sb, "\tu16 reg_size(Register r) const {\n") - strings.write_string(&sb, "\t\tswitch (reg_class(r)) {\n") + strings.write_string(&sb, "\t\tswitch (reg_class(register_codes[r])) {\n") strings.write_string(&sb, "\t\tcase REG_CLASS_GPR64: return 64;\n") strings.write_string(&sb, "\t\tcase REG_CLASS_GPR32: return 32;\n") strings.write_string(&sb, "\t\tcase REG_CLASS_GPR16: return 16;\n") @@ -279,6 +279,7 @@ main :: proc() { strings.write_string(&sb, "\t\treturn 0;\n") strings.write_string(&sb, "\t}\n") } + strings.write_string(&sb, "\n") { strings.write_string(&sb, "\tAsmOperandKind kind_from_operand_type(OperandType type) {\n") strings.write_string(&sb, "\t\tswitch (type) {\n") @@ -314,6 +315,56 @@ main :: proc() { strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t}\n") } + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, "\tbool operand_type_is_implicit(OperandType t) {\n") + strings.write_string(&sb, "\t\tswitch (t) {\n") + strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_EAX_IMPL: case OP_RAX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_ONE_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_ST0_IMPL: case OP_XMM0_IMPL:\n") + strings.write_string(&sb, "\t\t\treturn true;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn false;\n") + strings.write_string(&sb, "\t}\n") + } + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, "\tAsmRegClass operand_type_reg_class(OperandType t) {\n") + strings.write_string(&sb, "\t\tswitch (t) {\n") + strings.write_string(&sb, "\t\tcase OP_R8: case OP_R16: case OP_R32: case OP_R64:\n") + strings.write_string(&sb, "\t\tcase OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64:\n") + strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL:\n") + strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") + strings.write_string(&sb, "\t\t\treturn AsmRegClass_Integer;\n") + strings.write_string(&sb, "\t\tcase OP_XMM: case OP_YMM: case OP_ZMM:\n") + strings.write_string(&sb, "\t\tcase OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128:\n") + strings.write_string(&sb, "\t\tcase OP_YMM_M256: case OP_ZMM_M512:\n") + strings.write_string(&sb, "\t\tcase OP_XMM0_IMPL:\n") + strings.write_string(&sb, "\t\t\treturn AsmRegClass_Vector; // xmm/ymm/zmm; float scalars also land here (see note)\n") + strings.write_string(&sb, "\t\tcase OP_K:\n") + strings.write_string(&sb, "\t\tcase OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64:\n") + strings.write_string(&sb, "\t\t\treturn AsmRegClass_Mask;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn AsmRegClass_Unknown; // OP_M*, OP_IMM*, OP_REL*, OP_SREG/CR/DR/MM/STi, moffs, ptr, m16_16... : no GPR/XMM class constraint here\n") + strings.write_string(&sb, "\t}\n") + } + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, "\tu16 operand_type_bit_width(OperandType t) {\n") + strings.write_string(&sb, "\t\tswitch (t) {\n") + strings.write_string(&sb, "\t\tcase OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8;\n") + strings.write_string(&sb, "\t\tcase OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16;\n") + strings.write_string(&sb, "\t\tcase OP_R32: case OP_RM32: case OP_M32: case OP_EAX_IMPL: case OP_XMM_M32: case OP_K_M32: return 32;\n") + strings.write_string(&sb, "\t\tcase OP_R64: case OP_RM64: case OP_M64: case OP_RAX_IMPL: case OP_XMM_M64: case OP_K_M64: case OP_MM: case OP_MM_M64: return 64;\n") + strings.write_string(&sb, "\t\tcase OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128;\n") + strings.write_string(&sb, "\t\tcase OP_M256: case OP_YMM: case OP_YMM_M256: return 256;\n") + strings.write_string(&sb, "\t\tcase OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc.\n") + strings.write_string(&sb, "\t}\n") + } strings.write_string(&sb, "};\n") diff --git a/src/asm_tables.cpp b/src/asm_tables.cpp index df68ce1b8..561da7523 100644 --- a/src/asm_tables.cpp +++ b/src/asm_tables.cpp @@ -1,3 +1,12 @@ +enum AsmRegClass : u8 { + AsmRegClass_Unknown, + AsmRegClass_Integer, + AsmRegClass_Float, + AsmRegClass_Vector, + AsmRegClass_Mask, +}; + + enum AsmOperandKind : u8 { AsmOperand_Invalid, AsmOperand_Register, diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index e7853bd31..a64c87750 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -285,7 +285,7 @@ struct Asm_amd64 { } // size in bits for register u16 reg_size(Register r) const { - switch (reg_class(r)) { + switch (reg_class(register_codes[r])) { case REG_CLASS_GPR64: return 64; case REG_CLASS_GPR32: return 32; case REG_CLASS_GPR16: return 16; @@ -304,6 +304,7 @@ struct Asm_amd64 { } return 0; } + AsmOperandKind kind_from_operand_type(OperandType type) { switch (type) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: @@ -337,6 +338,50 @@ struct Asm_amd64 { return AsmOperand_Invalid; } } + + bool operand_type_is_implicit(OperandType t) { + switch (t) { + case OP_AL_IMPL: case OP_AX_IMPL: + case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + case OP_ONE_IMPL: + case OP_ST0_IMPL: case OP_XMM0_IMPL: + return true; + } + return false; + } + + AsmRegClass operand_type_reg_class(OperandType t) { + switch (t) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + return AsmRegClass_Integer; + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_XMM0_IMPL: + return AsmRegClass_Vector; // xmm/ymm/zmm; float scalars also land here (see note) + case OP_K: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmRegClass_Mask; + } + return AsmRegClass_Unknown; // OP_M*, OP_IMM*, OP_REL*, OP_SREG/CR/DR/MM/STi, moffs, ptr, m16_16... : no GPR/XMM class constraint here + } + + u16 operand_type_bit_width(OperandType t) { + switch (t) { + case OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8; + case OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16; + case OP_R32: case OP_RM32: case OP_M32: case OP_EAX_IMPL: case OP_XMM_M32: case OP_K_M32: return 32; + case OP_R64: case OP_RM64: case OP_M64: case OP_RAX_IMPL: case OP_XMM_M64: case OP_K_M64: case OP_MM: case OP_MM_M64: return 64; + case OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128; + case OP_M256: case OP_YMM: case OP_YMM_M256: return 256; + case OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512; + } + return 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc. + } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index ea807fe97..d90428ce4 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1,3 +1,38 @@ +// Bit-width the operand's Odin type occupies in a register/immediate slot. +// Integers/floats/bools/pointers -> their size; #simd -> total vector width. 0 if unknown. +gb_internal i32 check_asm_operand_bit_width(Type *type) { + if (type == nullptr || type == t_invalid) { + return 0; + } + if (is_type_untyped(type)) { + return -1; + } + i64 sz = type_size_of(base_type(type)); + if (sz <= 0) { + return 0; + } + return cast(i32)(sz * 8); +} + +// Map the user's explicit operand index -> index into form.ops[], skipping implicit slots. +// Returns -1 if there is no such explicit slot (shouldn't happen once explicit_count matches). +gb_internal int asm_form_explicit_slot(Asm_amd64::Encoding const &form, int explicit_index) { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (g_asm_amd64.operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; +} gb_internal bool is_valid_asm_parameter_type(Type *type) { if (is_type_integer(type)) { @@ -37,6 +72,75 @@ gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { return AsmRegClass_Unknown; } + +// Returns true if the operand's Odin type is size/class-compatible with the form's slot. +// On mismatch, fills *reason (static string) for a precise diagnostic. `type` here is the +// resolved OperandType at the correct (implicit-skipped) slot. +template +gb_internal bool check_asm_operand_size_class(T *asm_ctx, typename T::OperandType slot, Operand const *operand, + String *reason_, i32 *want_bits_, i32 *got_bits_) { + if (reason_) *reason_ = {}; + // Only register/memory-sized slots constrain width & class. Immediates/labels/sizeless-mem: skip here. + AsmRegClass want_class = asm_ctx->operand_type_reg_class(slot); + i32 want_w = asm_ctx->operand_type_bit_width(slot); + + // A pure-immediate or label slot imposes no reg width/class; value-range is checked elsewhere. + if (want_class == AsmRegClass_Unknown && want_w == 0) { + return true; + } + + AsmRegClass got_class = AsmRegClass_Unknown; + i32 got_w = 0; + if (operand->expr->kind == Ast_AsmRegister) { + + } + got_class = check_asm_reg_class_from_type(operand->type); + got_w = check_asm_operand_bit_width(operand->type); + if (got_w < 0) { + // TODO(bill): determine the correct width from the untyped constant value + got_w = want_w; + } + if (want_bits_) *want_bits_ = want_w; + if (got_bits_) *got_bits_ = got_w; + + // Class check (only when the slot constrains a class). + if (want_class != AsmRegClass_Unknown) { + bool class_ok; + switch (want_class) { + case AsmRegClass_Integer: + class_ok = (got_class == AsmRegClass_Integer); + break; + case AsmRegClass_Vector: + // XMM/YMM/ZMM slots accept both scalar float and #simd vector operands. + class_ok = (got_class == AsmRegClass_Vector || got_class == AsmRegClass_Float); + break; + case AsmRegClass_Mask: + class_ok = (got_class == AsmRegClass_Mask); + break; + default: + class_ok = true; + break; + } + + if (operand->expr->kind == Ast_AsmRegister) { + gb_printf_err("HERE: %s: %s %d %d\n", expr_to_string(operand->expr), type_to_string(operand->type), want_class, got_class); + } + + if (!class_ok) { + if (reason_) *reason_ = str_lit("register class"); + return false; + } + } + + // Width check (only when the slot pins a width and we could size the type). + if (want_w != 0 && got_w != 0 && want_w != got_w) { + if (reason_) *reason_ = str_lit("size"); + return false; + } + return true; +} + + gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { Type *tuple = alloc_type_tuple(); if (_params == nullptr) { @@ -285,10 +389,42 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } } -gb_internal bool check_register(AstAsmRegister *asm_reg) { +gb_internal bool check_register(Operand *operand, AstAsmRegister *asm_reg) { String name = asm_reg->name.string; auto r = g_asm_amd64.register_lookup(name); if (r) { + operand->mode = Addressing_Value; + u16 width_in_bits = g_asm_amd64.reg_size(r); + switch (width_in_bits) { + case 8: + operand->type = t_u8; + break; + case 16: + operand->type = t_u16; + break; + case 32: + operand->type = t_u32; + break; + case 64: + operand->type = t_u64; + break; + case 80: + error(operand->expr, "80-bit width asm registers are not supported"); + return false; + case 128: + operand->type = alloc_type_simd_vector(4, t_f32); + break; + case 256: + operand->type = alloc_type_simd_vector(8, t_f32); + break; + case 512: + operand->type = alloc_type_simd_vector(16, t_f32); + break; + default: + GB_PANIC("Unhandled register width size: %d", width_in_bits); + break; + } + return true; } error(asm_reg->name, "Unknown register for this target platform: %%%.*s", LIT(name)); @@ -409,9 +545,19 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(operand); - bool spot_ok = (dst == src) || + bool kind_ok = (dst == src) || (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + bool spot_ok = false; + if (kind_ok) { + spot_ok = true; + if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory) { + // No need to do an extra size class check, it accepts memory + } else { + spot_ok = check_asm_operand_size_class(&g_asm_amd64, type, operand, nullptr, nullptr, nullptr); + } + } + if (spot_ok) { score += 1; valid_spots[i] = true; @@ -446,27 +592,67 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u } // failure path + enum { MAX_VARIANT_COUNT = 32 }; + String mismatch_reason[MAX_VARIANT_COUNT] = {}; // parallels valid_spots for the best form + i32 want_bits[MAX_VARIANT_COUNT] = {}; + i32 got_bits[MAX_VARIANT_COUNT] = {}; if (best_form >= 0) { auto &form = forms[best_form]; for_array(i, operands) { - AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(form.ops[i]); + int slot = asm_form_explicit_slot(form, cast(int)i); + Asm_amd64::OperandType type = (slot >= 0) ? form.ops[slot] : Asm_amd64::OP_NONE; + AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(&operands[i]); possible_kinds[i] = dst; - valid_spots[i] = (dst == src) || - (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + + bool kind_ok = (dst == src) || + (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + if (!kind_ok) { + valid_spots[i] = false; + } else { + String reason = {}; + i32 wb_ = 0; + i32 gb_ = 0; + bool ok = check_asm_operand_size_class(&g_asm_amd64, type, &operands[i], &reason, &wb_, &gb_); + valid_spots[i] = ok; + if (!ok && i < MAX_VARIANT_COUNT) { + mismatch_reason[i] = reason; + want_bits[i] = wb_; + got_bits[i] = gb_; + } + } } } { error(instr->name, "The operands to '%.*s' matched none of the expected encoding forms", LIT(name)); for_array(i, valid_spots) { - if (!valid_spots[i] && i < operands.count) { - auto kind = possible_kinds[i]; - if (kind) { - error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s', expected %.*s operand", LIT(name), LIT(asm_operand_kind_expected_strings[kind])); - } else { - error(operands[i].expr, "Invalid operand kind for the asm instruction '%.*s'", LIT(name)); - } + if (valid_spots[i] || i >= operands.count) { + continue; + } + auto dst = possible_kinds[i]; + AsmOperandKind src = determine_asm_operand_kind(&operands[i]); + + String reason = {}; + if (i < MAX_VARIANT_COUNT) { + reason = mismatch_reason[i]; + } + + if (reason == "size" && want_bits[i] && got_bits[i]) { + // dst kind was right, width was wrong + error(operands[i].expr, + "Operand %td of '%.*s' has the wrong size: expected a %u-bit operand, got %u-bit", + i, LIT(name), cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); + } else if (reason == "register class") { + error(operands[i].expr, + "Operand %td of '%.*s' is in the wrong register class, expected %.*s operand, got %.*s", + i, LIT(name), LIT(asm_operand_kind_expected_strings[dst]), LIT(asm_operand_kind_expected_strings[src])); + } else if (dst) { + error(operands[i].expr, + "Operand %td of '%.*s' has an invalid kind, expected %.*s operand", + i, LIT(name), LIT(asm_operand_kind_expected_strings[dst])); + } else { + error(operands[i].expr, "Operand %td of '%.*s' has an invalid kind", i, LIT(name)); } } } @@ -508,13 +694,17 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti return; case_end; case_ast_node(asm_reg, AsmRegister, expr); - check_register(asm_reg); + check_register(operand, asm_reg); return; case_end; case_ast_node(mem_op, AsmMemoryOperand, expr); + operand->type = t_rawptr; + operand->mode = Addressing_Value; + if (!allow_memory_operands) { break; } + Operand base = {}; Operand index = {}; Operand scale = {}; @@ -526,7 +716,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; base.expr && i == 0; i++) { if (base.expr->kind == Ast_AsmRegister) { - check_register(&base.expr->AsmRegister); + check_register(&base, &base.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(base.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -547,7 +737,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; index.expr && i == 0; i++) { if (index.expr->kind == Ast_AsmRegister) { - check_register(&index.expr->AsmRegister); + check_register(&index, &index.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(index.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -607,7 +797,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; disp.expr && i == 0; i++) { if (disp.expr->kind == Ast_AsmRegister) { - check_register(&disp.expr->AsmRegister); + check_register(&disp, &disp.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(disp.expr); if (disp.mode == Addressing_Constant) { @@ -707,7 +897,8 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf switch (clobber->value->kind) { case_ast_node(asm_reg, AsmRegister, clobber->value) String reg = asm_reg->name.string; - if (check_register(asm_reg)) { + Operand operand = {}; + if (check_register(&operand, asm_reg)) { if (string_set_update(®_set, reg)) { error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); } diff --git a/src/entity.cpp b/src/entity.cpp index f2a3f3add..31a479eb9 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -169,14 +169,6 @@ enum AsmTemplateEntityDeclKind : u8 { AsmTemplateEntityDecl_COUNT }; -enum AsmRegClass : u8 { - AsmRegClass_Unknown, - AsmRegClass_Integer, - AsmRegClass_Float, - AsmRegClass_Vector, - AsmRegClass_Mask, -}; - enum AsmTemplateEntityDeclParamGroup : u8 { AsmTemplateEntityDeclParamGroup_Unknown, AsmTemplateEntityDeclParamGroup_Input, From 813f73275990beac3b40b3703b6725c074a9c45f Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 13:09:42 +0100 Subject: [PATCH 21/92] Remove debug message --- src/check_asm.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index d90428ce4..9edc806fe 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -122,10 +122,6 @@ gb_internal bool check_asm_operand_size_class(T *asm_ctx, typename T::OperandTyp break; } - if (operand->expr->kind == Ast_AsmRegister) { - gb_printf_err("HERE: %s: %s %d %d\n", expr_to_string(operand->expr), type_to_string(operand->type), want_class, got_class); - } - if (!class_ok) { if (reason_) *reason_ = str_lit("register class"); return false; From ef21ffa285b0a761b4a4b3a714abad66d14750fd Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 14:00:41 +0100 Subject: [PATCH 22/92] Templatize the `check_asm.cpp` code ready for other architectures --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 21 +++ src/asm_tables.cpp | 6 +- src/asm_tables_amd64.cpp | 18 +++ src/check_asm.cpp | 153 +++++++++--------- src/check_decl.cpp | 6 +- src/main.cpp | 4 +- 6 files changed, 122 insertions(+), 86 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 8129f4fbc..a005a4258 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -365,6 +365,27 @@ main :: proc() { strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc.\n") strings.write_string(&sb, "\t}\n") } + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, "\tint form_explicit_slot(Encoding const &form, int explicit_index) {\n") + strings.write_string(&sb, "\t\tint seen = 0;\n") + strings.write_string(&sb, "\t\tfor (int j = 0; j < gb_count_of(form.ops); j++) {\n") + strings.write_string(&sb, "\t\t\tauto t = form.ops[j];\n") + strings.write_string(&sb, "\t\t\tif (!t) {\n") + strings.write_string(&sb, "\t\t\t\tbreak;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\t\tif (operand_type_is_implicit(t)) {\n") + strings.write_string(&sb, "\t\t\t\tcontinue;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\t\tif (seen == explicit_index) {\n") + strings.write_string(&sb, "\t\t\t\treturn j;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\t\tseen += 1;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn -1;\n") + strings.write_string(&sb, "\t}\n") + + } strings.write_string(&sb, "};\n") diff --git a/src/asm_tables.cpp b/src/asm_tables.cpp index 561da7523..e599ff1b5 100644 --- a/src/asm_tables.cpp +++ b/src/asm_tables.cpp @@ -36,4 +36,8 @@ gb_global String const asm_operand_kind_expected_strings[AsmOperand_COUNT] = { str_lit("a label"), }; -#include "asm_tables_amd64.cpp" \ No newline at end of file +#include "asm_tables_amd64.cpp" + +void init_asm_tables() { + g_asm_amd64.init(); +} \ No newline at end of file diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index a64c87750..1a2f93b81 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -382,6 +382,24 @@ struct Asm_amd64 { } return 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc. } + + int form_explicit_slot(Encoding const &form, int explicit_index) { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; + } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 9edc806fe..d6624ed44 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -14,26 +14,6 @@ gb_internal i32 check_asm_operand_bit_width(Type *type) { return cast(i32)(sz * 8); } -// Map the user's explicit operand index -> index into form.ops[], skipping implicit slots. -// Returns -1 if there is no such explicit slot (shouldn't happen once explicit_count matches). -gb_internal int asm_form_explicit_slot(Asm_amd64::Encoding const &form, int explicit_index) { - int seen = 0; - for (int j = 0; j < gb_count_of(form.ops); j++) { - auto t = form.ops[j]; - if (!t) { - break; - } - if (g_asm_amd64.operand_type_is_implicit(t)) { - continue; - } - if (seen == explicit_index) { - return j; - } - seen += 1; - } - return -1; -} - gb_internal bool is_valid_asm_parameter_type(Type *type) { if (is_type_integer(type)) { return true; @@ -73,13 +53,19 @@ gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { } +enum AsmMismatch : u8 { + AsmMismatch_None, + AsmMismatch_Size, + AsmMismatch_Class, +}; + // Returns true if the operand's Odin type is size/class-compatible with the form's slot. -// On mismatch, fills *reason (static string) for a precise diagnostic. `type` here is the +// On mismatch, fills *mismatch_ for a precise diagnostic. `slot` here is the // resolved OperandType at the correct (implicit-skipped) slot. -template -gb_internal bool check_asm_operand_size_class(T *asm_ctx, typename T::OperandType slot, Operand const *operand, - String *reason_, i32 *want_bits_, i32 *got_bits_) { - if (reason_) *reason_ = {}; +template +gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx::OperandType slot, Operand const *operand, + AsmMismatch *mismatch_, i32 *want_bits_, i32 *got_bits_) { + if (mismatch_) *mismatch_ = AsmMismatch_None; // Only register/memory-sized slots constrain width & class. Immediates/labels/sizeless-mem: skip here. AsmRegClass want_class = asm_ctx->operand_type_reg_class(slot); i32 want_w = asm_ctx->operand_type_bit_width(slot); @@ -89,13 +75,8 @@ gb_internal bool check_asm_operand_size_class(T *asm_ctx, typename T::OperandTyp return true; } - AsmRegClass got_class = AsmRegClass_Unknown; - i32 got_w = 0; - if (operand->expr->kind == Ast_AsmRegister) { - - } - got_class = check_asm_reg_class_from_type(operand->type); - got_w = check_asm_operand_bit_width(operand->type); + AsmRegClass got_class = check_asm_reg_class_from_type(operand->type); + i32 got_w = check_asm_operand_bit_width(operand->type); if (got_w < 0) { // TODO(bill): determine the correct width from the untyped constant value got_w = want_w; @@ -123,14 +104,14 @@ gb_internal bool check_asm_operand_size_class(T *asm_ctx, typename T::OperandTyp } if (!class_ok) { - if (reason_) *reason_ = str_lit("register class"); + if (mismatch_) *mismatch_ = AsmMismatch_Class; return false; } } // Width check (only when the slot pins a width and we could size the type). if (want_w != 0 && got_w != 0 && want_w != got_w) { - if (reason_) *reason_ = str_lit("size"); + if (mismatch_) *mismatch_ = AsmMismatch_Size; return false; } return true; @@ -385,12 +366,21 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } } -gb_internal bool check_register(Operand *operand, AstAsmRegister *asm_reg) { +template +gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegister *asm_reg) { String name = asm_reg->name.string; - auto r = g_asm_amd64.register_lookup(name); + auto r = asm_ctx->register_lookup(name); if (r) { operand->mode = Addressing_Value; - u16 width_in_bits = g_asm_amd64.reg_size(r); + + u16 reg_class = asm_ctx->reg_class(r); + if (reg_class == asm_ctx->REG_CLASS_K) { + // Opmask register: classify as a mask, not a 64-bit integer. + // operand->type = t_asm_mask; // see note if this type does not yet exist + // return true; + } + + u16 width_in_bits = asm_ctx->reg_size(r); switch (width_in_bits) { case 8: operand->type = t_u8; @@ -433,14 +423,15 @@ enum CheckMnemomicResult { CheckMnemomic_Prefix, }; -gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u16 *mnemonic_) { +template +gb_internal CheckMnemomicResult check_mnemonic_name(AsmCtx *asm_ctx, AstAsmInstruction *instr, u16 *mnemonic_) { String name = instr->name->Ident.token.string; - auto m = g_asm_amd64.mnemonic_lookup(name); + auto m = asm_ctx->mnemonic_lookup(name); if (m) { if (mnemonic_) *mnemonic_ = cast(u16)m; return CheckMnemomic_Mnemonic; } - auto p = g_asm_amd64.prefix_lookup(name); + auto p = asm_ctx->prefix_lookup(name); if (p) { if (mnemonic_) *mnemonic_ = cast(u16)p; return CheckMnemomic_Prefix; @@ -453,15 +444,15 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AstAsmInstruction *instr, u1 error(instr->name, "Unknown mnemonic for this target platform: %.*s", LIT(name)); } - auto dym = did_you_mean_make(heap_allocator(), g_asm_amd64.MNEMONIC_COUNT, name); + auto dym = did_you_mean_make(heap_allocator(), asm_ctx->MNEMONIC_COUNT, name); defer (did_you_mean_destroy(&dym)); - for (u16 i = g_asm_amd64.M_INVALID+1; i < g_asm_amd64.MNEMONIC_COUNT; i++) { - String str = g_asm_amd64.mnemonic_strings[i]; + for (u16 i = asm_ctx->M_INVALID+1; i < asm_ctx->MNEMONIC_COUNT; i++) { + String str = asm_ctx->mnemonic_strings[i]; did_you_mean_append(&dym, str); } if (instr->operands.count == 0) { - for (u16 i = g_asm_amd64.PREFIX_INVALID+1; i < g_asm_amd64.PREFIX_COUNT; i++) { - String str = g_asm_amd64.prefix_strings[i]; + for (u16 i = asm_ctx->PREFIX_INVALID+1; i < asm_ctx->PREFIX_COUNT; i++) { + String str = asm_ctx->prefix_strings[i]; did_you_mean_append(&dym, str); } } @@ -500,10 +491,11 @@ gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { } -gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix) { +template +gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix) { GB_ASSERT(mnemonic > 0); - auto forms = g_asm_amd64.encoding_forms(mnemonic); - String name = g_asm_amd64.mnemonic_strings[mnemonic]; + auto forms = asm_ctx->encoding_forms(mnemonic); + String name = asm_ctx->mnemonic_strings[mnemonic]; int min_count = I32_MAX; int max_count = -1; @@ -536,9 +528,10 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u int score = 0; for_array(i, operands) { - auto type = form.ops[i]; + int slot = asm_ctx->form_explicit_slot(form, cast(int)i); + auto type = (slot >= 0) ? form.ops[slot] : asm_ctx->OP_NONE; Operand const *operand = &operands[i]; - AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(type); + AsmOperandKind dst = asm_ctx->kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(operand); bool kind_ok = (dst == src) || @@ -550,7 +543,7 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory) { // No need to do an extra size class check, it accepts memory } else { - spot_ok = check_asm_operand_size_class(&g_asm_amd64, type, operand, nullptr, nullptr, nullptr); + spot_ok = check_asm_operand_size_class(asm_ctx, type, operand, nullptr, nullptr, nullptr); } } @@ -589,15 +582,15 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u // failure path enum { MAX_VARIANT_COUNT = 32 }; - String mismatch_reason[MAX_VARIANT_COUNT] = {}; // parallels valid_spots for the best form - i32 want_bits[MAX_VARIANT_COUNT] = {}; - i32 got_bits[MAX_VARIANT_COUNT] = {}; + AsmMismatch mismatch[MAX_VARIANT_COUNT] = {}; // parallels valid_spots for the best form + i32 want_bits[MAX_VARIANT_COUNT] = {}; + i32 got_bits[MAX_VARIANT_COUNT] = {}; if (best_form >= 0) { auto &form = forms[best_form]; for_array(i, operands) { - int slot = asm_form_explicit_slot(form, cast(int)i); - Asm_amd64::OperandType type = (slot >= 0) ? form.ops[slot] : Asm_amd64::OP_NONE; - AsmOperandKind dst = g_asm_amd64.kind_from_operand_type(type); + int slot = asm_ctx->form_explicit_slot(form, cast(int)i); + auto type = (slot >= 0) ? form.ops[slot] : asm_ctx->OP_NONE; + AsmOperandKind dst = asm_ctx->kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(&operands[i]); possible_kinds[i] = dst; @@ -606,13 +599,13 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u if (!kind_ok) { valid_spots[i] = false; } else { - String reason = {}; + AsmMismatch m = AsmMismatch_None; i32 wb_ = 0; i32 gb_ = 0; - bool ok = check_asm_operand_size_class(&g_asm_amd64, type, &operands[i], &reason, &wb_, &gb_); + bool ok = check_asm_operand_size_class(asm_ctx, type, &operands[i], &m, &wb_, &gb_); valid_spots[i] = ok; if (!ok && i < MAX_VARIANT_COUNT) { - mismatch_reason[i] = reason; + mismatch[i] = m; want_bits[i] = wb_; got_bits[i] = gb_; } @@ -629,17 +622,14 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u auto dst = possible_kinds[i]; AsmOperandKind src = determine_asm_operand_kind(&operands[i]); - String reason = {}; - if (i < MAX_VARIANT_COUNT) { - reason = mismatch_reason[i]; - } + AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; - if (reason == "size" && want_bits[i] && got_bits[i]) { + if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { // dst kind was right, width was wrong error(operands[i].expr, "Operand %td of '%.*s' has the wrong size: expected a %u-bit operand, got %u-bit", i, LIT(name), cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); - } else if (reason == "register class") { + } else if (m == AsmMismatch_Class) { error(operands[i].expr, "Operand %td of '%.*s' is in the wrong register class, expected %.*s operand, got %.*s", i, LIT(name), LIT(asm_operand_kind_expected_strings[dst]), LIT(asm_operand_kind_expected_strings[src])); @@ -655,8 +645,8 @@ gb_internal void check_mnemonic(CheckerContext *ctx, AstAsmInstruction *instr, u } - -gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { +template +gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *entity, Operand *operand, Ast *expr, bool allow_memory_operands) { if (expr == nullptr) { return; } @@ -690,7 +680,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti return; case_end; case_ast_node(asm_reg, AsmRegister, expr); - check_register(operand, asm_reg); + check_register(asm_ctx, operand, asm_reg); return; case_end; case_ast_node(mem_op, AsmMemoryOperand, expr); @@ -705,14 +695,14 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti Operand index = {}; Operand scale = {}; Operand disp = {}; - check_asm_instruction_operand(ctx, entity, &base, mem_op->base, false); - check_asm_instruction_operand(ctx, entity, &index, mem_op->index, false); - check_asm_instruction_operand(ctx, entity, &scale, mem_op->scale, false); - check_asm_instruction_operand(ctx, entity, &disp, mem_op->disp, false); + check_asm_instruction_operand(asm_ctx, ctx, entity, &base, mem_op->base, false); + check_asm_instruction_operand(asm_ctx, ctx, entity, &index, mem_op->index, false); + check_asm_instruction_operand(asm_ctx, ctx, entity, &scale, mem_op->scale, false); + check_asm_instruction_operand(asm_ctx, ctx, entity, &disp, mem_op->disp, false); for (int i = 0; base.expr && i == 0; i++) { if (base.expr->kind == Ast_AsmRegister) { - check_register(&base, &base.expr->AsmRegister); + check_register(asm_ctx, &base, &base.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(base.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -733,7 +723,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; index.expr && i == 0; i++) { if (index.expr->kind == Ast_AsmRegister) { - check_register(&index, &index.expr->AsmRegister); + check_register(asm_ctx, &index, &index.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(index.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { @@ -793,7 +783,7 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti for (int i = 0; disp.expr && i == 0; i++) { if (disp.expr->kind == Ast_AsmRegister) { - check_register(&disp, &disp.expr->AsmRegister); + check_register(asm_ctx, &disp, &disp.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(disp.expr); if (disp.mode == Addressing_Constant) { @@ -850,7 +840,8 @@ gb_internal void check_asm_instruction_operand(CheckerContext *ctx, Entity *enti } -gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInfo *d) { +template +gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *entity, DeclInfo *d) { GB_ASSERT(entity->kind == Entity_AsmTemplate); auto *ate = &entity->AsmTemplate; @@ -894,7 +885,7 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf case_ast_node(asm_reg, AsmRegister, clobber->value) String reg = asm_reg->name.string; Operand operand = {}; - if (check_register(&operand, asm_reg)) { + if (check_register(asm_ctx, &operand, asm_reg)) { if (string_set_update(®_set, reg)) { error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); } @@ -962,14 +953,14 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf GB_ASSERT(instr->name->kind == Ast_Ident); u16 mnemonic = 0; - CheckMnemomicResult res = check_mnemonic_name(instr, &mnemonic); + CheckMnemomicResult res = check_mnemonic_name(asm_ctx, instr, &mnemonic); array_clear(&operands); for (Ast *expr : instr->operands) { Operand operand = {}; - check_asm_instruction_operand(ctx, entity, &operand, expr, /*allow_memory_operands*/true); + check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); array_add(&operands, operand); } if (res == CheckMnemomic_Prefix) { @@ -978,7 +969,7 @@ gb_internal void check_asm_template(CheckerContext *ctx, Entity *entity, DeclInf } previous_prefix = cast(u8)mnemonic; } else if (res == CheckMnemomic_Mnemonic) { - check_mnemonic(ctx, instr, mnemonic, slice_from_array(operands), previous_prefix); + check_mnemonic(asm_ctx, ctx, instr, mnemonic, slice_from_array(operands), previous_prefix); } case_end; diff --git a/src/check_decl.cpp b/src/check_decl.cpp index c70672036..520aa5e5d 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2065,7 +2065,11 @@ gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, break; case Entity_AsmTemplate: - check_asm_template(&c, e, d); + if (build_context.metrics.arch == TargetArch_amd64) { + check_asm_template(&g_asm_amd64, &c, e, d); + } else { + error(e->token, "asm templates are not currently supported for this target"); + } break; } diff --git a/src/main.cpp b/src/main.cpp index aeefd09b6..14d526043 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -4314,9 +4314,7 @@ int main(int arg_count, char const **arg_ptr) { bool failed_to_cache_parsing = false; TIME_SECTION("init asm tables"); - { - g_asm_amd64.init(); - } + init_asm_tables(); MAIN_TIME_SECTION("parse files"); From ed2bc9159682921b6eeab503f9e1fb286a7ef6d0 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 14:18:37 +0100 Subject: [PATCH 23/92] Add some missing vector instructions to the x86 encoding table --- core/rexcode/isa/x86/mnemonics.odin | 18 + .../isa/x86/tablegen/encoding_table.odin | 78 + .../x86/tablegen/generated/decode_tables.odin | 808 ++++++----- .../x86/tablegen/generated/encode_tables.odin | 1290 +++++++++-------- .../isa/x86/tables/x86.encode_forms.bin | Bin 37680 -> 38320 bytes .../isa/x86/tables/x86.encode_recipes.bin | Bin 28260 -> 28740 bytes .../isa/x86/tables/x86.encode_runs.bin | Bin 9408 -> 9552 bytes core/rexcode/isa/x86/tables/x86.evex.bin | Bin 8360 -> 8360 bytes core/rexcode/isa/x86/tables/x86.legacy.bin | Bin 25400 -> 25400 bytes core/rexcode/isa/x86/tables/x86.vex.bin | Bin 13340 -> 14140 bytes .../rexcode/isa/x86/tables/x86.vex_idx_0f.bin | Bin 4096 -> 4096 bytes .../isa/x86/tables/x86.vex_idx_0f38.bin | Bin 4096 -> 4096 bytes .../isa/x86/tables/x86.vex_idx_0f3a.bin | Bin 4096 -> 4096 bytes src/asm_tables_amd64.cpp | 843 +++++------ 14 files changed, 1640 insertions(+), 1397 deletions(-) diff --git a/core/rexcode/isa/x86/mnemonics.odin b/core/rexcode/isa/x86/mnemonics.odin index 0ed1b142c..7428b208a 100644 --- a/core/rexcode/isa/x86/mnemonics.odin +++ b/core/rexcode/isa/x86/mnemonics.odin @@ -658,6 +658,24 @@ Mnemonic :: enum u16 { VMOVNTPD, VMOVNTDQ, VMOVNTDQA, + VADDSUBPS, + VADDSUBPD, + VHADDPS, + VHADDPD, + VHSUBPS, + VHSUBPD, + VLDDQU, + VMOVDDUP, + VMOVSLDUP, + VMOVSHDUP, + VPCMPESTRI, + VPCMPESTRM, + VPCMPISTRI, + VPCMPISTRM, + VPBROADCASTB, + VPBROADCASTW, + VPBROADCASTD, + VPBROADCASTQ, VCVTPS2PD, VCVTPD2PS, VCVTSS2SD, diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index bcd20bf28..108f7153d 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -2396,6 +2396,84 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, }, + .VADDSUBPS = { + {.VADDSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, + {.VADDSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + }, + .VADDSUBPD = { + {.VADDSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {.VADDSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + }, + .VHADDPS = { // <-- the instruction you named + {.VHADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, + {.VHADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + }, + .VHADDPD = { + {.VHADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {.VHADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + }, + .VHSUBPS = { + {.VHSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, + {.VHSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + }, + .VHSUBPD = { + {.VHSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {.VHSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + }, + .VLDDQU = { // 2-operand (load only) + {.VLDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, + {.VLDDQU, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + }, + .VMOVDDUP = { + {.VMOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, + {.VMOVDDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + }, + .VMOVSLDUP = { + {.VMOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, + {.VMOVSLDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + }, + .VMOVSHDUP = { + {.VMOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, + {.VMOVSHDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + }, + // VEX.128.66.0F3A. — ESTR* also have a W1 (RAX/RDX) variant; W0 shown to match the SSE entries. + .VPCMPESTRI = { + {.VPCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + }, + .VPCMPESTRM = { + {.VPCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + }, + .VPCMPISTRI = { + {.VPCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + }, + .VPCMPISTRM = { + {.VPCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + }, + // VEX.128/256.66.0F38.W0 element broadcasts (AVX2). reg-source + memory-source forms, mirroring .VBROADCASTSS + .VPBROADCASTB = { + {.VPBROADCASTB, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTB, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {.VPBROADCASTB, {.XMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTB, {.YMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + }, + .VPBROADCASTW = { + {.VPBROADCASTW, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTW, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {.VPBROADCASTW, {.XMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTW, {.YMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + }, + .VPBROADCASTD = { + {.VPBROADCASTD, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {.VPBROADCASTD, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTD, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + }, + .VPBROADCASTQ = { + {.VPBROADCASTQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTQ, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {.VPBROADCASTQ, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {.VPBROADCASTQ, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + }, .VCVTPS2PD = { {.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index fb1c3c1d4..6821eb95a 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -1418,20 +1418,20 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ } @(rodata) -VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ +VEX_DECODE_ENTRIES := [707]lib.VEX_Decode_Entry{ {._0F, 0, 0x10, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x10, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x11, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x11, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x11, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x13, 0xFF, .WIG, .L0, .VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x17, 0xFF, .WIG, .L0, .VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x28, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x28, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, @@ -1443,30 +1443,30 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 0, 0x2F, 0xFF, .WIG, .LIG, .VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .W0, .L1, .KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .W1, .L1, .KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .W1, .L1, .KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x42, 0xFF, .W0, .L1, .KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .W1, .L1, .KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .W1, .L0, .KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .W0, .L0, .KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .W0, .L1, .KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .W1, .L1, .KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .W1, .L1, .KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .W0, .L1, .KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .W1, .L1, .KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .W1, .L1, .KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .W0, .L1, .KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .W0, .L1, .KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .W1, .L1, .KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x4A, 0xFF, .W1, .L1, .KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .W0, .L1, .KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .W1, .L1, .KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .W0, .L1, .KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x51, 0xFF, .WIG, .L1, .VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .WIG, .L0, .VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x52, 0xFF, .WIG, .L1, .VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x51, 0xFF, .WIG, .L1, .VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x52, 0xFF, .WIG, .L0, .VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x53, 0xFF, .WIG, .L0, .VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x52, 0xFF, .WIG, .L1, .VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x53, 0xFF, .WIG, .L1, .VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x54, 0xFF, .WIG, .L0, .VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x53, 0xFF, .WIG, .L0, .VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x54, 0xFF, .WIG, .L1, .VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x54, 0xFF, .WIG, .L0, .VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x55, 0xFF, .WIG, .L0, .VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x55, 0xFF, .WIG, .L1, .VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x56, 0xFF, .WIG, .L0, .VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -1477,8 +1477,8 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 0, 0x58, 0xFF, .WIG, .L1, .VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x59, 0xFF, .WIG, .L0, .VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 0, 0x59, 0xFF, .WIG, .L1, .VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 0, 0x5A, 0xFF, .WIG, .L1, .VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x5A, 0xFF, .WIG, .L0, .VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5A, 0xFF, .WIG, .L1, .VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x5B, 0xFF, .WIG, .L1, .VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 0, 0x5B, 0xFF, .WIG, .L0, .VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x5C, 0xFF, .WIG, .L0, .VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -1497,10 +1497,10 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 0, 0x91, 0xFF, .W0, .L0, .KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x92, 0xFF, .W0, .L0, .KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .W0, .L0, .KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x98, 0xFF, .W0, .L0, .KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x98, 0xFF, .W1, .L0, .KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x99, 0xFF, .W1, .L0, .KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x98, 0xFF, .W0, .L0, .KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0x99, 0xFF, .W0, .L0, .KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x99, 0xFF, .W1, .L0, .KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .WIG, .L0, .VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .WIG, .L1, .VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F, 0, 0xC6, 0xFF, .WIG, .L1, .VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, @@ -1511,22 +1511,22 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0x11, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x12, 0xFF, .WIG, .L0, .VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x13, 0xFF, .WIG, .L0, .VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x16, 0xFF, .WIG, .L0, .VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x17, 0xFF, .WIG, .L0, .VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x28, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x28, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x29, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x28, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x29, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x29, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2F, 0xFF, .WIG, .LIG, .VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x41, 0xFF, .W1, .L1, .KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x41, 0xFF, .W0, .L1, .KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x41, 0xFF, .W1, .L1, .KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x42, 0xFF, .W0, .L1, .KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x42, 0xFF, .W1, .L1, .KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x44, 0xFF, .W1, .L0, .KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, @@ -1535,13 +1535,13 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0x45, 0xFF, .W1, .L1, .KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x46, 0xFF, .W1, .L1, .KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x46, 0xFF, .W0, .L1, .KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x47, 0xFF, .W1, .L1, .KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x47, 0xFF, .W0, .L1, .KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x47, 0xFF, .W1, .L1, .KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x4A, 0xFF, .W0, .L1, .KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x4A, 0xFF, .W1, .L1, .KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x4B, 0xFF, .W0, .L1, .KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x51, 0xFF, .WIG, .L1, .VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x51, 0xFF, .WIG, .L0, .VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x54, 0xFF, .WIG, .L1, .VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, @@ -1558,8 +1558,8 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0x59, 0xFF, .WIG, .L0, .VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x5A, 0xFF, .WIG, .L0, .VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x5A, 0xFF, .WIG, .L1, .VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x5B, 0xFF, .WIG, .L0, .VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x5B, 0xFF, .WIG, .L1, .VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5B, 0xFF, .WIG, .L0, .VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x5C, 0xFF, .WIG, .L1, .VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x5C, 0xFF, .WIG, .L0, .VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x5D, 0xFF, .WIG, .L0, .VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -1568,32 +1568,32 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0x5E, 0xFF, .WIG, .L0, .VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x5F, 0xFF, .WIG, .L0, .VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x5F, 0xFF, .WIG, .L1, .VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x60, 0xFF, .WIG, .L1, .VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x60, 0xFF, .WIG, .L0, .VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x61, 0xFF, .WIG, .L0, .VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x60, 0xFF, .WIG, .L1, .VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x61, 0xFF, .WIG, .L1, .VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x62, 0xFF, .WIG, .L1, .VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x61, 0xFF, .WIG, .L0, .VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x62, 0xFF, .WIG, .L0, .VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x63, 0xFF, .WIG, .L0, .VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x62, 0xFF, .WIG, .L1, .VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x63, 0xFF, .WIG, .L1, .VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x63, 0xFF, .WIG, .L0, .VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x64, 0xFF, .WIG, .L1, .VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x64, 0xFF, .WIG, .L0, .VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x65, 0xFF, .WIG, .L1, .VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x65, 0xFF, .WIG, .L0, .VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x66, 0xFF, .WIG, .L1, .VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x66, 0xFF, .WIG, .L0, .VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x67, 0xFF, .WIG, .L0, .VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x66, 0xFF, .WIG, .L1, .VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x67, 0xFF, .WIG, .L1, .VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x67, 0xFF, .WIG, .L0, .VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x68, 0xFF, .WIG, .L1, .VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x68, 0xFF, .WIG, .L0, .VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x69, 0xFF, .WIG, .L1, .VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x69, 0xFF, .WIG, .L0, .VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x69, 0xFF, .WIG, .L1, .VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6A, 0xFF, .WIG, .L0, .VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6A, 0xFF, .WIG, .L1, .VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x6B, 0xFF, .WIG, .L0, .VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6B, 0xFF, .WIG, .L1, .VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x6C, 0xFF, .WIG, .L0, .VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6B, 0xFF, .WIG, .L0, .VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6C, 0xFF, .WIG, .L1, .VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6C, 0xFF, .WIG, .L0, .VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6D, 0xFF, .WIG, .L0, .VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6D, 0xFF, .WIG, .L1, .VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x6E, 0xFF, .WIG, .L0, .VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, @@ -1610,32 +1610,36 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0x71, 0x06, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x72, 0x02, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x72, 0x02, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x72, 0x04, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x72, 0x04, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x04, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x72, 0x06, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x72, 0x06, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x73, 0x02, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x73, 0x02, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x73, 0x02, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x73, 0x06, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x73, 0x06, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, {._0F, 1, 0x74, 0xFF, .WIG, .L0, .VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x74, 0xFF, .WIG, .L1, .VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x75, 0xFF, .WIG, .L0, .VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x75, 0xFF, .WIG, .L1, .VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0x76, 0xFF, .WIG, .L0, .VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x75, 0xFF, .WIG, .L0, .VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x76, 0xFF, .WIG, .L1, .VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x76, 0xFF, .WIG, .L0, .VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7C, 0xFF, .WIG, .L0, .VHADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7C, 0xFF, .WIG, .L1, .VHADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7D, 0xFF, .WIG, .L1, .VHSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7D, 0xFF, .WIG, .L0, .VHSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .WIG, .L0, .VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .W1, .L0, .VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x90, 0xFF, .W1, .L0, .KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x90, 0xFF, .W0, .L0, .KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x91, 0xFF, .W0, .L0, .KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x91, 0xFF, .W1, .L0, .KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x91, 0xFF, .W0, .L0, .KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x92, 0xFF, .W0, .L0, .KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x93, 0xFF, .W0, .L0, .KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x98, 0xFF, .W0, .L0, .KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x98, 0xFF, .W1, .L0, .KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x98, 0xFF, .W0, .L0, .KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x99, 0xFF, .W1, .L0, .KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0x99, 0xFF, .W0, .L0, .KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0xC2, 0xFF, .WIG, .L1, .VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, @@ -1644,25 +1648,27 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0xC5, 0xFF, .WIG, .L0, .VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC6, 0xFF, .WIG, .L0, .VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F, 1, 0xC6, 0xFF, .WIG, .L1, .VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xD0, 0xFF, .WIG, .L1, .VADDSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD0, 0xFF, .WIG, .L0, .VADDSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD1, 0xFF, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD1, 0xFF, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xD2, 0xFF, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD2, 0xFF, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD2, 0xFF, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD3, 0xFF, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD3, 0xFF, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xD4, 0xFF, .WIG, .L0, .VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD4, 0xFF, .WIG, .L1, .VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD4, 0xFF, .WIG, .L0, .VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD5, 0xFF, .WIG, .L0, .VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD5, 0xFF, .WIG, .L1, .VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xD6, 0xFF, .WIG, .L0, .VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0xD7, 0xFF, .WIG, .L0, .VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0xD7, 0xFF, .WIG, .L1, .VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .WIG, .L0, .VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0xDB, 0xFF, .WIG, .L1, .VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xDB, 0xFF, .WIG, .L0, .VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xDF, 0xFF, .WIG, .L1, .VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xDF, 0xFF, .WIG, .L0, .VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xE1, 0xFF, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xE1, 0xFF, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE1, 0xFF, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xE2, 0xFF, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xE2, 0xFF, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xE4, 0xFF, .WIG, .L0, .VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -1673,52 +1679,56 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 1, 0xE6, 0xFF, .WIG, .L0, .VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 1, 0xE7, 0xFF, .WIG, .L1, .VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xE7, 0xFF, .WIG, .L0, .VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0xEB, 0xFF, .WIG, .L1, .VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xEB, 0xFF, .WIG, .L0, .VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xEF, 0xFF, .WIG, .L0, .VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xEB, 0xFF, .WIG, .L1, .VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xEF, 0xFF, .WIG, .L1, .VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xF1, 0xFF, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xEF, 0xFF, .WIG, .L0, .VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF1, 0xFF, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF1, 0xFF, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF2, 0xFF, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF2, 0xFF, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF3, 0xFF, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF3, 0xFF, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF4, 0xFF, .WIG, .L0, .VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF4, 0xFF, .WIG, .L1, .VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xF5, 0xFF, .WIG, .L1, .VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF5, 0xFF, .WIG, .L0, .VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF5, 0xFF, .WIG, .L1, .VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF7, 0xFF, .WIG, .L0, .VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F, 1, 0xF8, 0xFF, .WIG, .L1, .VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF8, 0xFF, .WIG, .L0, .VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF8, 0xFF, .WIG, .L1, .VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF9, 0xFF, .WIG, .L1, .VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xF9, 0xFF, .WIG, .L0, .VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xFA, 0xFF, .WIG, .L0, .VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xFA, 0xFF, .WIG, .L1, .VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xFB, 0xFF, .WIG, .L1, .VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFA, 0xFF, .WIG, .L0, .VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xFB, 0xFF, .WIG, .L0, .VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xFC, 0xFF, .WIG, .L0, .VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFB, 0xFF, .WIG, .L1, .VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xFC, 0xFF, .WIG, .L1, .VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xFD, 0xFF, .WIG, .L0, .VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFC, 0xFF, .WIG, .L0, .VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xFD, 0xFF, .WIG, .L1, .VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xFE, 0xFF, .WIG, .L0, .VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFD, 0xFF, .WIG, .L0, .VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 1, 0xFE, 0xFF, .WIG, .L1, .VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFE, 0xFF, .WIG, .L0, .VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x11, 0xFF, .WIG, .LIG, .VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x12, 0xFF, .WIG, .L0, .VMOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x12, 0xFF, .WIG, .L1, .VMOVSLDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x16, 0xFF, .WIG, .L1, .VMOVSHDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x16, 0xFF, .WIG, .L0, .VMOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, - {._0F, 2, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .W1, .LIG, .VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x2D, 0xFF, .WIG, .LIG, .VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2D, 0xFF, .W1, .LIG, .VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .WIG, .LIG, .VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 2, 0x51, 0xFF, .WIG, .LIG, .VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x52, 0xFF, .WIG, .LIG, .VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x53, 0xFF, .WIG, .LIG, .VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x58, 0xFF, .WIG, .LIG, .VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x59, 0xFF, .WIG, .LIG, .VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x5A, 0xFF, .WIG, .LIG, .VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, - {._0F, 2, 0x5B, 0xFF, .WIG, .L1, .VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 2, 0x5B, 0xFF, .WIG, .L0, .VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5B, 0xFF, .WIG, .L1, .VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 2, 0x5C, 0xFF, .WIG, .LIG, .VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x5D, 0xFF, .WIG, .LIG, .VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 2, 0x5E, 0xFF, .WIG, .LIG, .VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, @@ -1731,15 +1741,17 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 2, 0x7F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 2, 0x7F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 2, 0xC2, 0xFF, .WIG, .LIG, .VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=4, needs_modrm=true}}, - {._0F, 2, 0xE6, 0xFF, .WIG, .L1, .VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 2, 0xE6, 0xFF, .WIG, .L0, .VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xE6, 0xFF, .WIG, .L1, .VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 3, 0x11, 0xFF, .WIG, .LIG, .VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x12, 0xFF, .WIG, .L0, .VMOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x12, 0xFF, .WIG, .L1, .VMOVDDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, - {._0F, 3, 0x2C, 0xFF, .W1, .LIG, .VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .W1, .LIG, .VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .WIG, .LIG, .VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .W1, .LIG, .VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, {._0F, 3, 0x51, 0xFF, .WIG, .LIG, .VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, @@ -1750,15 +1762,23 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F, 3, 0x5D, 0xFF, .WIG, .LIG, .VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 3, 0x5E, 0xFF, .WIG, .LIG, .VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, {._0F, 3, 0x5F, 0xFF, .WIG, .LIG, .VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, - {._0F, 3, 0x70, 0xFF, .WIG, .L1, .VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 3, 0x70, 0xFF, .WIG, .L0, .VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F, 3, 0x92, 0xFF, .W1, .L0, .KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x70, 0xFF, .WIG, .L1, .VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x7C, 0xFF, .WIG, .L0, .VHADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x7C, 0xFF, .WIG, .L1, .VHADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x7D, 0xFF, .WIG, .L1, .VHSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x7D, 0xFF, .WIG, .L0, .VHSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F, 3, 0x92, 0xFF, .W0, .L0, .KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x92, 0xFF, .W1, .L0, .KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 3, 0x93, 0xFF, .W0, .L0, .KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 3, 0x93, 0xFF, .W1, .L0, .KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F, 3, 0xC2, 0xFF, .WIG, .LIG, .VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=4, needs_modrm=true}}, + {._0F, 3, 0xD0, 0xFF, .WIG, .L0, .VADDSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 3, 0xD0, 0xFF, .WIG, .L1, .VADDSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 3, 0xE6, 0xFF, .WIG, .L1, .VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F, 3, 0xE6, 0xFF, .WIG, .L0, .VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xF0, 0xFF, .WIG, .L1, .VLDDQU, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xF0, 0xFF, .WIG, .L0, .VLDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF2, 0xFF, .W1, .L0, .ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 0, 0xF2, 0xFF, .W0, .L0, .ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 0, 0xF3, 0x01, .W1, .L0, .BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -1771,36 +1791,36 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F38, 0, 0xF5, 0xFF, .W1, .L0, .BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 0, 0xF7, 0xFF, .W1, .L0, .BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 0, 0xF7, 0xFF, .W0, .L0, .BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x00, 0xFF, .WIG, .L0, .VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x00, 0xFF, .WIG, .L1, .VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x00, 0xFF, .WIG, .L0, .VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x01, 0xFF, .WIG, .L0, .VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x01, 0xFF, .WIG, .L1, .VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x02, 0xFF, .WIG, .L1, .VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x02, 0xFF, .WIG, .L0, .VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x02, 0xFF, .WIG, .L1, .VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x03, 0xFF, .WIG, .L0, .VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x03, 0xFF, .WIG, .L1, .VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x04, 0xFF, .WIG, .L0, .VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x04, 0xFF, .WIG, .L1, .VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x05, 0xFF, .WIG, .L0, .VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x05, 0xFF, .WIG, .L1, .VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x06, 0xFF, .WIG, .L1, .VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x06, 0xFF, .WIG, .L0, .VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x07, 0xFF, .WIG, .L1, .VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x06, 0xFF, .WIG, .L1, .VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x07, 0xFF, .WIG, .L0, .VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x07, 0xFF, .WIG, .L1, .VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x08, 0xFF, .WIG, .L1, .VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x08, 0xFF, .WIG, .L0, .VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x09, 0xFF, .WIG, .L0, .VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x09, 0xFF, .WIG, .L1, .VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x0A, 0xFF, .WIG, .L0, .VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x0A, 0xFF, .WIG, .L1, .VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0A, 0xFF, .WIG, .L0, .VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x0B, 0xFF, .WIG, .L1, .VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x0B, 0xFF, .WIG, .L0, .VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x0E, 0xFF, .WIG, .L1, .VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x0E, 0xFF, .WIG, .L0, .VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x0F, 0xFF, .WIG, .L0, .VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x0F, 0xFF, .WIG, .L1, .VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x13, 0xFF, .WIG, .L0, .VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0F, 0xFF, .WIG, .L0, .VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x13, 0xFF, .WIG, .L1, .VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x13, 0xFF, .WIG, .L0, .VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x16, 0xFF, .W0, .L1, .VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x17, 0xFF, .WIG, .L0, .VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x17, 0xFF, .WIG, .L1, .VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, @@ -1811,205 +1831,221 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x1A, 0xFF, .WIG, .L1, .VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x1C, 0xFF, .WIG, .L1, .VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x1C, 0xFF, .WIG, .L0, .VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1C, 0xFF, .WIG, .L1, .VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x1D, 0xFF, .WIG, .L0, .VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x1D, 0xFF, .WIG, .L1, .VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x1E, 0xFF, .WIG, .L0, .VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x1E, 0xFF, .WIG, .L1, .VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x20, 0xFF, .WIG, .L1, .VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1E, 0xFF, .WIG, .L0, .VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x20, 0xFF, .WIG, .L0, .VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x21, 0xFF, .WIG, .L0, .VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x20, 0xFF, .WIG, .L1, .VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x21, 0xFF, .WIG, .L1, .VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x21, 0xFF, .WIG, .L0, .VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x22, 0xFF, .WIG, .L1, .VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x22, 0xFF, .WIG, .L0, .VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x23, 0xFF, .WIG, .L0, .VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x23, 0xFF, .WIG, .L1, .VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x23, 0xFF, .WIG, .L0, .VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x24, 0xFF, .WIG, .L0, .VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x24, 0xFF, .WIG, .L1, .VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x25, 0xFF, .WIG, .L1, .VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x25, 0xFF, .WIG, .L0, .VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x28, 0xFF, .WIG, .L1, .VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x28, 0xFF, .WIG, .L0, .VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x29, 0xFF, .WIG, .L1, .VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x29, 0xFF, .WIG, .L0, .VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x29, 0xFF, .WIG, .L1, .VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2A, 0xFF, .WIG, .L0, .VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x2A, 0xFF, .WIG, .L1, .VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x2B, 0xFF, .WIG, .L1, .VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2B, 0xFF, .WIG, .L0, .VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2C, 0xFF, .WIG, .L0, .VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2C, 0xFF, .WIG, .L1, .VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x2D, 0xFF, .WIG, .L1, .VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2D, 0xFF, .WIG, .L0, .VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2D, 0xFF, .WIG, .L1, .VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2E, 0xFF, .WIG, .L0, .VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2E, 0xFF, .WIG, .L1, .VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2F, 0xFF, .WIG, .L1, .VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x2F, 0xFF, .WIG, .L0, .VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x30, 0xFF, .WIG, .L1, .VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x30, 0xFF, .WIG, .L0, .VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x30, 0xFF, .WIG, .L1, .VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x31, 0xFF, .WIG, .L1, .VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x31, 0xFF, .WIG, .L0, .VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x32, 0xFF, .WIG, .L1, .VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x32, 0xFF, .WIG, .L0, .VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x32, 0xFF, .WIG, .L1, .VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x33, 0xFF, .WIG, .L0, .VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x33, 0xFF, .WIG, .L1, .VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x34, 0xFF, .WIG, .L0, .VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x34, 0xFF, .WIG, .L1, .VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x35, 0xFF, .WIG, .L1, .VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x34, 0xFF, .WIG, .L0, .VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x35, 0xFF, .WIG, .L0, .VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x35, 0xFF, .WIG, .L1, .VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x36, 0xFF, .W0, .L1, .VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x37, 0xFF, .WIG, .L0, .VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x37, 0xFF, .WIG, .L1, .VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x37, 0xFF, .WIG, .L0, .VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x38, 0xFF, .WIG, .L0, .VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x38, 0xFF, .WIG, .L1, .VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x39, 0xFF, .WIG, .L0, .VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x39, 0xFF, .WIG, .L1, .VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3A, 0xFF, .WIG, .L0, .VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3A, 0xFF, .WIG, .L1, .VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x3B, 0xFF, .WIG, .L0, .VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3B, 0xFF, .WIG, .L1, .VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3B, 0xFF, .WIG, .L0, .VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3C, 0xFF, .WIG, .L1, .VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3C, 0xFF, .WIG, .L0, .VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x3D, 0xFF, .WIG, .L0, .VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3D, 0xFF, .WIG, .L1, .VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x3E, 0xFF, .WIG, .L1, .VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3D, 0xFF, .WIG, .L0, .VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3E, 0xFF, .WIG, .L0, .VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x3F, 0xFF, .WIG, .L0, .VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3E, 0xFF, .WIG, .L1, .VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x3F, 0xFF, .WIG, .L1, .VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3F, 0xFF, .WIG, .L0, .VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x40, 0xFF, .WIG, .L1, .VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x40, 0xFF, .WIG, .L0, .VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x41, 0xFF, .WIG, .L0, .VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x45, 0xFF, .W1, .L0, .VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x45, 0xFF, .W0, .L1, .VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x45, 0xFF, .W1, .L1, .VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x45, 0xFF, .W0, .L0, .VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x46, 0xFF, .W0, .L0, .VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W1, .L0, .VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W1, .L1, .VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W0, .L1, .VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x46, 0xFF, .W0, .L1, .VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x47, 0xFF, .W1, .L1, .VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x47, 0xFF, .W1, .L0, .VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W0, .L0, .VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x47, 0xFF, .W0, .L0, .VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W1, .L1, .VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x47, 0xFF, .W0, .L1, .VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W1, .L0, .VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x58, 0xFF, .W0, .L1, .VPBROADCASTD, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x58, 0xFF, .W0, .L0, .VPBROADCASTD, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x58, 0xFF, .W0, .L0, .VPBROADCASTD, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x58, 0xFF, .W0, .L1, .VPBROADCASTD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x59, 0xFF, .W0, .L1, .VPBROADCASTQ, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x59, 0xFF, .W0, .L0, .VPBROADCASTQ, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x59, 0xFF, .W0, .L0, .VPBROADCASTQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x59, 0xFF, .W0, .L1, .VPBROADCASTQ, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x5A, 0xFF, .WIG, .L1, .VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x8C, 0xFF, .W1, .L1, .VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x78, 0xFF, .W0, .L1, .VPBROADCASTB, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x78, 0xFF, .W0, .L0, .VPBROADCASTB, {.XMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x78, 0xFF, .W0, .L0, .VPBROADCASTB, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x78, 0xFF, .W0, .L1, .VPBROADCASTB, {.YMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x79, 0xFF, .W0, .L0, .VPBROADCASTW, {.XMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x79, 0xFF, .W0, .L1, .VPBROADCASTW, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x79, 0xFF, .W0, .L1, .VPBROADCASTW, {.YMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x79, 0xFF, .W0, .L0, .VPBROADCASTW, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x8C, 0xFF, .W0, .L0, .VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x8C, 0xFF, .W0, .L1, .VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x8C, 0xFF, .W1, .L0, .VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x8E, 0xFF, .W0, .L0, .VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W0, .L1, .VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W1, .L1, .VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x8E, 0xFF, .W1, .L1, .VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x8E, 0xFF, .W1, .L0, .VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x8E, 0xFF, .W0, .L1, .VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x90, 0xFF, .W0, .L1, .VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x90, 0xFF, .W0, .L0, .VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8E, 0xFF, .W0, .L0, .VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x90, 0xFF, .W1, .L1, .VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W0, .L1, .VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x90, 0xFF, .W1, .L0, .VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x91, 0xFF, .W1, .L1, .VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W0, .L0, .VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x91, 0xFF, .W0, .L1, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x91, 0xFF, .W1, .L0, .VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x91, 0xFF, .W0, .L0, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x92, 0xFF, .W1, .L0, .VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x92, 0xFF, .W0, .L0, .VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x91, 0xFF, .W1, .L1, .VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x92, 0xFF, .W0, .L1, .VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x92, 0xFF, .W1, .L1, .VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W1, .L0, .VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W0, .L0, .VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W0, .L1, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W1, .L1, .VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x93, 0xFF, .W1, .L0, .VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x93, 0xFF, .W0, .L0, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x93, 0xFF, .W1, .L1, .VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x93, 0xFF, .W0, .L1, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x96, 0xFF, .W1, .L0, .VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x96, 0xFF, .W0, .L1, .VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x96, 0xFF, .W1, .L1, .VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W1, .L0, .VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x96, 0xFF, .W0, .L0, .VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x97, 0xFF, .W1, .L0, .VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W0, .L1, .VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x97, 0xFF, .W1, .L1, .VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x97, 0xFF, .W0, .L1, .VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x97, 0xFF, .W0, .L0, .VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x97, 0xFF, .W1, .L0, .VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x98, 0xFF, .W1, .L0, .VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x98, 0xFF, .W1, .L1, .VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x98, 0xFF, .W0, .L0, .VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x98, 0xFF, .W0, .L1, .VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x98, 0xFF, .W0, .L0, .VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x99, 0xFF, .W1, .LIG, .VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x99, 0xFF, .W0, .LIG, .VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9A, 0xFF, .W1, .L0, .VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9A, 0xFF, .W0, .L1, .VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9A, 0xFF, .W1, .L1, .VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9A, 0xFF, .W0, .L0, .VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9A, 0xFF, .W0, .L1, .VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9B, 0xFF, .W0, .LIG, .VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9B, 0xFF, .W1, .LIG, .VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W1, .L0, .VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W0, .L1, .VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9C, 0xFF, .W0, .L0, .VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9C, 0xFF, .W1, .L1, .VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9C, 0xFF, .W0, .L1, .VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9C, 0xFF, .W1, .L0, .VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9D, 0xFF, .W1, .LIG, .VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9D, 0xFF, .W0, .LIG, .VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9E, 0xFF, .W0, .L1, .VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9D, 0xFF, .W1, .LIG, .VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W1, .L1, .VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9E, 0xFF, .W0, .L0, .VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9E, 0xFF, .W1, .L0, .VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0x9E, 0xFF, .W1, .L1, .VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W0, .L1, .VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9F, 0xFF, .W0, .LIG, .VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0x9F, 0xFF, .W1, .LIG, .VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xA6, 0xFF, .W1, .L1, .VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xA6, 0xFF, .W0, .L0, .VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA6, 0xFF, .W1, .L0, .VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W0, .L0, .VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA6, 0xFF, .W0, .L1, .VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xA7, 0xFF, .W1, .L0, .VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W1, .L1, .VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA7, 0xFF, .W1, .L1, .VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA7, 0xFF, .W1, .L0, .VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA7, 0xFF, .W0, .L0, .VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA7, 0xFF, .W0, .L1, .VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xA8, 0xFF, .W1, .L0, .VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA8, 0xFF, .W1, .L1, .VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA8, 0xFF, .W1, .L0, .VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA8, 0xFF, .W0, .L1, .VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA8, 0xFF, .W0, .L0, .VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xA9, 0xFF, .W0, .LIG, .VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xA9, 0xFF, .W1, .LIG, .VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA9, 0xFF, .W0, .LIG, .VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAA, 0xFF, .W1, .L0, .VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAA, 0xFF, .W1, .L1, .VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAA, 0xFF, .W0, .L0, .VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAA, 0xFF, .W0, .L1, .VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAA, 0xFF, .W1, .L1, .VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAB, 0xFF, .W1, .LIG, .VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAB, 0xFF, .W0, .LIG, .VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAC, 0xFF, .W0, .L1, .VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAC, 0xFF, .W1, .L1, .VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAC, 0xFF, .W0, .L0, .VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W1, .L1, .VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAC, 0xFF, .W1, .L0, .VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAD, 0xFF, .W1, .LIG, .VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W0, .L1, .VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAD, 0xFF, .W0, .LIG, .VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAE, 0xFF, .W0, .L1, .VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAE, 0xFF, .W1, .L0, .VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAE, 0xFF, .W1, .L1, .VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAD, 0xFF, .W1, .LIG, .VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAE, 0xFF, .W0, .L0, .VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xAF, 0xFF, .W0, .LIG, .VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W1, .L1, .VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W1, .L0, .VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W0, .L1, .VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xAF, 0xFF, .W1, .LIG, .VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB6, 0xFF, .W0, .L1, .VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAF, 0xFF, .W0, .LIG, .VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB6, 0xFF, .W0, .L0, .VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB6, 0xFF, .W1, .L0, .VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB6, 0xFF, .W1, .L1, .VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB7, 0xFF, .W1, .L0, .VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB7, 0xFF, .W0, .L1, .VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB7, 0xFF, .W0, .L0, .VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB6, 0xFF, .W0, .L1, .VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB7, 0xFF, .W1, .L1, .VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB8, 0xFF, .W1, .L1, .VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB8, 0xFF, .W0, .L1, .VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB8, 0xFF, .W0, .L0, .VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W1, .L0, .VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W0, .L0, .VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W0, .L1, .VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB8, 0xFF, .W1, .L0, .VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xB9, 0xFF, .W1, .LIG, .VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W0, .L0, .VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W0, .L1, .VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W1, .L1, .VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xB9, 0xFF, .W0, .LIG, .VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xBA, 0xFF, .W1, .L1, .VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xBA, 0xFF, .W1, .L0, .VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB9, 0xFF, .W1, .LIG, .VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBA, 0xFF, .W0, .L1, .VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBA, 0xFF, .W0, .L0, .VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W1, .L0, .VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W1, .L1, .VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBB, 0xFF, .W1, .LIG, .VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBB, 0xFF, .W0, .LIG, .VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBC, 0xFF, .W1, .L0, .VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBC, 0xFF, .W1, .L1, .VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBC, 0xFF, .W0, .L0, .VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBC, 0xFF, .W0, .L1, .VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xBD, 0xFF, .W1, .LIG, .VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBD, 0xFF, .W0, .LIG, .VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBD, 0xFF, .W1, .LIG, .VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBE, 0xFF, .W0, .L1, .VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBE, 0xFF, .W1, .L1, .VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBE, 0xFF, .W1, .L0, .VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xBE, 0xFF, .W0, .L1, .VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBE, 0xFF, .W0, .L0, .VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F38, 1, 0xBF, 0xFF, .W1, .LIG, .VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xBF, 0xFF, .W0, .LIG, .VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBF, 0xFF, .W1, .LIG, .VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xDB, 0xFF, .WIG, .L0, .VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDC, 0xFF, .WIG, .L0, .VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F38, 1, 0xDD, 0xFF, .WIG, .L0, .VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -2044,27 +2080,27 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F3A, 1, 0x0D, 0xFF, .WIG, .L0, .VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x0E, 0xFF, .WIG, .L1, .VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x0E, 0xFF, .WIG, .L0, .VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, - {._0F3A, 1, 0x0F, 0xFF, .WIG, .L1, .VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x0F, 0xFF, .WIG, .L0, .VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0F, 0xFF, .WIG, .L1, .VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x14, 0xFF, .WIG, .L0, .VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x15, 0xFF, .WIG, .L0, .VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F3A, 1, 0x16, 0xFF, .WIG, .L0, .VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x16, 0xFF, .W1, .L0, .VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x16, 0xFF, .WIG, .L0, .VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x17, 0xFF, .WIG, .L0, .VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x18, 0xFF, .WIG, .L1, .VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x19, 0xFF, .WIG, .L1, .VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, - {._0F3A, 1, 0x1D, 0xFF, .WIG, .L1, .VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x1D, 0xFF, .WIG, .L0, .VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x1D, 0xFF, .WIG, .L1, .VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x20, 0xFF, .WIG, .L0, .VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x21, 0xFF, .WIG, .L0, .VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, - {._0F3A, 1, 0x22, 0xFF, .WIG, .L0, .VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x22, 0xFF, .W1, .L0, .VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, - {._0F3A, 1, 0x30, 0xFF, .W0, .L0, .KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x22, 0xFF, .WIG, .L0, .VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x30, 0xFF, .W1, .L0, .KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x30, 0xFF, .W0, .L0, .KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x31, 0xFF, .W0, .L0, .KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x31, 0xFF, .W1, .L0, .KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, - {._0F3A, 1, 0x32, 0xFF, .W1, .L0, .KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x32, 0xFF, .W0, .L0, .KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x32, 0xFF, .W1, .L0, .KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x33, 0xFF, .W0, .L0, .KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x33, 0xFF, .W1, .L0, .KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x38, 0xFF, .WIG, .L1, .VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, @@ -2072,8 +2108,8 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F3A, 1, 0x40, 0xFF, .WIG, .L1, .VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x40, 0xFF, .WIG, .L0, .VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x41, 0xFF, .WIG, .L0, .VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, - {._0F3A, 1, 0x42, 0xFF, .WIG, .L0, .VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x42, 0xFF, .WIG, .L1, .VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .WIG, .L0, .VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x44, 0xFF, .WIG, .L0, .VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x44, 0xFF, .WIG, .L1, .VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x46, 0xFF, .WIG, .L1, .VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, @@ -2081,8 +2117,12 @@ VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ {._0F3A, 1, 0x4A, 0xFF, .W0, .L1, .VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x4B, 0xFF, .W0, .L1, .VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x4B, 0xFF, .W0, .L0, .VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, - {._0F3A, 1, 0x4C, 0xFF, .W0, .L1, .VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, {._0F3A, 1, 0x4C, 0xFF, .W0, .L0, .VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4C, 0xFF, .W0, .L1, .VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x60, 0xFF, .W0, .L0, .VPCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x61, 0xFF, .W0, .L0, .VPCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x62, 0xFF, .WIG, .L0, .VPCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x63, 0xFF, .WIG, .L0, .VPCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0xDF, 0xFF, .WIG, .L0, .VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 3, 0xF0, 0xFF, .W0, .L0, .RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, {._0F3A, 3, 0xF0, 0xFF, .W1, .L0, .RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, @@ -3219,214 +3259,228 @@ VEX_INDEX_0F := [4][256]lib.Decode_Index{ 0x74 = {199, 2}, 0x75 = {201, 2}, 0x76 = {203, 2}, - 0x7E = {205, 2}, - 0x7F = {207, 2}, - 0x90 = {209, 2}, - 0x91 = {211, 2}, - 0x92 = {213, 1}, - 0x93 = {214, 1}, - 0x98 = {215, 2}, - 0x99 = {217, 2}, - 0xC2 = {219, 2}, - 0xC4 = {221, 1}, - 0xC5 = {222, 1}, - 0xC6 = {223, 2}, - 0xD1 = {225, 2}, - 0xD2 = {227, 2}, - 0xD3 = {229, 2}, - 0xD4 = {231, 2}, - 0xD5 = {233, 2}, - 0xD6 = {235, 1}, - 0xD7 = {236, 2}, - 0xDB = {238, 2}, - 0xDF = {240, 2}, - 0xE1 = {242, 2}, - 0xE2 = {244, 2}, - 0xE4 = {246, 2}, - 0xE5 = {248, 2}, - 0xE6 = {250, 2}, - 0xE7 = {252, 2}, - 0xEB = {254, 2}, - 0xEF = {256, 2}, - 0xF1 = {258, 2}, - 0xF2 = {260, 2}, - 0xF3 = {262, 2}, - 0xF4 = {264, 2}, - 0xF5 = {266, 2}, - 0xF7 = {268, 1}, - 0xF8 = {269, 2}, - 0xF9 = {271, 2}, - 0xFA = {273, 2}, - 0xFB = {275, 2}, - 0xFC = {277, 2}, - 0xFD = {279, 2}, - 0xFE = {281, 2}, + 0x7C = {205, 2}, + 0x7D = {207, 2}, + 0x7E = {209, 2}, + 0x7F = {211, 2}, + 0x90 = {213, 2}, + 0x91 = {215, 2}, + 0x92 = {217, 1}, + 0x93 = {218, 1}, + 0x98 = {219, 2}, + 0x99 = {221, 2}, + 0xC2 = {223, 2}, + 0xC4 = {225, 1}, + 0xC5 = {226, 1}, + 0xC6 = {227, 2}, + 0xD0 = {229, 2}, + 0xD1 = {231, 2}, + 0xD2 = {233, 2}, + 0xD3 = {235, 2}, + 0xD4 = {237, 2}, + 0xD5 = {239, 2}, + 0xD6 = {241, 1}, + 0xD7 = {242, 2}, + 0xDB = {244, 2}, + 0xDF = {246, 2}, + 0xE1 = {248, 2}, + 0xE2 = {250, 2}, + 0xE4 = {252, 2}, + 0xE5 = {254, 2}, + 0xE6 = {256, 2}, + 0xE7 = {258, 2}, + 0xEB = {260, 2}, + 0xEF = {262, 2}, + 0xF1 = {264, 2}, + 0xF2 = {266, 2}, + 0xF3 = {268, 2}, + 0xF4 = {270, 2}, + 0xF5 = {272, 2}, + 0xF7 = {274, 1}, + 0xF8 = {275, 2}, + 0xF9 = {277, 2}, + 0xFA = {279, 2}, + 0xFB = {281, 2}, + 0xFC = {283, 2}, + 0xFD = {285, 2}, + 0xFE = {287, 2}, }, 2 = { /* prefix = F3 */ - 0x10 = {283, 2}, - 0x11 = {285, 1}, - 0x2A = {286, 2}, - 0x2C = {288, 2}, - 0x2D = {290, 2}, - 0x51 = {292, 1}, - 0x52 = {293, 1}, - 0x53 = {294, 1}, - 0x58 = {295, 1}, - 0x59 = {296, 1}, - 0x5A = {297, 1}, - 0x5B = {298, 2}, - 0x5C = {300, 1}, - 0x5D = {301, 1}, - 0x5E = {302, 1}, - 0x5F = {303, 1}, - 0x6F = {304, 2}, - 0x70 = {306, 2}, - 0x7E = {308, 1}, - 0x7F = {309, 2}, - 0xC2 = {311, 1}, - 0xE6 = {312, 2}, + 0x10 = {289, 2}, + 0x11 = {291, 1}, + 0x12 = {292, 2}, + 0x16 = {294, 2}, + 0x2A = {296, 2}, + 0x2C = {298, 2}, + 0x2D = {300, 2}, + 0x51 = {302, 1}, + 0x52 = {303, 1}, + 0x53 = {304, 1}, + 0x58 = {305, 1}, + 0x59 = {306, 1}, + 0x5A = {307, 1}, + 0x5B = {308, 2}, + 0x5C = {310, 1}, + 0x5D = {311, 1}, + 0x5E = {312, 1}, + 0x5F = {313, 1}, + 0x6F = {314, 2}, + 0x70 = {316, 2}, + 0x7E = {318, 1}, + 0x7F = {319, 2}, + 0xC2 = {321, 1}, + 0xE6 = {322, 2}, }, 3 = { /* prefix = F2 */ - 0x10 = {314, 2}, - 0x11 = {316, 1}, - 0x2A = {317, 2}, - 0x2C = {319, 2}, - 0x2D = {321, 2}, - 0x51 = {323, 1}, - 0x58 = {324, 1}, - 0x59 = {325, 1}, - 0x5A = {326, 1}, - 0x5C = {327, 1}, - 0x5D = {328, 1}, - 0x5E = {329, 1}, - 0x5F = {330, 1}, - 0x70 = {331, 2}, - 0x92 = {333, 2}, - 0x93 = {335, 2}, - 0xC2 = {337, 1}, - 0xE6 = {338, 2}, + 0x10 = {324, 2}, + 0x11 = {326, 1}, + 0x12 = {327, 2}, + 0x2A = {329, 2}, + 0x2C = {331, 2}, + 0x2D = {333, 2}, + 0x51 = {335, 1}, + 0x58 = {336, 1}, + 0x59 = {337, 1}, + 0x5A = {338, 1}, + 0x5C = {339, 1}, + 0x5D = {340, 1}, + 0x5E = {341, 1}, + 0x5F = {342, 1}, + 0x70 = {343, 2}, + 0x7C = {345, 2}, + 0x7D = {347, 2}, + 0x92 = {349, 2}, + 0x93 = {351, 2}, + 0xC2 = {353, 1}, + 0xD0 = {354, 2}, + 0xE6 = {356, 2}, + 0xF0 = {358, 2}, }, } @(rodata) VEX_INDEX_0F38 := [4][256]lib.Decode_Index{ 0 = { /* prefix = none */ - 0xF2 = {340, 2}, - 0xF3 = {342, 6}, - 0xF5 = {348, 2}, - 0xF7 = {350, 2}, + 0xF2 = {360, 2}, + 0xF3 = {362, 6}, + 0xF5 = {368, 2}, + 0xF7 = {370, 2}, }, 1 = { /* prefix = 66 */ - 0x00 = {352, 2}, - 0x01 = {354, 2}, - 0x02 = {356, 2}, - 0x03 = {358, 2}, - 0x04 = {360, 2}, - 0x05 = {362, 2}, - 0x06 = {364, 2}, - 0x07 = {366, 2}, - 0x08 = {368, 2}, - 0x09 = {370, 2}, - 0x0A = {372, 2}, - 0x0B = {374, 2}, - 0x0E = {376, 2}, - 0x0F = {378, 2}, - 0x13 = {380, 2}, - 0x16 = {382, 1}, - 0x17 = {383, 2}, - 0x18 = {385, 4}, - 0x19 = {389, 2}, - 0x1A = {391, 1}, - 0x1C = {392, 2}, - 0x1D = {394, 2}, - 0x1E = {396, 2}, - 0x20 = {398, 2}, - 0x21 = {400, 2}, - 0x22 = {402, 2}, - 0x23 = {404, 2}, - 0x24 = {406, 2}, - 0x25 = {408, 2}, - 0x28 = {410, 2}, - 0x29 = {412, 2}, - 0x2A = {414, 2}, - 0x2B = {416, 2}, - 0x2C = {418, 2}, - 0x2D = {420, 2}, - 0x2E = {422, 2}, - 0x2F = {424, 2}, - 0x30 = {426, 2}, - 0x31 = {428, 2}, - 0x32 = {430, 2}, - 0x33 = {432, 2}, - 0x34 = {434, 2}, - 0x35 = {436, 2}, - 0x36 = {438, 1}, - 0x37 = {439, 2}, - 0x38 = {441, 2}, - 0x39 = {443, 2}, - 0x3A = {445, 2}, - 0x3B = {447, 2}, - 0x3C = {449, 2}, - 0x3D = {451, 2}, - 0x3E = {453, 2}, - 0x3F = {455, 2}, - 0x40 = {457, 2}, - 0x41 = {459, 1}, - 0x45 = {460, 4}, - 0x46 = {464, 2}, - 0x47 = {466, 4}, - 0x5A = {470, 1}, - 0x8C = {471, 4}, - 0x8E = {475, 4}, - 0x90 = {479, 4}, - 0x91 = {483, 4}, - 0x92 = {487, 4}, - 0x93 = {491, 4}, - 0x96 = {495, 4}, - 0x97 = {499, 4}, - 0x98 = {503, 4}, - 0x99 = {507, 2}, - 0x9A = {509, 4}, - 0x9B = {513, 2}, - 0x9C = {515, 4}, - 0x9D = {519, 2}, - 0x9E = {521, 4}, - 0x9F = {525, 2}, - 0xA6 = {527, 4}, - 0xA7 = {531, 4}, - 0xA8 = {535, 4}, - 0xA9 = {539, 2}, - 0xAA = {541, 4}, - 0xAB = {545, 2}, - 0xAC = {547, 4}, - 0xAD = {551, 2}, - 0xAE = {553, 4}, - 0xAF = {557, 2}, - 0xB6 = {559, 4}, - 0xB7 = {563, 4}, - 0xB8 = {567, 4}, - 0xB9 = {571, 2}, - 0xBA = {573, 4}, - 0xBB = {577, 2}, - 0xBC = {579, 4}, - 0xBD = {583, 2}, - 0xBE = {585, 4}, - 0xBF = {589, 2}, - 0xDB = {591, 1}, - 0xDC = {592, 1}, - 0xDD = {593, 1}, - 0xDE = {594, 1}, - 0xDF = {595, 1}, - 0xF7 = {596, 2}, + 0x00 = {372, 2}, + 0x01 = {374, 2}, + 0x02 = {376, 2}, + 0x03 = {378, 2}, + 0x04 = {380, 2}, + 0x05 = {382, 2}, + 0x06 = {384, 2}, + 0x07 = {386, 2}, + 0x08 = {388, 2}, + 0x09 = {390, 2}, + 0x0A = {392, 2}, + 0x0B = {394, 2}, + 0x0E = {396, 2}, + 0x0F = {398, 2}, + 0x13 = {400, 2}, + 0x16 = {402, 1}, + 0x17 = {403, 2}, + 0x18 = {405, 4}, + 0x19 = {409, 2}, + 0x1A = {411, 1}, + 0x1C = {412, 2}, + 0x1D = {414, 2}, + 0x1E = {416, 2}, + 0x20 = {418, 2}, + 0x21 = {420, 2}, + 0x22 = {422, 2}, + 0x23 = {424, 2}, + 0x24 = {426, 2}, + 0x25 = {428, 2}, + 0x28 = {430, 2}, + 0x29 = {432, 2}, + 0x2A = {434, 2}, + 0x2B = {436, 2}, + 0x2C = {438, 2}, + 0x2D = {440, 2}, + 0x2E = {442, 2}, + 0x2F = {444, 2}, + 0x30 = {446, 2}, + 0x31 = {448, 2}, + 0x32 = {450, 2}, + 0x33 = {452, 2}, + 0x34 = {454, 2}, + 0x35 = {456, 2}, + 0x36 = {458, 1}, + 0x37 = {459, 2}, + 0x38 = {461, 2}, + 0x39 = {463, 2}, + 0x3A = {465, 2}, + 0x3B = {467, 2}, + 0x3C = {469, 2}, + 0x3D = {471, 2}, + 0x3E = {473, 2}, + 0x3F = {475, 2}, + 0x40 = {477, 2}, + 0x41 = {479, 1}, + 0x45 = {480, 4}, + 0x46 = {484, 2}, + 0x47 = {486, 4}, + 0x58 = {490, 4}, + 0x59 = {494, 4}, + 0x5A = {498, 1}, + 0x78 = {499, 4}, + 0x79 = {503, 4}, + 0x8C = {507, 4}, + 0x8E = {511, 4}, + 0x90 = {515, 4}, + 0x91 = {519, 4}, + 0x92 = {523, 4}, + 0x93 = {527, 4}, + 0x96 = {531, 4}, + 0x97 = {535, 4}, + 0x98 = {539, 4}, + 0x99 = {543, 2}, + 0x9A = {545, 4}, + 0x9B = {549, 2}, + 0x9C = {551, 4}, + 0x9D = {555, 2}, + 0x9E = {557, 4}, + 0x9F = {561, 2}, + 0xA6 = {563, 4}, + 0xA7 = {567, 4}, + 0xA8 = {571, 4}, + 0xA9 = {575, 2}, + 0xAA = {577, 4}, + 0xAB = {581, 2}, + 0xAC = {583, 4}, + 0xAD = {587, 2}, + 0xAE = {589, 4}, + 0xAF = {593, 2}, + 0xB6 = {595, 4}, + 0xB7 = {599, 4}, + 0xB8 = {603, 4}, + 0xB9 = {607, 2}, + 0xBA = {609, 4}, + 0xBB = {613, 2}, + 0xBC = {615, 4}, + 0xBD = {619, 2}, + 0xBE = {621, 4}, + 0xBF = {625, 2}, + 0xDB = {627, 1}, + 0xDC = {628, 1}, + 0xDD = {629, 1}, + 0xDE = {630, 1}, + 0xDF = {631, 1}, + 0xF7 = {632, 2}, }, 2 = { /* prefix = F3 */ - 0xF5 = {598, 2}, - 0xF7 = {600, 2}, + 0xF5 = {634, 2}, + 0xF7 = {636, 2}, }, 3 = { /* prefix = F2 */ - 0xF5 = {602, 2}, - 0xF6 = {604, 2}, - 0xF7 = {606, 2}, + 0xF5 = {638, 2}, + 0xF6 = {640, 2}, + 0xF7 = {642, 2}, }, } @@ -3434,47 +3488,51 @@ VEX_INDEX_0F38 := [4][256]lib.Decode_Index{ VEX_INDEX_0F3A := [4][256]lib.Decode_Index{ 0 = { /* prefix = none */ }, 1 = { /* prefix = 66 */ - 0x00 = {608, 1}, - 0x01 = {609, 1}, - 0x02 = {610, 2}, - 0x06 = {612, 1}, - 0x08 = {613, 2}, - 0x09 = {615, 2}, - 0x0A = {617, 1}, - 0x0B = {618, 1}, - 0x0C = {619, 2}, - 0x0D = {621, 2}, - 0x0E = {623, 2}, - 0x0F = {625, 2}, - 0x14 = {627, 1}, - 0x15 = {628, 1}, - 0x16 = {629, 2}, - 0x17 = {631, 1}, - 0x18 = {632, 1}, - 0x19 = {633, 1}, - 0x1D = {634, 2}, - 0x20 = {636, 1}, - 0x21 = {637, 1}, - 0x22 = {638, 2}, - 0x30 = {640, 2}, - 0x31 = {642, 2}, - 0x32 = {644, 2}, - 0x33 = {646, 2}, - 0x38 = {648, 1}, - 0x39 = {649, 1}, - 0x40 = {650, 2}, - 0x41 = {652, 1}, - 0x42 = {653, 2}, - 0x44 = {655, 2}, - 0x46 = {657, 1}, - 0x4A = {658, 2}, - 0x4B = {660, 2}, - 0x4C = {662, 2}, - 0xDF = {664, 1}, + 0x00 = {644, 1}, + 0x01 = {645, 1}, + 0x02 = {646, 2}, + 0x06 = {648, 1}, + 0x08 = {649, 2}, + 0x09 = {651, 2}, + 0x0A = {653, 1}, + 0x0B = {654, 1}, + 0x0C = {655, 2}, + 0x0D = {657, 2}, + 0x0E = {659, 2}, + 0x0F = {661, 2}, + 0x14 = {663, 1}, + 0x15 = {664, 1}, + 0x16 = {665, 2}, + 0x17 = {667, 1}, + 0x18 = {668, 1}, + 0x19 = {669, 1}, + 0x1D = {670, 2}, + 0x20 = {672, 1}, + 0x21 = {673, 1}, + 0x22 = {674, 2}, + 0x30 = {676, 2}, + 0x31 = {678, 2}, + 0x32 = {680, 2}, + 0x33 = {682, 2}, + 0x38 = {684, 1}, + 0x39 = {685, 1}, + 0x40 = {686, 2}, + 0x41 = {688, 1}, + 0x42 = {689, 2}, + 0x44 = {691, 2}, + 0x46 = {693, 1}, + 0x4A = {694, 2}, + 0x4B = {696, 2}, + 0x4C = {698, 2}, + 0x60 = {700, 1}, + 0x61 = {701, 1}, + 0x62 = {702, 1}, + 0x63 = {703, 1}, + 0xDF = {704, 1}, }, 2 = { /* prefix = F3 */ }, 3 = { /* prefix = F2 */ - 0xF0 = {665, 2}, + 0xF0 = {705, 2}, }, } diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 3cbdec673..fa4a01692 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_x86_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2355]lib.Encoding{ +ENCODE_FORMS := [2395]lib.Encoding{ // .MOV {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {explicit_count=2}}, {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}}, @@ -1762,6 +1762,64 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .VMOVNTDQA {.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, {.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + // .VADDSUBPS + {.VADDSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VADDSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VADDSUBPD + {.VADDSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VADDSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VHADDPS + {.VHADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VHADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VHADDPD + {.VHADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VHADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VHSUBPS + {.VHSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VHSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VHSUBPD + {.VHSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VHSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + // .VLDDQU + {.VLDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VLDDQU, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + // .VMOVDDUP + {.VMOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVDDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + // .VMOVSLDUP + {.VMOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVSLDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + // .VMOVSHDUP + {.VMOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVSHDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + // .VPCMPESTRI + {.VPCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + // .VPCMPESTRM + {.VPCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + // .VPCMPISTRI + {.VPCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + // .VPCMPISTRM + {.VPCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + // .VPBROADCASTB + {.VPBROADCASTB, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTB, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPBROADCASTB, {.XMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTB, {.YMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + // .VPBROADCASTW + {.VPBROADCASTW, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTW, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPBROADCASTW, {.XMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTW, {.YMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + // .VPBROADCASTD + {.VPBROADCASTD, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPBROADCASTD, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTD, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + // .VPBROADCASTQ + {.VPBROADCASTQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTQ, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPBROADCASTQ, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPBROADCASTQ, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, // .VCVTPS2PD {.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, {.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, @@ -4114,615 +4172,633 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .VMOVNTPD = { 1177, 2}, .VMOVNTDQ = { 1179, 2}, .VMOVNTDQA = { 1181, 2}, - .VCVTPS2PD = { 1183, 2}, - .VCVTPD2PS = { 1185, 2}, - .VCVTSS2SD = { 1187, 1}, - .VCVTSD2SS = { 1188, 1}, - .VCVTPS2DQ = { 1189, 2}, - .VCVTPD2DQ = { 1191, 2}, - .VCVTDQ2PS = { 1193, 2}, - .VCVTDQ2PD = { 1195, 2}, - .VCVTSS2SI = { 1197, 2}, - .VCVTSD2SI = { 1199, 2}, - .VCVTSI2SS = { 1201, 2}, - .VCVTSI2SD = { 1203, 2}, - .VCVTTPS2DQ = { 1205, 2}, - .VCVTTPD2DQ = { 1207, 2}, - .VCVTTSS2SI = { 1209, 2}, - .VCVTTSD2SI = { 1211, 2}, - .VPADDB = { 1213, 2}, - .VPADDW = { 1215, 2}, - .VPADDD = { 1217, 2}, - .VPADDQ = { 1219, 2}, - .VPSUBB = { 1221, 2}, - .VPSUBW = { 1223, 2}, - .VPSUBD = { 1225, 2}, - .VPSUBQ = { 1227, 2}, - .VPMULLW = { 1229, 2}, - .VPMULHW = { 1231, 2}, - .VPMULHUW = { 1233, 2}, - .VPMULUDQ = { 1235, 2}, - .VPMADDWD = { 1237, 2}, - .VPAND = { 1239, 2}, - .VPANDN = { 1241, 2}, - .VPOR = { 1243, 2}, - .VPXOR = { 1245, 2}, - .VPSLLW = { 1247, 4}, - .VPSLLD = { 1251, 4}, - .VPSLLQ = { 1255, 4}, - .VPSRLW = { 1259, 4}, - .VPSRLD = { 1263, 4}, - .VPSRLQ = { 1267, 4}, - .VPSRAW = { 1271, 4}, - .VPSRAD = { 1275, 4}, - .VPCMPEQB = { 1279, 2}, - .VPCMPEQW = { 1281, 2}, - .VPCMPEQD = { 1283, 2}, - .VPCMPEQQ = { 1285, 2}, - .VPCMPGTB = { 1287, 2}, - .VPCMPGTW = { 1289, 2}, - .VPCMPGTD = { 1291, 2}, - .VPCMPGTQ = { 1293, 2}, - .VPACKSSWB = { 1295, 2}, - .VPACKSSDW = { 1297, 2}, - .VPACKUSWB = { 1299, 2}, - .VPACKUSDW = { 1301, 2}, - .VPUNPCKLBW = { 1303, 2}, - .VPUNPCKLWD = { 1305, 2}, - .VPUNPCKLDQ = { 1307, 2}, - .VPUNPCKLQDQ = { 1309, 2}, - .VPUNPCKHBW = { 1311, 2}, - .VPUNPCKHWD = { 1313, 2}, - .VPUNPCKHDQ = { 1315, 2}, - .VPUNPCKHQDQ = { 1317, 2}, - .VPSHUFD = { 1319, 2}, - .VPSHUFHW = { 1321, 2}, - .VPSHUFLW = { 1323, 2}, - .VPEXTRB = { 1325, 1}, - .VPEXTRW = { 1326, 2}, - .VPEXTRD = { 1328, 1}, - .VPEXTRQ = { 1329, 1}, - .VPINSRB = { 1330, 1}, - .VPINSRW = { 1331, 1}, - .VPINSRD = { 1332, 1}, - .VPINSRQ = { 1333, 1}, - .VPMOVMSKB = { 1334, 2}, - .VPTEST = { 1336, 2}, - .VPSHUFB = { 1338, 2}, - .VPHADDW = { 1340, 2}, - .VPHADDD = { 1342, 2}, - .VPHADDSW = { 1344, 2}, - .VPHSUBW = { 1346, 2}, - .VPHSUBD = { 1348, 2}, - .VPHSUBSW = { 1350, 2}, - .VPMADDUBSW = { 1352, 2}, - .VPMULHRSW = { 1354, 2}, - .VPSIGNB = { 1356, 2}, - .VPSIGNW = { 1358, 2}, - .VPSIGND = { 1360, 2}, - .VPABSB = { 1362, 2}, - .VPABSW = { 1364, 2}, - .VPABSD = { 1366, 2}, - .VPALIGNR = { 1368, 2}, - .VPBLENDW = { 1370, 2}, - .VPBLENDVB = { 1372, 2}, - .VMPSADBW = { 1374, 2}, - .VPHMINPOSUW = { 1376, 1}, - .VPMAXSB = { 1377, 2}, - .VPMAXSD = { 1379, 2}, - .VPMAXUW = { 1381, 2}, - .VPMAXUD = { 1383, 2}, - .VPMINSB = { 1385, 2}, - .VPMINSD = { 1387, 2}, - .VPMINUW = { 1389, 2}, - .VPMINUD = { 1391, 2}, - .VPMOVSXBW = { 1393, 2}, - .VPMOVSXBD = { 1395, 2}, - .VPMOVSXBQ = { 1397, 2}, - .VPMOVSXWD = { 1399, 2}, - .VPMOVSXWQ = { 1401, 2}, - .VPMOVSXDQ = { 1403, 2}, - .VPMOVZXBW = { 1405, 2}, - .VPMOVZXBD = { 1407, 2}, - .VPMOVZXBQ = { 1409, 2}, - .VPMOVZXWD = { 1411, 2}, - .VPMOVZXWQ = { 1413, 2}, - .VPMOVZXDQ = { 1415, 2}, - .VPMULDQ = { 1417, 2}, - .VPMULLD = { 1419, 2}, - .VMASKMOVDQU = { 1421, 1}, - .VPCLMULQDQ = { 1422, 2}, - .VAESDEC = { 1424, 1}, - .VAESDECLAST = { 1425, 1}, - .VAESENC = { 1426, 1}, - .VAESENCLAST = { 1427, 1}, - .VAESIMC = { 1428, 1}, - .VAESKEYGENASSIST = { 1429, 1}, - .VBROADCASTSS = { 1430, 4}, - .VBROADCASTSD = { 1434, 2}, - .VBROADCASTF128 = { 1436, 1}, - .VEXTRACTF128 = { 1437, 1}, - .VINSERTF128 = { 1438, 1}, - .VPERM2F128 = { 1439, 1}, - .VMASKMOVPS = { 1440, 4}, - .VMASKMOVPD = { 1444, 4}, - .VTESTPS = { 1448, 2}, - .VTESTPD = { 1450, 2}, - .VZEROALL = { 1452, 1}, - .VZEROUPPER = { 1453, 1}, - .VBROADCASTI128 = { 1454, 1}, - .VEXTRACTI128 = { 1455, 1}, - .VINSERTI128 = { 1456, 1}, - .VPERM2I128 = { 1457, 1}, - .VPERMD = { 1458, 1}, - .VPERMPS = { 1459, 1}, - .VPERMQ = { 1460, 1}, - .VPERMPD = { 1461, 1}, - .VPBLENDD = { 1462, 2}, - .VPSLLVD = { 1464, 2}, - .VPSLLVQ = { 1466, 2}, - .VPSRLVD = { 1468, 2}, - .VPSRLVQ = { 1470, 2}, - .VPSRAVD = { 1472, 2}, - .VPMASKMOVD = { 1474, 4}, - .VPMASKMOVQ = { 1478, 4}, - .VGATHERDPS = { 1482, 2}, - .VGATHERDPD = { 1484, 2}, - .VGATHERQPS = { 1486, 2}, - .VGATHERQPD = { 1488, 2}, - .VPGATHERDD = { 1490, 2}, - .VPGATHERDQ = { 1492, 2}, - .VPGATHERQD = { 1494, 2}, - .VPGATHERQQ = { 1496, 2}, - .VFMADD132PS = { 1498, 2}, - .VFMADD213PS = { 1500, 2}, - .VFMADD231PS = { 1502, 2}, - .VFMADD132PD = { 1504, 2}, - .VFMADD213PD = { 1506, 2}, - .VFMADD231PD = { 1508, 2}, - .VFMADD132SS = { 1510, 1}, - .VFMADD213SS = { 1511, 1}, - .VFMADD231SS = { 1512, 1}, - .VFMADD132SD = { 1513, 1}, - .VFMADD213SD = { 1514, 1}, - .VFMADD231SD = { 1515, 1}, - .VFMSUB132PS = { 1516, 2}, - .VFMSUB213PS = { 1518, 2}, - .VFMSUB231PS = { 1520, 2}, - .VFMSUB132PD = { 1522, 2}, - .VFMSUB213PD = { 1524, 2}, - .VFMSUB231PD = { 1526, 2}, - .VFMSUB132SS = { 1528, 1}, - .VFMSUB213SS = { 1529, 1}, - .VFMSUB231SS = { 1530, 1}, - .VFMSUB132SD = { 1531, 1}, - .VFMSUB213SD = { 1532, 1}, - .VFMSUB231SD = { 1533, 1}, - .VFNMADD132PS = { 1534, 2}, - .VFNMADD213PS = { 1536, 2}, - .VFNMADD231PS = { 1538, 2}, - .VFNMADD132PD = { 1540, 2}, - .VFNMADD213PD = { 1542, 2}, - .VFNMADD231PD = { 1544, 2}, - .VFNMADD132SS = { 1546, 1}, - .VFNMADD213SS = { 1547, 1}, - .VFNMADD231SS = { 1548, 1}, - .VFNMADD132SD = { 1549, 1}, - .VFNMADD213SD = { 1550, 1}, - .VFNMADD231SD = { 1551, 1}, - .VFNMSUB132PS = { 1552, 2}, - .VFNMSUB213PS = { 1554, 2}, - .VFNMSUB231PS = { 1556, 2}, - .VFNMSUB132PD = { 1558, 2}, - .VFNMSUB213PD = { 1560, 2}, - .VFNMSUB231PD = { 1562, 2}, - .VFNMSUB132SS = { 1564, 1}, - .VFNMSUB213SS = { 1565, 1}, - .VFNMSUB231SS = { 1566, 1}, - .VFNMSUB132SD = { 1567, 1}, - .VFNMSUB213SD = { 1568, 1}, - .VFNMSUB231SD = { 1569, 1}, - .VFMADDSUB132PS = { 1570, 2}, - .VFMADDSUB213PS = { 1572, 2}, - .VFMADDSUB231PS = { 1574, 2}, - .VFMADDSUB132PD = { 1576, 2}, - .VFMADDSUB213PD = { 1578, 2}, - .VFMADDSUB231PD = { 1580, 2}, - .VFMSUBADD132PS = { 1582, 2}, - .VFMSUBADD213PS = { 1584, 2}, - .VFMSUBADD231PS = { 1586, 2}, - .VFMSUBADD132PD = { 1588, 2}, - .VFMSUBADD213PD = { 1590, 2}, - .VFMSUBADD231PD = { 1592, 2}, - .VCVTPH2PS = { 1594, 3}, - .VCVTPS2PH = { 1597, 3}, - .VMOVDQA32 = { 1600, 6}, - .VMOVDQA64 = { 1606, 6}, - .VMOVDQU8 = { 1612, 6}, - .VMOVDQU16 = { 1618, 6}, - .VMOVDQU32 = { 1624, 6}, - .VMOVDQU64 = { 1630, 6}, - .VPBLENDMB = { 1636, 3}, - .VPBLENDMW = { 1639, 3}, - .VPBLENDMD = { 1642, 3}, - .VPBLENDMQ = { 1645, 3}, - .VBLENDMPS = { 1648, 3}, - .VBLENDMPD = { 1651, 3}, - .VPCMPB = { 1654, 3}, - .VPCMPUB = { 1657, 3}, - .VPCMPW = { 1660, 3}, - .VPCMPUW = { 1663, 3}, - .VPCMPD = { 1666, 3}, - .VPCMPUD = { 1669, 3}, - .VPCMPQ = { 1672, 3}, - .VPCMPUQ = { 1675, 3}, - .VPTESTMB = { 1678, 3}, - .VPTESTMW = { 1681, 3}, - .VPTESTMD = { 1684, 3}, - .VPTESTMQ = { 1687, 3}, - .VPTESTNMB = { 1690, 3}, - .VPTESTNMW = { 1693, 3}, - .VPTESTNMD = { 1696, 3}, - .VPTESTNMQ = { 1699, 3}, - .VPCOMPRESSD = { 1702, 3}, - .VPCOMPRESSQ = { 1705, 3}, - .VCOMPRESSPS = { 1708, 3}, - .VCOMPRESSPD = { 1711, 3}, - .VPEXPANDD = { 1714, 3}, - .VPEXPANDQ = { 1717, 3}, - .VEXPANDPS = { 1720, 3}, - .VEXPANDPD = { 1723, 3}, - .VPCONFLICTD = { 1726, 3}, - .VPCONFLICTQ = { 1729, 3}, - .VPLZCNTD = { 1732, 3}, - .VPLZCNTQ = { 1735, 3}, - .VPERMI2B = { 1738, 3}, - .VPERMI2W = { 1741, 3}, - .VPERMI2D = { 1744, 3}, - .VPERMI2Q = { 1747, 3}, - .VPERMI2PS = { 1750, 3}, - .VPERMI2PD = { 1753, 3}, - .VPERMT2B = { 1756, 3}, - .VPERMT2W = { 1759, 3}, - .VPERMT2D = { 1762, 3}, - .VPERMT2Q = { 1765, 3}, - .VPERMT2PS = { 1768, 3}, - .VPERMT2PD = { 1771, 3}, - .VPERMB = { 1774, 3}, - .VPERMW = { 1777, 3}, - .VPMOVB2M = { 1780, 3}, - .VPMOVW2M = { 1783, 3}, - .VPMOVD2M = { 1786, 3}, - .VPMOVQ2M = { 1789, 3}, - .VPMOVM2B = { 1792, 3}, - .VPMOVM2W = { 1795, 3}, - .VPMOVM2D = { 1798, 3}, - .VPMOVM2Q = { 1801, 3}, - .VPMOVQB = { 1804, 3}, - .VPMOVSQB = { 1807, 3}, - .VPMOVUSQB = { 1810, 3}, - .VPMOVQW = { 1813, 3}, - .VPMOVSQW = { 1816, 3}, - .VPMOVUSQW = { 1819, 3}, - .VPMOVQD = { 1822, 3}, - .VPMOVSQD = { 1825, 3}, - .VPMOVUSQD = { 1828, 3}, - .VPMOVDB = { 1831, 3}, - .VPMOVSDB = { 1834, 3}, - .VPMOVUSDB = { 1837, 3}, - .VPMOVDW = { 1840, 3}, - .VPMOVSDW = { 1843, 3}, - .VPMOVUSDW = { 1846, 3}, - .VPMOVWB = { 1849, 3}, - .VPMOVSWB = { 1852, 3}, - .VPMOVUSWB = { 1855, 3}, - .VPROLD = { 1858, 3}, - .VPROLQ = { 1861, 3}, - .VPROLVD = { 1864, 3}, - .VPROLVQ = { 1867, 3}, - .VPRORD = { 1870, 3}, - .VPRORQ = { 1873, 3}, - .VPRORVD = { 1876, 3}, - .VPRORVQ = { 1879, 3}, - .VPSCATTERDD = { 1882, 3}, - .VPSCATTERDQ = { 1885, 3}, - .VPSCATTERQD = { 1888, 3}, - .VPSCATTERQQ = { 1891, 3}, - .VSCATTERDPS = { 1894, 3}, - .VSCATTERDPD = { 1897, 3}, - .VSCATTERQPS = { 1900, 3}, - .VSCATTERQPD = { 1903, 3}, - .VPSRAVQ = { 1906, 3}, - .VPSRAVW = { 1909, 3}, - .VPSLLVW = { 1912, 3}, - .VPSRLVW = { 1915, 3}, - .VRANGEPS = { 1918, 3}, - .VRANGEPD = { 1921, 3}, - .VRANGESS = { 1924, 1}, - .VRANGESD = { 1925, 1}, - .VREDUCEPS = { 1926, 3}, - .VREDUCEPD = { 1929, 3}, - .VREDUCESS = { 1932, 1}, - .VREDUCESD = { 1933, 1}, - .VRNDSCALEPS = { 1934, 3}, - .VRNDSCALEPD = { 1937, 3}, - .VRNDSCALESS = { 1940, 1}, - .VRNDSCALESD = { 1941, 1}, - .VRSQRT14PS = { 1942, 3}, - .VRSQRT14PD = { 1945, 3}, - .VRSQRT14SS = { 1948, 1}, - .VRSQRT14SD = { 1949, 1}, - .VRCP14PS = { 1950, 3}, - .VRCP14PD = { 1953, 3}, - .VRCP14SS = { 1956, 1}, - .VRCP14SD = { 1957, 1}, - .VSCALEFPS = { 1958, 3}, - .VSCALEFPD = { 1961, 3}, - .VSCALEFSS = { 1964, 1}, - .VSCALEFSD = { 1965, 1}, - .VGETEXPPS = { 1966, 3}, - .VGETEXPPD = { 1969, 3}, - .VGETEXPSS = { 1972, 1}, - .VGETEXPSD = { 1973, 1}, - .VGETMANTPS = { 1974, 3}, - .VGETMANTPD = { 1977, 3}, - .VGETMANTSS = { 1980, 1}, - .VGETMANTSD = { 1981, 1}, - .VFIXUPIMMPS = { 1982, 3}, - .VFIXUPIMMPD = { 1985, 3}, - .VFIXUPIMMSS = { 1988, 1}, - .VFIXUPIMMSD = { 1989, 1}, - .VFPCLASSPS = { 1990, 3}, - .VFPCLASSPD = { 1993, 3}, - .VFPCLASSSS = { 1996, 1}, - .VFPCLASSSD = { 1997, 1}, - .VALIGNQ = { 1998, 3}, - .VALIGND = { 2001, 3}, - .VDBPSADBW = { 2004, 3}, - .VPTERNLOGD = { 2007, 3}, - .VPTERNLOGQ = { 2010, 3}, - .VPMULTISHIFTQB = { 2013, 3}, - .KADDW = { 2016, 1}, - .KADDB = { 2017, 1}, - .KADDQ = { 2018, 1}, - .KADDD = { 2019, 1}, - .KANDW = { 2020, 1}, - .KANDB = { 2021, 1}, - .KANDQ = { 2022, 1}, - .KANDD = { 2023, 1}, - .KANDNW = { 2024, 1}, - .KANDNB = { 2025, 1}, - .KANDNQ = { 2026, 1}, - .KANDND = { 2027, 1}, - .KMOVW = { 2028, 4}, - .KMOVB = { 2032, 4}, - .KMOVQ = { 2036, 4}, - .KMOVD = { 2040, 4}, - .KNOTW = { 2044, 1}, - .KNOTB = { 2045, 1}, - .KNOTQ = { 2046, 1}, - .KNOTD = { 2047, 1}, - .KORW = { 2048, 1}, - .KORB = { 2049, 1}, - .KORQ = { 2050, 1}, - .KORD = { 2051, 1}, - .KORTESTW = { 2052, 1}, - .KORTESTB = { 2053, 1}, - .KORTESTQ = { 2054, 1}, - .KORTESTD = { 2055, 1}, - .KSHIFTLW = { 2056, 1}, - .KSHIFTLB = { 2057, 1}, - .KSHIFTLQ = { 2058, 1}, - .KSHIFTLD = { 2059, 1}, - .KSHIFTRW = { 2060, 1}, - .KSHIFTRB = { 2061, 1}, - .KSHIFTRQ = { 2062, 1}, - .KSHIFTRD = { 2063, 1}, - .KTESTW = { 2064, 1}, - .KTESTB = { 2065, 1}, - .KTESTQ = { 2066, 1}, - .KTESTD = { 2067, 1}, - .KUNPCKBW = { 2068, 1}, - .KUNPCKWD = { 2069, 1}, - .KUNPCKDQ = { 2070, 1}, - .KXNORW = { 2071, 1}, - .KXNORB = { 2072, 1}, - .KXNORQ = { 2073, 1}, - .KXNORD = { 2074, 1}, - .KXORW = { 2075, 1}, - .KXORB = { 2076, 1}, - .KXORQ = { 2077, 1}, - .KXORD = { 2078, 1}, - .FADD = { 2079, 4}, - .FADDP = { 2083, 2}, - .FIADD = { 2085, 2}, - .FSUB = { 2087, 4}, - .FSUBP = { 2091, 2}, - .FISUB = { 2093, 2}, - .FSUBR = { 2095, 4}, - .FSUBRP = { 2099, 2}, - .FISUBR = { 2101, 2}, - .FMUL = { 2103, 4}, - .FMULP = { 2107, 2}, - .FIMUL = { 2109, 2}, - .FDIV = { 2111, 4}, - .FDIVP = { 2115, 2}, - .FIDIV = { 2117, 2}, - .FDIVR = { 2119, 4}, - .FDIVRP = { 2123, 2}, - .FIDIVR = { 2125, 2}, - .FSQRT = { 2127, 1}, - .FABS = { 2128, 1}, - .FCHS = { 2129, 1}, - .FPREM = { 2130, 1}, - .FPREM1 = { 2131, 1}, - .FRNDINT = { 2132, 1}, - .FSCALE = { 2133, 1}, - .FXTRACT = { 2134, 1}, - .FXAM = { 2135, 1}, - .FLD = { 2136, 4}, - .FILD = { 2140, 3}, - .FBLD = { 2143, 1}, - .FST = { 2144, 3}, - .FSTP = { 2147, 4}, - .FIST = { 2151, 2}, - .FISTP = { 2153, 3}, - .FISTTP = { 2156, 3}, - .FBSTP = { 2159, 1}, - .FXCH = { 2160, 2}, - .FCMOVB = { 2162, 1}, - .FCMOVE = { 2163, 1}, - .FCMOVBE = { 2164, 1}, - .FCMOVU = { 2165, 1}, - .FCMOVNB = { 2166, 1}, - .FCMOVNE = { 2167, 1}, - .FCMOVNBE = { 2168, 1}, - .FCMOVNU = { 2169, 1}, - .FCOM = { 2170, 4}, - .FCOMP = { 2174, 4}, - .FCOMPP = { 2178, 1}, - .FICOM = { 2179, 2}, - .FICOMP = { 2181, 2}, - .FCOMI = { 2183, 1}, - .FCOMIP = { 2184, 1}, - .FUCOMI = { 2185, 1}, - .FUCOMIP = { 2186, 1}, - .FUCOM = { 2187, 2}, - .FUCOMP = { 2189, 2}, - .FUCOMPP = { 2191, 1}, - .FTST = { 2192, 1}, - .FLDZ = { 2193, 1}, - .FLD1 = { 2194, 1}, - .FLDPI = { 2195, 1}, - .FLDL2T = { 2196, 1}, - .FLDL2E = { 2197, 1}, - .FLDLG2 = { 2198, 1}, - .FLDLN2 = { 2199, 1}, - .FSIN = { 2200, 1}, - .FCOS = { 2201, 1}, - .FSINCOS = { 2202, 1}, - .FPTAN = { 2203, 1}, - .FPATAN = { 2204, 1}, - .F2XM1 = { 2205, 1}, - .FYL2X = { 2206, 1}, - .FYL2XP1 = { 2207, 1}, - .FINIT = { 2208, 1}, - .FNINIT = { 2209, 1}, - .FINCSTP = { 2210, 1}, - .FDECSTP = { 2211, 1}, - .FFREE = { 2212, 1}, - .FFREEP = { 2213, 1}, - .FNOP = { 2214, 1}, - .FWAIT = { 2215, 1}, - .FCLEX = { 2216, 1}, - .FNCLEX = { 2217, 1}, - .FSTCW = { 2218, 1}, - .FNSTCW = { 2219, 1}, - .FLDCW = { 2220, 1}, - .FSTENV = { 2221, 1}, - .FNSTENV = { 2222, 1}, - .FLDENV = { 2223, 1}, - .FSAVE = { 2224, 1}, - .FNSAVE = { 2225, 1}, - .FRSTOR = { 2226, 1}, - .FSTSW = { 2227, 2}, - .FNSTSW = { 2229, 2}, - .FXSAVE = { 2231, 1}, - .FXSAVE64 = { 2232, 1}, - .FXRSTOR = { 2233, 1}, - .FXRSTOR64 = { 2234, 1}, - .LGDT = { 2235, 2}, - .SGDT = { 2237, 2}, - .LIDT = { 2239, 2}, - .SIDT = { 2241, 2}, - .LLDT = { 2243, 1}, - .SLDT = { 2244, 3}, - .LTR = { 2247, 1}, - .STR = { 2248, 3}, - .LMSW = { 2251, 1}, - .SMSW = { 2252, 3}, - .CLTS = { 2255, 1}, - .ARPL = { 2256, 1}, - .LAR = { 2257, 3}, - .LSL = { 2260, 3}, - .VERR = { 2263, 1}, - .VERW = { 2264, 1}, - .INVD = { 2265, 1}, - .WBINVD = { 2266, 1}, - .INVLPG = { 2267, 1}, - .INVPCID = { 2268, 2}, - .RSM = { 2270, 1}, - .RDMSR = { 2271, 1}, - .WRMSR = { 2272, 1}, - .VMCALL = { 2273, 1}, - .VMLAUNCH = { 2274, 1}, - .VMRESUME = { 2275, 1}, - .VMXOFF = { 2276, 1}, - .VMXON = { 2277, 1}, - .VMCLEAR = { 2278, 1}, - .VMPTRLD = { 2279, 1}, - .VMPTRST = { 2280, 1}, - .VMREAD = { 2281, 1}, - .VMWRITE = { 2282, 1}, - .VMFUNC = { 2283, 1}, - .INVEPT = { 2284, 1}, - .INVVPID = { 2285, 1}, - .ENCLS = { 2286, 1}, - .ENCLU = { 2287, 1}, - .ENCLV = { 2288, 1}, - .RDPKRU = { 2289, 1}, - .WRPKRU = { 2290, 1}, - .INCSSPD = { 2291, 1}, - .INCSSPQ = { 2292, 1}, - .RDSSPD = { 2293, 1}, - .RDSSPQ = { 2294, 1}, - .SAVEPREVSSP = { 2295, 1}, - .RSTORSSP = { 2296, 1}, - .WRSSD = { 2297, 1}, - .WRSSQ = { 2298, 1}, - .WRUSSD = { 2299, 1}, - .WRUSSQ = { 2300, 1}, - .SETSSBSY = { 2301, 1}, - .CLRSSBSY = { 2302, 1}, - .ENDBR64 = { 2303, 1}, - .ENDBR32 = { 2304, 1}, - .XSAVE = { 2305, 1}, - .XSAVE64 = { 2306, 1}, - .XRSTOR = { 2307, 1}, - .XRSTOR64 = { 2308, 1}, - .XSAVEOPT = { 2309, 1}, - .XSAVEOPT64 = { 2310, 1}, - .XSAVEC = { 2311, 1}, - .XSAVEC64 = { 2312, 1}, - .XSAVES = { 2313, 1}, - .XSAVES64 = { 2314, 1}, - .XRSTORS = { 2315, 1}, - .XRSTORS64 = { 2316, 1}, - .PREFETCHT0 = { 2317, 1}, - .PREFETCHT1 = { 2318, 1}, - .PREFETCHT2 = { 2319, 1}, - .PREFETCHNTA = { 2320, 1}, - .PREFETCHW = { 2321, 1}, - .CLFLUSHOPT = { 2322, 1}, - .CLWB = { 2323, 1}, - .CLDEMOTE = { 2324, 1}, - .BSWAP = { 2325, 2}, - .CMPXCHG = { 2327, 4}, - .CMPXCHG8B = { 2331, 1}, - .CMPXCHG16B = { 2332, 1}, - .XADD = { 2333, 4}, - .BOUND = { 2337, 2}, - .ENTER = { 2339, 1}, - .LEAVE = { 2340, 1}, - .XLAT = { 2341, 1}, - .XLATB = { 2342, 1}, - .MOVBE = { 2343, 6}, - .RDRAND = { 2349, 3}, - .RDSEED = { 2352, 3}, + .VADDSUBPS = { 1183, 2}, + .VADDSUBPD = { 1185, 2}, + .VHADDPS = { 1187, 2}, + .VHADDPD = { 1189, 2}, + .VHSUBPS = { 1191, 2}, + .VHSUBPD = { 1193, 2}, + .VLDDQU = { 1195, 2}, + .VMOVDDUP = { 1197, 2}, + .VMOVSLDUP = { 1199, 2}, + .VMOVSHDUP = { 1201, 2}, + .VPCMPESTRI = { 1203, 1}, + .VPCMPESTRM = { 1204, 1}, + .VPCMPISTRI = { 1205, 1}, + .VPCMPISTRM = { 1206, 1}, + .VPBROADCASTB = { 1207, 4}, + .VPBROADCASTW = { 1211, 4}, + .VPBROADCASTD = { 1215, 4}, + .VPBROADCASTQ = { 1219, 4}, + .VCVTPS2PD = { 1223, 2}, + .VCVTPD2PS = { 1225, 2}, + .VCVTSS2SD = { 1227, 1}, + .VCVTSD2SS = { 1228, 1}, + .VCVTPS2DQ = { 1229, 2}, + .VCVTPD2DQ = { 1231, 2}, + .VCVTDQ2PS = { 1233, 2}, + .VCVTDQ2PD = { 1235, 2}, + .VCVTSS2SI = { 1237, 2}, + .VCVTSD2SI = { 1239, 2}, + .VCVTSI2SS = { 1241, 2}, + .VCVTSI2SD = { 1243, 2}, + .VCVTTPS2DQ = { 1245, 2}, + .VCVTTPD2DQ = { 1247, 2}, + .VCVTTSS2SI = { 1249, 2}, + .VCVTTSD2SI = { 1251, 2}, + .VPADDB = { 1253, 2}, + .VPADDW = { 1255, 2}, + .VPADDD = { 1257, 2}, + .VPADDQ = { 1259, 2}, + .VPSUBB = { 1261, 2}, + .VPSUBW = { 1263, 2}, + .VPSUBD = { 1265, 2}, + .VPSUBQ = { 1267, 2}, + .VPMULLW = { 1269, 2}, + .VPMULHW = { 1271, 2}, + .VPMULHUW = { 1273, 2}, + .VPMULUDQ = { 1275, 2}, + .VPMADDWD = { 1277, 2}, + .VPAND = { 1279, 2}, + .VPANDN = { 1281, 2}, + .VPOR = { 1283, 2}, + .VPXOR = { 1285, 2}, + .VPSLLW = { 1287, 4}, + .VPSLLD = { 1291, 4}, + .VPSLLQ = { 1295, 4}, + .VPSRLW = { 1299, 4}, + .VPSRLD = { 1303, 4}, + .VPSRLQ = { 1307, 4}, + .VPSRAW = { 1311, 4}, + .VPSRAD = { 1315, 4}, + .VPCMPEQB = { 1319, 2}, + .VPCMPEQW = { 1321, 2}, + .VPCMPEQD = { 1323, 2}, + .VPCMPEQQ = { 1325, 2}, + .VPCMPGTB = { 1327, 2}, + .VPCMPGTW = { 1329, 2}, + .VPCMPGTD = { 1331, 2}, + .VPCMPGTQ = { 1333, 2}, + .VPACKSSWB = { 1335, 2}, + .VPACKSSDW = { 1337, 2}, + .VPACKUSWB = { 1339, 2}, + .VPACKUSDW = { 1341, 2}, + .VPUNPCKLBW = { 1343, 2}, + .VPUNPCKLWD = { 1345, 2}, + .VPUNPCKLDQ = { 1347, 2}, + .VPUNPCKLQDQ = { 1349, 2}, + .VPUNPCKHBW = { 1351, 2}, + .VPUNPCKHWD = { 1353, 2}, + .VPUNPCKHDQ = { 1355, 2}, + .VPUNPCKHQDQ = { 1357, 2}, + .VPSHUFD = { 1359, 2}, + .VPSHUFHW = { 1361, 2}, + .VPSHUFLW = { 1363, 2}, + .VPEXTRB = { 1365, 1}, + .VPEXTRW = { 1366, 2}, + .VPEXTRD = { 1368, 1}, + .VPEXTRQ = { 1369, 1}, + .VPINSRB = { 1370, 1}, + .VPINSRW = { 1371, 1}, + .VPINSRD = { 1372, 1}, + .VPINSRQ = { 1373, 1}, + .VPMOVMSKB = { 1374, 2}, + .VPTEST = { 1376, 2}, + .VPSHUFB = { 1378, 2}, + .VPHADDW = { 1380, 2}, + .VPHADDD = { 1382, 2}, + .VPHADDSW = { 1384, 2}, + .VPHSUBW = { 1386, 2}, + .VPHSUBD = { 1388, 2}, + .VPHSUBSW = { 1390, 2}, + .VPMADDUBSW = { 1392, 2}, + .VPMULHRSW = { 1394, 2}, + .VPSIGNB = { 1396, 2}, + .VPSIGNW = { 1398, 2}, + .VPSIGND = { 1400, 2}, + .VPABSB = { 1402, 2}, + .VPABSW = { 1404, 2}, + .VPABSD = { 1406, 2}, + .VPALIGNR = { 1408, 2}, + .VPBLENDW = { 1410, 2}, + .VPBLENDVB = { 1412, 2}, + .VMPSADBW = { 1414, 2}, + .VPHMINPOSUW = { 1416, 1}, + .VPMAXSB = { 1417, 2}, + .VPMAXSD = { 1419, 2}, + .VPMAXUW = { 1421, 2}, + .VPMAXUD = { 1423, 2}, + .VPMINSB = { 1425, 2}, + .VPMINSD = { 1427, 2}, + .VPMINUW = { 1429, 2}, + .VPMINUD = { 1431, 2}, + .VPMOVSXBW = { 1433, 2}, + .VPMOVSXBD = { 1435, 2}, + .VPMOVSXBQ = { 1437, 2}, + .VPMOVSXWD = { 1439, 2}, + .VPMOVSXWQ = { 1441, 2}, + .VPMOVSXDQ = { 1443, 2}, + .VPMOVZXBW = { 1445, 2}, + .VPMOVZXBD = { 1447, 2}, + .VPMOVZXBQ = { 1449, 2}, + .VPMOVZXWD = { 1451, 2}, + .VPMOVZXWQ = { 1453, 2}, + .VPMOVZXDQ = { 1455, 2}, + .VPMULDQ = { 1457, 2}, + .VPMULLD = { 1459, 2}, + .VMASKMOVDQU = { 1461, 1}, + .VPCLMULQDQ = { 1462, 2}, + .VAESDEC = { 1464, 1}, + .VAESDECLAST = { 1465, 1}, + .VAESENC = { 1466, 1}, + .VAESENCLAST = { 1467, 1}, + .VAESIMC = { 1468, 1}, + .VAESKEYGENASSIST = { 1469, 1}, + .VBROADCASTSS = { 1470, 4}, + .VBROADCASTSD = { 1474, 2}, + .VBROADCASTF128 = { 1476, 1}, + .VEXTRACTF128 = { 1477, 1}, + .VINSERTF128 = { 1478, 1}, + .VPERM2F128 = { 1479, 1}, + .VMASKMOVPS = { 1480, 4}, + .VMASKMOVPD = { 1484, 4}, + .VTESTPS = { 1488, 2}, + .VTESTPD = { 1490, 2}, + .VZEROALL = { 1492, 1}, + .VZEROUPPER = { 1493, 1}, + .VBROADCASTI128 = { 1494, 1}, + .VEXTRACTI128 = { 1495, 1}, + .VINSERTI128 = { 1496, 1}, + .VPERM2I128 = { 1497, 1}, + .VPERMD = { 1498, 1}, + .VPERMPS = { 1499, 1}, + .VPERMQ = { 1500, 1}, + .VPERMPD = { 1501, 1}, + .VPBLENDD = { 1502, 2}, + .VPSLLVD = { 1504, 2}, + .VPSLLVQ = { 1506, 2}, + .VPSRLVD = { 1508, 2}, + .VPSRLVQ = { 1510, 2}, + .VPSRAVD = { 1512, 2}, + .VPMASKMOVD = { 1514, 4}, + .VPMASKMOVQ = { 1518, 4}, + .VGATHERDPS = { 1522, 2}, + .VGATHERDPD = { 1524, 2}, + .VGATHERQPS = { 1526, 2}, + .VGATHERQPD = { 1528, 2}, + .VPGATHERDD = { 1530, 2}, + .VPGATHERDQ = { 1532, 2}, + .VPGATHERQD = { 1534, 2}, + .VPGATHERQQ = { 1536, 2}, + .VFMADD132PS = { 1538, 2}, + .VFMADD213PS = { 1540, 2}, + .VFMADD231PS = { 1542, 2}, + .VFMADD132PD = { 1544, 2}, + .VFMADD213PD = { 1546, 2}, + .VFMADD231PD = { 1548, 2}, + .VFMADD132SS = { 1550, 1}, + .VFMADD213SS = { 1551, 1}, + .VFMADD231SS = { 1552, 1}, + .VFMADD132SD = { 1553, 1}, + .VFMADD213SD = { 1554, 1}, + .VFMADD231SD = { 1555, 1}, + .VFMSUB132PS = { 1556, 2}, + .VFMSUB213PS = { 1558, 2}, + .VFMSUB231PS = { 1560, 2}, + .VFMSUB132PD = { 1562, 2}, + .VFMSUB213PD = { 1564, 2}, + .VFMSUB231PD = { 1566, 2}, + .VFMSUB132SS = { 1568, 1}, + .VFMSUB213SS = { 1569, 1}, + .VFMSUB231SS = { 1570, 1}, + .VFMSUB132SD = { 1571, 1}, + .VFMSUB213SD = { 1572, 1}, + .VFMSUB231SD = { 1573, 1}, + .VFNMADD132PS = { 1574, 2}, + .VFNMADD213PS = { 1576, 2}, + .VFNMADD231PS = { 1578, 2}, + .VFNMADD132PD = { 1580, 2}, + .VFNMADD213PD = { 1582, 2}, + .VFNMADD231PD = { 1584, 2}, + .VFNMADD132SS = { 1586, 1}, + .VFNMADD213SS = { 1587, 1}, + .VFNMADD231SS = { 1588, 1}, + .VFNMADD132SD = { 1589, 1}, + .VFNMADD213SD = { 1590, 1}, + .VFNMADD231SD = { 1591, 1}, + .VFNMSUB132PS = { 1592, 2}, + .VFNMSUB213PS = { 1594, 2}, + .VFNMSUB231PS = { 1596, 2}, + .VFNMSUB132PD = { 1598, 2}, + .VFNMSUB213PD = { 1600, 2}, + .VFNMSUB231PD = { 1602, 2}, + .VFNMSUB132SS = { 1604, 1}, + .VFNMSUB213SS = { 1605, 1}, + .VFNMSUB231SS = { 1606, 1}, + .VFNMSUB132SD = { 1607, 1}, + .VFNMSUB213SD = { 1608, 1}, + .VFNMSUB231SD = { 1609, 1}, + .VFMADDSUB132PS = { 1610, 2}, + .VFMADDSUB213PS = { 1612, 2}, + .VFMADDSUB231PS = { 1614, 2}, + .VFMADDSUB132PD = { 1616, 2}, + .VFMADDSUB213PD = { 1618, 2}, + .VFMADDSUB231PD = { 1620, 2}, + .VFMSUBADD132PS = { 1622, 2}, + .VFMSUBADD213PS = { 1624, 2}, + .VFMSUBADD231PS = { 1626, 2}, + .VFMSUBADD132PD = { 1628, 2}, + .VFMSUBADD213PD = { 1630, 2}, + .VFMSUBADD231PD = { 1632, 2}, + .VCVTPH2PS = { 1634, 3}, + .VCVTPS2PH = { 1637, 3}, + .VMOVDQA32 = { 1640, 6}, + .VMOVDQA64 = { 1646, 6}, + .VMOVDQU8 = { 1652, 6}, + .VMOVDQU16 = { 1658, 6}, + .VMOVDQU32 = { 1664, 6}, + .VMOVDQU64 = { 1670, 6}, + .VPBLENDMB = { 1676, 3}, + .VPBLENDMW = { 1679, 3}, + .VPBLENDMD = { 1682, 3}, + .VPBLENDMQ = { 1685, 3}, + .VBLENDMPS = { 1688, 3}, + .VBLENDMPD = { 1691, 3}, + .VPCMPB = { 1694, 3}, + .VPCMPUB = { 1697, 3}, + .VPCMPW = { 1700, 3}, + .VPCMPUW = { 1703, 3}, + .VPCMPD = { 1706, 3}, + .VPCMPUD = { 1709, 3}, + .VPCMPQ = { 1712, 3}, + .VPCMPUQ = { 1715, 3}, + .VPTESTMB = { 1718, 3}, + .VPTESTMW = { 1721, 3}, + .VPTESTMD = { 1724, 3}, + .VPTESTMQ = { 1727, 3}, + .VPTESTNMB = { 1730, 3}, + .VPTESTNMW = { 1733, 3}, + .VPTESTNMD = { 1736, 3}, + .VPTESTNMQ = { 1739, 3}, + .VPCOMPRESSD = { 1742, 3}, + .VPCOMPRESSQ = { 1745, 3}, + .VCOMPRESSPS = { 1748, 3}, + .VCOMPRESSPD = { 1751, 3}, + .VPEXPANDD = { 1754, 3}, + .VPEXPANDQ = { 1757, 3}, + .VEXPANDPS = { 1760, 3}, + .VEXPANDPD = { 1763, 3}, + .VPCONFLICTD = { 1766, 3}, + .VPCONFLICTQ = { 1769, 3}, + .VPLZCNTD = { 1772, 3}, + .VPLZCNTQ = { 1775, 3}, + .VPERMI2B = { 1778, 3}, + .VPERMI2W = { 1781, 3}, + .VPERMI2D = { 1784, 3}, + .VPERMI2Q = { 1787, 3}, + .VPERMI2PS = { 1790, 3}, + .VPERMI2PD = { 1793, 3}, + .VPERMT2B = { 1796, 3}, + .VPERMT2W = { 1799, 3}, + .VPERMT2D = { 1802, 3}, + .VPERMT2Q = { 1805, 3}, + .VPERMT2PS = { 1808, 3}, + .VPERMT2PD = { 1811, 3}, + .VPERMB = { 1814, 3}, + .VPERMW = { 1817, 3}, + .VPMOVB2M = { 1820, 3}, + .VPMOVW2M = { 1823, 3}, + .VPMOVD2M = { 1826, 3}, + .VPMOVQ2M = { 1829, 3}, + .VPMOVM2B = { 1832, 3}, + .VPMOVM2W = { 1835, 3}, + .VPMOVM2D = { 1838, 3}, + .VPMOVM2Q = { 1841, 3}, + .VPMOVQB = { 1844, 3}, + .VPMOVSQB = { 1847, 3}, + .VPMOVUSQB = { 1850, 3}, + .VPMOVQW = { 1853, 3}, + .VPMOVSQW = { 1856, 3}, + .VPMOVUSQW = { 1859, 3}, + .VPMOVQD = { 1862, 3}, + .VPMOVSQD = { 1865, 3}, + .VPMOVUSQD = { 1868, 3}, + .VPMOVDB = { 1871, 3}, + .VPMOVSDB = { 1874, 3}, + .VPMOVUSDB = { 1877, 3}, + .VPMOVDW = { 1880, 3}, + .VPMOVSDW = { 1883, 3}, + .VPMOVUSDW = { 1886, 3}, + .VPMOVWB = { 1889, 3}, + .VPMOVSWB = { 1892, 3}, + .VPMOVUSWB = { 1895, 3}, + .VPROLD = { 1898, 3}, + .VPROLQ = { 1901, 3}, + .VPROLVD = { 1904, 3}, + .VPROLVQ = { 1907, 3}, + .VPRORD = { 1910, 3}, + .VPRORQ = { 1913, 3}, + .VPRORVD = { 1916, 3}, + .VPRORVQ = { 1919, 3}, + .VPSCATTERDD = { 1922, 3}, + .VPSCATTERDQ = { 1925, 3}, + .VPSCATTERQD = { 1928, 3}, + .VPSCATTERQQ = { 1931, 3}, + .VSCATTERDPS = { 1934, 3}, + .VSCATTERDPD = { 1937, 3}, + .VSCATTERQPS = { 1940, 3}, + .VSCATTERQPD = { 1943, 3}, + .VPSRAVQ = { 1946, 3}, + .VPSRAVW = { 1949, 3}, + .VPSLLVW = { 1952, 3}, + .VPSRLVW = { 1955, 3}, + .VRANGEPS = { 1958, 3}, + .VRANGEPD = { 1961, 3}, + .VRANGESS = { 1964, 1}, + .VRANGESD = { 1965, 1}, + .VREDUCEPS = { 1966, 3}, + .VREDUCEPD = { 1969, 3}, + .VREDUCESS = { 1972, 1}, + .VREDUCESD = { 1973, 1}, + .VRNDSCALEPS = { 1974, 3}, + .VRNDSCALEPD = { 1977, 3}, + .VRNDSCALESS = { 1980, 1}, + .VRNDSCALESD = { 1981, 1}, + .VRSQRT14PS = { 1982, 3}, + .VRSQRT14PD = { 1985, 3}, + .VRSQRT14SS = { 1988, 1}, + .VRSQRT14SD = { 1989, 1}, + .VRCP14PS = { 1990, 3}, + .VRCP14PD = { 1993, 3}, + .VRCP14SS = { 1996, 1}, + .VRCP14SD = { 1997, 1}, + .VSCALEFPS = { 1998, 3}, + .VSCALEFPD = { 2001, 3}, + .VSCALEFSS = { 2004, 1}, + .VSCALEFSD = { 2005, 1}, + .VGETEXPPS = { 2006, 3}, + .VGETEXPPD = { 2009, 3}, + .VGETEXPSS = { 2012, 1}, + .VGETEXPSD = { 2013, 1}, + .VGETMANTPS = { 2014, 3}, + .VGETMANTPD = { 2017, 3}, + .VGETMANTSS = { 2020, 1}, + .VGETMANTSD = { 2021, 1}, + .VFIXUPIMMPS = { 2022, 3}, + .VFIXUPIMMPD = { 2025, 3}, + .VFIXUPIMMSS = { 2028, 1}, + .VFIXUPIMMSD = { 2029, 1}, + .VFPCLASSPS = { 2030, 3}, + .VFPCLASSPD = { 2033, 3}, + .VFPCLASSSS = { 2036, 1}, + .VFPCLASSSD = { 2037, 1}, + .VALIGNQ = { 2038, 3}, + .VALIGND = { 2041, 3}, + .VDBPSADBW = { 2044, 3}, + .VPTERNLOGD = { 2047, 3}, + .VPTERNLOGQ = { 2050, 3}, + .VPMULTISHIFTQB = { 2053, 3}, + .KADDW = { 2056, 1}, + .KADDB = { 2057, 1}, + .KADDQ = { 2058, 1}, + .KADDD = { 2059, 1}, + .KANDW = { 2060, 1}, + .KANDB = { 2061, 1}, + .KANDQ = { 2062, 1}, + .KANDD = { 2063, 1}, + .KANDNW = { 2064, 1}, + .KANDNB = { 2065, 1}, + .KANDNQ = { 2066, 1}, + .KANDND = { 2067, 1}, + .KMOVW = { 2068, 4}, + .KMOVB = { 2072, 4}, + .KMOVQ = { 2076, 4}, + .KMOVD = { 2080, 4}, + .KNOTW = { 2084, 1}, + .KNOTB = { 2085, 1}, + .KNOTQ = { 2086, 1}, + .KNOTD = { 2087, 1}, + .KORW = { 2088, 1}, + .KORB = { 2089, 1}, + .KORQ = { 2090, 1}, + .KORD = { 2091, 1}, + .KORTESTW = { 2092, 1}, + .KORTESTB = { 2093, 1}, + .KORTESTQ = { 2094, 1}, + .KORTESTD = { 2095, 1}, + .KSHIFTLW = { 2096, 1}, + .KSHIFTLB = { 2097, 1}, + .KSHIFTLQ = { 2098, 1}, + .KSHIFTLD = { 2099, 1}, + .KSHIFTRW = { 2100, 1}, + .KSHIFTRB = { 2101, 1}, + .KSHIFTRQ = { 2102, 1}, + .KSHIFTRD = { 2103, 1}, + .KTESTW = { 2104, 1}, + .KTESTB = { 2105, 1}, + .KTESTQ = { 2106, 1}, + .KTESTD = { 2107, 1}, + .KUNPCKBW = { 2108, 1}, + .KUNPCKWD = { 2109, 1}, + .KUNPCKDQ = { 2110, 1}, + .KXNORW = { 2111, 1}, + .KXNORB = { 2112, 1}, + .KXNORQ = { 2113, 1}, + .KXNORD = { 2114, 1}, + .KXORW = { 2115, 1}, + .KXORB = { 2116, 1}, + .KXORQ = { 2117, 1}, + .KXORD = { 2118, 1}, + .FADD = { 2119, 4}, + .FADDP = { 2123, 2}, + .FIADD = { 2125, 2}, + .FSUB = { 2127, 4}, + .FSUBP = { 2131, 2}, + .FISUB = { 2133, 2}, + .FSUBR = { 2135, 4}, + .FSUBRP = { 2139, 2}, + .FISUBR = { 2141, 2}, + .FMUL = { 2143, 4}, + .FMULP = { 2147, 2}, + .FIMUL = { 2149, 2}, + .FDIV = { 2151, 4}, + .FDIVP = { 2155, 2}, + .FIDIV = { 2157, 2}, + .FDIVR = { 2159, 4}, + .FDIVRP = { 2163, 2}, + .FIDIVR = { 2165, 2}, + .FSQRT = { 2167, 1}, + .FABS = { 2168, 1}, + .FCHS = { 2169, 1}, + .FPREM = { 2170, 1}, + .FPREM1 = { 2171, 1}, + .FRNDINT = { 2172, 1}, + .FSCALE = { 2173, 1}, + .FXTRACT = { 2174, 1}, + .FXAM = { 2175, 1}, + .FLD = { 2176, 4}, + .FILD = { 2180, 3}, + .FBLD = { 2183, 1}, + .FST = { 2184, 3}, + .FSTP = { 2187, 4}, + .FIST = { 2191, 2}, + .FISTP = { 2193, 3}, + .FISTTP = { 2196, 3}, + .FBSTP = { 2199, 1}, + .FXCH = { 2200, 2}, + .FCMOVB = { 2202, 1}, + .FCMOVE = { 2203, 1}, + .FCMOVBE = { 2204, 1}, + .FCMOVU = { 2205, 1}, + .FCMOVNB = { 2206, 1}, + .FCMOVNE = { 2207, 1}, + .FCMOVNBE = { 2208, 1}, + .FCMOVNU = { 2209, 1}, + .FCOM = { 2210, 4}, + .FCOMP = { 2214, 4}, + .FCOMPP = { 2218, 1}, + .FICOM = { 2219, 2}, + .FICOMP = { 2221, 2}, + .FCOMI = { 2223, 1}, + .FCOMIP = { 2224, 1}, + .FUCOMI = { 2225, 1}, + .FUCOMIP = { 2226, 1}, + .FUCOM = { 2227, 2}, + .FUCOMP = { 2229, 2}, + .FUCOMPP = { 2231, 1}, + .FTST = { 2232, 1}, + .FLDZ = { 2233, 1}, + .FLD1 = { 2234, 1}, + .FLDPI = { 2235, 1}, + .FLDL2T = { 2236, 1}, + .FLDL2E = { 2237, 1}, + .FLDLG2 = { 2238, 1}, + .FLDLN2 = { 2239, 1}, + .FSIN = { 2240, 1}, + .FCOS = { 2241, 1}, + .FSINCOS = { 2242, 1}, + .FPTAN = { 2243, 1}, + .FPATAN = { 2244, 1}, + .F2XM1 = { 2245, 1}, + .FYL2X = { 2246, 1}, + .FYL2XP1 = { 2247, 1}, + .FINIT = { 2248, 1}, + .FNINIT = { 2249, 1}, + .FINCSTP = { 2250, 1}, + .FDECSTP = { 2251, 1}, + .FFREE = { 2252, 1}, + .FFREEP = { 2253, 1}, + .FNOP = { 2254, 1}, + .FWAIT = { 2255, 1}, + .FCLEX = { 2256, 1}, + .FNCLEX = { 2257, 1}, + .FSTCW = { 2258, 1}, + .FNSTCW = { 2259, 1}, + .FLDCW = { 2260, 1}, + .FSTENV = { 2261, 1}, + .FNSTENV = { 2262, 1}, + .FLDENV = { 2263, 1}, + .FSAVE = { 2264, 1}, + .FNSAVE = { 2265, 1}, + .FRSTOR = { 2266, 1}, + .FSTSW = { 2267, 2}, + .FNSTSW = { 2269, 2}, + .FXSAVE = { 2271, 1}, + .FXSAVE64 = { 2272, 1}, + .FXRSTOR = { 2273, 1}, + .FXRSTOR64 = { 2274, 1}, + .LGDT = { 2275, 2}, + .SGDT = { 2277, 2}, + .LIDT = { 2279, 2}, + .SIDT = { 2281, 2}, + .LLDT = { 2283, 1}, + .SLDT = { 2284, 3}, + .LTR = { 2287, 1}, + .STR = { 2288, 3}, + .LMSW = { 2291, 1}, + .SMSW = { 2292, 3}, + .CLTS = { 2295, 1}, + .ARPL = { 2296, 1}, + .LAR = { 2297, 3}, + .LSL = { 2300, 3}, + .VERR = { 2303, 1}, + .VERW = { 2304, 1}, + .INVD = { 2305, 1}, + .WBINVD = { 2306, 1}, + .INVLPG = { 2307, 1}, + .INVPCID = { 2308, 2}, + .RSM = { 2310, 1}, + .RDMSR = { 2311, 1}, + .WRMSR = { 2312, 1}, + .VMCALL = { 2313, 1}, + .VMLAUNCH = { 2314, 1}, + .VMRESUME = { 2315, 1}, + .VMXOFF = { 2316, 1}, + .VMXON = { 2317, 1}, + .VMCLEAR = { 2318, 1}, + .VMPTRLD = { 2319, 1}, + .VMPTRST = { 2320, 1}, + .VMREAD = { 2321, 1}, + .VMWRITE = { 2322, 1}, + .VMFUNC = { 2323, 1}, + .INVEPT = { 2324, 1}, + .INVVPID = { 2325, 1}, + .ENCLS = { 2326, 1}, + .ENCLU = { 2327, 1}, + .ENCLV = { 2328, 1}, + .RDPKRU = { 2329, 1}, + .WRPKRU = { 2330, 1}, + .INCSSPD = { 2331, 1}, + .INCSSPQ = { 2332, 1}, + .RDSSPD = { 2333, 1}, + .RDSSPQ = { 2334, 1}, + .SAVEPREVSSP = { 2335, 1}, + .RSTORSSP = { 2336, 1}, + .WRSSD = { 2337, 1}, + .WRSSQ = { 2338, 1}, + .WRUSSD = { 2339, 1}, + .WRUSSQ = { 2340, 1}, + .SETSSBSY = { 2341, 1}, + .CLRSSBSY = { 2342, 1}, + .ENDBR64 = { 2343, 1}, + .ENDBR32 = { 2344, 1}, + .XSAVE = { 2345, 1}, + .XSAVE64 = { 2346, 1}, + .XRSTOR = { 2347, 1}, + .XRSTOR64 = { 2348, 1}, + .XSAVEOPT = { 2349, 1}, + .XSAVEOPT64 = { 2350, 1}, + .XSAVEC = { 2351, 1}, + .XSAVEC64 = { 2352, 1}, + .XSAVES = { 2353, 1}, + .XSAVES64 = { 2354, 1}, + .XRSTORS = { 2355, 1}, + .XRSTORS64 = { 2356, 1}, + .PREFETCHT0 = { 2357, 1}, + .PREFETCHT1 = { 2358, 1}, + .PREFETCHT2 = { 2359, 1}, + .PREFETCHNTA = { 2360, 1}, + .PREFETCHW = { 2361, 1}, + .CLFLUSHOPT = { 2362, 1}, + .CLWB = { 2363, 1}, + .CLDEMOTE = { 2364, 1}, + .BSWAP = { 2365, 2}, + .CMPXCHG = { 2367, 4}, + .CMPXCHG8B = { 2371, 1}, + .CMPXCHG16B = { 2372, 1}, + .XADD = { 2373, 4}, + .BOUND = { 2377, 2}, + .ENTER = { 2379, 1}, + .LEAVE = { 2380, 1}, + .XLAT = { 2381, 1}, + .XLATB = { 2382, 1}, + .MOVBE = { 2383, 6}, + .RDRAND = { 2389, 3}, + .RDSEED = { 2392, 3}, } // Emit descriptor per form (derived from ENCODE_FORMS via lib.form_to_recipe). -ENCODE_RECIPES: [2355]lib.Form_Recipe +ENCODE_RECIPES: [2395]lib.Form_Recipe @(init) _fill_recipes :: proc "contextless" () { for i in 0 ..< len(ENCODE_FORMS) { ENCODE_RECIPES[i] = lib.form_to_recipe(&ENCODE_FORMS[i]) diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index 3ec40035e3546002fa6d3c040a0620303dff1066..71049b89b699a440b4f72e7c2bcf1d5e9d0d1331 100644 GIT binary patch literal 38320 zcmZQ%U}a=rU}R!o=wM)A;9y{6U}J*tJE44bW>h{03!KjZQqRcBz`(@Fz|aL%&%_4d zcSHHi?5KPe4mcm8UxS*+m!_7}*hg4g{YAq+ZgLfq|2Qfnfmy1A__! zBZHI~guf8Vmo`V`%UHnq93b_kk_-$SoD2+$pz6(}ApFHpzPU6i-$Dk?2kU23fP`lc z)V~}EKG=T>(D3Yo$}2#_uMg^f7Db4D1qMcN{3)_P!dD5(XHkO4D?<57PHO$>1i9-easBZXnasw z0j0NX42&Ec49pD7(D2y~RS!x#Ao=ZJc^0^N`@r%naPwe%n0fo4>S5;XhpLB}w;wFe z3Qmh4^OM2h&&D9d#K6GG!oV;A9N%mV(#)uQ85TI7Lxq72p5NLS7#uhl*x>oC9m7y`gFJD3gSv#>C*Gq5o*FfcMOF#Km@U|?lnXW&5a zSwMU-29P)dLl#uOFarZvPX?4P!oa}5&cMI`<12vk5h#B!GJwp7@mDZ__#ANeM1b{k zz}*wUz`(-70P-QkJ^f&NIpFT;2WNW@2AFvZq2|H(E5UqD1}08OdhP|Me@+HwG(HQ0 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zbQu{L^cWc#^cfi^GTO2lFfuV1O+LtJ&T7KQ$Y2UK)_{2nvpLw(UPcSB$Opy%b}L3E z1{<(wBCjpfDfWy^431zG6BsR+ok2!Q%DXT!GPp7_GPprqK;=Lh)-f_M zY+z(!*u==hu!WI{VH+b8!wyC!hFy$I40{-v81^wTF&toIVmQRe#BhX>iQyO{6T=Bc zCWcdtj0~q4nHbJ8GBKQIWMa6;$i#4&k%{3dBNM}QMka=vj7$u-8JQUFGBPpThq?`9 z9|%8SWMO#1$i(oBkp;x12)|-vVR*;L!te>r4vGvVLGx!u7KZOs@CVGw-%zvuLuqCv z76x`E76xu676yJMM0g1^u`q};u`oz8u`tLpF)=7Iu`sAIF)^q!u`p;eF)`>eu`n1i zLDDJAY-HM)iG{(OiG{(MiG{(QiHX6HiG{(HiHX6TiG{(NiHX6NiG?8$kN#jL7KU&p z7KUgh7KV5xCWb^N7KT(NCWdq-7KUslCWc%l7KTDR`jOp2Ep{;zBSQ%jBSR?@BSRSz zBSSe8Bu`Mwd~|av=t{CWaYMIgo}~j7$u3 z7?~L6F)}eMU}R!g#K^?3gprA186y+J3PvV|Rg6pwYZ#dr)-f_MY+z(!*u==hu!WI{ zVH+bO!*)g{hMkN|47(Yb81^zUG3;k#VmQdi#Bi9AiQy>8Y%{I)_X=4 zhR=*F4Br`97=AM{G5lp@VPIrpVqj)sVPI!sV&G(AVc=zgq*IW3bj;7h!XV7V!XVDX z!XVAW#30MW!l1~+#GuT?!l2H?#GuK_2R7 t7!?~0fzc44ZwQ1z^L+%ArmyXzwvC3sXb22s2t+Y4F~l%2F~kv({{iZBH~jzr diff --git a/core/rexcode/isa/x86/tables/x86.vex_idx_0f3a.bin b/core/rexcode/isa/x86/tables/x86.vex_idx_0f3a.bin index f270c4c2bf98d29c31767a1367e8c4e24f4bace4..31bcec3caca0aa62fce28c862a7bd938ee8dd3ac 100644 GIT binary patch literal 4096 zcmZP=1*0J_8UiCW1X`FF8Csbb8QPebP{N>ti4n~2WMX3IW@2LKWnyILV`60JXJTTQ z$i&1jnTd&EDw-aUhUrX<3^SM*8D=suG0bLSWSGOm$S@ab7Dyh1=OO7^z{JR~kcp9D z5t0~44Y7C$6BENSCMJdzOiT=`u$ZxiiIHI~n*GRTuVZ3j*uccduo0?vGnC$nre_-y z6T=QBCWc*5d1NyvVeesLWZ28Z$gq!zkzqfYos^h6s(0{*z=6^D9{iCs>cY_w7!85Z S5Eu=C(GVDfA#jkw_9y^AKpRQ` literal 4096 zcmZP=1*0J_8UiCW1QM7S84{To8IqWoP{JUEi4n|CWnyATXJTT=WMX8-W@2K< zWnyB;XJTR~MAHM(P|U>0P{PE>P|C!_P|n22P{G8=Pzf~)BoD$>Ncw7+7#V7r7#Zr2 z#6W6@#SKhM3{6Z-3@uDd3~gA<=wM=G=tQ$0+3YSRCWam+MuuLf-hL=O5lzn|CMJd{ yOiT>Zpz_FOjIu{VfSeGRftJR|F=JHEXb6mkz-S1JhQMeDjE2C-3xSywwnqU^3liu6 diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 1a2f93b81..7db8b9b4d 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -46,45 +46,46 @@ struct Asm_amd64 { M_VMINPD, M_VMINSS, M_VMINSD, M_VANDPS, M_VANDPD, M_VANDNPS, M_VANDNPD, M_VORPS, M_VORPD, M_VXORPS, M_VXORPD, M_VCMPPS, M_VCMPPD, M_VCMPSS, M_VCMPSD, M_VCOMISS, M_VCOMISD, M_VUCOMISS, M_VUCOMISD, M_VSHUFPS, M_VSHUFPD, M_VUNPCKLPS, M_VUNPCKHPS, M_VUNPCKLPD, M_VUNPCKHPD, M_VBLENDPS, M_VBLENDPD, M_VBLENDVPS, M_VBLENDVPD, M_VDPPS, M_VDPPD, M_VROUNDPS, M_VROUNDPD, M_VROUNDSS, M_VROUNDSD, M_VEXTRACTPS, M_VINSERTPS, M_VMOVAPS, M_VMOVUPS, M_VMOVAPD, M_VMOVUPD, M_VMOVSS, M_VMOVSD, M_VMOVDQA, M_VMOVDQU, M_VMOVQ, M_VMOVD, M_VMOVLPS, - M_VMOVHPS, M_VMOVLPD, M_VMOVHPD, M_VMOVLHPS, M_VMOVHLPS, M_VMOVMSKPS, M_VMOVMSKPD, M_VMOVNTPS, M_VMOVNTPD, M_VMOVNTDQ, M_VMOVNTDQA, M_VCVTPS2PD, M_VCVTPD2PS, M_VCVTSS2SD, M_VCVTSD2SS, M_VCVTPS2DQ, - M_VCVTPD2DQ, M_VCVTDQ2PS, M_VCVTDQ2PD, M_VCVTSS2SI, M_VCVTSD2SI, M_VCVTSI2SS, M_VCVTSI2SD, M_VCVTTPS2DQ, M_VCVTTPD2DQ, M_VCVTTSS2SI, M_VCVTTSD2SI, M_VPADDB, M_VPADDW, M_VPADDD, M_VPADDQ, M_VPSUBB, - M_VPSUBW, M_VPSUBD, M_VPSUBQ, M_VPMULLW, M_VPMULHW, M_VPMULHUW, M_VPMULUDQ, M_VPMADDWD, M_VPAND, M_VPANDN, M_VPOR, M_VPXOR, M_VPSLLW, M_VPSLLD, M_VPSLLQ, M_VPSRLW, - M_VPSRLD, M_VPSRLQ, M_VPSRAW, M_VPSRAD, M_VPCMPEQB, M_VPCMPEQW, M_VPCMPEQD, M_VPCMPEQQ, M_VPCMPGTB, M_VPCMPGTW, M_VPCMPGTD, M_VPCMPGTQ, M_VPACKSSWB, M_VPACKSSDW, M_VPACKUSWB, M_VPACKUSDW, - M_VPUNPCKLBW, M_VPUNPCKLWD, M_VPUNPCKLDQ, M_VPUNPCKLQDQ, M_VPUNPCKHBW, M_VPUNPCKHWD, M_VPUNPCKHDQ, M_VPUNPCKHQDQ, M_VPSHUFD, M_VPSHUFHW, M_VPSHUFLW, M_VPEXTRB, M_VPEXTRW, M_VPEXTRD, M_VPEXTRQ, M_VPINSRB, - M_VPINSRW, M_VPINSRD, M_VPINSRQ, M_VPMOVMSKB, M_VPTEST, M_VPSHUFB, M_VPHADDW, M_VPHADDD, M_VPHADDSW, M_VPHSUBW, M_VPHSUBD, M_VPHSUBSW, M_VPMADDUBSW, M_VPMULHRSW, M_VPSIGNB, M_VPSIGNW, - M_VPSIGND, M_VPABSB, M_VPABSW, M_VPABSD, M_VPALIGNR, M_VPBLENDW, M_VPBLENDVB, M_VMPSADBW, M_VPHMINPOSUW, M_VPMAXSB, M_VPMAXSD, M_VPMAXUW, M_VPMAXUD, M_VPMINSB, M_VPMINSD, M_VPMINUW, - M_VPMINUD, M_VPMOVSXBW, M_VPMOVSXBD, M_VPMOVSXBQ, M_VPMOVSXWD, M_VPMOVSXWQ, M_VPMOVSXDQ, M_VPMOVZXBW, M_VPMOVZXBD, M_VPMOVZXBQ, M_VPMOVZXWD, M_VPMOVZXWQ, M_VPMOVZXDQ, M_VPMULDQ, M_VPMULLD, M_VMASKMOVDQU, - M_VPCLMULQDQ, M_VAESDEC, M_VAESDECLAST, M_VAESENC, M_VAESENCLAST, M_VAESIMC, M_VAESKEYGENASSIST, M_VBROADCASTSS, M_VBROADCASTSD, M_VBROADCASTF128, M_VEXTRACTF128, M_VINSERTF128, M_VPERM2F128, M_VMASKMOVPS, M_VMASKMOVPD, M_VTESTPS, - M_VTESTPD, M_VZEROALL, M_VZEROUPPER, M_VBROADCASTI128, M_VEXTRACTI128, M_VINSERTI128, M_VPERM2I128, M_VPERMD, M_VPERMPS, M_VPERMQ, M_VPERMPD, M_VPBLENDD, M_VPSLLVD, M_VPSLLVQ, M_VPSRLVD, M_VPSRLVQ, - M_VPSRAVD, M_VPMASKMOVD, M_VPMASKMOVQ, M_VGATHERDPS, M_VGATHERDPD, M_VGATHERQPS, M_VGATHERQPD, M_VPGATHERDD, M_VPGATHERDQ, M_VPGATHERQD, M_VPGATHERQQ, M_VFMADD132PS, M_VFMADD213PS, M_VFMADD231PS, M_VFMADD132PD, M_VFMADD213PD, - M_VFMADD231PD, M_VFMADD132SS, M_VFMADD213SS, M_VFMADD231SS, M_VFMADD132SD, M_VFMADD213SD, M_VFMADD231SD, M_VFMSUB132PS, M_VFMSUB213PS, M_VFMSUB231PS, M_VFMSUB132PD, M_VFMSUB213PD, M_VFMSUB231PD, M_VFMSUB132SS, M_VFMSUB213SS, M_VFMSUB231SS, - M_VFMSUB132SD, M_VFMSUB213SD, M_VFMSUB231SD, M_VFNMADD132PS, M_VFNMADD213PS, M_VFNMADD231PS, M_VFNMADD132PD, M_VFNMADD213PD, M_VFNMADD231PD, M_VFNMADD132SS, M_VFNMADD213SS, M_VFNMADD231SS, M_VFNMADD132SD, M_VFNMADD213SD, M_VFNMADD231SD, M_VFNMSUB132PS, - M_VFNMSUB213PS, M_VFNMSUB231PS, M_VFNMSUB132PD, M_VFNMSUB213PD, M_VFNMSUB231PD, M_VFNMSUB132SS, M_VFNMSUB213SS, M_VFNMSUB231SS, M_VFNMSUB132SD, M_VFNMSUB213SD, M_VFNMSUB231SD, M_VFMADDSUB132PS, M_VFMADDSUB213PS, M_VFMADDSUB231PS, M_VFMADDSUB132PD, M_VFMADDSUB213PD, - M_VFMADDSUB231PD, M_VFMSUBADD132PS, M_VFMSUBADD213PS, M_VFMSUBADD231PS, M_VFMSUBADD132PD, M_VFMSUBADD213PD, M_VFMSUBADD231PD, M_VCVTPH2PS, M_VCVTPS2PH, M_VMOVDQA32, M_VMOVDQA64, M_VMOVDQU8, M_VMOVDQU16, M_VMOVDQU32, M_VMOVDQU64, M_VPBLENDMB, - M_VPBLENDMW, M_VPBLENDMD, M_VPBLENDMQ, M_VBLENDMPS, M_VBLENDMPD, M_VPCMPB, M_VPCMPUB, M_VPCMPW, M_VPCMPUW, M_VPCMPD, M_VPCMPUD, M_VPCMPQ, M_VPCMPUQ, M_VPTESTMB, M_VPTESTMW, M_VPTESTMD, - M_VPTESTMQ, M_VPTESTNMB, M_VPTESTNMW, M_VPTESTNMD, M_VPTESTNMQ, M_VPCOMPRESSD, M_VPCOMPRESSQ, M_VCOMPRESSPS, M_VCOMPRESSPD, M_VPEXPANDD, M_VPEXPANDQ, M_VEXPANDPS, M_VEXPANDPD, M_VPCONFLICTD, M_VPCONFLICTQ, M_VPLZCNTD, - M_VPLZCNTQ, M_VPERMI2B, M_VPERMI2W, M_VPERMI2D, M_VPERMI2Q, M_VPERMI2PS, M_VPERMI2PD, M_VPERMT2B, M_VPERMT2W, M_VPERMT2D, M_VPERMT2Q, M_VPERMT2PS, M_VPERMT2PD, M_VPERMB, M_VPERMW, M_VPMOVB2M, - M_VPMOVW2M, M_VPMOVD2M, M_VPMOVQ2M, M_VPMOVM2B, M_VPMOVM2W, M_VPMOVM2D, M_VPMOVM2Q, M_VPMOVQB, M_VPMOVSQB, M_VPMOVUSQB, M_VPMOVQW, M_VPMOVSQW, M_VPMOVUSQW, M_VPMOVQD, M_VPMOVSQD, M_VPMOVUSQD, - M_VPMOVDB, M_VPMOVSDB, M_VPMOVUSDB, M_VPMOVDW, M_VPMOVSDW, M_VPMOVUSDW, M_VPMOVWB, M_VPMOVSWB, M_VPMOVUSWB, M_VPROLD, M_VPROLQ, M_VPROLVD, M_VPROLVQ, M_VPRORD, M_VPRORQ, M_VPRORVD, - M_VPRORVQ, M_VPSCATTERDD, M_VPSCATTERDQ, M_VPSCATTERQD, M_VPSCATTERQQ, M_VSCATTERDPS, M_VSCATTERDPD, M_VSCATTERQPS, M_VSCATTERQPD, M_VPSRAVQ, M_VPSRAVW, M_VPSLLVW, M_VPSRLVW, M_VRANGEPS, M_VRANGEPD, M_VRANGESS, - M_VRANGESD, M_VREDUCEPS, M_VREDUCEPD, M_VREDUCESS, M_VREDUCESD, M_VRNDSCALEPS, M_VRNDSCALEPD, M_VRNDSCALESS, M_VRNDSCALESD, M_VRSQRT14PS, M_VRSQRT14PD, M_VRSQRT14SS, M_VRSQRT14SD, M_VRCP14PS, M_VRCP14PD, M_VRCP14SS, - M_VRCP14SD, M_VSCALEFPS, M_VSCALEFPD, M_VSCALEFSS, M_VSCALEFSD, M_VGETEXPPS, M_VGETEXPPD, M_VGETEXPSS, M_VGETEXPSD, M_VGETMANTPS, M_VGETMANTPD, M_VGETMANTSS, M_VGETMANTSD, M_VFIXUPIMMPS, M_VFIXUPIMMPD, M_VFIXUPIMMSS, - M_VFIXUPIMMSD, M_VFPCLASSPS, M_VFPCLASSPD, M_VFPCLASSSS, M_VFPCLASSSD, M_VALIGNQ, M_VALIGND, M_VDBPSADBW, M_VPTERNLOGD, M_VPTERNLOGQ, M_VPMULTISHIFTQB, M_KADDW, M_KADDB, M_KADDQ, M_KADDD, M_KANDW, - M_KANDB, M_KANDQ, M_KANDD, M_KANDNW, M_KANDNB, M_KANDNQ, M_KANDND, M_KMOVW, M_KMOVB, M_KMOVQ, M_KMOVD, M_KNOTW, M_KNOTB, M_KNOTQ, M_KNOTD, M_KORW, - M_KORB, M_KORQ, M_KORD, M_KORTESTW, M_KORTESTB, M_KORTESTQ, M_KORTESTD, M_KSHIFTLW, M_KSHIFTLB, M_KSHIFTLQ, M_KSHIFTLD, M_KSHIFTRW, M_KSHIFTRB, M_KSHIFTRQ, M_KSHIFTRD, M_KTESTW, - M_KTESTB, M_KTESTQ, M_KTESTD, M_KUNPCKBW, M_KUNPCKWD, M_KUNPCKDQ, M_KXNORW, M_KXNORB, M_KXNORQ, M_KXNORD, M_KXORW, M_KXORB, M_KXORQ, M_KXORD, M_FADD, M_FADDP, - M_FIADD, M_FSUB, M_FSUBP, M_FISUB, M_FSUBR, M_FSUBRP, M_FISUBR, M_FMUL, M_FMULP, M_FIMUL, M_FDIV, M_FDIVP, M_FIDIV, M_FDIVR, M_FDIVRP, M_FIDIVR, - M_FSQRT, M_FABS, M_FCHS, M_FPREM, M_FPREM1, M_FRNDINT, M_FSCALE, M_FXTRACT, M_FXAM, M_FLD, M_FILD, M_FBLD, M_FST, M_FSTP, M_FIST, M_FISTP, - M_FISTTP, M_FBSTP, M_FXCH, M_FCMOVB, M_FCMOVE, M_FCMOVBE, M_FCMOVU, M_FCMOVNB, M_FCMOVNE, M_FCMOVNBE, M_FCMOVNU, M_FCOM, M_FCOMP, M_FCOMPP, M_FICOM, M_FICOMP, - M_FCOMI, M_FCOMIP, M_FUCOMI, M_FUCOMIP, M_FUCOM, M_FUCOMP, M_FUCOMPP, M_FTST, M_FLDZ, M_FLD1, M_FLDPI, M_FLDL2T, M_FLDL2E, M_FLDLG2, M_FLDLN2, M_FSIN, - M_FCOS, M_FSINCOS, M_FPTAN, M_FPATAN, M_F2XM1, M_FYL2X, M_FYL2XP1, M_FINIT, M_FNINIT, M_FINCSTP, M_FDECSTP, M_FFREE, M_FFREEP, M_FNOP, M_FWAIT, M_FCLEX, - M_FNCLEX, M_FSTCW, M_FNSTCW, M_FLDCW, M_FSTENV, M_FNSTENV, M_FLDENV, M_FSAVE, M_FNSAVE, M_FRSTOR, M_FSTSW, M_FNSTSW, M_FXSAVE, M_FXSAVE64, M_FXRSTOR, M_FXRSTOR64, - M_LGDT, M_SGDT, M_LIDT, M_SIDT, M_LLDT, M_SLDT, M_LTR, M_STR, M_LMSW, M_SMSW, M_CLTS, M_ARPL, M_LAR, M_LSL, M_VERR, M_VERW, - M_INVD, M_WBINVD, M_INVLPG, M_INVPCID, M_RSM, M_RDMSR, M_WRMSR, M_VMCALL, M_VMLAUNCH, M_VMRESUME, M_VMXOFF, M_VMXON, M_VMCLEAR, M_VMPTRLD, M_VMPTRST, M_VMREAD, - M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, M_RSTORSSP, M_WRSSD, - M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, M_XSAVEC64, M_XSAVES, - M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, M_CMPXCHG16B, M_XADD, - M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, + M_VMOVHPS, M_VMOVLPD, M_VMOVHPD, M_VMOVLHPS, M_VMOVHLPS, M_VMOVMSKPS, M_VMOVMSKPD, M_VMOVNTPS, M_VMOVNTPD, M_VMOVNTDQ, M_VMOVNTDQA, M_VADDSUBPS, M_VADDSUBPD, M_VHADDPS, M_VHADDPD, M_VHSUBPS, + M_VHSUBPD, M_VLDDQU, M_VMOVDDUP, M_VMOVSLDUP, M_VMOVSHDUP, M_VPCMPESTRI, M_VPCMPESTRM, M_VPCMPISTRI, M_VPCMPISTRM, M_VPBROADCASTB, M_VPBROADCASTW, M_VPBROADCASTD, M_VPBROADCASTQ, M_VCVTPS2PD, M_VCVTPD2PS, M_VCVTSS2SD, + M_VCVTSD2SS, M_VCVTPS2DQ, M_VCVTPD2DQ, M_VCVTDQ2PS, M_VCVTDQ2PD, M_VCVTSS2SI, M_VCVTSD2SI, M_VCVTSI2SS, M_VCVTSI2SD, M_VCVTTPS2DQ, M_VCVTTPD2DQ, M_VCVTTSS2SI, M_VCVTTSD2SI, M_VPADDB, M_VPADDW, M_VPADDD, + M_VPADDQ, M_VPSUBB, M_VPSUBW, M_VPSUBD, M_VPSUBQ, M_VPMULLW, M_VPMULHW, M_VPMULHUW, M_VPMULUDQ, M_VPMADDWD, M_VPAND, M_VPANDN, M_VPOR, M_VPXOR, M_VPSLLW, M_VPSLLD, + M_VPSLLQ, M_VPSRLW, M_VPSRLD, M_VPSRLQ, M_VPSRAW, M_VPSRAD, M_VPCMPEQB, M_VPCMPEQW, M_VPCMPEQD, M_VPCMPEQQ, M_VPCMPGTB, M_VPCMPGTW, M_VPCMPGTD, M_VPCMPGTQ, M_VPACKSSWB, M_VPACKSSDW, + M_VPACKUSWB, M_VPACKUSDW, M_VPUNPCKLBW, M_VPUNPCKLWD, M_VPUNPCKLDQ, M_VPUNPCKLQDQ, M_VPUNPCKHBW, M_VPUNPCKHWD, M_VPUNPCKHDQ, M_VPUNPCKHQDQ, M_VPSHUFD, M_VPSHUFHW, M_VPSHUFLW, M_VPEXTRB, M_VPEXTRW, M_VPEXTRD, + M_VPEXTRQ, M_VPINSRB, M_VPINSRW, M_VPINSRD, M_VPINSRQ, M_VPMOVMSKB, M_VPTEST, M_VPSHUFB, M_VPHADDW, M_VPHADDD, M_VPHADDSW, M_VPHSUBW, M_VPHSUBD, M_VPHSUBSW, M_VPMADDUBSW, M_VPMULHRSW, + M_VPSIGNB, M_VPSIGNW, M_VPSIGND, M_VPABSB, M_VPABSW, M_VPABSD, M_VPALIGNR, M_VPBLENDW, M_VPBLENDVB, M_VMPSADBW, M_VPHMINPOSUW, M_VPMAXSB, M_VPMAXSD, M_VPMAXUW, M_VPMAXUD, M_VPMINSB, + M_VPMINSD, M_VPMINUW, M_VPMINUD, M_VPMOVSXBW, M_VPMOVSXBD, M_VPMOVSXBQ, M_VPMOVSXWD, M_VPMOVSXWQ, M_VPMOVSXDQ, M_VPMOVZXBW, M_VPMOVZXBD, M_VPMOVZXBQ, M_VPMOVZXWD, M_VPMOVZXWQ, M_VPMOVZXDQ, M_VPMULDQ, + M_VPMULLD, M_VMASKMOVDQU, M_VPCLMULQDQ, M_VAESDEC, M_VAESDECLAST, M_VAESENC, M_VAESENCLAST, M_VAESIMC, M_VAESKEYGENASSIST, M_VBROADCASTSS, M_VBROADCASTSD, M_VBROADCASTF128, M_VEXTRACTF128, M_VINSERTF128, M_VPERM2F128, M_VMASKMOVPS, + M_VMASKMOVPD, M_VTESTPS, M_VTESTPD, M_VZEROALL, M_VZEROUPPER, M_VBROADCASTI128, M_VEXTRACTI128, M_VINSERTI128, M_VPERM2I128, M_VPERMD, M_VPERMPS, M_VPERMQ, M_VPERMPD, M_VPBLENDD, M_VPSLLVD, M_VPSLLVQ, + M_VPSRLVD, M_VPSRLVQ, M_VPSRAVD, M_VPMASKMOVD, M_VPMASKMOVQ, M_VGATHERDPS, M_VGATHERDPD, M_VGATHERQPS, M_VGATHERQPD, M_VPGATHERDD, M_VPGATHERDQ, M_VPGATHERQD, M_VPGATHERQQ, M_VFMADD132PS, M_VFMADD213PS, M_VFMADD231PS, + M_VFMADD132PD, M_VFMADD213PD, M_VFMADD231PD, M_VFMADD132SS, M_VFMADD213SS, M_VFMADD231SS, M_VFMADD132SD, M_VFMADD213SD, M_VFMADD231SD, M_VFMSUB132PS, M_VFMSUB213PS, M_VFMSUB231PS, M_VFMSUB132PD, M_VFMSUB213PD, M_VFMSUB231PD, M_VFMSUB132SS, + M_VFMSUB213SS, M_VFMSUB231SS, M_VFMSUB132SD, M_VFMSUB213SD, M_VFMSUB231SD, M_VFNMADD132PS, M_VFNMADD213PS, M_VFNMADD231PS, M_VFNMADD132PD, M_VFNMADD213PD, M_VFNMADD231PD, M_VFNMADD132SS, M_VFNMADD213SS, M_VFNMADD231SS, M_VFNMADD132SD, M_VFNMADD213SD, + M_VFNMADD231SD, M_VFNMSUB132PS, M_VFNMSUB213PS, M_VFNMSUB231PS, M_VFNMSUB132PD, M_VFNMSUB213PD, M_VFNMSUB231PD, M_VFNMSUB132SS, M_VFNMSUB213SS, M_VFNMSUB231SS, M_VFNMSUB132SD, M_VFNMSUB213SD, M_VFNMSUB231SD, M_VFMADDSUB132PS, M_VFMADDSUB213PS, M_VFMADDSUB231PS, + M_VFMADDSUB132PD, M_VFMADDSUB213PD, M_VFMADDSUB231PD, M_VFMSUBADD132PS, M_VFMSUBADD213PS, M_VFMSUBADD231PS, M_VFMSUBADD132PD, M_VFMSUBADD213PD, M_VFMSUBADD231PD, M_VCVTPH2PS, M_VCVTPS2PH, M_VMOVDQA32, M_VMOVDQA64, M_VMOVDQU8, M_VMOVDQU16, M_VMOVDQU32, + M_VMOVDQU64, M_VPBLENDMB, M_VPBLENDMW, M_VPBLENDMD, M_VPBLENDMQ, M_VBLENDMPS, M_VBLENDMPD, M_VPCMPB, M_VPCMPUB, M_VPCMPW, M_VPCMPUW, M_VPCMPD, M_VPCMPUD, M_VPCMPQ, M_VPCMPUQ, M_VPTESTMB, + M_VPTESTMW, M_VPTESTMD, M_VPTESTMQ, M_VPTESTNMB, M_VPTESTNMW, M_VPTESTNMD, M_VPTESTNMQ, M_VPCOMPRESSD, M_VPCOMPRESSQ, M_VCOMPRESSPS, M_VCOMPRESSPD, M_VPEXPANDD, M_VPEXPANDQ, M_VEXPANDPS, M_VEXPANDPD, M_VPCONFLICTD, + M_VPCONFLICTQ, M_VPLZCNTD, M_VPLZCNTQ, M_VPERMI2B, M_VPERMI2W, M_VPERMI2D, M_VPERMI2Q, M_VPERMI2PS, M_VPERMI2PD, M_VPERMT2B, M_VPERMT2W, M_VPERMT2D, M_VPERMT2Q, M_VPERMT2PS, M_VPERMT2PD, M_VPERMB, + M_VPERMW, M_VPMOVB2M, M_VPMOVW2M, M_VPMOVD2M, M_VPMOVQ2M, M_VPMOVM2B, M_VPMOVM2W, M_VPMOVM2D, M_VPMOVM2Q, M_VPMOVQB, M_VPMOVSQB, M_VPMOVUSQB, M_VPMOVQW, M_VPMOVSQW, M_VPMOVUSQW, M_VPMOVQD, + M_VPMOVSQD, M_VPMOVUSQD, M_VPMOVDB, M_VPMOVSDB, M_VPMOVUSDB, M_VPMOVDW, M_VPMOVSDW, M_VPMOVUSDW, M_VPMOVWB, M_VPMOVSWB, M_VPMOVUSWB, M_VPROLD, M_VPROLQ, M_VPROLVD, M_VPROLVQ, M_VPRORD, + M_VPRORQ, M_VPRORVD, M_VPRORVQ, M_VPSCATTERDD, M_VPSCATTERDQ, M_VPSCATTERQD, M_VPSCATTERQQ, M_VSCATTERDPS, M_VSCATTERDPD, M_VSCATTERQPS, M_VSCATTERQPD, M_VPSRAVQ, M_VPSRAVW, M_VPSLLVW, M_VPSRLVW, M_VRANGEPS, + M_VRANGEPD, M_VRANGESS, M_VRANGESD, M_VREDUCEPS, M_VREDUCEPD, M_VREDUCESS, M_VREDUCESD, M_VRNDSCALEPS, M_VRNDSCALEPD, M_VRNDSCALESS, M_VRNDSCALESD, M_VRSQRT14PS, M_VRSQRT14PD, M_VRSQRT14SS, M_VRSQRT14SD, M_VRCP14PS, + M_VRCP14PD, M_VRCP14SS, M_VRCP14SD, M_VSCALEFPS, M_VSCALEFPD, M_VSCALEFSS, M_VSCALEFSD, M_VGETEXPPS, M_VGETEXPPD, M_VGETEXPSS, M_VGETEXPSD, M_VGETMANTPS, M_VGETMANTPD, M_VGETMANTSS, M_VGETMANTSD, M_VFIXUPIMMPS, + M_VFIXUPIMMPD, M_VFIXUPIMMSS, M_VFIXUPIMMSD, M_VFPCLASSPS, M_VFPCLASSPD, M_VFPCLASSSS, M_VFPCLASSSD, M_VALIGNQ, M_VALIGND, M_VDBPSADBW, M_VPTERNLOGD, M_VPTERNLOGQ, M_VPMULTISHIFTQB, M_KADDW, M_KADDB, M_KADDQ, + M_KADDD, M_KANDW, M_KANDB, M_KANDQ, M_KANDD, M_KANDNW, M_KANDNB, M_KANDNQ, M_KANDND, M_KMOVW, M_KMOVB, M_KMOVQ, M_KMOVD, M_KNOTW, M_KNOTB, M_KNOTQ, + M_KNOTD, M_KORW, M_KORB, M_KORQ, M_KORD, M_KORTESTW, M_KORTESTB, M_KORTESTQ, M_KORTESTD, M_KSHIFTLW, M_KSHIFTLB, M_KSHIFTLQ, M_KSHIFTLD, M_KSHIFTRW, M_KSHIFTRB, M_KSHIFTRQ, + M_KSHIFTRD, M_KTESTW, M_KTESTB, M_KTESTQ, M_KTESTD, M_KUNPCKBW, M_KUNPCKWD, M_KUNPCKDQ, M_KXNORW, M_KXNORB, M_KXNORQ, M_KXNORD, M_KXORW, M_KXORB, M_KXORQ, M_KXORD, + M_FADD, M_FADDP, M_FIADD, M_FSUB, M_FSUBP, M_FISUB, M_FSUBR, M_FSUBRP, M_FISUBR, M_FMUL, M_FMULP, M_FIMUL, M_FDIV, M_FDIVP, M_FIDIV, M_FDIVR, + M_FDIVRP, M_FIDIVR, M_FSQRT, M_FABS, M_FCHS, M_FPREM, M_FPREM1, M_FRNDINT, M_FSCALE, M_FXTRACT, M_FXAM, M_FLD, M_FILD, M_FBLD, M_FST, M_FSTP, + M_FIST, M_FISTP, M_FISTTP, M_FBSTP, M_FXCH, M_FCMOVB, M_FCMOVE, M_FCMOVBE, M_FCMOVU, M_FCMOVNB, M_FCMOVNE, M_FCMOVNBE, M_FCMOVNU, M_FCOM, M_FCOMP, M_FCOMPP, + M_FICOM, M_FICOMP, M_FCOMI, M_FCOMIP, M_FUCOMI, M_FUCOMIP, M_FUCOM, M_FUCOMP, M_FUCOMPP, M_FTST, M_FLDZ, M_FLD1, M_FLDPI, M_FLDL2T, M_FLDL2E, M_FLDLG2, + M_FLDLN2, M_FSIN, M_FCOS, M_FSINCOS, M_FPTAN, M_FPATAN, M_F2XM1, M_FYL2X, M_FYL2XP1, M_FINIT, M_FNINIT, M_FINCSTP, M_FDECSTP, M_FFREE, M_FFREEP, M_FNOP, + M_FWAIT, M_FCLEX, M_FNCLEX, M_FSTCW, M_FNSTCW, M_FLDCW, M_FSTENV, M_FNSTENV, M_FLDENV, M_FSAVE, M_FNSAVE, M_FRSTOR, M_FSTSW, M_FNSTSW, M_FXSAVE, M_FXSAVE64, + M_FXRSTOR, M_FXRSTOR64, M_LGDT, M_SGDT, M_LIDT, M_SIDT, M_LLDT, M_SLDT, M_LTR, M_STR, M_LMSW, M_SMSW, M_CLTS, M_ARPL, M_LAR, M_LSL, + M_VERR, M_VERW, M_INVD, M_WBINVD, M_INVLPG, M_INVPCID, M_RSM, M_RDMSR, M_WRMSR, M_VMCALL, M_VMLAUNCH, M_VMRESUME, M_VMXOFF, M_VMXON, M_VMCLEAR, M_VMPTRLD, + M_VMPTRST, M_VMREAD, M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, + M_RSTORSSP, M_WRSSD, M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, + M_XSAVEC64, M_XSAVES, M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, + M_CMPXCHG16B, M_XADD, M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, MNEMONIC_COUNT }; @@ -243,8 +244,8 @@ struct Asm_amd64 { }; - static EncodeRun const raw_encode_runs[1176]; - static u8 const raw_encode_forms[37680]; + static EncodeRun const raw_encode_runs[1194]; + static u8 const raw_encode_forms[38320]; StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; @@ -444,45 +445,46 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit("vminpd"), str_lit("vminss"), str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), str_lit("vcomisd"), str_lit("vucomiss"), str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), str_lit("vroundpd"), str_lit("vroundss"), str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), - str_lit("vmovhps"), str_lit("vmovlpd"), str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), - str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), str_lit("vpaddq"), str_lit("vpsubb"), - str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), str_lit("vpsllq"), str_lit("vpsrlw"), - str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), str_lit("vpackuswb"), str_lit("vpackusdw"), - str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), str_lit("vpextrq"), str_lit("vpinsrb"), - str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), str_lit("vpsignb"), str_lit("vpsignw"), - str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), str_lit("vpminsd"), str_lit("vpminuw"), - str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), str_lit("vpmulld"), str_lit("vmaskmovdqu"), - str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), str_lit("vmaskmovpd"), str_lit("vtestps"), - str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), str_lit("vpsrlvd"), str_lit("vpsrlvq"), - str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), - str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), - str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), - str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), - str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), str_lit("vmovdqu64"), str_lit("vpblendmb"), - str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), str_lit("vptestmw"), str_lit("vptestmd"), - str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), str_lit("vpconflictq"), str_lit("vplzcntd"), - str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), str_lit("vpermw"), str_lit("vpmovb2m"), - str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), str_lit("vpmovsqd"), str_lit("vpmovusqd"), - str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), str_lit("vprorq"), str_lit("vprorvd"), - str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), str_lit("vrangepd"), str_lit("vrangess"), - str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), str_lit("vrcp14pd"), str_lit("vrcp14ss"), - str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), str_lit("vfixupimmpd"), str_lit("vfixupimmss"), - str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), str_lit("kaddd"), str_lit("kandw"), - str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), str_lit("knotd"), str_lit("korw"), - str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), str_lit("kshiftrd"), str_lit("ktestw"), - str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), str_lit("fadd"), str_lit("faddp"), - str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), str_lit("fdivrp"), str_lit("fidivr"), - str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), str_lit("fist"), str_lit("fistp"), - str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), str_lit("ficom"), str_lit("ficomp"), - str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), str_lit("fldln2"), str_lit("fsin"), - str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), str_lit("fwait"), str_lit("fclex"), - str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), str_lit("fxrstor"), str_lit("fxrstor64"), - str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), str_lit("verr"), str_lit("verw"), - str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), str_lit("vmptrst"), str_lit("vmread"), - str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), str_lit("wrssd"), - str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), str_lit("xsaves"), - str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"), - str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), + str_lit("vmovhps"), str_lit("vmovlpd"), str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vaddsubps"), str_lit("vaddsubpd"), str_lit("vhaddps"), str_lit("vhaddpd"), str_lit("vhsubps"), + str_lit("vhsubpd"), str_lit("vlddqu"), str_lit("vmovddup"), str_lit("vmovsldup"), str_lit("vmovshdup"), str_lit("vpcmpestri"), str_lit("vpcmpestrm"), str_lit("vpcmpistri"), str_lit("vpcmpistrm"), str_lit("vpbroadcastb"), str_lit("vpbroadcastw"), str_lit("vpbroadcastd"), str_lit("vpbroadcastq"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), + str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), + str_lit("vpaddq"), str_lit("vpsubb"), str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), + str_lit("vpsllq"), str_lit("vpsrlw"), str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), + str_lit("vpackuswb"), str_lit("vpackusdw"), str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), + str_lit("vpextrq"), str_lit("vpinsrb"), str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), + str_lit("vpsignb"), str_lit("vpsignw"), str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), + str_lit("vpminsd"), str_lit("vpminuw"), str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), + str_lit("vpmulld"), str_lit("vmaskmovdqu"), str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), + str_lit("vmaskmovpd"), str_lit("vtestps"), str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), + str_lit("vpsrlvd"), str_lit("vpsrlvq"), str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), + str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), + str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), + str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), + str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), + str_lit("vmovdqu64"), str_lit("vpblendmb"), str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), + str_lit("vptestmw"), str_lit("vptestmd"), str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), + str_lit("vpconflictq"), str_lit("vplzcntd"), str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), + str_lit("vpermw"), str_lit("vpmovb2m"), str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), + str_lit("vpmovsqd"), str_lit("vpmovusqd"), str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), + str_lit("vprorq"), str_lit("vprorvd"), str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), + str_lit("vrangepd"), str_lit("vrangess"), str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), + str_lit("vrcp14pd"), str_lit("vrcp14ss"), str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), + str_lit("vfixupimmpd"), str_lit("vfixupimmss"), str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), + str_lit("kaddd"), str_lit("kandw"), str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), + str_lit("knotd"), str_lit("korw"), str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), + str_lit("kshiftrd"), str_lit("ktestw"), str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), + str_lit("fadd"), str_lit("faddp"), str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), + str_lit("fdivrp"), str_lit("fidivr"), str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), + str_lit("fist"), str_lit("fistp"), str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), + str_lit("ficom"), str_lit("ficomp"), str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), + str_lit("fldln2"), str_lit("fsin"), str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), + str_lit("fwait"), str_lit("fclex"), str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), + str_lit("fxrstor"), str_lit("fxrstor64"), str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), + str_lit("verr"), str_lit("verw"), str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), + str_lit("vmptrst"), str_lit("vmread"), str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), + str_lit("rstorssp"), str_lit("wrssd"), str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), + str_lit("xsavec64"), str_lit("xsaves"), str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), + str_lit("cmpxchg16b"), str_lit("xadd"), str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), }; String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] { str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"), @@ -519,7 +521,7 @@ String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] { str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"), str_lit("st6"), str_lit("st7"), str_lit("rip"), }; -Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1176] = { +Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1194] = { { 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13}, { 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12}, { 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2}, @@ -555,47 +557,48 @@ Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1176] = { {1064, 2}, {1066, 1}, {1067, 1}, {1068, 2}, {1070, 2}, {1072, 2}, {1074, 2}, {1076, 2}, {1078, 2}, {1080, 2}, {1082, 2}, {1084, 2}, {1086, 2}, {1088, 1}, {1089, 1}, {1090, 1}, {1091, 1}, {1092, 1}, {1093, 1}, {1094, 2}, {1096, 2}, {1098, 2}, {1100, 2}, {1102, 2}, {1104, 2}, {1106, 2}, {1108, 2}, {1110, 2}, {1112, 2}, {1114, 2}, {1116, 1}, {1117, 2}, {1119, 2}, {1121, 1}, {1122, 1}, {1123, 1}, {1124, 1}, {1125, 4}, {1129, 4}, {1133, 4}, {1137, 4}, {1141, 3}, {1144, 3}, {1147, 4}, {1151, 4}, {1155, 4}, {1159, 2}, {1161, 2}, - {1163, 2}, {1165, 2}, {1167, 2}, {1169, 1}, {1170, 1}, {1171, 2}, {1173, 2}, {1175, 2}, {1177, 2}, {1179, 2}, {1181, 2}, {1183, 2}, {1185, 2}, {1187, 1}, {1188, 1}, {1189, 2}, - {1191, 2}, {1193, 2}, {1195, 2}, {1197, 2}, {1199, 2}, {1201, 2}, {1203, 2}, {1205, 2}, {1207, 2}, {1209, 2}, {1211, 2}, {1213, 2}, {1215, 2}, {1217, 2}, {1219, 2}, {1221, 2}, - {1223, 2}, {1225, 2}, {1227, 2}, {1229, 2}, {1231, 2}, {1233, 2}, {1235, 2}, {1237, 2}, {1239, 2}, {1241, 2}, {1243, 2}, {1245, 2}, {1247, 4}, {1251, 4}, {1255, 4}, {1259, 4}, - {1263, 4}, {1267, 4}, {1271, 4}, {1275, 4}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 2}, {1289, 2}, {1291, 2}, {1293, 2}, {1295, 2}, {1297, 2}, {1299, 2}, {1301, 2}, - {1303, 2}, {1305, 2}, {1307, 2}, {1309, 2}, {1311, 2}, {1313, 2}, {1315, 2}, {1317, 2}, {1319, 2}, {1321, 2}, {1323, 2}, {1325, 1}, {1326, 2}, {1328, 1}, {1329, 1}, {1330, 1}, - {1331, 1}, {1332, 1}, {1333, 1}, {1334, 2}, {1336, 2}, {1338, 2}, {1340, 2}, {1342, 2}, {1344, 2}, {1346, 2}, {1348, 2}, {1350, 2}, {1352, 2}, {1354, 2}, {1356, 2}, {1358, 2}, - {1360, 2}, {1362, 2}, {1364, 2}, {1366, 2}, {1368, 2}, {1370, 2}, {1372, 2}, {1374, 2}, {1376, 1}, {1377, 2}, {1379, 2}, {1381, 2}, {1383, 2}, {1385, 2}, {1387, 2}, {1389, 2}, - {1391, 2}, {1393, 2}, {1395, 2}, {1397, 2}, {1399, 2}, {1401, 2}, {1403, 2}, {1405, 2}, {1407, 2}, {1409, 2}, {1411, 2}, {1413, 2}, {1415, 2}, {1417, 2}, {1419, 2}, {1421, 1}, - {1422, 2}, {1424, 1}, {1425, 1}, {1426, 1}, {1427, 1}, {1428, 1}, {1429, 1}, {1430, 4}, {1434, 2}, {1436, 1}, {1437, 1}, {1438, 1}, {1439, 1}, {1440, 4}, {1444, 4}, {1448, 2}, - {1450, 2}, {1452, 1}, {1453, 1}, {1454, 1}, {1455, 1}, {1456, 1}, {1457, 1}, {1458, 1}, {1459, 1}, {1460, 1}, {1461, 1}, {1462, 2}, {1464, 2}, {1466, 2}, {1468, 2}, {1470, 2}, - {1472, 2}, {1474, 4}, {1478, 4}, {1482, 2}, {1484, 2}, {1486, 2}, {1488, 2}, {1490, 2}, {1492, 2}, {1494, 2}, {1496, 2}, {1498, 2}, {1500, 2}, {1502, 2}, {1504, 2}, {1506, 2}, - {1508, 2}, {1510, 1}, {1511, 1}, {1512, 1}, {1513, 1}, {1514, 1}, {1515, 1}, {1516, 2}, {1518, 2}, {1520, 2}, {1522, 2}, {1524, 2}, {1526, 2}, {1528, 1}, {1529, 1}, {1530, 1}, - {1531, 1}, {1532, 1}, {1533, 1}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, {1544, 2}, {1546, 1}, {1547, 1}, {1548, 1}, {1549, 1}, {1550, 1}, {1551, 1}, {1552, 2}, - {1554, 2}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 2}, {1564, 1}, {1565, 1}, {1566, 1}, {1567, 1}, {1568, 1}, {1569, 1}, {1570, 2}, {1572, 2}, {1574, 2}, {1576, 2}, {1578, 2}, - {1580, 2}, {1582, 2}, {1584, 2}, {1586, 2}, {1588, 2}, {1590, 2}, {1592, 2}, {1594, 3}, {1597, 3}, {1600, 6}, {1606, 6}, {1612, 6}, {1618, 6}, {1624, 6}, {1630, 6}, {1636, 3}, - {1639, 3}, {1642, 3}, {1645, 3}, {1648, 3}, {1651, 3}, {1654, 3}, {1657, 3}, {1660, 3}, {1663, 3}, {1666, 3}, {1669, 3}, {1672, 3}, {1675, 3}, {1678, 3}, {1681, 3}, {1684, 3}, - {1687, 3}, {1690, 3}, {1693, 3}, {1696, 3}, {1699, 3}, {1702, 3}, {1705, 3}, {1708, 3}, {1711, 3}, {1714, 3}, {1717, 3}, {1720, 3}, {1723, 3}, {1726, 3}, {1729, 3}, {1732, 3}, - {1735, 3}, {1738, 3}, {1741, 3}, {1744, 3}, {1747, 3}, {1750, 3}, {1753, 3}, {1756, 3}, {1759, 3}, {1762, 3}, {1765, 3}, {1768, 3}, {1771, 3}, {1774, 3}, {1777, 3}, {1780, 3}, - {1783, 3}, {1786, 3}, {1789, 3}, {1792, 3}, {1795, 3}, {1798, 3}, {1801, 3}, {1804, 3}, {1807, 3}, {1810, 3}, {1813, 3}, {1816, 3}, {1819, 3}, {1822, 3}, {1825, 3}, {1828, 3}, - {1831, 3}, {1834, 3}, {1837, 3}, {1840, 3}, {1843, 3}, {1846, 3}, {1849, 3}, {1852, 3}, {1855, 3}, {1858, 3}, {1861, 3}, {1864, 3}, {1867, 3}, {1870, 3}, {1873, 3}, {1876, 3}, - {1879, 3}, {1882, 3}, {1885, 3}, {1888, 3}, {1891, 3}, {1894, 3}, {1897, 3}, {1900, 3}, {1903, 3}, {1906, 3}, {1909, 3}, {1912, 3}, {1915, 3}, {1918, 3}, {1921, 3}, {1924, 1}, - {1925, 1}, {1926, 3}, {1929, 3}, {1932, 1}, {1933, 1}, {1934, 3}, {1937, 3}, {1940, 1}, {1941, 1}, {1942, 3}, {1945, 3}, {1948, 1}, {1949, 1}, {1950, 3}, {1953, 3}, {1956, 1}, - {1957, 1}, {1958, 3}, {1961, 3}, {1964, 1}, {1965, 1}, {1966, 3}, {1969, 3}, {1972, 1}, {1973, 1}, {1974, 3}, {1977, 3}, {1980, 1}, {1981, 1}, {1982, 3}, {1985, 3}, {1988, 1}, - {1989, 1}, {1990, 3}, {1993, 3}, {1996, 1}, {1997, 1}, {1998, 3}, {2001, 3}, {2004, 3}, {2007, 3}, {2010, 3}, {2013, 3}, {2016, 1}, {2017, 1}, {2018, 1}, {2019, 1}, {2020, 1}, - {2021, 1}, {2022, 1}, {2023, 1}, {2024, 1}, {2025, 1}, {2026, 1}, {2027, 1}, {2028, 4}, {2032, 4}, {2036, 4}, {2040, 4}, {2044, 1}, {2045, 1}, {2046, 1}, {2047, 1}, {2048, 1}, - {2049, 1}, {2050, 1}, {2051, 1}, {2052, 1}, {2053, 1}, {2054, 1}, {2055, 1}, {2056, 1}, {2057, 1}, {2058, 1}, {2059, 1}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, - {2065, 1}, {2066, 1}, {2067, 1}, {2068, 1}, {2069, 1}, {2070, 1}, {2071, 1}, {2072, 1}, {2073, 1}, {2074, 1}, {2075, 1}, {2076, 1}, {2077, 1}, {2078, 1}, {2079, 4}, {2083, 2}, - {2085, 2}, {2087, 4}, {2091, 2}, {2093, 2}, {2095, 4}, {2099, 2}, {2101, 2}, {2103, 4}, {2107, 2}, {2109, 2}, {2111, 4}, {2115, 2}, {2117, 2}, {2119, 4}, {2123, 2}, {2125, 2}, - {2127, 1}, {2128, 1}, {2129, 1}, {2130, 1}, {2131, 1}, {2132, 1}, {2133, 1}, {2134, 1}, {2135, 1}, {2136, 4}, {2140, 3}, {2143, 1}, {2144, 3}, {2147, 4}, {2151, 2}, {2153, 3}, - {2156, 3}, {2159, 1}, {2160, 2}, {2162, 1}, {2163, 1}, {2164, 1}, {2165, 1}, {2166, 1}, {2167, 1}, {2168, 1}, {2169, 1}, {2170, 4}, {2174, 4}, {2178, 1}, {2179, 2}, {2181, 2}, - {2183, 1}, {2184, 1}, {2185, 1}, {2186, 1}, {2187, 2}, {2189, 2}, {2191, 1}, {2192, 1}, {2193, 1}, {2194, 1}, {2195, 1}, {2196, 1}, {2197, 1}, {2198, 1}, {2199, 1}, {2200, 1}, - {2201, 1}, {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 1}, {2207, 1}, {2208, 1}, {2209, 1}, {2210, 1}, {2211, 1}, {2212, 1}, {2213, 1}, {2214, 1}, {2215, 1}, {2216, 1}, - {2217, 1}, {2218, 1}, {2219, 1}, {2220, 1}, {2221, 1}, {2222, 1}, {2223, 1}, {2224, 1}, {2225, 1}, {2226, 1}, {2227, 2}, {2229, 2}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, - {2235, 2}, {2237, 2}, {2239, 2}, {2241, 2}, {2243, 1}, {2244, 3}, {2247, 1}, {2248, 3}, {2251, 1}, {2252, 3}, {2255, 1}, {2256, 1}, {2257, 3}, {2260, 3}, {2263, 1}, {2264, 1}, - {2265, 1}, {2266, 1}, {2267, 1}, {2268, 2}, {2270, 1}, {2271, 1}, {2272, 1}, {2273, 1}, {2274, 1}, {2275, 1}, {2276, 1}, {2277, 1}, {2278, 1}, {2279, 1}, {2280, 1}, {2281, 1}, - {2282, 1}, {2283, 1}, {2284, 1}, {2285, 1}, {2286, 1}, {2287, 1}, {2288, 1}, {2289, 1}, {2290, 1}, {2291, 1}, {2292, 1}, {2293, 1}, {2294, 1}, {2295, 1}, {2296, 1}, {2297, 1}, - {2298, 1}, {2299, 1}, {2300, 1}, {2301, 1}, {2302, 1}, {2303, 1}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 1}, {2309, 1}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, - {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 1}, {2319, 1}, {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, {2324, 1}, {2325, 2}, {2327, 4}, {2331, 1}, {2332, 1}, {2333, 4}, - {2337, 2}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 6}, {2349, 3}, {2352, 3}, + {1163, 2}, {1165, 2}, {1167, 2}, {1169, 1}, {1170, 1}, {1171, 2}, {1173, 2}, {1175, 2}, {1177, 2}, {1179, 2}, {1181, 2}, {1183, 2}, {1185, 2}, {1187, 2}, {1189, 2}, {1191, 2}, + {1193, 2}, {1195, 2}, {1197, 2}, {1199, 2}, {1201, 2}, {1203, 1}, {1204, 1}, {1205, 1}, {1206, 1}, {1207, 4}, {1211, 4}, {1215, 4}, {1219, 4}, {1223, 2}, {1225, 2}, {1227, 1}, + {1228, 1}, {1229, 2}, {1231, 2}, {1233, 2}, {1235, 2}, {1237, 2}, {1239, 2}, {1241, 2}, {1243, 2}, {1245, 2}, {1247, 2}, {1249, 2}, {1251, 2}, {1253, 2}, {1255, 2}, {1257, 2}, + {1259, 2}, {1261, 2}, {1263, 2}, {1265, 2}, {1267, 2}, {1269, 2}, {1271, 2}, {1273, 2}, {1275, 2}, {1277, 2}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 4}, {1291, 4}, + {1295, 4}, {1299, 4}, {1303, 4}, {1307, 4}, {1311, 4}, {1315, 4}, {1319, 2}, {1321, 2}, {1323, 2}, {1325, 2}, {1327, 2}, {1329, 2}, {1331, 2}, {1333, 2}, {1335, 2}, {1337, 2}, + {1339, 2}, {1341, 2}, {1343, 2}, {1345, 2}, {1347, 2}, {1349, 2}, {1351, 2}, {1353, 2}, {1355, 2}, {1357, 2}, {1359, 2}, {1361, 2}, {1363, 2}, {1365, 1}, {1366, 2}, {1368, 1}, + {1369, 1}, {1370, 1}, {1371, 1}, {1372, 1}, {1373, 1}, {1374, 2}, {1376, 2}, {1378, 2}, {1380, 2}, {1382, 2}, {1384, 2}, {1386, 2}, {1388, 2}, {1390, 2}, {1392, 2}, {1394, 2}, + {1396, 2}, {1398, 2}, {1400, 2}, {1402, 2}, {1404, 2}, {1406, 2}, {1408, 2}, {1410, 2}, {1412, 2}, {1414, 2}, {1416, 1}, {1417, 2}, {1419, 2}, {1421, 2}, {1423, 2}, {1425, 2}, + {1427, 2}, {1429, 2}, {1431, 2}, {1433, 2}, {1435, 2}, {1437, 2}, {1439, 2}, {1441, 2}, {1443, 2}, {1445, 2}, {1447, 2}, {1449, 2}, {1451, 2}, {1453, 2}, {1455, 2}, {1457, 2}, + {1459, 2}, {1461, 1}, {1462, 2}, {1464, 1}, {1465, 1}, {1466, 1}, {1467, 1}, {1468, 1}, {1469, 1}, {1470, 4}, {1474, 2}, {1476, 1}, {1477, 1}, {1478, 1}, {1479, 1}, {1480, 4}, + {1484, 4}, {1488, 2}, {1490, 2}, {1492, 1}, {1493, 1}, {1494, 1}, {1495, 1}, {1496, 1}, {1497, 1}, {1498, 1}, {1499, 1}, {1500, 1}, {1501, 1}, {1502, 2}, {1504, 2}, {1506, 2}, + {1508, 2}, {1510, 2}, {1512, 2}, {1514, 4}, {1518, 4}, {1522, 2}, {1524, 2}, {1526, 2}, {1528, 2}, {1530, 2}, {1532, 2}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, + {1544, 2}, {1546, 2}, {1548, 2}, {1550, 1}, {1551, 1}, {1552, 1}, {1553, 1}, {1554, 1}, {1555, 1}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 2}, {1564, 2}, {1566, 2}, {1568, 1}, + {1569, 1}, {1570, 1}, {1571, 1}, {1572, 1}, {1573, 1}, {1574, 2}, {1576, 2}, {1578, 2}, {1580, 2}, {1582, 2}, {1584, 2}, {1586, 1}, {1587, 1}, {1588, 1}, {1589, 1}, {1590, 1}, + {1591, 1}, {1592, 2}, {1594, 2}, {1596, 2}, {1598, 2}, {1600, 2}, {1602, 2}, {1604, 1}, {1605, 1}, {1606, 1}, {1607, 1}, {1608, 1}, {1609, 1}, {1610, 2}, {1612, 2}, {1614, 2}, + {1616, 2}, {1618, 2}, {1620, 2}, {1622, 2}, {1624, 2}, {1626, 2}, {1628, 2}, {1630, 2}, {1632, 2}, {1634, 3}, {1637, 3}, {1640, 6}, {1646, 6}, {1652, 6}, {1658, 6}, {1664, 6}, + {1670, 6}, {1676, 3}, {1679, 3}, {1682, 3}, {1685, 3}, {1688, 3}, {1691, 3}, {1694, 3}, {1697, 3}, {1700, 3}, {1703, 3}, {1706, 3}, {1709, 3}, {1712, 3}, {1715, 3}, {1718, 3}, + {1721, 3}, {1724, 3}, {1727, 3}, {1730, 3}, {1733, 3}, {1736, 3}, {1739, 3}, {1742, 3}, {1745, 3}, {1748, 3}, {1751, 3}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, {1766, 3}, + {1769, 3}, {1772, 3}, {1775, 3}, {1778, 3}, {1781, 3}, {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, + {1817, 3}, {1820, 3}, {1823, 3}, {1826, 3}, {1829, 3}, {1832, 3}, {1835, 3}, {1838, 3}, {1841, 3}, {1844, 3}, {1847, 3}, {1850, 3}, {1853, 3}, {1856, 3}, {1859, 3}, {1862, 3}, + {1865, 3}, {1868, 3}, {1871, 3}, {1874, 3}, {1877, 3}, {1880, 3}, {1883, 3}, {1886, 3}, {1889, 3}, {1892, 3}, {1895, 3}, {1898, 3}, {1901, 3}, {1904, 3}, {1907, 3}, {1910, 3}, + {1913, 3}, {1916, 3}, {1919, 3}, {1922, 3}, {1925, 3}, {1928, 3}, {1931, 3}, {1934, 3}, {1937, 3}, {1940, 3}, {1943, 3}, {1946, 3}, {1949, 3}, {1952, 3}, {1955, 3}, {1958, 3}, + {1961, 3}, {1964, 1}, {1965, 1}, {1966, 3}, {1969, 3}, {1972, 1}, {1973, 1}, {1974, 3}, {1977, 3}, {1980, 1}, {1981, 1}, {1982, 3}, {1985, 3}, {1988, 1}, {1989, 1}, {1990, 3}, + {1993, 3}, {1996, 1}, {1997, 1}, {1998, 3}, {2001, 3}, {2004, 1}, {2005, 1}, {2006, 3}, {2009, 3}, {2012, 1}, {2013, 1}, {2014, 3}, {2017, 3}, {2020, 1}, {2021, 1}, {2022, 3}, + {2025, 3}, {2028, 1}, {2029, 1}, {2030, 3}, {2033, 3}, {2036, 1}, {2037, 1}, {2038, 3}, {2041, 3}, {2044, 3}, {2047, 3}, {2050, 3}, {2053, 3}, {2056, 1}, {2057, 1}, {2058, 1}, + {2059, 1}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, {2065, 1}, {2066, 1}, {2067, 1}, {2068, 4}, {2072, 4}, {2076, 4}, {2080, 4}, {2084, 1}, {2085, 1}, {2086, 1}, + {2087, 1}, {2088, 1}, {2089, 1}, {2090, 1}, {2091, 1}, {2092, 1}, {2093, 1}, {2094, 1}, {2095, 1}, {2096, 1}, {2097, 1}, {2098, 1}, {2099, 1}, {2100, 1}, {2101, 1}, {2102, 1}, + {2103, 1}, {2104, 1}, {2105, 1}, {2106, 1}, {2107, 1}, {2108, 1}, {2109, 1}, {2110, 1}, {2111, 1}, {2112, 1}, {2113, 1}, {2114, 1}, {2115, 1}, {2116, 1}, {2117, 1}, {2118, 1}, + {2119, 4}, {2123, 2}, {2125, 2}, {2127, 4}, {2131, 2}, {2133, 2}, {2135, 4}, {2139, 2}, {2141, 2}, {2143, 4}, {2147, 2}, {2149, 2}, {2151, 4}, {2155, 2}, {2157, 2}, {2159, 4}, + {2163, 2}, {2165, 2}, {2167, 1}, {2168, 1}, {2169, 1}, {2170, 1}, {2171, 1}, {2172, 1}, {2173, 1}, {2174, 1}, {2175, 1}, {2176, 4}, {2180, 3}, {2183, 1}, {2184, 3}, {2187, 4}, + {2191, 2}, {2193, 3}, {2196, 3}, {2199, 1}, {2200, 2}, {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 1}, {2207, 1}, {2208, 1}, {2209, 1}, {2210, 4}, {2214, 4}, {2218, 1}, + {2219, 2}, {2221, 2}, {2223, 1}, {2224, 1}, {2225, 1}, {2226, 1}, {2227, 2}, {2229, 2}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, {2235, 1}, {2236, 1}, {2237, 1}, {2238, 1}, + {2239, 1}, {2240, 1}, {2241, 1}, {2242, 1}, {2243, 1}, {2244, 1}, {2245, 1}, {2246, 1}, {2247, 1}, {2248, 1}, {2249, 1}, {2250, 1}, {2251, 1}, {2252, 1}, {2253, 1}, {2254, 1}, + {2255, 1}, {2256, 1}, {2257, 1}, {2258, 1}, {2259, 1}, {2260, 1}, {2261, 1}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 2}, {2269, 2}, {2271, 1}, {2272, 1}, + {2273, 1}, {2274, 1}, {2275, 2}, {2277, 2}, {2279, 2}, {2281, 2}, {2283, 1}, {2284, 3}, {2287, 1}, {2288, 3}, {2291, 1}, {2292, 3}, {2295, 1}, {2296, 1}, {2297, 3}, {2300, 3}, + {2303, 1}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 2}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 1}, {2319, 1}, + {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, + {2336, 1}, {2337, 1}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, + {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 2}, {2367, 4}, {2371, 1}, + {2372, 1}, {2373, 4}, {2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, }; -u8 const Asm_amd64::raw_encode_forms[37680] = { +u8 const Asm_amd64::raw_encode_forms[38320] = { 0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x05, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x12, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x13, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x14, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x15, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x08, 0x08, 0x00, @@ -891,298 +894,308 @@ u8 const Asm_amd64::raw_encode_forms[37680] = { 0x32, 0x02, 0x0d, 0x23, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x17, 0x00, 0x15, 0x01, 0x08, 0x00, 0x33, 0x02, 0x23, 0x23, 0x23, 0x00, 0x02, 0x03, 0x01, 0x00, 0x16, 0x00, 0x11, 0x01, 0x0c, 0x00, 0x34, 0x02, 0x23, 0x23, 0x23, 0x00, 0x02, 0x03, 0x01, 0x00, 0x12, 0x00, 0x11, 0x01, 0x0c, 0x00, 0x35, 0x02, 0x03, 0x23, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x50, 0x00, 0x11, 0x01, 0x08, 0x00, 0x35, 0x02, 0x03, 0x24, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x50, 0x00, 0x11, 0x02, 0x08, 0x00, 0x36, 0x02, 0x03, 0x23, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x50, 0x00, 0x15, 0x01, 0x08, 0x00, 0x36, 0x02, 0x03, 0x24, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x50, 0x00, 0x15, 0x02, 0x08, 0x00, 0x37, 0x02, 0x0f, 0x23, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x2b, 0x00, 0x11, 0x01, 0x08, 0x00, 0x37, 0x02, 0x10, 0x24, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x2b, 0x00, 0x11, 0x02, 0x08, 0x00, 0x38, 0x02, 0x0f, 0x23, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x2b, 0x00, 0x15, 0x01, 0x08, 0x00, 0x38, 0x02, 0x10, 0x24, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x2b, 0x00, 0x15, 0x02, 0x08, 0x00, 0x39, 0x02, 0x0f, 0x23, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xe7, 0x00, 0x15, 0x01, 0x08, 0x00, - 0x39, 0x02, 0x10, 0x24, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xe7, 0x00, 0x15, 0x02, 0x08, 0x00, 0x3a, 0x02, 0x23, 0x0f, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2a, 0x00, 0x16, 0x01, 0x08, 0x00, 0x3a, 0x02, 0x24, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2a, 0x00, 0x16, 0x02, 0x08, 0x00, 0x3b, 0x02, 0x23, 0x27, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5a, 0x00, 0x11, 0x01, 0x08, 0x00, - 0x3b, 0x02, 0x24, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5a, 0x00, 0x11, 0x02, 0x08, 0x00, 0x3c, 0x02, 0x23, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5a, 0x00, 0x15, 0x01, 0x08, 0x00, 0x3c, 0x02, 0x23, 0x29, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5a, 0x00, 0x15, 0x02, 0x08, 0x00, 0x3d, 0x02, 0x23, 0x23, 0x26, 0x00, 0x02, 0x03, 0x01, 0x00, 0x5a, 0x00, 0x19, 0x00, 0x0c, 0x00, - 0x3e, 0x02, 0x23, 0x23, 0x27, 0x00, 0x02, 0x03, 0x01, 0x00, 0x5a, 0x00, 0x1d, 0x00, 0x0c, 0x00, 0x3f, 0x02, 0x23, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5b, 0x00, 0x15, 0x01, 0x08, 0x00, 0x3f, 0x02, 0x24, 0x29, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5b, 0x00, 0x15, 0x02, 0x08, 0x00, 0x40, 0x02, 0x23, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xe6, 0x00, 0x1d, 0x01, 0x08, 0x00, - 0x40, 0x02, 0x23, 0x29, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xe6, 0x00, 0x1d, 0x02, 0x08, 0x00, 0x41, 0x02, 0x23, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5b, 0x00, 0x11, 0x01, 0x08, 0x00, 0x41, 0x02, 0x24, 0x29, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x5b, 0x00, 0x11, 0x02, 0x08, 0x00, 0x42, 0x02, 0x23, 0x27, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xe6, 0x00, 0x19, 0x01, 0x08, 0x00, - 0x42, 0x02, 0x24, 0x28, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xe6, 0x00, 0x19, 0x02, 0x08, 0x00, 0x43, 0x02, 0x03, 0x26, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2d, 0x00, 0x19, 0x00, 0x08, 0x00, 0x43, 0x02, 0x04, 0x26, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2d, 0x00, 0x99, 0x00, 0x08, 0x00, 0x44, 0x02, 0x03, 0x27, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2d, 0x00, 0x1d, 0x00, 0x08, 0x00, - 0x44, 0x02, 0x04, 0x27, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x2d, 0x00, 0x9d, 0x00, 0x08, 0x00, 0x45, 0x02, 0x23, 0x23, 0x07, 0x00, 0x02, 0x03, 0x01, 0x00, 0x2a, 0x00, 0x19, 0x00, 0x0c, 0x00, 0x45, 0x02, 0x23, 0x23, 0x08, 0x00, 0x02, 0x03, 0x01, 0x00, 0x2a, 0x00, 0x99, 0x00, 0x0c, 0x00, 0x46, 0x02, 0x23, 0x23, 0x07, 0x00, 0x02, 0x03, 0x01, 0x00, 0x2a, 0x00, 0x1d, 0x00, 0x0c, 0x00, - 0x46, 0x02, 0x23, 0x23, 0x08, 0x00, 0x02, 0x03, 0x01, 0x00, 0x2a, 0x00, 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0x00, 0xa7, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x00, 0x08, 0x00, + 0xa7, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa8, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa8, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa8, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x08, 0x05, 0x00, + 0xa9, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa9, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa9, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, }; From c70f717211fc039941d8638f1e5dffed4bf22f45 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 14:21:21 +0100 Subject: [PATCH 24/92] Correct `check_asm_operand_size_class` for scalar floats in vector register slots --- src/check_asm.cpp | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index d6624ed44..e34cde6d7 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -110,9 +110,29 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: } // Width check (only when the slot pins a width and we could size the type). - if (want_w != 0 && got_w != 0 && want_w != got_w) { - if (mismatch_) *mismatch_ = AsmMismatch_Size; - return false; + if (want_w != 0 && got_w != 0) { + if (want_class == AsmRegClass_Vector) { + // XMM/YMM/ZMM slot. A scalar float (f32/f64) uses only the low lane, so + // it is valid in any vector-register slot as long as it fits. A #simd + // vector, by contrast, must match the register width exactly (a 128-bit + // vector is not a ymm, a 256-bit vector is not an xmm). + bool width_ok = false; + if (got_class == AsmRegClass_Float) { + width_ok = (got_w <= want_w); // scalar in low lane + } else { + width_ok = (got_w == want_w); // #simd must be exact + } + if (!width_ok) { + if (mismatch_) *mismatch_ = AsmMismatch_Size; + return false; + } + } else { + // GPR / mask / memory-sized slot: exact width. + if (want_w != got_w) { + if (mismatch_) *mismatch_ = AsmMismatch_Size; + return false; + } + } } return true; } From ce6346a20ff2eec8422208481d552a9bcdc6acf6 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 14:52:21 +0100 Subject: [PATCH 25/92] Check immediates if they support the range or are not allowed (e.g. floats) --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 8 +- src/asm_tables_amd64.cpp | 8 +- src/check_asm.cpp | 129 ++++++++++++++---- src/llvm_backend_asm.cpp | 4 + 4 files changed, 124 insertions(+), 25 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index a005a4258..7e30180d3 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -361,8 +361,14 @@ main :: proc() { strings.write_string(&sb, "\t\tcase OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128;\n") strings.write_string(&sb, "\t\tcase OP_M256: case OP_YMM: case OP_YMM_M256: return 256;\n") strings.write_string(&sb, "\t\tcase OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512;\n") + strings.write_string(&sb, "\t\tcase OP_IMM8: return 8;\n") + strings.write_string(&sb, "\t\tcase OP_IMM16: return 16;\n") + strings.write_string(&sb, "\t\tcase OP_IMM32: return 32;\n") + strings.write_string(&sb, "\t\tcase OP_IMM64: return 64;\n") + strings.write_string(&sb, "\t\tcase OP_REL8: return 8;\n") + strings.write_string(&sb, "\t\tcase OP_REL32: return 32;\n") strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc.\n") + strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc.\n") strings.write_string(&sb, "\t}\n") } strings.write_string(&sb, "\n") diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 7db8b9b4d..6abc829b1 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -380,8 +380,14 @@ struct Asm_amd64 { case OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128; case OP_M256: case OP_YMM: case OP_YMM_M256: return 256; case OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512; + case OP_IMM8: return 8; + case OP_IMM16: return 16; + case OP_IMM32: return 32; + case OP_IMM64: return 64; + case OP_REL8: return 8; + case OP_REL32: return 32; } - return 0; // OP_M (sizeless), OP_IMM*, OP_REL*, OP_K (opmask width is data-dependent), etc. + return 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc. } int form_explicit_slot(Encoding const &form, int explicit_index) { diff --git a/src/check_asm.cpp b/src/check_asm.cpp index e34cde6d7..fcbd7e583 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -55,10 +55,73 @@ gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { enum AsmMismatch : u8 { AsmMismatch_None, - AsmMismatch_Size, - AsmMismatch_Class, + AsmMismatch_Size, // register / vector width mismatch + AsmMismatch_Class, // register class mismatch + AsmMismatch_ImmRange, // constant immediate does not fit the slot width + AsmMismatch_ImmType, // non-integer constant where an integer immediate is required }; +// Does a constant immediate value fit a slot of `bits` width (0 == unconstrained)? +// Accepts either a signed or an unsigned interpretation of the bit pattern, which +// matches how the assembler treats imm fields (e.g. both 200 and -56 fit imm8). +gb_internal bool check_asm_immediate_value_fits(ExactValue ev, i32 bits, i32 *needed_, AsmMismatch *mismatch_) { + if (ev.kind == ExactValue_Float) { + // Try to convert it if possible to an integer + ev = exact_value_to_integer(ev); + } + + switch (ev.kind) { + case ExactValue_Bool: + // Encodes as 0 or 1; fits any immediate slot with a non-zero width. + if (needed_) *needed_ = 1; + return true; + + case ExactValue_Integer: { + mp_int const *v = &ev.value_integer; + i32 mag_bits = cast(i32)mp_count_bits(v); + if (needed_) *needed_ = mag_bits; + + if (bits == 0) { + // TODO(bill): is this a decent width?! + bits = 64; // slot does not pin a width, just set a decent default + } + if (mp_iszero(v)) { + return true; + } + if (!mp_isneg(v)) { + // Non-negative: fits if the unsigned bit pattern is <= `bits` wide. + if (mag_bits <= bits) { + return true; + } + } else { + // Negative: fits signed in `bits` iff mp_count_bits(-v - 1) <= bits-1. + // (-v-1 ranges 0 .. 2^(bits-1)-1 for the representable negatives.) + mp_int tmp = {}; + mp_init(&tmp); + defer (mp_clear(&tmp)); + mp_neg(v, &tmp); // tmp = -v (positive magnitude) + mp_sub_d(&tmp, 1, &tmp); // tmp = -v - 1 + i32 nb = cast(i32)mp_count_bits(&tmp); + if (needed_) *needed_ = nb + 1; // signed bit-width, for the diagnostic + if (nb <= bits-1) { + return true; + } + } + if (mismatch_) *mismatch_ = AsmMismatch_ImmRange; + return false; + } + + case ExactValue_Float: + // TODO(bill): does any architecture support floating-point immediates? + // amd64 has no floating-point instruction immediates. + if (needed_) *needed_ = 0; + if (mismatch_) *mismatch_ = AsmMismatch_ImmType; + return false; + } + if (mismatch_) *mismatch_ = AsmMismatch_ImmType; + return false; +} + // Returns true if the operand's Odin type is size/class-compatible with the form's slot. // On mismatch, fills *mismatch_ for a precise diagnostic. `slot` here is the // resolved OperandType at the correct (implicit-skipped) slot. @@ -66,11 +129,26 @@ template gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx::OperandType slot, Operand const *operand, AsmMismatch *mismatch_, i32 *want_bits_, i32 *got_bits_) { if (mismatch_) *mismatch_ = AsmMismatch_None; - // Only register/memory-sized slots constrain width & class. Immediates/labels/sizeless-mem: skip here. + + AsmOperandKind slot_kind = asm_ctx->kind_from_operand_type(slot); + if (slot_kind == AsmOperand_Immediate) { + i32 want_w = asm_ctx->operand_type_bit_width(slot); // 32 for OP_IMM32 + if (want_bits_) *want_bits_ = want_w; + if (operand->mode != Addressing_Constant) { + return true; // $-immediate, bound per instantiation; defer + } + i32 needed = 0; + ExactValue ev = operand->value; + bool ok = check_asm_immediate_value_fits(ev, want_w, &needed, mismatch_); + if (got_bits_) *got_bits_ = needed; + return ok; + } + + // Register / memory-sized slots AsmRegClass want_class = asm_ctx->operand_type_reg_class(slot); i32 want_w = asm_ctx->operand_type_bit_width(slot); - // A pure-immediate or label slot imposes no reg width/class; value-range is checked elsewhere. + // A pure-label / sizeless slot imposes no reg width/class. if (want_class == AsmRegClass_Unknown && want_w == 0) { return true; } @@ -78,8 +156,15 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: AsmRegClass got_class = check_asm_reg_class_from_type(operand->type); i32 got_w = check_asm_operand_bit_width(operand->type); if (got_w < 0) { - // TODO(bill): determine the correct width from the untyped constant value - got_w = want_w; + // Untyped constant: width is a property of the value, not the type. + if (operand->mode == Addressing_Constant && operand->value.kind == ExactValue_Integer) { + got_w = cast(i32)mp_count_bits(&operand->value.value_integer); + if (got_w == 0) { + got_w = 1; // zero still occupies a slot + } + } else { + got_w = 0; // unknown; skip the width comparison rather than fake a pass + } } if (want_bits_) *want_bits_ = want_w; if (got_bits_) *got_bits_ = got_w; @@ -92,7 +177,6 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: class_ok = (got_class == AsmRegClass_Integer); break; case AsmRegClass_Vector: - // XMM/YMM/ZMM slots accept both scalar float and #simd vector operands. class_ok = (got_class == AsmRegClass_Vector || got_class == AsmRegClass_Float); break; case AsmRegClass_Mask: @@ -102,32 +186,23 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: class_ok = true; break; } - if (!class_ok) { if (mismatch_) *mismatch_ = AsmMismatch_Class; return false; } } - // Width check (only when the slot pins a width and we could size the type). + // Width check. if (want_w != 0 && got_w != 0) { if (want_class == AsmRegClass_Vector) { - // XMM/YMM/ZMM slot. A scalar float (f32/f64) uses only the low lane, so - // it is valid in any vector-register slot as long as it fits. A #simd - // vector, by contrast, must match the register width exactly (a 128-bit - // vector is not a ymm, a 256-bit vector is not an xmm). - bool width_ok = false; - if (got_class == AsmRegClass_Float) { - width_ok = (got_w <= want_w); // scalar in low lane - } else { - width_ok = (got_w == want_w); // #simd must be exact - } + // A scalar float uses only the low lane, so it is valid in any vector + // register slot as long as it fits; a #simd vector must match exactly. + bool width_ok = (got_class == AsmRegClass_Float) ? (got_w <= want_w) : (got_w == want_w); if (!width_ok) { if (mismatch_) *mismatch_ = AsmMismatch_Size; return false; } } else { - // GPR / mask / memory-sized slot: exact width. if (want_w != got_w) { if (mismatch_) *mismatch_ = AsmMismatch_Size; return false; @@ -137,7 +212,6 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: return true; } - gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { Type *tuple = alloc_type_tuple(); if (_params == nullptr) { @@ -644,8 +718,17 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; - if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { - // dst kind was right, width was wrong + if (m == AsmMismatch_ImmRange) { + gbString vs = exact_value_to_string(operands[i].value); + error(operands[i].expr, + "Operand %td of '%.*s': immediate value %s does not fit in a %d-bit immediate", + i, LIT(name), vs, cast(int)want_bits[i]); + gb_string_free(vs); + } else if (m == AsmMismatch_ImmType) { + error(operands[i].expr, + "Operand %td of '%.*s': a floating-point constant cannot be used as an immediate", + i, LIT(name)); + } else if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { error(operands[i].expr, "Operand %td of '%.*s' has the wrong size: expected a %u-bit operand, got %u-bit", i, LIT(name), cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 24a6daef9..eae026648 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -49,6 +49,7 @@ struct lbAsmGenerate { case_end; case_ast_node(bl, BasicLit, op); + op->tav.value = exact_value_to_integer(op->tav.value); ExactValue ev = op->tav.value; GB_ASSERT(ev.kind != ExactValue_Invalid); switch (ev.kind) { @@ -61,6 +62,9 @@ struct lbAsmGenerate { gb_free(heap_allocator(), s.text); break; } + case ExactValue_Float: + error(op, "Floating-point literals that cannot be represented as an integer are not supported within asm operands"); + break; default: GB_PANIC("Unsupported asm immediate literal %s", expr_to_string(op)); break; From cd6b8a9ddb9fa0f34749478f5f742d21e2e84c49 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 14:59:14 +0100 Subject: [PATCH 26/92] Improve error messages when passing an immediate that does not fit the expect range. --- src/check_asm.cpp | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index fcbd7e583..81c42c862 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -633,20 +633,21 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst bool spot_ok = false; if (kind_ok) { - spot_ok = true; if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory) { - // No need to do an extra size class check, it accepts memory + spot_ok = true; // memory form accepts memory; skip size check } else { spot_ok = check_asm_operand_size_class(asm_ctx, type, operand, nullptr, nullptr, nullptr); } } if (spot_ok) { - score += 1; + score += 2; // full match valid_spots[i] = true; + } else if (kind_ok) { + score += 1; // kind matched, only value/size/class failed -> better near-miss } } - if (score == operands.count) { + if (score == operands.count*2) { // the result has been found to be correct matched = true; valid_form_index = form_index; @@ -708,7 +709,11 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst } { - error(instr->name, "The operands to '%.*s' matched none of the expected encoding forms", LIT(name)); + if (best_score == operands.count*2 - 1) { + error(instr->name, "Asm operands to '%.*s' nearly matched the expected encoding forms", LIT(name)); + } else { + error(instr->name, "Asm operands to '%.*s' matched none of the expected encoding forms", LIT(name)); + } for_array(i, valid_spots) { if (valid_spots[i] || i >= operands.count) { continue; @@ -721,7 +726,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst if (m == AsmMismatch_ImmRange) { gbString vs = exact_value_to_string(operands[i].value); error(operands[i].expr, - "Operand %td of '%.*s': immediate value %s does not fit in a %d-bit immediate", + "Operand %td of '%.*s' is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", i, LIT(name), vs, cast(int)want_bits[i]); gb_string_free(vs); } else if (m == AsmMismatch_ImmType) { From 5621cbc85a1ef038dde9a2bb80a93805eee5b4de Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 15:06:14 +0100 Subject: [PATCH 27/92] Improve scoring for operand error handling --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 1 + src/asm_tables_amd64.cpp | 1 + src/check_asm.cpp | 53 +++++++++++++++---- 3 files changed, 44 insertions(+), 11 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 7e30180d3..c658df2ca 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -367,6 +367,7 @@ main :: proc() { strings.write_string(&sb, "\t\tcase OP_IMM64: return 64;\n") strings.write_string(&sb, "\t\tcase OP_REL8: return 8;\n") strings.write_string(&sb, "\t\tcase OP_REL32: return 32;\n") + strings.write_string(&sb, "\t\tcase OP_IMM8SX: return 8;\n") strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc.\n") strings.write_string(&sb, "\t}\n") diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 6abc829b1..1a451c124 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -386,6 +386,7 @@ struct Asm_amd64 { case OP_IMM64: return 64; case OP_REL8: return 8; case OP_REL32: return 32; + case OP_IMM8SX: return 8; } return 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc. } diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 81c42c862..6a6fddb24 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -133,6 +133,9 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: AsmOperandKind slot_kind = asm_ctx->kind_from_operand_type(slot); if (slot_kind == AsmOperand_Immediate) { i32 want_w = asm_ctx->operand_type_bit_width(slot); // 32 for OP_IMM32 + if (want_w == 0) { + GB_PANIC("HERE: %d", slot); + } if (want_bits_) *want_bits_ = want_w; if (operand->mode != Addressing_Constant) { return true; // $-immediate, bound per instantiation; defer @@ -609,10 +612,13 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst auto possible_kinds = slice_make(heap_allocator(), max_count); defer (slice_free(&possible_kinds, heap_allocator())); - bool matched = false; + bool matched = false; isize valid_form_index = -1; - isize best_form = -1; + + isize best_form = -1; int best_score = -1; + int best_dist = I32_MAX; // secondary: prefer smaller width distance + int best_pref = -1; // tertiary: prefer wider slots (r64 over r32) for_array(form_index, forms) { auto &form = forms[form_index]; @@ -620,7 +626,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst continue; } - int score = 0; + int score = 0; + int width_dist = 0; + int width_pref = 0; + for_array(i, operands) { int slot = asm_ctx->form_explicit_slot(form, cast(int)i); auto type = (slot >= 0) ? form.ops[slot] : asm_ctx->OP_NONE; @@ -631,31 +640,53 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst bool kind_ok = (dst == src) || (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); + // Tertiary key: bias toward wider register slots so an r64 form outranks + // an otherwise-equal r32 form. + width_pref += cast(int)asm_ctx->operand_type_bit_width(type); + bool spot_ok = false; if (kind_ok) { if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory) { - spot_ok = true; // memory form accepts memory; skip size check + spot_ok = true; // memory form accepts memory; no size check } else { - spot_ok = check_asm_operand_size_class(asm_ctx, type, operand, nullptr, nullptr, nullptr); + AsmMismatch m = AsmMismatch_None; + i32 wb_ = 0, gb_ = 0; + spot_ok = check_asm_operand_size_class(asm_ctx, type, operand, &m, &wb_, &gb_); + if (!spot_ok && (m == AsmMismatch_Size || m == AsmMismatch_ImmRange) && wb_ > 0 && gb_ > 0) { + int d = cast(int)wb_ - cast(int)gb_; + width_dist += (d < 0) ? -d : d; + } } } if (spot_ok) { - score += 2; // full match + score += 2; valid_spots[i] = true; } else if (kind_ok) { - score += 1; // kind matched, only value/size/class failed -> better near-miss + score += 1; // kind matched, only value/size/class failed } } - if (score == operands.count*2) { - // the result has been found to be correct + + if (score == operands.count * 2) { matched = true; valid_form_index = form_index; break; } - if (score > best_score) { + + // Lexicographic rank: score desc, then width_dist asc, then width_pref desc. + bool better; + if (score != best_score) { + better = score > best_score; + } else if (width_dist != best_dist) { + better = width_dist < best_dist; + } else { + better = width_pref > best_pref; + } + if (better) { best_score = score; - best_form = form_index; + best_dist = width_dist; + best_pref = width_pref; + best_form = form_index; } } From a76664ed2aa2246d5c84384381d366a718f2296f Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 15:12:00 +0100 Subject: [PATCH 28/92] Improve error messages for immediate values and explain how far out they are in terms of bits too. --- src/check_asm.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 6a6fddb24..12bdc5f56 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -755,10 +755,19 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; if (m == AsmMismatch_ImmRange) { - gbString vs = exact_value_to_string(operands[i].value); - error(operands[i].expr, - "Operand %td of '%.*s' is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", - i, LIT(name), vs, cast(int)want_bits[i]); + ExactValue ev = operands[i].value; + gbString vs = exact_value_to_string(ev); + i32 bits_required = 0; + check_asm_immediate_value_fits(ev, want_bits[i], &bits_required, nullptr); + if (bits_required > 0) { + error(operands[i].expr, + "Operand %td of '%.*s' is a %d-bit immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + i, LIT(name), bits_required, vs, cast(int)want_bits[i]); + } else { + error(operands[i].expr, + "Operand %td of '%.*s' is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + i, LIT(name), vs, cast(int)want_bits[i]); + } gb_string_free(vs); } else if (m == AsmMismatch_ImmType) { error(operands[i].expr, From 6a20d213589a2e8bfbe93e85f8b6303b3fc8e1e0 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 16:00:03 +0100 Subject: [PATCH 29/92] Add extra checks for asm memory operand scale in frontend and backend --- src/check_asm.cpp | 52 +++++++++++++++++++++------------------- src/llvm_backend_asm.cpp | 40 +++++++++++++++++++++++-------- 2 files changed, 58 insertions(+), 34 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 12bdc5f56..070da2ba6 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -740,10 +740,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst } { - if (best_score == operands.count*2 - 1) { - error(instr->name, "Asm operands to '%.*s' nearly matched the expected encoding forms", LIT(name)); + if (best_score >= gb_max(operands.count*2 - 2, 0)) { + error(instr->name, "'%.*s' operands nearly matched the expected encoding forms", LIT(name)); } else { - error(instr->name, "Asm operands to '%.*s' matched none of the expected encoding forms", LIT(name)); + error(instr->name, "'%.*s' operands matched none of the expected encoding forms", LIT(name)); } for_array(i, valid_spots) { if (valid_spots[i] || i >= operands.count) { @@ -760,33 +760,27 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst i32 bits_required = 0; check_asm_immediate_value_fits(ev, want_bits[i], &bits_required, nullptr); if (bits_required > 0) { - error(operands[i].expr, - "Operand %td of '%.*s' is a %d-bit immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", - i, LIT(name), bits_required, vs, cast(int)want_bits[i]); + error(operands[i].expr, "'%.*s' operand-%td is a %d-bit immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + LIT(name), i, bits_required, vs, cast(int)want_bits[i]); } else { - error(operands[i].expr, - "Operand %td of '%.*s' is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", - i, LIT(name), vs, cast(int)want_bits[i]); + error(operands[i].expr, "'%.*s' operand-%td is an immediate value, but the value %s does not fit in the %d-bit immediate this form encodes", + LIT(name), i, vs, cast(int)want_bits[i]); } gb_string_free(vs); } else if (m == AsmMismatch_ImmType) { - error(operands[i].expr, - "Operand %td of '%.*s': a floating-point constant cannot be used as an immediate", - i, LIT(name)); + error(operands[i].expr, "'%.*s'' operand-%td a floating-point constant cannot be used as an immediate", + LIT(name), i); } else if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { - error(operands[i].expr, - "Operand %td of '%.*s' has the wrong size: expected a %u-bit operand, got %u-bit", - i, LIT(name), cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); + error(operands[i].expr, "'%.*s' operand-%td has the wrong size: expected a %u-bit operand, got %u-bit", + LIT(name), i, cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); } else if (m == AsmMismatch_Class) { - error(operands[i].expr, - "Operand %td of '%.*s' is in the wrong register class, expected %.*s operand, got %.*s", - i, LIT(name), LIT(asm_operand_kind_expected_strings[dst]), LIT(asm_operand_kind_expected_strings[src])); + error(operands[i].expr, "'%.*s' operand-%td is in the wrong register class, expected %.*s operand, got %.*s", + LIT(name), i, LIT(asm_operand_kind_expected_strings[dst]), LIT(asm_operand_kind_expected_strings[src])); } else if (dst) { - error(operands[i].expr, - "Operand %td of '%.*s' has an invalid kind, expected %.*s operand", - i, LIT(name), LIT(asm_operand_kind_expected_strings[dst])); + error(operands[i].expr, "'%.*s' operand-%td has an invalid kind, expected %.*s operand", + LIT(name), i, LIT(asm_operand_kind_expected_strings[dst])); } else { - error(operands[i].expr, "Operand %td of '%.*s' has an invalid kind", i, LIT(name)); + error(operands[i].expr, "'%.*s' operand-%td has an invalid kind", LIT(name), i); } } } @@ -905,11 +899,21 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * break; } if (scale.mode == Addressing_Constant) { + gbString s = exact_value_to_string(scale.value); + defer (gb_string_free(s)); if (scale.value.kind != ExactValue_Integer) { - gbString s = exact_value_to_string(scale.value); error(scale.expr, "A scale must be a constant integer or an immediate, got %s", s); - gb_string_free(s); break; + } else { + i64 v = exact_value_to_i64(scale.value); + switch (v) { + case 1: case 2: case 4: case 8: + // okay + break; + default: + error(scale.expr, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %s", s); + break; + } } } else { Entity *param_entity = entity_of_node(scale.expr); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index eae026648..3ba6c5cd3 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -3,6 +3,14 @@ struct lbAsmGenerate { AstAsmTemplate * tmpl_node; Array *ops; + enum WriteOperandFlags : u32 { + WriteOperandFlag_PrintPrefixes = 1<<0, + WriteOperandFlag_IsScale = 1<<1, + + WriteOperandFlag_NONE = 0, + WriteOperandFlag_DEFAULT = WriteOperandFlag_PrintPrefixes, + }; + void init(Entity *entity) { this->tmpl_entity = entity; GB_ASSERT(this->tmpl_entity != nullptr); @@ -34,7 +42,7 @@ struct lbAsmGenerate { return nullptr; } - gbString write_operand(gbString asm_string, Array op_number, Ast *op, bool print_prefixes=true) { + gbString write_operand(gbString asm_string, Array op_number, Ast *op, u32 flags) { switch (op->kind) { case_ast_node(i, Ident, op); Entity *e = entity_of_node(op); @@ -45,7 +53,7 @@ struct lbAsmGenerate { asm_string = gb_string_append_fmt(asm_string, "$%d", idx); case_end; case_ast_node(mem_op, AsmMemoryOperand, op); - asm_string = this->write_memory_operand(asm_string, op_number, mem_op, false); + asm_string = this->write_memory_operand(asm_string, op_number, mem_op, flags&~WriteOperandFlag_PrintPrefixes); case_end; case_ast_node(bl, BasicLit, op); @@ -55,11 +63,23 @@ struct lbAsmGenerate { switch (ev.kind) { case ExactValue_Integer: { String s = big_int_to_string(heap_allocator(), &ev.value_integer, 10); - if (print_prefixes) { + if (flags & WriteOperandFlag_PrintPrefixes) { asm_string = gb_string_appendc(asm_string, "$$"); } asm_string = gb_string_append_length(asm_string, s.text, s.len); gb_free(heap_allocator(), s.text); + + if (flags & WriteOperandFlag_IsScale) { + i64 val = exact_value_to_i64(ev); + switch (val) { + case 1: case 2: case 4: case 8: + // okay + break; + default: + error(op, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %.*s", LIT(s)); + break; + } + } break; } case ExactValue_Float: @@ -100,24 +120,24 @@ struct lbAsmGenerate { }; - virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, bool print_prefixes=true) = 0; + virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; }; struct lbAsmGenerate_amd64 : lbAsmGenerate { - gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, bool print_prefixes=true) override { + gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { if (mem_op->disp) { - asm_string = this->write_operand(asm_string, op_number, mem_op->disp, /*print_prefixes*/false); + asm_string = this->write_operand(asm_string, op_number, mem_op->disp, flags&~WriteOperandFlag_PrintPrefixes); } asm_string = gb_string_appendc(asm_string, "("); GB_ASSERT(mem_op->base != nullptr); - asm_string = this->write_operand(asm_string, op_number, mem_op->base); + asm_string = this->write_operand(asm_string, op_number, mem_op->base, flags); if (mem_op->index) { asm_string = gb_string_appendc(asm_string, ","); - asm_string = this->write_operand(asm_string, op_number, mem_op->index); + asm_string = this->write_operand(asm_string, op_number, mem_op->index, flags); if (mem_op->scale) { asm_string = gb_string_appendc(asm_string, ","); - asm_string = this->write_operand(asm_string, op_number, mem_op->scale, /*print_prefixes*/false); + asm_string = this->write_operand(asm_string, op_number, mem_op->scale, (flags|WriteOperandFlag_IsScale)&~WriteOperandFlag_PrintPrefixes); } } asm_string = gb_string_appendc(asm_string, ")"); @@ -273,7 +293,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { if (j < instr->operands.count-1) { asm_string = gb_string_appendc(asm_string, ", "); } - asm_string = this->write_operand(asm_string, op_number, op); + asm_string = this->write_operand(asm_string, op_number, op, WriteOperandFlag_DEFAULT); } case_end; case_ast_node(label, AsmLabelDecl, instr_); From e31bacd66462e12593802176369af55eea3ff086 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 16:37:55 +0100 Subject: [PATCH 30/92] Check memory operand parameters better --- src/check_asm.cpp | 205 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 145 insertions(+), 60 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 070da2ba6..cbeba1268 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -133,9 +133,6 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: AsmOperandKind slot_kind = asm_ctx->kind_from_operand_type(slot); if (slot_kind == AsmOperand_Immediate) { i32 want_w = asm_ctx->operand_type_bit_width(slot); // 32 for OP_IMM32 - if (want_w == 0) { - GB_PANIC("HERE: %d", slot); - } if (want_bits_) *want_bits_ = want_w; if (operand->mode != Addressing_Constant) { return true; // $-immediate, bound per instantiation; defer @@ -215,6 +212,47 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: return true; } + +enum AsmAddrRole { + AsmAddr_Base, + AsmAddr_Index, +}; + +// Validate that a resolved base/index operand is a 32- or 64-bit integer register. +// `reg_name` is the literal register string when the operand was an AstAsmRegister +// (so rsp/esp-as-index can be caught), else the empty string. +gb_internal bool check_asm_addr_register(Operand const *operand, AsmAddrRole role, String reg_name, i32 *width_) { + char const *role_name = (role == AsmAddr_Base) ? "base" : "index"; + + AsmRegClass cls = check_asm_reg_class_from_type(operand->type); + i32 w = check_asm_operand_bit_width(operand->type); + if (width_) *width_ = w; + + if (cls != AsmRegClass_Integer) { + char const *got = "non-integer"; + if (cls == AsmRegClass_Vector) { + got = "vector"; + } else if (cls == AsmRegClass_Mask) { + got = "mask"; + } + error(operand->expr, "A memory operand's %s must be an integer register, got a %s value", role_name, got); + return false; + } + if (w != 32 && w != 64) { + error(operand->expr, "A memory operand's %s must be a 32-bit or 64-bit register, got a %d-bit register", role_name, cast(int)w); + return false; + } + if (role == AsmAddr_Index && reg_name.len != 0) { + // rsp/esp cannot be encoded as an index register. + if (reg_name == "rsp" || reg_name == "esp") { + error(operand->expr, "%%%.*s cannot be used as an index register", LIT(reg_name)); + return false; + } + } + return true; +} + + gb_internal Type *check_asm_template_signature_params(CheckerContext *ctx, Scope *scope, Ast *_params, bool input_parameters, Array *asm_template_entity_decls) { Type *tuple = alloc_type_tuple(); if (_params == nullptr) { @@ -375,7 +413,7 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice Type *type = check_type(ctx, spec->type); if (!is_valid_asm_parameter_type(type)) { gbString s = type_to_string(type); - error(spec->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", type); + error(spec->type, "Invalid type for an asm template. It must be an integer, float, boolean, pointer, multi-pointer, or #simd vector, got '%s'", s); gb_string_free(s); continue; } @@ -768,7 +806,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst } gb_string_free(vs); } else if (m == AsmMismatch_ImmType) { - error(operands[i].expr, "'%.*s'' operand-%td a floating-point constant cannot be used as an immediate", + error(operands[i].expr, "'%.*s' operand-%td: a floating-point constant cannot be used as an immediate", LIT(name), i); } else if (m == AsmMismatch_Size && want_bits[i] && got_bits[i]) { error(operands[i].expr, "'%.*s' operand-%td has the wrong size: expected a %u-bit operand, got %u-bit", @@ -842,55 +880,92 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * check_asm_instruction_operand(asm_ctx, ctx, entity, &scale, mem_op->scale, false); check_asm_instruction_operand(asm_ctx, ctx, entity, &disp, mem_op->disp, false); - for (int i = 0; base.expr && i == 0; i++) { + i32 base_w = 0; + i32 index_w = 0; + bool have_base = false; + bool have_index = false; + + // base: must resolve to a 32/64-bit integer register + if (base.expr) { + String reg_name = {}; + bool ok_kind = true; if (base.expr->kind == Ast_AsmRegister) { - check_register(asm_ctx, &base, &base.expr->AsmRegister); + reg_name = base.expr->AsmRegister.name.string; + ok_kind = check_register(asm_ctx, &base, &base.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(base.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { gbString s = expr_to_string(base.expr); - error(base.expr, "A base value must be a memory parameter, got %s", s); + error(base.expr, "A base value must be a register parameter, got %s", s); gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - if (kind != AsmTemplateEntityDecl_Memory) { - gbString s = expr_to_string(base.expr); - error(base.expr, "A base value must be a memory parameter, got %s", s); - gb_string_free(s); - break; + ok_kind = false; + } else { + auto kind = check_asm_find_kind(param_entity, ate->decls); + // A pointer/integer parameter used as an address base lowers to a + // register operand, so accept both Register and Memory kinds here. + if (kind != AsmTemplateEntityDecl_Register && kind != AsmTemplateEntityDecl_Memory) { + gbString s = expr_to_string(base.expr); + error(base.expr, "A base value must be a register parameter, got %s", s); + gb_string_free(s); + ok_kind = false; + } } } + if (ok_kind) { + have_base = check_asm_addr_register(&base, AsmAddr_Base, reg_name, &base_w); + } } - for (int i = 0; index.expr && i == 0; i++) { + // index: must resolve to a 32/64-bit integer register, and not rsp/esp + if (index.expr) { + String reg_name = {}; + bool ok_kind = true; if (index.expr->kind == Ast_AsmRegister) { - check_register(asm_ctx, &index, &index.expr->AsmRegister); + reg_name = index.expr->AsmRegister.name.string; + ok_kind = check_register(asm_ctx, &index, &index.expr->AsmRegister); } else { Entity *param_entity = entity_of_node(index.expr); if (param_entity == nullptr || param_entity->kind != Entity_Variable) { gbString s = expr_to_string(index.expr); - error(index.expr, "An index value must an integer, got %s", s); + error(index.expr, "An index value must be an integer register, got %s", s); gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - switch (kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Immediate: - // okay: - break; - default: - { - gbString s = expr_to_string(index.expr); - error(index.expr, "An index must be an integer value, got %s", s); - gb_string_free(s); + ok_kind = false; + } else { + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + // okay + break; + default: + { + gbString s = expr_to_string(index.expr); + error(index.expr, "An index must be an integer register, got %s", s); + gb_string_free(s); + ok_kind = false; + } + break; } - break; } } + if (ok_kind) { + have_index = check_asm_addr_register(&index, AsmAddr_Index, reg_name, &index_w); + } } + // base and index must be the same width + if (have_base && have_index && base_w != index_w) { + Ast *at = mem_op->base ? mem_op->base : expr; + error(at, "A memory operand's base and index registers must be the same width, got a %d-bit base and a %d-bit index", + cast(int)base_w, cast(int)index_w); + } + + // a scale factor is meaningless without an index + if (scale.expr && !index.expr) { + error(scale.expr, "A scale factor requires an index register"); + } + + // scale: constant 1/2/4/8, or an immediate parameter for (int i = 0; scale.expr && i == 0; i++) { if (!is_type_integer(scale.type)) { gbString s = expr_to_string(scale.expr); @@ -933,40 +1008,50 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * } } + // displacement: an integer that fits a signed 32-bit value for (int i = 0; disp.expr && i == 0; i++) { if (disp.expr->kind == Ast_AsmRegister) { - check_register(asm_ctx, &disp, &disp.expr->AsmRegister); - } else { - Entity *param_entity = entity_of_node(disp.expr); - if (disp.mode == Addressing_Constant) { - if (is_type_integer(disp.type)) { - break; + error(disp.expr, "A displacement must be an integer value, got a register"); + break; + } + + Entity *param_entity = entity_of_node(disp.expr); + if (disp.mode == Addressing_Constant) { + if (disp.value.kind == ExactValue_Integer) { + AsmMismatch m = AsmMismatch_None; + i32 needed = 0; + if (!check_asm_immediate_value_fits(disp.value, 32, &needed, &m)) { + gbString vs = exact_value_to_string(disp.value); + error(disp.expr, "A memory displacement must fit in a signed 32-bit value, got %s (needs %d bits)", vs, cast(int)needed); + gb_string_free(vs); } + break; } - if (param_entity == nullptr) { + } + + if (param_entity == nullptr) { + gbString s = expr_to_string(disp.expr); + error(disp.expr, "A displacement value must be an integer, got %s", s); + gb_string_free(s); + break; + } + auto kind = check_asm_find_kind(param_entity, ate->decls); + switch (kind) { + case AsmTemplateEntityDecl_Register: + case AsmTemplateEntityDecl_Immediate: + if (is_type_integer(disp.type)) { + break; + } + /*fallthrough*/ + default: + { gbString s = expr_to_string(disp.expr); - error(disp.expr, "An displacement value must an integer, got %s", s); + gbString t = type_to_string(disp.type); + error(disp.expr, "A displacement must be an integer value, got %s of type %s", s, t); + gb_string_free(t); gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - switch (kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Immediate: - if (is_type_integer(disp.type)) { - break; - } - /*fallthrough*/ - default: - { - gbString s = expr_to_string(disp.expr); - gbString t = type_to_string(disp.type); - error(disp.expr, "An displacement must be an integer value, got %s of type %s", s, t); - gb_string_free(t); - gb_string_free(s); - } - break; } + break; } } From 21ad041232ec7766bb24f7777cb533c881ba3159 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 11 Aug 2026 17:44:55 +0100 Subject: [PATCH 31/92] Handle prefixes better --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 57 +++++++++++++++++++ src/asm_tables_amd64.cpp | 42 ++++++++++++++ src/check_asm.cpp | 48 ++++++++++++---- 3 files changed, 137 insertions(+), 10 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index c658df2ca..a5705dde6 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -82,6 +82,12 @@ main :: proc() { strings.write_string(&sb, "\tstatic String const mnemonic_strings[MNEMONIC_COUNT];\n") strings.write_string(&sb, "\tstatic String const prefix_strings[PREFIX_COUNT];\n") + { + strings.write_string(&sb, "\n"); + strings.write_string(&sb, "\tenum PrefixKind : u8 { PrefixKind_None, PrefixKind_Lock, PrefixKind_Rep, PrefixKind_Repne, PrefixKind_Other };\n"); + strings.write_string(&sb, "\n"); + } + { strings.write_string(&sb, "\n"); strings.write_string(&sb, "\t// Register classes (upper byte)\n") @@ -186,6 +192,18 @@ main :: proc() { fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) strings.write_string(&sb, " }\n") } + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "lock_ok") + strings.write_string(&sb, "\t\tbool lock_ok () const { ") + fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) + strings.write_string(&sb, " }\n") + } + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "rep_ok") + strings.write_string(&sb, "\t\tbool rep_ok () const { ") + fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) + strings.write_string(&sb, " }\n") + } } strings.write_string(&sb, "\n\n") { @@ -393,6 +411,45 @@ main :: proc() { strings.write_string(&sb, "\t}\n") } + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, "\tbool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) {\n") + strings.write_string(&sb, "\t\tPrefixKind kind = PrefixKind_None;\n") + strings.write_string(&sb, "\t\tif (prefix != 0) {\n") + strings.write_string(&sb, "\t\t\tswitch (prefix) {\n") + strings.write_string(&sb, "\t\t\tcase PREFIX_LOCK: kind = PrefixKind_Lock; break;\n") + strings.write_string(&sb, "\t\t\tcase PREFIX_REP: kind = PrefixKind_Rep; break;\n") + strings.write_string(&sb, "\t\t\tcase PREFIX_REPNE: kind = PrefixKind_Repne; break;\n") + strings.write_string(&sb, "\t\t\tdefault: kind = PrefixKind_Other; break;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\tswitch (kind) {\n") + strings.write_string(&sb, "\t\tcase PrefixKind_Lock:\n") + strings.write_string(&sb, "\t\t\tif (!form.lock_ok()) {\n") + strings.write_string(&sb, "\t\t\t\treturn false;\n") + strings.write_string(&sb, "\t\t\t} else {\n") + strings.write_string(&sb, "\t\t\t\tif (requires_memory_dest_) *requires_memory_dest_ = true;\n") + strings.write_string(&sb, "\t\t\t\treturn true;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\tcase PrefixKind_Rep:\n") + strings.write_string(&sb, "\t\t\tif (!form.rep_ok()) {\n") + strings.write_string(&sb, "\t\t\t\treturn false;\n") + strings.write_string(&sb, "\t\t\t} else {\n") + strings.write_string(&sb, "\t\t\t\treturn true;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\tcase PrefixKind_Repne:\n") + strings.write_string(&sb, "\t\t\tif (!form.rep_ok()) {\n") + strings.write_string(&sb, "\t\t\t\treturn false;\n") + strings.write_string(&sb, "\t\t\t} else {\n") + strings.write_string(&sb, "\t\t\t\treturn true;\n") + strings.write_string(&sb, "\t\t\t}\n") + strings.write_string(&sb, "\t\tcase PrefixKind_Other:\n") + strings.write_string(&sb, "\t\tcase PrefixKind_None:\n") + strings.write_string(&sb, "\t\t\treturn true;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\treturn true;\n") + strings.write_string(&sb, "\t}\n") + } strings.write_string(&sb, "};\n") diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 1a451c124..2a4e6010d 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -97,6 +97,9 @@ struct Asm_amd64 { static String const mnemonic_strings[MNEMONIC_COUNT]; static String const prefix_strings[PREFIX_COUNT]; + enum PrefixKind : u8 { PrefixKind_None, PrefixKind_Lock, PrefixKind_Rep, PrefixKind_Repne, PrefixKind_Other }; + + // Register classes (upper byte) static const u16 REG_CLASS_NONE = 0x000; static const u16 REG_CLASS_GPR64 = 0x100; @@ -232,6 +235,8 @@ struct Asm_amd64 { bool has_implicit () const { return ((flags>>21u)&1) != 0; } u8 explicit_count() const { return cast(u8)((flags>>18u)&((1u<<3)-1)); } u8 op_count () const { return cast(u8)((flags>>22u)&((1u<<3)-1)); } + bool lock_ok () const { return ((flags>>14u)&1) != 0; } + bool rep_ok () const { return ((flags>>15u)&1) != 0; } }; #pragma pack(pop) GB_STATIC_ASSERT(gb_size_of(Encoding) == 16); @@ -408,6 +413,43 @@ struct Asm_amd64 { } return -1; } + + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) { + PrefixKind kind = PrefixKind_None; + if (prefix != 0) { + switch (prefix) { + case PREFIX_LOCK: kind = PrefixKind_Lock; break; + case PREFIX_REP: kind = PrefixKind_Rep; break; + case PREFIX_REPNE: kind = PrefixKind_Repne; break; + default: kind = PrefixKind_Other; break; + } + } + switch (kind) { + case PrefixKind_Lock: + if (!form.lock_ok()) { + return false; + } else { + if (requires_memory_dest_) *requires_memory_dest_ = true; + return true; + } + case PrefixKind_Rep: + if (!form.rep_ok()) { + return false; + } else { + return true; + } + case PrefixKind_Repne: + if (!form.rep_ok()) { + return false; + } else { + return true; + } + case PrefixKind_Other: + case PrefixKind_None: + return true; + } + return true; + } }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index cbeba1268..add1757c1 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -627,7 +627,7 @@ gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { template -gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix) { +gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix, Ast *previous_prefix_instr) { GB_ASSERT(mnemonic > 0); auto forms = asm_ctx->encoding_forms(mnemonic); String name = asm_ctx->mnemonic_strings[mnemonic]; @@ -738,9 +738,19 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst } if (matched) { if (valid_form_index >= 0 && previous_prefix > 0) { - // TODO(bill): validate the prefix for the selected form - } + auto &form = forms[valid_form_index]; + bool requires_memory_dest = false; + bool ok = asm_ctx->prefix_kind_okay(previous_prefix, form, &requires_memory_dest); + if (ok) { + if (operands.count != 0 && determine_asm_operand_kind(&operands[0]) != AsmOperand_Memory) { + error(previous_prefix_instr ? previous_prefix_instr : instr->name, + "Asm prefix requires '%.*s' to have a memory destination operand", LIT(name)); + } + } else { + error(instr->name, "Asm prefix cannot be applied to '%.*s'", LIT(name)); + } + } return; } @@ -1182,9 +1192,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity array_reserve(&operands, 16); defer (array_free(&operands)); - for (Ast *instruction_ : at->instructions) { - u8 previous_prefix = 0; + u8 previous_prefix = 0; + Ast *previous_prefix_instr = nullptr; // for a good error location + for (Ast *instruction_ : at->instructions) { switch (instruction_->kind) { case_ast_node(instr, AsmInstruction, instruction_); GB_ASSERT(instr->name->kind == Ast_Ident); @@ -1192,30 +1203,47 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity u16 mnemonic = 0; CheckMnemomicResult res = check_mnemonic_name(asm_ctx, instr, &mnemonic); - array_clear(&operands); - for (Ast *expr : instr->operands) { Operand operand = {}; check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); array_add(&operands, operand); } + if (res == CheckMnemomic_Prefix) { if (instr->operands.count != 0) { error(instr->name, "A prefix must not have any operands, and be separate from the instruction it is prefixing"); } + if (previous_prefix != 0) { + error(instr->name, "A prefix cannot immediately follow another prefix"); + } previous_prefix = cast(u8)mnemonic; + previous_prefix_instr = instruction_; } else if (res == CheckMnemomic_Mnemonic) { - check_mnemonic(asm_ctx, ctx, instr, mnemonic, slice_from_array(operands), previous_prefix); + check_mnemonic(asm_ctx, ctx, instr, mnemonic, slice_from_array(operands), previous_prefix, previous_prefix_instr); + previous_prefix = 0; + previous_prefix_instr = nullptr; + } else { + // invalid mnemonic already reported; a pending prefix now has no target + previous_prefix = 0; + previous_prefix_instr = nullptr; } + case_end; - case_end; case_ast_node(label, AsmLabelDecl, instruction_); - // already done + if (previous_prefix != 0) { + error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but a label declaration was found"); + previous_prefix = 0; + previous_prefix_instr = nullptr; + } case_end; + default: error(instruction_, "Unexpected instruction in asm template"); break; } } + if (previous_prefix != 0) { + error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); + } } \ No newline at end of file From c80fedc070fc2a76225874c190cbefce419c2807 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 09:03:31 +0100 Subject: [PATCH 32/92] Support `[base + index<>scale]`; Support syntax for `[base]:u8` (not implemented yet) --- src/check_asm.cpp | 48 ++++++++++++++++++++++++++++++++++++---- src/llvm_backend_asm.cpp | 38 ++++++++++++++++++++++--------- src/parser.cpp | 27 ++++++++++++++++------ src/parser.hpp | 14 +++++++----- src/parser_pos.cpp | 3 +++ 5 files changed, 103 insertions(+), 27 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index add1757c1..d96c33885 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -991,14 +991,40 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * break; } else { i64 v = exact_value_to_i64(scale.value); - switch (v) { - case 1: case 2: case 4: case 8: - // okay + + Token op = mem_op->scale_op; + switch (op.kind) { + case Token_Mul: + switch (v) { + case 1: case 2: case 4: case 8: + // okay + break; + default: + error(scale.expr, "A scale using '*' must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %s", s); + break; + } + break; + case Token_Shl: + case Token_Shr: + switch (v) { + case 0: case 1: case 2: case 3: + // okay + break; + default: + error(scale.expr, "A shifting scale using '%.*s' must be a constant integer or an immediate with the value 0, 1, 2, or 3, got %s", LIT(op.string), s); + break; + } break; default: - error(scale.expr, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %s", s); + error(op, "Unknown/unhandled scaling operator '%.*s'", LIT(op.string)); break; } + + if (op.kind == Token_Shr) { + if (build_context.metrics.arch != TargetArch_arm64) { + error(op, "The target platform does not support '%.*s' for shifting scale parameters in memory operands", LIT(op.string)); + } + } } } else { Entity *param_entity = entity_of_node(scale.expr); @@ -1065,6 +1091,20 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * } } + if (mem_op->type) { + Type *type_interpretation = check_type(ctx, mem_op->type); + if (type_interpretation != nullptr && type_interpretation != t_invalid) { + operand->type = alloc_type_pointer(type_interpretation); + if (!is_valid_asm_parameter_type(type_interpretation) || + is_type_pointer(type_interpretation)) { // do not allow pointers even if they are valid asm parameter types + gbString s = type_to_string(type_interpretation); + error(mem_op->type, "Asm memory operands type interpretation must be either an integer, boolean, float, or #simd vector, got %s", s); + gb_string_free(s); + } + + } + } + return; case_end; case_ast_node(label, AsmLabelDecl, expr); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 3ba6c5cd3..b8f768102 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -6,6 +6,7 @@ struct lbAsmGenerate { enum WriteOperandFlags : u32 { WriteOperandFlag_PrintPrefixes = 1<<0, WriteOperandFlag_IsScale = 1<<1, + WriteOperandFlag_IsScaleLog2 = 1<<2, WriteOperandFlag_NONE = 0, WriteOperandFlag_DEFAULT = WriteOperandFlag_PrintPrefixes, @@ -62,24 +63,33 @@ struct lbAsmGenerate { GB_ASSERT(ev.kind != ExactValue_Invalid); switch (ev.kind) { case ExactValue_Integer: { - String s = big_int_to_string(heap_allocator(), &ev.value_integer, 10); - if (flags & WriteOperandFlag_PrintPrefixes) { - asm_string = gb_string_appendc(asm_string, "$$"); - } - asm_string = gb_string_append_length(asm_string, s.text, s.len); - gb_free(heap_allocator(), s.text); - + i64 val = exact_value_to_i64(ev); if (flags & WriteOperandFlag_IsScale) { - i64 val = exact_value_to_i64(ev); switch (val) { case 1: case 2: case 4: case 8: // okay break; default: - error(op, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %.*s", LIT(s)); + error(op, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %lld", cast(long long)val); + break; + } + } else if (flags & WriteOperandFlag_IsScaleLog2) { + switch (val) { + case 0: case 1: case 2: case 3: + // NOTE(bill): AMD64 only supports full scales + val = (cast(i64)1)<write_operand(asm_string, op_number, mem_op->index, flags); if (mem_op->scale) { asm_string = gb_string_appendc(asm_string, ","); - asm_string = this->write_operand(asm_string, op_number, mem_op->scale, (flags|WriteOperandFlag_IsScale)&~WriteOperandFlag_PrintPrefixes); + switch (mem_op->scale_op.kind) { + case Token_Mul: + asm_string = this->write_operand(asm_string, op_number, mem_op->scale, (flags|WriteOperandFlag_IsScale)&~WriteOperandFlag_PrintPrefixes); + break; + case Token_Shl: + case Token_Shr: + asm_string = this->write_operand(asm_string, op_number, mem_op->scale, (flags|WriteOperandFlag_IsScaleLog2)&~WriteOperandFlag_PrintPrefixes); + break; + } } } asm_string = gb_string_appendc(asm_string, ")"); diff --git a/src/parser.cpp b/src/parser.cpp index d63c60585..cc9905bfa 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -551,6 +551,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmMemoryOperand.index = clone_ast(n->AsmMemoryOperand.index, f); n->AsmMemoryOperand.scale = clone_ast(n->AsmMemoryOperand.scale, f); n->AsmMemoryOperand.disp = clone_ast(n->AsmMemoryOperand.disp, f); + n->AsmMemoryOperand.type = clone_ast(n->AsmMemoryOperand.type, f); break; } return n; @@ -2444,12 +2445,18 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { Ast *index = nullptr; Ast *scale = nullptr; Ast *disp = nullptr; + Ast *type = nullptr; + + Token scale_op = {}; base = parse_asm_operand(f, false); if (allow_token(f, Token_Add)) { Ast *possible_index = parse_asm_operand(f, false); - if (allow_token(f, Token_Mul)) { + if (allow_token(f, Token_Mul) || + allow_token(f, Token_Shl) || + allow_token(f, Token_Shr)) { + scale_op = f->prev_token; index = possible_index; scale = parse_asm_operand(f, false); if (allow_token(f, Token_Add)) { @@ -2462,13 +2469,19 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { Token close = expect_token(f, Token_CloseBracket); + if (allow_token(f, Token_Colon)) { + type = parse_type(f); + } + Ast *mem = alloc_ast_node(f, Ast_AsmMemoryOperand); - mem->AsmMemoryOperand.open = open; - mem->AsmMemoryOperand.base = base; - mem->AsmMemoryOperand.index = index; - mem->AsmMemoryOperand.scale = scale; - mem->AsmMemoryOperand.disp = disp; - mem->AsmMemoryOperand.close = close; + mem->AsmMemoryOperand.open = open; + mem->AsmMemoryOperand.base = base; + mem->AsmMemoryOperand.index = index; + mem->AsmMemoryOperand.scale = scale; + mem->AsmMemoryOperand.scale_op = scale_op; + mem->AsmMemoryOperand.disp = disp; + mem->AsmMemoryOperand.close = close; + mem->AsmMemoryOperand.type = type; return mem; } diff --git a/src/parser.hpp b/src/parser.hpp index 22ddc0938..aa75e3df4 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -502,12 +502,14 @@ struct AstSplitArgs { Slice operands; \ }) \ AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ - Token open; \ - Ast * base; \ - Ast * index; \ - Ast * scale; \ - Ast * disp; \ - Token close; \ + Token open; \ + Ast * base; \ + Ast * index; \ + Token scale_op; \ + Ast * scale; \ + Ast * disp; \ + Ast * type; \ + Token close; \ }) \ AST_KIND(_ExprBegin, "", bool) \ AST_KIND(BadExpr, "bad expression", struct { Token begin, end; }) \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 3313d831d..4f07c8e8e 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -196,6 +196,9 @@ Token ast_end_token(Ast *node) { } return ast_end_token(node->AsmInstruction.name); case Ast_AsmMemoryOperand: + if (node->AsmMemoryOperand.type) { + return ast_end_token(node->AsmMemoryOperand.type); + } return node->AsmMemoryOperand.close; case Ast_BadExpr: return node->BadExpr.end; From 658fa54ee4a95f1b4daee3c7fcca34ec6fdb6473 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 09:30:55 +0100 Subject: [PATCH 33/92] Support `[base]:u8` type interpretations for memory operands; And determine the correct suffix to use --- src/check_asm.cpp | 109 +++++++++++++++++++++++---------------- src/llvm_backend_asm.cpp | 54 +++++++++++++++++++ src/parser.cpp | 2 +- 3 files changed, 119 insertions(+), 46 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index d96c33885..cbaeab8c5 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -153,8 +153,25 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: return true; } - AsmRegClass got_class = check_asm_reg_class_from_type(operand->type); - i32 got_w = check_asm_operand_bit_width(operand->type); + // Determine the type whose width/class we actually measure. + // + // Memory operands encode their *access* type as a pointer: `[p]:u8` -> `^u8`, + // with a bare `rawptr` meaning "unsized" (no explicit `:type` annotation). A + // register/immediate/parameter operand measures its own type directly. + Type *measured = operand->type; + bool is_memory = (determine_asm_operand_kind(operand) == AsmOperand_Memory); + if (is_memory) { + if (are_types_identical(measured, t_rawptr)) { + // Unsized memory operand: the width is inferred elsewhere (from the + // register operand or deferred), so nothing to check against here. + if (want_bits_) *want_bits_ = want_w; + return true; + } + measured = type_deref(measured); // ^u8 -> u8 + } + + AsmRegClass got_class = check_asm_reg_class_from_type(measured); + i32 got_w = check_asm_operand_bit_width(measured); if (got_w < 0) { // Untyped constant: width is a property of the value, not the type. if (operand->mode == Addressing_Constant && operand->value.kind == ExactValue_Integer) { @@ -170,13 +187,20 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: if (got_bits_) *got_bits_ = got_w; // Class check (only when the slot constrains a class). - if (want_class != AsmRegClass_Unknown) { + // + // A *memory* operand against a register-or-memory slot (e.g. OP_XMM_M64) has no + // lane semantics -- it is just N bytes of memory -- so its integer/vector class + // must not be held against the slot's register class. Only width matters for the + // memory interpretation. Register operands still get the full class check. + if (want_class != AsmRegClass_Unknown && !is_memory) { bool class_ok; switch (want_class) { case AsmRegClass_Integer: class_ok = (got_class == AsmRegClass_Integer); break; case AsmRegClass_Vector: + // A scalar float uses only the low lane, so it is valid in any vector + // register slot; a #simd vector matches the vector class exactly. class_ok = (got_class == AsmRegClass_Vector || got_class == AsmRegClass_Float); break; case AsmRegClass_Mask: @@ -194,7 +218,7 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: // Width check. if (want_w != 0 && got_w != 0) { - if (want_class == AsmRegClass_Vector) { + if (want_class == AsmRegClass_Vector && !is_memory) { // A scalar float uses only the low lane, so it is valid in any vector // register slot as long as it fits; a #simd vector must match exactly. bool width_ok = (got_class == AsmRegClass_Float) ? (got_w <= want_w) : (got_w == want_w); @@ -203,6 +227,7 @@ gb_internal bool check_asm_operand_size_class(AsmCtx *asm_ctx, typename AsmCtx:: return false; } } else { + // Integer/mask registers, and all memory operands: exact width. if (want_w != got_w) { if (mismatch_) *mismatch_ = AsmMismatch_Size; return false; @@ -684,7 +709,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst bool spot_ok = false; if (kind_ok) { - if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory) { + bool mem_unsized = (src == AsmOperand_Memory) && are_types_identical(operand->type, t_rawptr); + + if (dst == AsmOperand_Register_Or_Memory && src == AsmOperand_Memory && mem_unsized) { spot_ok = true; // memory form accepts memory; no size check } else { AsmMismatch m = AsmMismatch_None; @@ -1047,59 +1074,51 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * // displacement: an integer that fits a signed 32-bit value for (int i = 0; disp.expr && i == 0; i++) { if (disp.expr->kind == Ast_AsmRegister) { - error(disp.expr, "A displacement must be an integer value, got a register"); + error(disp.expr, "A displacement must be a constant integer value, got a register"); + break; + } + + // A displacement must be assemble-time constant. A register-valued + // parameter belongs in the index slot, not the displacement. + if (disp.mode == Addressing_Constant && disp.value.kind == ExactValue_Integer) { + AsmMismatch m = AsmMismatch_None; + i32 needed = 0; + if (!check_asm_immediate_value_fits(disp.value, 32, &needed, &m)) { + gbString vs = exact_value_to_string(disp.value); + error(disp.expr, "A memory displacement must fit in a signed 32-bit value, got %s (needs %d bits)", vs, cast(int)needed); + gb_string_free(vs); + } break; } Entity *param_entity = entity_of_node(disp.expr); - if (disp.mode == Addressing_Constant) { - if (disp.value.kind == ExactValue_Integer) { - AsmMismatch m = AsmMismatch_None; - i32 needed = 0; - if (!check_asm_immediate_value_fits(disp.value, 32, &needed, &m)) { - gbString vs = exact_value_to_string(disp.value); - error(disp.expr, "A memory displacement must fit in a signed 32-bit value, got %s (needs %d bits)", vs, cast(int)needed); - gb_string_free(vs); - } + if (param_entity != nullptr && param_entity->kind == Entity_Variable) { + auto kind = check_asm_find_kind(param_entity, ate->decls); + if (kind == AsmTemplateEntityDecl_Immediate) { + // A $-immediate parameter is a legal (assemble-time) displacement. + break; + } + if (kind == AsmTemplateEntityDecl_Register) { + error(disp.expr, "A register parameter cannot be a displacement; use it as an index, e.g. [base + %.*s]", LIT(disp.expr->Ident.token.string)); break; } } - if (param_entity == nullptr) { - gbString s = expr_to_string(disp.expr); - error(disp.expr, "A displacement value must be an integer, got %s", s); - gb_string_free(s); - break; - } - auto kind = check_asm_find_kind(param_entity, ate->decls); - switch (kind) { - case AsmTemplateEntityDecl_Register: - case AsmTemplateEntityDecl_Immediate: - if (is_type_integer(disp.type)) { - break; - } - /*fallthrough*/ - default: - { - gbString s = expr_to_string(disp.expr); - gbString t = type_to_string(disp.type); - error(disp.expr, "A displacement must be an integer value, got %s of type %s", s, t); - gb_string_free(t); - gb_string_free(s); - } - break; - } + gbString s = expr_to_string(disp.expr); + error(disp.expr, "A displacement must be a constant integer or immediate, got %s", s); + gb_string_free(s); } if (mem_op->type) { - Type *type_interpretation = check_type(ctx, mem_op->type); - if (type_interpretation != nullptr && type_interpretation != t_invalid) { - operand->type = alloc_type_pointer(type_interpretation); - if (!is_valid_asm_parameter_type(type_interpretation) || - is_type_pointer(type_interpretation)) { // do not allow pointers even if they are valid asm parameter types - gbString s = type_to_string(type_interpretation); + Type *t = check_type(ctx, mem_op->type); + if (t != nullptr && t != t_invalid) { + if (is_valid_asm_parameter_type(t) && !is_type_pointer(t)) { + operand->type = alloc_type_pointer(t); + } else { + gbString s = type_to_string(t); error(mem_op->type, "Asm memory operands type interpretation must be either an integer, boolean, float, or #simd vector, got %s", s); gb_string_free(s); + // leave operand->type == t_rawptr ("unsized") } } diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index b8f768102..8dbff8a3b 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -121,6 +121,47 @@ struct lbAsmGenerate { } }; + // AT&T operand-size suffix ('b','w','l','q') for an annotated memory operand, + // or 0 if there is no size annotation to apply. Vector/other widths return 0, + // since those forms take no b/w/l/q suffix (the register operand fixes the size). + char size_suffix_for_operand(Ast *op) { + if (op->kind != Ast_AsmMemoryOperand) { + return 0; + } + AstAsmMemoryOperand *mem_op = &op->AsmMemoryOperand; + if (mem_op->type == nullptr) { + return 0; // unsized: rely on a register operand to fix the width + } + // The frontend stored the access type as a pointer on the node's tav: [p]:u8 -> ^u8. + Type *ptr = mem_op->type->tav.type; + if (ptr == nullptr) { + return 0; + } + Type *access = type_deref(ptr); // ^u8 -> u8 + i64 sz = type_size_of(base_type(access)); + switch (sz) { + case 1: return 'b'; + case 2: return 'w'; + case 4: return 'l'; + case 8: return 'q'; + } + return 0; + } + + // Scan an instruction's operands for an annotated memory operand and return its + // AT&T size suffix, or 0 if none. The checker has already verified the annotation + // agrees with the matched encoding form, so a suffix here can never conflict. + char instruction_size_suffix(AstAsmInstruction *instr) { + char suffix = 0; + for (Ast *operand : instr->operands) { + char s = this->size_suffix_for_operand(operand); + if (s != 0) { + suffix = s; + } + } + return suffix; + } + // LLVM type of a returned register output, taken from the proc signature's results. LLVMTypeRef output_llvm_type(lbModule *m, AsmTemplateEntityDecl const &e) { @@ -304,6 +345,19 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { asm_string = gb_string_appendc(asm_string, "\t"); String name = instr->name->Ident.token.string; asm_string = gb_string_append_length(asm_string, name.text, name.len); + + // If a memory operand carries an explicit size annotation ([p]:u8) and + // no register operand pins the width, the AT&T assembler needs the size + // encoded as a mnemonic suffix (crc32 -> crc32b). The checker has already + // verified the annotation agrees with the matched form, so an emitted + // suffix can never conflict with a register operand's implied width. + { + char suffix = this->instruction_size_suffix(instr); + if (suffix != 0) { + asm_string = gb_string_append_length(asm_string, &suffix, 1); + } + } + asm_string = gb_string_appendc(asm_string, " "); // Intel-source operand order reversed to AT&T (src, ..., dst). for (isize j = instr->operands.count-1; j >= 0; j -= 1) { diff --git a/src/parser.cpp b/src/parser.cpp index cc9905bfa..a67aafe35 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2463,7 +2463,7 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { disp = parse_asm_operand(f, false); } } else { - disp = possible_index; + index = possible_index; } } From a9df33e4821ee07f73d657924cd8ee68352085a0 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 09:31:52 +0100 Subject: [PATCH 34/92] Virtualize the suffix handling in the llvm_backend_asm.cpp code --- src/llvm_backend_asm.cpp | 58 ++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 8dbff8a3b..486cc5dcd 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -121,10 +121,38 @@ struct lbAsmGenerate { } }; + // Scan an instruction's operands for an annotated memory operand and return its + // size suffix, or 0 if none. The checker has already verified the annotation + // agrees with the matched encoding form, so a suffix here can never conflict. + char instruction_size_suffix(AstAsmInstruction *instr) { + char suffix = 0; + for (Ast *operand : instr->operands) { + char s = this->size_suffix_for_operand(operand); + if (s != 0) { + suffix = s; + } + } + return suffix; + } + + + // LLVM type of a returned register output, taken from the proc signature's results. + LLVMTypeRef output_llvm_type(lbModule *m, AsmTemplateEntityDecl const &e) { + Type *pt = base_type(tmpl_entity->type); + Type *rt = pt->Proc.results->Tuple.variables[e.result_index]->type; + return lb_type(m, rt); + }; + + virtual char size_suffix_for_operand(Ast *op) = 0; + virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; + virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; +}; + +struct lbAsmGenerate_amd64 : lbAsmGenerate { // AT&T operand-size suffix ('b','w','l','q') for an annotated memory operand, // or 0 if there is no size annotation to apply. Vector/other widths return 0, // since those forms take no b/w/l/q suffix (the register operand fixes the size). - char size_suffix_for_operand(Ast *op) { + char size_suffix_for_operand(Ast *op) override { if (op->kind != Ast_AsmMemoryOperand) { return 0; } @@ -148,34 +176,6 @@ struct lbAsmGenerate { return 0; } - // Scan an instruction's operands for an annotated memory operand and return its - // AT&T size suffix, or 0 if none. The checker has already verified the annotation - // agrees with the matched encoding form, so a suffix here can never conflict. - char instruction_size_suffix(AstAsmInstruction *instr) { - char suffix = 0; - for (Ast *operand : instr->operands) { - char s = this->size_suffix_for_operand(operand); - if (s != 0) { - suffix = s; - } - } - return suffix; - } - - - // LLVM type of a returned register output, taken from the proc signature's results. - LLVMTypeRef output_llvm_type(lbModule *m, AsmTemplateEntityDecl const &e) { - Type *pt = base_type(tmpl_entity->type); - Type *rt = pt->Proc.results->Tuple.variables[e.result_index]->type; - return lb_type(m, rt); - }; - - - virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; - virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; -}; - -struct lbAsmGenerate_amd64 : lbAsmGenerate { gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { if (mem_op->disp) { asm_string = this->write_operand(asm_string, op_number, mem_op->disp, flags&~WriteOperandFlag_PrintPrefixes); From 612b25a425950fb54214dd2bdf31f24aa78804d4 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 09:34:16 +0100 Subject: [PATCH 35/92] Handle `disp` parameter correctly --- src/check_asm.cpp | 4 +++- src/parser.cpp | 6 +++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index cbaeab8c5..089afb05a 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -977,7 +977,9 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * default: { gbString s = expr_to_string(index.expr); - error(index.expr, "An index must be an integer register, got %s", s); + gbString t = type_to_string(index.type); + error(index.expr, "An index must be an integer register, got %s of type %s", s, t); + gb_string_free(t); gb_string_free(s); ok_kind = false; } diff --git a/src/parser.cpp b/src/parser.cpp index a67aafe35..8b81334a1 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2459,12 +2459,12 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { scale_op = f->prev_token; index = possible_index; scale = parse_asm_operand(f, false); - if (allow_token(f, Token_Add)) { - disp = parse_asm_operand(f, false); - } } else { index = possible_index; } + if (allow_token(f, Token_Add)) { + disp = parse_asm_operand(f, false); + } } Token close = expect_token(f, Token_CloseBracket); From a87f5dd5e9b62e834d3f497f8e9a3e4a2d841d09 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 09:38:55 +0100 Subject: [PATCH 36/92] Clean up parsing for `AstAsmMemoryOperand` --- src/parser.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/parser.cpp b/src/parser.cpp index 8b81334a1..c06c99845 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2451,16 +2451,18 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { base = parse_asm_operand(f, false); + // [base] + // [base + index] + // [base + index + disp] + // [base + index*scale] // *, <<, >> + // [base + index*scale + disp] if (allow_token(f, Token_Add)) { - Ast *possible_index = parse_asm_operand(f, false); + index = parse_asm_operand(f, false); if (allow_token(f, Token_Mul) || allow_token(f, Token_Shl) || allow_token(f, Token_Shr)) { scale_op = f->prev_token; - index = possible_index; scale = parse_asm_operand(f, false); - } else { - index = possible_index; } if (allow_token(f, Token_Add)) { disp = parse_asm_operand(f, false); @@ -2469,6 +2471,7 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { Token close = expect_token(f, Token_CloseBracket); + // [...]:type if (allow_token(f, Token_Colon)) { type = parse_type(f); } From db41921a16766ccf10048329eda0d4426875bb1e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 10:20:11 +0100 Subject: [PATCH 37/92] Mock out `p0: u64 = %rax, p0b: u8 = p0` --- src/check_asm.cpp | 66 ++++++++++++++++++++++++++++++++++++----------- src/parser.cpp | 10 ++++++- 2 files changed, 60 insertions(+), 16 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 089afb05a..c4aee9b38 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -411,24 +411,37 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice GB_ASSERT(spec->name->kind == Ast_Ident); Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); + Entity *other_scratch = nullptr; String pin = {}; if (spec->value != nullptr) { - if (spec->value->kind != Ast_AsmRegister) { - gbString s = expr_to_string(spec->value); - error(spec->value, "Expected an asm register, got %s", s); - gb_string_free(s); - continue; - } + if (spec->value->kind == Ast_Ident) { + other_scratch = scope_lookup(scope, spec->value->Ident.interned, spec->value->Ident.hash); + if (other_scratch) { + auto group = check_asm_find_group(other_scratch, *asm_template_entity_decls, nullptr); + if (!group) { + error(spec->value, "This must be another parameter, got %.*s", LIT(other_scratch->token.string)); + } + } else { + error(spec->value, "Undefined parameter declaration '%.*s'", LIT(spec->value->Ident.token.string)); + } + } else { + if (spec->value->kind != Ast_AsmRegister) { + gbString s = expr_to_string(spec->value); + error(spec->value, "Expected an asm register or scratch parameter, got %s", s); + gb_string_free(s); + continue; + } - ast_node(reg, AsmRegister, spec->value); - pin = reg->name.string; - if (pin == "any") { - pin = {}; - } - if (pin.len != 0) { - if (string_set_update(&pin_set, pin)) { - error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); + ast_node(reg, AsmRegister, spec->value); + pin = reg->name.string; + if (pin == "any") { + pin = {}; + } + if (pin.len != 0) { + if (string_set_update(&pin_set, pin)) { + error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); + } } } } @@ -454,6 +467,20 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; ed.total_index = cast(i32)asm_template_entity_decls->count; ed.pin = pin; + + if (other_scratch != nullptr) { + // TODO(bill): subsetting parameters + // p0: u64 = %rax, + // p0b: u8 = p0, + // + // or + // + // p0: u64, // implied = %any + // p0b: u8 = p0, // the 8-bit subsection of the same register, if possible + GB_ASSERT(spec->value != nullptr); + error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration"); + } + array_add(asm_template_entity_decls, ed); } else { TokenPos pos = found->token.pos; @@ -478,8 +505,12 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice } else { error(spec_, "Asm register has already been pinned"); } - } + if (other_scratch != nullptr) { + GB_ASSERT(spec->value != nullptr); + error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration"); + } + } } else { GB_ASSERT(spec->tied_name->kind == Ast_Ident); @@ -522,6 +553,11 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice i->pin = pin; o->pin = pin; + + if (other_scratch != nullptr) { + GB_ASSERT(spec->value != nullptr); + error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration, not a tie"); + } } } } diff --git a/src/parser.cpp b/src/parser.cpp index c06c99845..c8b1b0ace 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2642,7 +2642,15 @@ gb_internal Ast *parse_asm_template(AstFile *f) { type = parse_type(f); } if (allow_token(f, Token_Eq)) { - value = parse_asm_register(f); + if (f->curr_token.kind == Token_Ident) { + value = parse_ident(f); + } else if (f->curr_token.kind == Token_Mod) { + value = parse_asm_register(f); + } else { + error(f->curr_token, "Expected a register or scratch parameter"); + Ast *dummy = parse_expr(f, true); + gb_unused(dummy); + } } if (tied_name != nullptr) { From bef386b1fb649dc2919bf839a8c5c1e7c9bbcb89 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 10:33:53 +0100 Subject: [PATCH 38/92] Implement asm view-of parameters `pred: i64, predb: u8 = pred` --- src/check_asm.cpp | 67 ++++++++++++++++++++++++++++++++++------ src/entity.cpp | 5 +++ src/llvm_backend_asm.cpp | 42 ++++++++++++++++++++++--- 3 files changed, 100 insertions(+), 14 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index c4aee9b38..94b8a82dc 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -469,16 +469,65 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice ed.pin = pin; if (other_scratch != nullptr) { - // TODO(bill): subsetting parameters - // p0: u64 = %rax, - // p0b: u8 = p0, - // - // or - // - // p0: u64, // implied = %any - // p0b: u8 = p0, // the 8-bit subsection of the same register, if possible + // Width-view of another operand: `p0b: u8 = p0`. + // p0b shares p0's register, viewed at p0b's declared width. GB_ASSERT(spec->value != nullptr); - error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration"); + + i32 src_index = -1; + auto src_group = check_asm_find_group(other_scratch, *asm_template_entity_decls, &src_index); + + // 1. The source must already exist and be a register-class operand + // (you cannot take a width-view of an immediate or memory operand). + if (src_index < 0) { + error(spec->value, "'%.*s' must refer to a previously declared parameter", LIT(other_scratch->token.string)); + } else { + auto &src = (*asm_template_entity_decls)[src_index]; + + bool src_is_reg = src_group == AsmTemplateEntityDeclParamGroup_Input || + src_group == AsmTemplateEntityDeclParamGroup_Output || + src_group == AsmTemplateEntityDeclParamGroup_Scratch; + if (src.kind == AsmTemplateEntityDecl_Immediate || src.kind == AsmTemplateEntityDecl_Memory) { + src_is_reg = false; + } + if (!src_is_reg) { + error(spec->value, "A width-view can only be taken of a register operand, not '%.*s'", LIT(other_scratch->token.string)); + } + + // 2. The view width must be a legal sub-register width and no wider + // than the source (only narrowing views exist). + i32 view_w = check_asm_operand_bit_width(type); // this decl's type (u8 -> 8) + i32 src_w = check_asm_operand_bit_width(src.entity->type); + AsmRegClass view_class = check_asm_reg_class_from_type(type); + AsmRegClass src_class = check_asm_reg_class_from_type(src.entity->type); + + if (view_class != AsmRegClass_Integer || src_class != AsmRegClass_Integer) { + error(spec->type, "Width-views are only supported for integer registers"); + } else { + switch (view_w) { + case 8: case 16: case 32: case 64: + if (view_w > src_w) { + error(spec->type, "A width-view (%d-bit) cannot be wider than its source '%.*s' (%d-bit)", + cast(int)view_w, LIT(other_scratch->token.string), cast(int)src_w); + } + break; + default: + error(spec->type, "A width-view must be an 8, 16, 32, or 64-bit integer type, got a %d-bit type", cast(int)view_w); + break; + } + } + + // 3. A view does not carry its own pin; it inherits the source's register. + if (pin.len != 0) { + error(spec->value, "A width-view cannot also be pinned to a register; it inherits the source operand's register"); + } + + ed.kind = AsmTemplateEntityDecl_Register; + ed.view_of = src_index; + ed.view_bits = view_w; + // A view is not itself an input/output/scratch slot for allocation: + // mark it so the lowering passes skip it. Reuse the Scratch group but + // with view_of >= 0 as the discriminator (see lowering note). + } } array_add(asm_template_entity_decls, ed); diff --git a/src/entity.cpp b/src/entity.cpp index 31a479eb9..446947ef0 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -192,6 +192,9 @@ struct AsmTemplateEntityDecl { i32 param_index; // index into the Proc signature's params (inputs), else -1 i32 result_index; // index into results (outputs), else -1 i32 tie; // InOut: index into operands[] of the tied output; else -1 + + i32 view_of; // total_index of the source operand this is a width-view of, else -1 + i32 view_bits; // the view width in bits, otherwise 0 }; // An Entity is a named "thing" in the language @@ -374,6 +377,8 @@ gb_internal AsmTemplateEntityDecl asm_template_entity_decl_default(Entity *entit ed.param_index = -1; ed.result_index = -1; ed.tie = -1; + ed.view_of = -1; + ed.view_bits = 0; return ed; } diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 486cc5dcd..530106ed2 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -49,9 +49,26 @@ struct lbAsmGenerate { Entity *e = entity_of_node(op); auto *ed = entity_op(e); - i32 idx = op_number[ed->total_index]; - GB_ASSERT(idx >= 0); - asm_string = gb_string_append_fmt(asm_string, "$%d", idx); + if (ed->view_of >= 0) { + // Width-view of another operand (e.g. `p0b: u8 = p0`): emit the SOURCE + // operand's number with an LLVM width modifier, so both names share the + // one register the allocator chose, viewed at the requested width. + i32 idx = op_number[ed->view_of]; + GB_ASSERT(idx >= 0); + char mod = 0; + switch (ed->view_bits) { + case 8: mod = 'b'; break; // low 8-bit (al/r11b/...) + case 16: mod = 'w'; break; // 16-bit (ax/r11w/...) + case 32: mod = 'k'; break; // 32-bit (eax/r11d/...) + case 64: mod = 'q'; break; // 64-bit (rax/r11/...) + default: GB_PANIC("asm: invalid width-view size %d", ed->view_bits); break; + } + asm_string = gb_string_append_fmt(asm_string, "${%d:%c}", idx, mod); + } else { + i32 idx = op_number[ed->total_index]; + GB_ASSERT(idx >= 0); + asm_string = gb_string_append_fmt(asm_string, "$%d", idx); + } case_end; case_ast_node(mem_op, AsmMemoryOperand, op); asm_string = this->write_memory_operand(asm_string, op_number, mem_op, flags&~WriteOperandFlag_PrintPrefixes); @@ -218,7 +235,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { auto ret_types = array_make(temporary_allocator(), 0, ops->count); // Per-operand bookkeeping, indexed the same as `ops` (via total_index). - auto op_number = array_make(temporary_allocator(), ops->count, ops->count); // $N, or -1 for clobbers + auto op_number = array_make(temporary_allocator(), ops->count, ops->count); // $N, or -1 for clobbers/views auto ret_slot = array_make(temporary_allocator(), ops->count, ops->count); // return-struct index, or -1 for_array(i, *ops) { op_number[i] = -1; @@ -259,6 +276,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { for_array(i, *ops) { AsmTemplateEntityDecl const &e = (*ops)[i]; + if (e.view_of >= 0) { + continue; // width-view: resolved to its source's operand, owns no slot + } + bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch && e.kind == AsmTemplateEntityDecl_Register @@ -292,6 +313,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // Pass 2: inputs for (isize i = 0; i < ops->count; i++) { AsmTemplateEntityDecl const &e = (*ops)[i]; + + if (e.view_of >= 0) { + continue; // width-view: not its own input + } if (e.param_group != AsmTemplateEntityDeclParamGroup_Input) { continue; } @@ -383,6 +408,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // output in Pass 1, so it is skipped here. for (isize i = 0; i < ops->count; i++) { AsmTemplateEntityDecl const &e = (*ops)[i]; + + if (e.view_of >= 0) { + continue; // width-view carries no clobber; its source owns the register + } if (e.param_group != AsmTemplateEntityDeclParamGroup_Scratch) { continue; } @@ -466,6 +495,9 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { for (isize i = 0; i < ops->count; i++) { AsmTemplateEntityDecl const &e = (*ops)[i]; + if (e.view_of >= 0) { + continue; // width-view: never a returned value + } if (e.param_group != AsmTemplateEntityDeclParamGroup_Output) { continue; } @@ -502,4 +534,4 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar lbAsmGenerate_amd64 generator = {}; generator.init(entity); return generator.emit_call(p, args); -} \ No newline at end of file +} From 99a128e78e07b6c61cbd820145dfdc02986af1eb Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 11:08:33 +0100 Subject: [PATCH 39/92] Remove `%any` as a concept --- src/check_asm.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 94b8a82dc..7da9e22e4 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -435,9 +435,6 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice ast_node(reg, AsmRegister, spec->value); pin = reg->name.string; - if (pin == "any") { - pin = {}; - } if (pin.len != 0) { if (string_set_update(&pin_set, pin)) { error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); From 6bd2fd7e8bbb8b6c865a74b6e9eff838aa90510b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 11:25:03 +0100 Subject: [PATCH 40/92] Add clobber table for x86 --- core/rexcode/isa/x86/clobber_types.odin | 50 + .../isa/x86/tablegen/clobber_table.odin | 1275 +++++++++++++++++ .../isa/x86/tablegen/encoding_table.odin | 2 +- core/rexcode/isa/x86/tablegen/gen.odin | 8 +- .../isa/x86/tablegen/generated/writer.odin | 3 + core/rexcode/isa/x86/tables.odin | 1 + .../isa/x86/tables/x86.clobber_table.bin | Bin 0 -> 19104 bytes 7 files changed, 1337 insertions(+), 2 deletions(-) create mode 100644 core/rexcode/isa/x86/clobber_types.odin create mode 100644 core/rexcode/isa/x86/tablegen/clobber_table.odin create mode 100644 core/rexcode/isa/x86/tables/x86.clobber_table.bin diff --git a/core/rexcode/isa/x86/clobber_types.odin b/core/rexcode/isa/x86/clobber_types.odin new file mode 100644 index 000000000..164003cd2 --- /dev/null +++ b/core/rexcode/isa/x86/clobber_types.odin @@ -0,0 +1,50 @@ +package rexcode_x86 + +Clobber_Flags :: distinct bit_set[Clobber_Flag; u16] +Clobber_Flag :: enum u8 { + CF, + PF, + AF, + ZF, + SF, + OF, + DF, + IF, + TF, +} + +Side_Effect :: enum u8 { + FENCE, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK) + SERIALIZING, // architecturally serializing (drains pipeline) + HINT, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR) + CACHE, // cache-line maintenance with coherence effects (CLFLUSH/CLWB) + TRAP, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND + INTERRUPT, // software interrupt / syscall gate + HALT, // stops execution until an external event + PRIVILEGED, // requires CPL0 / reads-writes supervisor machine state + CONTROL, // alters control flow (writes RIP): branches, calls, returns + CET, // control-flow-enforcement: landing pads, shadow-stack ops +} +Side_Effects :: distinct bit_set[Side_Effect; u16] + +Clobber_Regs :: distinct bit_set[Clobber_Reg; u16] +Clobber_Reg :: enum u8 { + RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R11, + XMM0, VECTOR, MXCSR, FPU_ST, FPU_SW, +} + +Operand_Set :: distinct bit_set[Operand_Slot; u8] +Operand_Slot :: enum u8 { OP0, OP1, OP2, OP3 } + +Clobber :: struct { + written: Operand_Set, + read: Operand_Set, + implicit_wr: Clobber_Regs, + implicit_rd: Clobber_Regs, + flags_wr: Clobber_Flags, + flags_undef: Clobber_Flags, + flags_rd: Clobber_Flags, + writes_mem: bool, + reads_mem: bool, + side_effects: Side_Effects, +} \ No newline at end of file diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin new file mode 100644 index 000000000..857b604be --- /dev/null +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -0,0 +1,1275 @@ +// clobber_table.odin -- auxiliary side-effect table for rexcode_x86_tablegen +// +// DERIVED, NOT EXTRACTED. The ENCODING_TABLE describes how bytes are laid out +// (opcode, ModRM roles, prefixes, REX). It carries no read/write direction and +// no implicit side effects, so this table cannot be produced from it alone -- +// it is a hand-authored semantics layer sourced from the Intel SDM Vol.2 +// ("Operation" + "Flags Affected") applied per instruction family. +// +// Conventions: +// written / read explicit operand slots (OP0..OP3). rmw = written & read. +// implicit_wr / _rd registers touched that are NOT explicit operands +// (widths follow operand size; e.g. RAX means AL/AX/EAX/RAX). +// flags_wr EFLAGS set to a DEFINED value (a cleared flag counts). +// flags_undef EFLAGS left ARCHITECTURALLY UNDEFINED (must be treated +// as clobbered by a compiler, value not guaranteed). +// flags_rd EFLAGS consumed by the instruction. +// writes_mem/reads_mem memory VALUE touched (explicit mem operand or +// implicit: PUSH/CALL/string ops/gather/scatter/etc). +// side_effects effects that are NOT clobbers but still make the +// instruction non-eliminable and/or non-reorderable +// (fences, serialization, traps, control flow, ...). +// This is what separates MFENCE -- orders memory, +// clobbers nothing -- from a genuine no-op. +// FPU_ST/FPU_SW = x87 stack / status word; MXCSR = SSE control-status; +// VECTOR = the whole SIMD register file (VZEROALL/VZEROUPPER). +// +// INVARIANT: an instruction is a pure, freely-eliminable no-op iff every +// clobber set is empty AND side_effects == {}. In this table only .NOP +// (and the .INVALID sentinel) satisfy that. + +package rexcode_x86_tablegen + +import "core:rexcode/isa/x86" + +@(rodata) +CLOBBER_TABLE := [Mnemonic]x86.Clobber{ + .INVALID = {}, + + // ---- 8.1 Data Transfer Encodings ---- + .MOV = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + .MOVABS = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + .MOVZX = {written={.OP0}, read={.OP1}, reads_mem=true}, + .MOVSX = {written={.OP0}, read={.OP1}, reads_mem=true}, + .MOVSXD = {written={.OP0}, read={.OP1}, reads_mem=true}, + .XCHG = {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, // asserts LOCK when a mem operand is used + .PUSH = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + .POP = {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + .LEA = {written={.OP0}}, // no memory access: computes effective address only + + // ---- 8.2 Arithmetic Encodings ---- + .ADD = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + .ADC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + .SUB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + .SBB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + .MUL = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // RAX/RDX widths follow operand size (r/m8 -> AX only) + .IMUL = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit + .DIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only + .IDIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only + .INC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected + .DEC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected + .NEG = {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + .CMP = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // no operand written; flags only + + // ---- 8.3 Logical Encodings ---- + .AND = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + .OR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + .XOR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + .NOT = {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + .TEST = {read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, reads_mem=true}, // no operand written; flags only + + // ---- 8.4 Shift/Rotate Encodings ---- + .SHL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged + .SHR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged + .SAR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged + .ROL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged + .ROR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged + .RCL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + .RCR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + .SHLD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, + .SHRD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, + + // ---- 8.5 Bit Operation Encodings ---- + .BT = {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF unaffected + .BTS = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected + .BTR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected + .BTC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected + .BSF = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 + .BSR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 + .POPCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // ZF per source; CF/OF/SF/AF/PF cleared + .LZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, + .TZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, + + // ---- 8.6 Control Flow Encodings ---- + .JMP = {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, // indirect forms read reg/mem; writes RIP + .JA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JNS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JPE = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JPO = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch + .JCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads CX + .JECXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads ECX + .JRCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads RCX + .LOOP = {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, + .LOOPE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + .LOOPNE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + .CALL = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, // pushes return address + .RET = {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, // pops return address (+imm16 form adjusts RSP) + .IRET = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) + .IRETD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) + .IRETQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) + .INT = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate + .INT3 = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate + .INTO = {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.OF, .CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // #OF only if OF=1 + .SYSCALL = {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK + .SYSRET = {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // RIP<-RCX, RFLAGS<-R11 + .SYSENTER = {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, // privileged; RSP/RIP from MSRs + .SYSEXIT = {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX + + // ---- 8.7 Conditional Set/Move Encodings ---- + .SETA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + .SETAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + .SETC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + .SETG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + .SETGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + .SETL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + .SETLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + .SETNA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + .SETNAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETNB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETNBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + .SETNC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + .SETNE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + .SETNG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + .SETNGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + .SETNL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + .SETNLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + .SETNO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + .SETNP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + .SETNS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + .SETNZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + .SETO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + .SETP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + .SETPE = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + .SETPO = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + .SETS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + .SETZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + .CMOVA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVNAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVNB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVNBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVNC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 + .CMOVNE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVNG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 + .CMOVNP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 + .CMOVNS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 + .CMOVNZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + .CMOVO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 + .CMOVP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 + .CMOVPE = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 + .CMOVPO = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 + .CMOVS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 + .CMOVZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + + // ---- 8.8 String Operation Encodings ---- + .MOVS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .MOVSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .MOVSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .MOVSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .MOVSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .CMPS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .CMPSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .CMPSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .CMPSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .CMPSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .SCAS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .SCASB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .SCASW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .SCASD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .SCASQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .LODS = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .LODSB = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .LODSW = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .LODSD = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .LODSQ = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .STOS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .STOSB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .STOSW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .STOSD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + .STOSQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + + // ---- 8.9 Flag Operation Encodings ---- + .CLC = {flags_wr={.CF}}, + .STC = {flags_wr={.CF}}, + .CMC = {flags_wr={.CF}, flags_rd={.CF}}, + .CLD = {flags_wr={.DF}}, + .STD = {flags_wr={.DF}}, + .CLI = {flags_wr={.IF}}, + .STI = {flags_wr={.IF}}, + .LAHF = {implicit_wr={.RAX}, flags_rd={.SF, .ZF, .AF, .PF, .CF}}, // AH <- flags + .SAHF = {implicit_rd={.RAX}, flags_wr={.SF, .ZF, .AF, .PF, .CF}}, // flags <- AH + .PUSHF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + .PUSHFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + .PUSHFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + .POPF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + .POPFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + .POPFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + + // ---- 8.10 Miscellaneous Encodings ---- + .NOP = {}, // no register/flag/memory clobber + .HLT = {side_effects={.HALT, .PRIVILEGED}}, // no register/flag/memory clobber + .WAIT = {implicit_rd={.FPU_SW}}, // waits on pending x87 exception + .LOCK = {side_effects={.FENCE}}, // no register/flag/memory clobber + .UD0 = {side_effects={.TRAP}}, // no register/flag/memory clobber + .UD1 = {side_effects={.TRAP}}, // no register/flag/memory clobber + .UD2 = {side_effects={.TRAP}}, // no register/flag/memory clobber + .CPUID = {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + .RDTSC = {implicit_wr={.RAX, .RDX}}, + .RDTSCP = {implicit_wr={.RAX, .RDX, .RCX}}, + .RDPMC = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + .XGETBV = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + .XSETBV = {implicit_rd={.RCX, .RDX, .RAX}}, // privileged; writes XCR[ECX] + .CBW = {implicit_wr={.RAX}, implicit_rd={.RAX}}, + .CWDE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, + .CDQE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, + .CWD = {implicit_wr={.RDX}, implicit_rd={.RAX}}, + .CDQ = {implicit_wr={.RDX}, implicit_rd={.RAX}}, + .CQO = {implicit_wr={.RDX}, implicit_rd={.RAX}}, + + // ---- 8.11 BMI/ADX Encodings ---- + .ANDN = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.SF, .ZF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, + .BEXTR = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .CF, .OF}, flags_undef={.SF, .AF, .PF}, reads_mem=true}, + .BLSI = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, + .BLSMSK = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, + .BLSR = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, + .BZHI = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .SF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, + .PDEP = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected + .PEXT = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected + .RORX = {written={.OP0}, read={.OP1}, reads_mem=true}, // no flags affected + .SARX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) + .SHLX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) + .SHRX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) + .MULX = {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, // no flags affected; implicit multiplicand in rDX + .ADCX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, // only CF (chains with ADCX) + .ADOX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, // only OF (chains with ADOX) + + // ---- 8.12 SSE Encodings ---- + .MOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR + .MOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR + .MOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .MOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .DIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .DIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .DIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .DIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .SQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .RCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .RCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .RSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .RSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .ORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .XORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .XORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .CMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CMPSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .COMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .COMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .UCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .UCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .SHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .UNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .UNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .UNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .UNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .CVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .CVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .CVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .CVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .CVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .PADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PADDUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSUBUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .POR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSHUFW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .PINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR + .PAVGB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PAVGW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] + .LFENCE = {side_effects={.FENCE, .SERIALIZING}}, // ordering/hint; no clobber + .SFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber + .MFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber + .PAUSE = {side_effects={.HINT}}, // ordering/hint; no clobber + .CLFLUSH = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // flushes cache line for the addressed byte + .ADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .HADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .HADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .HSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .HSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .MOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .LDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .BLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .BLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .BLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .BLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .DPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .DPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .EXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .INSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .MPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .PEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .PEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .PHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared + .ROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .ROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .PCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .CRC32 = {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, // accumulates CRC into OP0; no flags + .PCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + .PCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + .PCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + .PCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + .PCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .PCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .AESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA1MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA1MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA1NEXTE = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA1RNDS4 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA256MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA256MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .SHA256RNDS2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + + // ---- 8.13 AVX/AVX2 Encodings ---- + .VADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VDIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VDIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VDIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VDIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VXORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VXORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VCMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCMPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .VCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .VUCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .VUCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared + .VSHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VSHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VUNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VUNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VUNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VUNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VDPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VDPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VEXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .VINSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR + .VMOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR + .VMOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VHADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VHADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VHSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VHSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VLDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + .VPCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + .VPCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + .VPCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + .VPBROADCASTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBROADCASTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBROADCASTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBROADCASTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VCVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .VCVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .VCVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .VCVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR + .VPADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .VPEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .VPEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .VPEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory + .VPINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR + .VPTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared + .VPSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] + .VPCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VAESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBROADCASTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBROADCASTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBROADCASTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VEXTRACTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VINSERTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERM2F128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMASKMOVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VMASKMOVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VTESTPS = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared + .VTESTPD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared + .VZEROALL = {implicit_wr={.VECTOR}}, // zeroes the entire vector register file (YMM/ZMM) + .VZEROUPPER = {implicit_wr={.VECTOR}}, // zeroes bits [MAXVL-1:128] of every vector register + .VBROADCASTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VEXTRACTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VINSERTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERM2I128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRAVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMASKMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VPMASKMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, + .VGATHERDPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VGATHERDPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VGATHERQPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VGATHERQPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VPGATHERDD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VPGATHERDQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VPGATHERQD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + .VPGATHERQQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + + // ---- 8.14 FMA Encodings ---- + .VFMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFNMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMADDSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFMSUBADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTPH2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VCVTPS2PH = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, // may set MXCSR exception/status bits + + // ---- 8.15 AVX-512 Encodings ---- + .VMOVDQA32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDQA64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDQU8 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDQU16 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDQU32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VMOVDQU64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPBLENDMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VBLENDMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCMPB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPUB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPUW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPUD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCMPUQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTNMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTNMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTNMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPTESTNMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS + .VPCOMPRESSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCOMPRESSQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VCOMPRESSPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VCOMPRESSPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPEXPANDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPEXPANDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VEXPANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VEXPANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCONFLICTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPCONFLICTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPLZCNTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPLZCNTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMI2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMT2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPERMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVB2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register + .VPMOVW2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register + .VPMOVD2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register + .VPMOVQ2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register + .VPMOVM2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVM2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVM2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVM2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMOVUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPROLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPROLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPROLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPROLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPRORD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPRORQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPRORVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPRORVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSCATTERDD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VPSCATTERDQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VPSCATTERQD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VPSCATTERQQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VSCATTERDPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VSCATTERDPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VSCATTERQPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VSCATTERQPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element + .VPSRAVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRAVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSLLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPSRLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VRANGEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRANGEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRANGESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRANGESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VREDUCEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VREDUCEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VREDUCESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VREDUCESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRNDSCALEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRNDSCALEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRNDSCALESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRNDSCALESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRT14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRT14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRT14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRSQRT14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCP14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCP14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCP14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VRCP14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSCALEFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSCALEFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSCALEFSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VSCALEFSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETEXPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETEXPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETEXPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETEXPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETMANTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETMANTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETMANTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VGETMANTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFIXUPIMMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFIXUPIMMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFIXUPIMMSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFIXUPIMMSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits + .VFPCLASSPS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register + .VFPCLASSPD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register + .VFPCLASSSS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register + .VFPCLASSSD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register + .VALIGNQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VALIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VDBPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPTERNLOGD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPTERNLOGQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .VPMULTISHIFTQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + .KADDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KADDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KADDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KADDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDNW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDNB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDNQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KANDND = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KMOVW = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask + .KMOVB = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask + .KMOVQ = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask + .KMOVD = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask + .KNOTW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KNOTB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KNOTQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KNOTD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KORTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KORTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KORTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KORTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KSHIFTLW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTLB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTLQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTLD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTRW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTRB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTRQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KSHIFTRD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test + .KUNPCKBW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KUNPCKWD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KUNPCKDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXNORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXNORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXNORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXNORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + .KXORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + + // ---- 8.16 x87 FPU Encodings ---- + .FADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FADDP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FIADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSUBP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FISUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSUBRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FISUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FMULP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FIMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FDIVP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FIDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FDIVRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FIDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSQRT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FABS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FCHS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FPREM = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FPREM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FRNDINT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FSCALE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FXTRACT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FXAM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack + .FILD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack + .FBLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack + .FST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FIST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FISTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FISTTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FBSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) + .FXCH = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FCMOVB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS + .FCMOVE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS + .FCMOVBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS + .FCMOVU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS + .FCMOVNB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS + .FCMOVNE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS + .FCMOVNBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS + .FCMOVNU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS + .FCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FICOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FICOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS + .FCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS + .FUCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS + .FUCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS + .FUCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FUCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FUCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FTST = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS + .FLDZ = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLD1 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLDPI = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLDL2T = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLDL2E = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLDLG2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FLDLN2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack + .FSIN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FSINCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FPTAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FPATAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .F2XM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FYL2X = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FYL2XP1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FNINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FINCSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FDECSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FFREE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FFREEP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FNOP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FWAIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 + .FCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FNCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 + .FSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FNSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FLDCW = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + .FSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FNSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FLDENV = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + .FSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FNSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + .FSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory + .FNSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory + .FXSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FXSAVE64 = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory + .FXRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + .FXRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + + // ---- 8.17 System Instruction Encodings ---- + .LGDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load + .SGDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) + .LIDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load + .SIDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) + .LLDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load + .SLDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) + .LTR = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load + .STR = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) + .LMSW = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load + .SMSW = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) + .CLTS = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .ARPL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // legacy; adjusts RPL, sets ZF + .LAR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure + .LSL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure + .VERR = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable + .VERW = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable + .INVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .WBINVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .INVLPG = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .INVPCID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .RSM = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .RDMSR = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, // privileged; EDX:EAX <- MSR[ECX] + .WRMSR = {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; MSR[ECX] <- EDX:EAX + .VMCALL = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .VMLAUNCH = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMRESUME = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMXOFF = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .VMXON = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMCLEAR = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMPTRLD = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMPTRST = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .VMREAD = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF + .VMWRITE = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF + .VMFUNC = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled + .INVEPT = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + .INVVPID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + + // ---- 8.18 Security and Memory Protection Encodings ---- + .ENCLS = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX + .ENCLU = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX + .ENCLV = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX + .RDPKRU = {implicit_wr={.RAX}, implicit_rd={.RCX}}, // EAX <- PKRU (EDX cleared); reads ECX + .WRPKRU = {implicit_rd={.RAX, .RCX, .RDX}}, // PKRU <- EAX; ECX/EDX must be 0 + .INCSSPD = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP + .INCSSPQ = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP + .RDSSPD = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 + .RDSSPQ = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 + .SAVEPREVSSP = {side_effects={.CET}}, // CET shadow-stack management + .RSTORSSP = {side_effects={.CET}}, // CET shadow-stack management + .WRSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack + .WRSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack + .WRUSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack + .WRUSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack + .SETSSBSY = {side_effects={.CET}}, // CET shadow-stack management + .CLRSSBSY = {side_effects={.CET}}, // CET shadow-stack management + .ENDBR64 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like + .ENDBR32 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like + + // ---- 8.19 XSAVE/XRSTOR State Management Encodings ---- + .XSAVE = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XSAVE64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XRSTOR = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX + .XRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX + .XSAVEOPT = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XSAVEOPT64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XSAVEC = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XSAVEC64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX + .XSAVES = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX + .XSAVES64 = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX + .XRSTORS = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX + .XRSTORS64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX + + // ---- 8.20 Cache and Prefetch Encodings ---- + .PREFETCHT0 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + .PREFETCHT1 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + .PREFETCHT2 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + .PREFETCHNTA = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + .PREFETCHW = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + .CLFLUSHOPT = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber + .CLWB = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber + .CLDEMOTE = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + + // ---- 8.21 Atomic and Byte Swap Encodings ---- + .BSWAP = {written={.OP0}, read={.OP0}}, + .CMPXCHG = {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // ZF set on match; on mismatch RAX <- dest + .CMPXCHG8B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + .CMPXCHG16B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + .XADD = {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + + // ---- 8.22 Miscellaneous Encodings ---- + .BOUND = {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, // #BR if out of bounds + .ENTER = {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, // builds stack frame + .LEAVE = {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, + .XLAT = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] + .XLATB = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] + .MOVBE = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // byte-swapping load/store + .RDRAND = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + .RDSEED = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared +} diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index 108f7153d..9793858ee 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -3811,7 +3811,7 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, {.VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, }, - // AVX-512 scatter instructions (use M for VSIB addressing) + // AVX-512 scatter instructions (u. M for VSIB addressing) .VPSCATTERDD = { {.VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, {.VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 50c41129f..fbd0af645 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -62,6 +62,7 @@ BLOBS := [?]Blob{ {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin","Decode_Index"}, {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin","Decode_Index"}, + {"CLOBBER_TABLE", "x86.clobber_table.bin","Clobber"}, } DIR_GEN :: #directory + "/generated/" @@ -456,6 +457,7 @@ emit_writer :: proc() { strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "import tablegen \"..\"\n\n") strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n") strings.write_string(&sb, "\treturn (cast([^]u8)p)[:n]\n}\n\n") @@ -465,7 +467,11 @@ emit_writer :: proc() { strings.write_string(&sb, "\t\tos.exit(1)\n\t}\n}\n\n") strings.write_string(&sb, "main :: proc() {\n") for b in BLOBS { - fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + if b.global == "CLOBBER_TABLE" { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&tablegen.%s, size_of(tablegen.%s)))", b.file, b.global, b.global) + } else { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } } strings.write_string(&sb, "}\n") emit_file(DIR_GEN + "writer.odin", &sb) diff --git a/core/rexcode/isa/x86/tablegen/generated/writer.odin b/core/rexcode/isa/x86/tablegen/generated/writer.odin index 7a91efc83..85bcd8a48 100644 --- a/core/rexcode/isa/x86/tablegen/generated/writer.odin +++ b/core/rexcode/isa/x86/tablegen/generated/writer.odin @@ -8,6 +8,8 @@ package rexcode_x86_generated import "core:os" import "core:fmt" +import tablegen ".." + TABLES :: #directory + "/../../tables/" raw :: #force_inline proc "contextless" (p: rawptr, n: int) -> []u8 { @@ -40,4 +42,5 @@ main :: proc() { w(TABLES + "x86.evex_idx_0f.bin", raw(&EVEX_INDEX_0F, size_of(EVEX_INDEX_0F))) w(TABLES + "x86.evex_idx_0f38.bin", raw(&EVEX_INDEX_0F38, size_of(EVEX_INDEX_0F38))) w(TABLES + "x86.evex_idx_0f3a.bin", raw(&EVEX_INDEX_0F3A, size_of(EVEX_INDEX_0F3A))) + w(TABLES + "x86.clobber_table.bin", raw(&tablegen.CLOBBER_TABLE, size_of(tablegen.CLOBBER_TABLE))) } diff --git a/core/rexcode/isa/x86/tables.odin b/core/rexcode/isa/x86/tables.odin index 32a5c7af1..13482ddbc 100644 --- a/core/rexcode/isa/x86/tables.odin +++ b/core/rexcode/isa/x86/tables.odin @@ -94,6 +94,7 @@ Decode_Index :: struct { @(rodata) EVEX_INDEX_0F := #load("tables/x86.evex_idx_0f.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F38 := #load("tables/x86.evex_idx_0f38.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F3A := #load("tables/x86.evex_idx_0f3a.bin", []Decode_Index) +@(rodata) CLOBBER_TABLE := #load("tables/x86.clobber_table.bin", []Clobber) // ----------------------------------------------------------------------------- // Accessors diff --git a/core/rexcode/isa/x86/tables/x86.clobber_table.bin b/core/rexcode/isa/x86/tables/x86.clobber_table.bin new file mode 100644 index 0000000000000000000000000000000000000000..338d8d8572fd6b842e2e45eba9f8410e9e7a0160 GIT binary patch literal 19104 zcmZQT1B^@v0Y*j!27G)5GlYx;zkwFe*0?57WsC5YTI9Ht*D9}>P`|AXZ@ z5%!_+L25uofiWX84;0JDd~iU639wp-6cV41dJd2_B=zWg3p9BH0(^A!gzN`f4JJSa zGcXWRkM2HnKDzy+x>o_@3?%n}BL;~tfF@5!J-U8$KEgau-U1m8N}?bdKc5Ah7eVSE z>S26Xc%bo7%PU3(r1FXZoW4Ni*MEp{j7(5@JbXq_>DR!(!0?}ekwJkGR30)gAo0Pa zBQl?b5u_GkfdV)@Ss0<_Gb{qz2hk5w0g`uM-~lngco8TIf?1&S0n!Y@5CO2`A*miL zfX)Y%lc1anmIMbCNG}LOL^!~D5qt|Yz5xL~x_UzP4Yd0d(EP)M#uq^2qlXV6{pjYQ z^KqCD&K95;;RHt(qP_+d#>n+II-ihw4m9&D(D()f_~_~h**DPcQ$X_%6B=ItjgKBa zg!H4Eht9`tJ_CaZg9#{l85|((0jlsp^{E5cKM?aN;j1vHf?H28^C;yDGJs2VP&o)L zTqxy(+ye?gSol%O2bl$S7>EJI*!aj|pfVq-6ilJ>LFGMI0!kqBVdls~dQjd=hG7A?z0FeM!7}w&DVV^|XJi8@vSa{Lpdt;- z&}0w;34{0`FEJp=6XJvQBdG`TL56{=WCni!6W+*%tsDyP?VtaDF_d+`Fx1z809lCFpj+N zfMhNZ3Ce;<=?R)1Kr#?a8+mwf0JV=KJ_9o-{c=OvFrZ?DL_S7-qrU%1@(|l{JwuO=KR;6*U!&&3aww!e8*JeL zbKO9te~Q9m2=qrO4PT1FhhYB}y?(`0evOU?BG11;q7}KmAT@kI&2NJ7LwWfNaVUs{ zls_OA1QWprtrkJ8Kj~hd(l-4Q3Sac`6?8r!{ee2Q_fOi4{(O1_8p}0Rti-9# zn~yFJ;e$#W&549RXH9*g6fs{3f_7j8;ay+EJj^KmD;5+_6 zegR?FmJ~1>Vlsqmf>3a>304L}L>OUwXnThdc^@lC2}nQkeocrxVn-)P9;6P28=&SR znFn?g5+9}%OcS9VT|XKh5~8A0wxZoh%}V0&N$5%$59f@z3Y&vp~-XfU96&WCrbThNWjvpl~wqL-RMNd;pzy zgv^JW*My`VDLpVSf-1%X4A5QQ(BMA+2^El)-~eVsBpEDxNd5vThMw01W#-Ra7y$6PsvH0S literal 0 HcmV?d00001 From b9a7ed9942c123c185cb3e809e5e777690b316fa Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 11:33:07 +0100 Subject: [PATCH 41/92] Add amd64 clobber table to asm_tables_amd64.cpp --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 93 ++++- src/asm_tables_amd64.cpp | 365 ++++++++++++++++++ src/entity.cpp | 6 +- 3 files changed, 461 insertions(+), 3 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index a5705dde6..09c6cd4c7 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -13,8 +13,9 @@ import gen ".." ISA_NAME :: "amd64" main :: proc() { - raw_encode_runs := #load("../../tables/x86.encode_runs.bin", []x86.Encode_Run) - raw_encode_forms := #load("../../tables/x86.encode_forms.bin", []u8) + raw_encode_runs := #load("../../tables/x86.encode_runs.bin", []x86.Encode_Run) + raw_encode_forms := #load("../../tables/x86.encode_forms.bin", []u8) + raw_clobber_table := #load("../../tables/x86.clobber_table.bin", []u8) sb := strings.builder_make() @@ -128,6 +129,67 @@ main :: proc() { strings.write_string(&sb, "\t};\n") } } + strings.write_string(&sb, "\n"); + { + strings.write_string(&sb, "\tenum ClobberFlags : u16 {\n") + strings.write_string(&sb, "\t\tClobberFlag_CF = 1<<0,\n") + strings.write_string(&sb, "\t\tClobberFlag_PF = 1<<1,\n") + strings.write_string(&sb, "\t\tClobberFlag_AF = 1<<2,\n") + strings.write_string(&sb, "\t\tClobberFlag_ZF = 1<<3,\n") + strings.write_string(&sb, "\t\tClobberFlag_SF = 1<<4,\n") + strings.write_string(&sb, "\t\tClobberFlag_OF = 1<<5,\n") + strings.write_string(&sb, "\t\tClobberFlag_DF = 1<<6,\n") + strings.write_string(&sb, "\t\tClobberFlag_IF = 1<<7,\n") + strings.write_string(&sb, "\t\tClobberFlag_TF = 1<<8,\n") + strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, "\tenum SideEffectFlags : u16 {\n") + strings.write_string(&sb, "\t\tSideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK)\n") + strings.write_string(&sb, "\t\tSideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline)\n") + strings.write_string(&sb, "\t\tSideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR)\n") + strings.write_string(&sb, "\t\tSideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB)\n") + strings.write_string(&sb, "\t\tSideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND\n") + strings.write_string(&sb, "\t\tSideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate\n") + strings.write_string(&sb, "\t\tSideEffectFlag_HALT = 1<<6, // stops execution until an external event\n") + strings.write_string(&sb, "\t\tSideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state\n") + strings.write_string(&sb, "\t\tSideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns\n") + strings.write_string(&sb, "\t\tSideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops\n") + strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, "\tenum ClobberRegs : u16 {\n") + strings.write_string(&sb, "\t\tClobberReg_RAX = 1<<0, \n") + strings.write_string(&sb, "\t\tClobberReg_RBX = 1<<1, \n") + strings.write_string(&sb, "\t\tClobberReg_RCX = 1<<2, \n") + strings.write_string(&sb, "\t\tClobberReg_RDX = 1<<3, \n") + strings.write_string(&sb, "\t\tClobberReg_RSI = 1<<4, \n") + strings.write_string(&sb, "\t\tClobberReg_RDI = 1<<5, \n") + strings.write_string(&sb, "\t\tClobberReg_RSP = 1<<6, \n") + strings.write_string(&sb, "\t\tClobberReg_RBP = 1<<7, \n") + strings.write_string(&sb, "\t\tClobberReg_R11 = 1<<8,\n") + strings.write_string(&sb, "\t\tClobberReg_XMM0 = 1<<9, \n") + strings.write_string(&sb, "\t\tClobberReg_VECTOR = 1<<10, \n") + strings.write_string(&sb, "\t\tClobberReg_MXCSR = 1<<11, \n") + strings.write_string(&sb, "\t\tClobberReg_FPU_ST = 1<<12, \n") + strings.write_string(&sb, "\t\tClobberReg_FPU_SW = 1<<13,\n") + strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, "\tenum OperandSet : u8 { \n") + strings.write_string(&sb, "\t\tOperandSet_OP0 = 1<<0, \n") + strings.write_string(&sb, "\t\tOperandSet_OP1 = 1<<1, \n") + strings.write_string(&sb, "\t\tOperandSet_OP2 = 1<<2, \n") + strings.write_string(&sb, "\t\tOperandSet_OP3 = 1<<3,\n") + strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, "\tstruct Clobber {\n") + strings.write_string(&sb, "\t\tOperandSet written;\n") + strings.write_string(&sb, "\t\tOperandSet read;\n") + strings.write_string(&sb, "\t\tClobberRegs implicit_wr;\n") + strings.write_string(&sb, "\t\tClobberRegs implicit_rd;\n") + strings.write_string(&sb, "\t\tClobberFlags flags_wr;\n") + strings.write_string(&sb, "\t\tClobberFlags flags_undef;\n") + strings.write_string(&sb, "\t\tClobberFlags flags_rd;\n") + strings.write_string(&sb, "\t\tbool writes_mem;\n") + strings.write_string(&sb, "\t\tbool reads_mem;\n") + strings.write_string(&sb, "\t\tSideEffectFlags side_effects;\n") + strings.write_string(&sb, "\t};\n") + } + strings.write_string(&sb, "\n"); strings.write_string(&sb, "\tstatic u16 const register_codes[REG_COUNT];\n") @@ -217,6 +279,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs[%d];\n", len(raw_encode_runs)) fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms[%d];\n", len(raw_encode_forms)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_table[%d];\n", len(raw_clobber_table)) strings.write_string(&sb, "\tStringMap mnemonic_map;\n") strings.write_string(&sb, "\tStringMap prefix_map;\n") @@ -269,6 +332,13 @@ main :: proc() { strings.write_string(&sb, "\t\tEncoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms;\n") strings.write_string(&sb, "\t\treturn Slice{ENCODE_FORMS+r.start, r.count};\n") } + { + strings.write_string(&sb, "\tClobber clobber(/*Mnemonic*/ u16 m) const {\n") + defer strings.write_string(&sb, "\t}\n") + + strings.write_string(&sb, "\t\tClobber *c = cast(Clobber *)raw_clobber_table;\n") + strings.write_string(&sb, "\t\treturn c[m];\n") + } { strings.write_string(&sb, "\tu16 reg_class(/*Register*/ u16 r) const {\n") strings.write_string(&sb, "\t\treturn 0xFF00 & r;\n") @@ -606,6 +676,25 @@ main :: proc() { } defer strings.write_string(&sb, "\n"); } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_clobber_table[%d] = {{\n", ISA_NAME, len(raw_clobber_table)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_clobber_table { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n"); + } diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 2a4e6010d..3d4b35ba2 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -135,6 +135,65 @@ struct Asm_amd64 { REG_ST6, REG_ST7, REG_RIP, REG_COUNT }; + + enum ClobberFlags : u16 { + ClobberFlag_CF = 1<<0, + ClobberFlag_PF = 1<<1, + ClobberFlag_AF = 1<<2, + ClobberFlag_ZF = 1<<3, + ClobberFlag_SF = 1<<4, + ClobberFlag_OF = 1<<5, + ClobberFlag_DF = 1<<6, + ClobberFlag_IF = 1<<7, + ClobberFlag_TF = 1<<8, + }; + enum SideEffectFlags : u16 { + SideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK) + SideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline) + SideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR) + SideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB) + SideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND + SideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate + SideEffectFlag_HALT = 1<<6, // stops execution until an external event + SideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state + SideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns + SideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops + }; + enum ClobberRegs : u16 { + ClobberReg_RAX = 1<<0, + ClobberReg_RBX = 1<<1, + ClobberReg_RCX = 1<<2, + ClobberReg_RDX = 1<<3, + ClobberReg_RSI = 1<<4, + ClobberReg_RDI = 1<<5, + ClobberReg_RSP = 1<<6, + ClobberReg_RBP = 1<<7, + ClobberReg_R11 = 1<<8, + ClobberReg_XMM0 = 1<<9, + ClobberReg_VECTOR = 1<<10, + ClobberReg_MXCSR = 1<<11, + ClobberReg_FPU_ST = 1<<12, + ClobberReg_FPU_SW = 1<<13, + }; + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + struct Clobber { + OperandSet written; + OperandSet read; + ClobberRegs implicit_wr; + ClobberRegs implicit_rd; + ClobberFlags flags_wr; + ClobberFlags flags_undef; + ClobberFlags flags_rd; + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; + }; + static u16 const register_codes[REG_COUNT]; static String const register_strings[REG_COUNT]; @@ -251,6 +310,7 @@ struct Asm_amd64 { static EncodeRun const raw_encode_runs[1194]; static u8 const raw_encode_forms[38320]; + static u8 const raw_clobber_table[19104]; StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; @@ -286,6 +346,10 @@ struct Asm_amd64 { Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; return Slice{ENCODE_FORMS+r.start, r.count}; } + Clobber clobber(/*Mnemonic*/ u16 m) const { + Clobber *c = cast(Clobber *)raw_clobber_table; + return c[m]; + } u16 reg_class(/*Register*/ u16 r) const { return 0xFF00 & r; } @@ -1248,3 +1312,304 @@ u8 const Asm_amd64::raw_encode_forms[38320] = { 0xa7, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa8, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa8, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa8, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x08, 0x05, 0x00, 0xa9, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa9, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa9, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, }; +u8 const Asm_amd64::raw_clobber_table[19104] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 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0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/src/entity.cpp b/src/entity.cpp index 446947ef0..6a5991857 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -342,10 +342,14 @@ struct Entity { Ast *node; bool has_side_effects; bool is_align_stack; + + bool clobber_cc; + bool clobber_memory; + Array clobber_registers; + Scope *param_scope; Scope *label_scope; Array decls; - } AsmTemplate; }; }; From 2300a4878210940b8d712767636eb48c0fe5a885 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 12:45:48 +0100 Subject: [PATCH 42/92] Infer `#clobber memory` and `#clobber cc` from the mnemonics directly --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 12 +++++++++ src/asm_tables_amd64.cpp | 12 +++++++++ src/check_asm.cpp | 26 ++++++++++++++----- src/entity.cpp | 2 +- src/llvm_backend_asm.cpp | 16 ++++++++++++ 5 files changed, 60 insertions(+), 8 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 09c6cd4c7..1dbff1890 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -187,6 +187,18 @@ main :: proc() { strings.write_string(&sb, "\t\tbool writes_mem;\n") strings.write_string(&sb, "\t\tbool reads_mem;\n") strings.write_string(&sb, "\t\tSideEffectFlags side_effects;\n") + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\t\tbool implies_clobber_cc() {\n") + strings.write_string(&sb, "\t\t\tu16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF|\n") + strings.write_string(&sb, "\t\t\t ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF;\n") + strings.write_string(&sb, "\t\t\treturn ((flags_wr | flags_undef) & CC_MASK) != 0;\n") + strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\tbool implies_clobber_memory() {\n") + strings.write_string(&sb, "\t\t\treturn writes_mem || reads_mem ||\n") + strings.write_string(&sb, "\t\t\t\t(side_effects & (SideEffectFlag_FENCE |\n") + strings.write_string(&sb, "\t\t\t\t SideEffectFlag_CACHE |\n") + strings.write_string(&sb, "\t\t\t\t SideEffectFlag_SERIALIZING)) != 0;\n") + strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t};\n") } strings.write_string(&sb, "\n"); diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 3d4b35ba2..c5a722f14 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -192,6 +192,18 @@ struct Asm_amd64 { bool writes_mem; bool reads_mem; SideEffectFlags side_effects; + + bool implies_clobber_cc() { + u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| + ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; + return ((flags_wr | flags_undef) & CC_MASK) != 0; + } + bool implies_clobber_memory() { + return writes_mem || reads_mem || + (side_effects & (SideEffectFlag_FENCE | + SideEffectFlag_CACHE | + SideEffectFlag_SERIALIZING)) != 0; + } }; static u16 const register_codes[REG_COUNT]; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 7da9e22e4..b40e3b167 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -734,7 +734,9 @@ gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { template -gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInstruction *instr, u16 mnemonic, Slice const &operands, u8 previous_prefix, Ast *previous_prefix_instr) { +gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, + u16 mnemonic, Slice const &operands, + u8 previous_prefix, Ast *previous_prefix_instr) { GB_ASSERT(mnemonic > 0); auto forms = asm_ctx->encoding_forms(mnemonic); String name = asm_ctx->mnemonic_strings[mnemonic]; @@ -860,6 +862,15 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, AstAsmInst error(instr->name, "Asm prefix cannot be applied to '%.*s'", LIT(name)); } } + + GB_ASSERT(tmpl_entity->kind == Entity_AsmTemplate); + + // Handle clobbering from mnemonic + auto clobber = asm_ctx->clobber(mnemonic); + + tmpl_entity->AsmTemplate.clobber_cc |= clobber.implies_clobber_cc(); + tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); + tmpl_entity->AsmTemplate.has_side_effects |= clobber.side_effects != 0; return; } @@ -1260,12 +1271,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->type = type; + auto *clobber_registers_set = &entity->AsmTemplate.clobber_registers_set; + check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); { // check clobbers - StringSet reg_set = {}; - string_set_init(®_set, 16); - defer (string_set_destroy(®_set)); - bool clobber_cc = false; bool clobber_memory = false; @@ -1276,7 +1285,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity String reg = asm_reg->name.string; Operand operand = {}; if (check_register(asm_ctx, &operand, asm_reg)) { - if (string_set_update(®_set, reg)) { + if (string_set_update(clobber_registers_set, reg)) { error(clobber->value, "#clobber %%%.*s has already been defined", LIT(reg)); } } @@ -1302,6 +1311,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity break; } } + + entity->AsmTemplate.clobber_cc = clobber_cc; + entity->AsmTemplate.clobber_memory = clobber_memory; } // collect label decls @@ -1363,7 +1375,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity previous_prefix = cast(u8)mnemonic; previous_prefix_instr = instruction_; } else if (res == CheckMnemomic_Mnemonic) { - check_mnemonic(asm_ctx, ctx, instr, mnemonic, slice_from_array(operands), previous_prefix, previous_prefix_instr); + check_mnemonic(asm_ctx, ctx, entity, instr, mnemonic, slice_from_array(operands), previous_prefix, previous_prefix_instr); previous_prefix = 0; previous_prefix_instr = nullptr; } else { diff --git a/src/entity.cpp b/src/entity.cpp index 6a5991857..e5f31eb7b 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -345,7 +345,7 @@ struct Entity { bool clobber_cc; bool clobber_memory; - Array clobber_registers; + StringSet clobber_registers_set; Scope *param_scope; Scope *label_scope; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 530106ed2..108baab73 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -403,6 +403,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } } + bool memory_clobbered_already = false; // Pass 3: clobbers // Only the Scratch group. Unpinned register scratch was already emitted as an // output in Pass 1, so it is skipped here. @@ -427,12 +428,27 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { break; case AsmTemplateEntityDecl_Memory: // general memory clobber raw("~{memory}"); + memory_clobbered_already = true; break; default: GB_PANIC("asm: invalid scratch operand kind"); } } + // Template-level clobbers derived from #clobber cc / #clobber memory. + if (tmpl_entity->AsmTemplate.clobber_cc) { + sep(); + if (build_context.metrics.arch == TargetArch_amd64) { + raw("~{flags}"); // x86 EFLAGS condition codes + } else { + raw("~{cc}"); // AArch64 uses ~{cc} + } + } + if (tmpl_entity->AsmTemplate.clobber_memory && memory_clobbered_already) { + sep(); + raw("~{memory}"); + } + // Build the callee type // NOTE(bill): Even though the user has given a signature, this might not actually match what // LLVM requires it to be due to the scratch parameters and more, so many of the results might From b32846bb354c81831e60c18d149aa0039dd267a9 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 14:16:10 +0100 Subject: [PATCH 43/92] Minor change to `implies_side_effects` --- core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin | 3 +++ src/asm_tables_amd64.cpp | 3 +++ src/check_asm.cpp | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 1dbff1890..cb23e4666 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -199,6 +199,9 @@ main :: proc() { strings.write_string(&sb, "\t\t\t\t SideEffectFlag_CACHE |\n") strings.write_string(&sb, "\t\t\t\t SideEffectFlag_SERIALIZING)) != 0;\n") strings.write_string(&sb, "\t\t}\n") + strings.write_string(&sb, "\t\tbool implies_side_effects() {\n") + strings.write_string(&sb, "\t\t\treturn side_effects;\n") + strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t};\n") } strings.write_string(&sb, "\n"); diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index c5a722f14..f35abb5d3 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -204,6 +204,9 @@ struct Asm_amd64 { SideEffectFlag_CACHE | SideEffectFlag_SERIALIZING)) != 0; } + bool implies_side_effects() { + return side_effects; + } }; static u16 const register_codes[REG_COUNT]; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index b40e3b167..f60e85817 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -870,7 +870,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm tmpl_entity->AsmTemplate.clobber_cc |= clobber.implies_clobber_cc(); tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); - tmpl_entity->AsmTemplate.has_side_effects |= clobber.side_effects != 0; + tmpl_entity->AsmTemplate.has_side_effects |= clobber.implies_side_effects(); return; } From ecb4495e81970943985fa84a898d035fe35f1f1b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 14:29:59 +0100 Subject: [PATCH 44/92] Clobber manually specified registers --- src/llvm_backend_asm.cpp | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 108baab73..1803489b9 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -407,6 +407,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // Pass 3: clobbers // Only the Scratch group. Unpinned register scratch was already emitted as an // output in Pass 1, so it is skipped here. + StringSet emitted_reg_clobbers = {}; + string_set_init(&emitted_reg_clobbers); + defer (string_set_destroy(&emitted_reg_clobbers)); + for (isize i = 0; i < ops->count; i++) { AsmTemplateEntityDecl const &e = (*ops)[i]; @@ -425,6 +429,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { case AsmTemplateEntityDecl_Register: // pinned -> real clobber GB_ASSERT(e.pin.len != 0); raw("~{"); put(e.pin); raw("}"); + string_set_update(&emitted_reg_clobbers, e.pin); break; case AsmTemplateEntityDecl_Memory: // general memory clobber raw("~{memory}"); @@ -435,6 +440,17 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } } + // Explicit register clobbers from #clobber , deduped against the pinned + // scratch clobbers already emitted above. + for (String const ® : tmpl_entity->AsmTemplate.clobber_registers_set) { + if (string_set_exists(&emitted_reg_clobbers, reg)) { + continue; // already clobbered as a pinned scratch; don't double-emit + } + sep(); + raw("~{"); put(reg); raw("}"); + string_set_update(&emitted_reg_clobbers, reg); + } + // Template-level clobbers derived from #clobber cc / #clobber memory. if (tmpl_entity->AsmTemplate.clobber_cc) { sep(); @@ -444,7 +460,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { raw("~{cc}"); // AArch64 uses ~{cc} } } - if (tmpl_entity->AsmTemplate.clobber_memory && memory_clobbered_already) { + if (tmpl_entity->AsmTemplate.clobber_memory && !memory_clobbered_already) { sep(); raw("~{memory}"); } From 43f078aedc88dc707e34b8c283b8ac59714d1a50 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 14:52:37 +0100 Subject: [PATCH 45/92] Infer `asm #side_effects` where possible from the mnemonics --- .../isa/x86/tablegen/cpp-compiler/cpp-gen.odin | 13 ++++++++++++- src/asm_tables_amd64.cpp | 13 ++++++++++++- src/llvm_backend_asm.cpp | 9 +++------ 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index cb23e4666..e6a8a863f 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -200,7 +200,18 @@ main :: proc() { strings.write_string(&sb, "\t\t\t\t SideEffectFlag_SERIALIZING)) != 0;\n") strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t\tbool implies_side_effects() {\n") - strings.write_string(&sb, "\t\t\treturn side_effects;\n") + strings.write_string(&sb, "\t\t\tu16 const VOLATILE_SE =\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_FENCE |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_SERIALIZING |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CACHE |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_TRAP |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_INTERRUPT |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_HALT |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_PRIVILEGED |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CONTROL |\n") + strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CET;\n") + strings.write_string(&sb, "\t\t\t\t// NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd.\n") + strings.write_string(&sb, "\t\t\treturn ((side_effects & VOLATILE_SE) != 0);\n") strings.write_string(&sb, "\t\t}\n") strings.write_string(&sb, "\t};\n") } diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index f35abb5d3..8151ad8a4 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -205,7 +205,18 @@ struct Asm_amd64 { SideEffectFlag_SERIALIZING)) != 0; } bool implies_side_effects() { - return side_effects; + u16 const VOLATILE_SE = + SideEffectFlag_FENCE | + SideEffectFlag_SERIALIZING | + SideEffectFlag_CACHE | + SideEffectFlag_TRAP | + SideEffectFlag_INTERRUPT | + SideEffectFlag_HALT | + SideEffectFlag_PRIVILEGED | + SideEffectFlag_CONTROL | + SideEffectFlag_CET; + // NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd. + return ((side_effects & VOLATILE_SE) != 0); } }; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 1803489b9..406622921 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -480,21 +480,18 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMTypeRef fn_ty = LLVMFunctionType(ret_ty, param_types.data, cast(unsigned)param_types.count, /*vararg*/false); - // TODO(bill): determine all the cases when side-effects happen - bool has_side_effects = tmpl_node->has_side_effects; - LLVMValueRef ia = LLVMGetInlineAsm( fn_ty, asm_string, cast(size_t)gb_string_length(asm_string), constraints, cast(size_t)gb_string_length(constraints), - /*HasSideEffects*/ has_side_effects, - /*IsAlignStack*/ tmpl_node->is_align_stack, + /*HasSideEffects*/ tmpl_entity->AsmTemplate.has_side_effects, + /*IsAlignStack*/ tmpl_entity->AsmTemplate.is_align_stack, LLVMInlineAsmDialectATT, /*CanThrow*/ false); LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (false) { + if (true) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From 5197806f884cfca659dbc904ea6e8e35eb919496 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 15:42:36 +0100 Subject: [PATCH 46/92] Implement triple quote strings to allow for easier templating purposes --- src/parser.cpp | 6 +- src/string.cpp | 162 ++++++++++++++++++++++++++++++++++++++++++++++ src/tokenizer.cpp | 26 ++++++++ 3 files changed, 193 insertions(+), 1 deletion(-) diff --git a/src/parser.cpp b/src/parser.cpp index c8b1b0ace..f8e7193ad 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -854,7 +854,11 @@ gb_internal ExactValue exact_value_from_token(AstFile *f, Token const &token) { } break; case Token_String: - if (!unquote_string(ast_allocator(f), &s, 0, s.text[0] == '`')) { + if (s.len >= 3 && s.text[0] == '"' && s.text[1] == '"' && s.text[2] == '"') { + if (!unquote_string_triple(ast_allocator(f), &s, string_contains_char(s, '\r'))) { + syntax_error(token, "Invalid multi-line string literal"); + } + } else if (!unquote_string(ast_allocator(f), &s, 0, s.text[0] == '`')) { syntax_error(token, "Invalid string literal"); } break; diff --git a/src/string.cpp b/src/string.cpp index 199aa017f..26440f459 100644 --- a/src/string.cpp +++ b/src/string.cpp @@ -1234,6 +1234,168 @@ gb_internal i32 unquote_string(gbAllocator a, String *s_, u8 quote=0, bool has_c } +// Escape-process the already-delimiter-stripped body of a triple-quoted +// string. `force_new` is true when `s` already points at a freshly allocated +// buffer, so the "no escapes" fast path still reports a new allocation. +// +// 0 == failure +// 1 == original memory +// 2 == new allocation +gb_internal i32 unquote_string_triple_content(gbAllocator a, String *s_, String s, bool has_carriage_return, bool force_new) { + if (!string_contains_char(s, '\\')) { + if (has_carriage_return) { + *s_ = strip_carriage_return(a, s); + return 2; + } + *s_ = s; + return force_new ? 2 : 1; + } + if (has_carriage_return) { + s = strip_carriage_return(a, s); + } + u8 rune_temp[4] = {}; + isize buf_len = 3*s.len / 2 + 1; + u8 *buf = gb_alloc_array(a, u8, buf_len); + isize offset = 0; + while (s.len > 0) { + String tail_string = {}; + Rune r = 0; + bool multiple_bytes = false; + // NOTE: quote==0 makes unquote_char treat `"` as an ordinary byte + // (it only rejects a bare quote when quote is '"' or '\''), while + // `\\` escapes — including `\"` — are still handled. + bool success = unquote_char(s, 0, &r, &multiple_bytes, &tail_string); + if (!success) { + gb_free(a, buf); + return 0; + } + s = tail_string; + if (r < 0x80 || !multiple_bytes) { + buf[offset++] = cast(u8)r; + } else { + isize size = gb_utf8_encode_rune(rune_temp, r); + gb_memmove(buf+offset, rune_temp, size); + offset += size; + } + } + *s_ = make_string(buf, offset); + return 2; +} + +// Java-style triple-quoted string literal `"""..."""` with indentation stripping for the multi-line form. +// +// If the literal spans multiple lines, the whitespace preceding the closing +// `"""` on its own line determines the indentation removed from every content +// line, and the line breaks immediately after the opening `"""` and before the +// closing `"""` are excluded from the value. A single-line `"""..."""` keeps +// its content verbatim (aside from escape processing). Escapes are processed in +// both forms. +// +// 0 == failure +// 1 == original memory +// 2 == new allocation +gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carriage_return=false) { + String s = *s_; + isize n = s.len; + // Smallest valid literal is `""""""` (an empty string): 6 bytes. + if (n < 6) { + return 0; + } + if (!(s[0] == '"' && s[1] == '"' && s[2] == '"') || + !(s[n-1] == '"' && s[n-2] == '"' && s[n-3] == '"')) { + return 0; + } + + String body = make_string(s.text+3, s.len-6); + + // Single-line form: no newline, so no indentation handling. + if (!string_contains_char(body, '\n')) { + return unquote_string_triple_content(a, s_, body, has_carriage_return, false); + } + + + // The opening delimiter's line (everything up to the first newline) must + // contain only whitespace; content is not allowed on that line. + isize first_nl = 0; + while (body.text[first_nl] != '\n') { + first_nl += 1; + } + for (isize i = 0; i < first_nl; i++) { + u8 c = body.text[i]; + if (c != ' ' && c != '\t' && c != '\r') { + return 0; + } + } + + // The closing delimiter must sit on its own line; the whitespace between + // the final newline and the closing `"""` is the indentation to strip. + isize last_nl = body.len - 1; + while (body.text[last_nl] != '\n') { + last_nl -= 1; + } + String indent = make_string(body.text+last_nl+1, body.len-(last_nl+1)); + for (isize i = 0; i < indent.len; i++) { + u8 c = indent.text[i]; + if (c != ' ' && c != '\t') { + return 0; + } + } + + // The value is everything strictly between those two newlines. + String content = make_string(body.text+first_nl+1, last_nl-(first_nl+1)); + + // De-indent line by line into a fresh buffer (never larger than `content`). + u8 *dbuf = gb_alloc_array(a, u8, content.len+1); + isize dlen = 0; + isize li = 0; + for (;;) { + isize le = li; + while (le < content.len && content.text[le] != '\n') { + le += 1; + } + isize len = le - li; + if (len > 0 && content.text[li+len-1] == '\r') { + len -= 1; // normalize CRLF line endings + } + + bool blank = true; + for (isize k = 0; k < len; k++) { + u8 c = content.text[li+k]; + if (c != ' ' && c != '\t') { + blank = false; + break; + } + } + if (blank) { + // A whitespace-only line contributes an empty line. + } else { + if (len < indent.len) { + gb_free(a, dbuf); + return 0; // content line is less indented than the closing """ + } + for (isize k = 0; k < indent.len; k++) { + if (content.text[li+k] != indent.text[k]) { + gb_free(a, dbuf); + return 0; // indentation whitespace does not match + } + } + for (isize k = indent.len; k < len; k++) { + dbuf[dlen++] = content.text[li+k]; + } + } + + if (le >= content.len) { + break; + } + dbuf[dlen++] = '\n'; + li = le + 1; + } + + // Process escapes on the de-indented content (already a fresh buffer). + return unquote_string_triple_content(a, s_, make_string(dbuf, dlen), false, true); +} + + gb_internal bool string_is_valid_identifier(String str) { if (str.len <= 0) return false; diff --git a/src/tokenizer.cpp b/src/tokenizer.cpp index f505b142e..d8db328e4 100644 --- a/src/tokenizer.cpp +++ b/src/tokenizer.cpp @@ -793,6 +793,32 @@ gb_internal void tokenizer_get_token(Tokenizer *t, Token *token, int repeat=0) { Rune quote = curr_rune; token->kind = Token_String; if (curr_rune == '"') { + // NOTE(bill): Python-style triple-quoted string literal `"""..."""`. + if (t->curr_rune == '"' && peek_byte(t, 0) == '"') { + advance_to_next_rune(t); // consume the second opening `"` + advance_to_next_rune(t); // consume the third opening `"` + for (;;) { + Rune r = t->curr_rune; + if (r < 0) { + tokenizer_err(t, "Triple-quote multi-line string literal not terminated"); + break; + } + advance_to_next_rune(t); + // A closing `"""` is three consecutive quotes: `r` plus the + // next two runes. `t->curr_rune` is now the second quote and + // `peek_byte(t, 0)` is the third. + if (r == quote && t->curr_rune == '"' && peek_byte(t, 0) == '"') { + advance_to_next_rune(t); // consume the second closing `"` + advance_to_next_rune(t); // consume the third closing `"` + break; + } + if (r == '\\') { + scan_escape(t); + } + } + token->string.len = t->curr - token->string.text; + goto semicolon_check; + } for (;;) { Rune r = t->curr_rune; if (r == '\n' || r < 0) { From ae2c7ead48f420bef9e0cbfd42992e35dc9a7cfa Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 16:08:58 +0100 Subject: [PATCH 47/92] Support triple backtick strings --- src/parser.cpp | 4 +- src/string.cpp | 106 ++++++++++++++++++++++++++-------------------- src/tokenizer.cpp | 19 +++++++++ 3 files changed, 83 insertions(+), 46 deletions(-) diff --git a/src/parser.cpp b/src/parser.cpp index f8e7193ad..573566237 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -854,7 +854,9 @@ gb_internal ExactValue exact_value_from_token(AstFile *f, Token const &token) { } break; case Token_String: - if (s.len >= 3 && s.text[0] == '"' && s.text[1] == '"' && s.text[2] == '"') { + if (s.len >= 6 && + ((s.text[0] == '"' && s.text[1] == '"' && s.text[2] == '"') || + (s.text[0] == '`' && s.text[1] == '`' && s.text[2] == '`'))) { if (!unquote_string_triple(ast_allocator(f), &s, string_contains_char(s, '\r'))) { syntax_error(token, "Invalid multi-line string literal"); } diff --git a/src/string.cpp b/src/string.cpp index 26440f459..551a6250c 100644 --- a/src/string.cpp +++ b/src/string.cpp @@ -1233,7 +1233,6 @@ gb_internal i32 unquote_string(gbAllocator a, String *s_, u8 quote=0, bool has_c return 2; } - // Escape-process the already-delimiter-stripped body of a triple-quoted // string. `force_new` is true when `s` already points at a freshly allocated // buffer, so the "no escapes" fast path still reports a new allocation. @@ -1282,40 +1281,8 @@ gb_internal i32 unquote_string_triple_content(gbAllocator a, String *s_, String return 2; } -// Java-style triple-quoted string literal `"""..."""` with indentation stripping for the multi-line form. -// -// If the literal spans multiple lines, the whitespace preceding the closing -// `"""` on its own line determines the indentation removed from every content -// line, and the line breaks immediately after the opening `"""` and before the -// closing `"""` are excluded from the value. A single-line `"""..."""` keeps -// its content verbatim (aside from escape processing). Escapes are processed in -// both forms. -// -// 0 == failure -// 1 == original memory -// 2 == new allocation -gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carriage_return=false) { - String s = *s_; - isize n = s.len; - // Smallest valid literal is `""""""` (an empty string): 6 bytes. - if (n < 6) { - return 0; - } - if (!(s[0] == '"' && s[1] == '"' && s[2] == '"') || - !(s[n-1] == '"' && s[n-2] == '"' && s[n-3] == '"')) { - return 0; - } - - String body = make_string(s.text+3, s.len-6); - - // Single-line form: no newline, so no indentation handling. - if (!string_contains_char(body, '\n')) { - return unquote_string_triple_content(a, s_, body, has_carriage_return, false); - } - - - // The opening delimiter's line (everything up to the first newline) must - // contain only whitespace; content is not allowed on that line. +gb_internal bool triple_string_deindent(gbAllocator a, String body, String *out) { + // Opening delimiter's line (up to the first newline) must be blank. isize first_nl = 0; while (body.text[first_nl] != '\n') { first_nl += 1; @@ -1323,12 +1290,12 @@ gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carria for (isize i = 0; i < first_nl; i++) { u8 c = body.text[i]; if (c != ' ' && c != '\t' && c != '\r') { - return 0; + return false; } } - // The closing delimiter must sit on its own line; the whitespace between - // the final newline and the closing `"""` is the indentation to strip. + // Closing delimiter's line: whitespace after the final newline is the + // indentation prefix removed from each content line. isize last_nl = body.len - 1; while (body.text[last_nl] != '\n') { last_nl -= 1; @@ -1337,14 +1304,12 @@ gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carria for (isize i = 0; i < indent.len; i++) { u8 c = indent.text[i]; if (c != ' ' && c != '\t') { - return 0; + return false; } } - // The value is everything strictly between those two newlines. String content = make_string(body.text+first_nl+1, last_nl-(first_nl+1)); - // De-indent line by line into a fresh buffer (never larger than `content`). u8 *dbuf = gb_alloc_array(a, u8, content.len+1); isize dlen = 0; isize li = 0; @@ -1371,12 +1336,12 @@ gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carria } else { if (len < indent.len) { gb_free(a, dbuf); - return 0; // content line is less indented than the closing """ + return false; // content line is less indented than the closing delimiter } for (isize k = 0; k < indent.len; k++) { if (content.text[li+k] != indent.text[k]) { gb_free(a, dbuf); - return 0; // indentation whitespace does not match + return false; // indentation whitespace does not match } } for (isize k = indent.len; k < len; k++) { @@ -1391,12 +1356,63 @@ gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carria li = le + 1; } - // Process escapes on the de-indented content (already a fresh buffer). - return unquote_string_triple_content(a, s_, make_string(dbuf, dlen), false, true); + *out = make_string(dbuf, dlen); + return true; } +// Triple-quoted string literal, dispatching on the delimiter: +// `"` -> escapes processed; multi-line form is Java-style de-indented +// `\`` -> raw (no escapes); multi-line form is ALSO Java-style de-indented +// (carriage returns normalized), embedded single/double backticks +// are literal +// +// 0 == failure +// 1 == original memory +// 2 == new allocation +gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carriage_return=false) { + String s = *s_; + isize n = s.len; + if (n < 6) { + return 0; + } + u8 quote = s[0]; + if (quote != '"' && quote != '`') { + return 0; + } + if (!(s[0] == quote && s[1] == quote && s[2] == quote) || + !(s[n-1] == quote && s[n-2] == quote && s[n-3] == quote)) { + return 0; + } + String body = make_string(s.text+3, s.len-6); + bool raw = (quote == '`'); + // Single-line form: no indentation handling. + if (!string_contains_char(body, '\n')) { + if (raw) { + if (has_carriage_return) { + *s_ = strip_carriage_return(a, body); + return 2; + } + *s_ = body; + return 1; + } + return unquote_string_triple_content(a, s_, body, has_carriage_return, false); + } + + // Multi-line form: Java-style de-indentation for both delimiters. + String di = {}; + if (!triple_string_deindent(a, body, &di)) { + return 0; + } + if (raw) { + // Raw: the de-indented content is used verbatim (no escape processing). + *s_ = di; + return 2; + } + // Processed: run escape sequences on the de-indented content. + return unquote_string_triple_content(a, s_, di, false, true); +} gb_internal bool string_is_valid_identifier(String str) { if (str.len <= 0) return false; diff --git a/src/tokenizer.cpp b/src/tokenizer.cpp index d8db328e4..84d4d3041 100644 --- a/src/tokenizer.cpp +++ b/src/tokenizer.cpp @@ -834,6 +834,25 @@ gb_internal void tokenizer_get_token(Tokenizer *t, Token *token, int repeat=0) { } } } else { + if (t->curr_rune == '`' && peek_byte(t, 0) == '`') { + advance_to_next_rune(t); // consume the second opening ``` + advance_to_next_rune(t); // consume the third opening ``` + for (;;) { + Rune r = t->curr_rune; + if (r < 0) { + tokenizer_err(t, "Triple-quote multi-line string literal not terminated"); + break; + } + advance_to_next_rune(t); + if (r == quote && t->curr_rune == '`' && peek_byte(t, 0) == '`') { + advance_to_next_rune(t); // consume the second closing ``` + advance_to_next_rune(t); // consume the third closing ``` + break; + } + } + token->string.len = t->curr - token->string.text; + goto semicolon_check; + } for (;;) { Rune r = t->curr_rune; if (r < 0) { From 5eb023947480abc8f3a3964552b4c20341446c36 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 16:09:18 +0100 Subject: [PATCH 48/92] Utilize triple quote strings within the C++ asm table generation --- build.bat | 36 +- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 686 +++++++++--------- src/asm_tables_amd64.cpp | 55 +- 3 files changed, 387 insertions(+), 390 deletions(-) diff --git a/build.bat b/build.bat index cc9d6af05..95c8e528f 100644 --- a/build.bat +++ b/build.bat @@ -121,20 +121,38 @@ set linker_settings=%libs% %odin_res% %linker_flags% del *.pdb > NUL 2> NUL del *.ilk > NUL 2> NUL -rc %rc_flags% %odin_rc% +rem pushd core\rexcode\isa\x86\tablegen +rem W:\Odin\odin run . +rem W:\Odin\odin run generated +rem popd +rem if %errorlevel% neq 0 goto end_of_build + + +pushd core\rexcode\isa\x86\tablegen\cpp-compiler + W:\Odin\odin run . +popd +if %errorlevel% neq 0 goto end_of_build + +rem goto end_of_build + +rem rc %rc_flags% %odin_rc% cl %compiler_settings% "src\main.cpp" "src\libtommath.cpp" /link %linker_settings% -OUT:%exe_name% if %errorlevel% neq 0 goto end_of_build -mt -nologo -inputresource:%exe_name%;#1 -manifest misc\odin.manifest -outputresource:%exe_name%;#1 -validate_manifest -identity:"odin, processorArchitecture=amd64, version=%odin_version_full%, type=win32" -if %errorlevel% neq 0 goto end_of_build +rem mt -nologo -inputresource:%exe_name%;#1 -manifest misc\odin.manifest -outputresource:%exe_name%;#1 -validate_manifest -identity:"odin, processorArchitecture=amd64, version=%odin_version_full%, type=win32" +rem if %errorlevel% neq 0 goto end_of_build -call build_vendor.bat -if %errorlevel% neq 0 goto end_of_build +rem call build_vendor.bat +rem if %errorlevel% neq 0 goto end_of_build + +rem rem If the demo doesn't run for you and your CPU is more than a decade old, try -microarch:native +rem if %release_mode% EQU 0 odin run examples/demo -vet -strict-style -resource:examples/demo/demo.rc -- Hellope World + +rem rem Many non-compiler devs seem to run debug build but don't realize. +rem if %release_mode% EQU 0 echo: & echo Debug compiler built. Note: run "build.bat release" if you want a faster, release mode compiler. + +W:\Odin\odin run examples/bug -rem If the demo doesn't run for you and your CPU is more than a decade old, try -microarch:native -if %release_mode% EQU 0 odin run examples/demo -vet -strict-style -resource:examples/demo/demo.rc -- Hellope World -rem Many non-compiler devs seem to run debug build but don't realize. -if %release_mode% EQU 0 echo: & echo Debug compiler built. Note: run "build.bat release" if you want a faster, release mode compiler. del *.obj > NUL 2> NUL diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index e6a8a863f..13416af60 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -19,15 +19,18 @@ main :: proc() { sb := strings.builder_make() - strings.write_string(&sb, "// =============================================================================\n") - strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") - strings.write_string(&sb, "// =============================================================================\n") - strings.write_string(&sb, "//\n") - strings.write_string(&sb, "// Produces a C++ equivalent of the encoding table from core:rexcode written in Odin\n") - strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") - strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") - strings.write_string(&sb, "// odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals\n") - strings.write_string(&sb, "//\n\n\n") + strings.write_string(&sb, """ + // ============================================================================= + // GENERATED FILE - DO NOT EDIT + // ============================================================================= + // + // Produces a C++ equivalent of the encoding table from core:rexcode written in Odin + // odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file + // odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin + // odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals + // + \n\n + """) // strings.write_string(&sb, "struct Asm_a @@ -91,24 +94,25 @@ main :: proc() { { strings.write_string(&sb, "\n"); - strings.write_string(&sb, "\t// Register classes (upper byte)\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_NONE = 0x000;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR64 = 0x100;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR32 = 0x200;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR16 = 0x300;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR8 = 0x400;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_XMM = 0x600;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_YMM = 0x700;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_ZMM = 0x800;\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_K = 0x900; // opmask\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_SEG = 0xA00; // segment\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_CR = 0xB00; // control\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_DR = 0xC00; // debug\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_BND = 0xD00; // bound\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_MM = 0xE00; // MMX\n") - strings.write_string(&sb, "\tstatic const u16 REG_CLASS_ST = 0xF00; // x87 FPU\n") - strings.write_string(&sb, "\n"); + strings.write_string(&sb, """ + static const u16 REG_CLASS_NONE = 0x000; + static const u16 REG_CLASS_GPR64 = 0x100; + static const u16 REG_CLASS_GPR32 = 0x200; + static const u16 REG_CLASS_GPR16 = 0x300; + static const u16 REG_CLASS_GPR8 = 0x400; + static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs + static const u16 REG_CLASS_XMM = 0x600; + static const u16 REG_CLASS_YMM = 0x700; + static const u16 REG_CLASS_ZMM = 0x800; + static const u16 REG_CLASS_K = 0x900; // opmask + static const u16 REG_CLASS_SEG = 0xA00; // segment + static const u16 REG_CLASS_CR = 0xB00; // control + static const u16 REG_CLASS_DR = 0xC00; // debug + static const u16 REG_CLASS_BND = 0xD00; // bound + static const u16 REG_CLASS_MM = 0xE00; // MMX + static const u16 REG_CLASS_ST = 0xF00; // x87 FPU + \n + """) { count := uint(0) ROW_COUNT :: 16 @@ -131,89 +135,91 @@ main :: proc() { } strings.write_string(&sb, "\n"); { - strings.write_string(&sb, "\tenum ClobberFlags : u16 {\n") - strings.write_string(&sb, "\t\tClobberFlag_CF = 1<<0,\n") - strings.write_string(&sb, "\t\tClobberFlag_PF = 1<<1,\n") - strings.write_string(&sb, "\t\tClobberFlag_AF = 1<<2,\n") - strings.write_string(&sb, "\t\tClobberFlag_ZF = 1<<3,\n") - strings.write_string(&sb, "\t\tClobberFlag_SF = 1<<4,\n") - strings.write_string(&sb, "\t\tClobberFlag_OF = 1<<5,\n") - strings.write_string(&sb, "\t\tClobberFlag_DF = 1<<6,\n") - strings.write_string(&sb, "\t\tClobberFlag_IF = 1<<7,\n") - strings.write_string(&sb, "\t\tClobberFlag_TF = 1<<8,\n") - strings.write_string(&sb, "\t};\n") - strings.write_string(&sb, "\tenum SideEffectFlags : u16 {\n") - strings.write_string(&sb, "\t\tSideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK)\n") - strings.write_string(&sb, "\t\tSideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline)\n") - strings.write_string(&sb, "\t\tSideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR)\n") - strings.write_string(&sb, "\t\tSideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB)\n") - strings.write_string(&sb, "\t\tSideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND\n") - strings.write_string(&sb, "\t\tSideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate\n") - strings.write_string(&sb, "\t\tSideEffectFlag_HALT = 1<<6, // stops execution until an external event\n") - strings.write_string(&sb, "\t\tSideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state\n") - strings.write_string(&sb, "\t\tSideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns\n") - strings.write_string(&sb, "\t\tSideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops\n") - strings.write_string(&sb, "\t};\n") - strings.write_string(&sb, "\tenum ClobberRegs : u16 {\n") - strings.write_string(&sb, "\t\tClobberReg_RAX = 1<<0, \n") - strings.write_string(&sb, "\t\tClobberReg_RBX = 1<<1, \n") - strings.write_string(&sb, "\t\tClobberReg_RCX = 1<<2, \n") - strings.write_string(&sb, "\t\tClobberReg_RDX = 1<<3, \n") - strings.write_string(&sb, "\t\tClobberReg_RSI = 1<<4, \n") - strings.write_string(&sb, "\t\tClobberReg_RDI = 1<<5, \n") - strings.write_string(&sb, "\t\tClobberReg_RSP = 1<<6, \n") - strings.write_string(&sb, "\t\tClobberReg_RBP = 1<<7, \n") - strings.write_string(&sb, "\t\tClobberReg_R11 = 1<<8,\n") - strings.write_string(&sb, "\t\tClobberReg_XMM0 = 1<<9, \n") - strings.write_string(&sb, "\t\tClobberReg_VECTOR = 1<<10, \n") - strings.write_string(&sb, "\t\tClobberReg_MXCSR = 1<<11, \n") - strings.write_string(&sb, "\t\tClobberReg_FPU_ST = 1<<12, \n") - strings.write_string(&sb, "\t\tClobberReg_FPU_SW = 1<<13,\n") - strings.write_string(&sb, "\t};\n") - strings.write_string(&sb, "\tenum OperandSet : u8 { \n") - strings.write_string(&sb, "\t\tOperandSet_OP0 = 1<<0, \n") - strings.write_string(&sb, "\t\tOperandSet_OP1 = 1<<1, \n") - strings.write_string(&sb, "\t\tOperandSet_OP2 = 1<<2, \n") - strings.write_string(&sb, "\t\tOperandSet_OP3 = 1<<3,\n") - strings.write_string(&sb, "\t};\n") - strings.write_string(&sb, "\tstruct Clobber {\n") - strings.write_string(&sb, "\t\tOperandSet written;\n") - strings.write_string(&sb, "\t\tOperandSet read;\n") - strings.write_string(&sb, "\t\tClobberRegs implicit_wr;\n") - strings.write_string(&sb, "\t\tClobberRegs implicit_rd;\n") - strings.write_string(&sb, "\t\tClobberFlags flags_wr;\n") - strings.write_string(&sb, "\t\tClobberFlags flags_undef;\n") - strings.write_string(&sb, "\t\tClobberFlags flags_rd;\n") - strings.write_string(&sb, "\t\tbool writes_mem;\n") - strings.write_string(&sb, "\t\tbool reads_mem;\n") - strings.write_string(&sb, "\t\tSideEffectFlags side_effects;\n") - strings.write_string(&sb, "\n") - strings.write_string(&sb, "\t\tbool implies_clobber_cc() {\n") - strings.write_string(&sb, "\t\t\tu16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF|\n") - strings.write_string(&sb, "\t\t\t ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF;\n") - strings.write_string(&sb, "\t\t\treturn ((flags_wr | flags_undef) & CC_MASK) != 0;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\tbool implies_clobber_memory() {\n") - strings.write_string(&sb, "\t\t\treturn writes_mem || reads_mem ||\n") - strings.write_string(&sb, "\t\t\t\t(side_effects & (SideEffectFlag_FENCE |\n") - strings.write_string(&sb, "\t\t\t\t SideEffectFlag_CACHE |\n") - strings.write_string(&sb, "\t\t\t\t SideEffectFlag_SERIALIZING)) != 0;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\tbool implies_side_effects() {\n") - strings.write_string(&sb, "\t\t\tu16 const VOLATILE_SE =\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_FENCE |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_SERIALIZING |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CACHE |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_TRAP |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_INTERRUPT |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_HALT |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_PRIVILEGED |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CONTROL |\n") - strings.write_string(&sb, "\t\t\t\tSideEffectFlag_CET;\n") - strings.write_string(&sb, "\t\t\t\t// NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd.\n") - strings.write_string(&sb, "\t\t\treturn ((side_effects & VOLATILE_SE) != 0);\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t};\n") + strings.write_string(&sb, """ + enum ClobberFlags : u16 { + ClobberFlag_CF = 1<<0, + ClobberFlag_PF = 1<<1, + ClobberFlag_AF = 1<<2, + ClobberFlag_ZF = 1<<3, + ClobberFlag_SF = 1<<4, + ClobberFlag_OF = 1<<5, + ClobberFlag_DF = 1<<6, + ClobberFlag_IF = 1<<7, + ClobberFlag_TF = 1<<8, + }; + enum SideEffectFlags : u16 { + SideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK) + SideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline) + SideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR) + SideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB) + SideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND + SideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate + SideEffectFlag_HALT = 1<<6, // stops execution until an external event + SideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state + SideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns + SideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops + }; + enum ClobberRegs : u16 { + ClobberReg_RAX = 1<<0, + ClobberReg_RBX = 1<<1, + ClobberReg_RCX = 1<<2, + ClobberReg_RDX = 1<<3, + ClobberReg_RSI = 1<<4, + ClobberReg_RDI = 1<<5, + ClobberReg_RSP = 1<<6, + ClobberReg_RBP = 1<<7, + ClobberReg_R11 = 1<<8, + ClobberReg_XMM0 = 1<<9, + ClobberReg_VECTOR = 1<<10, + ClobberReg_MXCSR = 1<<11, + ClobberReg_FPU_ST = 1<<12, + ClobberReg_FPU_SW = 1<<13, + }; + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + struct Clobber { + OperandSet written; + OperandSet read; + ClobberRegs implicit_wr; + ClobberRegs implicit_rd; + ClobberFlags flags_wr; + ClobberFlags flags_undef; + ClobberFlags flags_rd; + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; + + bool implies_clobber_cc() { + u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| + ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; + return ((flags_wr | flags_undef) & CC_MASK) != 0; + } + bool implies_clobber_memory() { + return writes_mem || reads_mem || + (side_effects & (SideEffectFlag_FENCE | + SideEffectFlag_CACHE | + SideEffectFlag_SERIALIZING)) != 0; + } + bool implies_side_effects() { + u16 const VOLATILE_SE = + SideEffectFlag_FENCE | + SideEffectFlag_SERIALIZING | + SideEffectFlag_CACHE | + SideEffectFlag_TRAP | + SideEffectFlag_INTERRUPT | + SideEffectFlag_HALT | + SideEffectFlag_PRIVILEGED | + SideEffectFlag_CONTROL | + SideEffectFlag_CET; + // NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd. + return ((side_effects & VOLATILE_SE) != 0); + } + }; + """) } strings.write_string(&sb, "\n"); @@ -249,15 +255,15 @@ main :: proc() { defer strings.write_string(&sb, "\t#pragma pack(pop)\n") strings.write_string(&sb, "\tstruct Encoding {\n") defer strings.write_string(&sb, "\t};\n") - strings.write_string(&sb, "\t\tMnemonic mnemonic;\n") - strings.write_string(&sb, "\t\tOperandType ops[4];\n") - strings.write_string(&sb, "\t\tOperandEncoding enc[4];\n") - strings.write_string(&sb, "\t\tu8 opcode;\n") - strings.write_string(&sb, "\t\tu8 ext;\n") - strings.write_string(&sb, "\t\tEncodingFlags flags;\n") - - - strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + Mnemonic mnemonic; + OperandType ops[4]; + OperandEncoding enc[4]; + u8 opcode; + u8 ext; + EncodingFlags flags; + \n + """) Encoding_Flags :: type_of(gen.Encoding{}.flags) { @@ -311,244 +317,226 @@ main :: proc() { strings.write_string(&sb, "\tStringMap prefix_map;\n") strings.write_string(&sb, "\tStringMap register_map;\n") - { - strings.write_string(&sb, "\tbool init() {\n") - defer strings.write_string(&sb, "\t}\n") + strings.write_string(&sb, """ - strings.write_string(&sb, "\t\tstring_map_init(&mnemonic_map, MNEMONIC_COUNT*2);\n") - strings.write_string(&sb, "\t\tfor (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) {\n") - strings.write_string(&sb, "\t\t\tstring_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m);\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\tstring_map_init(&prefix_map, PREFIX_COUNT*2);\n") - strings.write_string(&sb, "\t\tfor (u8 r = PREFIX_INVALID+1; r < PREFIX_COUNT; r++) {\n") - strings.write_string(&sb, "\t\t\tstring_map_set(&prefix_map, prefix_strings[r], cast(Prefix)r);\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\tstring_map_init(®ister_map, REG_COUNT*2);\n") - strings.write_string(&sb, "\t\tfor (u16 r = REG_INVALID+1; r < REG_COUNT; r++) {\n") - strings.write_string(&sb, "\t\t\tstring_map_set(®ister_map, register_strings[r], cast(Register)r);\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn true;\n") - } - { - strings.write_string(&sb, "\tMnemonic mnemonic_lookup(String const &name) {\n") - defer strings.write_string(&sb, "\t}\n") + bool init() { + string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); + for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { + string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); + } + string_map_init(&prefix_map, PREFIX_COUNT*2); + for (u8 r = PREFIX_INVALID+1; r < PREFIX_COUNT; r++) { + string_map_set(&prefix_map, prefix_strings[r], cast(Prefix)r); + } + string_map_init(®ister_map, REG_COUNT*2); + for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_strings[r], cast(Register)r); + } + return true; + } - strings.write_string(&sb, "\t\tMnemonic *found = string_map_get(&mnemonic_map, name);\n") - strings.write_string(&sb, "\t\treturn found ? *found : M_INVALID;\n") - } - { - strings.write_string(&sb, "\tPrefix prefix_lookup(String const &name) {\n") - defer strings.write_string(&sb, "\t}\n") + Mnemonic mnemonic_lookup(String const &name) { + Mnemonic *found = string_map_get(&mnemonic_map, name); + return found ? *found : M_INVALID; + } + Prefix prefix_lookup(String const &name) { + Prefix *found = string_map_get(&prefix_map, name); + return found ? *found : PREFIX_INVALID; + } + Register register_lookup(String const &name) { + Register *found = string_map_get(®ister_map, name); + return found ? *found : REG_INVALID; + } + Slice encoding_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; + return Slice{ENCODE_FORMS+r.start, r.count}; + } + Clobber clobber(/*Mnemonic*/ u16 m) const { + Clobber *c = cast(Clobber *)raw_clobber_table; + return c[m]; + } + u16 reg_class(/*Register*/ u16 r) const { + return 0xFF00 & r; + } + // size in bits for register + u16 reg_size(Register r) const { + switch (reg_class(register_codes[r])) { + case REG_CLASS_GPR64: return 64; + case REG_CLASS_GPR32: return 32; + case REG_CLASS_GPR16: return 16; + case REG_CLASS_GPR8: return 8; + case REG_CLASS_GPR8H: return 8; + case REG_CLASS_XMM: return 128; + case REG_CLASS_YMM: return 256; + case REG_CLASS_ZMM: return 512; + case REG_CLASS_K: return 64; + case REG_CLASS_MM: return 64; + case REG_CLASS_ST: return 80; + case REG_CLASS_SEG: return 16; + case REG_CLASS_CR: return 64; + case REG_CLASS_DR: return 64; + case REG_CLASS_BND: return 128; + } + return 0; + } + """) + strings.write_string(&sb, "\n\n") - strings.write_string(&sb, "\t\tPrefix *found = string_map_get(&prefix_map, name);\n") - strings.write_string(&sb, "\t\treturn found ? *found : PREFIX_INVALID;\n") - } - { - strings.write_string(&sb, "\tRegister register_lookup(String const &name) {\n") - defer strings.write_string(&sb, "\t}\n") + strings.write_string(&sb, """ + AsmOperandKind kind_from_operand_type(OperandType type) { + switch (type) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_SREG: case OP_CR: case OP_DR: + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_MM: case OP_K: case OP_STI: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + case OP_ST0_IMPL: case OP_XMM0_IMPL: + return AsmOperand_Register; + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_MM_M64: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmOperand_Register_Or_Memory; + case OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64: + case OP_M80: case OP_M128: case OP_M256: case OP_M512: + case OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64: + case OP_M16_16: case OP_M16_32: case OP_M16_64: + return AsmOperand_Memory; + case OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64: + case OP_IMM8SX: + case OP_ONE_IMPL: + case OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64: + return AsmOperand_Immediate; + case OP_REL8: case OP_REL32: + return AsmOperand_Label; + case OP_NONE: + default: + return AsmOperand_Invalid; + } + } + """) + strings.write_string(&sb, "\n\n") - strings.write_string(&sb, "\t\tRegister *found = string_map_get(®ister_map, name);\n") - strings.write_string(&sb, "\t\treturn found ? *found : REG_INVALID;\n") - } - { - strings.write_string(&sb, "\tSlice encoding_forms(/*Mnemonic*/ u16 m) const {\n") - defer strings.write_string(&sb, "\t}\n") + strings.write_string(&sb, """ + bool operand_type_is_implicit(OperandType t) { + switch (t) { + case OP_AL_IMPL: case OP_AX_IMPL: + case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + case OP_ONE_IMPL: + case OP_ST0_IMPL: case OP_XMM0_IMPL: + return true; + } + return false; + } + """) - strings.write_string(&sb, "\t\tEncodeRun r = raw_encode_runs[m];\n") - strings.write_string(&sb, "\t\tEncoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms;\n") - strings.write_string(&sb, "\t\treturn Slice{ENCODE_FORMS+r.start, r.count};\n") - } - { - strings.write_string(&sb, "\tClobber clobber(/*Mnemonic*/ u16 m) const {\n") - defer strings.write_string(&sb, "\t}\n") + strings.write_string(&sb, "\n\n") - strings.write_string(&sb, "\t\tClobber *c = cast(Clobber *)raw_clobber_table;\n") - strings.write_string(&sb, "\t\treturn c[m];\n") - } - { - strings.write_string(&sb, "\tu16 reg_class(/*Register*/ u16 r) const {\n") - strings.write_string(&sb, "\t\treturn 0xFF00 & r;\n") - strings.write_string(&sb, "\t}\n") - } - { - strings.write_string(&sb, "\t// size in bits for register\n") - strings.write_string(&sb, "\tu16 reg_size(Register r) const {\n") - strings.write_string(&sb, "\t\tswitch (reg_class(register_codes[r])) {\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_GPR64: return 64;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_GPR32: return 32;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_GPR16: return 16;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_GPR8: return 8;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_GPR8H: return 8;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_XMM: return 128;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_YMM: return 256;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_ZMM: return 512;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_K: return 64;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_MM: return 64;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_ST: return 80;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_SEG: return 16;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_CR: return 64;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_DR: return 64;\n") - strings.write_string(&sb, "\t\tcase REG_CLASS_BND: return 128;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn 0;\n") - strings.write_string(&sb, "\t}\n") - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tAsmOperandKind kind_from_operand_type(OperandType type) {\n") - strings.write_string(&sb, "\t\tswitch (type) {\n") - strings.write_string(&sb, "\t\tcase OP_R8: case OP_R16: case OP_R32: case OP_R64:\n") - strings.write_string(&sb, "\t\tcase OP_SREG: case OP_CR: case OP_DR:\n") - strings.write_string(&sb, "\t\tcase OP_XMM: case OP_YMM: case OP_ZMM:\n") - strings.write_string(&sb, "\t\tcase OP_MM: case OP_K: case OP_STI:\n") - strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_ST0_IMPL: case OP_XMM0_IMPL:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Register;\n") - strings.write_string(&sb, "\t\tcase OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64:\n") - strings.write_string(&sb, "\t\tcase OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128:\n") - strings.write_string(&sb, "\t\tcase OP_YMM_M256: case OP_ZMM_M512:\n") - strings.write_string(&sb, "\t\tcase OP_MM_M64:\n") - strings.write_string(&sb, "\t\tcase OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Register_Or_Memory;\n") - strings.write_string(&sb, "\t\tcase OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64:\n") - strings.write_string(&sb, "\t\tcase OP_M80: case OP_M128: case OP_M256: case OP_M512:\n") - strings.write_string(&sb, "\t\tcase OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64:\n") - strings.write_string(&sb, "\t\tcase OP_M16_16: case OP_M16_32: case OP_M16_64:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Memory;\n") - strings.write_string(&sb, "\t\tcase OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64:\n") - strings.write_string(&sb, "\t\tcase OP_IMM8SX:\n") - strings.write_string(&sb, "\t\tcase OP_ONE_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Immediate;\n") - strings.write_string(&sb, "\t\tcase OP_REL8: case OP_REL32:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Label;\n") - strings.write_string(&sb, "\t\tcase OP_NONE:\n") - strings.write_string(&sb, "\t\tdefault:\n") - strings.write_string(&sb, "\t\t\treturn AsmOperand_Invalid;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t}\n") - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tbool operand_type_is_implicit(OperandType t) {\n") - strings.write_string(&sb, "\t\tswitch (t) {\n") - strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_EAX_IMPL: case OP_RAX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_ONE_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_ST0_IMPL: case OP_XMM0_IMPL:\n") - strings.write_string(&sb, "\t\t\treturn true;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn false;\n") - strings.write_string(&sb, "\t}\n") - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tAsmRegClass operand_type_reg_class(OperandType t) {\n") - strings.write_string(&sb, "\t\tswitch (t) {\n") - strings.write_string(&sb, "\t\tcase OP_R8: case OP_R16: case OP_R32: case OP_R64:\n") - strings.write_string(&sb, "\t\tcase OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64:\n") - strings.write_string(&sb, "\t\tcase OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL:\n") - strings.write_string(&sb, "\t\tcase OP_CL_IMPL: case OP_DX_IMPL:\n") - strings.write_string(&sb, "\t\t\treturn AsmRegClass_Integer;\n") - strings.write_string(&sb, "\t\tcase OP_XMM: case OP_YMM: case OP_ZMM:\n") - strings.write_string(&sb, "\t\tcase OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128:\n") - strings.write_string(&sb, "\t\tcase OP_YMM_M256: case OP_ZMM_M512:\n") - strings.write_string(&sb, "\t\tcase OP_XMM0_IMPL:\n") - strings.write_string(&sb, "\t\t\treturn AsmRegClass_Vector; // xmm/ymm/zmm; float scalars also land here (see note)\n") - strings.write_string(&sb, "\t\tcase OP_K:\n") - strings.write_string(&sb, "\t\tcase OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64:\n") - strings.write_string(&sb, "\t\t\treturn AsmRegClass_Mask;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn AsmRegClass_Unknown; // OP_M*, OP_IMM*, OP_REL*, OP_SREG/CR/DR/MM/STi, moffs, ptr, m16_16... : no GPR/XMM class constraint here\n") - strings.write_string(&sb, "\t}\n") - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tu16 operand_type_bit_width(OperandType t) {\n") - strings.write_string(&sb, "\t\tswitch (t) {\n") - strings.write_string(&sb, "\t\tcase OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8;\n") - strings.write_string(&sb, "\t\tcase OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16;\n") - strings.write_string(&sb, "\t\tcase OP_R32: case OP_RM32: case OP_M32: case OP_EAX_IMPL: case OP_XMM_M32: case OP_K_M32: return 32;\n") - strings.write_string(&sb, "\t\tcase OP_R64: case OP_RM64: case OP_M64: case OP_RAX_IMPL: case OP_XMM_M64: case OP_K_M64: case OP_MM: case OP_MM_M64: return 64;\n") - strings.write_string(&sb, "\t\tcase OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128;\n") - strings.write_string(&sb, "\t\tcase OP_M256: case OP_YMM: case OP_YMM_M256: return 256;\n") - strings.write_string(&sb, "\t\tcase OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512;\n") - strings.write_string(&sb, "\t\tcase OP_IMM8: return 8;\n") - strings.write_string(&sb, "\t\tcase OP_IMM16: return 16;\n") - strings.write_string(&sb, "\t\tcase OP_IMM32: return 32;\n") - strings.write_string(&sb, "\t\tcase OP_IMM64: return 64;\n") - strings.write_string(&sb, "\t\tcase OP_REL8: return 8;\n") - strings.write_string(&sb, "\t\tcase OP_REL32: return 32;\n") - strings.write_string(&sb, "\t\tcase OP_IMM8SX: return 8;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc.\n") - strings.write_string(&sb, "\t}\n") - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tint form_explicit_slot(Encoding const &form, int explicit_index) {\n") - strings.write_string(&sb, "\t\tint seen = 0;\n") - strings.write_string(&sb, "\t\tfor (int j = 0; j < gb_count_of(form.ops); j++) {\n") - strings.write_string(&sb, "\t\t\tauto t = form.ops[j];\n") - strings.write_string(&sb, "\t\t\tif (!t) {\n") - strings.write_string(&sb, "\t\t\t\tbreak;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\t\tif (operand_type_is_implicit(t)) {\n") - strings.write_string(&sb, "\t\t\t\tcontinue;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\t\tif (seen == explicit_index) {\n") - strings.write_string(&sb, "\t\t\t\treturn j;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\t\tseen += 1;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn -1;\n") - strings.write_string(&sb, "\t}\n") - - } - strings.write_string(&sb, "\n") - { - strings.write_string(&sb, "\tbool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) {\n") - strings.write_string(&sb, "\t\tPrefixKind kind = PrefixKind_None;\n") - strings.write_string(&sb, "\t\tif (prefix != 0) {\n") - strings.write_string(&sb, "\t\t\tswitch (prefix) {\n") - strings.write_string(&sb, "\t\t\tcase PREFIX_LOCK: kind = PrefixKind_Lock; break;\n") - strings.write_string(&sb, "\t\t\tcase PREFIX_REP: kind = PrefixKind_Rep; break;\n") - strings.write_string(&sb, "\t\t\tcase PREFIX_REPNE: kind = PrefixKind_Repne; break;\n") - strings.write_string(&sb, "\t\t\tdefault: kind = PrefixKind_Other; break;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\tswitch (kind) {\n") - strings.write_string(&sb, "\t\tcase PrefixKind_Lock:\n") - strings.write_string(&sb, "\t\t\tif (!form.lock_ok()) {\n") - strings.write_string(&sb, "\t\t\t\treturn false;\n") - strings.write_string(&sb, "\t\t\t} else {\n") - strings.write_string(&sb, "\t\t\t\tif (requires_memory_dest_) *requires_memory_dest_ = true;\n") - strings.write_string(&sb, "\t\t\t\treturn true;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\tcase PrefixKind_Rep:\n") - strings.write_string(&sb, "\t\t\tif (!form.rep_ok()) {\n") - strings.write_string(&sb, "\t\t\t\treturn false;\n") - strings.write_string(&sb, "\t\t\t} else {\n") - strings.write_string(&sb, "\t\t\t\treturn true;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\tcase PrefixKind_Repne:\n") - strings.write_string(&sb, "\t\t\tif (!form.rep_ok()) {\n") - strings.write_string(&sb, "\t\t\t\treturn false;\n") - strings.write_string(&sb, "\t\t\t} else {\n") - strings.write_string(&sb, "\t\t\t\treturn true;\n") - strings.write_string(&sb, "\t\t\t}\n") - strings.write_string(&sb, "\t\tcase PrefixKind_Other:\n") - strings.write_string(&sb, "\t\tcase PrefixKind_None:\n") - strings.write_string(&sb, "\t\t\treturn true;\n") - strings.write_string(&sb, "\t\t}\n") - strings.write_string(&sb, "\t\treturn true;\n") - strings.write_string(&sb, "\t}\n") - } + strings.write_string(&sb, """ + AsmRegClass operand_type_reg_class(OperandType t) { + switch (t) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + return AsmRegClass_Integer; + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_XMM0_IMPL: + return AsmRegClass_Vector; // xmm/ymm/zmm; float scalars also land here (see note) + case OP_K: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmRegClass_Mask; + } + return AsmRegClass_Unknown; // OP_M*, OP_IMM*, OP_REL*, OP_SREG/CR/DR/MM/STi, moffs, ptr, m16_16... : no GPR/XMM class constraint here + } + """) - strings.write_string(&sb, "};\n") + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + u16 operand_type_bit_width(OperandType t) { + switch (t) { + case OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8; + case OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16; + case OP_R32: case OP_RM32: case OP_M32: case OP_EAX_IMPL: case OP_XMM_M32: case OP_K_M32: return 32; + case OP_R64: case OP_RM64: case OP_M64: case OP_RAX_IMPL: case OP_XMM_M64: case OP_K_M64: case OP_MM: case OP_MM_M64: return 64; + case OP_M128: case OP_XMM: case OP_XMM_M128: case OP_XMM0_IMPL: return 128; + case OP_M256: case OP_YMM: case OP_YMM_M256: return 256; + case OP_M512: case OP_ZMM: case OP_ZMM_M512: return 512; + case OP_IMM8: return 8; + case OP_IMM16: return 16; + case OP_IMM32: return 32; + case OP_IMM64: return 64; + case OP_REL8: return 8; + case OP_REL32: return 32; + case OP_IMM8SX: return 8; + } + return 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc. + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + int form_explicit_slot(Encoding const &form, int explicit_index) { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) { + PrefixKind kind = PrefixKind_None; + if (prefix != 0) { + switch (prefix) { + case PREFIX_LOCK: kind = PrefixKind_Lock; break; + case PREFIX_REP: kind = PrefixKind_Rep; break; + case PREFIX_REPNE: kind = PrefixKind_Repne; break; + default: kind = PrefixKind_Other; break; + } + } + switch (kind) { + case PrefixKind_Lock: + if (!form.lock_ok()) { + return false; + } + if (requires_memory_dest_) *requires_memory_dest_ = true; + return true; + case PrefixKind_Rep: + return form.rep_ok(); + case PrefixKind_Repne: + return form.rep_ok(); + case PrefixKind_Other: + case PrefixKind_None: + return true; + } + return true; + } + """) + + strings.write_string(&sb, "\n};\n") strings.write_string(&sb, "\n\n\n") diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 8151ad8a4..2b6d9ea4d 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -100,7 +100,6 @@ struct Asm_amd64 { enum PrefixKind : u8 { PrefixKind_None, PrefixKind_Lock, PrefixKind_Rep, PrefixKind_Repne, PrefixKind_Other }; - // Register classes (upper byte) static const u16 REG_CLASS_NONE = 0x000; static const u16 REG_CLASS_GPR64 = 0x100; static const u16 REG_CLASS_GPR32 = 0x200; @@ -117,7 +116,7 @@ struct Asm_amd64 { static const u16 REG_CLASS_BND = 0xD00; // bound static const u16 REG_CLASS_MM = 0xE00; // MMX static const u16 REG_CLASS_ST = 0xF00; // x87 FPU - + enum Register : u16 { REG_INVALID, REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, REG_EAX, REG_ECX, REG_EDX, REG_EBX, REG_ESP, REG_EBP, REG_ESI, REG_EDI, REG_R8D, REG_R9D, REG_R10D, REG_R11D, REG_R12D, REG_R13D, REG_R14D, @@ -160,25 +159,25 @@ struct Asm_amd64 { SideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops }; enum ClobberRegs : u16 { - ClobberReg_RAX = 1<<0, - ClobberReg_RBX = 1<<1, - ClobberReg_RCX = 1<<2, - ClobberReg_RDX = 1<<3, - ClobberReg_RSI = 1<<4, - ClobberReg_RDI = 1<<5, - ClobberReg_RSP = 1<<6, - ClobberReg_RBP = 1<<7, + ClobberReg_RAX = 1<<0, + ClobberReg_RBX = 1<<1, + ClobberReg_RCX = 1<<2, + ClobberReg_RDX = 1<<3, + ClobberReg_RSI = 1<<4, + ClobberReg_RDI = 1<<5, + ClobberReg_RSP = 1<<6, + ClobberReg_RBP = 1<<7, ClobberReg_R11 = 1<<8, - ClobberReg_XMM0 = 1<<9, - ClobberReg_VECTOR = 1<<10, - ClobberReg_MXCSR = 1<<11, - ClobberReg_FPU_ST = 1<<12, + ClobberReg_XMM0 = 1<<9, + ClobberReg_VECTOR = 1<<10, + ClobberReg_MXCSR = 1<<11, + ClobberReg_FPU_ST = 1<<12, ClobberReg_FPU_SW = 1<<13, }; - enum OperandSet : u8 { - OperandSet_OP0 = 1<<0, - OperandSet_OP1 = 1<<1, - OperandSet_OP2 = 1<<2, + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, OperandSet_OP3 = 1<<3, }; struct Clobber { @@ -219,7 +218,6 @@ struct Asm_amd64 { return ((side_effects & VOLATILE_SE) != 0); } }; - static u16 const register_codes[REG_COUNT]; static String const register_strings[REG_COUNT]; @@ -340,6 +338,7 @@ struct Asm_amd64 { StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; + bool init() { string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { @@ -355,6 +354,7 @@ struct Asm_amd64 { } return true; } + Mnemonic mnemonic_lookup(String const &name) { Mnemonic *found = string_map_get(&mnemonic_map, name); return found ? *found : M_INVALID; @@ -518,22 +518,13 @@ struct Asm_amd64 { case PrefixKind_Lock: if (!form.lock_ok()) { return false; - } else { - if (requires_memory_dest_) *requires_memory_dest_ = true; - return true; } + if (requires_memory_dest_) *requires_memory_dest_ = true; + return true; case PrefixKind_Rep: - if (!form.rep_ok()) { - return false; - } else { - return true; - } + return form.rep_ok(); case PrefixKind_Repne: - if (!form.rep_ok()) { - return false; - } else { - return true; - } + return form.rep_ok(); case PrefixKind_Other: case PrefixKind_None: return true; From 8f389578de2dc49d170dbcbba97e608b1f83797e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 16:17:49 +0100 Subject: [PATCH 49/92] Revert build.bat --- build.bat | 38 ++++++++++---------------------------- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/build.bat b/build.bat index 95c8e528f..0f08af87a 100644 --- a/build.bat +++ b/build.bat @@ -121,39 +121,21 @@ set linker_settings=%libs% %odin_res% %linker_flags% del *.pdb > NUL 2> NUL del *.ilk > NUL 2> NUL -rem pushd core\rexcode\isa\x86\tablegen -rem W:\Odin\odin run . -rem W:\Odin\odin run generated -rem popd -rem if %errorlevel% neq 0 goto end_of_build - - -pushd core\rexcode\isa\x86\tablegen\cpp-compiler - W:\Odin\odin run . -popd -if %errorlevel% neq 0 goto end_of_build - -rem goto end_of_build - -rem rc %rc_flags% %odin_rc% +rc %rc_flags% %odin_rc% cl %compiler_settings% "src\main.cpp" "src\libtommath.cpp" /link %linker_settings% -OUT:%exe_name% if %errorlevel% neq 0 goto end_of_build -rem mt -nologo -inputresource:%exe_name%;#1 -manifest misc\odin.manifest -outputresource:%exe_name%;#1 -validate_manifest -identity:"odin, processorArchitecture=amd64, version=%odin_version_full%, type=win32" -rem if %errorlevel% neq 0 goto end_of_build +mt -nologo -inputresource:%exe_name%;#1 -manifest misc\odin.manifest -outputresource:%exe_name%;#1 -validate_manifest -identity:"odin, processorArchitecture=amd64, version=%odin_version_full%, type=win32" +if %errorlevel% neq 0 goto end_of_build -rem call build_vendor.bat -rem if %errorlevel% neq 0 goto end_of_build - -rem rem If the demo doesn't run for you and your CPU is more than a decade old, try -microarch:native -rem if %release_mode% EQU 0 odin run examples/demo -vet -strict-style -resource:examples/demo/demo.rc -- Hellope World - -rem rem Many non-compiler devs seem to run debug build but don't realize. -rem if %release_mode% EQU 0 echo: & echo Debug compiler built. Note: run "build.bat release" if you want a faster, release mode compiler. - -W:\Odin\odin run examples/bug +call build_vendor.bat +if %errorlevel% neq 0 goto end_of_build +rem If the demo doesn't run for you and your CPU is more than a decade old, try -microarch:native +if %release_mode% EQU 0 odin run examples/demo -vet -strict-style -resource:examples/demo/demo.rc -- Hellope World +rem Many non-compiler devs seem to run debug build but don't realize. +if %release_mode% EQU 0 echo: & echo Debug compiler built. Note: run "build.bat release" if you want a faster, release mode compiler. del *.obj > NUL 2> NUL -:end_of_build +:end_of_build \ No newline at end of file From dbe5761bb04b3e4fabd02073c6ffb4ea4e69d855 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 16:19:58 +0100 Subject: [PATCH 50/92] Minor change --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 170 +++++++++--------- 1 file changed, 84 insertions(+), 86 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 13416af60..29fb8f98a 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -134,93 +134,91 @@ main :: proc() { } } strings.write_string(&sb, "\n"); - { - strings.write_string(&sb, """ - enum ClobberFlags : u16 { - ClobberFlag_CF = 1<<0, - ClobberFlag_PF = 1<<1, - ClobberFlag_AF = 1<<2, - ClobberFlag_ZF = 1<<3, - ClobberFlag_SF = 1<<4, - ClobberFlag_OF = 1<<5, - ClobberFlag_DF = 1<<6, - ClobberFlag_IF = 1<<7, - ClobberFlag_TF = 1<<8, - }; - enum SideEffectFlags : u16 { - SideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK) - SideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline) - SideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR) - SideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB) - SideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND - SideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate - SideEffectFlag_HALT = 1<<6, // stops execution until an external event - SideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state - SideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns - SideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops - }; - enum ClobberRegs : u16 { - ClobberReg_RAX = 1<<0, - ClobberReg_RBX = 1<<1, - ClobberReg_RCX = 1<<2, - ClobberReg_RDX = 1<<3, - ClobberReg_RSI = 1<<4, - ClobberReg_RDI = 1<<5, - ClobberReg_RSP = 1<<6, - ClobberReg_RBP = 1<<7, - ClobberReg_R11 = 1<<8, - ClobberReg_XMM0 = 1<<9, - ClobberReg_VECTOR = 1<<10, - ClobberReg_MXCSR = 1<<11, - ClobberReg_FPU_ST = 1<<12, - ClobberReg_FPU_SW = 1<<13, - }; - enum OperandSet : u8 { - OperandSet_OP0 = 1<<0, - OperandSet_OP1 = 1<<1, - OperandSet_OP2 = 1<<2, - OperandSet_OP3 = 1<<3, - }; - struct Clobber { - OperandSet written; - OperandSet read; - ClobberRegs implicit_wr; - ClobberRegs implicit_rd; - ClobberFlags flags_wr; - ClobberFlags flags_undef; - ClobberFlags flags_rd; - bool writes_mem; - bool reads_mem; - SideEffectFlags side_effects; + strings.write_string(&sb, """ + enum ClobberFlags : u16 { + ClobberFlag_CF = 1<<0, + ClobberFlag_PF = 1<<1, + ClobberFlag_AF = 1<<2, + ClobberFlag_ZF = 1<<3, + ClobberFlag_SF = 1<<4, + ClobberFlag_OF = 1<<5, + ClobberFlag_DF = 1<<6, + ClobberFlag_IF = 1<<7, + ClobberFlag_TF = 1<<8, + }; + enum SideEffectFlags : u16 { + SideEffectFlag_FENCE = 1<<0, // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK) + SideEffectFlag_SERIALIZING = 1<<1, // architecturally serializing (drains pipeline) + SideEffectFlag_HINT = 1<<2, // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR) + SideEffectFlag_CACHE = 1<<3, // cache-line maintenance with coherence effects (CLFLUSH/CLWB) + SideEffectFlag_TRAP = 1<<4, // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND + SideEffectFlag_INTERRUPT = 1<<5, // software interrupt / syscall gate + SideEffectFlag_HALT = 1<<6, // stops execution until an external event + SideEffectFlag_PRIVILEGED = 1<<7, // requires CPL0 / reads-writes supervisor machine state + SideEffectFlag_CONTROL = 1<<8, // alters control flow (writes RIP): branches, calls, returns + SideEffectFlag_CET = 1<<9, // control-flow-enforcement: landing pads, shadow-stack ops + }; + enum ClobberRegs : u16 { + ClobberReg_RAX = 1<<0, + ClobberReg_RBX = 1<<1, + ClobberReg_RCX = 1<<2, + ClobberReg_RDX = 1<<3, + ClobberReg_RSI = 1<<4, + ClobberReg_RDI = 1<<5, + ClobberReg_RSP = 1<<6, + ClobberReg_RBP = 1<<7, + ClobberReg_R11 = 1<<8, + ClobberReg_XMM0 = 1<<9, + ClobberReg_VECTOR = 1<<10, + ClobberReg_MXCSR = 1<<11, + ClobberReg_FPU_ST = 1<<12, + ClobberReg_FPU_SW = 1<<13, + }; + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + struct Clobber { + OperandSet written; + OperandSet read; + ClobberRegs implicit_wr; + ClobberRegs implicit_rd; + ClobberFlags flags_wr; + ClobberFlags flags_undef; + ClobberFlags flags_rd; + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; - bool implies_clobber_cc() { - u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| - ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; - return ((flags_wr | flags_undef) & CC_MASK) != 0; - } - bool implies_clobber_memory() { - return writes_mem || reads_mem || - (side_effects & (SideEffectFlag_FENCE | - SideEffectFlag_CACHE | - SideEffectFlag_SERIALIZING)) != 0; - } - bool implies_side_effects() { - u16 const VOLATILE_SE = - SideEffectFlag_FENCE | - SideEffectFlag_SERIALIZING | - SideEffectFlag_CACHE | - SideEffectFlag_TRAP | - SideEffectFlag_INTERRUPT | - SideEffectFlag_HALT | - SideEffectFlag_PRIVILEGED | - SideEffectFlag_CONTROL | - SideEffectFlag_CET; - // NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd. - return ((side_effects & VOLATILE_SE) != 0); - } - }; - """) - } + bool implies_clobber_cc() { + u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| + ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; + return ((flags_wr | flags_undef) & CC_MASK) != 0; + } + bool implies_clobber_memory() { + return writes_mem || reads_mem || + (side_effects & (SideEffectFlag_FENCE | + SideEffectFlag_CACHE | + SideEffectFlag_SERIALIZING)) != 0; + } + bool implies_side_effects() { + u16 const VOLATILE_SE = + SideEffectFlag_FENCE | + SideEffectFlag_SERIALIZING | + SideEffectFlag_CACHE | + SideEffectFlag_TRAP | + SideEffectFlag_INTERRUPT | + SideEffectFlag_HALT | + SideEffectFlag_PRIVILEGED | + SideEffectFlag_CONTROL | + SideEffectFlag_CET; + // NOTE: SideEffectFlag_HINT deliberately excluded — inert, may be DCE'd. + return ((side_effects & VOLATILE_SE) != 0); + } + }; + """) strings.write_string(&sb, "\n"); From 39c5e69f829db01ac02e986b8984488e6ba8d9e4 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 16:23:31 +0100 Subject: [PATCH 51/92] Move `determine_asm_operand_kind` upwards --- src/check_asm.cpp | 59 +++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index f60e85817..494a01c7a 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -52,6 +52,35 @@ gb_internal AsmRegClass check_asm_reg_class_from_type(Type *type) { return AsmRegClass_Unknown; } +gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { + if (operand->mode == Addressing_Constant) { + return AsmOperand_Immediate; + } + Ast *expr = operand->expr; + switch (expr->kind) { + case_ast_node(label, AsmLabelDecl, expr); + return AsmOperand_Label; + case_end; + case_ast_node(reg, AsmRegister, expr); + return AsmOperand_Register; + case_end; + case_ast_node(reg, AsmMemoryOperand, expr); + return AsmOperand_Memory; + case_end; + case_ast_node(ident, Ident, expr); + // TODO(bill): Is this correct? + if (expr->tav.mode == Addressing_Constant) { + return AsmOperand_Immediate; + } + Entity *e = entity_of_node(expr); + if (e != nullptr && e->kind == Entity_Variable && (e->flags & EntityFlag_PolyConst) != 0) { + return AsmOperand_Immediate; + } + return AsmOperand_Register; + case_end; + } + return AsmOperand_Invalid; +} enum AsmMismatch : u8 { AsmMismatch_None, @@ -702,36 +731,6 @@ gb_internal CheckMnemomicResult check_mnemonic_name(AsmCtx *asm_ctx, AstAsmInstr return CheckMnemomic_Invalid; } -gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { - if (operand->mode == Addressing_Constant) { - return AsmOperand_Immediate; - } - Ast *expr = operand->expr; - switch (expr->kind) { - case_ast_node(label, AsmLabelDecl, expr); - return AsmOperand_Label; - case_end; - case_ast_node(reg, AsmRegister, expr); - return AsmOperand_Register; - case_end; - case_ast_node(reg, AsmMemoryOperand, expr); - return AsmOperand_Memory; - case_end; - case_ast_node(ident, Ident, expr); - // TODO(bill): Is this correct? - if (expr->tav.mode == Addressing_Constant) { - return AsmOperand_Immediate; - } - Entity *e = entity_of_node(expr); - if (e != nullptr && e->kind == Entity_Variable && (e->flags & EntityFlag_PolyConst) != 0) { - return AsmOperand_Immediate; - } - return AsmOperand_Register; - case_end; - } - return AsmOperand_Invalid; -} - template gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tmpl_entity, AstAsmInstruction *instr, From 5768668af9f790fe28e8cec199f2e2a8d9b66e49 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 20:52:26 +0100 Subject: [PATCH 52/92] Add did you mean for registers --- src/check_asm.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 494a01c7a..b159ef1a8 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -684,7 +684,17 @@ gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegiste return true; } + + ERROR_BLOCK(); error(asm_reg->name, "Unknown register for this target platform: %%%.*s", LIT(name)); + { + auto dym = did_you_mean_make(heap_allocator(), asm_ctx->register_map.count, name); + defer (did_you_mean_destroy(&dym)); + for (auto const &entry : asm_ctx->register_map) { + did_you_mean_append(&dym, entry.key); + } + check_did_you_mean_print(&dym); + } return false; } From 08f3be70cf3f837161e093cd5f296a970ee89201 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 21:18:10 +0100 Subject: [PATCH 53/92] Add helper methods to the asm_tables_amd64.cpp --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 39 +++++++++++++++++++ src/asm_tables_amd64.cpp | 39 +++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 29fb8f98a..2d5386edc 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -180,6 +180,45 @@ main :: proc() { OperandSet_OP2 = 1<<2, OperandSet_OP3 = 1<<3, }; + + u16 clobber_bit_for_reg_name(String const &pin) { + static const struct { String name; u16 bit; } table[] = { + {str_lit(\"rax\"), ClobberReg_RAX}, {str_lit(\"eax\"), ClobberReg_RAX}, {str_lit(\"ax\"), ClobberReg_RAX}, {str_lit(\"al\"), ClobberReg_RAX}, {str_lit(\"ah\"), ClobberReg_RAX}, + {str_lit(\"rbx\"), ClobberReg_RBX}, {str_lit(\"ebx\"), ClobberReg_RBX}, {str_lit(\"bx\"), ClobberReg_RBX}, {str_lit(\"bl\"), ClobberReg_RBX}, {str_lit(\"bh\"), ClobberReg_RBX}, + {str_lit(\"rcx\"), ClobberReg_RCX}, {str_lit(\"ecx\"), ClobberReg_RCX}, {str_lit(\"cx\"), ClobberReg_RCX}, {str_lit(\"cl\"), ClobberReg_RCX}, {str_lit(\"ch\"), ClobberReg_RCX}, + {str_lit(\"rdx\"), ClobberReg_RDX}, {str_lit(\"edx\"), ClobberReg_RDX}, {str_lit(\"dx\"), ClobberReg_RDX}, {str_lit(\"dl\"), ClobberReg_RDX}, {str_lit(\"dh\"), ClobberReg_RDX}, + {str_lit(\"rsi\"), ClobberReg_RSI}, {str_lit(\"esi\"), ClobberReg_RSI}, {str_lit(\"si\"), ClobberReg_RSI}, {str_lit(\"sil\"), ClobberReg_RSI}, + {str_lit(\"rdi\"), ClobberReg_RDI}, {str_lit(\"edi\"), ClobberReg_RDI}, {str_lit(\"di\"), ClobberReg_RDI}, {str_lit(\"dil\"), ClobberReg_RDI}, + {str_lit(\"rsp\"), ClobberReg_RSP}, {str_lit(\"esp\"), ClobberReg_RSP}, + {str_lit(\"rbp\"), ClobberReg_RBP}, {str_lit(\"ebp\"), ClobberReg_RBP}, + {str_lit(\"r11\"), ClobberReg_R11}, {str_lit(\"r11d\"), ClobberReg_R11}, + {str_lit(\"r11w\"), ClobberReg_R11}, {str_lit(\"r11b\"), ClobberReg_R11}, + {str_lit(\"xmm0\"), ClobberReg_XMM0}, + }; + for (auto const &t : table) { + if (pin == t.name) { + return t.bit; + } + } + return 0; + } + + char const *clobber_reg_bit_name(u16 bit) { + switch (bit) { + case ClobberReg_RAX: return \"rax\"; + case ClobberReg_RBX: return \"rbx\"; + case ClobberReg_RCX: return \"rcx\"; + case ClobberReg_RDX: return \"rdx\"; + case ClobberReg_RSI: return \"rsi\"; + case ClobberReg_RDI: return \"rdi\"; + case ClobberReg_RSP: return \"rsp\"; + case ClobberReg_RBP: return \"rbp\"; + case ClobberReg_R11: return \"r11\"; + case ClobberReg_XMM0: return \"xmm0\"; + } + return \"\"; + } + struct Clobber { OperandSet written; OperandSet read; diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 2b6d9ea4d..be0425c77 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -180,6 +180,45 @@ struct Asm_amd64 { OperandSet_OP2 = 1<<2, OperandSet_OP3 = 1<<3, }; + + u16 clobber_bit_for_reg_name(String const &pin) { + static const struct { String name; u16 bit; } table[] = { + {str_lit("rax"), ClobberReg_RAX}, {str_lit("eax"), ClobberReg_RAX}, {str_lit("ax"), ClobberReg_RAX}, {str_lit("al"), ClobberReg_RAX}, {str_lit("ah"), ClobberReg_RAX}, + {str_lit("rbx"), ClobberReg_RBX}, {str_lit("ebx"), ClobberReg_RBX}, {str_lit("bx"), ClobberReg_RBX}, {str_lit("bl"), ClobberReg_RBX}, {str_lit("bh"), ClobberReg_RBX}, + {str_lit("rcx"), ClobberReg_RCX}, {str_lit("ecx"), ClobberReg_RCX}, {str_lit("cx"), ClobberReg_RCX}, {str_lit("cl"), ClobberReg_RCX}, {str_lit("ch"), ClobberReg_RCX}, + {str_lit("rdx"), ClobberReg_RDX}, {str_lit("edx"), ClobberReg_RDX}, {str_lit("dx"), ClobberReg_RDX}, {str_lit("dl"), ClobberReg_RDX}, {str_lit("dh"), ClobberReg_RDX}, + {str_lit("rsi"), ClobberReg_RSI}, {str_lit("esi"), ClobberReg_RSI}, {str_lit("si"), ClobberReg_RSI}, {str_lit("sil"), ClobberReg_RSI}, + {str_lit("rdi"), ClobberReg_RDI}, {str_lit("edi"), ClobberReg_RDI}, {str_lit("di"), ClobberReg_RDI}, {str_lit("dil"), ClobberReg_RDI}, + {str_lit("rsp"), ClobberReg_RSP}, {str_lit("esp"), ClobberReg_RSP}, + {str_lit("rbp"), ClobberReg_RBP}, {str_lit("ebp"), ClobberReg_RBP}, + {str_lit("r11"), ClobberReg_R11}, {str_lit("r11d"), ClobberReg_R11}, + {str_lit("r11w"), ClobberReg_R11}, {str_lit("r11b"), ClobberReg_R11}, + {str_lit("xmm0"), ClobberReg_XMM0}, + }; + for (auto const &t : table) { + if (pin == t.name) { + return t.bit; + } + } + return 0; + } + + char const *clobber_reg_bit_name(u16 bit) { + switch (bit) { + case ClobberReg_RAX: return "rax"; + case ClobberReg_RBX: return "rbx"; + case ClobberReg_RCX: return "rcx"; + case ClobberReg_RDX: return "rdx"; + case ClobberReg_RSI: return "rsi"; + case ClobberReg_RDI: return "rdi"; + case ClobberReg_RSP: return "rsp"; + case ClobberReg_RBP: return "rbp"; + case ClobberReg_R11: return "r11"; + case ClobberReg_XMM0: return "xmm0"; + } + return ""; + } + struct Clobber { OperandSet written; OperandSet read; From c085a461859d17a79b938921a5d756c84fbe8246 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 12 Aug 2026 23:40:57 +0100 Subject: [PATCH 54/92] Move `#side_effects` and `#align_stack` to the specification list --- src/check_asm.cpp | 34 ++++++++++++++++++++++++++++++---- src/check_expr.cpp | 14 ++++++-------- src/entity.cpp | 2 -- src/parser.cpp | 44 ++++++++++++-------------------------------- src/parser.hpp | 3 +-- src/parser_pos.cpp | 7 +++++-- 6 files changed, 54 insertions(+), 50 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index b159ef1a8..a9988be18 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -426,7 +426,8 @@ gb_internal AsmTemplateEntityDeclKind check_asm_find_kind(Entity *entity, Array< }; -gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { +template +gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *scope, Slice const &specs, Array *asm_template_entity_decls) { StringSet pin_set = {}; string_set_init(&pin_set, specs.count); defer (string_set_destroy(&pin_set)); @@ -465,6 +466,8 @@ gb_internal void check_asm_specs(CheckerContext *ctx, Scope *scope, Slice ast_node(reg, AsmRegister, spec->value); pin = reg->name.string; if (pin.len != 0) { + Operand op = {}; + check_register(asm_ctx, &op, reg); if (string_set_update(&pin_set, pin)) { error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); } @@ -1280,15 +1283,36 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->type = type; + + bool has_side_effects = false; + bool is_align_stack = false; auto *clobber_registers_set = &entity->AsmTemplate.clobber_registers_set; - check_asm_specs(ctx, ate->param_scope, at->specs, &ate->decls); + check_asm_specs(asm_ctx, ctx, ate->param_scope, at->specs, &ate->decls); { // check clobbers bool clobber_cc = false; bool clobber_memory = false; for (Ast *clobber_ : at->clobbers) { ast_node(clobber, AsmClobber, clobber_); + + if (clobber->value == nullptr) { + if (clobber->name.string == "side_effects") { + if (has_side_effects) { + error(clobber->name, "#side_effects has already been defined as an asm specification"); + } + has_side_effects = true; + } else if (clobber->name.string == "align_stack") { + if (is_align_stack) { + error(clobber->name, "#align_stack has already been defined as an asm specification"); + } + is_align_stack = true; + } else { + error(clobber->name, "Unknown clobber directive '#%.*s'", LIT(clobber->name.string)); + } + continue; + } + switch (clobber->value->kind) { case_ast_node(asm_reg, AsmRegister, clobber->value) String reg = asm_reg->name.string; @@ -1321,8 +1345,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } } - entity->AsmTemplate.clobber_cc = clobber_cc; - entity->AsmTemplate.clobber_memory = clobber_memory; + entity->AsmTemplate.clobber_cc = clobber_cc; + entity->AsmTemplate.clobber_memory = clobber_memory; + entity->AsmTemplate.has_side_effects = has_side_effects; + entity->AsmTemplate.is_align_stack = is_align_stack; } // collect label decls diff --git a/src/check_expr.cpp b/src/check_expr.cpp index cf6c45d05..37eccae96 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -13633,12 +13633,6 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan } } - if (at->has_side_effects) { - str = gb_string_appendc(str, " #side_effects"); - } - if (at->is_align_stack) { - str = gb_string_appendc(str, " #align_stack"); - } if (at->specs.count) { str = gb_string_append_rune(str, '['); for_array(j, at->specs) { @@ -13688,8 +13682,12 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan case_end; case_ast_node(clobber, AsmClobber, node); - str = gb_string_appendc(str, "#clobber "); - str = write_expr_to_string(str, clobber->value, shorthand); + str = gb_string_appendc(str, "#"); + str = gb_string_append_length(str, clobber->name.string.text, clobber->name.string.len); + if (clobber->value) { + str = gb_string_appendc(str, " "); + str = write_expr_to_string(str, clobber->value, shorthand); + } case_end; case_ast_node(label, AsmLabelDecl, node); diff --git a/src/entity.cpp b/src/entity.cpp index e5f31eb7b..49faed0bd 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -556,8 +556,6 @@ gb_internal Entity *alloc_entity_asm_template(Scope *scope, Token token, Type *t GB_ASSERT(node->kind == Ast_AsmTemplate); Entity *entity = alloc_entity(Entity_AsmTemplate, scope, token, type); entity->AsmTemplate.node = node; - entity->AsmTemplate.has_side_effects = node->AsmTemplate.has_side_effects; - entity->AsmTemplate.is_align_stack = node->AsmTemplate.is_align_stack; return entity; } diff --git a/src/parser.cpp b/src/parser.cpp index 573566237..bea018906 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2590,34 +2590,8 @@ gb_internal Ast *parse_asm_signature(AstFile *f, Token asm_token) { gb_internal Ast *parse_asm_template(AstFile *f) { Token token = expect_token(f, Token_asm); - bool has_side_effects = false; - bool is_align_stack = false; - Ast *signature = parse_asm_signature(f, token); - while (f->curr_token.kind == Token_Hash) { - advance_token(f); - if (f->curr_token.kind == Token_Ident) { - Token token = advance_token(f); - String name = token.string; - if (name == "side_effects") { - if (has_side_effects) { - syntax_error(token, "Duplicate directive on inline asm expression: '#side_effects'"); - } - has_side_effects = true; - } else if (name == "align_stack") { - if (is_align_stack) { - syntax_error(token, "Duplicate directive on inline asm expression: '#align_stack'"); - } - is_align_stack = true; - } else { - syntax_error(token, "Invalid directive on inline asm expression: '#%.*s'", LIT(token.string)); - } - } else { - syntax_error(f->curr_token, "Expected an identifier after hash"); - } - } - Slice asm_specs = {}; Slice asm_clobbers = {}; @@ -2674,15 +2648,23 @@ gb_internal Ast *parse_asm_template(AstFile *f) { spec->AsmSpec.value = value; } else if (f->curr_token.kind == Token_Hash) { Token hash = expect_token(f, Token_Hash); - Token clobber_token = expect_token(f, Token_Ident); - if (clobber_token.string != "clobber") { - syntax_error(clobber_token, "Expected #clobber, got '%.*s'", LIT(clobber_token.string)); - } else { + Token name = expect_token(f, Token_Ident); + + if (name.string == "side_effects" || + name.string == "align_stack") { + Ast *clobber = alloc_ast_node(f, Ast_AsmClobber); + clobber->AsmClobber.token = hash; + clobber->AsmClobber.name = name; + array_add(&clobbers, clobber); + } else if (name.string == "clobber") { Ast *value = parse_asm_operand(f, false); Ast *clobber = alloc_ast_node(f, Ast_AsmClobber); clobber->AsmClobber.token = hash; + clobber->AsmClobber.name = name; clobber->AsmClobber.value = value; array_add(&clobbers, clobber); + } else { + syntax_error(name, "Expected #clobber, #side_effects, or #align_stack, got '%.*s'", LIT(name.string)); } } else { syntax_error(f->curr_token, "Expected am asm specification which begins with a identifier, got '%.*s'", LIT(f->curr_token.string)); @@ -2732,8 +2714,6 @@ gb_internal Ast *parse_asm_template(AstFile *f) { Ast *asm_template = alloc_ast_node(f, Ast_AsmTemplate); asm_template->AsmTemplate.token = token; - asm_template->AsmTemplate.has_side_effects = has_side_effects; - asm_template->AsmTemplate.is_align_stack = is_align_stack; asm_template->AsmTemplate.signature = signature; asm_template->AsmTemplate.specs = asm_specs; asm_template->AsmTemplate.clobbers = asm_clobbers; diff --git a/src/parser.hpp b/src/parser.hpp index aa75e3df4..0c884c72c 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -470,8 +470,6 @@ struct AstSplitArgs { }) \ AST_KIND(AsmTemplate, "asm template", struct { \ Token token; \ - bool has_side_effects; \ - bool is_align_stack; \ Ast * signature; \ Slice specs; \ Slice clobbers; \ @@ -490,6 +488,7 @@ struct AstSplitArgs { }) \ AST_KIND(AsmClobber, "asm clobber", struct { \ Token token; \ + Token name; \ Ast * value; \ }) \ AST_KIND(AsmLabelDecl, "asm label declaration", struct { \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 4f07c8e8e..b58b07c6a 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -177,7 +177,7 @@ Token ast_end_token(Ast *node) { return node->AsmRegister.name; case Ast_AsmSpec: if (node->AsmSpec.value) { - return ast_end_token(node->AsmSpec.value); + return ast_end_token(node->AsmSpec.value); } if (node->AsmSpec.type) { return ast_end_token(node->AsmSpec.type); @@ -187,7 +187,10 @@ Token ast_end_token(Ast *node) { } return ast_end_token(node->AsmSpec.name); case Ast_AsmClobber: - return ast_end_token(node->AsmClobber.value); + if (node->AsmClobber.value) { + return ast_end_token(node->AsmClobber.value); + } + return node->AsmClobber.name; case Ast_AsmLabelDecl: return ast_end_token(node->AsmLabelDecl.name); case Ast_AsmInstruction: From 3453643c118cfe04261e769f6268a825fc9b152a Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 13 Aug 2026 00:34:28 +0100 Subject: [PATCH 55/92] Improve `unquote_string_triple` to give better error messages on invalid literals --- src/parser.cpp | 45 ++++++++++++++- src/string.cpp | 145 ++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 169 insertions(+), 21 deletions(-) diff --git a/src/parser.cpp b/src/parser.cpp index bea018906..06f7a822e 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -845,6 +845,25 @@ gb_internal Ast *ast_uninit(AstFile *f, Token token) { } gb_internal ExactValue exact_value_from_token(AstFile *f, Token const &token) { + auto token_pos_at_offset = [](Token const &token, isize offset) -> TokenPos { + TokenPos pos = token.pos; + if (offset <= 0) { + return pos; + } + String s = token.string; + isize n = gb_min(offset, s.len); + for (isize i = 0; i < n; i++) { + if (s.text[i] == '\n') { + pos.line += 1; + pos.column = 1; + } else { + pos.column += 1; + } + pos.offset += 1; + } + return pos; + }; + String s = token.string; string_interner_insert(s); switch (token.kind) { @@ -857,8 +876,30 @@ gb_internal ExactValue exact_value_from_token(AstFile *f, Token const &token) { if (s.len >= 6 && ((s.text[0] == '"' && s.text[1] == '"' && s.text[2] == '"') || (s.text[0] == '`' && s.text[1] == '`' && s.text[2] == '`'))) { - if (!unquote_string_triple(ast_allocator(f), &s, string_contains_char(s, '\r'))) { - syntax_error(token, "Invalid multi-line string literal"); + TripleStringErrorKind terr = TripleStringError_None; + isize terr_off = -1; + if (!unquote_string_triple(ast_allocator(f), &s, string_contains_char(s, '\r'), &terr, &terr_off)) { + TokenPos pos = token_pos_at_offset(token, terr_off); + switch (terr) { + case TripleStringError_ContentOnOpeningLine: + syntax_error(pos, "A multi-line string literal must begin on the line after the opening delimiter"); + break; + case TripleStringError_ClosingNotOnOwnLine: + syntax_error(pos, "The closing delimiter of a multi-line string literal must be on its own line"); + break; + case TripleStringError_UnderIndented: + syntax_error(pos, "This line is indented less than the closing delimiter of the multi-line string literal"); + break; + case TripleStringError_IndentationMismatch: + syntax_error(pos, "The indentation of this line does not match the closing delimiter of the multi-line string literal"); + break; + case TripleStringError_InvalidEscape: + syntax_error(pos, "Invalid escape sequence in string literal"); + break; + default: + syntax_error(pos, "Invalid multi-line string literal"); + break; + } } } else if (!unquote_string(ast_allocator(f), &s, 0, s.text[0] == '`')) { syntax_error(token, "Invalid string literal"); diff --git a/src/string.cpp b/src/string.cpp index 551a6250c..76d03d55f 100644 --- a/src/string.cpp +++ b/src/string.cpp @@ -1360,34 +1360,54 @@ gb_internal bool triple_string_deindent(gbAllocator a, String body, String *out) return true; } -// Triple-quoted string literal, dispatching on the delimiter: -// `"` -> escapes processed; multi-line form is Java-style de-indented -// `\`` -> raw (no escapes); multi-line form is ALSO Java-style de-indented -// (carriage returns normalized), embedded single/double backticks -// are literal + +enum TripleStringErrorKind { + TripleStringError_None = 0, + TripleStringError_InvalidLiteral, // malformed delimiters (shouldn't occur for a real token) + TripleStringError_ContentOnOpeningLine, // text after the opening delimiter on its own line + TripleStringError_ClosingNotOnOwnLine, // closing delimiter is not alone on its line + TripleStringError_UnderIndented, // a content line is indented less than the closing delimiter + TripleStringError_IndentationMismatch, // a line's indentation whitespace differs from the closing delimiter + TripleStringError_InvalidEscape, // bad escape sequence (only reachable for `"""` strings) +}; + +// `out_err` receives the failure reason and `out_err_offset` a byte offset into +// the *token string* (i.e. into *s_ on entry) pointing at the offending +// character, or -1 when no precise location is available. Both are only +// meaningful when the function returns 0. // // 0 == failure // 1 == original memory // 2 == new allocation -gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carriage_return=false) { +gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carriage_return=false, + TripleStringErrorKind *out_err=nullptr, isize *out_err_offset=nullptr) { + if (out_err) *out_err = TripleStringError_None; + if (out_err_offset) *out_err_offset = -1; + + #define TRIPLE_FAIL(kind, off) do { \ + if (out_err) *out_err = (kind); \ + if (out_err_offset) *out_err_offset = (off); \ + return 0; \ + } while (0) + String s = *s_; isize n = s.len; if (n < 6) { - return 0; + TRIPLE_FAIL(TripleStringError_InvalidLiteral, 0); } u8 quote = s[0]; if (quote != '"' && quote != '`') { - return 0; + TRIPLE_FAIL(TripleStringError_InvalidLiteral, 0); } if (!(s[0] == quote && s[1] == quote && s[2] == quote) || !(s[n-1] == quote && s[n-2] == quote && s[n-3] == quote)) { - return 0; + TRIPLE_FAIL(TripleStringError_InvalidLiteral, 0); } - String body = make_string(s.text+3, s.len-6); bool raw = (quote == '`'); + String body = make_string(s.text+3, s.len-6); // body begins at token offset 3 - // Single-line form: no indentation handling. + // Single-line form: no indentation handling if (!string_contains_char(body, '\n')) { if (raw) { if (has_carriage_return) { @@ -1397,22 +1417,109 @@ gb_internal i32 unquote_string_triple(gbAllocator a, String *s_, bool has_carria *s_ = body; return 1; } - return unquote_string_triple_content(a, s_, body, has_carriage_return, false); + i32 r = unquote_string_triple_content(a, s_, body, has_carriage_return, false); + if (r == 0) { + TRIPLE_FAIL(TripleStringError_InvalidEscape, -1); + } + return r; } - // Multi-line form: Java-style de-indentation for both delimiters. - String di = {}; - if (!triple_string_deindent(a, body, &di)) { - return 0; + // Opening delimiter's line must be whitespace only. + isize first_nl = 0; + while (body.text[first_nl] != '\n') { + first_nl += 1; } + for (isize i = 0; i < first_nl; i++) { + u8 c = body.text[i]; + if (c != ' ' && c != '\t' && c != '\r') { + TRIPLE_FAIL(TripleStringError_ContentOnOpeningLine, 3 + i); + } + } + + // Closing delimiter's line: whitespace after the final newline is the indent prefix. + isize last_nl = body.len - 1; + while (body.text[last_nl] != '\n') { + last_nl -= 1; + } + String indent = make_string(body.text+last_nl+1, body.len-(last_nl+1)); + for (isize i = 0; i < indent.len; i++) { + u8 c = indent.text[i]; + if (c != ' ' && c != '\t') { + TRIPLE_FAIL(TripleStringError_ClosingNotOnOwnLine, 3 + (last_nl+1) + i); + } + } + + String content = make_string(body.text+first_nl+1, last_nl-(first_nl+1)); + isize content_base = 3 + (first_nl+1); // token offset of the content start + + u8 *dbuf = gb_alloc_array(a, u8, content.len+1); + isize dlen = 0; + isize li = 0; + for (;;) { + isize le = li; + while (le < content.len && content.text[le] != '\n') { + le += 1; + } + isize len = le - li; + if (len > 0 && content.text[li+len-1] == '\r') { + len -= 1; // normalize CRLF + } + + bool blank = true; + for (isize k = 0; k < len; k++) { + u8 c = content.text[li+k]; + if (c != ' ' && c != '\t') { + blank = false; + break; + } + } + if (!blank) { + isize ws = 0; + while (ws < len && (content.text[li+ws] == ' ' || content.text[li+ws] == '\t')) { + ws += 1; + } + isize ws_end_off = content_base + li + ws; + + for (isize k = 0; k < indent.len; k++) { + if (k >= len || content.text[li+k] != indent.text[k]) { + u8 lc = 0; + if (k < len) { + lc = content.text[li+k]; + } + gb_free(a, dbuf); + + if (k < len && (lc == ' ' || lc == '\t')) { + TRIPLE_FAIL(TripleStringError_IndentationMismatch, ws_end_off); + } + TRIPLE_FAIL(TripleStringError_UnderIndented, ws_end_off); + } + } + for (isize k = indent.len; k < len; k++) { + dbuf[dlen++] = content.text[li+k]; + } + } + if (le >= content.len) { + break; + } + dbuf[dlen++] = '\n'; + li = le + 1; + } + + String di = make_string(dbuf, dlen); if (raw) { - // Raw: the de-indented content is used verbatim (no escape processing). *s_ = di; return 2; } - // Processed: run escape sequences on the de-indented content. - return unquote_string_triple_content(a, s_, di, false, true); + i32 r = unquote_string_triple_content(a, s_, di, false, true); + if (r == 0) { + TRIPLE_FAIL(TripleStringError_InvalidEscape, -1); + } + return r; + + #undef TRIPLE_FAIL } + + gb_internal bool string_is_valid_identifier(String str) { if (str.len <= 0) return false; From 4f82bed1f7ddfafda575d91ba111239928a22f43 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 13 Aug 2026 01:21:38 +0100 Subject: [PATCH 56/92] Hide debug printing for LLVM's ASM IR --- src/llvm_backend_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 406622921..c2412076c 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -491,7 +491,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (true) { + if (false) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From cb903df235738629f794c34d76bb5445f1bfd3b2 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 13 Aug 2026 10:03:00 +0100 Subject: [PATCH 57/92] `#side_effects` -> `#volatile`; Remove dead code --- src/check_asm.cpp | 14 +++---- src/check_expr.cpp | 81 --------------------------------------- src/entity.cpp | 2 +- src/llvm_backend_asm.cpp | 2 +- src/llvm_backend_expr.cpp | 33 ---------------- src/parser.cpp | 35 +---------------- src/parser.hpp | 11 ------ src/parser_pos.cpp | 2 - 8 files changed, 10 insertions(+), 170 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index a9988be18..a794fa506 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -882,7 +882,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm tmpl_entity->AsmTemplate.clobber_cc |= clobber.implies_clobber_cc(); tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); - tmpl_entity->AsmTemplate.has_side_effects |= clobber.implies_side_effects(); + tmpl_entity->AsmTemplate.is_volatile |= clobber.implies_side_effects(); return; } @@ -1284,7 +1284,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->type = type; - bool has_side_effects = false; + bool is_volatile = false; bool is_align_stack = false; auto *clobber_registers_set = &entity->AsmTemplate.clobber_registers_set; @@ -1297,11 +1297,11 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity ast_node(clobber, AsmClobber, clobber_); if (clobber->value == nullptr) { - if (clobber->name.string == "side_effects") { - if (has_side_effects) { - error(clobber->name, "#side_effects has already been defined as an asm specification"); + if (clobber->name.string == "volatile") { + if (is_volatile) { + error(clobber->name, "#volatile has already been defined as an asm specification"); } - has_side_effects = true; + is_volatile = true; } else if (clobber->name.string == "align_stack") { if (is_align_stack) { error(clobber->name, "#align_stack has already been defined as an asm specification"); @@ -1347,7 +1347,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity entity->AsmTemplate.clobber_cc = clobber_cc; entity->AsmTemplate.clobber_memory = clobber_memory; - entity->AsmTemplate.has_side_effects = has_side_effects; + entity->AsmTemplate.is_volatile = is_volatile; entity->AsmTemplate.is_align_stack = is_align_stack; } diff --git a/src/check_expr.cpp b/src/check_expr.cpp index 37eccae96..416f60b9b 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -12683,53 +12683,6 @@ gb_internal ExprKind check_expr_base_internal(CheckerContext *c, Operand *o, Ast } case_end; - case_ast_node(ia, InlineAsmExpr, node); - if (c->curr_proc_decl == nullptr) { - error(node, "Inline asm expressions are only allowed within a procedure body"); - } - - auto param_types = array_make(heap_allocator(), ia->param_types.count); - Type *return_type = nullptr; - for_array(i, ia->param_types) { - param_types[i] = check_type(c, ia->param_types[i]); - } - if (ia->return_type != nullptr) { - return_type = check_type(c, ia->return_type); - } - Operand x = {}; - check_expr(c, &x, ia->asm_string); - if (x.mode != Addressing_Constant || !is_type_string(x.type)) { - error(x.expr, "Expected a constant string for the inline asm main parameter"); - } - check_expr(c, &x, ia->constraints_string); - if (x.mode != Addressing_Constant || !is_type_string(x.type)) { - error(x.expr, "Expected a constant string for the inline asm constraints parameter"); - } - - Scope *scope = create_scope(c->info, c->scope); - scope->flags |= ScopeFlag_Proc; - - Type *params = alloc_type_tuple(); - Type *results = alloc_type_tuple(); - if (param_types.count != 0) { - slice_init(¶ms->Tuple.variables, heap_allocator(), param_types.count); - for_array(i, param_types) { - params->Tuple.variables[i] = alloc_entity_param(scope, blank_token, param_types[i], false, true); - } - } - if (return_type != nullptr) { - slice_init(&results->Tuple.variables, heap_allocator(), 1); - results->Tuple.variables[0] = alloc_entity_param(scope, blank_token, return_type, false, true); - } - - - Type *pt = alloc_type_proc(scope, params, param_types.count, results, return_type != nullptr ? 1 : 0, false, ProcCC_InlineAsm); - o->type = pt; - o->mode = Addressing_Value; - o->expr = node; - return Expr_Expr; - case_end; - case Ast_DistinctType: case Ast_TypeidType: case Ast_PolyType: @@ -13567,40 +13520,6 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan str = gb_string_appendc(str, "}"); case_end; - case_ast_node(ia, InlineAsmExpr, node); - str = gb_string_appendc(str, "asm("); - for_array(i, ia->param_types) { - if (i > 0) { - str = gb_string_appendc(str, ", "); - } - str = write_expr_to_string(str, ia->param_types[i], shorthand); - } - str = gb_string_appendc(str, ")"); - if (ia->return_type != nullptr) { - str = gb_string_appendc(str, " -> "); - str = write_expr_to_string(str, ia->return_type, shorthand); - } - if (ia->has_side_effects) { - str = gb_string_appendc(str, " #side_effects"); - } - if (ia->is_align_stack) { - str = gb_string_appendc(str, " #stack_align"); - } - if (ia->dialect) { - str = gb_string_appendc(str, " #"); - str = gb_string_appendc(str, inline_asm_dialect_strings[ia->dialect]); - } - str = gb_string_appendc(str, " {"); - if (shorthand) { - str = gb_string_appendc(str, "..."); - } else { - str = write_expr_to_string(str, ia->asm_string, shorthand); - str = gb_string_appendc(str, ", "); - str = write_expr_to_string(str, ia->constraints_string, shorthand); - } - str = gb_string_appendc(str, "}"); - case_end; - case_ast_node(at, AsmTemplate, node); str = gb_string_appendc(str, "asm"); { diff --git a/src/entity.cpp b/src/entity.cpp index 49faed0bd..535201013 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -340,7 +340,7 @@ struct Entity { } Label; struct { Ast *node; - bool has_side_effects; + bool is_volatile; bool is_align_stack; bool clobber_cc; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index c2412076c..0fb03f13a 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -484,7 +484,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { fn_ty, asm_string, cast(size_t)gb_string_length(asm_string), constraints, cast(size_t)gb_string_length(constraints), - /*HasSideEffects*/ tmpl_entity->AsmTemplate.has_side_effects, + /*HasSideEffects*/ tmpl_entity->AsmTemplate.is_volatile, /*IsAlignStack*/ tmpl_entity->AsmTemplate.is_align_stack, LLVMInlineAsmDialectATT, /*CanThrow*/ false); diff --git a/src/llvm_backend_expr.cpp b/src/llvm_backend_expr.cpp index 5a478edd0..419609645 100644 --- a/src/llvm_backend_expr.cpp +++ b/src/llvm_backend_expr.cpp @@ -4733,39 +4733,6 @@ gb_internal lbValue lb_build_expr_internal(lbProcedure *p, Ast *expr) { case_ast_node(ie, MatrixIndexExpr, expr); return lb_addr_load(p, lb_build_addr(p, expr)); case_end; - - case_ast_node(ia, InlineAsmExpr, expr); - Type *t = type_of_expr(expr); - GB_ASSERT(is_type_asm_proc(t)); - - String asm_string = {}; - String constraints_string = {}; - - TypeAndValue tav; - tav = type_and_value_of_expr(ia->asm_string); - GB_ASSERT(is_type_string(tav.type)); - GB_ASSERT(tav.value.kind == ExactValue_String); - asm_string = tav.value.value_string; - - tav = type_and_value_of_expr(ia->constraints_string); - GB_ASSERT(is_type_string(tav.type)); - GB_ASSERT(tav.value.kind == ExactValue_String); - constraints_string = tav.value.value_string; - - - LLVMInlineAsmDialect dialect = LLVMInlineAsmDialectATT; - switch (ia->dialect) { - case InlineAsmDialect_Default: dialect = LLVMInlineAsmDialectATT; break; - case InlineAsmDialect_ATT: dialect = LLVMInlineAsmDialectATT; break; - case InlineAsmDialect_Intel: dialect = LLVMInlineAsmDialectIntel; break; - default: GB_PANIC("Unhandled inline asm dialect"); break; - } - - LLVMTypeRef func_type = lb_type_internal_for_procedures_raw(p->module, t); - LLVMValueRef the_asm = llvm_get_inline_asm(func_type, asm_string, constraints_string, ia->has_side_effects, ia->has_side_effects, dialect); - GB_ASSERT(the_asm != nullptr); - return {the_asm, t}; - case_end; } GB_PANIC("lb_build_expr: %.*s", LIT(ast_strings[expr->kind])); diff --git a/src/parser.cpp b/src/parser.cpp index 06f7a822e..417c4b418 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -331,13 +331,6 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AutoCast.expr = clone_ast(n->AutoCast.expr, f); break; - case Ast_InlineAsmExpr: - n->InlineAsmExpr.param_types = clone_ast_array(n->InlineAsmExpr.param_types, f); - n->InlineAsmExpr.return_type = clone_ast(n->InlineAsmExpr.return_type, f); - n->InlineAsmExpr.asm_string = clone_ast(n->InlineAsmExpr.asm_string, f); - n->InlineAsmExpr.constraints_string = clone_ast(n->InlineAsmExpr.constraints_string, f); - break; - case Ast_BadStmt: break; case Ast_EmptyStmt: break; case Ast_ExprStmt: @@ -1072,32 +1065,6 @@ gb_internal Ast *ast_auto_cast(AstFile *f, Token token, Ast *expr) { } -gb_internal Ast *ast_inline_asm_expr(AstFile *f, Token token, Token open, Token close, - Array const ¶m_types, - Ast *return_type, - Ast *asm_string, - Ast *constraints_string, - bool has_side_effects, - bool is_align_stack, - InlineAsmDialectKind dialect) { - - Ast *result = alloc_ast_node(f, Ast_InlineAsmExpr); - result->InlineAsmExpr.token = token; - result->InlineAsmExpr.open = open; - result->InlineAsmExpr.close = close; - result->InlineAsmExpr.param_types = slice_from_array(param_types); - result->InlineAsmExpr.return_type = return_type; - result->InlineAsmExpr.asm_string = asm_string; - result->InlineAsmExpr.constraints_string = constraints_string; - result->InlineAsmExpr.has_side_effects = has_side_effects; - result->InlineAsmExpr.is_align_stack = is_align_stack; - result->InlineAsmExpr.dialect = dialect; - return result; -} - - - - gb_internal Ast *ast_bad_stmt(AstFile *f, Token begin, Token end) { Ast *result = alloc_ast_node(f, Ast_BadStmt); result->BadStmt.begin = begin; @@ -2691,7 +2658,7 @@ gb_internal Ast *parse_asm_template(AstFile *f) { Token hash = expect_token(f, Token_Hash); Token name = expect_token(f, Token_Ident); - if (name.string == "side_effects" || + if (name.string == "volatile" || name.string == "align_stack") { Ast *clobber = alloc_ast_node(f, Ast_AsmClobber); clobber->AsmClobber.token = hash; diff --git a/src/parser.hpp b/src/parser.hpp index 0c884c72c..a8b69593e 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -571,17 +571,6 @@ AST_KIND(_ExprBegin, "", bool) \ }) \ AST_KIND(TypeCast, "type cast", struct { Token token; Ast *type, *expr; }) \ AST_KIND(AutoCast, "auto_cast", struct { Token token; Ast *expr; }) \ - AST_KIND(InlineAsmExpr, "inline asm expression", struct { \ - Token token; \ - Token open, close; \ - Slice param_types; \ - Ast *return_type; \ - Ast *asm_string; \ - Ast *constraints_string; \ - bool has_side_effects; \ - bool is_align_stack; \ - InlineAsmDialectKind dialect; \ - }) \ AST_KIND(MatrixIndexExpr, "matrix index expression", struct { Ast *expr, *row_index, *column_index; Token open, close; }) \ AST_KIND(_ExprEnd, "", bool) \ AST_KIND(_StmtBegin, "", bool) \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index b58b07c6a..96611b7a8 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -71,7 +71,6 @@ gb_internal Token ast_token(Ast *node) { case Ast_TypeAssertion: return ast_token(node->TypeAssertion.expr); case Ast_TypeCast: return node->TypeCast.token; case Ast_AutoCast: return node->AutoCast.token; - case Ast_InlineAsmExpr: return node->InlineAsmExpr.token; case Ast_BadStmt: return node->BadStmt.begin; case Ast_EmptyStmt: return node->EmptyStmt.token; @@ -254,7 +253,6 @@ Token ast_end_token(Ast *node) { case Ast_TypeAssertion: return ast_end_token(node->TypeAssertion.type); case Ast_TypeCast: return ast_end_token(node->TypeCast.expr); case Ast_AutoCast: return ast_end_token(node->AutoCast.expr); - case Ast_InlineAsmExpr: return node->InlineAsmExpr.close; case Ast_BadStmt: return node->BadStmt.end; case Ast_EmptyStmt: return node->EmptyStmt.token; From 344e8afa362719cf8c954db8886c8c3ee3a81ca4 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 12:10:08 +0100 Subject: [PATCH 58/92] `#clobber cc` -> `#clobber flags` --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 8 ++--- src/asm_tables_amd64.cpp | 8 ++--- src/check_asm.cpp | 32 ++++++++++++------- src/entity.cpp | 4 +-- src/llvm_backend_asm.cpp | 4 +-- src/parser.cpp | 6 ++++ src/parser.hpp | 1 + 7 files changed, 40 insertions(+), 23 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 2d5386edc..4d5228d92 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -231,10 +231,10 @@ main :: proc() { bool reads_mem; SideEffectFlags side_effects; - bool implies_clobber_cc() { - u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| - ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; - return ((flags_wr | flags_undef) & CC_MASK) != 0; + bool implies_clobber_flags() { + u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| + ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; + return ((flags_wr | flags_undef) & FLAGS_MASK) != 0; } bool implies_clobber_memory() { return writes_mem || reads_mem || diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index be0425c77..fd218e0e9 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -231,10 +231,10 @@ struct Asm_amd64 { bool reads_mem; SideEffectFlags side_effects; - bool implies_clobber_cc() { - u16 const CC_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| - ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; - return ((flags_wr | flags_undef) & CC_MASK) != 0; + bool implies_clobber_flags() { + u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| + ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; + return ((flags_wr | flags_undef) & FLAGS_MASK) != 0; } bool implies_clobber_memory() { return writes_mem || reads_mem || diff --git a/src/check_asm.cpp b/src/check_asm.cpp index a794fa506..6e4914961 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -643,6 +643,13 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc template gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegister *asm_reg) { String name = asm_reg->name.string; + if (asm_reg->flag.kind == Token_Ident) { + // TODO(bill): has flags + if (name != "cc") { + + } + } + auto r = asm_ctx->register_lookup(name); if (r) { operand->mode = Addressing_Value; @@ -880,9 +887,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm // Handle clobbering from mnemonic auto clobber = asm_ctx->clobber(mnemonic); - tmpl_entity->AsmTemplate.clobber_cc |= clobber.implies_clobber_cc(); - tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); - tmpl_entity->AsmTemplate.is_volatile |= clobber.implies_side_effects(); + tmpl_entity->AsmTemplate.clobber_flags |= clobber.implies_clobber_flags(); + tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); + tmpl_entity->AsmTemplate.is_volatile |= clobber.implies_side_effects(); return; } @@ -1290,7 +1297,7 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity check_asm_specs(asm_ctx, ctx, ate->param_scope, at->specs, &ate->decls); { // check clobbers - bool clobber_cc = false; + bool clobber_flags = false; bool clobber_memory = false; for (Ast *clobber_ : at->clobbers) { @@ -1316,6 +1323,9 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity switch (clobber->value->kind) { case_ast_node(asm_reg, AsmRegister, clobber->value) String reg = asm_reg->name.string; + if (asm_reg->flag.string != "") { + error(asm_reg->flag, "#clobber on specific flags is not allowed"); + } Operand operand = {}; if (check_register(asm_ctx, &operand, asm_reg)) { if (string_set_update(clobber_registers_set, reg)) { @@ -1325,27 +1335,27 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity case_end; case_ast_node(ident, Ident, clobber->value); String str = ident->token.string; - if (str == "cc") { - if (clobber_cc) { - error(clobber->value, "#clobber cc has already been defined"); + if (str == "flags") { + if (clobber_flags) { + error(clobber->value, "#clobber flags has already been defined"); } - clobber_cc = true; + clobber_flags = true; } else if (str == "memory") { if (clobber_memory) { error(clobber->value, "#clobber memory has already been defined"); } clobber_memory = true; } else { - error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); + error(clobber->value, "Expected either a register, 'flags', or 'memory' for a '#clobber' specification, got '%.*s'", LIT(str)); } case_end; default: - error(clobber->value, "Expected either a register, 'cc', or 'memory' for a '#clobber' specification"); + error(clobber->value, "Expected either a register, 'flags', or 'memory' for a '#clobber' specification"); break; } } - entity->AsmTemplate.clobber_cc = clobber_cc; + entity->AsmTemplate.clobber_flags = clobber_flags; entity->AsmTemplate.clobber_memory = clobber_memory; entity->AsmTemplate.is_volatile = is_volatile; entity->AsmTemplate.is_align_stack = is_align_stack; diff --git a/src/entity.cpp b/src/entity.cpp index bfe4c42c9..3ec3860e2 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -344,8 +344,8 @@ struct Entity { bool is_volatile; bool is_align_stack; - bool clobber_cc; - bool clobber_memory; + bool clobber_flags; + bool clobber_memory; StringSet clobber_registers_set; Scope *param_scope; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 0fb03f13a..1e36459c8 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -451,8 +451,8 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { string_set_update(&emitted_reg_clobbers, reg); } - // Template-level clobbers derived from #clobber cc / #clobber memory. - if (tmpl_entity->AsmTemplate.clobber_cc) { + // Template-level clobbers derived from #clobber flags / #clobber memory. + if (tmpl_entity->AsmTemplate.clobber_flags) { sep(); if (build_context.metrics.arch == TargetArch_amd64) { raw("~{flags}"); // x86 EFLAGS condition codes diff --git a/src/parser.cpp b/src/parser.cpp index 6742f44f0..518beb2f0 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2437,6 +2437,12 @@ gb_internal Ast *parse_asm_register(AstFile *f) { Ast *reg = alloc_ast_node(f, Ast_AsmRegister); reg->AsmRegister.token = token; reg->AsmRegister.name = name; + if (allow_token(f, Token_Period)) { + Token flag = expect_token_after(f, Token_Ident, "register name and period for the flag"); + if (flag.kind == Token_Ident) { + reg->AsmRegister.flag = flag; + } + } return reg; } gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { diff --git a/src/parser.hpp b/src/parser.hpp index a8b69593e..cbbf84867 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -479,6 +479,7 @@ struct AstSplitArgs { AST_KIND(AsmRegister, "asm register", struct { \ Token token; \ Token name; \ + Token flag; \ }) \ AST_KIND(AsmSpec, "asm specification", struct { \ Ast *name; \ From db94c5a6cb46d0a0db341975ff72190be69be049 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 12:25:17 +0100 Subject: [PATCH 59/92] Begin work in `%flags.zf` et al --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 36 +++++++++++++++ src/asm_tables_amd64.cpp | 36 +++++++++++++++ src/check_asm.cpp | 46 +++++++++++++++++-- src/entity.cpp | 1 + src/llvm_backend_asm.cpp | 2 +- 5 files changed, 115 insertions(+), 6 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 4d5228d92..2fa8f34d9 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -219,6 +219,42 @@ main :: proc() { return \"\"; } + i32 flag_bit_from_name(String const &name, i32 *width_) { + static const struct {String name; i32 bit; } table[] = { + {str_lit(\"cf\"), 0}, // Carry + {str_lit(\"pf\"), 2}, // Parity + {str_lit(\"af\"), 4}, // Auxiliary Carry + {str_lit(\"zf\"), 6}, // Zero + {str_lit(\"sf\"), 7}, // Sign + {str_lit(\"tf\"), 8}, // Trap + {str_lit(\"if\"), 9}, // Interrupt Enable + {str_lit(\"df\"), 10}, // Direction + {str_lit(\"of\"), 11}, // Overflow + {str_lit(\"iopl\"),12}, // I/O Privilege Level (2-bit field: bits 12-13, low bit) + {str_lit(\"nt\"), 14}, // Nested Task + {str_lit(\"rf\"), 16}, // Resume + {str_lit(\"vm\"), 17}, // Virtual-8086 Mode + {str_lit(\"ac\"), 18}, // Alignment Check / Access Control + {str_lit(\"vif\"), 19}, // Virtual Interrupt Flag + {str_lit(\"vip\"), 20}, // Virtual Interrupt Pending + {str_lit(\"id\"), 21}, // Identification + }; + + for (auto const &t : table) { + if (name == t.name) { + if (width_) { + if (t.name == \"iopl\") { + *width_ = 2; + } else { + *width_ = 1; + } + } + return t.bit; + } + } + return -1; + } + struct Clobber { OperandSet written; OperandSet read; diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index fd218e0e9..fda95ad24 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -219,6 +219,42 @@ struct Asm_amd64 { return ""; } + i32 flag_bit_from_name(String const &name, i32 *width_) { + static const struct {String name; i32 bit; } table[] = { + {str_lit("cf"), 0}, // Carry + {str_lit("pf"), 2}, // Parity + {str_lit("af"), 4}, // Auxiliary Carry + {str_lit("zf"), 6}, // Zero + {str_lit("sf"), 7}, // Sign + {str_lit("tf"), 8}, // Trap + {str_lit("if"), 9}, // Interrupt Enable + {str_lit("df"), 10}, // Direction + {str_lit("of"), 11}, // Overflow + {str_lit("iopl"),12}, // I/O Privilege Level (2-bit field: bits 12-13, low bit) + {str_lit("nt"), 14}, // Nested Task + {str_lit("rf"), 16}, // Resume + {str_lit("vm"), 17}, // Virtual-8086 Mode + {str_lit("ac"), 18}, // Alignment Check / Access Control + {str_lit("vif"), 19}, // Virtual Interrupt Flag + {str_lit("vip"), 20}, // Virtual Interrupt Pending + {str_lit("id"), 21}, // Identification + }; + + for (auto const &t : table) { + if (name == t.name) { + if (width_) { + if (t.name == "iopl") { + *width_ = 2; + } else { + *width_ = 1; + } + } + return t.bit; + } + } + return -1; + } + struct Clobber { OperandSet written; OperandSet read; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 6e4914961..7f2d1298c 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -7,6 +7,9 @@ gb_internal i32 check_asm_operand_bit_width(Type *type) { if (is_type_untyped(type)) { return -1; } + if (is_type_boolean(type)) { + return 1; + } i64 sz = type_size_of(base_type(type)); if (sz <= 0) { return 0; @@ -432,6 +435,10 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc string_set_init(&pin_set, specs.count); defer (string_set_destroy(&pin_set)); + StringSet pin_flag_set = {}; + string_set_init(&pin_flag_set, specs.count); + defer (string_set_destroy(&pin_flag_set)); + for (Ast *spec_ : specs) { if (spec_->kind != Ast_AsmSpec) { continue; @@ -444,6 +451,7 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc Entity *other_scratch = nullptr; String pin = {}; + String pin_flag = {}; if (spec->value != nullptr) { if (spec->value->kind == Ast_Ident) { other_scratch = scope_lookup(scope, spec->value->Ident.interned, spec->value->Ident.hash); @@ -467,9 +475,17 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc pin = reg->name.string; if (pin.len != 0) { Operand op = {}; - check_register(asm_ctx, &op, reg); - if (string_set_update(&pin_set, pin)) { - error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); + if (check_register(asm_ctx, &op, reg)) { + if (reg->flag.string.len) { + GB_ASSERT(pin == "flags"); + pin_flag = reg->flag.string; + if (string_set_update(&pin_flag_set, pin_flag)) { + error(spec->value, "Pinned register flag %%%.*s.%.*s has already been assigned", LIT(pin), LIT(pin_flag)); + } + } + if (string_set_update(&pin_set, pin)) { + error(spec->value, "Pinned register %%%.*s has already been assigned", LIT(pin)); + } } } } @@ -496,6 +512,7 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc ed.param_group = AsmTemplateEntityDeclParamGroup_Scratch; ed.total_index = cast(i32)asm_template_entity_decls->count; ed.pin = pin; + ed.pin_flag = pin_flag; if (other_scratch != nullptr) { // Width-view of another operand: `p0b: u8 = p0`. @@ -632,6 +649,9 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc i->pin = pin; o->pin = pin; + i->pin_flag = pin_flag; + o->pin_flag = pin_flag; + if (other_scratch != nullptr) { GB_ASSERT(spec->value != nullptr); error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration, not a tie"); @@ -644,10 +664,26 @@ template gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegister *asm_reg) { String name = asm_reg->name.string; if (asm_reg->flag.kind == Token_Ident) { - // TODO(bill): has flags - if (name != "cc") { + bool ok = true; + i32 width = 0; + String flag = asm_reg->flag.string; + if (name != "flags") { + error(asm_reg->name, "Register flags can only be called on %%flags"); + ok = false; + } else { + i32 bit = asm_ctx->flag_bit_from_name(flag, &width); + if (bit < 0) { + error(asm_reg->flag, "Unknown register %%flags name: %.*s", LIT(flag)); + ok = false; + } } + + operand->type = t_bool; + if (width > 1) { + operand->type = t_u8; + } + return ok; } auto r = asm_ctx->register_lookup(name); diff --git a/src/entity.cpp b/src/entity.cpp index 3ec3860e2..ea5317447 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -186,6 +186,7 @@ struct AsmTemplateEntityDecl { AsmRegClass reg_class; String pin; + String pin_flag; // e.g. %flags.zf i32 total_index; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 1e36459c8..ff502cf47 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -491,7 +491,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (false) { + if (true) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From d1f561ec88391ff1696eae0da4545975a632475b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 12:59:23 +0100 Subject: [PATCH 60/92] Correct `instruction_size_suffix` so that the correct suffix can be selected for the instruction to adhere to AT&T syntax --- src/check_asm.cpp | 16 +++-- src/llvm_backend_asm.cpp | 141 +++++++++++++++++++++++++++++++++------ src/parser.cpp | 2 +- src/parser.hpp | 3 +- 4 files changed, 137 insertions(+), 25 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 7f2d1298c..24528dda6 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -597,6 +597,10 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc auto *i = &(*asm_template_entity_decls)[index]; if (i->pin.len == 0) { i->pin = pin; + i->pin_flag = pin_flag; + if (pin_flag.len != 0 && group != AsmTemplateEntityDeclParamGroup_Output) { + error(spec->value, "Input parameters cannot be pinned to a flag style register"); + } } else { error(spec_, "Asm register has already been pinned"); } @@ -648,14 +652,14 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc i->pin = pin; o->pin = pin; - - i->pin_flag = pin_flag; - o->pin_flag = pin_flag; - if (other_scratch != nullptr) { GB_ASSERT(spec->value != nullptr); error(spec->value, "Another parameter must be assigned/paired with a scratch parameter declaration, not a tie"); } + + if (pin_flag.len != 0) { + error(spec->value, "Input parameters, and thus tied parameters, cannot be pinned to a flag style register"); + } } } } @@ -920,6 +924,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm GB_ASSERT(tmpl_entity->kind == Entity_AsmTemplate); + GB_ASSERT(valid_form_index >= 0); + instr->mnemonic = mnemonic; + instr->valid_form_index = cast(i32)valid_form_index; + // Handle clobbering from mnemonic auto clobber = asm_ctx->clobber(mnemonic); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index ff502cf47..e34b33122 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -138,20 +138,6 @@ struct lbAsmGenerate { } }; - // Scan an instruction's operands for an annotated memory operand and return its - // size suffix, or 0 if none. The checker has already verified the annotation - // agrees with the matched encoding form, so a suffix here can never conflict. - char instruction_size_suffix(AstAsmInstruction *instr) { - char suffix = 0; - for (Ast *operand : instr->operands) { - char s = this->size_suffix_for_operand(operand); - if (s != 0) { - suffix = s; - } - } - return suffix; - } - // LLVM type of a returned register output, taken from the proc signature's results. LLVMTypeRef output_llvm_type(lbModule *m, AsmTemplateEntityDecl const &e) { @@ -160,9 +146,18 @@ struct lbAsmGenerate { return lb_type(m, rt); }; + // The declared Odin result type for an output entity. + Type *result_type_of(AsmTemplateEntityDecl const &e) { + Type *pt = base_type(tmpl_entity->type); + return pt->Proc.results->Tuple.variables[e.result_index]->type; + } + + virtual char instruction_size_suffix(AstAsmInstruction *instr) = 0; virtual char size_suffix_for_operand(Ast *op) = 0; virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; + virtual String flag_output_cc_suffix(String const &pin_flag) = 0; + }; struct lbAsmGenerate_amd64 : lbAsmGenerate { @@ -193,6 +188,72 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { return 0; } + + // Scan an instruction's operands for an annotated memory operand and return its + // size suffix, or 0 if none. The checker has already verified the annotation + // agrees with the matched encoding form, so a suffix here can never conflict. + char instruction_size_suffix(AstAsmInstruction *instr) override { + char suffix = 0; + for (Ast *operand : instr->operands) { + char s = this->size_suffix_for_operand(operand); + if (s != 0) { + suffix = s; + } + } + if (suffix) { + return suffix; + } + GB_ASSERT(instr->mnemonic != 0); + GB_ASSERT(instr->valid_form_index >= 0); + // Otherwise derive from the matched form's operand widths. + auto forms = g_asm_amd64.encoding_forms(instr->mnemonic); + auto &form = forms[instr->valid_form_index]; + + i32 width = 0; + bool any_vector = false; + for (isize k = 0; k < gb_count_of(form.ops); k++) { + auto ot = form.ops[k]; + if (ot == g_asm_amd64.OP_NONE) { + break; + } + if (g_asm_amd64.operand_type_is_implicit(ot)) { + continue; + } + AsmRegClass cls = g_asm_amd64.operand_type_reg_class(ot); + if (cls == AsmRegClass_Vector || cls == AsmRegClass_Mask) { + any_vector = true; + continue; // xmm/ymm/zmm/k forms take no b/w/l/q suffix + } + i32 w = g_asm_amd64.operand_type_bit_width(ot); + if (w == 8 || w == 16 || w == 32 || w == 64) { + width = gb_max(width, w); // GP/memory width + } + } + + if (any_vector || width == 0) { + return 0; // vector op, or nothing that needs a GP-width suffix + } + switch (width) { + case 8: return 'b'; + case 16: return 'w'; + case 32: return 'l'; + case 64: return 'q'; + } + return 0; + } + + // Map an EFLAGS flag name to its LLVM `=@cc` setcc condition, or {} if + // the flag has no single-flag setcc form (af/df/if/... can't be a flag output). + String flag_output_cc_suffix(String const &pin_flag) override { + if (pin_flag == "cf") return str_lit("c"); // carry + if (pin_flag == "pf") return str_lit("p"); // parity (even) + if (pin_flag == "zf") return str_lit("z"); // zero + if (pin_flag == "sf") return str_lit("s"); // sign + if (pin_flag == "of") return str_lit("o"); // overflow + return {}; + } + + gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { if (mem_op->disp) { asm_string = this->write_operand(asm_string, op_number, mem_op->disp, flags&~WriteOperandFlag_PrintPrefixes); @@ -280,6 +341,28 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { continue; // width-view: resolved to its source's operand, owns no slot } + // Flag output: an output pinned to a condition flag (e.g. `= %flags.zf`). + // Lowers to LLVM's `=@cc`, which yields an i1 (0/1). It takes a + // return-struct slot but is NEVER referenced in the body (the instruction + // sets the flag as a side effect), so it gets no $N operand number. + if (e.param_group == AsmTemplateEntityDeclParamGroup_Output && e.pin_flag.len != 0) { + GB_ASSERT(e.pin == "flags"); + String suffix = this->flag_output_cc_suffix(e.pin_flag); + GB_ASSERT_MSG(suffix.len != 0, "asm: flag '%.*s' has no setcc condition form", LIT(e.pin_flag)); + + sep(); + raw("={@cc"); + put(suffix); + raw("}"); + + ret_slot[i] = cast(i32)ret_types.count; + array_add(&ret_types, LLVMInt8TypeInContext(ctx)); + + // Counted in $N even though never referenced in the body. + op_number[i] = next_op++; + continue; + } + bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch && e.kind == AsmTemplateEntityDecl_Register @@ -311,7 +394,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } // Pass 2: inputs - for (isize i = 0; i < ops->count; i++) { + for_array(i, *ops) { AsmTemplateEntityDecl const &e = (*ops)[i]; if (e.view_of >= 0) { @@ -411,7 +494,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { string_set_init(&emitted_reg_clobbers); defer (string_set_destroy(&emitted_reg_clobbers)); - for (isize i = 0; i < ops->count; i++) { + for_array(i, *ops) { AsmTemplateEntityDecl const &e = (*ops)[i]; if (e.view_of >= 0) { @@ -455,7 +538,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { if (tmpl_entity->AsmTemplate.clobber_flags) { sep(); if (build_context.metrics.arch == TargetArch_amd64) { - raw("~{flags}"); // x86 EFLAGS condition codes + raw("~{dirflag},~{fpsr},~{flags}"); // clang's canonical x86 flags clobber } else { raw("~{cc}"); // AArch64 uses ~{cc} } @@ -522,7 +605,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { result_vals[i] = nullptr; } - for (isize i = 0; i < ops->count; i++) { + for_array(i, *ops) { AsmTemplateEntityDecl const &e = (*ops)[i]; if (e.view_of >= 0) { continue; // width-view: never a returned value @@ -538,6 +621,26 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef v = (ret_types.count == 1) ? call // single-element return is not a struct : LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); + + // A flag output is delivered as i8; coerce it to the declared result type + // (e.g. i1, or a wider bool). zext when widening, trunc when narrowing. + // zext (not sext) is correct: a flag output is 0 or 1. + if (e.pin_flag.len != 0) { + Type *rt = this->result_type_of(e); + LLVMTypeRef want = lb_type(m, rt); + LLVMTypeRef got = LLVMTypeOf(v); + if (want != got) { + unsigned want_w = LLVMGetIntTypeWidth(want); + unsigned got_w = LLVMGetIntTypeWidth(got); + if (want_w < got_w) { + v = LLVMBuildTrunc(p->builder, v, want, ""); + } else if (want_w > got_w) { + v = LLVMBuildZExt(p->builder, v, want, ""); + } + // want_w == got_w with differing type identity: same width, no-op. + } + } + result_vals[e.result_index] = v; } @@ -563,4 +666,4 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar lbAsmGenerate_amd64 generator = {}; generator.init(entity); return generator.emit_call(p, args); -} +} \ No newline at end of file diff --git a/src/parser.cpp b/src/parser.cpp index 518beb2f0..2d78991c2 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -541,7 +541,6 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmLabelDecl.name = clone_ast(n->AsmLabelDecl.name, f); break; case Ast_AsmInstruction: - n->AsmInstruction.prefix = clone_ast(n->AsmInstruction.prefix, f); n->AsmInstruction.name = clone_ast(n->AsmInstruction.name, f); n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); break; @@ -2561,6 +2560,7 @@ gb_internal Ast *parse_asm_instruction(AstFile *f) { Ast *instruction = alloc_ast_node(f, Ast_AsmInstruction); instruction->AsmInstruction.name = name; instruction->AsmInstruction.operands = operands; + instruction->AsmInstruction.valid_form_index = -1; return instruction; } case Token_Period: diff --git a/src/parser.hpp b/src/parser.hpp index cbbf84867..fb3445825 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -497,9 +497,10 @@ struct AstSplitArgs { Ast * name; \ }) \ AST_KIND(AsmInstruction, "asm instruction", struct { \ - Ast * prefix; /*optional*/ \ Ast * name; \ Slice operands; \ + u16 mnemonic; \ + i32 valid_form_index; \ }) \ AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ Token open; \ From 5fe724bff3f34216a3acb0bda30c77dec0d3957d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:00:18 +0100 Subject: [PATCH 61/92] Remove `f` suffix e.g. `%flags.z` rather than `%flags.zf` --- src/asm_tables_amd64.cpp | 22 +++++++++++----------- src/llvm_backend_asm.cpp | 10 +++++----- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index fda95ad24..8cbaa9b3e 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -221,21 +221,21 @@ struct Asm_amd64 { i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct {String name; i32 bit; } table[] = { - {str_lit("cf"), 0}, // Carry - {str_lit("pf"), 2}, // Parity - {str_lit("af"), 4}, // Auxiliary Carry - {str_lit("zf"), 6}, // Zero - {str_lit("sf"), 7}, // Sign - {str_lit("tf"), 8}, // Trap - {str_lit("if"), 9}, // Interrupt Enable - {str_lit("df"), 10}, // Direction - {str_lit("of"), 11}, // Overflow + {str_lit("c"), 0}, // Carry + {str_lit("p"), 2}, // Parity + {str_lit("a"), 4}, // Auxiliary Carry + {str_lit("z"), 6}, // Zero + {str_lit("s"), 7}, // Sign + {str_lit("t"), 8}, // Trap + {str_lit("i"), 9}, // Interrupt Enable + {str_lit("d"), 10}, // Direction + {str_lit("o"), 11}, // Overflow {str_lit("iopl"),12}, // I/O Privilege Level (2-bit field: bits 12-13, low bit) {str_lit("nt"), 14}, // Nested Task - {str_lit("rf"), 16}, // Resume + {str_lit("r"), 16}, // Resume {str_lit("vm"), 17}, // Virtual-8086 Mode {str_lit("ac"), 18}, // Alignment Check / Access Control - {str_lit("vif"), 19}, // Virtual Interrupt Flag + {str_lit("vi"), 19}, // Virtual Interrupt Flag {str_lit("vip"), 20}, // Virtual Interrupt Pending {str_lit("id"), 21}, // Identification }; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index e34b33122..f1775e205 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -245,11 +245,11 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // Map an EFLAGS flag name to its LLVM `=@cc` setcc condition, or {} if // the flag has no single-flag setcc form (af/df/if/... can't be a flag output). String flag_output_cc_suffix(String const &pin_flag) override { - if (pin_flag == "cf") return str_lit("c"); // carry - if (pin_flag == "pf") return str_lit("p"); // parity (even) - if (pin_flag == "zf") return str_lit("z"); // zero - if (pin_flag == "sf") return str_lit("s"); // sign - if (pin_flag == "of") return str_lit("o"); // overflow + if (pin_flag == "c") return str_lit("c"); // carry + if (pin_flag == "p") return str_lit("p"); // parity (even) + if (pin_flag == "z") return str_lit("z"); // zero + if (pin_flag == "s") return str_lit("s"); // sign + if (pin_flag == "o") return str_lit("o"); // overflow return {}; } From dd5c2f98fd6ec57d786f655ba26089d11305e971 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:05:33 +0100 Subject: [PATCH 62/92] Always require the results of `asm` templates --- src/check_asm.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 24528dda6..6c077d1de 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1331,6 +1331,10 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity Type *type = alloc_type_proc(ate->param_scope, params, params->Tuple.variables.count, results, results->Tuple.variables.count, false, pt->calling_convention); type->Proc.diverging = pt->diverging; + if (!type->Proc.diverging && results->Tuple.variables.count != 0) { + // always require the results of `asm` templates + type->Proc.require_results = true; + } entity->type = type; From c2dfcb3c28c8424055776cc02ff7603735f29306 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:10:28 +0100 Subject: [PATCH 63/92] Remove debug printing --- src/llvm_backend_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index f1775e205..d107b5032 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -574,7 +574,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (true) { + if (false) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From 55377f71ef55980b95ec2ce836ac6db82e9d7c4b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:21:40 +0100 Subject: [PATCH 64/92] Support `#byte` directive for `asm` templates --- src/check_asm.cpp | 32 ++++++++++++++++++++++++++++++++ src/llvm_backend_asm.cpp | 19 +++++++++++++++++++ src/parser.cpp | 14 ++++++++++++++ src/parser.hpp | 5 +++++ src/parser_pos.cpp | 7 +++++++ 5 files changed, 77 insertions(+) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 6c077d1de..ea50aa45e 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1486,6 +1486,38 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } case_end; + case_ast_node(dir, AsmDirective, instruction_); + String name = dir->name.string; + if (name == "byte") { + if (dir->operands.count == 0) { + error(dir->name, "Expected 1 or more integers for the asm directive #%.*s", LIT(name)); + break; + } + array_clear(&operands); + for (Ast *expr : dir->operands) { + Operand operand = {}; + check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); + array_add(&operands, operand); + } + for (auto const &op : operands) { + if (op.mode != Addressing_Constant) { + error(op.expr, "Expected an integer for the asm directive #%.*s", LIT(name)); + continue; + } + ExactValue ev = exact_value_to_integer(op.value); + if (ev.kind != ExactValue_Integer) { + error(op.expr, "Expected an integer for the asm directive #%.*s", LIT(name)); + continue; + } + i64 i = exact_value_to_i64(ev); + if (i < 0 || i > 255) { + error(op.expr, "Expected an integer within 0..<256 for the asm directive #%.*s, got %lld", LIT(name), cast(long long)i); + continue; + } + } + } + case_end; + default: error(instruction_, "Unexpected instruction in asm template"); break; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index d107b5032..19a902c99 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -480,6 +480,25 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { asm_string = this->write_label(asm_string, &label->name->Ident); asm_string = gb_string_appendc(asm_string, ":"); case_end; + case_ast_node(dir, AsmDirective, instr_); + String name = dir->name.string; + if (name == "byte") { + asm_string = gb_string_appendc(asm_string, ".byte "); + isize op_index = 0; + for (auto const &op : dir->operands) { + if (op_index > 0) { + asm_string = gb_string_appendc(asm_string, ", "); + } + ExactValue ev = exact_value_to_integer(op->tav.value); + GB_ASSERT(ev.kind == ExactValue_Integer); + i64 i = exact_value_to_i64(ev); + asm_string = gb_string_append_fmt(asm_string, "%d", cast(int)i); + op_index += 1; + } + } else { + GB_PANIC("Invalid asm directive: %.*s", LIT(name)); + } + case_end; default: GB_PANIC("Invalid asm instruction"); break; diff --git a/src/parser.cpp b/src/parser.cpp index 2d78991c2..02c35687e 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -551,6 +551,9 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmMemoryOperand.disp = clone_ast(n->AsmMemoryOperand.disp, f); n->AsmMemoryOperand.type = clone_ast(n->AsmMemoryOperand.type, f); break; + case Ast_AsmDirective: + n->AsmDirective.operands = clone_ast_array(n->AsmDirective.operands, f); + break; } return n; } @@ -2573,6 +2576,17 @@ gb_internal Ast *parse_asm_instruction(AstFile *f) { label_decl->AsmLabelDecl.name = name; return label_decl; } + case Token_Hash: + { + Token token = expect_token(f, Token_Hash); + Token name = expect_token(f, Token_Ident); + auto operands = parse_asm_operands(f); + Ast *dir = alloc_ast_node(f, Ast_AsmDirective); + dir->AsmDirective.token = token; + dir->AsmDirective.name = name; + dir->AsmDirective.operands = operands; + return dir; + } } syntax_error(f->curr_token, "Expected an asm instruction, got '%.*s'", LIT(f->curr_token.string)); advance_token(f); diff --git a/src/parser.hpp b/src/parser.hpp index fb3445825..d39b28589 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -512,6 +512,11 @@ struct AstSplitArgs { Ast * type; \ Token close; \ }) \ + AST_KIND(AsmDirective, "asm directive", struct { \ + Token token; \ + Token name; \ + Slice operands; \ + }) \ AST_KIND(_ExprBegin, "", bool) \ AST_KIND(BadExpr, "bad expression", struct { Token begin, end; }) \ AST_KIND(TagExpr, "tag expression", struct { Token token, name; Ast *expr; }) \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 96611b7a8..99f1ce65d 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -27,6 +27,8 @@ gb_internal Token ast_token(Ast *node) { return ast_token(node->AsmInstruction.name); case Ast_AsmMemoryOperand: return node->AsmMemoryOperand.open; + case Ast_AsmDirective: + return node->AsmDirective.token; case Ast_TagExpr: return node->TagExpr.token; case Ast_BadExpr: return node->BadExpr.begin; @@ -197,6 +199,11 @@ Token ast_end_token(Ast *node) { return ast_end_token(node->AsmInstruction.operands[node->AsmInstruction.operands.count-1]); } return ast_end_token(node->AsmInstruction.name); + case Ast_AsmDirective: + if (node->AsmDirective.operands.count > 0) { + return ast_end_token(node->AsmDirective.operands[node->AsmDirective.operands.count-1]); + } + return node->AsmDirective.name; case Ast_AsmMemoryOperand: if (node->AsmMemoryOperand.type) { return ast_end_token(node->AsmMemoryOperand.type); From bd95d2ae66be16a8d5d4281e28347fba0ed625b3 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:32:28 +0100 Subject: [PATCH 65/92] Add `asm` directive `#align N` --- src/check_asm.cpp | 31 +++++++++++++++++++++++++++++++ src/llvm_backend_asm.cpp | 9 +++++++++ 2 files changed, 40 insertions(+) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index ea50aa45e..c847b1932 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1515,7 +1515,38 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity continue; } } + } else if (name == "align") { + if (dir->operands.count != 1) { + error(dir->name, "Expected 1 integer for the asm directive #%.*s", LIT(name)); + break; + } + array_clear(&operands); + for (Ast *expr : dir->operands) { + Operand operand = {}; + check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); + array_add(&operands, operand); + } + for (auto const &op : operands) { + if (op.mode != Addressing_Constant) { + error(op.expr, "Expected a power-of-two integer for the asm directive #%.*s", LIT(name)); + continue; + } + ExactValue ev = exact_value_to_integer(op.value); + if (ev.kind != ExactValue_Integer) { + error(op.expr, "Expected a power-of-two integer for the asm directive #%.*s", LIT(name)); + continue; + } + i64 i = exact_value_to_i64(ev); + if (i < 0 || !is_power_of_two(i)) { + error(op.expr, "Expected a power-of-two integer for the asm directive #%.*s, got %lld", LIT(name), cast(long long)i); + continue; + } + } + + } else { + error(dir->name, "Unknown asm directive: #%.*s", LIT(name)); } + case_end; default: diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 19a902c99..5cca6d89b 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -495,6 +495,15 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { asm_string = gb_string_append_fmt(asm_string, "%d", cast(int)i); op_index += 1; } + } else if (name == "align") { + asm_string = gb_string_appendc(asm_string, ".p2align "); + GB_ASSERT(dir->operands.count == 1); + auto const &op = dir->operands[0]; + ExactValue ev = exact_value_to_integer(op->tav.value); + GB_ASSERT(ev.kind == ExactValue_Integer); + u64 i = exact_value_to_u64(ev); + u64 i_log2 = floor_log2(i); + asm_string = gb_string_append_fmt(asm_string, "%llu", cast(unsigned long long)i_log2); } else { GB_PANIC("Invalid asm directive: %.*s", LIT(name)); } From d71c25dd9bf59ab657515a188e8a24c5ae6881b7 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 13:36:59 +0100 Subject: [PATCH 66/92] `asm`: add `#skip N` and `#nop N` --- src/check_asm.cpp | 28 ++++++++++++++++++++++++++++ src/llvm_backend_asm.cpp | 18 +++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index c847b1932..4f2a21bad 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1543,6 +1543,34 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } } + } else if (name == "skip" || + name == "nop") { + if (dir->operands.count != 1) { + error(dir->name, "Expected 1 integer for the asm directive #%.*s", LIT(name)); + break; + } + array_clear(&operands); + for (Ast *expr : dir->operands) { + Operand operand = {}; + check_asm_instruction_operand(asm_ctx, ctx, entity, &operand, expr, /*allow_memory_operands*/true); + array_add(&operands, operand); + } + for (auto const &op : operands) { + if (op.mode != Addressing_Constant) { + error(op.expr, "Expected an integer >0 for the asm directive #%.*s", LIT(name)); + continue; + } + ExactValue ev = exact_value_to_integer(op.value); + if (ev.kind != ExactValue_Integer) { + error(op.expr, "Expected an integer >0 for the asm directive #%.*s", LIT(name)); + continue; + } + i64 i = exact_value_to_i64(ev); + if (i < 0) { + error(op.expr, "Expected an integer >0 for the asm directive #%.*s, got %lld", LIT(name), cast(long long)i); + continue; + } + } } else { error(dir->name, "Unknown asm directive: #%.*s", LIT(name)); } diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 5cca6d89b..bc6425147 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -496,14 +496,30 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { op_index += 1; } } else if (name == "align") { - asm_string = gb_string_appendc(asm_string, ".p2align "); GB_ASSERT(dir->operands.count == 1); auto const &op = dir->operands[0]; ExactValue ev = exact_value_to_integer(op->tav.value); GB_ASSERT(ev.kind == ExactValue_Integer); u64 i = exact_value_to_u64(ev); u64 i_log2 = floor_log2(i); + asm_string = gb_string_appendc(asm_string, ".p2align "); asm_string = gb_string_append_fmt(asm_string, "%llu", cast(unsigned long long)i_log2); + } else if (name == "skip") { + GB_ASSERT(dir->operands.count == 1); + auto const &op = dir->operands[0]; + ExactValue ev = exact_value_to_integer(op->tav.value); + GB_ASSERT(ev.kind == ExactValue_Integer); + u64 i = exact_value_to_u64(ev); + asm_string = gb_string_appendc(asm_string, ".skip "); + asm_string = gb_string_append_fmt(asm_string, "%llu", cast(unsigned long long)i); + } else if (name == "nop") { + GB_ASSERT(dir->operands.count == 1); + auto const &op = dir->operands[0]; + ExactValue ev = exact_value_to_integer(op->tav.value); + GB_ASSERT(ev.kind == ExactValue_Integer); + u64 i = exact_value_to_u64(ev); + asm_string = gb_string_appendc(asm_string, ".nops "); + asm_string = gb_string_append_fmt(asm_string, "%llu", cast(unsigned long long)i); } else { GB_PANIC("Invalid asm directive: %.*s", LIT(name)); } From d0c3b78ece85128297e817a12ec0442996805b69 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 18:56:47 +0100 Subject: [PATCH 67/92] Allow (parent scope) constants within `asm` templates --- src/check_asm.cpp | 40 +++++++++----- src/llvm_backend_asm.cpp | 112 ++++++++++++++++++++++++--------------- 2 files changed, 98 insertions(+), 54 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 4f2a21bad..e3ad7d6e9 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -447,14 +447,14 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc GB_ASSERT(spec->name->kind == Ast_Ident); - Entity *input = scope_lookup(scope, spec->name->Ident.interned, spec->name->Ident.hash); + Entity *input = scope_lookup_current(scope, spec->name->Ident.interned, spec->name->Ident.hash); Entity *other_scratch = nullptr; String pin = {}; String pin_flag = {}; if (spec->value != nullptr) { if (spec->value->kind == Ast_Ident) { - other_scratch = scope_lookup(scope, spec->value->Ident.interned, spec->value->Ident.hash); + other_scratch = scope_lookup_current(scope, spec->value->Ident.interned, spec->value->Ident.hash); if (other_scratch) { auto group = check_asm_find_group(other_scratch, *asm_template_entity_decls, nullptr); if (!group) { @@ -621,7 +621,7 @@ gb_internal void check_asm_specs(AsmCtx *asm_ctx, CheckerContext *ctx, Scope *sc error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); continue; } - Entity *output = scope_lookup(scope, spec->tied_name->Ident.interned, spec->tied_name->Ident.hash); + Entity *output = scope_lookup_current(scope, spec->tied_name->Ident.interned, spec->tied_name->Ident.hash); if (output == nullptr) { error(spec->name, "Undefined parameter declaration '%.*s'", LIT(spec->name->Ident.token.string)); continue; @@ -1038,14 +1038,28 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * switch (expr->kind) { case_ast_node(i, Ident, expr); - Entity *found = scope_lookup(param_scope, i->interned, i->hash); - if (found == nullptr) { - error(expr, "Undeclared asm parameter '%.*s'", LIT(i->token.string)); + Entity *found = scope_lookup_current(param_scope, i->interned, i->hash); + if (found != nullptr) { + i->entity = found; + operand->mode = Addressing_Value; + operand->type = found->type; return; } - i->entity = found; - operand->mode = Addressing_Value; - operand->type = found->type; + found = scope_lookup(param_scope->parent, i->interned, i->hash); + if (found != nullptr) { + if (found->kind == Entity_Constant) { + i->entity = found; + operand->mode = Addressing_Constant; + operand->value = found->Constant.value; + operand->type = found->type; + + add_type_and_value(ctx, expr, operand->mode, operand->type, operand->value); + } else { + error(expr, "Only asm parameters or constants are allowed to be used within an 'asm' template"); + } + } else { + error(expr, "Undeclared asm parameter or constant '%.*s'", LIT(i->token.string)); + } return; case_end; case_ast_node(bl, BasicLit, expr); @@ -1286,11 +1300,13 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * case_end; case_ast_node(label, AsmLabelDecl, expr); ast_node(name, Ident, label->name); - Entity *found = scope_lookup(label_scope, name->interned, name->hash); + Entity *found = scope_lookup_current(label_scope, name->interned, name->hash); if (found == nullptr) { error(expr, "Undeclared asm label '.%.*s'", LIT(name->token.string)); } name->entity = found; + + add_type_and_value(ctx, expr, Addressing_Value, found->type, {}); return; case_end; } @@ -1321,8 +1337,8 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity } AstProcType *pt = &at->signature->ProcType; - ate->param_scope = create_scope(nullptr, nullptr); - ate->label_scope = create_scope(nullptr, nullptr); + ate->param_scope = create_scope(ctx->info, ctx->scope); + ate->label_scope = create_scope(ctx->info, ctx->scope); ate->decls.allocator = heap_allocator(); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index bc6425147..c5eab544f 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -39,11 +39,64 @@ struct lbAsmGenerate { return &op; } } - GB_PANIC("Could not find asm entity %s", LIT(parameter->token.string)); + GB_PANIC("Could not find asm entity %.*s", LIT(parameter->token.string)); return nullptr; } + gbString write_constant_operand(gbString asm_string, Ast *op, u32 flags) { + GB_ASSERT(op->tav.mode == Addressing_Constant); + + op->tav.value = exact_value_to_integer(op->tav.value); + ExactValue ev = op->tav.value; + GB_ASSERT(ev.kind != ExactValue_Invalid); + switch (ev.kind) { + case ExactValue_Integer: { + i64 val = exact_value_to_i64(ev); + if (flags & WriteOperandFlag_IsScale) { + switch (val) { + case 1: case 2: case 4: case 8: + // okay + break; + default: + error(op, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %lld", cast(long long)val); + break; + } + } else if (flags & WriteOperandFlag_IsScaleLog2) { + switch (val) { + case 0: case 1: case 2: case 3: + // NOTE(bill): AMD64 only supports full scales + val = (cast(i64)1)< op_number, Ast *op, u32 flags) { + if (op->tav.mode == Addressing_Constant) { + return write_constant_operand(asm_string, op, flags); + } + switch (op->kind) { case_ast_node(i, Ident, op); Entity *e = entity_of_node(op); @@ -75,47 +128,7 @@ struct lbAsmGenerate { case_end; case_ast_node(bl, BasicLit, op); - op->tav.value = exact_value_to_integer(op->tav.value); - ExactValue ev = op->tav.value; - GB_ASSERT(ev.kind != ExactValue_Invalid); - switch (ev.kind) { - case ExactValue_Integer: { - i64 val = exact_value_to_i64(ev); - if (flags & WriteOperandFlag_IsScale) { - switch (val) { - case 1: case 2: case 4: case 8: - // okay - break; - default: - error(op, "A scale must be a constant integer or an immediate with the value 1, 2, 4, or 8, got %lld", cast(long long)val); - break; - } - } else if (flags & WriteOperandFlag_IsScaleLog2) { - switch (val) { - case 0: case 1: case 2: case 3: - // NOTE(bill): AMD64 only supports full scales - val = (cast(i64)1)<valid_form_index >= 0); // Otherwise derive from the matched form's operand widths. auto forms = g_asm_amd64.encoding_forms(instr->mnemonic); + if (forms.count <= 1) { + return 0; + } auto &form = forms[instr->valid_form_index]; i32 width = 0; @@ -224,6 +240,18 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { any_vector = true; continue; // xmm/ymm/zmm/k forms take no b/w/l/q suffix } + + // Only register and memory operands contribute an operand-size suffix. + // Relative branch targets (OP_REL8/REL32), immediates (OP_IMM*), and + // labels are NOT operand sizes -- jl/jmp/call/setcc must never get a + // b/w/l/q suffix from their displacement/immediate. + AsmOperandKind kind = g_asm_amd64.kind_from_operand_type(ot); + if (kind != AsmOperand_Register && + kind != AsmOperand_Memory && + kind != AsmOperand_Register_Or_Memory) { + continue; + } + i32 w = g_asm_amd64.operand_type_bit_width(ot); if (w == 8 || w == 16 || w == 32 || w == 64) { width = gb_max(width, w); // GP/memory width From 52ea617143b67cdcea5a8cd16f480188e248472c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:20:32 +0100 Subject: [PATCH 68/92] Minor fixes --- src/llvm_backend_asm.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index c5eab544f..af8d187df 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -135,7 +135,7 @@ struct lbAsmGenerate { asm_string = write_label(asm_string, &label->name->Ident); case_end; default: - GB_PANIC("TODO %s", expr_to_string(op)); + GB_PANIC("TODO(bill): write_operand for '%s'", expr_to_string(op)); break; } return asm_string; @@ -218,7 +218,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } GB_ASSERT(instr->mnemonic != 0); GB_ASSERT(instr->valid_form_index >= 0); - // Otherwise derive from the matched form's operand widths. + auto forms = g_asm_amd64.encoding_forms(instr->mnemonic); if (forms.count <= 1) { return 0; @@ -646,7 +646,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (false) { + if (true) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From e2e4a61003bcf64c8f8df64b45c034ae3b92db05 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:29:42 +0100 Subject: [PATCH 69/92] Remove suffixes --- core/rexcode/isa/x86/printer.odin | 1 + .../x86/tablegen/cpp-compiler/cpp-gen.odin | 22 +++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/core/rexcode/isa/x86/printer.odin b/core/rexcode/isa/x86/printer.odin index 42ef7a5bf..687fbf55f 100644 --- a/core/rexcode/isa/x86/printer.odin +++ b/core/rexcode/isa/x86/printer.odin @@ -53,6 +53,7 @@ mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool) -> string { #partial switch m { case .INVALID: return "???" case .MOVSD_SSE: return lowercase ? "movsd" : "MOVSD" + case .CMPSD_SSE: return lowercase ? "cmpsd" : "CMPSD" } if name, ok := reflect.enum_name_from_value(m); ok { return lowercase ? strings.to_lower(name, context.temp_allocator) : name diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 2fa8f34d9..1c3903f5a 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -221,21 +221,21 @@ main :: proc() { i32 flag_bit_from_name(String const &name, i32 *width_) { static const struct {String name; i32 bit; } table[] = { - {str_lit(\"cf\"), 0}, // Carry - {str_lit(\"pf\"), 2}, // Parity - {str_lit(\"af\"), 4}, // Auxiliary Carry - {str_lit(\"zf\"), 6}, // Zero - {str_lit(\"sf\"), 7}, // Sign - {str_lit(\"tf\"), 8}, // Trap - {str_lit(\"if\"), 9}, // Interrupt Enable - {str_lit(\"df\"), 10}, // Direction - {str_lit(\"of\"), 11}, // Overflow + {str_lit(\"c\"), 0}, // Carry + {str_lit(\"p\"), 2}, // Parity + {str_lit(\"a\"), 4}, // Auxiliary Carry + {str_lit(\"z\"), 6}, // Zero + {str_lit(\"s\"), 7}, // Sign + {str_lit(\"t\"), 8}, // Trap + {str_lit(\"i\"), 9}, // Interrupt Enable + {str_lit(\"d\"), 10}, // Direction + {str_lit(\"o\"), 11}, // Overflow {str_lit(\"iopl\"),12}, // I/O Privilege Level (2-bit field: bits 12-13, low bit) {str_lit(\"nt\"), 14}, // Nested Task - {str_lit(\"rf\"), 16}, // Resume + {str_lit(\"r\"), 16}, // Resume {str_lit(\"vm\"), 17}, // Virtual-8086 Mode {str_lit(\"ac\"), 18}, // Alignment Check / Access Control - {str_lit(\"vif\"), 19}, // Virtual Interrupt Flag + {str_lit(\"vi\"), 19}, // Virtual Interrupt Flag {str_lit(\"vip\"), 20}, // Virtual Interrupt Pending {str_lit(\"id\"), 21}, // Identification }; From 8f2a4346fc4ca0d9a64f0b37887fcc0863c3a5b0 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:31:38 +0100 Subject: [PATCH 70/92] Handle `_SSE` edge cases --- core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin | 9 ++++++--- src/asm_tables_amd64.cpp | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 1c3903f5a..a6f05f973 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -628,11 +628,14 @@ main :: proc() { strings.write_string(&sb, "\t") } - if mnemonic == .INVALID { + #partial switch mnemonic { + case .INVALID: strings.write_string(&sb, "str_lit(\"\"), ") - } else if mnemonic == .MOVSD_SSE { + case .MOVSD_SSE: strings.write_string(&sb, "str_lit(\"movsd\"), ") - } else { + case .CMPSD_SSE: + strings.write_string(&sb, "str_lit(\"cmpsd\"), ") + case: str := strings.to_lower(reflect.enum_string(mnemonic)) fmt.sbprintf(&sb, "str_lit(%q), ", str) delete(str) diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 8cbaa9b3e..d6b5b2d58 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -633,7 +633,7 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit("movlpd"), str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), str_lit("subss"), str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), str_lit("rsqrtps"), str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), - str_lit("xorps"), str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("cmpsd_sse"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), + str_lit("xorps"), str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("cmpsd"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), str_lit("cvtps2pd"), str_lit("cvtpd2ps"), str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), str_lit("paddb"), str_lit("paddw"), str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), str_lit("pmullw"), str_lit("pmulhw"), str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), From c3b2029f649480b416f8113e7c83080f243fd971 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:54:21 +0100 Subject: [PATCH 71/92] Support `asm` template groups --- src/check_asm.cpp | 8 +++ src/check_decl.cpp | 151 ++++++++++++++++++++++++++++++++++++++++++++- src/check_expr.cpp | 16 +++++ src/checker.cpp | 9 ++- src/entity.cpp | 1 + src/parser.cpp | 44 +++++++++++++ src/parser.hpp | 6 ++ src/parser_pos.cpp | 2 + 8 files changed, 235 insertions(+), 2 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index e3ad7d6e9..86769af6a 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1037,6 +1037,14 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * gb_unused(label_scope); switch (expr->kind) { + case_ast_node(pe, ParenExpr, expr); + check_expr(ctx, operand, expr); + if (operand->mode != Addressing_Constant) { + error(expr, "Asm operands within parentheses can only compile time constants"); + } + return; + case_end; + case_ast_node(i, Ident, expr); Entity *found = scope_lookup_current(param_scope, i->interned, i->hash); if (found != nullptr) { diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 520aa5e5d..6e89dbfcd 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -1985,6 +1985,151 @@ gb_internal void check_proc_group_decl(CheckerContext *ctx, Entity *pg_entity, D check_objc_methods(ctx, pg_entity, ac); } +gb_internal void check_asm_group_decl(CheckerContext *ctx, Entity *asm_entity, DeclInfo *d) { + GB_ASSERT(asm_entity->kind == Entity_ProcGroup); + auto *pge = &asm_entity->ProcGroup; + String proc_group_name = asm_entity->token.string; + + ast_node(pg, AsmGroup, d->init_expr); + + pge->entities = array_make(permanent_allocator(), 0, pg->args.count); + + // NOTE(bill): This must be set here to prevent cycles in checking if someone + // places the entity within itself + asm_entity->type = t_invalid; + + PtrSet entity_set = {}; + ptr_set_init(&entity_set, 2*pg->args.count); + + for (Ast *arg_ : pg->args) { + Ast *arg = arg_; + Entity *e = nullptr; + Operand o = {}; + if (arg->kind == Ast_BinaryExpr && arg->BinaryExpr.op.kind == Token_where) { + Ast *cond_expr = arg->BinaryExpr.right; + Operand cond = {}; + check_expr(ctx, &cond, cond_expr); + if (cond.mode != Addressing_Invalid) { + if (cond.mode != Addressing_Constant || !is_type_boolean(cond.type) || cond.value.kind != ExactValue_Bool) { + error(arg, "Expected a constant binary expression for the 'where' clause"); + } else if (!cond.value.value_bool) { + continue; + } + } + + arg = arg->BinaryExpr.left; + } + + if (arg->kind == Ast_Ident) { + e = check_ident(ctx, &o, arg, nullptr, nullptr, true); + } else if (arg->kind == Ast_SelectorExpr) { + e = check_selector(ctx, &o, arg, nullptr); + } + if (e == nullptr) { + error(arg, "Expected a valid entity name in asm group, got %.*s", LIT(ast_strings[arg->kind])); + continue; + } + if (e->kind != Entity_AsmTemplate) { + error(arg, "Expected an asm template"); + continue; + } + + if (ptr_set_update(&entity_set, e)) { + error(arg, "Previous use of `%.*s` in asm group", LIT(e->token.string)); + continue; + } + array_add(&pge->entities, e); + } + + ptr_set_destroy(&entity_set); + + for (isize j = 0; j < pge->entities.count; j++) { + Entity *p = pge->entities[j]; + if (p->type == t_invalid) { + // NOTE(bill): This invalid overload has already been handled + continue; + } + + if (p->flags & EntityFlag_Disabled) { + continue; + } + + String name = p->token.string; + + for (isize k = j+1; k < pge->entities.count; k++) { + Entity *q = pge->entities[k]; + GB_ASSERT(p != q); + + bool is_invalid = false; + + TokenPos pos = q->token.pos; + + if (q->type == nullptr || q->type == t_invalid) { + continue; + } + + + ERROR_BLOCK(); + + if (q->flags & EntityFlag_Disabled) { + continue; + } + + ProcTypeOverloadKind kind = are_proc_types_overload_safe(p->type, q->type); + bool both_have_where_clauses = false; + if (p->decl_info != nullptr && q->decl_info != nullptr && + p->decl_info->proc_lit != nullptr && q->decl_info->proc_lit != nullptr) { + GB_ASSERT(p->decl_info->proc_lit->kind == Ast_ProcLit); + GB_ASSERT(q->decl_info->proc_lit->kind == Ast_ProcLit); + auto pl = &p->decl_info->proc_lit->ProcLit; + auto ql = &q->decl_info->proc_lit->ProcLit; + + // Allow collisions if the procedures both have 'where' clauses and are both polymorphic + bool pw = pl->where_token.kind != Token_Invalid && is_type_polymorphic(p->type, true); + bool qw = ql->where_token.kind != Token_Invalid && is_type_polymorphic(q->type, true); + both_have_where_clauses = pw && qw; + } + + if (!both_have_where_clauses) switch (kind) { + case ProcOverload_Identical: + error(p->token, "Overloaded asm template '%.*s' has the same type as another asm template in the asm template group '%.*s'", LIT(name), LIT(proc_group_name)); + is_invalid = true; + break; + // case ProcOverload_CallingConvention: + // error(p->token, "Overloaded asm template '%.*s' has the same type as another asm template in the asm template group '%.*s'", LIT(name), LIT(proc_group_name)); + // is_invalid = true; + // break; + case ProcOverload_ParamVariadic: + error(p->token, "Overloaded asm template '%.*s' has the same type as another asm template in the asm template group '%.*s'", LIT(name), LIT(proc_group_name)); + is_invalid = true; + break; + case ProcOverload_ResultCount: + case ProcOverload_ResultTypes: + error(p->token, "Overloaded asm template '%.*s' has the same parameters but different results in the asm template group '%.*s'", LIT(name), LIT(proc_group_name)); + is_invalid = true; + break; + case ProcOverload_Polymorphic: + break; + case ProcOverload_ParamCount: + case ProcOverload_ParamTypes: + case ProcOverload_TargetFeatures: + // This is okay :) + break; + + } + + if (is_invalid) { + error_line("\tprevious asm template at %s\n", token_pos_to_string(pos)); + q->type = t_invalid; + } + } + } + + AttributeContext ac = {}; + check_decl_attributes(ctx, d->attributes, proc_group_attribute, &ac); + check_objc_methods(ctx, asm_entity, ac); +} + #include "check_asm.cpp" @@ -2061,7 +2206,11 @@ gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, check_proc_decl(&c, e, d); break; case Entity_ProcGroup: - check_proc_group_decl(&c, e, d); + if (e->ProcGroup.is_asm_group) { + check_asm_group_decl(&c, e, d); + } else { + check_proc_group_decl(&c, e, d); + } break; case Entity_AsmTemplate: diff --git a/src/check_expr.cpp b/src/check_expr.cpp index dd6449c61..1bc79a10a 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -12518,6 +12518,12 @@ gb_internal ExprKind check_expr_base_internal(CheckerContext *c, Operand *o, Ast o->mode = Addressing_Invalid; case_end; + case_ast_node(ag, AsmGroup, node); + error(node, "Illegal use of a asm group"); + o->mode = Addressing_Invalid; + case_end; + + case_ast_node(pl, ProcLit, node); CheckerContext ctx = *c; @@ -13039,6 +13045,16 @@ gb_internal gbString write_expr_to_string(gbString str, Ast *node, bool shorthan str = gb_string_append_rune(str, '}'); case_end; + case_ast_node(pg, AsmGroup, node); + str = gb_string_appendc(str, "asm{"); + for_array(i, pg->args) { + if (i > 0) str = gb_string_appendc(str, ", "); + str = write_expr_to_string(str, pg->args[i], shorthand); + } + str = gb_string_append_rune(str, '}'); + case_end; + + case_ast_node(pl, ProcLit, node); str = write_expr_to_string(str, pl->type, shorthand); if (pl->body) { diff --git a/src/checker.cpp b/src/checker.cpp index 22f557275..d6ca0b350 100644 --- a/src/checker.cpp +++ b/src/checker.cpp @@ -5064,7 +5064,14 @@ gb_internal void check_collect_value_decl(CheckerContext *c, Ast *decl) { if (fl != nullptr) { error(name, "Procedure groups are not allowed within a foreign block"); } - } else if (init->kind == Ast_AsmTemplate) { + } else if (init->kind == Ast_AsmGroup) { + ast_node(ag, AsmGroup, init); + e = alloc_entity_proc_group(d->scope, token, nullptr); + e->ProcGroup.is_asm_group = true; + if (fl != nullptr) { + error(name, "Asm template groups are not allowed within a foreign block"); + } + }else if (init->kind == Ast_AsmTemplate) { if (c->scope->flags&ScopeFlag_Type) { error(name, "Asm templates are not allowed within a struct"); continue; diff --git a/src/entity.cpp b/src/entity.cpp index ea5317447..8248515f4 100644 --- a/src/entity.cpp +++ b/src/entity.cpp @@ -316,6 +316,7 @@ struct Entity { bool is_objc_class_method : 1; } Procedure; struct { + bool is_asm_group; Array entities; } ProcGroup; struct { diff --git a/src/parser.cpp b/src/parser.cpp index 02c35687e..99175c3fa 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -237,6 +237,9 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { case Ast_ProcGroup: n->ProcGroup.args = clone_ast_array(n->ProcGroup.args, f); break; + case Ast_AsmGroup: + n->AsmGroup.args = clone_ast_array(n->AsmGroup.args, f); + break; case Ast_ProcLit: n->ProcLit.type = clone_ast(n->ProcLit.type, f); n->ProcLit.body = clone_ast(n->ProcLit.body, f); @@ -975,6 +978,15 @@ gb_internal Ast *ast_proc_group(AstFile *f, Token token, Token open, Token close return result; } +gb_internal Ast *ast_asm_group(AstFile *f, Token token, Token open, Token close, Array const &args) { + Ast *result = alloc_ast_node(f, Ast_AsmGroup); + result->AsmGroup.token = token; + result->AsmGroup.open = open; + result->AsmGroup.close = close; + result->AsmGroup.args = slice_from_array(args); + return result; +} + gb_internal Ast *ast_proc_lit(AstFile *f, Ast *type, Ast *body, u64 tags, Token where_token, Array const &where_clauses) { Ast *result = alloc_ast_node(f, Ast_ProcLit); result->ProcLit.type = type; @@ -2466,6 +2478,8 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { case Token_Float: case Token_Rune: return ast_basic_lit(f, advance_token(f)); + case Token_OpenParen: + return parse_expr(f, false); case Token_OpenBracket: if (allow_memory_operand) { Token open = expect_token(f, Token_OpenBracket); @@ -3484,6 +3498,36 @@ gb_internal Ast *parse_operand(AstFile *f, bool lhs) { } case Token_asm: + if (peek_token(f).kind == Token_OpenBrace) { // asm group + Token token = expect_token(f, Token_asm); + Token open = expect_token(f, Token_OpenBrace); + + auto args = array_make(ast_allocator(f)); + + while (f->curr_token.kind != Token_CloseBrace && + f->curr_token.kind != Token_EOF) { + Ast *elem = parse_expr(f, false); + + if (f->curr_token.kind == Token_where) { + Token where = expect_token(f, Token_where); + Ast *cond = parse_expr(f, false); + elem = ast_binary_expr(f, where, elem, cond); + } + + array_add(&args, elem); + if (!allow_field_separator(f)) { + break; + } + } + + Token close = expect_token(f, Token_CloseBrace); + + if (args.count == 0) { + syntax_error(token, "Expected a least 1 argument in a procedure group"); + } + + return ast_asm_group(f, token, open, close, args); + } return parse_asm_template(f); } diff --git a/src/parser.hpp b/src/parser.hpp index d39b28589..e945cadc3 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -451,6 +451,12 @@ struct AstSplitArgs { Token close; \ Slice args; \ }) \ + AST_KIND(AsmGroup, "asm group", struct { \ + Token token; \ + Token open; \ + Token close; \ + Slice args; \ + }) \ AST_KIND(ProcLit, "procedure literal", struct { \ Ast *type; \ Ast *body; \ diff --git a/src/parser_pos.cpp b/src/parser_pos.cpp index 99f1ce65d..70ba92728 100644 --- a/src/parser_pos.cpp +++ b/src/parser_pos.cpp @@ -6,6 +6,7 @@ gb_internal Token ast_token(Ast *node) { case Ast_BasicLit: return node->BasicLit.token; case Ast_BasicDirective: return node->BasicDirective.token; case Ast_ProcGroup: return node->ProcGroup.token; + case Ast_AsmGroup: return node->AsmGroup.token; case Ast_ProcLit: return ast_token(node->ProcLit.type); case Ast_CompoundLit: if (node->CompoundLit.type != nullptr) { @@ -164,6 +165,7 @@ Token ast_end_token(Ast *node) { case Ast_BasicLit: return node->BasicLit.token; case Ast_BasicDirective: return node->BasicDirective.token; case Ast_ProcGroup: return node->ProcGroup.close; + case Ast_AsmGroup: return node->AsmGroup.close; case Ast_ProcLit: if (node->ProcLit.body) { return ast_end_token(node->ProcLit.body); From 2738ff640dd9c8ec628400efc49f8fb45ebe2c77 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:56:03 +0100 Subject: [PATCH 72/92] Minor text fix --- src/check_decl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 6e89dbfcd..cc12791c8 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2026,7 +2026,7 @@ gb_internal void check_asm_group_decl(CheckerContext *ctx, Entity *asm_entity, D e = check_selector(ctx, &o, arg, nullptr); } if (e == nullptr) { - error(arg, "Expected a valid entity name in asm group, got %.*s", LIT(ast_strings[arg->kind])); + error(arg, "Expected a valid entity name in asm template group, got %.*s", LIT(ast_strings[arg->kind])); continue; } if (e->kind != Entity_AsmTemplate) { @@ -2035,7 +2035,7 @@ gb_internal void check_asm_group_decl(CheckerContext *ctx, Entity *asm_entity, D } if (ptr_set_update(&entity_set, e)) { - error(arg, "Previous use of `%.*s` in asm group", LIT(e->token.string)); + error(arg, "Previous use of `%.*s` in asm template group", LIT(e->token.string)); continue; } array_add(&pge->entities, e); From 6646a7b38e5758b888f6467c475086a20eed86ba Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:57:21 +0100 Subject: [PATCH 73/92] Remove redundant code --- src/check_decl.cpp | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/check_decl.cpp b/src/check_decl.cpp index cc12791c8..72b4a5892 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2068,7 +2068,6 @@ gb_internal void check_asm_group_decl(CheckerContext *ctx, Entity *asm_entity, D continue; } - ERROR_BLOCK(); if (q->flags & EntityFlag_Disabled) { @@ -2077,18 +2076,7 @@ gb_internal void check_asm_group_decl(CheckerContext *ctx, Entity *asm_entity, D ProcTypeOverloadKind kind = are_proc_types_overload_safe(p->type, q->type); bool both_have_where_clauses = false; - if (p->decl_info != nullptr && q->decl_info != nullptr && - p->decl_info->proc_lit != nullptr && q->decl_info->proc_lit != nullptr) { - GB_ASSERT(p->decl_info->proc_lit->kind == Ast_ProcLit); - GB_ASSERT(q->decl_info->proc_lit->kind == Ast_ProcLit); - auto pl = &p->decl_info->proc_lit->ProcLit; - auto ql = &q->decl_info->proc_lit->ProcLit; - - // Allow collisions if the procedures both have 'where' clauses and are both polymorphic - bool pw = pl->where_token.kind != Token_Invalid && is_type_polymorphic(p->type, true); - bool qw = ql->where_token.kind != Token_Invalid && is_type_polymorphic(q->type, true); - both_have_where_clauses = pw && qw; - } + // NOTE(bill): asm template do not have `where` clauses if (!both_have_where_clauses) switch (kind) { case ProcOverload_Identical: From ad1ef6328df802fa074687d7c63eb4073c2f6fe9 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 19:58:00 +0100 Subject: [PATCH 74/92] Remove debug print --- src/llvm_backend_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index af8d187df..7dbf84e15 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -646,7 +646,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (true) { + if (false) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! From a2bcf3177a7960467478d0c50c36c789a95664da Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 21:10:24 +0100 Subject: [PATCH 75/92] Improve error messages for register class printing --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 45 +++++++++++++++++++ src/asm_tables.cpp | 17 +++++++ src/asm_tables_amd64.cpp | 42 +++++++++++++++++ src/check_asm.cpp | 13 +++++- src/llvm_backend_asm.cpp | 13 ++++-- 5 files changed, 125 insertions(+), 5 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index a6f05f973..489f5cae7 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -493,6 +493,51 @@ main :: proc() { """) strings.write_string(&sb, "\n\n") + strings.write_string(&sb, """ + AsmRegClass reg_class_from_operand_type(OperandType type) { + switch (type) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + return AsmRegClass_Integer; + + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_XMM0_IMPL: + return AsmRegClass_Vector; + + case OP_K: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmRegClass_Mask; + + case OP_STI: + case OP_ST0_IMPL: + return AsmRegClass_Float; + + case OP_MM: + case OP_MM_M64: + return AsmRegClass_Vector; + + case OP_SREG: case OP_CR: case OP_DR: + case OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64: + case OP_M80: case OP_M128: case OP_M256: case OP_M512: + case OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64: + case OP_M16_16: case OP_M16_32: case OP_M16_64: + case OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64: + case OP_IMM8SX: + case OP_ONE_IMPL: + case OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64: + case OP_REL8: case OP_REL32: + case OP_NONE: + default: + return AsmRegClass_Unknown; + } + } + """) + strings.write_string(&sb, "\n\n") + strings.write_string(&sb, """ bool operand_type_is_implicit(OperandType t) { switch (t) { diff --git a/src/asm_tables.cpp b/src/asm_tables.cpp index e599ff1b5..eb7e3c109 100644 --- a/src/asm_tables.cpp +++ b/src/asm_tables.cpp @@ -4,8 +4,25 @@ enum AsmRegClass : u8 { AsmRegClass_Float, AsmRegClass_Vector, AsmRegClass_Mask, + + AsmRegClass_COUNT }; +gb_global String const asm_reg_class_strings[AsmRegClass_COUNT] = { + str_lit("unknown"), + str_lit("integer"), + str_lit("float"), + str_lit("vector"), + str_lit("mask"), +}; + +gb_global String const asm_reg_class_strings_with_article[AsmRegClass_COUNT] = { + str_lit("an unknown"), + str_lit("an integer"), + str_lit("a float"), + str_lit("a vector"), + str_lit("a mask"), +}; enum AsmOperandKind : u8 { AsmOperand_Invalid, diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index d6b5b2d58..1c229c97d 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -510,6 +510,48 @@ struct Asm_amd64 { } } + AsmRegClass reg_class_from_operand_type(OperandType type) { + switch (type) { + case OP_R8: case OP_R16: case OP_R32: case OP_R64: + case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: + case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: + case OP_CL_IMPL: case OP_DX_IMPL: + return AsmRegClass_Integer; + + case OP_XMM: case OP_YMM: case OP_ZMM: + case OP_XMM_M32: case OP_XMM_M64: case OP_XMM_M128: + case OP_YMM_M256: case OP_ZMM_M512: + case OP_XMM0_IMPL: + return AsmRegClass_Vector; + + case OP_K: + case OP_K_M8: case OP_K_M16: case OP_K_M32: case OP_K_M64: + return AsmRegClass_Mask; + + case OP_STI: + case OP_ST0_IMPL: + return AsmRegClass_Float; + + case OP_MM: + case OP_MM_M64: + return AsmRegClass_Vector; + + case OP_SREG: case OP_CR: case OP_DR: + case OP_M: case OP_M8: case OP_M16: case OP_M32: case OP_M64: + case OP_M80: case OP_M128: case OP_M256: case OP_M512: + case OP_MOFFS8: case OP_MOFFS16: case OP_MOFFS32: case OP_MOFFS64: + case OP_M16_16: case OP_M16_32: case OP_M16_64: + case OP_IMM8: case OP_IMM16: case OP_IMM32: case OP_IMM64: + case OP_IMM8SX: + case OP_ONE_IMPL: + case OP_PTR16_16: case OP_PTR16_32: case OP_PTR16_64: + case OP_REL8: case OP_REL32: + case OP_NONE: + default: + return AsmRegClass_Unknown; + } + } + bool operand_type_is_implicit(OperandType t) { switch (t) { case OP_AL_IMPL: case OP_AX_IMPL: diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 86769af6a..50515a490 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -818,6 +818,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm auto possible_kinds = slice_make(heap_allocator(), max_count); defer (slice_free(&possible_kinds, heap_allocator())); + auto possible_class_kinds = slice_make(heap_allocator(), max_count); + defer (slice_free(&possible_class_kinds, heap_allocator())); + bool matched = false; isize valid_form_index = -1; @@ -950,6 +953,7 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm AsmOperandKind dst = asm_ctx->kind_from_operand_type(type); AsmOperandKind src = determine_asm_operand_kind(&operands[i]); possible_kinds[i] = dst; + possible_class_kinds[i] = asm_ctx->reg_class_from_operand_type(type); bool kind_ok = (dst == src) || (dst == AsmOperand_Register_Or_Memory && (src == AsmOperand_Register || src == AsmOperand_Memory)); @@ -983,6 +987,9 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm auto dst = possible_kinds[i]; AsmOperandKind src = determine_asm_operand_kind(&operands[i]); + AsmRegClass dst_reg_class = possible_class_kinds[i]; + AsmRegClass src_reg_class = check_asm_reg_class_from_type(operands[i].type); + AsmMismatch m = (i < MAX_VARIANT_COUNT) ? mismatch[i] : AsmMismatch_None; if (m == AsmMismatch_ImmRange) { @@ -1005,8 +1012,10 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm error(operands[i].expr, "'%.*s' operand-%td has the wrong size: expected a %u-bit operand, got %u-bit", LIT(name), i, cast(unsigned)want_bits[i], cast(unsigned)got_bits[i]); } else if (m == AsmMismatch_Class) { - error(operands[i].expr, "'%.*s' operand-%td is in the wrong register class, expected %.*s operand, got %.*s", - LIT(name), i, LIT(asm_operand_kind_expected_strings[dst]), LIT(asm_operand_kind_expected_strings[src])); + error(operands[i].expr, "'%.*s' operand-%td is in the wrong register class, expected %d-bit %.*s %.*s, got %d-bit %.*s %.*s", + LIT(name), i, + want_bits[i], LIT(asm_reg_class_strings[dst_reg_class]), LIT(asm_operand_kind_strings[dst]), + got_bits[i], LIT(asm_reg_class_strings[src_reg_class]), LIT(asm_operand_kind_strings[src])); } else if (dst) { error(operands[i].expr, "'%.*s' operand-%td has an invalid kind, expected %.*s operand", LIT(name), i, LIT(asm_operand_kind_expected_strings[dst])); diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 7dbf84e15..215d0e7d5 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -735,7 +735,14 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Array const &args) { - lbAsmGenerate_amd64 generator = {}; - generator.init(entity); - return generator.emit_call(p, args); + lbAsmGenerate *generator = nullptr; + if (build_context.metrics.arch == TargetArch_amd64) { + lbAsmGenerate_amd64 generator_amd64 = {}; + generator = &generator_amd64; + } else { + compiler_error("Architecture does not support asm templates"); + return {}; + } + generator->init(entity); + return generator->emit_call(p, args); } \ No newline at end of file From 77bedf9947ed1c6c77e0ddb67a5d135ba448f4fb Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 21:37:03 +0100 Subject: [PATCH 76/92] Fix scratch register pinning --- src/check_asm.cpp | 2 ++ src/llvm_backend_asm.cpp | 7 +++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 50515a490..f124168f3 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1050,6 +1050,8 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * check_expr(ctx, operand, expr); if (operand->mode != Addressing_Constant) { error(expr, "Asm operands within parentheses can only compile time constants"); + } else { + error(expr, "Asm operands with parentheses are not currently supported"); } return; case_end; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 215d0e7d5..2fc957377 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -92,7 +92,7 @@ struct lbAsmGenerate { } - gbString write_operand(gbString asm_string, Array op_number, Ast *op, u32 flags) { + gbString write_operand(gbString asm_string, Array const &op_number, Ast *op, u32 flags) { if (op->tav.mode == Addressing_Constant) { return write_constant_operand(asm_string, op, flags); } @@ -387,14 +387,13 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { array_add(&ret_types, LLVMInt8TypeInContext(ctx)); // Counted in $N even though never referenced in the body. - op_number[i] = next_op++; + op_number[i] = next_op++; continue; } bool is_output = e.param_group == AsmTemplateEntityDeclParamGroup_Output; bool is_alloc_scratch = e.param_group == AsmTemplateEntityDeclParamGroup_Scratch - && e.kind == AsmTemplateEntityDecl_Register - && e.pin.len == 0; + && e.kind == AsmTemplateEntityDecl_Register; if (!is_output && !is_alloc_scratch) { continue; } From 582ff64bee044a66e5caa74f81ed1b841f813527 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 17 Aug 2026 22:58:51 +0100 Subject: [PATCH 77/92] General clean up of llvm_backend_asm.cpp code --- src/check_asm.cpp | 2 +- src/llvm_backend_asm.cpp | 127 ++++++++++++++++++--------------------- 2 files changed, 60 insertions(+), 69 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index f124168f3..a75b68c35 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1049,7 +1049,7 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * case_ast_node(pe, ParenExpr, expr); check_expr(ctx, operand, expr); if (operand->mode != Addressing_Constant) { - error(expr, "Asm operands within parentheses can only compile time constants"); + error(expr, "Asm operands within parentheses can only compile time constants, if they were supported"); } else { error(expr, "Asm operands with parentheses are not currently supported"); } diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 2fc957377..fce7eccf9 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -92,7 +92,7 @@ struct lbAsmGenerate { } - gbString write_operand(gbString asm_string, Array const &op_number, Ast *op, u32 flags) { + gbString write_operand(gbString asm_string, Slice const &op_number, Ast *op, u32 flags) { if (op->tav.mode == Addressing_Constant) { return write_constant_operand(asm_string, op, flags); } @@ -167,7 +167,7 @@ struct lbAsmGenerate { virtual char instruction_size_suffix(AstAsmInstruction *instr) = 0; virtual char size_suffix_for_operand(Ast *op) = 0; - virtual gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; + virtual gbString write_memory_operand(gbString asm_string, Slice const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) = 0; virtual lbValue emit_call(lbProcedure *p, Array const &args) = 0; virtual String flag_output_cc_suffix(String const &pin_flag) = 0; @@ -206,16 +206,12 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // size suffix, or 0 if none. The checker has already verified the annotation // agrees with the matched encoding form, so a suffix here can never conflict. char instruction_size_suffix(AstAsmInstruction *instr) override { - char suffix = 0; for (Ast *operand : instr->operands) { char s = this->size_suffix_for_operand(operand); if (s != 0) { - suffix = s; + return s; } } - if (suffix) { - return suffix; - } GB_ASSERT(instr->mnemonic != 0); GB_ASSERT(instr->valid_form_index >= 0); @@ -223,12 +219,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { if (forms.count <= 1) { return 0; } - auto &form = forms[instr->valid_form_index]; + auto const &form = forms[instr->valid_form_index]; i32 width = 0; - bool any_vector = false; - for (isize k = 0; k < gb_count_of(form.ops); k++) { - auto ot = form.ops[k]; + for (auto ot : form.ops) { if (ot == g_asm_amd64.OP_NONE) { break; } @@ -237,8 +231,8 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } AsmRegClass cls = g_asm_amd64.operand_type_reg_class(ot); if (cls == AsmRegClass_Vector || cls == AsmRegClass_Mask) { - any_vector = true; - continue; // xmm/ymm/zmm/k forms take no b/w/l/q suffix + // xmm/ymm/zmm/k forms take no b/w/l/q suffix + return 0; } // Only register and memory operands contribute an operand-size suffix. @@ -258,15 +252,13 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } } - if (any_vector || width == 0) { - return 0; // vector op, or nothing that needs a GP-width suffix - } switch (width) { case 8: return 'b'; case 16: return 'w'; case 32: return 'l'; case 64: return 'q'; } + // vector op, or nothing that needs a GP-width suffix return 0; } @@ -282,7 +274,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } - gbString write_memory_operand(gbString asm_string, Array const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { + gbString write_memory_operand(gbString asm_string, Slice const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { if (mem_op->disp) { asm_string = this->write_operand(asm_string, op_number, mem_op->disp, flags&~WriteOperandFlag_PrintPrefixes); } @@ -313,22 +305,25 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { lbModule *m = p->module; LLVMContextRef ctx = m->ctx; - // Assumed frontend accessor: template string, flags, dialect, and the operand table. + gbString asm_string = gb_string_make_reserve(heap_allocator(), 256); + gbString constraints = gb_string_make_reserve(heap_allocator(), 64); + defer ({ + gb_string_free(constraints); + gb_string_free(asm_string); + }); + TEMPORARY_ALLOCATOR_GUARD(); - gbString asm_string = gb_string_make_reserve(temporary_allocator(), 64); - gbString constraints = gb_string_make_reserve(temporary_allocator(), 64); - - auto param_types = array_make(temporary_allocator(), 0, ops->count); + auto param_types = array_make (temporary_allocator(), 0, ops->count); auto call_args = array_make(temporary_allocator(), 0, ops->count); - auto ret_types = array_make(temporary_allocator(), 0, ops->count); + auto ret_types = array_make (temporary_allocator(), 0, ops->count); // Per-operand bookkeeping, indexed the same as `ops` (via total_index). - auto op_number = array_make(temporary_allocator(), ops->count, ops->count); // $N, or -1 for clobbers/views - auto ret_slot = array_make(temporary_allocator(), ops->count, ops->count); // return-struct index, or -1 + auto op_number = slice_make(temporary_allocator(), ops->count); // $N, or -1 for clobbers/views + auto ret_slot = slice_make(temporary_allocator(), ops->count); // return-struct index, or -1 for_array(i, *ops) { op_number[i] = -1; - ret_slot[i] = -1; + ret_slot [i] = -1; } // elementtype() attrs to attach after the call is built (indirect/memory operands). @@ -338,7 +333,6 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { }; auto elem_attrs = array_make(temporary_allocator(), 0, ops->count); - i32 next_op = 0; // running $N counter (outputs first, then inputs) auto sep = [&]() { if (gb_string_length(constraints) != 0) { @@ -348,17 +342,20 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { auto raw = [&](char const *s) { constraints = gb_string_appendc(constraints, s); }; - auto put = [&](String s) { - constraints = gb_string_append_length(constraints, s.text, s.len); + auto clobber = [&](char const *start, String mid, char const *end) { + constraints = gb_string_appendc(constraints, start); + constraints = gb_string_append_length(constraints, mid.text, mid.len); + constraints = gb_string_appendc(constraints, end); }; - auto add_arg = [&](LLVMValueRef v) -> unsigned { - unsigned pos = cast(unsigned)call_args.count; - array_add(¶m_types, LLVMTypeOf(v)); - array_add(&call_args, v); - return pos; + auto add_input_value = [](Array *param_types, Array *call_args, LLVMValueRef v) { + array_add(param_types, LLVMTypeOf(v)); + array_add(call_args, v); }; + + i32 next_op = 0; // running $N counter (outputs first, then inputs) + // Pass 1: outputs // Real outputs plus *unpinned* register scratch (modeled as discarded // early-clobber outputs, since a clobber can only name a fixed register). @@ -379,9 +376,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { GB_ASSERT_MSG(suffix.len != 0, "asm: flag '%.*s' has no setcc condition form", LIT(e.pin_flag)); sep(); - raw("={@cc"); - put(suffix); - raw("}"); + clobber("={@cc", suffix, "}"); ret_slot[i] = cast(i32)ret_types.count; array_add(&ret_types, LLVMInt8TypeInContext(ctx)); @@ -406,7 +401,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { raw("&"); } if (e.pin.len != 0) { - raw("{"); put(e.pin); raw("}"); + clobber("{", e.pin, "}"); } else { raw(this->class_letter(e.reg_class)); } @@ -440,27 +435,21 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { i32 n = op_number[e.tie]; GB_ASSERT(n >= 0); constraints = gb_string_append_fmt(constraints, "%d", n); - add_arg(v.value); + add_input_value(¶m_types, &call_args, v.value); } else { switch (e.kind) { case AsmTemplateEntityDecl_Register: case AsmTemplateEntityDecl_Memory: if (e.pin.len != 0) { - raw("{"); put(e.pin); raw("}"); + clobber("{", e.pin, "}"); } else { raw(this->class_letter(e.reg_class)); } - add_arg(v.value); + add_input_value(¶m_types, &call_args, v.value); break; - // case AsmTemplateEntityDecl_Memory: { - // raw("*m"); // indirect - // unsigned pos = add_arg(v.value); - // array_add(&elem_attrs, ElemAttr{pos, lb_type(m, type_deref(v.type))}); - // break; - // } case AsmTemplateEntityDecl_Immediate: raw("i"); // TODO: "n" if a known-constant integer is required - add_arg(v.value); + add_input_value(¶m_types, &call_args, v.value); break; default: GB_PANIC("asm: invalid input operand kind"); @@ -486,11 +475,8 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // encoded as a mnemonic suffix (crc32 -> crc32b). The checker has already // verified the annotation agrees with the matched form, so an emitted // suffix can never conflict with a register operand's implied width. - { - char suffix = this->instruction_size_suffix(instr); - if (suffix != 0) { - asm_string = gb_string_append_length(asm_string, &suffix, 1); - } + if (char suffix = this->instruction_size_suffix(instr)) { + asm_string = gb_string_append_length(asm_string, &suffix, 1); } asm_string = gb_string_appendc(asm_string, " "); @@ -582,7 +568,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { switch (e.kind) { case AsmTemplateEntityDecl_Register: // pinned -> real clobber GB_ASSERT(e.pin.len != 0); - raw("~{"); put(e.pin); raw("}"); + clobber("~{", e.pin, "}"); string_set_update(&emitted_reg_clobbers, e.pin); break; case AsmTemplateEntityDecl_Memory: // general memory clobber @@ -601,7 +587,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { continue; // already clobbered as a pinned scratch; don't double-emit } sep(); - raw("~{"); put(reg); raw("}"); + clobber("~{", reg, "}"); string_set_update(&emitted_reg_clobbers, reg); } @@ -609,7 +595,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { if (tmpl_entity->AsmTemplate.clobber_flags) { sep(); if (build_context.metrics.arch == TargetArch_amd64) { - raw("~{dirflag},~{fpsr},~{flags}"); // clang's canonical x86 flags clobber + // clang's canonical x86 flags clobber + raw("~{dirflag}"); sep(); + raw("~{fpsr}"); sep(); + raw("~{flags}"); } else { raw("~{cc}"); // AArch64 uses ~{cc} } @@ -657,24 +646,24 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // Attach elementtype() to every indirect operand's pointer arg (opaque-pointer requirement). unsigned et_kind = LLVMGetEnumAttributeKindForName("elementtype", 11); - for (isize k = 0; k < elem_attrs.count; k++) { - LLVMAttributeRef attr = LLVMCreateTypeAttribute(ctx, et_kind, elem_attrs[k].elem); - LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attrs[k].arg_pos + 1), attr); + for (auto const &elem_attr : elem_attrs) { + LLVMAttributeRef attr = LLVMCreateTypeAttribute(ctx, et_kind, elem_attr.elem); + LLVMAddCallSiteAttribute(call, cast(LLVMAttributeIndex)(elem_attr.arg_pos + 1), attr); } // Repackage results in Odin result order Type *pt = base_type(tmpl_entity->type); - isize result_count = (pt->Proc.results != nullptr) ? pt->Proc.results->Tuple.variables.count : 0; + isize result_count = 0; + if (pt->Proc.results != nullptr) { + result_count = pt->Proc.results->Tuple.variables.count; + } if (result_count == 0) { return lbValue{}; // void asm (memory outputs already wrote through their pointers) } // The LLVM return struct is ordered by operand and includes scratch slots; // pull out only the real register outputs and index them by result_index. - auto result_vals = array_make(temporary_allocator(), result_count, result_count); - for (isize i = 0; i < result_count; i++) { - result_vals[i] = nullptr; - } + auto result_vals = slice_make(temporary_allocator(), result_count); for_array(i, *ops) { AsmTemplateEntityDecl const &e = (*ops)[i]; @@ -689,9 +678,11 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { } GB_ASSERT(ret_slot[i] >= 0); - LLVMValueRef v = (ret_types.count == 1) - ? call // single-element return is not a struct - : LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); + LLVMValueRef v = call; + if (ret_types.count != 1) { + // Not a single-element return but a struct + v = LLVMBuildExtractValue(p->builder, call, cast(unsigned)ret_slot[i], ""); + } // A flag output is delivered as i8; coerce it to the declared result type // (e.g. i1, or a wider bool). zext when widening, trunc when narrowing. @@ -723,7 +714,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { // Multiple results -> assemble Odin's result aggregate in result order. Type *results_type = pt->Proc.results; LLVMValueRef agg = LLVMGetUndef(lb_type(m, results_type)); - for (isize i = 0; i < result_count; i++) { + for_array(i, result_vals) { GB_ASSERT(result_vals[i] != nullptr); agg = LLVMBuildInsertValue(p->builder, agg, result_vals[i], cast(unsigned)i, ""); } From b1b08c13c00e4d7dccc22919d8fe099c1f076631 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:20:30 +0100 Subject: [PATCH 78/92] Update clobber table to encode the clobbering for each of the forms --- core/rexcode/isa/x86/mnemonic_builders.odin | 14 - core/rexcode/isa/x86/mnemonics.odin | 2 - core/rexcode/isa/x86/printer.odin | 4 +- .../isa/x86/tablegen/clobber_table.odin | 6076 +++++++++++++---- .../isa/x86/tablegen/encoding_table.odin | 14 +- core/rexcode/isa/x86/tablegen/gen.odin | 105 +- .../x86/tablegen/generated/decode_tables.odin | 128 +- .../x86/tablegen/generated/encode_tables.odin | 3870 ++++++++++- .../isa/x86/tablegen/generated/writer.odin | 2 +- core/rexcode/isa/x86/tables.odin | 10 +- .../isa/x86/tables/x86.clobber_table.bin | Bin 19104 -> 0 bytes .../isa/x86/tables/x86.encode_forms.bin | Bin 38320 -> 38320 bytes .../isa/x86/tables/x86.encode_recipes.bin | Bin 28740 -> 28740 bytes .../isa/x86/tables/x86.encode_runs.bin | Bin 9552 -> 9536 bytes core/rexcode/isa/x86/tables/x86.evex.bin | Bin 8360 -> 8360 bytes core/rexcode/isa/x86/tables/x86.legacy.bin | Bin 25400 -> 25400 bytes core/rexcode/isa/x86/tables/x86.vex.bin | Bin 14140 -> 14140 bytes 17 files changed, 8731 insertions(+), 1494 deletions(-) delete mode 100644 core/rexcode/isa/x86/tables/x86.clobber_table.bin diff --git a/core/rexcode/isa/x86/mnemonic_builders.odin b/core/rexcode/isa/x86/mnemonic_builders.odin index c7b518e03..2957a1264 100644 --- a/core/rexcode/isa/x86/mnemonic_builders.odin +++ b/core/rexcode/isa/x86/mnemonic_builders.odin @@ -2159,12 +2159,6 @@ inst_movss_m32_xmm :: #force_inline proc "contextless" (dst: Me emit_movss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movss_xmm_xmm(dst, src)) } emit_movss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_movss_xmm_m32(dst, src)) } emit_movss_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_movss_m32_xmm(dst, src)) } -inst_movsd_sse_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 733) } -inst_movsd_sse_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 733) } -inst_movsd_sse_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 734) } -emit_movsd_sse_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movsd_sse_xmm_xmm(dst, src)) } -emit_movsd_sse_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movsd_sse_xmm_m64(dst, src)) } -emit_movsd_sse_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movsd_sse_m64_xmm(dst, src)) } inst_movdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 735) } inst_movdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 735) } inst_movdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 736) } @@ -2417,10 +2411,6 @@ inst_cmpss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XM inst_cmpss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 809) } emit_cmpss_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpss_xmm_xmm_imm8(dst, src, imm)) } emit_cmpss_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_cmpss_xmm_m32_imm8(dst, src, imm)) } -inst_cmpsd_sse_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD_SSE, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 810) } -inst_cmpsd_sse_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD_SSE, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 810) } -emit_cmpsd_sse_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpsd_sse_xmm_xmm_imm8(dst, src, imm)) } -emit_cmpsd_sse_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64, imm: i8) { append(instructions, inst_cmpsd_sse_xmm_m64_imm8(dst, src, imm)) } inst_comiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 811) } inst_comiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 811) } emit_comiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_comiss_xmm_xmm(dst, src)) } @@ -8030,8 +8020,6 @@ inst_movupd :: proc{ inst_movupd_xmm_xmm, inst_movu emit_movupd :: proc{ emit_movupd_xmm_xmm, emit_movupd_xmm_m128, emit_movupd_m128_xmm } inst_movss :: proc{ inst_movss_xmm_xmm, inst_movss_xmm_m32, inst_movss_m32_xmm } emit_movss :: proc{ emit_movss_xmm_xmm, emit_movss_xmm_m32, emit_movss_m32_xmm } -inst_movsd_sse :: proc{ inst_movsd_sse_xmm_xmm, inst_movsd_sse_xmm_m64, inst_movsd_sse_m64_xmm } -emit_movsd_sse :: proc{ emit_movsd_sse_xmm_xmm, emit_movsd_sse_xmm_m64, emit_movsd_sse_m64_xmm } inst_movdqa :: proc{ inst_movdqa_xmm_xmm, inst_movdqa_xmm_m128, inst_movdqa_m128_xmm } emit_movdqa :: proc{ emit_movdqa_xmm_xmm, emit_movdqa_xmm_m128, emit_movdqa_m128_xmm } inst_movdqu :: proc{ inst_movdqu_xmm_xmm, inst_movdqu_xmm_m128, inst_movdqu_m128_xmm } @@ -8150,8 +8138,6 @@ inst_cmppd :: proc{ inst_cmppd_xmm_xmm_imm8, inst_ emit_cmppd :: proc{ emit_cmppd_xmm_xmm_imm8, emit_cmppd_xmm_m128_imm8 } inst_cmpss :: proc{ inst_cmpss_xmm_xmm_imm8, inst_cmpss_xmm_m32_imm8 } emit_cmpss :: proc{ emit_cmpss_xmm_xmm_imm8, emit_cmpss_xmm_m32_imm8 } -inst_cmpsd_sse :: proc{ inst_cmpsd_sse_xmm_xmm_imm8, inst_cmpsd_sse_xmm_m64_imm8 } -emit_cmpsd_sse :: proc{ emit_cmpsd_sse_xmm_xmm_imm8, emit_cmpsd_sse_xmm_m64_imm8 } inst_comiss :: proc{ inst_comiss_xmm_xmm, inst_comiss_xmm_m32 } emit_comiss :: proc{ emit_comiss_xmm_xmm, emit_comiss_xmm_m32 } inst_comisd :: proc{ inst_comisd_xmm_xmm, inst_comisd_xmm_m64 } diff --git a/core/rexcode/isa/x86/mnemonics.odin b/core/rexcode/isa/x86/mnemonics.odin index 7428b208a..e654bcd95 100644 --- a/core/rexcode/isa/x86/mnemonics.odin +++ b/core/rexcode/isa/x86/mnemonics.odin @@ -300,7 +300,6 @@ Mnemonic :: enum u16 { MOVAPD, MOVUPD, MOVSS, - MOVSD_SSE, // distinguish from string MOVSD MOVDQA, MOVDQU, MOVQ, @@ -360,7 +359,6 @@ Mnemonic :: enum u16 { CMPPS, CMPPD, CMPSS, - CMPSD_SSE, COMISS, COMISD, UCOMISS, diff --git a/core/rexcode/isa/x86/printer.odin b/core/rexcode/isa/x86/printer.odin index 687fbf55f..30ea392a9 100644 --- a/core/rexcode/isa/x86/printer.odin +++ b/core/rexcode/isa/x86/printer.odin @@ -51,9 +51,7 @@ Print_Result :: isa.Print_Result mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool) -> string { #partial switch m { - case .INVALID: return "???" - case .MOVSD_SSE: return lowercase ? "movsd" : "MOVSD" - case .CMPSD_SSE: return lowercase ? "cmpsd" : "CMPSD" + case .INVALID: return "???" } if name, ok := reflect.enum_name_from_value(m); ok { return lowercase ? strings.to_lower(name, context.temp_allocator) : name diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index 857b604be..3bc0a9b19 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -1,1275 +1,4867 @@ -// clobber_table.odin -- auxiliary side-effect table for rexcode_x86_tablegen +// clobber_table.odin -- PER-FORM side-effect table for rexcode_x86_tablegen // -// DERIVED, NOT EXTRACTED. The ENCODING_TABLE describes how bytes are laid out -// (opcode, ModRM roles, prefixes, REX). It carries no read/write direction and -// no implicit side effects, so this table cannot be produced from it alone -- -// it is a hand-authored semantics layer sourced from the Intel SDM Vol.2 -// ("Operation" + "Flags Affected") applied per instruction family. +// Type: [Mnemonic][]x86.Clobber (parallel to [Mnemonic][]Encoding) // -// Conventions: -// written / read explicit operand slots (OP0..OP3). rmw = written & read. -// implicit_wr / _rd registers touched that are NOT explicit operands -// (widths follow operand size; e.g. RAX means AL/AX/EAX/RAX). -// flags_wr EFLAGS set to a DEFINED value (a cleared flag counts). -// flags_undef EFLAGS left ARCHITECTURALLY UNDEFINED (must be treated -// as clobbered by a compiler, value not guaranteed). -// flags_rd EFLAGS consumed by the instruction. -// writes_mem/reads_mem memory VALUE touched (explicit mem operand or -// implicit: PUSH/CALL/string ops/gather/scatter/etc). -// side_effects effects that are NOT clobbers but still make the -// instruction non-eliminable and/or non-reorderable -// (fences, serialization, traps, control flow, ...). -// This is what separates MFENCE -- orders memory, -// clobbers nothing -- from a genuine no-op. -// FPU_ST/FPU_SW = x87 stack / status word; MXCSR = SSE control-status; -// VECTOR = the whole SIMD register file (VZEROALL/VZEROUPPER). +// HOW EACH FORM IS SPECIALISED FROM THE UNION: +// 1. Implicit-operand normalisation. An operand that is an implicit register +// (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, +// ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from the +// OP0..OP3 slot set and, if that slot was written/read, folded into +// implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an +// operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) +// are inherent and kept on every form. +// 2. Slot trimming. OP slots that are .NONE in a given form are dropped from +// written/read. +// 3. Per-form memory. writes_mem/reads_mem keep the union's DIRECTION but are +// asserted on a form only when that form actually carries a memory-capable +// operand, OR the instruction addresses memory implicitly (stack, string, +// XLAT table, MASKMOVDQU/[rDI] store, VMCS, shadow stack). Consequently +// register-only forms of otherwise-memory instructions (e.g. MOV r,imm; +// FADD ST(0),ST(i); FST ST(i); MOVLHPS; PEXTRW r32,xmm) no longer carry the +// blanket memory flag the union used. +// 4. Family splits that the union could only approximate: +// IMUL -- 1-operand form writes RDX:RAX implicitly (r/m8 -> AX only); +// 2-operand form is OP0 *= OP1; 3-operand form is OP0 = OP1 * imm +// (OP0 not read); neither multi-operand form touches RAX/RDX. +// MUL/DIV/IDIV -- the r/m8 form uses the A-register only and does not +// touch (R)DX. +// SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD -- only the CL form reads RCX; +// the 1/imm8 forms do not. +// Flags and side_effects are uniform across a mnemonic's forms and are carried +// through unchanged. // -// INVARIANT: an instruction is a pure, freely-eliminable no-op iff every -// clobber set is empty AND side_effects == {}. In this table only .NOP -// (and the .INVALID sentinel) satisfy that. +// INVARIANT preserved: a form is a freely-eliminable no-op iff every clobber set +// is empty AND side_effects == {} (only .NOP and the .INVALID sentinel qualify). package rexcode_x86_tablegen import "core:rexcode/isa/x86" @(rodata) -CLOBBER_TABLE := [Mnemonic]x86.Clobber{ +CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .INVALID = {}, - // ---- 8.1 Data Transfer Encodings ---- - .MOV = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - .MOVABS = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - .MOVZX = {written={.OP0}, read={.OP1}, reads_mem=true}, - .MOVSX = {written={.OP0}, read={.OP1}, reads_mem=true}, - .MOVSXD = {written={.OP0}, read={.OP1}, reads_mem=true}, - .XCHG = {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, // asserts LOCK when a mem operand is used - .PUSH = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - .POP = {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - .LEA = {written={.OP0}}, // no memory access: computes effective address only - // ---- 8.2 Arithmetic Encodings ---- - .ADD = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .ADC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .SUB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .SBB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .MUL = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // RAX/RDX widths follow operand size (r/m8 -> AX only) - .IMUL = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit - .DIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only - .IDIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only - .INC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected - .DEC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected - .NEG = {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .CMP = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // no operand written; flags only + // 8.1 Data Transfer Encodings + .MOV = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVABS = { + {written={.OP0}, read={.OP1}}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + }, + .MOVZX = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSX = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSXD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XCHG = { // asserts LOCK when a mem operand is used + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + }, + .PUSH = { + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + }, + .POP = { + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + }, + .LEA = { // no memory access: computes effective address only + {written={.OP0}}, + {written={.OP0}}, + {written={.OP0}}, + }, - // ---- 8.3 Logical Encodings ---- - .AND = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .OR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .XOR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .NOT = {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - .TEST = {read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, reads_mem=true}, // no operand written; flags only + // 8.2 Arithmetic Encodings + .ADD = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .ADC = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .SUB = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .SBB = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .MUL = { // RAX/RDX widths follow operand size (r/m8 -> AX only) + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + }, + .IMUL = { // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + }, + .DIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .IDIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .INC = { // CF deliberately NOT affected + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .DEC = { // CF deliberately NOT affected + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .NEG = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .CMP = { // no operand written; flags only + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, - // ---- 8.4 Shift/Rotate Encodings ---- - .SHL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .SHR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .SAR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .ROL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged - .ROR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged - .RCL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .RCR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .SHLD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, - .SHRD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, + // 8.3 Logical Encodings + .AND = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .OR = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .XOR = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .NOT = { + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + }, + .TEST = { // no operand written; flags only + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + }, - // ---- 8.5 Bit Operation Encodings ---- - .BT = {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF unaffected - .BTS = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BTR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BTC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BSF = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 - .BSR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 - .POPCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // ZF per source; CF/OF/SF/AF/PF cleared - .LZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, - .TZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, + // 8.4 Shift/Rotate Encodings + .SHL = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .SHR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .SAR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .ROL = { // only CF/OF affected; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + }, + .ROR = { // only CF/OF affected; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + }, + .RCL = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .RCR = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .SHLD = { + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + }, + .SHRD = { + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.6 Control Flow Encodings ---- - .JMP = {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, // indirect forms read reg/mem; writes RIP - .JA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JPE = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JPO = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads CX - .JECXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads ECX - .JRCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads RCX - .LOOP = {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, - .LOOPE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - .LOOPNE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - .CALL = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, // pushes return address - .RET = {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, // pops return address (+imm16 form adjusts RSP) - .IRET = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .IRETD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .IRETQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .INT = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate - .INT3 = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate - .INTO = {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.OF, .CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // #OF only if OF=1 - .SYSCALL = {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK - .SYSRET = {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // RIP<-RCX, RFLAGS<-R11 - .SYSENTER = {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, // privileged; RSP/RIP from MSRs - .SYSEXIT = {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX + // 8.5 Bit Operation Encodings + .BT = { // ZF unaffected + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .BTS = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BTR = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BTC = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BSF = { // destination undefined when source == 0 + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .BSR = { // destination undefined when source == 0 + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .POPCNT = { // ZF per source; CF/OF/SF/AF/PF cleared + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .LZCNT = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .TZCNT = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, - // ---- 8.7 Conditional Set/Move Encodings ---- - .SETA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETNAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETNC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETNG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETNL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETNLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, - .SETNP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETNS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, - .SETNZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, - .SETP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETPE = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETPO = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, - .SETZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .CMOVA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVNS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 - .CMOVNZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 - .CMOVP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVPE = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVPO = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 - .CMOVZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + // 8.6 Control Flow Encodings + .JMP = { // indirect forms read reg/mem; writes RIP + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + }, + .JA = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JAE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JB = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JBE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JC = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JZ = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JG = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JGE = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JL = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JLE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNA = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JNAE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNB = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNBE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JNC = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JNZ = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JNG = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNGE = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JNL = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JNLE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNO = { // reads flags; writes RIP on taken branch + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + }, + .JNP = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JNS = { // reads flags; writes RIP on taken branch + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + }, + .JO = { // reads flags; writes RIP on taken branch + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + }, + .JP = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JPE = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JPO = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JS = { // reads flags; writes RIP on taken branch + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + }, + .JCXZ = { // reads CX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .JECXZ = { // reads ECX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .JRCXZ = { // reads RCX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .LOOP = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .LOOPE = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .LOOPNE = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .CALL = { // pushes return address + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + }, + .RET = { // pops return address (+imm16 form adjusts RSP) + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + }, + .IRET = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .IRETD = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .IRETQ = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .INT = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate + {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .INT3 = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .INTO = { // #OF only if OF=1 + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSCALL = { // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK + {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSRET = { // RIP<-RCX, RFLAGS<-R11 + {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + }, + .SYSENTER = { // privileged; RSP/RIP from MSRs + {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSEXIT = { // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX + {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + }, - // ---- 8.8 String Operation Encodings ---- - .MOVS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCAS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODS = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSB = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSW = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSD = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSQ = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + // 8.7 Conditional Set/Move Encodings + .SETA = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETAE = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETB = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETBE = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETC = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETE = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETG = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETGE = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETL = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETLE = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNA = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETNAE = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNB = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNBE = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETNC = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNE = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETNG = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNGE = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETNL = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETNLE = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNO = { + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + }, + .SETNP = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETNS = { + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + }, + .SETNZ = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETO = { + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + }, + .SETP = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETPE = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETPO = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETS = { + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + }, + .SETZ = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .CMOVA = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVAE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVB = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVBE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVC = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVG = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVGE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVL = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVLE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNA = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVNAE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNB = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNBE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVNC = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVNG = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNGE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVNL = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVNLE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + }, + .CMOVNP = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVNS = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + }, + .CMOVNZ = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + }, + .CMOVP = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVPE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVPO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVS = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + }, + .CMOVZ = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, - // ---- 8.9 Flag Operation Encodings ---- - .CLC = {flags_wr={.CF}}, - .STC = {flags_wr={.CF}}, - .CMC = {flags_wr={.CF}, flags_rd={.CF}}, - .CLD = {flags_wr={.DF}}, - .STD = {flags_wr={.DF}}, - .CLI = {flags_wr={.IF}}, - .STI = {flags_wr={.IF}}, - .LAHF = {implicit_wr={.RAX}, flags_rd={.SF, .ZF, .AF, .PF, .CF}}, // AH <- flags - .SAHF = {implicit_rd={.RAX}, flags_wr={.SF, .ZF, .AF, .PF, .CF}}, // flags <- AH - .PUSHF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .PUSHFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .PUSHFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .POPF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - .POPFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - .POPFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // 8.8 String Operation Encodings + .MOVS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // SSE variants + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .CMPS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCAS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .LODS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .STOS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.10 Miscellaneous Encodings ---- - .NOP = {}, // no register/flag/memory clobber - .HLT = {side_effects={.HALT, .PRIVILEGED}}, // no register/flag/memory clobber - .WAIT = {implicit_rd={.FPU_SW}}, // waits on pending x87 exception - .LOCK = {side_effects={.FENCE}}, // no register/flag/memory clobber - .UD0 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .UD1 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .UD2 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .CPUID = {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, - .RDTSC = {implicit_wr={.RAX, .RDX}}, - .RDTSCP = {implicit_wr={.RAX, .RDX, .RCX}}, - .RDPMC = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - .XGETBV = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - .XSETBV = {implicit_rd={.RCX, .RDX, .RAX}}, // privileged; writes XCR[ECX] - .CBW = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CWDE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CDQE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CWD = {implicit_wr={.RDX}, implicit_rd={.RAX}}, - .CDQ = {implicit_wr={.RDX}, implicit_rd={.RAX}}, - .CQO = {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // 8.9 Flag Operation Encodings + .CLC = { + {flags_wr={.CF}}, + }, + .STC = { + {flags_wr={.CF}}, + }, + .CMC = { + {flags_wr={.CF}, flags_rd={.CF}}, + }, + .CLD = { + {flags_wr={.DF}}, + }, + .STD = { + {flags_wr={.DF}}, + }, + .CLI = { + {flags_wr={.IF}}, + }, + .STI = { + {flags_wr={.IF}}, + }, + .LAHF = { // AH <- flags + {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}, + }, + .SAHF = { // flags <- AH + {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}, + }, + .PUSHF = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .PUSHFD = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .PUSHFQ = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .POPF = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, + .POPFD = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, + .POPFQ = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, - // ---- 8.11 BMI/ADX Encodings ---- - .ANDN = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.SF, .ZF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BEXTR = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .CF, .OF}, flags_undef={.SF, .AF, .PF}, reads_mem=true}, - .BLSI = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BLSMSK = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BLSR = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BZHI = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .SF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .PDEP = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected - .PEXT = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected - .RORX = {written={.OP0}, read={.OP1}, reads_mem=true}, // no flags affected - .SARX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .SHLX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .SHRX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .MULX = {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, // no flags affected; implicit multiplicand in rDX - .ADCX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, // only CF (chains with ADCX) - .ADOX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, // only OF (chains with ADOX) + // 8.10 Miscellaneous Encodings + .NOP = { // no register/flag/memory clobber + {}, + {}, + {}, + {}, + }, + .HLT = { // no register/flag/memory clobber + {side_effects={.HALT, .PRIVILEGED}}, + }, + .WAIT = { // waits on pending x87 exception + {implicit_rd={.FPU_SW}}, + }, + .LOCK = { // no register/flag/memory clobber + {side_effects={.FENCE}}, + }, + .UD0 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .UD1 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .UD2 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .CPUID = { + {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + }, + .RDTSC = { + {implicit_wr={.RAX, .RDX}}, + }, + .RDTSCP = { + {implicit_wr={.RAX, .RCX, .RDX}}, + }, + .RDPMC = { + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + }, + .XGETBV = { + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + }, + .XSETBV = { // privileged; writes XCR[ECX] + {implicit_rd={.RAX, .RCX, .RDX}}, + }, + .CBW = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CWDE = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CDQE = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CWD = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, + .CDQ = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, + .CQO = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, - // ---- 8.12 SSE Encodings ---- - .MOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR - .MOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR - .MOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .XORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .XORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .COMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .COMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .UCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .UCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .SHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .PADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .POR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR - .PAVGB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PAVGW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] - .LFENCE = {side_effects={.FENCE, .SERIALIZING}}, // ordering/hint; no clobber - .SFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber - .MFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber - .PAUSE = {side_effects={.HINT}}, // ordering/hint; no clobber - .CLFLUSH = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // flushes cache line for the addressed byte - .ADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .LDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .DPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .EXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .INSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .ROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .PCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CRC32 = {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, // accumulates CRC into OP0; no flags - .PCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .PCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .PCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - .PCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - .PCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1NEXTE = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1RNDS4 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256RNDS2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // 8.11 BMI/ADX Encodings + .ANDN = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BEXTR = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + }, + .BLSI = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BLSMSK = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BLSR = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BZHI = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .PDEP = { // no flags affected + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PEXT = { // no flags affected + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .RORX = { // no flags affected + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SARX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHLX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHRX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .MULX = { // no flags affected; implicit multiplicand in rDX + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + }, + .ADCX = { // only CF (chains with ADCX) + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + }, + .ADOX = { // only OF (chains with ADOX) + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + }, - // ---- 8.13 AVX/AVX2 Encodings ---- - .VADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VXORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VXORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VUCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VUCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VSHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VSHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VDPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VEXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VINSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VMOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VMOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VLDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .VPCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .VPCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - .VPCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - .VPBROADCASTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VPADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VPTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VPSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] - .VPCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXTRACTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VINSERTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERM2F128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMASKMOVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMASKMOVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VTESTPS = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VTESTPD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VZEROALL = {implicit_wr={.VECTOR}}, // zeroes the entire vector register file (YMM/ZMM) - .VZEROUPPER = {implicit_wr={.VECTOR}}, // zeroes bits [MAXVL-1:128] of every vector register - .VBROADCASTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXTRACTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VINSERTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERM2I128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMASKMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VPMASKMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VGATHERDPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERDPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERQPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERQPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERDD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERDQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERQD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERQQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + // 8.12 SSE Encodings + .MOVAPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVUPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVAPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVUPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVSS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVDQA = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVDQU = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVHPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVHPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLHPS = { + {written={.OP0}, read={.OP1}}, + }, + .MOVHLPS = { + {written={.OP0}, read={.OP1}}, + }, + .MOVMSKPS = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVMSKPD = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVNTPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTDQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTDQA = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RCPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RCPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ANDPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDNPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDNPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ORPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ORPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XORPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XORPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CMPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .COMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .COMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .UCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .UCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .SHUFPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHUFPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .UNPCKLPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKHPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKLPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKHPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CVTPS2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPD2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSS2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSD2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTDQ2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTDQ2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSI2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSI2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .PADDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDUSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDUSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBUSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBUSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULUDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMADDWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PAND = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PANDN = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .POR = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PXOR = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSLLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSLLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSLLQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRAW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRAD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PCMPEQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPEQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPEQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKSSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKSSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKUSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLQDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHQDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSHUFD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PEXTRW = { // destination may be memory + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .PINSRW = { + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PMOVMSKB = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .PAVGB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PAVGW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSADBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MASKMOVDQU = { // byte-masked store to DS:[rDI] + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + }, + .LFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE, .SERIALIZING}}, + }, + .SFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE}}, + }, + .MFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE}}, + }, + .PAUSE = { // ordering/hint; no clobber + {side_effects={.HINT}}, + }, + .CLFLUSH = { // flushes cache line for the addressed byte + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .ADDSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MOVDDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSLDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSHDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .LDDQU = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSHUFB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMADDUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHRSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGNB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGNW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGND = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PALIGNR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDVPS = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .BLENDVPD = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .PBLENDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PBLENDVB = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .DPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .EXTRACTPS = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .INSERTPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .MPSADBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PACKUSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PEXTRB = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PEXTRD = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PEXTRQ = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PHMINPOSUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PINSRB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PINSRD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PINSRQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PMAXSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PTEST = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .ROUNDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .PCMPEQQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CRC32 = { // accumulates CRC into OP0; no flags + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + }, + .PCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPGTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCLMULQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .AESDEC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESDECLAST = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESENC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESENCLAST = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESIMC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESKEYGENASSIST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHA1MSG1 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1MSG2 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1NEXTE = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1RNDS4 = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHA256MSG1 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA256MSG2 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA256RNDS2 = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, - // ---- 8.14 FMA Encodings ---- - .VFMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPH2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPS2PH = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, // may set MXCSR exception/status bits + // 8.13 AVX/AVX2 Encodings + .VADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VANDPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDNPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDNPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VORPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VORPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VXORPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VXORPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VCMPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VUCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VUCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VSHUFPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VSHUFPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VUNPCKLPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKHPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKLPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKHPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDVPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDVPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VDPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VEXTRACTPS = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VINSERTPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMOVAPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVUPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVAPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVUPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVSS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVSD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVDQA = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVDQU = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVHPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVHPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLHPS = { + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVHLPS = { + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVMSKPS = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVMSKPD = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVNTPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTDQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTDQA = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VADDSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VLDDQU = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVSLDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVSHDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPBROADCASTB = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTW = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTD = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCVTPS2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPD2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSS2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSD2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTDQ2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTDQ2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSI2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSI2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VPADDB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULUDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMADDWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPAND = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPANDN = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPOR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPXOR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSLLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSLLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRAW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRAD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPCMPEQB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKSSWB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKSSDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKUSWB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKUSDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPEXTRB = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRW = { // destination may be memory + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRD = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRQ = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPINSRB = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPMOVMSKB = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPTEST = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VPSHUFB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMADDUBSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHRSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGNB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGNW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGND = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPABSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPABSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPABSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPALIGNR = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPBLENDW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPBLENDVB = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMPSADBW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPHMINPOSUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMAXSB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXSD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXUD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINSB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINSD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINUD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMOVSXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXBQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMULDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VMASKMOVDQU = { // byte-masked store to DS:[rDI] + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + }, + .VPCLMULQDQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VAESDEC = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESDECLAST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESENC = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESENCLAST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESIMC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VAESKEYGENASSIST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBROADCASTSS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VBROADCASTSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .VBROADCASTF128 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXTRACTF128 = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VINSERTF128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERM2F128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMASKMOVPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VMASKMOVPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VTESTPS = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VTESTPD = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VZEROALL = { // zeroes the entire vector register file (YMM/ZMM) + {implicit_wr={.VECTOR}}, + }, + .VZEROUPPER = { // zeroes bits [MAXVL-1:128] of every vector register + {implicit_wr={.VECTOR}}, + }, + .VBROADCASTI128 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXTRACTI128 = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VINSERTI128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERM2I128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERMD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPSLLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRAVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMASKMOVD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VPMASKMOVQ = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VGATHERDPS = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERDPD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERQPS = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERQPD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERDD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERDQ = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERQD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERQQ = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, - // ---- 8.15 AVX-512 Encodings ---- - .VMOVDQA32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQA64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU8 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU16 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCOMPRESSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCOMPRESSQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCOMPRESSPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCOMPRESSPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXPANDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXPANDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXPANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXPANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCONFLICTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCONFLICTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPLZCNTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPLZCNTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVB2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVW2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVD2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVQ2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVM2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSCATTERDD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERDQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERQD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERQQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERDPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERDPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERQPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERQPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSRAVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VRANGEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFPCLASSPS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSPD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSSS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSSD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VALIGNQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VALIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VDBPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPTERNLOGD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPTERNLOGQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULTISHIFTQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .KADDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDND = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KMOVW = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVB = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVQ = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVD = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KNOTW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KSHIFTLW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KUNPCKBW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KUNPCKWD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KUNPCKDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + // 8.14 FMA Encodings + .VFMADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPH2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPS2PH = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.16 x87 FPU Encodings ---- - .FADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FADDP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FIADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FISUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FISUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FMULP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FIMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FIDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FIDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSQRT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FABS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FCHS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPREM = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPREM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FRNDINT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSCALE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FXTRACT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FXAM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FILD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FBLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FIST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FISTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FISTTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FBSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FXCH = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FCMOVB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS - .FCMOVE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS - .FCMOVNB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS - .FCMOVNE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVNBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVNU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS - .FCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FICOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FICOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FUCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FUCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FTST = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FLDZ = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLD1 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDPI = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDL2T = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDL2E = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDLG2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDLN2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FSIN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FSINCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FPTAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPATAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .F2XM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FYL2X = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FYL2XP1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FNINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FINCSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDECSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FFREE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FFREEP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FNOP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FWAIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FNCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FLDCW = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FLDENV = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory - .FNSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory - .FXSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FXSAVE64 = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FXRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FXRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + // 8.15 AVX-512 Encodings + .VMOVDQA32 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQA64 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU8 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU16 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU32 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU64 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBLENDMB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDMPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDMPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCOMPRESSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCOMPRESSQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCOMPRESSPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCOMPRESSPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPEXPANDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPEXPANDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXPANDPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXPANDPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCONFLICTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCONFLICTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPLZCNTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPLZCNTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPERMI2B = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2W = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2D = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2Q = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2PS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2PD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2B = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2W = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2D = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2Q = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2PS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2PD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMOVB2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVW2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVD2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVQ2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2B = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2W = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2D = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2Q = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPROLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSCATTERDD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERDQ = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERQD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERQQ = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERDPS = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERDPD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERQPS = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERQPD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSRAVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRAVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VRANGEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFPCLASSPS = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSPD = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSSS = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSSD = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VALIGNQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VALIGND = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VDBPSADBW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPTERNLOGD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPTERNLOGQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPMULTISHIFTQB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .KADDW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDND = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KMOVW = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVB = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVQ = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVD = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KNOTW = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTB = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTQ = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTD = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORTESTW = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTB = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTQ = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTD = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KSHIFTLW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KTESTW = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTB = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTQ = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTD = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KUNPCKBW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KUNPCKWD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KUNPCKDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, - // ---- 8.17 System Instruction Encodings ---- - .LGDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SGDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LIDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SIDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LLDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SLDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LTR = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .STR = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LMSW = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SMSW = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .CLTS = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .ARPL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // legacy; adjusts RPL, sets ZF - .LAR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure - .LSL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure - .VERR = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable - .VERW = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable - .INVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .WBINVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVLPG = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVPCID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .RSM = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .RDMSR = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, // privileged; EDX:EAX <- MSR[ECX] - .WRMSR = {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; MSR[ECX] <- EDX:EAX - .VMCALL = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .VMLAUNCH = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMRESUME = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMXOFF = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .VMXON = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMCLEAR = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMPTRLD = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMPTRST = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMREAD = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF - .VMWRITE = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF - .VMFUNC = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVEPT = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .INVVPID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + // 8.16 x87 FPU Encodings + .FADD = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FADDP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIADD = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSUB = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSUBP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FISUB = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSUBR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSUBRP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FISUBR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FMUL = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FMULP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIMUL = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FDIV = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDIVP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIDIV = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FDIVR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDIVRP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIDIVR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSQRT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FABS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCHS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPREM = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPREM1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FRNDINT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSCALE = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FXTRACT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FXAM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FLD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FILD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FBLD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FST = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FSTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FIST = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FISTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FISTTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FBSTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXCH = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCMOVB = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + }, + .FCMOVE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + }, + .FCMOVBE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + }, + .FCMOVU = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + }, + .FCMOVNB = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + }, + .FCMOVNE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + }, + .FCMOVNBE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + }, + .FCMOVNU = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + }, + .FCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FICOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FICOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FCOMI = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FCOMIP = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOMI = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOMIP = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FUCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FUCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FTST = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FLDZ = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLD1 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDPI = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDL2T = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDL2E = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDLG2 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDLN2 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FSIN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSINCOS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPTAN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPATAN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .F2XM1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FYL2X = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FYL2XP1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FINIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNINIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FINCSTP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDECSTP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FFREE = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FFREEP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNOP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FWAIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCLEX = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNCLEX = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSTCW = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSTCW = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FLDCW = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSTENV = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSTENV = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FLDENV = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FRSTOR = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSTSW = { // AX form writes AX; m2byte form writes memory + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + }, + .FNSTSW = { // AX form writes AX; m2byte form writes memory + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + }, + .FXSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXSAVE64 = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXRSTOR = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FXRSTOR64 = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, - // ---- 8.18 Security and Memory Protection Encodings ---- - .ENCLS = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .ENCLU = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .ENCLV = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .RDPKRU = {implicit_wr={.RAX}, implicit_rd={.RCX}}, // EAX <- PKRU (EDX cleared); reads ECX - .WRPKRU = {implicit_rd={.RAX, .RCX, .RDX}}, // PKRU <- EAX; ECX/EDX must be 0 - .INCSSPD = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP - .INCSSPQ = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP - .RDSSPD = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 - .RDSSPQ = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 - .SAVEPREVSSP = {side_effects={.CET}}, // CET shadow-stack management - .RSTORSSP = {side_effects={.CET}}, // CET shadow-stack management - .WRSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRUSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRUSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .SETSSBSY = {side_effects={.CET}}, // CET shadow-stack management - .CLRSSBSY = {side_effects={.CET}}, // CET shadow-stack management - .ENDBR64 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like - .ENDBR32 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like + // 8.17 System Instruction Encodings + .LGDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SGDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + }, + .LIDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SIDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + }, + .LLDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SLDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .LTR = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .STR = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .LMSW = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SMSW = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .CLTS = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .ARPL = { // legacy; adjusts RPL, sets ZF + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .LAR = { // ZF=1 on success; OP0 undefined on failure + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + }, + .LSL = { // ZF=1 on success; OP0 undefined on failure + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + }, + .VERR = { // ZF=1 if segment is readable/writable + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + }, + .VERW = { // ZF=1 if segment is readable/writable + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + }, + .INVD = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .WBINVD = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .INVLPG = { // privileged; no GPR/EFLAGS clobber modeled + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .INVPCID = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .RSM = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .RDMSR = { // privileged; EDX:EAX <- MSR[ECX] + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, + }, + .WRMSR = { // privileged; MSR[ECX] <- EDX:EAX + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .VMCALL = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .VMLAUNCH = { // VMX/INVx status reported in ZF/CF + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMRESUME = { // VMX/INVx status reported in ZF/CF + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMXOFF = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .VMXON = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMCLEAR = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMPTRLD = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMPTRST = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMREAD = { // VMX status in ZF/CF + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMWRITE = { // VMX status in ZF/CF + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMFUNC = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .INVEPT = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .INVVPID = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, - // ---- 8.19 XSAVE/XRSTOR State Management Encodings ---- - .XSAVE = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVE64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XRSTOR = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX - .XRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX - .XSAVEOPT = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEOPT64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEC = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEC64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVES = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX - .XSAVES64 = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX - .XRSTORS = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX - .XRSTORS64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX + // 8.18 Security and Memory Protection Encodings + .ENCLS = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .ENCLU = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .ENCLV = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .RDPKRU = { // EAX <- PKRU (EDX cleared); reads ECX + {implicit_wr={.RAX}, implicit_rd={.RCX}}, + }, + .WRPKRU = { // PKRU <- EAX; ECX/EDX must be 0 + {implicit_rd={.RAX, .RCX, .RDX}}, + }, + .INCSSPD = { // advances SSP + {read={.OP0}, side_effects={.CET}}, + }, + .INCSSPQ = { // advances SSP + {read={.OP0}, side_effects={.CET}}, + }, + .RDSSPD = { // reads shadow-stack pointer into OP0 + {written={.OP0}, side_effects={.CET}}, + }, + .RDSSPQ = { // reads shadow-stack pointer into OP0 + {written={.OP0}, side_effects={.CET}}, + }, + .SAVEPREVSSP = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .RSTORSSP = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .WRSSD = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRSSQ = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRUSSD = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRUSSQ = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .SETSSBSY = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .CLRSSBSY = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .ENDBR64 = { // CET landing pad; NOP-like + {side_effects={.HINT, .CET}}, + }, + .ENDBR32 = { // CET landing pad; NOP-like + {side_effects={.HINT, .CET}}, + }, - // ---- 8.20 Cache and Prefetch Encodings ---- - .PREFETCHT0 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHT1 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHT2 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHNTA = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHW = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .CLFLUSHOPT = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber - .CLWB = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber - .CLDEMOTE = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + // 8.19 XSAVE/XRSTOR State Management Encodings + .XSAVE = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVE64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XRSTOR = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + }, + .XRSTOR64 = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + }, + .XSAVEOPT = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEOPT64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEC = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEC64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVES = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .XSAVES64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .XRSTORS = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .XRSTORS64 = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, - // ---- 8.21 Atomic and Byte Swap Encodings ---- - .BSWAP = {written={.OP0}, read={.OP0}}, - .CMPXCHG = {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // ZF set on match; on mismatch RAX <- dest - .CMPXCHG8B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - .CMPXCHG16B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - .XADD = {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // 8.20 Cache and Prefetch Encodings + .PREFETCHT0 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHT1 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHT2 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHNTA = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHW = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .CLFLUSHOPT = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .CLWB = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .CLDEMOTE = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, - // ---- 8.22 Miscellaneous Encodings ---- - .BOUND = {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, // #BR if out of bounds - .ENTER = {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, // builds stack frame - .LEAVE = {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, - .XLAT = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] - .XLATB = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] - .MOVBE = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // byte-swapping load/store - .RDRAND = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - .RDSEED = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + // 8.21 Atomic and Byte Swap Encodings + .BSWAP = { + {written={.OP0}, read={.OP0}}, + {written={.OP0}, read={.OP0}}, + }, + .CMPXCHG = { // ZF set on match; on mismatch RAX <- dest + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .CMPXCHG8B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .CMPXCHG16B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .XADD = { + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + + // 8.22 Miscellaneous Encodings + .BOUND = { // #BR if out of bounds + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + }, + .ENTER = { // builds stack frame + {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, + }, + .LEAVE = { + {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, + }, + .XLAT = { // AL <- [rBX + AL] + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + }, + .XLATB = { // AL <- [rBX + AL] + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + }, + .MOVBE = { // byte-swapping load/store + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .RDRAND = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .RDSEED = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, } diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index 9793858ee..9fc398807 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -12,7 +12,7 @@ package rexcode_x86_tablegen // Operand_Type list satisfies the user's Instruction operands. @(rodata) -ENCODING_TABLE: [Mnemonic][]Encoding = { +ENCODING_TABLE := [Mnemonic][]Encoding{ .INVALID = {}, // ------------------------------------------------------------------------- @@ -1000,6 +1000,8 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { }, .MOVSD = { {.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, + {.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, + {.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, }, .MOVSQ = { {.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true, force_rex_w=true}}, @@ -1014,7 +1016,8 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, opsize_16=true}}, }, .CMPSD = { - {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, }, .CMPSQ = { {.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, force_rex_w=true}}, @@ -1265,10 +1268,6 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3}}, {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3}}, }, - .MOVSD_SSE = { - {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, - }, .MOVDQA = { {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66}}, {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66}}, @@ -1462,9 +1461,6 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { .CMPSS = { {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3}}, }, - .CMPSD_SSE = { - {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, - }, .COMISS = { {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F}}, }, diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index fbd0af645..10225cd7d 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -34,6 +34,7 @@ import lib "../" // `Mnemonic`/`Encoding` unqualified — its body stays byte-for-byte unedited. Encoding :: lib.Encoding Mnemonic :: lib.Mnemonic +Clobber :: lib.Clobber PREFIX_66 :: lib.PREFIX_66 PREFIX_F3 :: lib.PREFIX_F3 PREFIX_F2 :: lib.PREFIX_F2 @@ -47,22 +48,22 @@ BLOBS := [?]Blob{ {"ENCODE_FORMS", "x86.encode_forms.bin", "Encoding"}, {"ENCODE_RUNS", "x86.encode_runs.bin", "Encode_Run"}, {"ENCODE_RECIPES", "x86.encode_recipes.bin", "Form_Recipe"}, - {"MODRM_TABLE", "x86.modrm.bin", "ModRM_Info"}, - {"SIB_TABLE", "x86.sib.bin", "SIB_Info"}, - {"LEGACY_DECODE_ENTRIES", "x86.legacy.bin", "Decode_Entry"}, - {"VEX_DECODE_ENTRIES", "x86.vex.bin", "VEX_Decode_Entry"}, - {"EVEX_DECODE_ENTRIES", "x86.evex.bin", "VEX_Decode_Entry"}, - {"DECODE_INDEX_LEGACY", "x86.idx_legacy.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F", "x86.idx_0f.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F38", "x86.idx_0f38.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F3A", "x86.idx_0f3a.bin", "Decode_Index"}, - {"VEX_INDEX_0F", "x86.vex_idx_0f.bin", "Decode_Index"}, - {"VEX_INDEX_0F38", "x86.vex_idx_0f38.bin", "Decode_Index"}, - {"VEX_INDEX_0F3A", "x86.vex_idx_0f3a.bin", "Decode_Index"}, - {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, - {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin","Decode_Index"}, - {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin","Decode_Index"}, - {"CLOBBER_TABLE", "x86.clobber_table.bin","Clobber"}, + {"MODRM_TABLE", "x86.modrm.bin", "ModRM_Info"}, + {"SIB_TABLE", "x86.sib.bin", "SIB_Info"}, + {"LEGACY_DECODE_ENTRIES", "x86.legacy.bin", "Decode_Entry"}, + {"VEX_DECODE_ENTRIES", "x86.vex.bin", "VEX_Decode_Entry"}, + {"EVEX_DECODE_ENTRIES", "x86.evex.bin", "VEX_Decode_Entry"}, + {"DECODE_INDEX_LEGACY", "x86.idx_legacy.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F", "x86.idx_0f.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F38", "x86.idx_0f38.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F3A", "x86.idx_0f3a.bin", "Decode_Index"}, + {"VEX_INDEX_0F", "x86.vex_idx_0f.bin", "Decode_Index"}, + {"VEX_INDEX_0F38", "x86.vex_idx_0f38.bin", "Decode_Index"}, + {"VEX_INDEX_0F3A", "x86.vex_idx_0f3a.bin", "Decode_Index"}, + {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, + {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin", "Decode_Index"}, + {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin", "Decode_Index"}, + {"CLOBBER_FORMS", "x86.clobber_forms.bin", "Clobber"}, } DIR_GEN :: #directory + "/generated/" @@ -110,6 +111,17 @@ emit_encode_tables :: proc() { } strings.write_string(&sb, "}\n\n") + strings.write_string(&sb, "@(rodata)\n") + fmt.sbprintfln(&sb, "CLOBBER_FORMS := [%d]lib.Clobber{{", total_forms()) + for m in Mnemonic { + forms := CLOBBER_TABLE[m] + assert(len(forms) == len(ENCODING_TABLE[m])) + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { write_clobber(&sb, f, max_name) } + } + strings.write_string(&sb, "}\n\n") + // Run index, one entry per mnemonic (dense, enum-ordinal order). run_name := 0 for m in Mnemonic { run_name = max(run_name, len(reflect.enum_string(m))) } @@ -153,6 +165,59 @@ write_encoding :: proc(sb: ^strings.Builder, e: lib.Encoding, max_name: int) { strings.write_string(sb, "},\n") } +write_clobber :: proc(sb: ^strings.Builder, c: lib.Clobber, max_name: int) { + i := 0 + sep :: proc(sb: ^strings.Builder, i: ^int) { + if i^ > 0 { strings.write_string(sb, ", ") } + i^ += 1 + } + write_flags :: proc(sb: ^strings.Builder, name: string, flags: $T) { + strings.write_string(sb, name) + strings.write_string(sb, "={") + i := 0 + for flag in flags { + if i > 0 { strings.write_string(sb, ", ") } + fmt.sbprintf(sb, ".%s", flag) + i += 1 + } + strings.write_string(sb, "}") + } + + strings.write_string(sb, "\t{") + if c.written != nil { + sep(sb, &i); write_flags(sb, "written", c.written) + } + if c.read != nil { + sep(sb, &i); write_flags(sb, "read", c.read) + } + if c.implicit_wr != nil { + sep(sb, &i); write_flags(sb, "implicit_wr", c.implicit_wr) + } + if c.implicit_rd != nil { + sep(sb, &i); write_flags(sb, "implicit_rd", c.implicit_rd) + } + if c.flags_wr != nil { + sep(sb, &i); write_flags(sb, "flags_wr", c.flags_wr) + } + if c.flags_undef != nil { + sep(sb, &i); write_flags(sb, "flags_undef", c.flags_undef) + } + if c.flags_rd != nil { + sep(sb, &i); write_flags(sb, "flags_rd", c.flags_rd) + } + if c.writes_mem { + sep(sb, &i); strings.write_string(sb, "writes_mem=true") + } + if c.reads_mem { + sep(sb, &i); strings.write_string(sb, "reads_mem=true") + } + if c.side_effects != nil { + sep(sb, &i); write_flags(sb, "side_effects", c.side_effects) + } + + strings.write_string(sb, "},\n") +} + // ----------------------------------------------------------------------------- // Decode side // ----------------------------------------------------------------------------- @@ -548,6 +613,14 @@ encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { return ENCODE_FORMS[r.start:][:r.count] } +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +clobber_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Clobber { + r := ENCODE_RUNS[u16(m)] + return CLOBBER_FORMS[r.start:][:r.count] +} + // Flat [prefix][opcode] lookup into a logical [4][256] index table. @(private, require_results) didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 6821eb95a..5d4939325 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -146,57 +146,57 @@ SIB_TABLE := [256]lib.SIB_Info{ @(rodata) LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -206,21 +206,21 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -231,18 +231,18 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -255,25 +255,25 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -282,16 +282,16 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -303,9 +303,9 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -313,17 +313,17 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -336,8 +336,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -373,24 +373,24 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, + {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, @@ -409,35 +409,35 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, - {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, @@ -451,11 +451,11 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -483,8 +483,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -599,8 +599,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFC, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFD, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFE, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -650,8 +650,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0xC0, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD0, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD8, .FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -760,8 +760,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -775,11 +775,11 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0xC0, .ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -795,12 +795,12 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0xEE, .RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xEF, .WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xF9, .RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -823,8 +823,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -931,8 +931,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x52, 0xFF, .RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x53, 0xFF, .RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1133,8 +1133,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 1, 0x2B, 0xFF, .MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2E, 0xFF, .UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2F, 0xFF, .COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x51, 0xFF, .SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x54, 0xFF, .ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x55, 0xFF, .ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1285,8 +1285,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x10, 0xFF, .MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x11, 0xFF, .MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x10, 0xFF, .MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x11, 0xFF, .MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1305,7 +1305,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0xC2, 0xFF, .CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, + {._0F, 3, 0xC2, 0xFF, .CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0xF0, 0xFF, .LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1380,8 +1380,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index fa4a01692..74eda1187 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -800,6 +800,8 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {opsize_16=true, rep_ok=true}}, // .MOVSD {.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, + {.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVSQ {.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {force_rex_w=true, rep_ok=true}}, // .CMPS @@ -810,6 +812,7 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {opsize_16=true, rep_ok=true}}, // .CMPSD {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .CMPSQ {.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {force_rex_w=true, rep_ok=true}}, // .SCAS @@ -973,9 +976,6 @@ ENCODE_FORMS := [2395]lib.Encoding{ // .MOVSS {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2, explicit_count=2}}, {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2, explicit_count=2}}, - // .MOVSD_SSE - {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, explicit_count=2}}, - {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVDQA {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, explicit_count=2}}, {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, explicit_count=2}}, @@ -1110,8 +1110,6 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .CMPSS {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=2, explicit_count=3}}, - // .CMPSD_SSE - {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .COMISS {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, explicit_count=2}}, // .COMISD @@ -3599,6 +3597,3596 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, } +@(rodata) +CLOBBER_FORMS := [2395]lib.Clobber{ + // .MOV + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVABS + {written={.OP0}, read={.OP1}}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + // .MOVZX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSXD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XCHG + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + // .PUSH + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + // .POP + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + // .LEA + {written={.OP0}}, + {written={.OP0}}, + {written={.OP0}}, + // .ADD + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .ADC + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .SUB + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .SBB + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .MUL + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + // .IMUL + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + // .DIV + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .IDIV + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .INC + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .DEC + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .NEG + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .CMP + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .AND + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .OR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .XOR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .NOT + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + // .TEST + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + // .SHL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .SHR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .SAR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .ROL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + // .ROR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + // .RCL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .RCR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .SHLD + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + // .SHRD + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + // .BT + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .BTS + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BTR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BTC + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BSF + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + // .BSR + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + // .POPCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .LZCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .TZCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .JMP + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + // .JA + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JAE + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JB + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JBE + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JC + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JE + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JZ + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JG + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JGE + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JL + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JLE + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNA + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JNAE + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNB + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNBE + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JNC + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNE + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JNZ + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JNG + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNGE + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JNL + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JNLE + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNO + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + // .JNP + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JNS + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + // .JO + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + // .JP + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JPE + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JPO + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JS + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + // .JCXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .JECXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .JRCXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .LOOP + {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .LOOPE + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + // .LOOPNE + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + // .CALL + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + // .RET + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + // .IRET + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .IRETD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .IRETQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .INT + {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .INT3 + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .INTO + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSCALL + {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSRET + {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + // .SYSENTER + {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSEXIT + {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + // .SETA + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETAE + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETB + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETBE + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETC + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETE + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETG + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETGE + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETL + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETLE + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNA + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETNAE + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNB + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNBE + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETNC + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNE + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETNG + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNGE + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETNL + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETNLE + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNO + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + // .SETNP + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETNS + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + // .SETNZ + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETO + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + // .SETP + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETPE + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETPO + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETS + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + // .SETZ + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .CMOVA + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVAE + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVB + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVBE + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVC + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVE + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVG + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVGE + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVL + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVLE + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNA + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVNAE + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNB + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNBE + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVNC + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNE + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVNG + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNGE + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVNL + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVNLE + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNO + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + // .CMOVNP + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVNS + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + // .CMOVNZ + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVO + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + // .CMOVP + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVPE + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVPO + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVS + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + // .CMOVZ + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .MOVS + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSB + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSW + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSD + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVSQ + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .CMPS + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSB + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSW + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSD + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPSQ + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCAS + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASB + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASW + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASD + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASQ + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .LODS + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSB + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSW + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSD + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSQ + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .STOS + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSB + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSW + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSD + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSQ + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .CLC + {flags_wr={.CF}}, + // .STC + {flags_wr={.CF}}, + // .CMC + {flags_wr={.CF}, flags_rd={.CF}}, + // .CLD + {flags_wr={.DF}}, + // .STD + {flags_wr={.DF}}, + // .CLI + {flags_wr={.IF}}, + // .STI + {flags_wr={.IF}}, + // .LAHF + {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}, + // .SAHF + {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}, + // .PUSHF + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .PUSHFD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .PUSHFQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .POPF + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .POPFD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .POPFQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .NOP + {}, + {}, + {}, + {}, + // .HLT + {side_effects={.HALT, .PRIVILEGED}}, + // .WAIT + {implicit_rd={.FPU_SW}}, + // .LOCK + {side_effects={.FENCE}}, + // .UD0 + {side_effects={.TRAP}}, + // .UD1 + {side_effects={.TRAP}}, + // .UD2 + {side_effects={.TRAP}}, + // .CPUID + {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + // .RDTSC + {implicit_wr={.RAX, .RDX}}, + // .RDTSCP + {implicit_wr={.RAX, .RCX, .RDX}}, + // .RDPMC + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + // .XGETBV + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + // .XSETBV + {implicit_rd={.RAX, .RCX, .RDX}}, + // .CBW + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CWDE + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CDQE + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CWD + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .CDQ + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .CQO + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .ANDN + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BEXTR + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + // .BLSI + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BLSMSK + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BLSR + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BZHI + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .PDEP + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PEXT + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .RORX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SARX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHLX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHRX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .MULX + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + // .ADCX + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + // .ADOX + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + // .MOVAPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVUPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVAPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVUPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVSS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVDQA + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVDQU + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVHPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVHPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLHPS + {written={.OP0}, read={.OP1}}, + // .MOVHLPS + {written={.OP0}, read={.OP1}}, + // .MOVMSKPS + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVMSKPD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVNTPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTDQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTDQA + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ADDPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RCPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RCPSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RSQRTSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ANDPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDNPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDNPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ORPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ORPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XORPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XORPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CMPPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .COMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .COMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .UCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .UCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .SHUFPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHUFPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .UNPCKLPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKHPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKLPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKHPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CVTPS2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPD2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSS2SD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSD2SS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTDQ2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTDQ2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSI2SS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSI2SD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .PADDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDUSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDUSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBUSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBUSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULUDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMADDWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PAND + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PANDN + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .POR + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PXOR + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSLLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSLLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSLLQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRAW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRAD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PCMPEQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPEQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPEQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKSSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKSSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKUSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLQDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHQDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSHUFD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PEXTRW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .PINSRW + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PMOVMSKB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .PAVGB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PAVGW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSADBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MASKMOVDQU + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + // .LFENCE + {side_effects={.FENCE, .SERIALIZING}}, + // .SFENCE + {side_effects={.FENCE}}, + // .MFENCE + {side_effects={.FENCE}}, + // .PAUSE + {side_effects={.HINT}}, + // .CLFLUSH + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .ADDSUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HADDPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HADDPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HSUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HSUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MOVDDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSLDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSHDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .LDDQU + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSHUFB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMADDUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHRSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGNB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGNW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGND + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PALIGNR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDVPS + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .BLENDVPD + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .PBLENDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PBLENDVB + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .DPPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DPPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .EXTRACTPS + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .INSERTPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .MPSADBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PACKUSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PEXTRB + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PEXTRD + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PEXTRQ + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PHMINPOSUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PINSRB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PINSRD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PINSRQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PMAXSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PTEST + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .ROUNDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .PCMPEQQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CRC32 + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + // .PCMPESTRI + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPESTRM + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPISTRI + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPISTRM + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPGTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCLMULQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .AESDEC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESDECLAST + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESENC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESENCLAST + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESIMC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESKEYGENASSIST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHA1MSG1 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1MSG2 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1NEXTE + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1RNDS4 + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHA256MSG1 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA256MSG2 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA256RNDS2 + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .VADDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRTSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VANDPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDNPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDNPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VORPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VORPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VXORPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VXORPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VCMPPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VUCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VUCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VSHUFPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VSHUFPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VUNPCKLPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKHPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKLPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKHPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDVPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDVPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VDPPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDPPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VEXTRACTPS + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VINSERTPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMOVAPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVUPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVAPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVUPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVSS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVSD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVDQA + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVDQU + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVHPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVHPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLHPS + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVHLPS + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVMSKPS + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVMSKPD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVNTPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTDQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTDQA + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VADDSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHADDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHADDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VLDDQU + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVSLDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVSHDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCMPESTRI + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPESTRM + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPISTRI + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPISTRM + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPBROADCASTB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCVTPS2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPD2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSS2SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSD2SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTDQ2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTDQ2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSI2SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSI2SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VPADDB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULUDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMADDWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPAND + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPANDN + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPOR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPXOR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSLLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSLLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRAW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRAD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPCMPEQB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKSSWB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKSSDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKUSWB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKUSDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPEXTRB + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRD + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRQ + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPINSRB + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPMOVMSKB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPTEST + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VPSHUFB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMADDUBSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHRSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGNB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGNW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGND + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPABSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPABSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPABSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPALIGNR + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPBLENDW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPBLENDVB + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMPSADBW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPHMINPOSUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMAXSB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXSD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINSB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINSD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMOVSXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXBQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMULDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VMASKMOVDQU + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + // .VPCLMULQDQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VAESDEC + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESDECLAST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESENC + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESENCLAST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESIMC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VAESKEYGENASSIST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBROADCASTSS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VBROADCASTSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .VBROADCASTF128 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXTRACTF128 + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VINSERTF128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERM2F128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMASKMOVPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VMASKMOVPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VTESTPS + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VTESTPD + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VZEROALL + {implicit_wr={.VECTOR}}, + // .VZEROUPPER + {implicit_wr={.VECTOR}}, + // .VBROADCASTI128 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXTRACTI128 + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VINSERTI128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERM2I128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPSLLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRAVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMASKMOVD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VPMASKMOVQ + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VGATHERDPS + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERDPD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERQPS + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERQPD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERDD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERDQ + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERQD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERQQ + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VFMADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPH2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPS2PH + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + // .VMOVDQA32 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQA64 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU8 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU16 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU32 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU64 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBLENDMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDMPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCOMPRESSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCOMPRESSQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCOMPRESSPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCOMPRESSPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPEXPANDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPEXPANDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXPANDPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXPANDPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCONFLICTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCONFLICTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPLZCNTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPLZCNTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPERMI2B + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2W + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2D + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2Q + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2PS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2PD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2B + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2W + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2D + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2Q + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2PS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2PD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMOVB2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVW2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVD2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVQ2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2B + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2W + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2D + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2Q + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPROLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSCATTERDD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERDQ + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERQD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERQQ + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERDPS + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERDPD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERQPS + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERQPD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSRAVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRAVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VRANGEPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGEPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCEPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCEPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALEPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALEPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFPCLASSPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSSS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VALIGNQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VALIGND + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VDBPSADBW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPTERNLOGD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPTERNLOGQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPMULTISHIFTQB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .KADDW + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDB + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDD + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDW + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDB + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDD + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNW + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNB + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDND + {written={.OP0}, read={.OP1, .OP2}}, + // .KMOVW + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVB + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KNOTW + {written={.OP0}, read={.OP1}}, + // .KNOTB + {written={.OP0}, read={.OP1}}, + // .KNOTQ + {written={.OP0}, read={.OP1}}, + // .KNOTD + {written={.OP0}, read={.OP1}}, + // .KORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KORD + {written={.OP0}, read={.OP1, .OP2}}, + // .KORTESTW + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTB + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTQ + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTD + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KSHIFTLW + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLB + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLD + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRW + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRB + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRD + {written={.OP0}, read={.OP1, .OP2}}, + // .KTESTW + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTB + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTQ + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTD + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KUNPCKBW + {written={.OP0}, read={.OP1, .OP2}}, + // .KUNPCKWD + {written={.OP0}, read={.OP1, .OP2}}, + // .KUNPCKDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORD + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORD + {written={.OP0}, read={.OP1, .OP2}}, + // .FADD + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FADDP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIADD + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSUB + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSUBP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FISUB + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSUBR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSUBRP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FISUBR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FMUL + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FMULP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIMUL + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FDIV + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDIVP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIDIV + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FDIVR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDIVRP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIDIVR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSQRT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FABS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCHS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPREM + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPREM1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FRNDINT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSCALE + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FXTRACT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FXAM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FLD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FILD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FBLD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FST + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FSTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FIST + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FISTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FISTTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FBSTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXCH + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCMOVB + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + // .FCMOVE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + // .FCMOVBE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + // .FCMOVU + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + // .FCMOVNB + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + // .FCMOVNE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + // .FCMOVNBE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + // .FCMOVNU + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + // .FCOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOMPP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FICOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FICOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FCOMI + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FCOMIP + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOMI + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOMIP + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FUCOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FUCOMPP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FTST + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FLDZ + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLD1 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDPI + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDL2T + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDL2E + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDLG2 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDLN2 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FSIN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSINCOS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPTAN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPATAN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .F2XM1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FYL2X + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FYL2XP1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FINIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNINIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FINCSTP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDECSTP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FFREE + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FFREEP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNOP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FWAIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCLEX + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNCLEX + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSTCW + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSTCW + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FLDCW + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSTENV + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSTENV + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FLDENV + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FRSTOR + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSTSW + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + // .FNSTSW + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + // .FXSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXSAVE64 + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXRSTOR + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FXRSTOR64 + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .LGDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SGDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + // .LIDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SIDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + // .LLDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SLDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .LTR + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .STR + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .LMSW + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SMSW + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .CLTS + {side_effects={.PRIVILEGED}}, + // .ARPL + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .LAR + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + // .LSL + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + // .VERR + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + // .VERW + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + // .INVD + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .WBINVD + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .INVLPG + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .INVPCID + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .RSM + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .RDMSR + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, + // .WRMSR + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .VMCALL + {side_effects={.PRIVILEGED}}, + // .VMLAUNCH + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMRESUME + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMXOFF + {side_effects={.PRIVILEGED}}, + // .VMXON + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMCLEAR + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMPTRLD + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMPTRST + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMREAD + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMWRITE + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMFUNC + {side_effects={.PRIVILEGED}}, + // .INVEPT + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .INVVPID + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .ENCLS + {side_effects={.PRIVILEGED}}, + // .ENCLU + {side_effects={.PRIVILEGED}}, + // .ENCLV + {side_effects={.PRIVILEGED}}, + // .RDPKRU + {implicit_wr={.RAX}, implicit_rd={.RCX}}, + // .WRPKRU + {implicit_rd={.RAX, .RCX, .RDX}}, + // .INCSSPD + {read={.OP0}, side_effects={.CET}}, + // .INCSSPQ + {read={.OP0}, side_effects={.CET}}, + // .RDSSPD + {written={.OP0}, side_effects={.CET}}, + // .RDSSPQ + {written={.OP0}, side_effects={.CET}}, + // .SAVEPREVSSP + {side_effects={.CET}}, + // .RSTORSSP + {side_effects={.CET}}, + // .WRSSD + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRSSQ + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRUSSD + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRUSSQ + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .SETSSBSY + {side_effects={.CET}}, + // .CLRSSBSY + {side_effects={.CET}}, + // .ENDBR64 + {side_effects={.HINT, .CET}}, + // .ENDBR32 + {side_effects={.HINT, .CET}}, + // .XSAVE + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVE64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XRSTOR + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + // .XRSTOR64 + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + // .XSAVEOPT + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEOPT64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEC + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEC64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVES + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .XSAVES64 + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .XRSTORS + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .XRSTORS64 + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .PREFETCHT0 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHT1 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHT2 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHNTA + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHW + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .CLFLUSHOPT + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .CLWB + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .CLDEMOTE + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .BSWAP + {written={.OP0}, read={.OP0}}, + {written={.OP0}, read={.OP0}}, + // .CMPXCHG + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .CMPXCHG8B + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .CMPXCHG16B + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .XADD + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BOUND + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + // .ENTER + {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, + // .LEAVE + {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, + // .XLAT + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + // .XLATB + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + // .MOVBE + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .RDRAND + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .RDSEED + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, +} + @(rodata) ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .INVALID = { 0, 0}, @@ -3758,143 +7346,141 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .MOVS = { 630, 1}, .MOVSB = { 631, 1}, .MOVSW = { 632, 1}, - .MOVSD = { 633, 1}, - .MOVSQ = { 634, 1}, - .CMPS = { 635, 1}, - .CMPSB = { 636, 1}, - .CMPSW = { 637, 1}, - .CMPSD = { 638, 1}, - .CMPSQ = { 639, 1}, - .SCAS = { 640, 1}, - .SCASB = { 641, 1}, - .SCASW = { 642, 1}, - .SCASD = { 643, 1}, - .SCASQ = { 644, 1}, - .LODS = { 645, 1}, - .LODSB = { 646, 1}, - .LODSW = { 647, 1}, - .LODSD = { 648, 1}, - .LODSQ = { 649, 1}, - .STOS = { 650, 1}, - .STOSB = { 651, 1}, - .STOSW = { 652, 1}, - .STOSD = { 653, 1}, - .STOSQ = { 654, 1}, - .CLC = { 655, 1}, - .STC = { 656, 1}, - .CMC = { 657, 1}, - .CLD = { 658, 1}, - .STD = { 659, 1}, - .CLI = { 660, 1}, - .STI = { 661, 1}, - .LAHF = { 662, 1}, - .SAHF = { 663, 1}, - .PUSHF = { 664, 1}, - .PUSHFD = { 665, 1}, - .PUSHFQ = { 666, 1}, - .POPF = { 667, 1}, - .POPFD = { 668, 1}, - .POPFQ = { 669, 1}, - .NOP = { 670, 4}, - .HLT = { 674, 1}, - .WAIT = { 675, 1}, - .LOCK = { 676, 1}, - .UD0 = { 677, 1}, - .UD1 = { 678, 1}, - .UD2 = { 679, 1}, - .CPUID = { 680, 1}, - .RDTSC = { 681, 1}, - .RDTSCP = { 682, 1}, - .RDPMC = { 683, 1}, - .XGETBV = { 684, 1}, - .XSETBV = { 685, 1}, - .CBW = { 686, 1}, - .CWDE = { 687, 1}, - .CDQE = { 688, 1}, - .CWD = { 689, 1}, - .CDQ = { 690, 1}, - .CQO = { 691, 1}, - .ANDN = { 692, 2}, - .BEXTR = { 694, 2}, - .BLSI = { 696, 2}, - .BLSMSK = { 698, 2}, - .BLSR = { 700, 2}, - .BZHI = { 702, 2}, - .PDEP = { 704, 2}, - .PEXT = { 706, 2}, - .RORX = { 708, 2}, - .SARX = { 710, 2}, - .SHLX = { 712, 2}, - .SHRX = { 714, 2}, - .MULX = { 716, 2}, - .ADCX = { 718, 2}, - .ADOX = { 720, 2}, - .MOVAPS = { 722, 2}, - .MOVUPS = { 724, 2}, - .MOVAPD = { 726, 2}, - .MOVUPD = { 728, 2}, - .MOVSS = { 730, 2}, - .MOVSD_SSE = { 732, 2}, - .MOVDQA = { 734, 2}, - .MOVDQU = { 736, 2}, - .MOVQ = { 738, 6}, - .MOVD = { 744, 4}, - .MOVLPS = { 748, 2}, - .MOVHPS = { 750, 2}, - .MOVLPD = { 752, 2}, - .MOVHPD = { 754, 2}, - .MOVLHPS = { 756, 1}, - .MOVHLPS = { 757, 1}, - .MOVMSKPS = { 758, 2}, - .MOVMSKPD = { 760, 2}, - .MOVNTPS = { 762, 1}, - .MOVNTPD = { 763, 1}, - .MOVNTDQ = { 764, 1}, - .MOVNTDQA = { 765, 1}, - .ADDPS = { 766, 1}, - .ADDPD = { 767, 1}, - .ADDSS = { 768, 1}, - .ADDSD = { 769, 1}, - .SUBPS = { 770, 1}, - .SUBPD = { 771, 1}, - .SUBSS = { 772, 1}, - .SUBSD = { 773, 1}, - .MULPS = { 774, 1}, - .MULPD = { 775, 1}, - .MULSS = { 776, 1}, - .MULSD = { 777, 1}, - .DIVPS = { 778, 1}, - .DIVPD = { 779, 1}, - .DIVSS = { 780, 1}, - .DIVSD = { 781, 1}, - .SQRTPS = { 782, 1}, - .SQRTPD = { 783, 1}, - .SQRTSS = { 784, 1}, - .SQRTSD = { 785, 1}, - .RCPPS = { 786, 1}, - .RCPSS = { 787, 1}, - .RSQRTPS = { 788, 1}, - .RSQRTSS = { 789, 1}, - .MAXPS = { 790, 1}, - .MAXPD = { 791, 1}, - .MAXSS = { 792, 1}, - .MAXSD = { 793, 1}, - .MINPS = { 794, 1}, - .MINPD = { 795, 1}, - .MINSS = { 796, 1}, - .MINSD = { 797, 1}, - .ANDPS = { 798, 1}, - .ANDPD = { 799, 1}, - .ANDNPS = { 800, 1}, - .ANDNPD = { 801, 1}, - .ORPS = { 802, 1}, - .ORPD = { 803, 1}, - .XORPS = { 804, 1}, - .XORPD = { 805, 1}, - .CMPPS = { 806, 1}, - .CMPPD = { 807, 1}, - .CMPSS = { 808, 1}, - .CMPSD_SSE = { 809, 1}, + .MOVSD = { 633, 3}, + .MOVSQ = { 636, 1}, + .CMPS = { 637, 1}, + .CMPSB = { 638, 1}, + .CMPSW = { 639, 1}, + .CMPSD = { 640, 2}, + .CMPSQ = { 642, 1}, + .SCAS = { 643, 1}, + .SCASB = { 644, 1}, + .SCASW = { 645, 1}, + .SCASD = { 646, 1}, + .SCASQ = { 647, 1}, + .LODS = { 648, 1}, + .LODSB = { 649, 1}, + .LODSW = { 650, 1}, + .LODSD = { 651, 1}, + .LODSQ = { 652, 1}, + .STOS = { 653, 1}, + .STOSB = { 654, 1}, + .STOSW = { 655, 1}, + .STOSD = { 656, 1}, + .STOSQ = { 657, 1}, + .CLC = { 658, 1}, + .STC = { 659, 1}, + .CMC = { 660, 1}, + .CLD = { 661, 1}, + .STD = { 662, 1}, + .CLI = { 663, 1}, + .STI = { 664, 1}, + .LAHF = { 665, 1}, + .SAHF = { 666, 1}, + .PUSHF = { 667, 1}, + .PUSHFD = { 668, 1}, + .PUSHFQ = { 669, 1}, + .POPF = { 670, 1}, + .POPFD = { 671, 1}, + .POPFQ = { 672, 1}, + .NOP = { 673, 4}, + .HLT = { 677, 1}, + .WAIT = { 678, 1}, + .LOCK = { 679, 1}, + .UD0 = { 680, 1}, + .UD1 = { 681, 1}, + .UD2 = { 682, 1}, + .CPUID = { 683, 1}, + .RDTSC = { 684, 1}, + .RDTSCP = { 685, 1}, + .RDPMC = { 686, 1}, + .XGETBV = { 687, 1}, + .XSETBV = { 688, 1}, + .CBW = { 689, 1}, + .CWDE = { 690, 1}, + .CDQE = { 691, 1}, + .CWD = { 692, 1}, + .CDQ = { 693, 1}, + .CQO = { 694, 1}, + .ANDN = { 695, 2}, + .BEXTR = { 697, 2}, + .BLSI = { 699, 2}, + .BLSMSK = { 701, 2}, + .BLSR = { 703, 2}, + .BZHI = { 705, 2}, + .PDEP = { 707, 2}, + .PEXT = { 709, 2}, + .RORX = { 711, 2}, + .SARX = { 713, 2}, + .SHLX = { 715, 2}, + .SHRX = { 717, 2}, + .MULX = { 719, 2}, + .ADCX = { 721, 2}, + .ADOX = { 723, 2}, + .MOVAPS = { 725, 2}, + .MOVUPS = { 727, 2}, + .MOVAPD = { 729, 2}, + .MOVUPD = { 731, 2}, + .MOVSS = { 733, 2}, + .MOVDQA = { 735, 2}, + .MOVDQU = { 737, 2}, + .MOVQ = { 739, 6}, + .MOVD = { 745, 4}, + .MOVLPS = { 749, 2}, + .MOVHPS = { 751, 2}, + .MOVLPD = { 753, 2}, + .MOVHPD = { 755, 2}, + .MOVLHPS = { 757, 1}, + .MOVHLPS = { 758, 1}, + .MOVMSKPS = { 759, 2}, + .MOVMSKPD = { 761, 2}, + .MOVNTPS = { 763, 1}, + .MOVNTPD = { 764, 1}, + .MOVNTDQ = { 765, 1}, + .MOVNTDQA = { 766, 1}, + .ADDPS = { 767, 1}, + .ADDPD = { 768, 1}, + .ADDSS = { 769, 1}, + .ADDSD = { 770, 1}, + .SUBPS = { 771, 1}, + .SUBPD = { 772, 1}, + .SUBSS = { 773, 1}, + .SUBSD = { 774, 1}, + .MULPS = { 775, 1}, + .MULPD = { 776, 1}, + .MULSS = { 777, 1}, + .MULSD = { 778, 1}, + .DIVPS = { 779, 1}, + .DIVPD = { 780, 1}, + .DIVSS = { 781, 1}, + .DIVSD = { 782, 1}, + .SQRTPS = { 783, 1}, + .SQRTPD = { 784, 1}, + .SQRTSS = { 785, 1}, + .SQRTSD = { 786, 1}, + .RCPPS = { 787, 1}, + .RCPSS = { 788, 1}, + .RSQRTPS = { 789, 1}, + .RSQRTSS = { 790, 1}, + .MAXPS = { 791, 1}, + .MAXPD = { 792, 1}, + .MAXSS = { 793, 1}, + .MAXSD = { 794, 1}, + .MINPS = { 795, 1}, + .MINPD = { 796, 1}, + .MINSS = { 797, 1}, + .MINSD = { 798, 1}, + .ANDPS = { 799, 1}, + .ANDPD = { 800, 1}, + .ANDNPS = { 801, 1}, + .ANDNPD = { 802, 1}, + .ORPS = { 803, 1}, + .ORPD = { 804, 1}, + .XORPS = { 805, 1}, + .XORPD = { 806, 1}, + .CMPPS = { 807, 1}, + .CMPPD = { 808, 1}, + .CMPSS = { 809, 1}, .COMISS = { 810, 1}, .COMISD = { 811, 1}, .UCOMISS = { 812, 1}, diff --git a/core/rexcode/isa/x86/tablegen/generated/writer.odin b/core/rexcode/isa/x86/tablegen/generated/writer.odin index 85bcd8a48..cae51a210 100644 --- a/core/rexcode/isa/x86/tablegen/generated/writer.odin +++ b/core/rexcode/isa/x86/tablegen/generated/writer.odin @@ -42,5 +42,5 @@ main :: proc() { w(TABLES + "x86.evex_idx_0f.bin", raw(&EVEX_INDEX_0F, size_of(EVEX_INDEX_0F))) w(TABLES + "x86.evex_idx_0f38.bin", raw(&EVEX_INDEX_0F38, size_of(EVEX_INDEX_0F38))) w(TABLES + "x86.evex_idx_0f3a.bin", raw(&EVEX_INDEX_0F3A, size_of(EVEX_INDEX_0F3A))) - w(TABLES + "x86.clobber_table.bin", raw(&tablegen.CLOBBER_TABLE, size_of(tablegen.CLOBBER_TABLE))) + w(TABLES + "x86.clobber_forms.bin", raw(&CLOBBER_FORMS, size_of(CLOBBER_FORMS))) } diff --git a/core/rexcode/isa/x86/tables.odin b/core/rexcode/isa/x86/tables.odin index 13482ddbc..4bd5710a2 100644 --- a/core/rexcode/isa/x86/tables.odin +++ b/core/rexcode/isa/x86/tables.odin @@ -94,7 +94,7 @@ Decode_Index :: struct { @(rodata) EVEX_INDEX_0F := #load("tables/x86.evex_idx_0f.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F38 := #load("tables/x86.evex_idx_0f38.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F3A := #load("tables/x86.evex_idx_0f3a.bin", []Decode_Index) -@(rodata) CLOBBER_TABLE := #load("tables/x86.clobber_table.bin", []Clobber) +@(rodata) CLOBBER_FORMS := #load("tables/x86.clobber_forms.bin", []Clobber) // ----------------------------------------------------------------------------- // Accessors @@ -108,6 +108,14 @@ encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { return ENCODE_FORMS[r.start:][:r.count] } +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +clobber_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Clobber { + r := ENCODE_RUNS[u16(m)] + return CLOBBER_FORMS[r.start:][:r.count] +} + // Flat [prefix][opcode] lookup into a logical [4][256] index table. @(private, require_results) didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { diff --git a/core/rexcode/isa/x86/tables/x86.clobber_table.bin b/core/rexcode/isa/x86/tables/x86.clobber_table.bin deleted file mode 100644 index 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z(bR#)BA2771C2W_!xUp$hNf5KKLcYg6RWZi10xeF10)PU>yZ1H*igj8{xdO7VB&y^ zO$Ub+XdQAt6FXE4q8Btisf;ED8e=@mq@tn$2^VmDfW{8bFlnej?FGjNX#7u$SsleZ z(DUU#^F)`kUi$U}nf#w(BVi3JX|CtzX!o?u! zjQ=w--hqoj)EWP0V!RC(gQ&Ck&%ksYE&M=ZDA&-!4>YDAix$5Q{}~u%(b55EOhFD! z%;`S^(@HeGPX8GgSE8wN`Om<32vdyd5Sm`M{|rnw(8Rp{Gcrnp^eQtkGjfH4;{&uN zS{kHI1uO Date: Tue, 18 Aug 2026 11:23:20 +0100 Subject: [PATCH 79/92] Use new clobber forms in check_asm.cpp --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 19 +- src/asm_tables_amd64.cpp | 2081 ++++++++++------- src/check_asm.cpp | 3 +- 3 files changed, 1201 insertions(+), 902 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 489f5cae7..57622c1a7 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -15,7 +15,7 @@ ISA_NAME :: "amd64" main :: proc() { raw_encode_runs := #load("../../tables/x86.encode_runs.bin", []x86.Encode_Run) raw_encode_forms := #load("../../tables/x86.encode_forms.bin", []u8) - raw_clobber_table := #load("../../tables/x86.clobber_table.bin", []u8) + raw_clobber_forms := #load("../../tables/x86.clobber_forms.bin", []u8) sb := strings.builder_make() @@ -384,7 +384,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs[%d];\n", len(raw_encode_runs)) fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms[%d];\n", len(raw_encode_forms)) - fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_table[%d];\n", len(raw_clobber_table)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_forms[%d];\n", len(raw_clobber_forms)) strings.write_string(&sb, "\tStringMap mnemonic_map;\n") strings.write_string(&sb, "\tStringMap prefix_map;\n") @@ -425,9 +425,10 @@ main :: proc() { Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; return Slice{ENCODE_FORMS+r.start, r.count}; } - Clobber clobber(/*Mnemonic*/ u16 m) const { - Clobber *c = cast(Clobber *)raw_clobber_table; - return c[m]; + Slice clobber_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms; + return Slice{CLOBBER_FORMS+r.start, r.count}; } u16 reg_class(/*Register*/ u16 r) const { return 0xFF00 & r; @@ -676,10 +677,6 @@ main :: proc() { #partial switch mnemonic { case .INVALID: strings.write_string(&sb, "str_lit(\"\"), ") - case .MOVSD_SSE: - strings.write_string(&sb, "str_lit(\"movsd\"), ") - case .CMPSD_SSE: - strings.write_string(&sb, "str_lit(\"cmpsd\"), ") case: str := strings.to_lower(reflect.enum_string(mnemonic)) fmt.sbprintf(&sb, "str_lit(%q), ", str) @@ -812,11 +809,11 @@ main :: proc() { defer strings.write_string(&sb, "\n"); } { - fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_clobber_table[%d] = {{\n", ISA_NAME, len(raw_clobber_table)) + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_clobber_forms[%d] = {{\n", ISA_NAME, len(raw_clobber_forms)) defer strings.write_string(&sb, "};\n"); ROW_COUNT :: 64 count := 0 - for the_byte in raw_clobber_table { + for the_byte in raw_clobber_forms { if count == 0 { strings.write_string(&sb, "\t") } diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 1c229c97d..7a734b2db 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -25,67 +25,67 @@ struct Asm_amd64 { M_STOSW, M_STOSD, M_STOSQ, M_CLC, M_STC, M_CMC, M_CLD, M_STD, M_CLI, M_STI, M_LAHF, M_SAHF, M_PUSHF, M_PUSHFD, M_PUSHFQ, M_POPF, M_POPFD, M_POPFQ, M_NOP, M_HLT, M_WAIT, M_LOCK, M_UD0, M_UD1, M_UD2, M_CPUID, M_RDTSC, M_RDTSCP, M_RDPMC, M_XGETBV, M_XSETBV, M_CBW, M_CWDE, M_CDQE, M_CWD, M_CDQ, M_CQO, M_ANDN, M_BEXTR, M_BLSI, M_BLSMSK, M_BLSR, M_BZHI, M_PDEP, M_PEXT, M_RORX, M_SARX, M_SHLX, - M_SHRX, M_MULX, M_ADCX, M_ADOX, M_MOVAPS, M_MOVUPS, M_MOVAPD, M_MOVUPD, M_MOVSS, M_MOVSD_SSE, M_MOVDQA, M_MOVDQU, M_MOVQ, M_MOVD, M_MOVLPS, M_MOVHPS, - M_MOVLPD, M_MOVHPD, M_MOVLHPS, M_MOVHLPS, M_MOVMSKPS, M_MOVMSKPD, M_MOVNTPS, M_MOVNTPD, M_MOVNTDQ, M_MOVNTDQA, M_ADDPS, M_ADDPD, M_ADDSS, M_ADDSD, M_SUBPS, M_SUBPD, - M_SUBSS, M_SUBSD, M_MULPS, M_MULPD, M_MULSS, M_MULSD, M_DIVPS, M_DIVPD, M_DIVSS, M_DIVSD, M_SQRTPS, M_SQRTPD, M_SQRTSS, M_SQRTSD, M_RCPPS, M_RCPSS, - M_RSQRTPS, M_RSQRTSS, M_MAXPS, M_MAXPD, M_MAXSS, M_MAXSD, M_MINPS, M_MINPD, M_MINSS, M_MINSD, M_ANDPS, M_ANDPD, M_ANDNPS, M_ANDNPD, M_ORPS, M_ORPD, - M_XORPS, M_XORPD, M_CMPPS, M_CMPPD, M_CMPSS, M_CMPSD_SSE, M_COMISS, M_COMISD, M_UCOMISS, M_UCOMISD, M_SHUFPS, M_SHUFPD, M_UNPCKLPS, M_UNPCKHPS, M_UNPCKLPD, M_UNPCKHPD, - M_CVTPS2PD, M_CVTPD2PS, M_CVTSS2SD, M_CVTSD2SS, M_CVTPS2DQ, M_CVTPD2DQ, M_CVTDQ2PS, M_CVTDQ2PD, M_CVTSS2SI, M_CVTSD2SI, M_CVTSI2SS, M_CVTSI2SD, M_CVTTPS2DQ, M_CVTTPD2DQ, M_CVTTSS2SI, M_CVTTSD2SI, - M_PADDB, M_PADDW, M_PADDD, M_PADDQ, M_PSUBB, M_PSUBW, M_PSUBD, M_PSUBQ, M_PADDSB, M_PADDSW, M_PADDUSB, M_PADDUSW, M_PSUBSB, M_PSUBSW, M_PSUBUSB, M_PSUBUSW, - M_PMULLW, M_PMULHW, M_PMULHUW, M_PMULUDQ, M_PMADDWD, M_PAND, M_PANDN, M_POR, M_PXOR, M_PSLLW, M_PSLLD, M_PSLLQ, M_PSRLW, M_PSRLD, M_PSRLQ, M_PSRAW, - M_PSRAD, M_PCMPEQB, M_PCMPEQW, M_PCMPEQD, M_PCMPGTB, M_PCMPGTW, M_PCMPGTD, M_PACKSSWB, M_PACKSSDW, M_PACKUSWB, M_PUNPCKLBW, M_PUNPCKLWD, M_PUNPCKLDQ, M_PUNPCKLQDQ, M_PUNPCKHBW, M_PUNPCKHWD, - M_PUNPCKHDQ, M_PUNPCKHQDQ, M_PSHUFD, M_PSHUFHW, M_PSHUFLW, M_PSHUFW, M_PEXTRW, M_PINSRW, M_PMOVMSKB, M_PAVGB, M_PAVGW, M_PMAXUB, M_PMAXSW, M_PMINUB, M_PMINSW, M_PSADBW, - M_MASKMOVDQU, M_LFENCE, M_SFENCE, M_MFENCE, M_PAUSE, M_CLFLUSH, M_ADDSUBPS, M_ADDSUBPD, M_HADDPS, M_HADDPD, M_HSUBPS, M_HSUBPD, M_MOVDDUP, M_MOVSLDUP, M_MOVSHDUP, M_LDDQU, - M_PSHUFB, M_PHADDW, M_PHADDD, M_PHADDSW, M_PHSUBW, M_PHSUBD, M_PHSUBSW, M_PMADDUBSW, M_PMULHRSW, M_PSIGNB, M_PSIGNW, M_PSIGND, M_PABSB, M_PABSW, M_PABSD, M_PALIGNR, - M_BLENDPS, M_BLENDPD, M_BLENDVPS, M_BLENDVPD, M_PBLENDW, M_PBLENDVB, M_DPPS, M_DPPD, M_EXTRACTPS, M_INSERTPS, M_MPSADBW, M_PACKUSDW, M_PEXTRB, M_PEXTRD, M_PEXTRQ, M_PHMINPOSUW, - M_PINSRB, M_PINSRD, M_PINSRQ, M_PMAXSB, M_PMAXSD, M_PMAXUW, M_PMAXUD, M_PMINSB, M_PMINSD, M_PMINUW, M_PMINUD, M_PMOVSXBW, M_PMOVSXBD, M_PMOVSXBQ, M_PMOVSXWD, M_PMOVSXWQ, - M_PMOVSXDQ, M_PMOVZXBW, M_PMOVZXBD, M_PMOVZXBQ, M_PMOVZXWD, M_PMOVZXWQ, M_PMOVZXDQ, M_PMULDQ, M_PMULLD, M_PTEST, M_ROUNDPS, M_ROUNDPD, M_ROUNDSS, M_ROUNDSD, M_PCMPEQQ, M_CRC32, - M_PCMPESTRI, M_PCMPESTRM, M_PCMPISTRI, M_PCMPISTRM, M_PCMPGTQ, M_PCLMULQDQ, M_AESDEC, M_AESDECLAST, M_AESENC, M_AESENCLAST, M_AESIMC, M_AESKEYGENASSIST, M_SHA1MSG1, M_SHA1MSG2, M_SHA1NEXTE, M_SHA1RNDS4, - M_SHA256MSG1, M_SHA256MSG2, M_SHA256RNDS2, M_VADDPS, M_VADDPD, M_VADDSS, M_VADDSD, M_VSUBPS, M_VSUBPD, M_VSUBSS, M_VSUBSD, M_VMULPS, M_VMULPD, M_VMULSS, M_VMULSD, M_VDIVPS, - M_VDIVPD, M_VDIVSS, M_VDIVSD, M_VSQRTPS, M_VSQRTPD, M_VSQRTSS, M_VSQRTSD, M_VRCPPS, M_VRCPSS, M_VRSQRTPS, M_VRSQRTSS, M_VMAXPS, M_VMAXPD, M_VMAXSS, M_VMAXSD, M_VMINPS, - M_VMINPD, M_VMINSS, M_VMINSD, M_VANDPS, M_VANDPD, M_VANDNPS, M_VANDNPD, M_VORPS, M_VORPD, M_VXORPS, M_VXORPD, M_VCMPPS, M_VCMPPD, M_VCMPSS, M_VCMPSD, M_VCOMISS, - M_VCOMISD, M_VUCOMISS, M_VUCOMISD, M_VSHUFPS, M_VSHUFPD, M_VUNPCKLPS, M_VUNPCKHPS, M_VUNPCKLPD, M_VUNPCKHPD, M_VBLENDPS, M_VBLENDPD, M_VBLENDVPS, M_VBLENDVPD, M_VDPPS, M_VDPPD, M_VROUNDPS, - M_VROUNDPD, M_VROUNDSS, M_VROUNDSD, M_VEXTRACTPS, M_VINSERTPS, M_VMOVAPS, M_VMOVUPS, M_VMOVAPD, M_VMOVUPD, M_VMOVSS, M_VMOVSD, M_VMOVDQA, M_VMOVDQU, M_VMOVQ, M_VMOVD, M_VMOVLPS, - M_VMOVHPS, M_VMOVLPD, M_VMOVHPD, M_VMOVLHPS, M_VMOVHLPS, M_VMOVMSKPS, M_VMOVMSKPD, M_VMOVNTPS, M_VMOVNTPD, M_VMOVNTDQ, M_VMOVNTDQA, M_VADDSUBPS, M_VADDSUBPD, M_VHADDPS, M_VHADDPD, M_VHSUBPS, - M_VHSUBPD, M_VLDDQU, M_VMOVDDUP, M_VMOVSLDUP, M_VMOVSHDUP, M_VPCMPESTRI, M_VPCMPESTRM, M_VPCMPISTRI, M_VPCMPISTRM, M_VPBROADCASTB, M_VPBROADCASTW, M_VPBROADCASTD, M_VPBROADCASTQ, M_VCVTPS2PD, M_VCVTPD2PS, M_VCVTSS2SD, - M_VCVTSD2SS, M_VCVTPS2DQ, M_VCVTPD2DQ, M_VCVTDQ2PS, M_VCVTDQ2PD, M_VCVTSS2SI, M_VCVTSD2SI, M_VCVTSI2SS, M_VCVTSI2SD, M_VCVTTPS2DQ, M_VCVTTPD2DQ, M_VCVTTSS2SI, M_VCVTTSD2SI, M_VPADDB, M_VPADDW, M_VPADDD, - M_VPADDQ, M_VPSUBB, M_VPSUBW, M_VPSUBD, M_VPSUBQ, M_VPMULLW, M_VPMULHW, M_VPMULHUW, M_VPMULUDQ, M_VPMADDWD, M_VPAND, M_VPANDN, M_VPOR, M_VPXOR, M_VPSLLW, M_VPSLLD, - M_VPSLLQ, M_VPSRLW, M_VPSRLD, M_VPSRLQ, M_VPSRAW, M_VPSRAD, M_VPCMPEQB, M_VPCMPEQW, M_VPCMPEQD, M_VPCMPEQQ, M_VPCMPGTB, M_VPCMPGTW, M_VPCMPGTD, M_VPCMPGTQ, M_VPACKSSWB, M_VPACKSSDW, - M_VPACKUSWB, M_VPACKUSDW, M_VPUNPCKLBW, M_VPUNPCKLWD, M_VPUNPCKLDQ, M_VPUNPCKLQDQ, M_VPUNPCKHBW, M_VPUNPCKHWD, M_VPUNPCKHDQ, M_VPUNPCKHQDQ, M_VPSHUFD, M_VPSHUFHW, M_VPSHUFLW, M_VPEXTRB, M_VPEXTRW, M_VPEXTRD, - M_VPEXTRQ, M_VPINSRB, M_VPINSRW, M_VPINSRD, M_VPINSRQ, M_VPMOVMSKB, M_VPTEST, M_VPSHUFB, M_VPHADDW, M_VPHADDD, M_VPHADDSW, M_VPHSUBW, M_VPHSUBD, M_VPHSUBSW, M_VPMADDUBSW, M_VPMULHRSW, - M_VPSIGNB, M_VPSIGNW, M_VPSIGND, M_VPABSB, M_VPABSW, M_VPABSD, M_VPALIGNR, M_VPBLENDW, M_VPBLENDVB, M_VMPSADBW, M_VPHMINPOSUW, M_VPMAXSB, M_VPMAXSD, M_VPMAXUW, M_VPMAXUD, M_VPMINSB, - M_VPMINSD, M_VPMINUW, M_VPMINUD, M_VPMOVSXBW, M_VPMOVSXBD, M_VPMOVSXBQ, M_VPMOVSXWD, M_VPMOVSXWQ, M_VPMOVSXDQ, M_VPMOVZXBW, M_VPMOVZXBD, M_VPMOVZXBQ, M_VPMOVZXWD, M_VPMOVZXWQ, M_VPMOVZXDQ, M_VPMULDQ, - M_VPMULLD, M_VMASKMOVDQU, M_VPCLMULQDQ, M_VAESDEC, M_VAESDECLAST, M_VAESENC, M_VAESENCLAST, M_VAESIMC, M_VAESKEYGENASSIST, M_VBROADCASTSS, M_VBROADCASTSD, M_VBROADCASTF128, M_VEXTRACTF128, M_VINSERTF128, M_VPERM2F128, M_VMASKMOVPS, - M_VMASKMOVPD, M_VTESTPS, M_VTESTPD, M_VZEROALL, M_VZEROUPPER, M_VBROADCASTI128, M_VEXTRACTI128, M_VINSERTI128, M_VPERM2I128, M_VPERMD, M_VPERMPS, M_VPERMQ, M_VPERMPD, M_VPBLENDD, M_VPSLLVD, M_VPSLLVQ, - M_VPSRLVD, M_VPSRLVQ, M_VPSRAVD, M_VPMASKMOVD, M_VPMASKMOVQ, M_VGATHERDPS, M_VGATHERDPD, M_VGATHERQPS, M_VGATHERQPD, M_VPGATHERDD, M_VPGATHERDQ, M_VPGATHERQD, M_VPGATHERQQ, M_VFMADD132PS, M_VFMADD213PS, M_VFMADD231PS, - M_VFMADD132PD, M_VFMADD213PD, M_VFMADD231PD, M_VFMADD132SS, M_VFMADD213SS, M_VFMADD231SS, M_VFMADD132SD, M_VFMADD213SD, M_VFMADD231SD, M_VFMSUB132PS, M_VFMSUB213PS, M_VFMSUB231PS, M_VFMSUB132PD, M_VFMSUB213PD, M_VFMSUB231PD, M_VFMSUB132SS, - M_VFMSUB213SS, M_VFMSUB231SS, M_VFMSUB132SD, M_VFMSUB213SD, M_VFMSUB231SD, M_VFNMADD132PS, M_VFNMADD213PS, M_VFNMADD231PS, M_VFNMADD132PD, M_VFNMADD213PD, M_VFNMADD231PD, M_VFNMADD132SS, M_VFNMADD213SS, M_VFNMADD231SS, M_VFNMADD132SD, M_VFNMADD213SD, - M_VFNMADD231SD, M_VFNMSUB132PS, M_VFNMSUB213PS, M_VFNMSUB231PS, M_VFNMSUB132PD, M_VFNMSUB213PD, M_VFNMSUB231PD, M_VFNMSUB132SS, M_VFNMSUB213SS, M_VFNMSUB231SS, M_VFNMSUB132SD, M_VFNMSUB213SD, M_VFNMSUB231SD, M_VFMADDSUB132PS, M_VFMADDSUB213PS, M_VFMADDSUB231PS, - M_VFMADDSUB132PD, M_VFMADDSUB213PD, M_VFMADDSUB231PD, M_VFMSUBADD132PS, M_VFMSUBADD213PS, M_VFMSUBADD231PS, M_VFMSUBADD132PD, M_VFMSUBADD213PD, M_VFMSUBADD231PD, M_VCVTPH2PS, M_VCVTPS2PH, M_VMOVDQA32, M_VMOVDQA64, M_VMOVDQU8, M_VMOVDQU16, M_VMOVDQU32, - M_VMOVDQU64, M_VPBLENDMB, M_VPBLENDMW, M_VPBLENDMD, M_VPBLENDMQ, M_VBLENDMPS, M_VBLENDMPD, M_VPCMPB, M_VPCMPUB, M_VPCMPW, M_VPCMPUW, M_VPCMPD, M_VPCMPUD, M_VPCMPQ, M_VPCMPUQ, M_VPTESTMB, - M_VPTESTMW, M_VPTESTMD, M_VPTESTMQ, M_VPTESTNMB, M_VPTESTNMW, M_VPTESTNMD, M_VPTESTNMQ, M_VPCOMPRESSD, M_VPCOMPRESSQ, M_VCOMPRESSPS, M_VCOMPRESSPD, M_VPEXPANDD, M_VPEXPANDQ, M_VEXPANDPS, M_VEXPANDPD, M_VPCONFLICTD, - M_VPCONFLICTQ, M_VPLZCNTD, M_VPLZCNTQ, M_VPERMI2B, M_VPERMI2W, M_VPERMI2D, M_VPERMI2Q, M_VPERMI2PS, M_VPERMI2PD, M_VPERMT2B, M_VPERMT2W, M_VPERMT2D, M_VPERMT2Q, M_VPERMT2PS, M_VPERMT2PD, M_VPERMB, - M_VPERMW, M_VPMOVB2M, M_VPMOVW2M, M_VPMOVD2M, M_VPMOVQ2M, M_VPMOVM2B, M_VPMOVM2W, M_VPMOVM2D, M_VPMOVM2Q, M_VPMOVQB, M_VPMOVSQB, M_VPMOVUSQB, M_VPMOVQW, M_VPMOVSQW, M_VPMOVUSQW, M_VPMOVQD, - M_VPMOVSQD, M_VPMOVUSQD, M_VPMOVDB, M_VPMOVSDB, M_VPMOVUSDB, M_VPMOVDW, M_VPMOVSDW, M_VPMOVUSDW, M_VPMOVWB, M_VPMOVSWB, M_VPMOVUSWB, M_VPROLD, M_VPROLQ, M_VPROLVD, M_VPROLVQ, M_VPRORD, - M_VPRORQ, M_VPRORVD, M_VPRORVQ, M_VPSCATTERDD, M_VPSCATTERDQ, M_VPSCATTERQD, M_VPSCATTERQQ, M_VSCATTERDPS, M_VSCATTERDPD, M_VSCATTERQPS, M_VSCATTERQPD, M_VPSRAVQ, M_VPSRAVW, M_VPSLLVW, M_VPSRLVW, M_VRANGEPS, - M_VRANGEPD, M_VRANGESS, M_VRANGESD, M_VREDUCEPS, M_VREDUCEPD, M_VREDUCESS, M_VREDUCESD, M_VRNDSCALEPS, M_VRNDSCALEPD, M_VRNDSCALESS, M_VRNDSCALESD, M_VRSQRT14PS, M_VRSQRT14PD, M_VRSQRT14SS, M_VRSQRT14SD, M_VRCP14PS, - M_VRCP14PD, M_VRCP14SS, M_VRCP14SD, M_VSCALEFPS, M_VSCALEFPD, M_VSCALEFSS, M_VSCALEFSD, M_VGETEXPPS, M_VGETEXPPD, M_VGETEXPSS, M_VGETEXPSD, M_VGETMANTPS, M_VGETMANTPD, M_VGETMANTSS, M_VGETMANTSD, M_VFIXUPIMMPS, - M_VFIXUPIMMPD, M_VFIXUPIMMSS, M_VFIXUPIMMSD, M_VFPCLASSPS, M_VFPCLASSPD, M_VFPCLASSSS, M_VFPCLASSSD, M_VALIGNQ, M_VALIGND, M_VDBPSADBW, M_VPTERNLOGD, M_VPTERNLOGQ, M_VPMULTISHIFTQB, M_KADDW, M_KADDB, M_KADDQ, - M_KADDD, M_KANDW, M_KANDB, M_KANDQ, M_KANDD, M_KANDNW, M_KANDNB, M_KANDNQ, M_KANDND, M_KMOVW, M_KMOVB, M_KMOVQ, M_KMOVD, M_KNOTW, M_KNOTB, M_KNOTQ, - M_KNOTD, M_KORW, M_KORB, M_KORQ, M_KORD, M_KORTESTW, M_KORTESTB, M_KORTESTQ, M_KORTESTD, M_KSHIFTLW, M_KSHIFTLB, M_KSHIFTLQ, M_KSHIFTLD, M_KSHIFTRW, M_KSHIFTRB, M_KSHIFTRQ, - M_KSHIFTRD, M_KTESTW, M_KTESTB, M_KTESTQ, M_KTESTD, M_KUNPCKBW, M_KUNPCKWD, M_KUNPCKDQ, M_KXNORW, M_KXNORB, M_KXNORQ, M_KXNORD, M_KXORW, M_KXORB, M_KXORQ, M_KXORD, - M_FADD, M_FADDP, M_FIADD, M_FSUB, M_FSUBP, M_FISUB, M_FSUBR, M_FSUBRP, M_FISUBR, M_FMUL, M_FMULP, M_FIMUL, M_FDIV, M_FDIVP, M_FIDIV, M_FDIVR, - M_FDIVRP, M_FIDIVR, M_FSQRT, M_FABS, M_FCHS, M_FPREM, M_FPREM1, M_FRNDINT, M_FSCALE, M_FXTRACT, M_FXAM, M_FLD, M_FILD, M_FBLD, M_FST, M_FSTP, - M_FIST, M_FISTP, M_FISTTP, M_FBSTP, M_FXCH, M_FCMOVB, M_FCMOVE, M_FCMOVBE, M_FCMOVU, M_FCMOVNB, M_FCMOVNE, M_FCMOVNBE, M_FCMOVNU, M_FCOM, M_FCOMP, M_FCOMPP, - M_FICOM, M_FICOMP, M_FCOMI, M_FCOMIP, M_FUCOMI, M_FUCOMIP, M_FUCOM, M_FUCOMP, M_FUCOMPP, M_FTST, M_FLDZ, M_FLD1, M_FLDPI, M_FLDL2T, M_FLDL2E, M_FLDLG2, - M_FLDLN2, M_FSIN, M_FCOS, M_FSINCOS, M_FPTAN, M_FPATAN, M_F2XM1, M_FYL2X, M_FYL2XP1, M_FINIT, M_FNINIT, M_FINCSTP, M_FDECSTP, M_FFREE, M_FFREEP, M_FNOP, - M_FWAIT, M_FCLEX, M_FNCLEX, M_FSTCW, M_FNSTCW, M_FLDCW, M_FSTENV, M_FNSTENV, M_FLDENV, M_FSAVE, M_FNSAVE, M_FRSTOR, M_FSTSW, M_FNSTSW, M_FXSAVE, M_FXSAVE64, - M_FXRSTOR, M_FXRSTOR64, M_LGDT, M_SGDT, M_LIDT, M_SIDT, M_LLDT, M_SLDT, M_LTR, M_STR, M_LMSW, M_SMSW, M_CLTS, M_ARPL, M_LAR, M_LSL, - M_VERR, M_VERW, M_INVD, M_WBINVD, M_INVLPG, M_INVPCID, M_RSM, M_RDMSR, M_WRMSR, M_VMCALL, M_VMLAUNCH, M_VMRESUME, M_VMXOFF, M_VMXON, M_VMCLEAR, M_VMPTRLD, - M_VMPTRST, M_VMREAD, M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, - M_RSTORSSP, M_WRSSD, M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, - M_XSAVEC64, M_XSAVES, M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, - M_CMPXCHG16B, M_XADD, M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, + M_SHRX, M_MULX, M_ADCX, M_ADOX, M_MOVAPS, M_MOVUPS, M_MOVAPD, M_MOVUPD, M_MOVSS, M_MOVDQA, M_MOVDQU, M_MOVQ, M_MOVD, M_MOVLPS, M_MOVHPS, M_MOVLPD, + M_MOVHPD, M_MOVLHPS, M_MOVHLPS, M_MOVMSKPS, M_MOVMSKPD, M_MOVNTPS, M_MOVNTPD, M_MOVNTDQ, M_MOVNTDQA, M_ADDPS, M_ADDPD, M_ADDSS, M_ADDSD, M_SUBPS, M_SUBPD, M_SUBSS, + M_SUBSD, M_MULPS, M_MULPD, M_MULSS, M_MULSD, M_DIVPS, M_DIVPD, M_DIVSS, M_DIVSD, M_SQRTPS, M_SQRTPD, M_SQRTSS, M_SQRTSD, M_RCPPS, M_RCPSS, M_RSQRTPS, + M_RSQRTSS, M_MAXPS, M_MAXPD, M_MAXSS, M_MAXSD, M_MINPS, M_MINPD, M_MINSS, M_MINSD, M_ANDPS, M_ANDPD, M_ANDNPS, M_ANDNPD, M_ORPS, M_ORPD, M_XORPS, + M_XORPD, M_CMPPS, M_CMPPD, M_CMPSS, M_COMISS, M_COMISD, M_UCOMISS, M_UCOMISD, M_SHUFPS, M_SHUFPD, M_UNPCKLPS, M_UNPCKHPS, M_UNPCKLPD, M_UNPCKHPD, M_CVTPS2PD, M_CVTPD2PS, + M_CVTSS2SD, M_CVTSD2SS, M_CVTPS2DQ, M_CVTPD2DQ, M_CVTDQ2PS, M_CVTDQ2PD, M_CVTSS2SI, M_CVTSD2SI, M_CVTSI2SS, M_CVTSI2SD, M_CVTTPS2DQ, M_CVTTPD2DQ, M_CVTTSS2SI, M_CVTTSD2SI, M_PADDB, M_PADDW, + M_PADDD, M_PADDQ, M_PSUBB, M_PSUBW, M_PSUBD, M_PSUBQ, M_PADDSB, M_PADDSW, M_PADDUSB, M_PADDUSW, M_PSUBSB, M_PSUBSW, M_PSUBUSB, M_PSUBUSW, M_PMULLW, M_PMULHW, + M_PMULHUW, M_PMULUDQ, M_PMADDWD, M_PAND, M_PANDN, M_POR, M_PXOR, M_PSLLW, M_PSLLD, M_PSLLQ, M_PSRLW, M_PSRLD, M_PSRLQ, M_PSRAW, M_PSRAD, M_PCMPEQB, + M_PCMPEQW, M_PCMPEQD, M_PCMPGTB, M_PCMPGTW, M_PCMPGTD, M_PACKSSWB, M_PACKSSDW, M_PACKUSWB, M_PUNPCKLBW, M_PUNPCKLWD, M_PUNPCKLDQ, M_PUNPCKLQDQ, M_PUNPCKHBW, M_PUNPCKHWD, M_PUNPCKHDQ, M_PUNPCKHQDQ, + M_PSHUFD, M_PSHUFHW, M_PSHUFLW, M_PSHUFW, M_PEXTRW, M_PINSRW, M_PMOVMSKB, M_PAVGB, M_PAVGW, M_PMAXUB, M_PMAXSW, M_PMINUB, M_PMINSW, M_PSADBW, M_MASKMOVDQU, M_LFENCE, + M_SFENCE, M_MFENCE, M_PAUSE, M_CLFLUSH, M_ADDSUBPS, M_ADDSUBPD, M_HADDPS, M_HADDPD, M_HSUBPS, M_HSUBPD, M_MOVDDUP, M_MOVSLDUP, M_MOVSHDUP, M_LDDQU, M_PSHUFB, M_PHADDW, + M_PHADDD, M_PHADDSW, M_PHSUBW, M_PHSUBD, M_PHSUBSW, M_PMADDUBSW, M_PMULHRSW, M_PSIGNB, M_PSIGNW, M_PSIGND, M_PABSB, M_PABSW, M_PABSD, M_PALIGNR, M_BLENDPS, M_BLENDPD, + M_BLENDVPS, M_BLENDVPD, M_PBLENDW, M_PBLENDVB, M_DPPS, M_DPPD, M_EXTRACTPS, M_INSERTPS, M_MPSADBW, M_PACKUSDW, M_PEXTRB, M_PEXTRD, M_PEXTRQ, M_PHMINPOSUW, M_PINSRB, M_PINSRD, + M_PINSRQ, M_PMAXSB, M_PMAXSD, M_PMAXUW, M_PMAXUD, M_PMINSB, M_PMINSD, M_PMINUW, M_PMINUD, M_PMOVSXBW, M_PMOVSXBD, M_PMOVSXBQ, M_PMOVSXWD, M_PMOVSXWQ, M_PMOVSXDQ, M_PMOVZXBW, + M_PMOVZXBD, M_PMOVZXBQ, M_PMOVZXWD, M_PMOVZXWQ, M_PMOVZXDQ, M_PMULDQ, M_PMULLD, M_PTEST, M_ROUNDPS, M_ROUNDPD, M_ROUNDSS, M_ROUNDSD, M_PCMPEQQ, M_CRC32, M_PCMPESTRI, M_PCMPESTRM, + M_PCMPISTRI, M_PCMPISTRM, M_PCMPGTQ, M_PCLMULQDQ, M_AESDEC, M_AESDECLAST, M_AESENC, M_AESENCLAST, M_AESIMC, M_AESKEYGENASSIST, M_SHA1MSG1, M_SHA1MSG2, M_SHA1NEXTE, M_SHA1RNDS4, M_SHA256MSG1, M_SHA256MSG2, + M_SHA256RNDS2, M_VADDPS, M_VADDPD, M_VADDSS, M_VADDSD, M_VSUBPS, M_VSUBPD, M_VSUBSS, M_VSUBSD, M_VMULPS, M_VMULPD, M_VMULSS, M_VMULSD, M_VDIVPS, M_VDIVPD, M_VDIVSS, + M_VDIVSD, M_VSQRTPS, M_VSQRTPD, M_VSQRTSS, M_VSQRTSD, M_VRCPPS, M_VRCPSS, M_VRSQRTPS, M_VRSQRTSS, M_VMAXPS, M_VMAXPD, M_VMAXSS, M_VMAXSD, M_VMINPS, M_VMINPD, M_VMINSS, + M_VMINSD, M_VANDPS, M_VANDPD, M_VANDNPS, M_VANDNPD, M_VORPS, M_VORPD, M_VXORPS, M_VXORPD, M_VCMPPS, M_VCMPPD, M_VCMPSS, M_VCMPSD, M_VCOMISS, M_VCOMISD, M_VUCOMISS, + M_VUCOMISD, M_VSHUFPS, M_VSHUFPD, M_VUNPCKLPS, M_VUNPCKHPS, M_VUNPCKLPD, M_VUNPCKHPD, M_VBLENDPS, M_VBLENDPD, M_VBLENDVPS, M_VBLENDVPD, M_VDPPS, M_VDPPD, M_VROUNDPS, M_VROUNDPD, M_VROUNDSS, + M_VROUNDSD, M_VEXTRACTPS, M_VINSERTPS, M_VMOVAPS, M_VMOVUPS, M_VMOVAPD, M_VMOVUPD, M_VMOVSS, M_VMOVSD, M_VMOVDQA, M_VMOVDQU, M_VMOVQ, M_VMOVD, M_VMOVLPS, M_VMOVHPS, M_VMOVLPD, + M_VMOVHPD, M_VMOVLHPS, M_VMOVHLPS, M_VMOVMSKPS, M_VMOVMSKPD, M_VMOVNTPS, M_VMOVNTPD, M_VMOVNTDQ, M_VMOVNTDQA, M_VADDSUBPS, M_VADDSUBPD, M_VHADDPS, M_VHADDPD, M_VHSUBPS, M_VHSUBPD, M_VLDDQU, + M_VMOVDDUP, M_VMOVSLDUP, M_VMOVSHDUP, M_VPCMPESTRI, M_VPCMPESTRM, M_VPCMPISTRI, M_VPCMPISTRM, M_VPBROADCASTB, M_VPBROADCASTW, M_VPBROADCASTD, M_VPBROADCASTQ, M_VCVTPS2PD, M_VCVTPD2PS, M_VCVTSS2SD, M_VCVTSD2SS, M_VCVTPS2DQ, + M_VCVTPD2DQ, M_VCVTDQ2PS, M_VCVTDQ2PD, M_VCVTSS2SI, M_VCVTSD2SI, M_VCVTSI2SS, M_VCVTSI2SD, M_VCVTTPS2DQ, M_VCVTTPD2DQ, M_VCVTTSS2SI, M_VCVTTSD2SI, M_VPADDB, M_VPADDW, M_VPADDD, M_VPADDQ, M_VPSUBB, + M_VPSUBW, M_VPSUBD, M_VPSUBQ, M_VPMULLW, M_VPMULHW, M_VPMULHUW, M_VPMULUDQ, M_VPMADDWD, M_VPAND, M_VPANDN, M_VPOR, M_VPXOR, M_VPSLLW, M_VPSLLD, M_VPSLLQ, M_VPSRLW, + M_VPSRLD, M_VPSRLQ, M_VPSRAW, M_VPSRAD, M_VPCMPEQB, M_VPCMPEQW, M_VPCMPEQD, M_VPCMPEQQ, M_VPCMPGTB, M_VPCMPGTW, M_VPCMPGTD, M_VPCMPGTQ, M_VPACKSSWB, M_VPACKSSDW, M_VPACKUSWB, M_VPACKUSDW, + M_VPUNPCKLBW, M_VPUNPCKLWD, M_VPUNPCKLDQ, M_VPUNPCKLQDQ, M_VPUNPCKHBW, M_VPUNPCKHWD, M_VPUNPCKHDQ, M_VPUNPCKHQDQ, M_VPSHUFD, M_VPSHUFHW, M_VPSHUFLW, M_VPEXTRB, M_VPEXTRW, M_VPEXTRD, M_VPEXTRQ, M_VPINSRB, + M_VPINSRW, M_VPINSRD, M_VPINSRQ, M_VPMOVMSKB, M_VPTEST, M_VPSHUFB, M_VPHADDW, M_VPHADDD, M_VPHADDSW, M_VPHSUBW, M_VPHSUBD, M_VPHSUBSW, M_VPMADDUBSW, M_VPMULHRSW, M_VPSIGNB, M_VPSIGNW, + M_VPSIGND, M_VPABSB, M_VPABSW, M_VPABSD, M_VPALIGNR, M_VPBLENDW, M_VPBLENDVB, M_VMPSADBW, M_VPHMINPOSUW, M_VPMAXSB, M_VPMAXSD, M_VPMAXUW, M_VPMAXUD, M_VPMINSB, M_VPMINSD, M_VPMINUW, + M_VPMINUD, M_VPMOVSXBW, M_VPMOVSXBD, M_VPMOVSXBQ, M_VPMOVSXWD, M_VPMOVSXWQ, M_VPMOVSXDQ, M_VPMOVZXBW, M_VPMOVZXBD, M_VPMOVZXBQ, M_VPMOVZXWD, M_VPMOVZXWQ, M_VPMOVZXDQ, M_VPMULDQ, M_VPMULLD, M_VMASKMOVDQU, + M_VPCLMULQDQ, M_VAESDEC, M_VAESDECLAST, M_VAESENC, M_VAESENCLAST, M_VAESIMC, M_VAESKEYGENASSIST, M_VBROADCASTSS, M_VBROADCASTSD, M_VBROADCASTF128, M_VEXTRACTF128, M_VINSERTF128, M_VPERM2F128, M_VMASKMOVPS, M_VMASKMOVPD, M_VTESTPS, + M_VTESTPD, M_VZEROALL, M_VZEROUPPER, M_VBROADCASTI128, M_VEXTRACTI128, M_VINSERTI128, M_VPERM2I128, M_VPERMD, M_VPERMPS, M_VPERMQ, M_VPERMPD, M_VPBLENDD, M_VPSLLVD, M_VPSLLVQ, M_VPSRLVD, M_VPSRLVQ, + M_VPSRAVD, M_VPMASKMOVD, M_VPMASKMOVQ, M_VGATHERDPS, M_VGATHERDPD, M_VGATHERQPS, M_VGATHERQPD, M_VPGATHERDD, M_VPGATHERDQ, M_VPGATHERQD, M_VPGATHERQQ, M_VFMADD132PS, M_VFMADD213PS, M_VFMADD231PS, M_VFMADD132PD, M_VFMADD213PD, + M_VFMADD231PD, M_VFMADD132SS, M_VFMADD213SS, M_VFMADD231SS, M_VFMADD132SD, M_VFMADD213SD, M_VFMADD231SD, M_VFMSUB132PS, M_VFMSUB213PS, M_VFMSUB231PS, M_VFMSUB132PD, M_VFMSUB213PD, M_VFMSUB231PD, M_VFMSUB132SS, M_VFMSUB213SS, M_VFMSUB231SS, + M_VFMSUB132SD, M_VFMSUB213SD, M_VFMSUB231SD, M_VFNMADD132PS, M_VFNMADD213PS, M_VFNMADD231PS, M_VFNMADD132PD, M_VFNMADD213PD, M_VFNMADD231PD, M_VFNMADD132SS, M_VFNMADD213SS, M_VFNMADD231SS, M_VFNMADD132SD, M_VFNMADD213SD, M_VFNMADD231SD, M_VFNMSUB132PS, + M_VFNMSUB213PS, M_VFNMSUB231PS, M_VFNMSUB132PD, M_VFNMSUB213PD, M_VFNMSUB231PD, M_VFNMSUB132SS, M_VFNMSUB213SS, M_VFNMSUB231SS, M_VFNMSUB132SD, M_VFNMSUB213SD, M_VFNMSUB231SD, M_VFMADDSUB132PS, M_VFMADDSUB213PS, M_VFMADDSUB231PS, M_VFMADDSUB132PD, M_VFMADDSUB213PD, + M_VFMADDSUB231PD, M_VFMSUBADD132PS, M_VFMSUBADD213PS, M_VFMSUBADD231PS, M_VFMSUBADD132PD, M_VFMSUBADD213PD, M_VFMSUBADD231PD, M_VCVTPH2PS, M_VCVTPS2PH, M_VMOVDQA32, M_VMOVDQA64, M_VMOVDQU8, M_VMOVDQU16, M_VMOVDQU32, M_VMOVDQU64, M_VPBLENDMB, + M_VPBLENDMW, M_VPBLENDMD, M_VPBLENDMQ, M_VBLENDMPS, M_VBLENDMPD, M_VPCMPB, M_VPCMPUB, M_VPCMPW, M_VPCMPUW, M_VPCMPD, M_VPCMPUD, M_VPCMPQ, M_VPCMPUQ, M_VPTESTMB, M_VPTESTMW, M_VPTESTMD, + M_VPTESTMQ, M_VPTESTNMB, M_VPTESTNMW, M_VPTESTNMD, M_VPTESTNMQ, M_VPCOMPRESSD, M_VPCOMPRESSQ, M_VCOMPRESSPS, M_VCOMPRESSPD, M_VPEXPANDD, M_VPEXPANDQ, M_VEXPANDPS, M_VEXPANDPD, M_VPCONFLICTD, M_VPCONFLICTQ, M_VPLZCNTD, + M_VPLZCNTQ, M_VPERMI2B, M_VPERMI2W, M_VPERMI2D, M_VPERMI2Q, M_VPERMI2PS, M_VPERMI2PD, M_VPERMT2B, M_VPERMT2W, M_VPERMT2D, M_VPERMT2Q, M_VPERMT2PS, M_VPERMT2PD, M_VPERMB, M_VPERMW, M_VPMOVB2M, + M_VPMOVW2M, M_VPMOVD2M, M_VPMOVQ2M, M_VPMOVM2B, M_VPMOVM2W, M_VPMOVM2D, M_VPMOVM2Q, M_VPMOVQB, M_VPMOVSQB, M_VPMOVUSQB, M_VPMOVQW, M_VPMOVSQW, M_VPMOVUSQW, M_VPMOVQD, M_VPMOVSQD, M_VPMOVUSQD, + M_VPMOVDB, M_VPMOVSDB, M_VPMOVUSDB, M_VPMOVDW, M_VPMOVSDW, M_VPMOVUSDW, M_VPMOVWB, M_VPMOVSWB, M_VPMOVUSWB, M_VPROLD, M_VPROLQ, M_VPROLVD, M_VPROLVQ, M_VPRORD, M_VPRORQ, M_VPRORVD, + M_VPRORVQ, M_VPSCATTERDD, M_VPSCATTERDQ, M_VPSCATTERQD, M_VPSCATTERQQ, M_VSCATTERDPS, M_VSCATTERDPD, M_VSCATTERQPS, M_VSCATTERQPD, M_VPSRAVQ, M_VPSRAVW, M_VPSLLVW, M_VPSRLVW, M_VRANGEPS, M_VRANGEPD, M_VRANGESS, + M_VRANGESD, M_VREDUCEPS, M_VREDUCEPD, M_VREDUCESS, M_VREDUCESD, M_VRNDSCALEPS, M_VRNDSCALEPD, M_VRNDSCALESS, M_VRNDSCALESD, M_VRSQRT14PS, M_VRSQRT14PD, M_VRSQRT14SS, M_VRSQRT14SD, M_VRCP14PS, M_VRCP14PD, M_VRCP14SS, + M_VRCP14SD, M_VSCALEFPS, M_VSCALEFPD, M_VSCALEFSS, M_VSCALEFSD, M_VGETEXPPS, M_VGETEXPPD, M_VGETEXPSS, M_VGETEXPSD, M_VGETMANTPS, M_VGETMANTPD, M_VGETMANTSS, M_VGETMANTSD, M_VFIXUPIMMPS, M_VFIXUPIMMPD, M_VFIXUPIMMSS, + M_VFIXUPIMMSD, M_VFPCLASSPS, M_VFPCLASSPD, M_VFPCLASSSS, M_VFPCLASSSD, M_VALIGNQ, M_VALIGND, M_VDBPSADBW, M_VPTERNLOGD, M_VPTERNLOGQ, M_VPMULTISHIFTQB, M_KADDW, M_KADDB, M_KADDQ, M_KADDD, M_KANDW, + M_KANDB, M_KANDQ, M_KANDD, M_KANDNW, M_KANDNB, M_KANDNQ, M_KANDND, M_KMOVW, M_KMOVB, M_KMOVQ, M_KMOVD, M_KNOTW, M_KNOTB, M_KNOTQ, M_KNOTD, M_KORW, + M_KORB, M_KORQ, M_KORD, M_KORTESTW, M_KORTESTB, M_KORTESTQ, M_KORTESTD, M_KSHIFTLW, M_KSHIFTLB, M_KSHIFTLQ, M_KSHIFTLD, M_KSHIFTRW, M_KSHIFTRB, M_KSHIFTRQ, M_KSHIFTRD, M_KTESTW, + M_KTESTB, M_KTESTQ, M_KTESTD, M_KUNPCKBW, M_KUNPCKWD, M_KUNPCKDQ, M_KXNORW, M_KXNORB, M_KXNORQ, M_KXNORD, M_KXORW, M_KXORB, M_KXORQ, M_KXORD, M_FADD, M_FADDP, + M_FIADD, M_FSUB, M_FSUBP, M_FISUB, M_FSUBR, M_FSUBRP, M_FISUBR, M_FMUL, M_FMULP, M_FIMUL, M_FDIV, M_FDIVP, M_FIDIV, M_FDIVR, M_FDIVRP, M_FIDIVR, + M_FSQRT, M_FABS, M_FCHS, M_FPREM, M_FPREM1, M_FRNDINT, M_FSCALE, M_FXTRACT, M_FXAM, M_FLD, M_FILD, M_FBLD, M_FST, M_FSTP, M_FIST, M_FISTP, + M_FISTTP, M_FBSTP, M_FXCH, M_FCMOVB, M_FCMOVE, M_FCMOVBE, M_FCMOVU, M_FCMOVNB, M_FCMOVNE, M_FCMOVNBE, M_FCMOVNU, M_FCOM, M_FCOMP, M_FCOMPP, M_FICOM, M_FICOMP, + M_FCOMI, M_FCOMIP, M_FUCOMI, M_FUCOMIP, M_FUCOM, M_FUCOMP, M_FUCOMPP, M_FTST, M_FLDZ, M_FLD1, M_FLDPI, M_FLDL2T, M_FLDL2E, M_FLDLG2, M_FLDLN2, M_FSIN, + M_FCOS, M_FSINCOS, M_FPTAN, M_FPATAN, M_F2XM1, M_FYL2X, M_FYL2XP1, M_FINIT, M_FNINIT, M_FINCSTP, M_FDECSTP, M_FFREE, M_FFREEP, M_FNOP, M_FWAIT, M_FCLEX, + M_FNCLEX, M_FSTCW, M_FNSTCW, M_FLDCW, M_FSTENV, M_FNSTENV, M_FLDENV, M_FSAVE, M_FNSAVE, M_FRSTOR, M_FSTSW, M_FNSTSW, M_FXSAVE, M_FXSAVE64, M_FXRSTOR, M_FXRSTOR64, + M_LGDT, M_SGDT, M_LIDT, M_SIDT, M_LLDT, M_SLDT, M_LTR, M_STR, M_LMSW, M_SMSW, M_CLTS, M_ARPL, M_LAR, M_LSL, M_VERR, M_VERW, + M_INVD, M_WBINVD, M_INVLPG, M_INVPCID, M_RSM, M_RDMSR, M_WRMSR, M_VMCALL, M_VMLAUNCH, M_VMRESUME, M_VMXOFF, M_VMXON, M_VMCLEAR, M_VMPTRLD, M_VMPTRST, M_VMREAD, + M_VMWRITE, M_VMFUNC, M_INVEPT, M_INVVPID, M_ENCLS, M_ENCLU, M_ENCLV, M_RDPKRU, M_WRPKRU, M_INCSSPD, M_INCSSPQ, M_RDSSPD, M_RDSSPQ, M_SAVEPREVSSP, M_RSTORSSP, M_WRSSD, + M_WRSSQ, M_WRUSSD, M_WRUSSQ, M_SETSSBSY, M_CLRSSBSY, M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, M_XSAVEC64, M_XSAVES, + M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, M_CMPXCHG16B, M_XADD, + M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, MNEMONIC_COUNT }; @@ -407,9 +407,9 @@ struct Asm_amd64 { }; - static EncodeRun const raw_encode_runs[1194]; + static EncodeRun const raw_encode_runs[1192]; static u8 const raw_encode_forms[38320]; - static u8 const raw_clobber_table[19104]; + static u8 const raw_clobber_forms[38320]; StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; @@ -447,9 +447,10 @@ struct Asm_amd64 { Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; return Slice{ENCODE_FORMS+r.start, r.count}; } - Clobber clobber(/*Mnemonic*/ u16 m) const { - Clobber *c = cast(Clobber *)raw_clobber_table; - return c[m]; + Slice clobber_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms; + return Slice{CLOBBER_FORMS+r.start, r.count}; } u16 reg_class(/*Register*/ u16 r) const { return 0xFF00 & r; @@ -671,67 +672,67 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit("stosw"), str_lit("stosd"), str_lit("stosq"), str_lit("clc"), str_lit("stc"), str_lit("cmc"), str_lit("cld"), str_lit("std"), str_lit("cli"), str_lit("sti"), str_lit("lahf"), str_lit("sahf"), str_lit("pushf"), str_lit("pushfd"), str_lit("pushfq"), str_lit("popf"), str_lit("popfd"), str_lit("popfq"), str_lit("nop"), str_lit("hlt"), str_lit("wait"), str_lit("lock"), str_lit("ud0"), str_lit("ud1"), str_lit("ud2"), str_lit("cpuid"), str_lit("rdtsc"), str_lit("rdtscp"), str_lit("rdpmc"), str_lit("xgetbv"), str_lit("xsetbv"), str_lit("cbw"), str_lit("cwde"), str_lit("cdqe"), str_lit("cwd"), str_lit("cdq"), str_lit("cqo"), str_lit("andn"), str_lit("bextr"), str_lit("blsi"), str_lit("blsmsk"), str_lit("blsr"), str_lit("bzhi"), str_lit("pdep"), str_lit("pext"), str_lit("rorx"), str_lit("sarx"), str_lit("shlx"), - str_lit("shrx"), str_lit("mulx"), str_lit("adcx"), str_lit("adox"), str_lit("movaps"), str_lit("movups"), str_lit("movapd"), str_lit("movupd"), str_lit("movss"), str_lit("movsd"), str_lit("movdqa"), str_lit("movdqu"), str_lit("movq"), str_lit("movd"), str_lit("movlps"), str_lit("movhps"), - str_lit("movlpd"), str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), - str_lit("subss"), str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), - str_lit("rsqrtps"), str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), - str_lit("xorps"), str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("cmpsd"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), - str_lit("cvtps2pd"), str_lit("cvtpd2ps"), str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), - str_lit("paddb"), str_lit("paddw"), str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), - str_lit("pmullw"), str_lit("pmulhw"), str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), - str_lit("psrad"), str_lit("pcmpeqb"), str_lit("pcmpeqw"), str_lit("pcmpeqd"), str_lit("pcmpgtb"), str_lit("pcmpgtw"), str_lit("pcmpgtd"), str_lit("packsswb"), str_lit("packssdw"), str_lit("packuswb"), str_lit("punpcklbw"), str_lit("punpcklwd"), str_lit("punpckldq"), str_lit("punpcklqdq"), str_lit("punpckhbw"), str_lit("punpckhwd"), - str_lit("punpckhdq"), str_lit("punpckhqdq"), str_lit("pshufd"), str_lit("pshufhw"), str_lit("pshuflw"), str_lit("pshufw"), str_lit("pextrw"), str_lit("pinsrw"), str_lit("pmovmskb"), str_lit("pavgb"), str_lit("pavgw"), str_lit("pmaxub"), str_lit("pmaxsw"), str_lit("pminub"), str_lit("pminsw"), str_lit("psadbw"), - str_lit("maskmovdqu"), str_lit("lfence"), str_lit("sfence"), str_lit("mfence"), str_lit("pause"), str_lit("clflush"), str_lit("addsubps"), str_lit("addsubpd"), str_lit("haddps"), str_lit("haddpd"), str_lit("hsubps"), str_lit("hsubpd"), str_lit("movddup"), str_lit("movsldup"), str_lit("movshdup"), str_lit("lddqu"), - str_lit("pshufb"), str_lit("phaddw"), str_lit("phaddd"), str_lit("phaddsw"), str_lit("phsubw"), str_lit("phsubd"), str_lit("phsubsw"), str_lit("pmaddubsw"), str_lit("pmulhrsw"), str_lit("psignb"), str_lit("psignw"), str_lit("psignd"), str_lit("pabsb"), str_lit("pabsw"), str_lit("pabsd"), str_lit("palignr"), - str_lit("blendps"), str_lit("blendpd"), str_lit("blendvps"), str_lit("blendvpd"), str_lit("pblendw"), str_lit("pblendvb"), str_lit("dpps"), str_lit("dppd"), str_lit("extractps"), str_lit("insertps"), str_lit("mpsadbw"), str_lit("packusdw"), str_lit("pextrb"), str_lit("pextrd"), str_lit("pextrq"), str_lit("phminposuw"), - str_lit("pinsrb"), str_lit("pinsrd"), str_lit("pinsrq"), str_lit("pmaxsb"), str_lit("pmaxsd"), str_lit("pmaxuw"), str_lit("pmaxud"), str_lit("pminsb"), str_lit("pminsd"), str_lit("pminuw"), str_lit("pminud"), str_lit("pmovsxbw"), str_lit("pmovsxbd"), str_lit("pmovsxbq"), str_lit("pmovsxwd"), str_lit("pmovsxwq"), - str_lit("pmovsxdq"), str_lit("pmovzxbw"), str_lit("pmovzxbd"), str_lit("pmovzxbq"), str_lit("pmovzxwd"), str_lit("pmovzxwq"), str_lit("pmovzxdq"), str_lit("pmuldq"), str_lit("pmulld"), str_lit("ptest"), str_lit("roundps"), str_lit("roundpd"), str_lit("roundss"), str_lit("roundsd"), str_lit("pcmpeqq"), str_lit("crc32"), - str_lit("pcmpestri"), str_lit("pcmpestrm"), str_lit("pcmpistri"), str_lit("pcmpistrm"), str_lit("pcmpgtq"), str_lit("pclmulqdq"), str_lit("aesdec"), str_lit("aesdeclast"), str_lit("aesenc"), str_lit("aesenclast"), str_lit("aesimc"), str_lit("aeskeygenassist"), str_lit("sha1msg1"), str_lit("sha1msg2"), str_lit("sha1nexte"), str_lit("sha1rnds4"), - str_lit("sha256msg1"), str_lit("sha256msg2"), str_lit("sha256rnds2"), str_lit("vaddps"), str_lit("vaddpd"), str_lit("vaddss"), str_lit("vaddsd"), str_lit("vsubps"), str_lit("vsubpd"), str_lit("vsubss"), str_lit("vsubsd"), str_lit("vmulps"), str_lit("vmulpd"), str_lit("vmulss"), str_lit("vmulsd"), str_lit("vdivps"), - str_lit("vdivpd"), str_lit("vdivss"), str_lit("vdivsd"), str_lit("vsqrtps"), str_lit("vsqrtpd"), str_lit("vsqrtss"), str_lit("vsqrtsd"), str_lit("vrcpps"), str_lit("vrcpss"), str_lit("vrsqrtps"), str_lit("vrsqrtss"), str_lit("vmaxps"), str_lit("vmaxpd"), str_lit("vmaxss"), str_lit("vmaxsd"), str_lit("vminps"), - str_lit("vminpd"), str_lit("vminss"), str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), - str_lit("vcomisd"), str_lit("vucomiss"), str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), - str_lit("vroundpd"), str_lit("vroundss"), str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), - str_lit("vmovhps"), str_lit("vmovlpd"), str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vaddsubps"), str_lit("vaddsubpd"), str_lit("vhaddps"), str_lit("vhaddpd"), str_lit("vhsubps"), - str_lit("vhsubpd"), str_lit("vlddqu"), str_lit("vmovddup"), str_lit("vmovsldup"), str_lit("vmovshdup"), str_lit("vpcmpestri"), str_lit("vpcmpestrm"), str_lit("vpcmpistri"), str_lit("vpcmpistrm"), str_lit("vpbroadcastb"), str_lit("vpbroadcastw"), str_lit("vpbroadcastd"), str_lit("vpbroadcastq"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), - str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), - str_lit("vpaddq"), str_lit("vpsubb"), str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), - str_lit("vpsllq"), str_lit("vpsrlw"), str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), - str_lit("vpackuswb"), str_lit("vpackusdw"), str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), - str_lit("vpextrq"), str_lit("vpinsrb"), str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), - str_lit("vpsignb"), str_lit("vpsignw"), str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), - str_lit("vpminsd"), str_lit("vpminuw"), str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), - str_lit("vpmulld"), str_lit("vmaskmovdqu"), str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), - str_lit("vmaskmovpd"), str_lit("vtestps"), str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), - str_lit("vpsrlvd"), str_lit("vpsrlvq"), str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), - str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), - str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), - str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), - str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), - str_lit("vmovdqu64"), str_lit("vpblendmb"), str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), - str_lit("vptestmw"), str_lit("vptestmd"), str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), - str_lit("vpconflictq"), str_lit("vplzcntd"), str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), - str_lit("vpermw"), str_lit("vpmovb2m"), str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), - str_lit("vpmovsqd"), str_lit("vpmovusqd"), str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), - str_lit("vprorq"), str_lit("vprorvd"), str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), - str_lit("vrangepd"), str_lit("vrangess"), str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), - str_lit("vrcp14pd"), str_lit("vrcp14ss"), str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), - str_lit("vfixupimmpd"), str_lit("vfixupimmss"), str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), - str_lit("kaddd"), str_lit("kandw"), str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), - str_lit("knotd"), str_lit("korw"), str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), - str_lit("kshiftrd"), str_lit("ktestw"), str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), - str_lit("fadd"), str_lit("faddp"), str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), - str_lit("fdivrp"), str_lit("fidivr"), str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), - str_lit("fist"), str_lit("fistp"), str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), - str_lit("ficom"), str_lit("ficomp"), str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), - str_lit("fldln2"), str_lit("fsin"), str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), - str_lit("fwait"), str_lit("fclex"), str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), - str_lit("fxrstor"), str_lit("fxrstor64"), str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), - str_lit("verr"), str_lit("verw"), str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), - str_lit("vmptrst"), str_lit("vmread"), str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), - str_lit("rstorssp"), str_lit("wrssd"), str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), - str_lit("xsavec64"), str_lit("xsaves"), str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), - str_lit("cmpxchg16b"), str_lit("xadd"), str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), + str_lit("shrx"), str_lit("mulx"), str_lit("adcx"), str_lit("adox"), str_lit("movaps"), str_lit("movups"), str_lit("movapd"), str_lit("movupd"), str_lit("movss"), str_lit("movdqa"), str_lit("movdqu"), str_lit("movq"), str_lit("movd"), str_lit("movlps"), str_lit("movhps"), str_lit("movlpd"), + str_lit("movhpd"), str_lit("movlhps"), str_lit("movhlps"), str_lit("movmskps"), str_lit("movmskpd"), str_lit("movntps"), str_lit("movntpd"), str_lit("movntdq"), str_lit("movntdqa"), str_lit("addps"), str_lit("addpd"), str_lit("addss"), str_lit("addsd"), str_lit("subps"), str_lit("subpd"), str_lit("subss"), + str_lit("subsd"), str_lit("mulps"), str_lit("mulpd"), str_lit("mulss"), str_lit("mulsd"), str_lit("divps"), str_lit("divpd"), str_lit("divss"), str_lit("divsd"), str_lit("sqrtps"), str_lit("sqrtpd"), str_lit("sqrtss"), str_lit("sqrtsd"), str_lit("rcpps"), str_lit("rcpss"), str_lit("rsqrtps"), + str_lit("rsqrtss"), str_lit("maxps"), str_lit("maxpd"), str_lit("maxss"), str_lit("maxsd"), str_lit("minps"), str_lit("minpd"), str_lit("minss"), str_lit("minsd"), str_lit("andps"), str_lit("andpd"), str_lit("andnps"), str_lit("andnpd"), str_lit("orps"), str_lit("orpd"), str_lit("xorps"), + str_lit("xorpd"), str_lit("cmpps"), str_lit("cmppd"), str_lit("cmpss"), str_lit("comiss"), str_lit("comisd"), str_lit("ucomiss"), str_lit("ucomisd"), str_lit("shufps"), str_lit("shufpd"), str_lit("unpcklps"), str_lit("unpckhps"), str_lit("unpcklpd"), str_lit("unpckhpd"), str_lit("cvtps2pd"), str_lit("cvtpd2ps"), + str_lit("cvtss2sd"), str_lit("cvtsd2ss"), str_lit("cvtps2dq"), str_lit("cvtpd2dq"), str_lit("cvtdq2ps"), str_lit("cvtdq2pd"), str_lit("cvtss2si"), str_lit("cvtsd2si"), str_lit("cvtsi2ss"), str_lit("cvtsi2sd"), str_lit("cvttps2dq"), str_lit("cvttpd2dq"), str_lit("cvttss2si"), str_lit("cvttsd2si"), str_lit("paddb"), str_lit("paddw"), + str_lit("paddd"), str_lit("paddq"), str_lit("psubb"), str_lit("psubw"), str_lit("psubd"), str_lit("psubq"), str_lit("paddsb"), str_lit("paddsw"), str_lit("paddusb"), str_lit("paddusw"), str_lit("psubsb"), str_lit("psubsw"), str_lit("psubusb"), str_lit("psubusw"), str_lit("pmullw"), str_lit("pmulhw"), + str_lit("pmulhuw"), str_lit("pmuludq"), str_lit("pmaddwd"), str_lit("pand"), str_lit("pandn"), str_lit("por"), str_lit("pxor"), str_lit("psllw"), str_lit("pslld"), str_lit("psllq"), str_lit("psrlw"), str_lit("psrld"), str_lit("psrlq"), str_lit("psraw"), str_lit("psrad"), str_lit("pcmpeqb"), + str_lit("pcmpeqw"), str_lit("pcmpeqd"), str_lit("pcmpgtb"), str_lit("pcmpgtw"), str_lit("pcmpgtd"), str_lit("packsswb"), str_lit("packssdw"), str_lit("packuswb"), str_lit("punpcklbw"), str_lit("punpcklwd"), str_lit("punpckldq"), str_lit("punpcklqdq"), str_lit("punpckhbw"), str_lit("punpckhwd"), str_lit("punpckhdq"), str_lit("punpckhqdq"), + str_lit("pshufd"), str_lit("pshufhw"), str_lit("pshuflw"), str_lit("pshufw"), str_lit("pextrw"), str_lit("pinsrw"), str_lit("pmovmskb"), str_lit("pavgb"), str_lit("pavgw"), str_lit("pmaxub"), str_lit("pmaxsw"), str_lit("pminub"), str_lit("pminsw"), str_lit("psadbw"), str_lit("maskmovdqu"), str_lit("lfence"), + str_lit("sfence"), str_lit("mfence"), str_lit("pause"), str_lit("clflush"), str_lit("addsubps"), str_lit("addsubpd"), str_lit("haddps"), str_lit("haddpd"), str_lit("hsubps"), str_lit("hsubpd"), str_lit("movddup"), str_lit("movsldup"), str_lit("movshdup"), str_lit("lddqu"), str_lit("pshufb"), str_lit("phaddw"), + str_lit("phaddd"), str_lit("phaddsw"), str_lit("phsubw"), str_lit("phsubd"), str_lit("phsubsw"), str_lit("pmaddubsw"), str_lit("pmulhrsw"), str_lit("psignb"), str_lit("psignw"), str_lit("psignd"), str_lit("pabsb"), str_lit("pabsw"), str_lit("pabsd"), str_lit("palignr"), str_lit("blendps"), str_lit("blendpd"), + str_lit("blendvps"), str_lit("blendvpd"), str_lit("pblendw"), str_lit("pblendvb"), str_lit("dpps"), str_lit("dppd"), str_lit("extractps"), str_lit("insertps"), str_lit("mpsadbw"), str_lit("packusdw"), str_lit("pextrb"), str_lit("pextrd"), str_lit("pextrq"), str_lit("phminposuw"), str_lit("pinsrb"), str_lit("pinsrd"), + str_lit("pinsrq"), str_lit("pmaxsb"), str_lit("pmaxsd"), str_lit("pmaxuw"), str_lit("pmaxud"), str_lit("pminsb"), str_lit("pminsd"), str_lit("pminuw"), str_lit("pminud"), str_lit("pmovsxbw"), str_lit("pmovsxbd"), str_lit("pmovsxbq"), str_lit("pmovsxwd"), str_lit("pmovsxwq"), str_lit("pmovsxdq"), str_lit("pmovzxbw"), + str_lit("pmovzxbd"), str_lit("pmovzxbq"), str_lit("pmovzxwd"), str_lit("pmovzxwq"), str_lit("pmovzxdq"), str_lit("pmuldq"), str_lit("pmulld"), str_lit("ptest"), str_lit("roundps"), str_lit("roundpd"), str_lit("roundss"), str_lit("roundsd"), str_lit("pcmpeqq"), str_lit("crc32"), str_lit("pcmpestri"), str_lit("pcmpestrm"), + str_lit("pcmpistri"), str_lit("pcmpistrm"), str_lit("pcmpgtq"), str_lit("pclmulqdq"), str_lit("aesdec"), str_lit("aesdeclast"), str_lit("aesenc"), str_lit("aesenclast"), str_lit("aesimc"), str_lit("aeskeygenassist"), str_lit("sha1msg1"), str_lit("sha1msg2"), str_lit("sha1nexte"), str_lit("sha1rnds4"), str_lit("sha256msg1"), str_lit("sha256msg2"), + str_lit("sha256rnds2"), str_lit("vaddps"), str_lit("vaddpd"), str_lit("vaddss"), str_lit("vaddsd"), str_lit("vsubps"), str_lit("vsubpd"), str_lit("vsubss"), str_lit("vsubsd"), str_lit("vmulps"), str_lit("vmulpd"), str_lit("vmulss"), str_lit("vmulsd"), str_lit("vdivps"), str_lit("vdivpd"), str_lit("vdivss"), + str_lit("vdivsd"), str_lit("vsqrtps"), str_lit("vsqrtpd"), str_lit("vsqrtss"), str_lit("vsqrtsd"), str_lit("vrcpps"), str_lit("vrcpss"), str_lit("vrsqrtps"), str_lit("vrsqrtss"), str_lit("vmaxps"), str_lit("vmaxpd"), str_lit("vmaxss"), str_lit("vmaxsd"), str_lit("vminps"), str_lit("vminpd"), str_lit("vminss"), + str_lit("vminsd"), str_lit("vandps"), str_lit("vandpd"), str_lit("vandnps"), str_lit("vandnpd"), str_lit("vorps"), str_lit("vorpd"), str_lit("vxorps"), str_lit("vxorpd"), str_lit("vcmpps"), str_lit("vcmppd"), str_lit("vcmpss"), str_lit("vcmpsd"), str_lit("vcomiss"), str_lit("vcomisd"), str_lit("vucomiss"), + str_lit("vucomisd"), str_lit("vshufps"), str_lit("vshufpd"), str_lit("vunpcklps"), str_lit("vunpckhps"), str_lit("vunpcklpd"), str_lit("vunpckhpd"), str_lit("vblendps"), str_lit("vblendpd"), str_lit("vblendvps"), str_lit("vblendvpd"), str_lit("vdpps"), str_lit("vdppd"), str_lit("vroundps"), str_lit("vroundpd"), str_lit("vroundss"), + str_lit("vroundsd"), str_lit("vextractps"), str_lit("vinsertps"), str_lit("vmovaps"), str_lit("vmovups"), str_lit("vmovapd"), str_lit("vmovupd"), str_lit("vmovss"), str_lit("vmovsd"), str_lit("vmovdqa"), str_lit("vmovdqu"), str_lit("vmovq"), str_lit("vmovd"), str_lit("vmovlps"), str_lit("vmovhps"), str_lit("vmovlpd"), + str_lit("vmovhpd"), str_lit("vmovlhps"), str_lit("vmovhlps"), str_lit("vmovmskps"), str_lit("vmovmskpd"), str_lit("vmovntps"), str_lit("vmovntpd"), str_lit("vmovntdq"), str_lit("vmovntdqa"), str_lit("vaddsubps"), str_lit("vaddsubpd"), str_lit("vhaddps"), str_lit("vhaddpd"), str_lit("vhsubps"), str_lit("vhsubpd"), str_lit("vlddqu"), + str_lit("vmovddup"), str_lit("vmovsldup"), str_lit("vmovshdup"), str_lit("vpcmpestri"), str_lit("vpcmpestrm"), str_lit("vpcmpistri"), str_lit("vpcmpistrm"), str_lit("vpbroadcastb"), str_lit("vpbroadcastw"), str_lit("vpbroadcastd"), str_lit("vpbroadcastq"), str_lit("vcvtps2pd"), str_lit("vcvtpd2ps"), str_lit("vcvtss2sd"), str_lit("vcvtsd2ss"), str_lit("vcvtps2dq"), + str_lit("vcvtpd2dq"), str_lit("vcvtdq2ps"), str_lit("vcvtdq2pd"), str_lit("vcvtss2si"), str_lit("vcvtsd2si"), str_lit("vcvtsi2ss"), str_lit("vcvtsi2sd"), str_lit("vcvttps2dq"), str_lit("vcvttpd2dq"), str_lit("vcvttss2si"), str_lit("vcvttsd2si"), str_lit("vpaddb"), str_lit("vpaddw"), str_lit("vpaddd"), str_lit("vpaddq"), str_lit("vpsubb"), + str_lit("vpsubw"), str_lit("vpsubd"), str_lit("vpsubq"), str_lit("vpmullw"), str_lit("vpmulhw"), str_lit("vpmulhuw"), str_lit("vpmuludq"), str_lit("vpmaddwd"), str_lit("vpand"), str_lit("vpandn"), str_lit("vpor"), str_lit("vpxor"), str_lit("vpsllw"), str_lit("vpslld"), str_lit("vpsllq"), str_lit("vpsrlw"), + str_lit("vpsrld"), str_lit("vpsrlq"), str_lit("vpsraw"), str_lit("vpsrad"), str_lit("vpcmpeqb"), str_lit("vpcmpeqw"), str_lit("vpcmpeqd"), str_lit("vpcmpeqq"), str_lit("vpcmpgtb"), str_lit("vpcmpgtw"), str_lit("vpcmpgtd"), str_lit("vpcmpgtq"), str_lit("vpacksswb"), str_lit("vpackssdw"), str_lit("vpackuswb"), str_lit("vpackusdw"), + str_lit("vpunpcklbw"), str_lit("vpunpcklwd"), str_lit("vpunpckldq"), str_lit("vpunpcklqdq"), str_lit("vpunpckhbw"), str_lit("vpunpckhwd"), str_lit("vpunpckhdq"), str_lit("vpunpckhqdq"), str_lit("vpshufd"), str_lit("vpshufhw"), str_lit("vpshuflw"), str_lit("vpextrb"), str_lit("vpextrw"), str_lit("vpextrd"), str_lit("vpextrq"), str_lit("vpinsrb"), + str_lit("vpinsrw"), str_lit("vpinsrd"), str_lit("vpinsrq"), str_lit("vpmovmskb"), str_lit("vptest"), str_lit("vpshufb"), str_lit("vphaddw"), str_lit("vphaddd"), str_lit("vphaddsw"), str_lit("vphsubw"), str_lit("vphsubd"), str_lit("vphsubsw"), str_lit("vpmaddubsw"), str_lit("vpmulhrsw"), str_lit("vpsignb"), str_lit("vpsignw"), + str_lit("vpsignd"), str_lit("vpabsb"), str_lit("vpabsw"), str_lit("vpabsd"), str_lit("vpalignr"), str_lit("vpblendw"), str_lit("vpblendvb"), str_lit("vmpsadbw"), str_lit("vphminposuw"), str_lit("vpmaxsb"), str_lit("vpmaxsd"), str_lit("vpmaxuw"), str_lit("vpmaxud"), str_lit("vpminsb"), str_lit("vpminsd"), str_lit("vpminuw"), + str_lit("vpminud"), str_lit("vpmovsxbw"), str_lit("vpmovsxbd"), str_lit("vpmovsxbq"), str_lit("vpmovsxwd"), str_lit("vpmovsxwq"), str_lit("vpmovsxdq"), str_lit("vpmovzxbw"), str_lit("vpmovzxbd"), str_lit("vpmovzxbq"), str_lit("vpmovzxwd"), str_lit("vpmovzxwq"), str_lit("vpmovzxdq"), str_lit("vpmuldq"), str_lit("vpmulld"), str_lit("vmaskmovdqu"), + str_lit("vpclmulqdq"), str_lit("vaesdec"), str_lit("vaesdeclast"), str_lit("vaesenc"), str_lit("vaesenclast"), str_lit("vaesimc"), str_lit("vaeskeygenassist"), str_lit("vbroadcastss"), str_lit("vbroadcastsd"), str_lit("vbroadcastf128"), str_lit("vextractf128"), str_lit("vinsertf128"), str_lit("vperm2f128"), str_lit("vmaskmovps"), str_lit("vmaskmovpd"), str_lit("vtestps"), + str_lit("vtestpd"), str_lit("vzeroall"), str_lit("vzeroupper"), str_lit("vbroadcasti128"), str_lit("vextracti128"), str_lit("vinserti128"), str_lit("vperm2i128"), str_lit("vpermd"), str_lit("vpermps"), str_lit("vpermq"), str_lit("vpermpd"), str_lit("vpblendd"), str_lit("vpsllvd"), str_lit("vpsllvq"), str_lit("vpsrlvd"), str_lit("vpsrlvq"), + str_lit("vpsravd"), str_lit("vpmaskmovd"), str_lit("vpmaskmovq"), str_lit("vgatherdps"), str_lit("vgatherdpd"), str_lit("vgatherqps"), str_lit("vgatherqpd"), str_lit("vpgatherdd"), str_lit("vpgatherdq"), str_lit("vpgatherqd"), str_lit("vpgatherqq"), str_lit("vfmadd132ps"), str_lit("vfmadd213ps"), str_lit("vfmadd231ps"), str_lit("vfmadd132pd"), str_lit("vfmadd213pd"), + str_lit("vfmadd231pd"), str_lit("vfmadd132ss"), str_lit("vfmadd213ss"), str_lit("vfmadd231ss"), str_lit("vfmadd132sd"), str_lit("vfmadd213sd"), str_lit("vfmadd231sd"), str_lit("vfmsub132ps"), str_lit("vfmsub213ps"), str_lit("vfmsub231ps"), str_lit("vfmsub132pd"), str_lit("vfmsub213pd"), str_lit("vfmsub231pd"), str_lit("vfmsub132ss"), str_lit("vfmsub213ss"), str_lit("vfmsub231ss"), + str_lit("vfmsub132sd"), str_lit("vfmsub213sd"), str_lit("vfmsub231sd"), str_lit("vfnmadd132ps"), str_lit("vfnmadd213ps"), str_lit("vfnmadd231ps"), str_lit("vfnmadd132pd"), str_lit("vfnmadd213pd"), str_lit("vfnmadd231pd"), str_lit("vfnmadd132ss"), str_lit("vfnmadd213ss"), str_lit("vfnmadd231ss"), str_lit("vfnmadd132sd"), str_lit("vfnmadd213sd"), str_lit("vfnmadd231sd"), str_lit("vfnmsub132ps"), + str_lit("vfnmsub213ps"), str_lit("vfnmsub231ps"), str_lit("vfnmsub132pd"), str_lit("vfnmsub213pd"), str_lit("vfnmsub231pd"), str_lit("vfnmsub132ss"), str_lit("vfnmsub213ss"), str_lit("vfnmsub231ss"), str_lit("vfnmsub132sd"), str_lit("vfnmsub213sd"), str_lit("vfnmsub231sd"), str_lit("vfmaddsub132ps"), str_lit("vfmaddsub213ps"), str_lit("vfmaddsub231ps"), str_lit("vfmaddsub132pd"), str_lit("vfmaddsub213pd"), + str_lit("vfmaddsub231pd"), str_lit("vfmsubadd132ps"), str_lit("vfmsubadd213ps"), str_lit("vfmsubadd231ps"), str_lit("vfmsubadd132pd"), str_lit("vfmsubadd213pd"), str_lit("vfmsubadd231pd"), str_lit("vcvtph2ps"), str_lit("vcvtps2ph"), str_lit("vmovdqa32"), str_lit("vmovdqa64"), str_lit("vmovdqu8"), str_lit("vmovdqu16"), str_lit("vmovdqu32"), str_lit("vmovdqu64"), str_lit("vpblendmb"), + str_lit("vpblendmw"), str_lit("vpblendmd"), str_lit("vpblendmq"), str_lit("vblendmps"), str_lit("vblendmpd"), str_lit("vpcmpb"), str_lit("vpcmpub"), str_lit("vpcmpw"), str_lit("vpcmpuw"), str_lit("vpcmpd"), str_lit("vpcmpud"), str_lit("vpcmpq"), str_lit("vpcmpuq"), str_lit("vptestmb"), str_lit("vptestmw"), str_lit("vptestmd"), + str_lit("vptestmq"), str_lit("vptestnmb"), str_lit("vptestnmw"), str_lit("vptestnmd"), str_lit("vptestnmq"), str_lit("vpcompressd"), str_lit("vpcompressq"), str_lit("vcompressps"), str_lit("vcompresspd"), str_lit("vpexpandd"), str_lit("vpexpandq"), str_lit("vexpandps"), str_lit("vexpandpd"), str_lit("vpconflictd"), str_lit("vpconflictq"), str_lit("vplzcntd"), + str_lit("vplzcntq"), str_lit("vpermi2b"), str_lit("vpermi2w"), str_lit("vpermi2d"), str_lit("vpermi2q"), str_lit("vpermi2ps"), str_lit("vpermi2pd"), str_lit("vpermt2b"), str_lit("vpermt2w"), str_lit("vpermt2d"), str_lit("vpermt2q"), str_lit("vpermt2ps"), str_lit("vpermt2pd"), str_lit("vpermb"), str_lit("vpermw"), str_lit("vpmovb2m"), + str_lit("vpmovw2m"), str_lit("vpmovd2m"), str_lit("vpmovq2m"), str_lit("vpmovm2b"), str_lit("vpmovm2w"), str_lit("vpmovm2d"), str_lit("vpmovm2q"), str_lit("vpmovqb"), str_lit("vpmovsqb"), str_lit("vpmovusqb"), str_lit("vpmovqw"), str_lit("vpmovsqw"), str_lit("vpmovusqw"), str_lit("vpmovqd"), str_lit("vpmovsqd"), str_lit("vpmovusqd"), + str_lit("vpmovdb"), str_lit("vpmovsdb"), str_lit("vpmovusdb"), str_lit("vpmovdw"), str_lit("vpmovsdw"), str_lit("vpmovusdw"), str_lit("vpmovwb"), str_lit("vpmovswb"), str_lit("vpmovuswb"), str_lit("vprold"), str_lit("vprolq"), str_lit("vprolvd"), str_lit("vprolvq"), str_lit("vprord"), str_lit("vprorq"), str_lit("vprorvd"), + str_lit("vprorvq"), str_lit("vpscatterdd"), str_lit("vpscatterdq"), str_lit("vpscatterqd"), str_lit("vpscatterqq"), str_lit("vscatterdps"), str_lit("vscatterdpd"), str_lit("vscatterqps"), str_lit("vscatterqpd"), str_lit("vpsravq"), str_lit("vpsravw"), str_lit("vpsllvw"), str_lit("vpsrlvw"), str_lit("vrangeps"), str_lit("vrangepd"), str_lit("vrangess"), + str_lit("vrangesd"), str_lit("vreduceps"), str_lit("vreducepd"), str_lit("vreducess"), str_lit("vreducesd"), str_lit("vrndscaleps"), str_lit("vrndscalepd"), str_lit("vrndscaless"), str_lit("vrndscalesd"), str_lit("vrsqrt14ps"), str_lit("vrsqrt14pd"), str_lit("vrsqrt14ss"), str_lit("vrsqrt14sd"), str_lit("vrcp14ps"), str_lit("vrcp14pd"), str_lit("vrcp14ss"), + str_lit("vrcp14sd"), str_lit("vscalefps"), str_lit("vscalefpd"), str_lit("vscalefss"), str_lit("vscalefsd"), str_lit("vgetexpps"), str_lit("vgetexppd"), str_lit("vgetexpss"), str_lit("vgetexpsd"), str_lit("vgetmantps"), str_lit("vgetmantpd"), str_lit("vgetmantss"), str_lit("vgetmantsd"), str_lit("vfixupimmps"), str_lit("vfixupimmpd"), str_lit("vfixupimmss"), + str_lit("vfixupimmsd"), str_lit("vfpclassps"), str_lit("vfpclasspd"), str_lit("vfpclassss"), str_lit("vfpclasssd"), str_lit("valignq"), str_lit("valignd"), str_lit("vdbpsadbw"), str_lit("vpternlogd"), str_lit("vpternlogq"), str_lit("vpmultishiftqb"), str_lit("kaddw"), str_lit("kaddb"), str_lit("kaddq"), str_lit("kaddd"), str_lit("kandw"), + str_lit("kandb"), str_lit("kandq"), str_lit("kandd"), str_lit("kandnw"), str_lit("kandnb"), str_lit("kandnq"), str_lit("kandnd"), str_lit("kmovw"), str_lit("kmovb"), str_lit("kmovq"), str_lit("kmovd"), str_lit("knotw"), str_lit("knotb"), str_lit("knotq"), str_lit("knotd"), str_lit("korw"), + str_lit("korb"), str_lit("korq"), str_lit("kord"), str_lit("kortestw"), str_lit("kortestb"), str_lit("kortestq"), str_lit("kortestd"), str_lit("kshiftlw"), str_lit("kshiftlb"), str_lit("kshiftlq"), str_lit("kshiftld"), str_lit("kshiftrw"), str_lit("kshiftrb"), str_lit("kshiftrq"), str_lit("kshiftrd"), str_lit("ktestw"), + str_lit("ktestb"), str_lit("ktestq"), str_lit("ktestd"), str_lit("kunpckbw"), str_lit("kunpckwd"), str_lit("kunpckdq"), str_lit("kxnorw"), str_lit("kxnorb"), str_lit("kxnorq"), str_lit("kxnord"), str_lit("kxorw"), str_lit("kxorb"), str_lit("kxorq"), str_lit("kxord"), str_lit("fadd"), str_lit("faddp"), + str_lit("fiadd"), str_lit("fsub"), str_lit("fsubp"), str_lit("fisub"), str_lit("fsubr"), str_lit("fsubrp"), str_lit("fisubr"), str_lit("fmul"), str_lit("fmulp"), str_lit("fimul"), str_lit("fdiv"), str_lit("fdivp"), str_lit("fidiv"), str_lit("fdivr"), str_lit("fdivrp"), str_lit("fidivr"), + str_lit("fsqrt"), str_lit("fabs"), str_lit("fchs"), str_lit("fprem"), str_lit("fprem1"), str_lit("frndint"), str_lit("fscale"), str_lit("fxtract"), str_lit("fxam"), str_lit("fld"), str_lit("fild"), str_lit("fbld"), str_lit("fst"), str_lit("fstp"), str_lit("fist"), str_lit("fistp"), + str_lit("fisttp"), str_lit("fbstp"), str_lit("fxch"), str_lit("fcmovb"), str_lit("fcmove"), str_lit("fcmovbe"), str_lit("fcmovu"), str_lit("fcmovnb"), str_lit("fcmovne"), str_lit("fcmovnbe"), str_lit("fcmovnu"), str_lit("fcom"), str_lit("fcomp"), str_lit("fcompp"), str_lit("ficom"), str_lit("ficomp"), + str_lit("fcomi"), str_lit("fcomip"), str_lit("fucomi"), str_lit("fucomip"), str_lit("fucom"), str_lit("fucomp"), str_lit("fucompp"), str_lit("ftst"), str_lit("fldz"), str_lit("fld1"), str_lit("fldpi"), str_lit("fldl2t"), str_lit("fldl2e"), str_lit("fldlg2"), str_lit("fldln2"), str_lit("fsin"), + str_lit("fcos"), str_lit("fsincos"), str_lit("fptan"), str_lit("fpatan"), str_lit("f2xm1"), str_lit("fyl2x"), str_lit("fyl2xp1"), str_lit("finit"), str_lit("fninit"), str_lit("fincstp"), str_lit("fdecstp"), str_lit("ffree"), str_lit("ffreep"), str_lit("fnop"), str_lit("fwait"), str_lit("fclex"), + str_lit("fnclex"), str_lit("fstcw"), str_lit("fnstcw"), str_lit("fldcw"), str_lit("fstenv"), str_lit("fnstenv"), str_lit("fldenv"), str_lit("fsave"), str_lit("fnsave"), str_lit("frstor"), str_lit("fstsw"), str_lit("fnstsw"), str_lit("fxsave"), str_lit("fxsave64"), str_lit("fxrstor"), str_lit("fxrstor64"), + str_lit("lgdt"), str_lit("sgdt"), str_lit("lidt"), str_lit("sidt"), str_lit("lldt"), str_lit("sldt"), str_lit("ltr"), str_lit("str"), str_lit("lmsw"), str_lit("smsw"), str_lit("clts"), str_lit("arpl"), str_lit("lar"), str_lit("lsl"), str_lit("verr"), str_lit("verw"), + str_lit("invd"), str_lit("wbinvd"), str_lit("invlpg"), str_lit("invpcid"), str_lit("rsm"), str_lit("rdmsr"), str_lit("wrmsr"), str_lit("vmcall"), str_lit("vmlaunch"), str_lit("vmresume"), str_lit("vmxoff"), str_lit("vmxon"), str_lit("vmclear"), str_lit("vmptrld"), str_lit("vmptrst"), str_lit("vmread"), + str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), str_lit("wrssd"), + str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), str_lit("xsaves"), + str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"), + str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), }; String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] { str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"), @@ -768,7 +769,7 @@ String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] { str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"), str_lit("st6"), str_lit("st7"), str_lit("rip"), }; -Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1194] = { +Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1192] = { { 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13}, { 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12}, { 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2}, @@ -778,72 +779,72 @@ Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1194] = { { 512, 1}, { 513, 1}, { 514, 1}, { 515, 1}, { 516, 1}, { 517, 1}, { 518, 1}, { 519, 1}, { 520, 1}, { 521, 1}, { 522, 1}, { 523, 1}, { 524, 1}, { 525, 1}, { 526, 1}, { 527, 1}, { 528, 1}, { 529, 1}, { 530, 1}, { 531, 1}, { 532, 1}, { 533, 1}, { 534, 1}, { 535, 1}, { 536, 1}, { 537, 1}, { 538, 1}, { 539, 1}, { 540, 3}, { 543, 3}, { 546, 3}, { 549, 3}, { 552, 3}, { 555, 3}, { 558, 3}, { 561, 3}, { 564, 3}, { 567, 3}, { 570, 3}, { 573, 3}, { 576, 3}, { 579, 3}, { 582, 3}, { 585, 3}, { 588, 3}, { 591, 3}, { 594, 3}, { 597, 3}, - { 600, 3}, { 603, 3}, { 606, 3}, { 609, 3}, { 612, 3}, { 615, 3}, { 618, 3}, { 621, 3}, { 624, 3}, { 627, 3}, { 630, 1}, { 631, 1}, { 632, 1}, { 633, 1}, { 634, 1}, { 635, 1}, - { 636, 1}, { 637, 1}, { 638, 1}, { 639, 1}, { 640, 1}, { 641, 1}, { 642, 1}, { 643, 1}, { 644, 1}, { 645, 1}, { 646, 1}, { 647, 1}, { 648, 1}, { 649, 1}, { 650, 1}, { 651, 1}, - { 652, 1}, { 653, 1}, { 654, 1}, { 655, 1}, { 656, 1}, { 657, 1}, { 658, 1}, { 659, 1}, { 660, 1}, { 661, 1}, { 662, 1}, { 663, 1}, { 664, 1}, { 665, 1}, { 666, 1}, { 667, 1}, - { 668, 1}, { 669, 1}, { 670, 4}, { 674, 1}, { 675, 1}, { 676, 1}, { 677, 1}, { 678, 1}, { 679, 1}, { 680, 1}, { 681, 1}, { 682, 1}, { 683, 1}, { 684, 1}, { 685, 1}, { 686, 1}, - { 687, 1}, { 688, 1}, { 689, 1}, { 690, 1}, { 691, 1}, { 692, 2}, { 694, 2}, { 696, 2}, { 698, 2}, { 700, 2}, { 702, 2}, { 704, 2}, { 706, 2}, { 708, 2}, { 710, 2}, { 712, 2}, - { 714, 2}, { 716, 2}, { 718, 2}, { 720, 2}, { 722, 2}, { 724, 2}, { 726, 2}, { 728, 2}, { 730, 2}, { 732, 2}, { 734, 2}, { 736, 2}, { 738, 6}, { 744, 4}, { 748, 2}, { 750, 2}, - { 752, 2}, { 754, 2}, { 756, 1}, { 757, 1}, { 758, 2}, { 760, 2}, { 762, 1}, { 763, 1}, { 764, 1}, { 765, 1}, { 766, 1}, { 767, 1}, { 768, 1}, { 769, 1}, { 770, 1}, { 771, 1}, - { 772, 1}, { 773, 1}, { 774, 1}, { 775, 1}, { 776, 1}, { 777, 1}, { 778, 1}, { 779, 1}, { 780, 1}, { 781, 1}, { 782, 1}, { 783, 1}, { 784, 1}, { 785, 1}, { 786, 1}, { 787, 1}, - { 788, 1}, { 789, 1}, { 790, 1}, { 791, 1}, { 792, 1}, { 793, 1}, { 794, 1}, { 795, 1}, { 796, 1}, { 797, 1}, { 798, 1}, { 799, 1}, { 800, 1}, { 801, 1}, { 802, 1}, { 803, 1}, - { 804, 1}, { 805, 1}, { 806, 1}, { 807, 1}, { 808, 1}, { 809, 1}, { 810, 1}, { 811, 1}, { 812, 1}, { 813, 1}, { 814, 1}, { 815, 1}, { 816, 1}, { 817, 1}, { 818, 1}, { 819, 1}, - { 820, 1}, { 821, 1}, { 822, 1}, { 823, 1}, { 824, 1}, { 825, 1}, { 826, 1}, { 827, 1}, { 828, 2}, { 830, 2}, { 832, 2}, { 834, 2}, { 836, 1}, { 837, 1}, { 838, 2}, { 840, 2}, - { 842, 1}, { 843, 1}, { 844, 1}, { 845, 1}, { 846, 1}, { 847, 1}, { 848, 1}, { 849, 1}, { 850, 1}, { 851, 1}, { 852, 1}, { 853, 1}, { 854, 1}, { 855, 1}, { 856, 1}, { 857, 1}, - { 858, 1}, { 859, 1}, { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, { 865, 1}, { 866, 1}, { 867, 2}, { 869, 2}, { 871, 2}, { 873, 2}, { 875, 2}, { 877, 2}, { 879, 2}, - { 881, 2}, { 883, 1}, { 884, 1}, { 885, 1}, { 886, 1}, { 887, 1}, { 888, 1}, { 889, 1}, { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 1}, { 897, 1}, - { 898, 1}, { 899, 1}, { 900, 1}, { 901, 1}, { 902, 1}, { 903, 1}, { 904, 2}, { 906, 2}, { 908, 2}, { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, - { 917, 1}, { 918, 1}, { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, { 930, 1}, { 931, 1}, { 932, 1}, - { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, { 942, 1}, { 943, 1}, { 944, 1}, { 945, 1}, { 946, 1}, { 947, 1}, { 948, 1}, - { 949, 1}, { 950, 1}, { 951, 1}, { 952, 1}, { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, { 959, 1}, { 960, 1}, { 961, 1}, { 962, 1}, { 963, 1}, { 964, 1}, - { 965, 1}, { 966, 1}, { 967, 1}, { 968, 1}, { 969, 1}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, { 975, 1}, { 976, 1}, { 977, 1}, { 978, 1}, { 979, 1}, { 980, 1}, - { 981, 1}, { 982, 1}, { 983, 1}, { 984, 1}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 1}, { 991, 1}, { 992, 1}, { 993, 1}, { 994, 1}, { 995, 1}, { 996, 5}, - {1001, 1}, {1002, 1}, {1003, 1}, {1004, 1}, {1005, 1}, {1006, 1}, {1007, 1}, {1008, 1}, {1009, 1}, {1010, 1}, {1011, 1}, {1012, 1}, {1013, 1}, {1014, 1}, {1015, 1}, {1016, 1}, - {1017, 1}, {1018, 1}, {1019, 1}, {1020, 2}, {1022, 2}, {1024, 1}, {1025, 1}, {1026, 2}, {1028, 2}, {1030, 1}, {1031, 1}, {1032, 2}, {1034, 2}, {1036, 1}, {1037, 1}, {1038, 2}, - {1040, 2}, {1042, 1}, {1043, 1}, {1044, 2}, {1046, 2}, {1048, 1}, {1049, 1}, {1050, 2}, {1052, 1}, {1053, 2}, {1055, 1}, {1056, 2}, {1058, 2}, {1060, 1}, {1061, 1}, {1062, 2}, - {1064, 2}, {1066, 1}, {1067, 1}, {1068, 2}, {1070, 2}, {1072, 2}, {1074, 2}, {1076, 2}, {1078, 2}, {1080, 2}, {1082, 2}, {1084, 2}, {1086, 2}, {1088, 1}, {1089, 1}, {1090, 1}, - {1091, 1}, {1092, 1}, {1093, 1}, {1094, 2}, {1096, 2}, {1098, 2}, {1100, 2}, {1102, 2}, {1104, 2}, {1106, 2}, {1108, 2}, {1110, 2}, {1112, 2}, {1114, 2}, {1116, 1}, {1117, 2}, - {1119, 2}, {1121, 1}, {1122, 1}, {1123, 1}, {1124, 1}, {1125, 4}, {1129, 4}, {1133, 4}, {1137, 4}, {1141, 3}, {1144, 3}, {1147, 4}, {1151, 4}, {1155, 4}, {1159, 2}, {1161, 2}, - {1163, 2}, {1165, 2}, {1167, 2}, {1169, 1}, {1170, 1}, {1171, 2}, {1173, 2}, {1175, 2}, {1177, 2}, {1179, 2}, {1181, 2}, {1183, 2}, {1185, 2}, {1187, 2}, {1189, 2}, {1191, 2}, - {1193, 2}, {1195, 2}, {1197, 2}, {1199, 2}, {1201, 2}, {1203, 1}, {1204, 1}, {1205, 1}, {1206, 1}, {1207, 4}, {1211, 4}, {1215, 4}, {1219, 4}, {1223, 2}, {1225, 2}, {1227, 1}, - {1228, 1}, {1229, 2}, {1231, 2}, {1233, 2}, {1235, 2}, {1237, 2}, {1239, 2}, {1241, 2}, {1243, 2}, {1245, 2}, {1247, 2}, {1249, 2}, {1251, 2}, {1253, 2}, {1255, 2}, {1257, 2}, - {1259, 2}, {1261, 2}, {1263, 2}, {1265, 2}, {1267, 2}, {1269, 2}, {1271, 2}, {1273, 2}, {1275, 2}, {1277, 2}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 4}, {1291, 4}, - {1295, 4}, {1299, 4}, {1303, 4}, {1307, 4}, {1311, 4}, {1315, 4}, {1319, 2}, {1321, 2}, {1323, 2}, {1325, 2}, {1327, 2}, {1329, 2}, {1331, 2}, {1333, 2}, {1335, 2}, {1337, 2}, - {1339, 2}, {1341, 2}, {1343, 2}, {1345, 2}, {1347, 2}, {1349, 2}, {1351, 2}, {1353, 2}, {1355, 2}, {1357, 2}, {1359, 2}, {1361, 2}, {1363, 2}, {1365, 1}, {1366, 2}, {1368, 1}, - {1369, 1}, {1370, 1}, {1371, 1}, {1372, 1}, {1373, 1}, {1374, 2}, {1376, 2}, {1378, 2}, {1380, 2}, {1382, 2}, {1384, 2}, {1386, 2}, {1388, 2}, {1390, 2}, {1392, 2}, {1394, 2}, - {1396, 2}, {1398, 2}, {1400, 2}, {1402, 2}, {1404, 2}, {1406, 2}, {1408, 2}, {1410, 2}, {1412, 2}, {1414, 2}, {1416, 1}, {1417, 2}, {1419, 2}, {1421, 2}, {1423, 2}, {1425, 2}, - {1427, 2}, {1429, 2}, {1431, 2}, {1433, 2}, {1435, 2}, {1437, 2}, {1439, 2}, {1441, 2}, {1443, 2}, {1445, 2}, {1447, 2}, {1449, 2}, {1451, 2}, {1453, 2}, {1455, 2}, {1457, 2}, - {1459, 2}, {1461, 1}, {1462, 2}, {1464, 1}, {1465, 1}, {1466, 1}, {1467, 1}, {1468, 1}, {1469, 1}, {1470, 4}, {1474, 2}, {1476, 1}, {1477, 1}, {1478, 1}, {1479, 1}, {1480, 4}, - {1484, 4}, {1488, 2}, {1490, 2}, {1492, 1}, {1493, 1}, {1494, 1}, {1495, 1}, {1496, 1}, {1497, 1}, {1498, 1}, {1499, 1}, {1500, 1}, {1501, 1}, {1502, 2}, {1504, 2}, {1506, 2}, - {1508, 2}, {1510, 2}, {1512, 2}, {1514, 4}, {1518, 4}, {1522, 2}, {1524, 2}, {1526, 2}, {1528, 2}, {1530, 2}, {1532, 2}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, - {1544, 2}, {1546, 2}, {1548, 2}, {1550, 1}, {1551, 1}, {1552, 1}, {1553, 1}, {1554, 1}, {1555, 1}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 2}, {1564, 2}, {1566, 2}, {1568, 1}, - {1569, 1}, {1570, 1}, {1571, 1}, {1572, 1}, {1573, 1}, {1574, 2}, {1576, 2}, {1578, 2}, {1580, 2}, {1582, 2}, {1584, 2}, {1586, 1}, {1587, 1}, {1588, 1}, {1589, 1}, {1590, 1}, - {1591, 1}, {1592, 2}, {1594, 2}, {1596, 2}, {1598, 2}, {1600, 2}, {1602, 2}, {1604, 1}, {1605, 1}, {1606, 1}, {1607, 1}, {1608, 1}, {1609, 1}, {1610, 2}, {1612, 2}, {1614, 2}, - {1616, 2}, {1618, 2}, {1620, 2}, {1622, 2}, {1624, 2}, {1626, 2}, {1628, 2}, {1630, 2}, {1632, 2}, {1634, 3}, {1637, 3}, {1640, 6}, {1646, 6}, {1652, 6}, {1658, 6}, {1664, 6}, - {1670, 6}, {1676, 3}, {1679, 3}, {1682, 3}, {1685, 3}, {1688, 3}, {1691, 3}, {1694, 3}, {1697, 3}, {1700, 3}, {1703, 3}, {1706, 3}, {1709, 3}, {1712, 3}, {1715, 3}, {1718, 3}, - {1721, 3}, {1724, 3}, {1727, 3}, {1730, 3}, {1733, 3}, {1736, 3}, {1739, 3}, {1742, 3}, {1745, 3}, {1748, 3}, {1751, 3}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, {1766, 3}, - {1769, 3}, {1772, 3}, {1775, 3}, {1778, 3}, {1781, 3}, {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, - {1817, 3}, {1820, 3}, {1823, 3}, {1826, 3}, {1829, 3}, {1832, 3}, {1835, 3}, {1838, 3}, {1841, 3}, {1844, 3}, {1847, 3}, {1850, 3}, {1853, 3}, {1856, 3}, {1859, 3}, {1862, 3}, - {1865, 3}, {1868, 3}, {1871, 3}, {1874, 3}, {1877, 3}, {1880, 3}, {1883, 3}, {1886, 3}, {1889, 3}, {1892, 3}, {1895, 3}, {1898, 3}, {1901, 3}, {1904, 3}, {1907, 3}, {1910, 3}, - {1913, 3}, {1916, 3}, {1919, 3}, {1922, 3}, {1925, 3}, {1928, 3}, {1931, 3}, {1934, 3}, {1937, 3}, {1940, 3}, {1943, 3}, {1946, 3}, {1949, 3}, {1952, 3}, {1955, 3}, {1958, 3}, - {1961, 3}, {1964, 1}, {1965, 1}, {1966, 3}, {1969, 3}, {1972, 1}, {1973, 1}, {1974, 3}, {1977, 3}, {1980, 1}, {1981, 1}, {1982, 3}, {1985, 3}, {1988, 1}, {1989, 1}, {1990, 3}, - {1993, 3}, {1996, 1}, {1997, 1}, {1998, 3}, {2001, 3}, {2004, 1}, {2005, 1}, {2006, 3}, {2009, 3}, {2012, 1}, {2013, 1}, {2014, 3}, {2017, 3}, {2020, 1}, {2021, 1}, {2022, 3}, - {2025, 3}, {2028, 1}, {2029, 1}, {2030, 3}, {2033, 3}, {2036, 1}, {2037, 1}, {2038, 3}, {2041, 3}, {2044, 3}, {2047, 3}, {2050, 3}, {2053, 3}, {2056, 1}, {2057, 1}, {2058, 1}, - {2059, 1}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, {2065, 1}, {2066, 1}, {2067, 1}, {2068, 4}, {2072, 4}, {2076, 4}, {2080, 4}, {2084, 1}, {2085, 1}, {2086, 1}, - {2087, 1}, {2088, 1}, {2089, 1}, {2090, 1}, {2091, 1}, {2092, 1}, {2093, 1}, {2094, 1}, {2095, 1}, {2096, 1}, {2097, 1}, {2098, 1}, {2099, 1}, {2100, 1}, {2101, 1}, {2102, 1}, - {2103, 1}, {2104, 1}, {2105, 1}, {2106, 1}, {2107, 1}, {2108, 1}, {2109, 1}, {2110, 1}, {2111, 1}, {2112, 1}, {2113, 1}, {2114, 1}, {2115, 1}, {2116, 1}, {2117, 1}, {2118, 1}, - {2119, 4}, {2123, 2}, {2125, 2}, {2127, 4}, {2131, 2}, {2133, 2}, {2135, 4}, {2139, 2}, {2141, 2}, {2143, 4}, {2147, 2}, {2149, 2}, {2151, 4}, {2155, 2}, {2157, 2}, {2159, 4}, - {2163, 2}, {2165, 2}, {2167, 1}, {2168, 1}, {2169, 1}, {2170, 1}, {2171, 1}, {2172, 1}, {2173, 1}, {2174, 1}, {2175, 1}, {2176, 4}, {2180, 3}, {2183, 1}, {2184, 3}, {2187, 4}, - {2191, 2}, {2193, 3}, {2196, 3}, {2199, 1}, {2200, 2}, {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 1}, {2207, 1}, {2208, 1}, {2209, 1}, {2210, 4}, {2214, 4}, {2218, 1}, - {2219, 2}, {2221, 2}, {2223, 1}, {2224, 1}, {2225, 1}, {2226, 1}, {2227, 2}, {2229, 2}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, {2235, 1}, {2236, 1}, {2237, 1}, {2238, 1}, - {2239, 1}, {2240, 1}, {2241, 1}, {2242, 1}, {2243, 1}, {2244, 1}, {2245, 1}, {2246, 1}, {2247, 1}, {2248, 1}, {2249, 1}, {2250, 1}, {2251, 1}, {2252, 1}, {2253, 1}, {2254, 1}, - {2255, 1}, {2256, 1}, {2257, 1}, {2258, 1}, {2259, 1}, {2260, 1}, {2261, 1}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 2}, {2269, 2}, {2271, 1}, {2272, 1}, - {2273, 1}, {2274, 1}, {2275, 2}, {2277, 2}, {2279, 2}, {2281, 2}, {2283, 1}, {2284, 3}, {2287, 1}, {2288, 3}, {2291, 1}, {2292, 3}, {2295, 1}, {2296, 1}, {2297, 3}, {2300, 3}, - {2303, 1}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 2}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 1}, {2319, 1}, - {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, - {2336, 1}, {2337, 1}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, - {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 2}, {2367, 4}, {2371, 1}, - {2372, 1}, {2373, 4}, {2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, + { 600, 3}, { 603, 3}, { 606, 3}, { 609, 3}, { 612, 3}, { 615, 3}, { 618, 3}, { 621, 3}, { 624, 3}, { 627, 3}, { 630, 1}, { 631, 1}, { 632, 1}, { 633, 3}, { 636, 1}, { 637, 1}, + { 638, 1}, { 639, 1}, { 640, 2}, { 642, 1}, { 643, 1}, { 644, 1}, { 645, 1}, { 646, 1}, { 647, 1}, { 648, 1}, { 649, 1}, { 650, 1}, { 651, 1}, { 652, 1}, { 653, 1}, { 654, 1}, + { 655, 1}, { 656, 1}, { 657, 1}, { 658, 1}, { 659, 1}, { 660, 1}, { 661, 1}, { 662, 1}, { 663, 1}, { 664, 1}, { 665, 1}, { 666, 1}, { 667, 1}, { 668, 1}, { 669, 1}, { 670, 1}, + { 671, 1}, { 672, 1}, { 673, 4}, { 677, 1}, { 678, 1}, { 679, 1}, { 680, 1}, { 681, 1}, { 682, 1}, { 683, 1}, { 684, 1}, { 685, 1}, { 686, 1}, { 687, 1}, { 688, 1}, { 689, 1}, + { 690, 1}, { 691, 1}, { 692, 1}, { 693, 1}, { 694, 1}, { 695, 2}, { 697, 2}, { 699, 2}, { 701, 2}, { 703, 2}, { 705, 2}, { 707, 2}, { 709, 2}, { 711, 2}, { 713, 2}, { 715, 2}, + { 717, 2}, { 719, 2}, { 721, 2}, { 723, 2}, { 725, 2}, { 727, 2}, { 729, 2}, { 731, 2}, { 733, 2}, { 735, 2}, { 737, 2}, { 739, 6}, { 745, 4}, { 749, 2}, { 751, 2}, { 753, 2}, + { 755, 2}, { 757, 1}, { 758, 1}, { 759, 2}, { 761, 2}, { 763, 1}, { 764, 1}, { 765, 1}, { 766, 1}, { 767, 1}, { 768, 1}, { 769, 1}, { 770, 1}, { 771, 1}, { 772, 1}, { 773, 1}, + { 774, 1}, { 775, 1}, { 776, 1}, { 777, 1}, { 778, 1}, { 779, 1}, { 780, 1}, { 781, 1}, { 782, 1}, { 783, 1}, { 784, 1}, { 785, 1}, { 786, 1}, { 787, 1}, { 788, 1}, { 789, 1}, + { 790, 1}, { 791, 1}, { 792, 1}, { 793, 1}, { 794, 1}, { 795, 1}, { 796, 1}, { 797, 1}, { 798, 1}, { 799, 1}, { 800, 1}, { 801, 1}, { 802, 1}, { 803, 1}, { 804, 1}, { 805, 1}, + { 806, 1}, { 807, 1}, { 808, 1}, { 809, 1}, { 810, 1}, { 811, 1}, { 812, 1}, { 813, 1}, { 814, 1}, { 815, 1}, { 816, 1}, { 817, 1}, { 818, 1}, { 819, 1}, { 820, 1}, { 821, 1}, + { 822, 1}, { 823, 1}, { 824, 1}, { 825, 1}, { 826, 1}, { 827, 1}, { 828, 2}, { 830, 2}, { 832, 2}, { 834, 2}, { 836, 1}, { 837, 1}, { 838, 2}, { 840, 2}, { 842, 1}, { 843, 1}, + { 844, 1}, { 845, 1}, { 846, 1}, { 847, 1}, { 848, 1}, { 849, 1}, { 850, 1}, { 851, 1}, { 852, 1}, { 853, 1}, { 854, 1}, { 855, 1}, { 856, 1}, { 857, 1}, { 858, 1}, { 859, 1}, + { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, { 865, 1}, { 866, 1}, { 867, 2}, { 869, 2}, { 871, 2}, { 873, 2}, { 875, 2}, { 877, 2}, { 879, 2}, { 881, 2}, { 883, 1}, + { 884, 1}, { 885, 1}, { 886, 1}, { 887, 1}, { 888, 1}, { 889, 1}, { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 1}, { 897, 1}, { 898, 1}, { 899, 1}, + { 900, 1}, { 901, 1}, { 902, 1}, { 903, 1}, { 904, 2}, { 906, 2}, { 908, 2}, { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, { 917, 1}, { 918, 1}, + { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, { 930, 1}, { 931, 1}, { 932, 1}, { 933, 1}, { 934, 1}, + { 935, 1}, { 936, 1}, { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, { 942, 1}, { 943, 1}, { 944, 1}, { 945, 1}, { 946, 1}, { 947, 1}, { 948, 1}, { 949, 1}, { 950, 1}, + { 951, 1}, { 952, 1}, { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, { 959, 1}, { 960, 1}, { 961, 1}, { 962, 1}, { 963, 1}, { 964, 1}, { 965, 1}, { 966, 1}, + { 967, 1}, { 968, 1}, { 969, 1}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, { 975, 1}, { 976, 1}, { 977, 1}, { 978, 1}, { 979, 1}, { 980, 1}, { 981, 1}, { 982, 1}, + { 983, 1}, { 984, 1}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 1}, { 991, 1}, { 992, 1}, { 993, 1}, { 994, 1}, { 995, 1}, { 996, 5}, {1001, 1}, {1002, 1}, + {1003, 1}, {1004, 1}, {1005, 1}, {1006, 1}, {1007, 1}, {1008, 1}, {1009, 1}, {1010, 1}, {1011, 1}, {1012, 1}, {1013, 1}, {1014, 1}, {1015, 1}, {1016, 1}, {1017, 1}, {1018, 1}, + {1019, 1}, {1020, 2}, {1022, 2}, {1024, 1}, {1025, 1}, {1026, 2}, {1028, 2}, {1030, 1}, {1031, 1}, {1032, 2}, {1034, 2}, {1036, 1}, {1037, 1}, {1038, 2}, {1040, 2}, {1042, 1}, + {1043, 1}, {1044, 2}, {1046, 2}, {1048, 1}, {1049, 1}, {1050, 2}, {1052, 1}, {1053, 2}, {1055, 1}, {1056, 2}, {1058, 2}, {1060, 1}, {1061, 1}, {1062, 2}, {1064, 2}, {1066, 1}, + {1067, 1}, {1068, 2}, {1070, 2}, {1072, 2}, {1074, 2}, {1076, 2}, {1078, 2}, {1080, 2}, {1082, 2}, {1084, 2}, {1086, 2}, {1088, 1}, {1089, 1}, {1090, 1}, {1091, 1}, {1092, 1}, + {1093, 1}, {1094, 2}, {1096, 2}, {1098, 2}, {1100, 2}, {1102, 2}, {1104, 2}, {1106, 2}, {1108, 2}, {1110, 2}, {1112, 2}, {1114, 2}, {1116, 1}, {1117, 2}, {1119, 2}, {1121, 1}, + {1122, 1}, {1123, 1}, {1124, 1}, {1125, 4}, {1129, 4}, {1133, 4}, {1137, 4}, {1141, 3}, {1144, 3}, {1147, 4}, {1151, 4}, {1155, 4}, {1159, 2}, {1161, 2}, {1163, 2}, {1165, 2}, + {1167, 2}, {1169, 1}, {1170, 1}, {1171, 2}, {1173, 2}, {1175, 2}, {1177, 2}, {1179, 2}, {1181, 2}, {1183, 2}, {1185, 2}, {1187, 2}, {1189, 2}, {1191, 2}, {1193, 2}, {1195, 2}, + {1197, 2}, {1199, 2}, {1201, 2}, {1203, 1}, {1204, 1}, {1205, 1}, {1206, 1}, {1207, 4}, {1211, 4}, {1215, 4}, {1219, 4}, {1223, 2}, {1225, 2}, {1227, 1}, {1228, 1}, {1229, 2}, + {1231, 2}, {1233, 2}, {1235, 2}, {1237, 2}, {1239, 2}, {1241, 2}, {1243, 2}, {1245, 2}, {1247, 2}, {1249, 2}, {1251, 2}, {1253, 2}, {1255, 2}, {1257, 2}, {1259, 2}, {1261, 2}, + {1263, 2}, {1265, 2}, {1267, 2}, {1269, 2}, {1271, 2}, {1273, 2}, {1275, 2}, {1277, 2}, {1279, 2}, {1281, 2}, {1283, 2}, {1285, 2}, {1287, 4}, {1291, 4}, {1295, 4}, {1299, 4}, + {1303, 4}, {1307, 4}, {1311, 4}, {1315, 4}, {1319, 2}, {1321, 2}, {1323, 2}, {1325, 2}, {1327, 2}, {1329, 2}, {1331, 2}, {1333, 2}, {1335, 2}, {1337, 2}, {1339, 2}, {1341, 2}, + {1343, 2}, {1345, 2}, {1347, 2}, {1349, 2}, {1351, 2}, {1353, 2}, {1355, 2}, {1357, 2}, {1359, 2}, {1361, 2}, {1363, 2}, {1365, 1}, {1366, 2}, {1368, 1}, {1369, 1}, {1370, 1}, + {1371, 1}, {1372, 1}, {1373, 1}, {1374, 2}, {1376, 2}, {1378, 2}, {1380, 2}, {1382, 2}, {1384, 2}, {1386, 2}, {1388, 2}, {1390, 2}, {1392, 2}, {1394, 2}, {1396, 2}, {1398, 2}, + {1400, 2}, {1402, 2}, {1404, 2}, {1406, 2}, {1408, 2}, {1410, 2}, {1412, 2}, {1414, 2}, {1416, 1}, {1417, 2}, {1419, 2}, {1421, 2}, {1423, 2}, {1425, 2}, {1427, 2}, {1429, 2}, + {1431, 2}, {1433, 2}, {1435, 2}, {1437, 2}, {1439, 2}, {1441, 2}, {1443, 2}, {1445, 2}, {1447, 2}, {1449, 2}, {1451, 2}, {1453, 2}, {1455, 2}, {1457, 2}, {1459, 2}, {1461, 1}, + {1462, 2}, {1464, 1}, {1465, 1}, {1466, 1}, {1467, 1}, {1468, 1}, {1469, 1}, {1470, 4}, {1474, 2}, {1476, 1}, {1477, 1}, {1478, 1}, {1479, 1}, {1480, 4}, {1484, 4}, {1488, 2}, + {1490, 2}, {1492, 1}, {1493, 1}, {1494, 1}, {1495, 1}, {1496, 1}, {1497, 1}, {1498, 1}, {1499, 1}, {1500, 1}, {1501, 1}, {1502, 2}, {1504, 2}, {1506, 2}, {1508, 2}, {1510, 2}, + {1512, 2}, {1514, 4}, {1518, 4}, {1522, 2}, {1524, 2}, {1526, 2}, {1528, 2}, {1530, 2}, {1532, 2}, {1534, 2}, {1536, 2}, {1538, 2}, {1540, 2}, {1542, 2}, {1544, 2}, {1546, 2}, + {1548, 2}, {1550, 1}, {1551, 1}, {1552, 1}, {1553, 1}, {1554, 1}, {1555, 1}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 2}, {1564, 2}, {1566, 2}, {1568, 1}, {1569, 1}, {1570, 1}, + {1571, 1}, {1572, 1}, {1573, 1}, {1574, 2}, {1576, 2}, {1578, 2}, {1580, 2}, {1582, 2}, {1584, 2}, {1586, 1}, {1587, 1}, {1588, 1}, {1589, 1}, {1590, 1}, {1591, 1}, {1592, 2}, + {1594, 2}, {1596, 2}, {1598, 2}, {1600, 2}, {1602, 2}, {1604, 1}, {1605, 1}, {1606, 1}, {1607, 1}, {1608, 1}, {1609, 1}, {1610, 2}, {1612, 2}, {1614, 2}, {1616, 2}, {1618, 2}, + {1620, 2}, {1622, 2}, {1624, 2}, {1626, 2}, {1628, 2}, {1630, 2}, {1632, 2}, {1634, 3}, {1637, 3}, {1640, 6}, {1646, 6}, {1652, 6}, {1658, 6}, {1664, 6}, {1670, 6}, {1676, 3}, + {1679, 3}, {1682, 3}, {1685, 3}, {1688, 3}, {1691, 3}, {1694, 3}, {1697, 3}, {1700, 3}, {1703, 3}, {1706, 3}, {1709, 3}, {1712, 3}, {1715, 3}, {1718, 3}, {1721, 3}, {1724, 3}, + {1727, 3}, {1730, 3}, {1733, 3}, {1736, 3}, {1739, 3}, {1742, 3}, {1745, 3}, {1748, 3}, {1751, 3}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, {1766, 3}, {1769, 3}, {1772, 3}, + {1775, 3}, {1778, 3}, {1781, 3}, {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, {1817, 3}, {1820, 3}, + {1823, 3}, {1826, 3}, {1829, 3}, {1832, 3}, {1835, 3}, {1838, 3}, {1841, 3}, {1844, 3}, {1847, 3}, {1850, 3}, {1853, 3}, {1856, 3}, {1859, 3}, {1862, 3}, {1865, 3}, {1868, 3}, + {1871, 3}, {1874, 3}, {1877, 3}, {1880, 3}, {1883, 3}, {1886, 3}, {1889, 3}, {1892, 3}, {1895, 3}, {1898, 3}, {1901, 3}, {1904, 3}, {1907, 3}, {1910, 3}, {1913, 3}, {1916, 3}, + {1919, 3}, {1922, 3}, {1925, 3}, {1928, 3}, {1931, 3}, {1934, 3}, {1937, 3}, {1940, 3}, {1943, 3}, {1946, 3}, {1949, 3}, {1952, 3}, {1955, 3}, {1958, 3}, {1961, 3}, {1964, 1}, + {1965, 1}, {1966, 3}, {1969, 3}, {1972, 1}, {1973, 1}, {1974, 3}, {1977, 3}, {1980, 1}, {1981, 1}, {1982, 3}, {1985, 3}, {1988, 1}, {1989, 1}, {1990, 3}, {1993, 3}, {1996, 1}, + {1997, 1}, {1998, 3}, {2001, 3}, {2004, 1}, {2005, 1}, {2006, 3}, {2009, 3}, {2012, 1}, {2013, 1}, {2014, 3}, {2017, 3}, {2020, 1}, {2021, 1}, {2022, 3}, {2025, 3}, {2028, 1}, + {2029, 1}, {2030, 3}, {2033, 3}, {2036, 1}, {2037, 1}, {2038, 3}, {2041, 3}, {2044, 3}, {2047, 3}, {2050, 3}, {2053, 3}, {2056, 1}, {2057, 1}, {2058, 1}, {2059, 1}, {2060, 1}, + {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, {2065, 1}, {2066, 1}, {2067, 1}, {2068, 4}, {2072, 4}, {2076, 4}, {2080, 4}, {2084, 1}, {2085, 1}, {2086, 1}, {2087, 1}, {2088, 1}, + {2089, 1}, {2090, 1}, {2091, 1}, {2092, 1}, {2093, 1}, {2094, 1}, {2095, 1}, {2096, 1}, {2097, 1}, {2098, 1}, {2099, 1}, {2100, 1}, {2101, 1}, {2102, 1}, {2103, 1}, {2104, 1}, + {2105, 1}, {2106, 1}, {2107, 1}, {2108, 1}, {2109, 1}, {2110, 1}, {2111, 1}, {2112, 1}, {2113, 1}, {2114, 1}, {2115, 1}, {2116, 1}, {2117, 1}, {2118, 1}, {2119, 4}, {2123, 2}, + {2125, 2}, {2127, 4}, {2131, 2}, {2133, 2}, {2135, 4}, {2139, 2}, {2141, 2}, {2143, 4}, {2147, 2}, {2149, 2}, {2151, 4}, {2155, 2}, {2157, 2}, {2159, 4}, {2163, 2}, {2165, 2}, + {2167, 1}, {2168, 1}, {2169, 1}, {2170, 1}, {2171, 1}, {2172, 1}, {2173, 1}, {2174, 1}, {2175, 1}, {2176, 4}, {2180, 3}, {2183, 1}, {2184, 3}, {2187, 4}, {2191, 2}, {2193, 3}, + {2196, 3}, {2199, 1}, {2200, 2}, {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 1}, {2207, 1}, {2208, 1}, {2209, 1}, {2210, 4}, {2214, 4}, {2218, 1}, {2219, 2}, {2221, 2}, + {2223, 1}, {2224, 1}, {2225, 1}, {2226, 1}, {2227, 2}, {2229, 2}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, {2235, 1}, {2236, 1}, {2237, 1}, {2238, 1}, {2239, 1}, {2240, 1}, + {2241, 1}, {2242, 1}, {2243, 1}, {2244, 1}, {2245, 1}, {2246, 1}, {2247, 1}, {2248, 1}, {2249, 1}, {2250, 1}, {2251, 1}, {2252, 1}, {2253, 1}, {2254, 1}, {2255, 1}, {2256, 1}, + {2257, 1}, {2258, 1}, {2259, 1}, {2260, 1}, {2261, 1}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 2}, {2269, 2}, {2271, 1}, {2272, 1}, {2273, 1}, {2274, 1}, + {2275, 2}, {2277, 2}, {2279, 2}, {2281, 2}, {2283, 1}, {2284, 3}, {2287, 1}, {2288, 3}, {2291, 1}, {2292, 3}, {2295, 1}, {2296, 1}, {2297, 3}, {2300, 3}, {2303, 1}, {2304, 1}, + {2305, 1}, {2306, 1}, {2307, 1}, {2308, 2}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 1}, {2319, 1}, {2320, 1}, {2321, 1}, + {2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, {2336, 1}, {2337, 1}, + {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1}, + {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 2}, {2367, 4}, {2371, 1}, {2372, 1}, {2373, 4}, + {2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, }; u8 const Asm_amd64::raw_encode_forms[38320] = { 0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00, @@ -1004,472 +1005,576 @@ u8 const Asm_amd64::raw_encode_forms[38320] = { 0x96, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x4a, 0x00, 0x01, 0x08, 0x08, 0x00, 0x97, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x4b, 0x00, 0x01, 0x00, 0x08, 0x00, 0x97, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x4b, 0x00, 0x01, 0x00, 0x08, 0x00, 0x97, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x4b, 0x00, 0x01, 0x08, 0x08, 0x00, 0x98, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x48, 0x00, 0x01, 0x00, 0x08, 0x00, 0x98, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x48, 0x00, 0x01, 0x00, 0x08, 0x00, 0x98, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x48, 0x00, 0x01, 0x08, 0x08, 0x00, 0x99, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x44, 0x00, 0x01, 0x00, 0x08, 0x00, 0x99, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x44, 0x00, 0x01, 0x00, 0x08, 0x00, 0x99, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x44, 0x00, 0x01, 0x08, 0x08, 0x00, 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0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, }; -u8 const Asm_amd64::raw_clobber_table[19104] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x40, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, @@ -1742,8 +2039,12 @@ u8 const Asm_amd64::raw_clobber_table[19104] = { 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x09, 0x00, 0x0f, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, - 0x00, 0x01, 0x09, 0x00, 0x0f, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x03, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x03, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x09, 0x00, 0x0f, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x00, 0x01, 0x09, 0x00, 0x0f, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index a75b68c35..ce15e2cd1 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -932,7 +932,8 @@ gb_internal void check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm instr->valid_form_index = cast(i32)valid_form_index; // Handle clobbering from mnemonic - auto clobber = asm_ctx->clobber(mnemonic); + auto clobber_forms = asm_ctx->clobber_forms(mnemonic); + auto clobber = clobber_forms[valid_form_index]; tmpl_entity->AsmTemplate.clobber_flags |= clobber.implies_clobber_flags(); tmpl_entity->AsmTemplate.clobber_memory |= clobber.implies_clobber_memory(); From 35ae861ff65620e6fbdc1e13e8ede222e897fd75 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:28:54 +0100 Subject: [PATCH 80/92] Use number rather than enum --- core/rexcode/isa/x86/clobber_types.odin | 9 +- .../isa/x86/tablegen/clobber_table.odin | 4098 ++++++++--------- core/rexcode/isa/x86/tablegen/gen.odin | 7 +- .../x86/tablegen/generated/encode_tables.odin | 4096 ++++++++-------- 4 files changed, 4108 insertions(+), 4102 deletions(-) diff --git a/core/rexcode/isa/x86/clobber_types.odin b/core/rexcode/isa/x86/clobber_types.odin index 164003cd2..2e2d2eb64 100644 --- a/core/rexcode/isa/x86/clobber_types.odin +++ b/core/rexcode/isa/x86/clobber_types.odin @@ -29,12 +29,13 @@ Side_Effects :: distinct bit_set[Side_Effect; u16] Clobber_Regs :: distinct bit_set[Clobber_Reg; u16] Clobber_Reg :: enum u8 { - RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R11, - XMM0, VECTOR, MXCSR, FPU_ST, FPU_SW, + RAX, RBX, RCX, RDX, + RSI, RDI, RSP, RBP, + R11, XMM0, VECTOR, MXCSR, + FPU_ST, FPU_SW, } -Operand_Set :: distinct bit_set[Operand_Slot; u8] -Operand_Slot :: enum u8 { OP0, OP1, OP2, OP3 } +Operand_Set :: distinct bit_set[0..<4; u8] Clobber :: struct { written: Operand_Set, diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index 3bc0a9b19..2d59cce41 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -6,7 +6,7 @@ // 1. Implicit-operand normalisation. An operand that is an implicit register // (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, // ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from the -// OP0..OP3 slot set and, if that slot was written/read, folded into +// OP0.3 slot set and, if that slot was written/read, folded into // implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an // operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) // are inherent and kept on every form. @@ -44,531 +44,531 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.1 Data Transfer Encodings .MOV = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVABS = { - {written={.OP0}, read={.OP1}}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, }, .MOVZX = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSX = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSXD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XCHG = { // asserts LOCK when a mem operand is used - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, }, .PUSH = { - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, }, .POP = { - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, }, .LEA = { // no memory access: computes effective address only - {written={.OP0}}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}}, + {written={0}}, + {written={0}}, }, // 8.2 Arithmetic Encodings .ADD = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .ADC = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .SUB = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .SBB = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .MUL = { // RAX/RDX widths follow operand size (r/m8 -> AX only) - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, }, .IMUL = { // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) }, .DIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .IDIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .INC = { // CF deliberately NOT affected - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .DEC = { // CF deliberately NOT affected - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .NEG = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .CMP = { // no operand written; flags only - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, // 8.3 Logical Encodings .AND = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .OR = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .XOR = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .NOT = { - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, }, .TEST = { // no operand written; flags only - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, }, // 8.4 Shift/Rotate Encodings .SHL = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .SHR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .SAR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .ROL = { // only CF/OF affected; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, }, .ROR = { // only CF/OF affected; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, }, .RCL = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .RCR = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .SHLD = { - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, }, .SHRD = { - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, }, // 8.5 Bit Operation Encodings .BT = { // ZF unaffected - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .BTS = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BTR = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BTC = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BSF = { // destination undefined when source == 0 - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, }, .BSR = { // destination undefined when source == 0 - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, }, .POPCNT = { // ZF per source; CF/OF/SF/AF/PF cleared - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .LZCNT = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .TZCNT = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, // 8.6 Control Flow Encodings .JMP = { // indirect forms read reg/mem; writes RIP - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, }, .JA = { // reads flags; writes RIP on taken branch {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, @@ -709,11 +709,11 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, }, .CALL = { // pushes return address - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, }, .RET = { // pops return address (+imm16 form adjusts RSP) {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, @@ -729,7 +729,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, }, .INT = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate - {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, }, .INT3 = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, @@ -752,244 +752,244 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.7 Conditional Set/Move Encodings .SETA = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETAE = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETB = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETBE = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETC = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETE = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETG = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETGE = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETL = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETLE = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNA = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETNAE = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNB = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNBE = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETNC = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNE = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETNG = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNGE = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETNL = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETNLE = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNO = { - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, }, .SETNP = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETNS = { - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, }, .SETNZ = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETO = { - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, }, .SETP = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETPE = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETPO = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETS = { - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, }, .SETZ = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .CMOVA = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVAE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVB = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVBE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVC = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVG = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVGE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVL = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVLE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNA = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVNAE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNB = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNBE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVNC = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVNG = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNGE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVNL = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVNLE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, }, .CMOVNP = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVNS = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, }, .CMOVNZ = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, }, .CMOVP = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVPE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVPO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVS = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, }, .CMOVZ = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, // 8.8 String Operation Encodings @@ -1005,8 +1005,8 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .MOVSD = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // SSE variants - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVSQ = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, @@ -1023,7 +1023,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .CMPSD = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPSQ = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, @@ -1185,569 +1185,569 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.11 BMI/ADX Encodings .ANDN = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BEXTR = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, }, .BLSI = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BLSMSK = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BLSR = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BZHI = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .PDEP = { // no flags affected - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PEXT = { // no flags affected - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .RORX = { // no flags affected - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SARX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHLX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHRX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .MULX = { // no flags affected; implicit multiplicand in rDX - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, }, .ADCX = { // only CF (chains with ADCX) - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, }, .ADOX = { // only OF (chains with ADOX) - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, }, // 8.12 SSE Encodings .MOVAPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVUPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVAPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVUPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVSS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVDQA = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVDQU = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVHPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVHPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLHPS = { - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .MOVHLPS = { - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .MOVMSKPS = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVMSKPD = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVNTPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTDQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTDQA = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RCPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RCPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ANDPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDNPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDNPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ORPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ORPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XORPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XORPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CMPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .COMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .COMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .UCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .UCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .SHUFPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHUFPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .UNPCKLPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKHPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKLPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKHPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CVTPS2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPD2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSS2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSD2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTDQ2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTDQ2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSI2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSI2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .PADDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDUSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDUSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBUSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBUSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULUDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMADDWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PAND = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PANDN = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .POR = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PXOR = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSLLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSLLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSLLQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRAW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRAD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PCMPEQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPEQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPEQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKSSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKSSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKUSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLQDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHQDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSHUFD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PEXTRW = { // destination may be memory - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .PINSRW = { - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PMOVMSKB = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .PAVGB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PAVGW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSADBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, }, .LFENCE = { // ordering/hint; no clobber {side_effects={.FENCE, .SERIALIZING}}, @@ -1762,233 +1762,233 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.HINT}}, }, .CLFLUSH = { // flushes cache line for the addressed byte - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .ADDSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MOVDDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSLDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSHDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .LDDQU = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSHUFB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMADDUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHRSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGNB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGNW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGND = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PALIGNR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDVPS = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .BLENDVPD = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .PBLENDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PBLENDVB = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .DPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .EXTRACTPS = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .INSERTPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .MPSADBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PACKUSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PEXTRB = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PEXTRD = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PEXTRQ = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PHMINPOSUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PINSRB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PINSRD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PINSRQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PMAXSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PTEST = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .ROUNDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .PCMPEQQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CRC32 = { // accumulates CRC into OP0; no flags - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, }, .PCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, @@ -2003,430 +2003,430 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .PCMPGTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCLMULQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .AESDEC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESDECLAST = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESENC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESENCLAST = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESIMC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESKEYGENASSIST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHA1MSG1 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1MSG2 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1NEXTE = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1RNDS4 = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHA256MSG1 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA256MSG2 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA256RNDS2 = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, // 8.13 AVX/AVX2 Encodings .VADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VANDPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDNPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDNPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VORPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VORPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VXORPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VXORPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VCMPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VUCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VUCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VSHUFPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VSHUFPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VUNPCKLPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKHPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKLPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKHPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDVPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDVPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VDPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VEXTRACTPS = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VINSERTPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMOVAPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVUPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVAPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVUPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVSS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VMOVSD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VMOVDQA = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVDQU = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVHPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVHPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLHPS = { - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .VMOVHLPS = { - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .VMOVMSKPS = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVMSKPD = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVNTPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTDQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTDQA = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VADDSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VLDDQU = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVSLDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVSHDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, @@ -2441,565 +2441,565 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .VPBROADCASTB = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTW = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTD = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCVTPS2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPD2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSS2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSD2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTDQ2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTDQ2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSI2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSI2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VPADDB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULUDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMADDWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPAND = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPANDN = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPOR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPXOR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSLLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSLLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRAW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRAD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPCMPEQB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKSSWB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKSSDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKUSWB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKUSDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPEXTRB = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRW = { // destination may be memory - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRD = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRQ = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPINSRB = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPMOVMSKB = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPTEST = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VPSHUFB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMADDUBSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHRSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGNB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGNW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGND = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPABSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPABSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPABSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPALIGNR = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPBLENDW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPBLENDVB = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMPSADBW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPHMINPOSUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMAXSB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXSD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXUD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINSB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINSD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINUD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMOVSXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXBQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMULDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VMASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, }, .VPCLMULQDQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VAESDEC = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESDECLAST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESENC = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESENCLAST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESIMC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VAESKEYGENASSIST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBROADCASTSS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VBROADCASTSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .VBROADCASTF128 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXTRACTF128 = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VINSERTF128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERM2F128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMASKMOVPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VMASKMOVPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VTESTPS = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VTESTPD = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VZEROALL = { // zeroes the entire vector register file (YMM/ZMM) {implicit_wr={.VECTOR}}, @@ -3008,1199 +3008,1199 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.VECTOR}}, }, .VBROADCASTI128 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXTRACTI128 = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VINSERTI128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERM2I128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERMD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPSLLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRAVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMASKMOVD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VPMASKMOVQ = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VGATHERDPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERDPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERQPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERQPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERDD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERDQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERQD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERQQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, // 8.14 FMA Encodings .VFMADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPH2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPS2PH = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, }, // 8.15 AVX-512 Encodings .VMOVDQA32 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQA64 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU8 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU16 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU32 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU64 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBLENDMB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDMPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDMPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCOMPRESSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCOMPRESSQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCOMPRESSPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCOMPRESSPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPEXPANDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPEXPANDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXPANDPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXPANDPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCONFLICTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCONFLICTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPLZCNTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPLZCNTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPERMI2B = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2W = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2D = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2Q = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2PS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2PD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2B = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2W = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2D = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2Q = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2PS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2PD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMOVB2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVW2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVD2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVQ2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2B = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2W = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2D = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2Q = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPROLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSCATTERDD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERDQ = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERQD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERQQ = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERDPS = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERDPD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERQPS = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERQPD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSRAVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRAVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VRANGEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFPCLASSPS = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSPD = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSSS = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSSD = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VALIGNQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VALIGND = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VDBPSADBW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPTERNLOGD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPTERNLOGQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPMULTISHIFTQB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .KADDW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDND = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KMOVW = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVB = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVQ = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVD = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KNOTW = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTB = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTQ = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTD = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORTESTW = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTB = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTQ = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTD = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KSHIFTLW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KTESTW = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTB = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTQ = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTD = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KUNPCKBW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KUNPCKWD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KUNPCKDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, // 8.16 x87 FPU Encodings @@ -4559,66 +4559,66 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.17 System Instruction Encodings .LGDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SGDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, }, .LIDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SIDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, }, .LLDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SLDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .LTR = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .STR = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .LMSW = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SMSW = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .CLTS = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.PRIVILEGED}}, }, .ARPL = { // legacy; adjusts RPL, sets ZF - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .LAR = { // ZF=1 on success; OP0 undefined on failure - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, }, .LSL = { // ZF=1 on success; OP0 undefined on failure - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, }, .VERR = { // ZF=1 if segment is readable/writable - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, }, .VERW = { // ZF=1 if segment is readable/writable - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, }, .INVD = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.SERIALIZING, .PRIVILEGED}}, @@ -4627,11 +4627,11 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.SERIALIZING, .PRIVILEGED}}, }, .INVLPG = { // privileged; no GPR/EFLAGS clobber modeled - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .INVPCID = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .RSM = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.SERIALIZING, .PRIVILEGED}}, @@ -4655,31 +4655,31 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.PRIVILEGED}}, }, .VMXON = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMCLEAR = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMPTRLD = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMPTRST = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMREAD = { // VMX status in ZF/CF - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMWRITE = { // VMX status in ZF/CF - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMFUNC = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.PRIVILEGED}}, }, .INVEPT = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .INVVPID = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, // 8.18 Security and Memory Protection Encodings @@ -4699,16 +4699,16 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_rd={.RAX, .RCX, .RDX}}, }, .INCSSPD = { // advances SSP - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, }, .INCSSPQ = { // advances SSP - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, }, .RDSSPD = { // reads shadow-stack pointer into OP0 - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, }, .RDSSPQ = { // reads shadow-stack pointer into OP0 - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, }, .SAVEPREVSSP = { // CET shadow-stack management {side_effects={.CET}}, @@ -4717,16 +4717,16 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.CET}}, }, .WRSSD = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRSSQ = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRUSSD = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRUSSQ = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .SETSSBSY = { // CET shadow-stack management {side_effects={.CET}}, @@ -4781,58 +4781,58 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.20 Cache and Prefetch Encodings .PREFETCHT0 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHT1 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHT2 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHNTA = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHW = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .CLFLUSHOPT = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .CLWB = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .CLDEMOTE = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, // 8.21 Atomic and Byte Swap Encodings .BSWAP = { - {written={.OP0}, read={.OP0}}, - {written={.OP0}, read={.OP0}}, + {written={0}, read={0}}, + {written={0}, read={0}}, }, .CMPXCHG = { // ZF set on match; on mismatch RAX <- dest - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .CMPXCHG8B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .CMPXCHG16B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .XADD = { - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, // 8.22 Miscellaneous Encodings .BOUND = { // #BR if out of bounds - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, }, .ENTER = { // builds stack frame {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, @@ -4847,21 +4847,21 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, }, .MOVBE = { // byte-swapping load/store - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .RDRAND = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .RDSEED = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, } diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 10225cd7d..54da4475d 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -23,6 +23,7 @@ package rexcode_x86_tablegen // before Stage B dumps it to raw bytes, so the blobs can never drift from a // well-typed table. +import "base:intrinsics" import "core:fmt" import "core:os" import "core:strings" @@ -177,7 +178,11 @@ write_clobber :: proc(sb: ^strings.Builder, c: lib.Clobber, max_name: int) { i := 0 for flag in flags { if i > 0 { strings.write_string(sb, ", ") } - fmt.sbprintf(sb, ".%s", flag) + when intrinsics.type_is_enum(type_of(flag)) { + fmt.sbprintf(sb, ".%s", flag) + } else { + fmt.sbprintf(sb, "%v", flag) + } i += 1 } strings.write_string(sb, "}") diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 74eda1187..041487e87 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -3600,477 +3600,477 @@ ENCODE_FORMS := [2395]lib.Encoding{ @(rodata) CLOBBER_FORMS := [2395]lib.Clobber{ // .MOV - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVABS - {written={.OP0}, read={.OP1}}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, // .MOVZX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSXD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XCHG - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, // .PUSH - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, // .POP - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, // .LEA - {written={.OP0}}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}}, + {written={0}}, + {written={0}}, // .ADD - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .ADC - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .SUB - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .SBB - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .MUL - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // .IMUL - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // .DIV - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .IDIV - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .INC - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .DEC - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .NEG - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .CMP - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .AND - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .OR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .XOR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .NOT - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, // .TEST - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, // .SHL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .SHR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .SAR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .ROL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // .ROR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // .RCL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .RCR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .SHLD - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, // .SHRD - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, // .BT - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .BTS - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BTR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BTC - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BSF - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, // .BSR - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, // .POPCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .LZCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .TZCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .JMP - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, // .JA {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, @@ -4174,11 +4174,11 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .LOOPNE {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, // .CALL - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, // .RET {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, @@ -4189,7 +4189,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .IRETQ {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // .INT - {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // .INT3 {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // .INTO @@ -4203,185 +4203,185 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .SYSEXIT {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // .SETA - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETAE - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETB - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETBE - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETC - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETE - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETG - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETGE - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETL - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETLE - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNA - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETNAE - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNB - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNBE - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETNC - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNE - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETNG - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNGE - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETNL - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETNLE - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNO - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, // .SETNP - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETNS - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, // .SETNZ - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETO - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, // .SETP - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETPE - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETPO - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETS - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, // .SETZ - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .CMOVA - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVAE - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVB - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVBE - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVC - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVE - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVG - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVGE - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVL - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVLE - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNA - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVNAE - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNB - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNBE - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVNC - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNE - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVNG - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNGE - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVNL - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVNLE - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNO - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, // .CMOVNP - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVNS - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, // .CMOVNZ - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVO - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, // .CMOVP - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVPE - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVPO - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVS - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, // .CMOVZ - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .MOVS {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .MOVSB @@ -4390,8 +4390,8 @@ CLOBBER_FORMS := [2395]lib.Clobber{ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .MOVSD {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVSQ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .CMPS @@ -4402,7 +4402,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // .CMPSD {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPSQ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // .SCAS @@ -4507,398 +4507,398 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .CQO {implicit_wr={.RDX}, implicit_rd={.RAX}}, // .ANDN - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BEXTR - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, // .BLSI - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BLSMSK - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BLSR - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BZHI - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .PDEP - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PEXT - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .RORX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SARX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHLX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHRX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .MULX - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, // .ADCX - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, // .ADOX - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, // .MOVAPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVUPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVAPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVUPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVSS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVDQA - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVDQU - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVHPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVHPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLHPS - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .MOVHLPS - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .MOVMSKPS - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVMSKPD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVNTPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTDQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTDQA - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ADDPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RCPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RCPSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RSQRTSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ANDPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDNPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDNPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ORPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ORPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XORPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XORPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CMPPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .COMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .COMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .UCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .UCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .SHUFPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHUFPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .UNPCKLPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKHPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKLPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKHPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CVTPS2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPD2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSS2SD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSD2SS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTDQ2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTDQ2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSI2SS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSI2SD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .PADDB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDUSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDUSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBUSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBUSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULLW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULUDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMADDWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PAND - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PANDN - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .POR - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PXOR - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSLLW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSLLD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSLLQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRAW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRAD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PCMPEQB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPEQW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPEQD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKSSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKSSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKUSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLQDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHQDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSHUFD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PEXTRW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .PINSRW - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, // .PMOVMSKB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .PAVGB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PAVGW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSADBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MASKMOVDQU - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // .LFENCE {side_effects={.FENCE, .SERIALIZING}}, // .SFENCE @@ -4908,159 +4908,159 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .PAUSE {side_effects={.HINT}}, // .CLFLUSH - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .ADDSUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HADDPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HADDPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HSUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HSUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MOVDDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSLDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSHDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .LDDQU - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSHUFB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMADDUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHRSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGNB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGNW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGND - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PALIGNR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDVPS - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .BLENDVPD - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .PBLENDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PBLENDVB - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .DPPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .DPPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .EXTRACTPS - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .INSERTPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .MPSADBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PACKUSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PEXTRB - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PEXTRD - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PEXTRQ - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PHMINPOSUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PINSRB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PINSRD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PINSRQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PMAXSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULLD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PTEST - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .ROUNDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .PCMPEQQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CRC32 - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, // .PCMPESTRI {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .PCMPESTRM @@ -5070,316 +5070,316 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .PCMPISTRM {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .PCMPGTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCLMULQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .AESDEC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESDECLAST - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESENC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESENCLAST - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESIMC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESKEYGENASSIST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHA1MSG1 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1MSG2 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1NEXTE - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1RNDS4 - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHA256MSG1 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA256MSG2 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA256RNDS2 - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .VADDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRTSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VANDPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDNPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDNPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VORPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VORPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VXORPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VXORPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VCMPPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VUCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VUCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VSHUFPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VSHUFPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VUNPCKLPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKHPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKLPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKHPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDVPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDVPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VDPPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDPPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VEXTRACTPS - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VINSERTPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMOVAPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVUPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVAPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVUPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVSS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, // .VMOVSD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, // .VMOVDQA - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVDQU - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVHPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVHPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLHPS - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .VMOVHLPS - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .VMOVMSKPS - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVMSKPD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVNTPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTDQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTDQA - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VADDSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHADDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHADDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VLDDQU - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVSLDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVSHDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCMPESTRI {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .VPCMPESTRM @@ -5389,1340 +5389,1340 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .VPCMPISTRM {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .VPBROADCASTB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCVTPS2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPD2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSS2SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSD2SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTDQ2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTDQ2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSI2SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSI2SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VPADDB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULUDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMADDWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPAND - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPANDN - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPOR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPXOR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSLLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSLLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRAW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRAD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPCMPEQB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKSSWB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKSSDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKUSWB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKUSDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPEXTRB - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRD - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRQ - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPINSRB - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPMOVMSKB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPTEST - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VPSHUFB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMADDUBSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHRSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGNB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGNW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGND - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPABSB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPABSW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPABSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPALIGNR - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPBLENDW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPBLENDVB - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMPSADBW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPHMINPOSUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMAXSB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXSD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINSB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINSD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMOVSXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXBQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMULDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VMASKMOVDQU - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // .VPCLMULQDQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VAESDEC - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESDECLAST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESENC - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESENCLAST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESIMC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VAESKEYGENASSIST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBROADCASTSS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VBROADCASTSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .VBROADCASTF128 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXTRACTF128 - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VINSERTF128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERM2F128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMASKMOVPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VMASKMOVPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VTESTPS - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VTESTPD - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VZEROALL {implicit_wr={.VECTOR}}, // .VZEROUPPER {implicit_wr={.VECTOR}}, // .VBROADCASTI128 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXTRACTI128 - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VINSERTI128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERM2I128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPSLLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRAVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMASKMOVD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VPMASKMOVQ - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VGATHERDPS - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERDPD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERQPS - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERQPD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERDD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERDQ - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERQD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERQQ - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VFMADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPH2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPS2PH - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, // .VMOVDQA32 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQA64 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU8 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU16 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU32 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU64 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBLENDMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDMPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCOMPRESSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCOMPRESSQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCOMPRESSPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCOMPRESSPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPEXPANDD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPEXPANDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXPANDPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXPANDPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCONFLICTD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCONFLICTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPLZCNTD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPLZCNTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPERMI2B - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2W - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2D - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2Q - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2PS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2PD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2B - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2W - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2D - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2Q - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2PS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2PD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMOVB2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVW2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVD2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVQ2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2B - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2W - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2D - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2Q - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPROLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSCATTERDD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERDQ - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERQD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERQQ - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERDPS - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERDPD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERQPS - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERQPD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSRAVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRAVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VRANGEPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGEPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCEPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCEPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALEPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALEPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFPCLASSPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSSS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VALIGNQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VALIGND - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VDBPSADBW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPTERNLOGD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPTERNLOGQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPMULTISHIFTQB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .KADDW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDND - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KMOVW - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVB - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KNOTW - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTB - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTQ - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTD - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORTESTW - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTB - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTQ - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTD - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KSHIFTLW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KTESTW - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTB - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTQ - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTD - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KUNPCKBW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KUNPCKWD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KUNPCKDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .FADD {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, @@ -6978,60 +6978,60 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .FXRSTOR64 {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // .LGDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SGDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, // .LIDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SIDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, // .LLDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SLDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .LTR - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .STR - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .LMSW - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SMSW - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .CLTS {side_effects={.PRIVILEGED}}, // .ARPL - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .LAR - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, // .LSL - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, // .VERR - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, // .VERW - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, // .INVD {side_effects={.SERIALIZING, .PRIVILEGED}}, // .WBINVD {side_effects={.SERIALIZING, .PRIVILEGED}}, // .INVLPG - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .INVPCID - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .RSM {side_effects={.SERIALIZING, .PRIVILEGED}}, // .RDMSR @@ -7047,23 +7047,23 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .VMXOFF {side_effects={.PRIVILEGED}}, // .VMXON - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMCLEAR - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMPTRLD - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMPTRST - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMREAD - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMWRITE - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMFUNC {side_effects={.PRIVILEGED}}, // .INVEPT - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .INVVPID - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .ENCLS {side_effects={.PRIVILEGED}}, // .ENCLU @@ -7075,25 +7075,25 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .WRPKRU {implicit_rd={.RAX, .RCX, .RDX}}, // .INCSSPD - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, // .INCSSPQ - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, // .RDSSPD - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, // .RDSSPQ - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, // .SAVEPREVSSP {side_effects={.CET}}, // .RSTORSSP {side_effects={.CET}}, // .WRSSD - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRSSQ - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRUSSD - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRUSSQ - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .SETSSBSY {side_effects={.CET}}, // .CLRSSBSY @@ -7127,41 +7127,41 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .XRSTORS64 {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // .PREFETCHT0 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHT1 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHT2 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHNTA - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHW - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .CLFLUSHOPT - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .CLWB - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .CLDEMOTE - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .BSWAP - {written={.OP0}, read={.OP0}}, - {written={.OP0}, read={.OP0}}, + {written={0}, read={0}}, + {written={0}, read={0}}, // .CMPXCHG - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .CMPXCHG8B - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .CMPXCHG16B - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .XADD - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BOUND - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, // .ENTER {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, // .LEAVE @@ -7171,20 +7171,20 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .XLATB {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // .MOVBE - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .RDRAND - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .RDSEED - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, } @(rodata) From 80d7f6462a7672d53adfd55c40b68c00da093c83 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:33:49 +0100 Subject: [PATCH 81/92] Minor clean up --- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 34 +++++++++---------- src/asm_tables_amd64.cpp | 33 +++++++++--------- 2 files changed, 34 insertions(+), 33 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 57622c1a7..84df9b951 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -267,18 +267,18 @@ main :: proc() { bool reads_mem; SideEffectFlags side_effects; - bool implies_clobber_flags() { + bool implies_clobber_flags() const { u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; return ((flags_wr | flags_undef) & FLAGS_MASK) != 0; } - bool implies_clobber_memory() { + bool implies_clobber_memory() const { return writes_mem || reads_mem || (side_effects & (SideEffectFlag_FENCE | SideEffectFlag_CACHE | SideEffectFlag_SERIALIZING)) != 0; } - bool implies_side_effects() { + bool implies_side_effects() const { u16 const VOLATILE_SE = SideEffectFlag_FENCE | SideEffectFlag_SERIALIZING | @@ -297,7 +297,7 @@ main :: proc() { strings.write_string(&sb, "\n"); - strings.write_string(&sb, "\tstatic u16 const register_codes[REG_COUNT];\n") + strings.write_string(&sb, "\tstatic u16 const register_codes [REG_COUNT];\n") strings.write_string(&sb, "\tstatic String const register_strings[REG_COUNT];\n") strings.write_string(&sb, "\n\n") @@ -361,13 +361,13 @@ main :: proc() { } { bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "lock_ok") - strings.write_string(&sb, "\t\tbool lock_ok () const { ") + strings.write_string(&sb, "\t\tbool lock_ok () const { ") fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) strings.write_string(&sb, " }\n") } { bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "rep_ok") - strings.write_string(&sb, "\t\tbool rep_ok () const { ") + strings.write_string(&sb, "\t\tbool rep_ok () const { ") fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) strings.write_string(&sb, " }\n") } @@ -382,10 +382,10 @@ main :: proc() { } strings.write_string(&sb, "\n\n") - fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs[%d];\n", len(raw_encode_runs)) - fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms[%d];\n", len(raw_encode_forms)) - fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_forms[%d];\n", len(raw_clobber_forms)) - + fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs [%d];\n", len(raw_encode_runs)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms [%d];\n", len(raw_encode_forms)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_forms[%d];\n", len(raw_clobber_forms)) + strings.write_string(&sb, "\n") strings.write_string(&sb, "\tStringMap mnemonic_map;\n") strings.write_string(&sb, "\tStringMap prefix_map;\n") strings.write_string(&sb, "\tStringMap register_map;\n") @@ -458,7 +458,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - AsmOperandKind kind_from_operand_type(OperandType type) { + AsmOperandKind kind_from_operand_type(OperandType type) const { switch (type) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_SREG: case OP_CR: case OP_DR: @@ -495,7 +495,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - AsmRegClass reg_class_from_operand_type(OperandType type) { + AsmRegClass reg_class_from_operand_type(OperandType type) const { switch (type) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: @@ -540,7 +540,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - bool operand_type_is_implicit(OperandType t) { + bool operand_type_is_implicit(OperandType t) const { switch (t) { case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: @@ -556,7 +556,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - AsmRegClass operand_type_reg_class(OperandType t) { + AsmRegClass operand_type_reg_class(OperandType t) const { switch (t) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: @@ -580,7 +580,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - u16 operand_type_bit_width(OperandType t) { + u16 operand_type_bit_width(OperandType t) const { switch (t) { case OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8; case OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16; @@ -604,7 +604,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - int form_explicit_slot(Encoding const &form, int explicit_index) { + int form_explicit_slot(Encoding const &form, int explicit_index) const { int seen = 0; for (int j = 0; j < gb_count_of(form.ops); j++) { auto t = form.ops[j]; @@ -626,7 +626,7 @@ main :: proc() { strings.write_string(&sb, "\n\n") strings.write_string(&sb, """ - bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) { + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const { PrefixKind kind = PrefixKind_None; if (prefix != 0) { switch (prefix) { diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 7a734b2db..69f461ce4 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -267,18 +267,18 @@ struct Asm_amd64 { bool reads_mem; SideEffectFlags side_effects; - bool implies_clobber_flags() { + bool implies_clobber_flags() const { u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF| ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF; return ((flags_wr | flags_undef) & FLAGS_MASK) != 0; } - bool implies_clobber_memory() { + bool implies_clobber_memory() const { return writes_mem || reads_mem || (side_effects & (SideEffectFlag_FENCE | SideEffectFlag_CACHE | SideEffectFlag_SERIALIZING)) != 0; } - bool implies_side_effects() { + bool implies_side_effects() const { u16 const VOLATILE_SE = SideEffectFlag_FENCE | SideEffectFlag_SERIALIZING | @@ -293,7 +293,7 @@ struct Asm_amd64 { return ((side_effects & VOLATILE_SE) != 0); } }; - static u16 const register_codes[REG_COUNT]; + static u16 const register_codes [REG_COUNT]; static String const register_strings[REG_COUNT]; @@ -393,8 +393,8 @@ struct Asm_amd64 { bool has_implicit () const { return ((flags>>21u)&1) != 0; } u8 explicit_count() const { return cast(u8)((flags>>18u)&((1u<<3)-1)); } u8 op_count () const { return cast(u8)((flags>>22u)&((1u<<3)-1)); } - bool lock_ok () const { return ((flags>>14u)&1) != 0; } - bool rep_ok () const { return ((flags>>15u)&1) != 0; } + bool lock_ok () const { return ((flags>>14u)&1) != 0; } + bool rep_ok () const { return ((flags>>15u)&1) != 0; } }; #pragma pack(pop) GB_STATIC_ASSERT(gb_size_of(Encoding) == 16); @@ -407,9 +407,10 @@ struct Asm_amd64 { }; - static EncodeRun const raw_encode_runs[1192]; - static u8 const raw_encode_forms[38320]; - static u8 const raw_clobber_forms[38320]; + static EncodeRun const raw_encode_runs [1192]; + static u8 const raw_encode_forms [38320]; + static u8 const raw_clobber_forms[38320]; + StringMap mnemonic_map; StringMap prefix_map; StringMap register_map; @@ -477,7 +478,7 @@ struct Asm_amd64 { return 0; } - AsmOperandKind kind_from_operand_type(OperandType type) { + AsmOperandKind kind_from_operand_type(OperandType type) const { switch (type) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_SREG: case OP_CR: case OP_DR: @@ -511,7 +512,7 @@ struct Asm_amd64 { } } - AsmRegClass reg_class_from_operand_type(OperandType type) { + AsmRegClass reg_class_from_operand_type(OperandType type) const { switch (type) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: @@ -553,7 +554,7 @@ struct Asm_amd64 { } } - bool operand_type_is_implicit(OperandType t) { + bool operand_type_is_implicit(OperandType t) const { switch (t) { case OP_AL_IMPL: case OP_AX_IMPL: case OP_EAX_IMPL: case OP_RAX_IMPL: @@ -565,7 +566,7 @@ struct Asm_amd64 { return false; } - AsmRegClass operand_type_reg_class(OperandType t) { + AsmRegClass operand_type_reg_class(OperandType t) const { switch (t) { case OP_R8: case OP_R16: case OP_R32: case OP_R64: case OP_RM8: case OP_RM16: case OP_RM32: case OP_RM64: @@ -584,7 +585,7 @@ struct Asm_amd64 { return AsmRegClass_Unknown; // OP_M*, OP_IMM*, OP_REL*, OP_SREG/CR/DR/MM/STi, moffs, ptr, m16_16... : no GPR/XMM class constraint here } - u16 operand_type_bit_width(OperandType t) { + u16 operand_type_bit_width(OperandType t) const { switch (t) { case OP_R8: case OP_RM8: case OP_M8: case OP_AL_IMPL: case OP_CL_IMPL: case OP_K_M8: return 8; case OP_R16: case OP_RM16: case OP_M16: case OP_AX_IMPL: case OP_DX_IMPL: case OP_K_M16: return 16; @@ -604,7 +605,7 @@ struct Asm_amd64 { return 0; // OP_M (sizeless), OP_K (opmask width is data-dependent), OP_ONE_IMPL, moffs, ptr, sreg/cr/dr, etc. } - int form_explicit_slot(Encoding const &form, int explicit_index) { + int form_explicit_slot(Encoding const &form, int explicit_index) const { int seen = 0; for (int j = 0; j < gb_count_of(form.ops); j++) { auto t = form.ops[j]; @@ -622,7 +623,7 @@ struct Asm_amd64 { return -1; } - bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) { + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const { PrefixKind kind = PrefixKind_None; if (prefix != 0) { switch (prefix) { From 18df1ed23eaa3cdd7bf30af355cbbff24d2000c7 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:44:35 +0100 Subject: [PATCH 82/92] Correct clobber_table.odin --- .../isa/x86/tablegen/clobber_table.odin | 20 +++++++++---------- .../x86/tablegen/generated/encode_tables.odin | 12 +++++------ src/asm_tables_amd64.cpp | 8 ++++---- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index 2d59cce41..a5d7a0ab7 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -4386,16 +4386,16 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, }, .FCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m32 + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m64 + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // ST(i) + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // no operand (ST(1)) }, .FCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m32 + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m64 + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // ST(i) + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // no operand (ST(1)) }, .FCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, @@ -4714,7 +4714,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.CET}}, }, .RSTORSSP = { // CET shadow-stack management - {side_effects={.CET}}, + {read={0}, reads_mem=true, writes_mem=true, side_effects={.CET}}, // reads restore token, writes previous-ssp token }, .WRSSD = { // writes to shadow stack {read={0, 1}, writes_mem=true, side_effects={.CET}}, @@ -4732,7 +4732,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.CET}}, }, .CLRSSBSY = { // CET shadow-stack management - {side_effects={.CET}}, + {read={0}, reads_mem=true, writes_mem=true, side_effects={.CET}}, // reads token, clears busy bit }, .ENDBR64 = { // CET landing pad; NOP-like {side_effects={.HINT, .CET}}, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 041487e87..71b6831ec 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -6860,13 +6860,13 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .FCMOVNU {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // .FCOM - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // .FCOMP - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // .FCOMPP @@ -7085,7 +7085,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .SAVEPREVSSP {side_effects={.CET}}, // .RSTORSSP - {side_effects={.CET}}, + {read={0}, writes_mem=true, reads_mem=true, side_effects={.CET}}, // .WRSSD {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRSSQ @@ -7097,7 +7097,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .SETSSBSY {side_effects={.CET}}, // .CLRSSBSY - {side_effects={.CET}}, + {read={0}, writes_mem=true, reads_mem=true, side_effects={.CET}}, // .ENDBR64 {side_effects={.HINT, .CET}}, // .ENDBR32 diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index 69f461ce4..ebb9b7411 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -2001,8 +2001,8 @@ u8 const Asm_amd64::raw_clobber_forms[38320] = { 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0b, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0b, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0b, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0b, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2033,8 +2033,8 @@ u8 const Asm_amd64::raw_clobber_forms[38320] = { 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, - 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x38, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, From 8d33a47fabe8d31b6ebd383ffce581619f49f5b1 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:54:45 +0100 Subject: [PATCH 83/92] Improve comment for the `CLOBBER_TABLE` --- core/rexcode/isa/x86/tablegen/clobber_table.odin | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index a5d7a0ab7..e13d2e8fb 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -15,10 +15,13 @@ // 3. Per-form memory. writes_mem/reads_mem keep the union's DIRECTION but are // asserted on a form only when that form actually carries a memory-capable // operand, OR the instruction addresses memory implicitly (stack, string, -// XLAT table, MASKMOVDQU/[rDI] store, VMCS, shadow stack). Consequently -// register-only forms of otherwise-memory instructions (e.g. MOV r,imm; -// FADD ST(0),ST(i); FST ST(i); MOVLHPS; PEXTRW r32,xmm) no longer carry the -// blanket memory flag the union used. +// XLAT table, MASKMOVDQU/[rDI] store, VMCS). Consequently register-only +// forms of otherwise-memory instructions (e.g. MOV r,imm; FADD ST(0),ST(i); +// FST ST(i); MOVLHPS; PEXTRW r32,xmm) no longer carry the blanket memory +// flag the union used. Shadow-stack accesses are not implicit: the +// shadow-stack instructions that touch memory (WRSS/WRUSS/RSTORSSP/CLRSSBSY) +// all do so through an explicit m64 operand and are covered by the +// memory-capable-operand branch above. // 4. Family splits that the union could only approximate: // IMUL -- 1-operand form writes RDX:RAX implicitly (r/m8 -> AX only); // 2-operand form is OP0 *= OP1; 3-operand form is OP0 = OP1 * imm @@ -28,7 +31,10 @@ // SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD -- only the CL form reads RCX; // the 1/imm8 forms do not. // Flags and side_effects are uniform across a mnemonic's forms and are carried -// through unchanged. +// through unchanged, EXCEPT where a single mnemonic aliases two distinct +// instructions: MOVSD and CMPSD each name both a string operation and an SSE +// scalar-double operation, so their string form and their SSE form carry +// different flags and side_effects. // // INVARIANT preserved: a form is a freely-eliminable no-op iff every clobber set // is empty AND side_effects == {} (only .NOP and the .INVALID sentinel qualify). From e0d83003997398f5553459c8e7b8202c4f51a9c8 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 11:58:49 +0100 Subject: [PATCH 84/92] Keep compiler happy --- src/llvm_backend_asm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index fce7eccf9..4016ad839 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -731,8 +731,8 @@ gb_internal lbValue lb_emit_asm_template_call(lbProcedure *p, Entity *entity, Ar generator = &generator_amd64; } else { compiler_error("Architecture does not support asm templates"); - return {}; } + GB_ASSERT(generator != nullptr); generator->init(entity); return generator->emit_call(p, args); } \ No newline at end of file From 6e17e7a2de9b149a8c08214c3f5c89b6ef225a6d Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 13:19:23 +0100 Subject: [PATCH 85/92] Add missing x86 instructions --- core/rexcode/isa/x86/mnemonics.odin | 78 ++ .../isa/x86/tablegen/clobber_table.odin | 163 +++ .../isa/x86/tablegen/encoding_table.odin | 179 ++++ .../x86/tablegen/generated/decode_tables.odin | 995 ++++++++++-------- .../x86/tablegen/generated/encode_tables.odin | 256 ++++- .../isa/x86/tables/x86.encode_forms.bin | Bin 38320 -> 39216 bytes .../isa/x86/tables/x86.encode_recipes.bin | Bin 28740 -> 29412 bytes .../isa/x86/tables/x86.encode_runs.bin | Bin 9536 -> 9904 bytes core/rexcode/isa/x86/tables/x86.idx_0f.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f38.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f3a.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.legacy.bin | Bin 25400 -> 26520 bytes src/asm_tables_amd64.cpp | 59 +- 13 files changed, 1252 insertions(+), 478 deletions(-) diff --git a/core/rexcode/isa/x86/mnemonics.odin b/core/rexcode/isa/x86/mnemonics.odin index e654bcd95..dc65bc3b2 100644 --- a/core/rexcode/isa/x86/mnemonics.odin +++ b/core/rexcode/isa/x86/mnemonics.odin @@ -1307,4 +1307,82 @@ Mnemonic :: enum u16 { MOVBE, RDRAND, RDSEED, + + // ------------------------------------------------------------------------- + // SECTION: 4.28 Additional System / GPR Instructions + // ------------------------------------------------------------------------- + SWAPGS, + MONITOR, + MWAIT, + CLAC, + STAC, + RDFSBASE, + RDGSBASE, + WRFSBASE, + WRGSBASE, + PTWRITE, + RDPID, + WBNOINVD, + SERIALIZE, + PREFETCH, + + // ------------------------------------------------------------------------- + // SECTION: 4.29 WAITPKG Instructions + // ------------------------------------------------------------------------- + TPAUSE, + UMONITOR, + UMWAIT, + + // ------------------------------------------------------------------------- + // SECTION: 4.30 Direct Store / Enqueue Store Instructions + // ------------------------------------------------------------------------- + MOVDIRI, + MOVDIR64B, + ENQCMD, + ENQCMDS, + + // ------------------------------------------------------------------------- + // SECTION: 4.31 Remote Atomic Operations (RAO-INT) + // ------------------------------------------------------------------------- + AADD, + AAND, + AOR, + AXOR, + + // ------------------------------------------------------------------------- + // SECTION: 4.32 Restricted Transactional Memory (RTM) + // ------------------------------------------------------------------------- + XEND, + XTEST, + + // ------------------------------------------------------------------------- + // SECTION: 4.33 AMD SVM (Secure Virtual Machine) Instructions + // ------------------------------------------------------------------------- + VMRUN, + VMMCALL, + VMLOAD, + VMSAVE, + STGI, + CLGI, + SKINIT, + INVLPGA, + INVLPGB, + TLBSYNC, + + // ------------------------------------------------------------------------- + // SECTION: 4.34 AMD SEV-SNP Instructions + // ------------------------------------------------------------------------- + PVALIDATE, + RMPADJUST, + RMPUPDATE, + PSMASH, + + // ------------------------------------------------------------------------- + // SECTION: 4.35 AMD Miscellaneous Instructions + // ------------------------------------------------------------------------- + CLZERO, + MONITORX, + MWAITX, + RDPRU, + MCOMMIT, } diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index e13d2e8fb..c241bb22e 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -4870,4 +4870,167 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, + // 8.23 Additional System / GPR Encodings + .SWAPGS = { // privileged; swaps GS.base with IA32_KERNEL_GS_BASE + {side_effects={.PRIVILEGED}}, + }, + .MONITOR = { // arms address monitor for [rAX]; ECX=extensions, EDX=hints + {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, + }, + .MWAIT = { // EAX=hints, ECX=extensions; enters optimized wait + {implicit_rd={.RAX, .RCX}, side_effects={.HALT}}, + }, + .CLAC = { // clears EFLAGS.AC (not modeled in Clobber_Flags); CPL0 + {side_effects={.PRIVILEGED}}, + }, + .STAC = { // sets EFLAGS.AC (not modeled in Clobber_Flags); CPL0 + {side_effects={.PRIVILEGED}}, + }, + .RDFSBASE = { + {written={0}}, + {written={0}}, + }, + .RDGSBASE = { + {written={0}}, + {written={0}}, + }, + .WRFSBASE = { + {read={0}}, + {read={0}}, + }, + .WRGSBASE = { + {read={0}}, + {read={0}}, + }, + .PTWRITE = { // writes source to a PT trace packet; no flags + {read={0}, reads_mem=true}, + {read={0}, reads_mem=true}, + }, + .RDPID = { // dest <- IA32_TSC_AUX + {written={0}}, + }, + .WBNOINVD = { // privileged; writes back caches without invalidation + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SERIALIZE = { // serializes execution; no register/flag clobber + {side_effects={.SERIALIZING}}, + }, + .PREFETCH = { // cache hint; no register or flag clobber + {read={0}, reads_mem=true, side_effects={.HINT}}, + }, + + // 8.24 WAITPKG Encodings + .TPAUSE = { // reads control r32 + EDX:EAX deadline; CF <- result + {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, + }, + .UMONITOR = { // arms address monitor for [reg] + {read={0}, reads_mem=true}, + }, + .UMWAIT = { // reads control r32 + EDX:EAX deadline; CF <- result + {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, + }, + + // 8.25 Direct Store / Enqueue Store Encodings + .MOVDIRI = { // direct store of source register to memory + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + }, + .MOVDIR64B = { // 64-byte direct store: reads m512, writes [reg] + {read={0}, implicit_rd={.RAX}, reads_mem=true, writes_mem=true}, + }, + .ENQCMD = { // enqueue store: reads m512, writes to device [reg]; ZF <- status + {read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}}, + }, + .ENQCMDS = { // supervisor enqueue store; ZF <- status + {read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}}, + }, + + // 8.26 Remote Atomic Operation (RAO-INT) Encodings + .AADD = { // atomic [mem] += reg; no flags, no result loaded + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + }, + .AAND = { // atomic [mem] &= reg + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + }, + .AOR = { // atomic [mem] |= reg + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + }, + .AXOR = { // atomic [mem] ^= reg + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + }, + + // 8.27 Restricted Transactional Memory (RTM) Encodings + .XEND = { // commits transaction; may transfer control on abort + {side_effects={.CONTROL}}, + }, + .XTEST = { // ZF <- (not in transactional region) + {flags_wr={.ZF}}, + }, + + // 8.28 AMD SVM Encodings + .VMRUN = { // privileged; runs guest from VMCB at [rAX] + {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMMCALL = { // guest-to-hypervisor call + {side_effects={.PRIVILEGED}}, + }, + .VMLOAD = { // privileged; loads guest state from VMCB at [rAX] + {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMSAVE = { // privileged; saves guest state to VMCB at [rAX] + {implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .STGI = { // privileged; sets global interrupt flag + {side_effects={.PRIVILEGED}}, + }, + .CLGI = { // privileged; clears global interrupt flag + {side_effects={.PRIVILEGED}}, + }, + .SKINIT = { // privileged; secure init from SLB at EAX + {implicit_rd={.RAX}, side_effects={.PRIVILEGED}}, + }, + .INVLPGA = { // privileged; invalidates TLB entry [rAX] for ASID ECX + {implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}}, + }, + .INVLPGB = { // privileged; rAX=va, ECX=count, EDX=flags + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}}, + }, + .TLBSYNC = { // privileged; synchronizes broadcast TLB invalidations + {side_effects={.PRIVILEGED}}, + }, + + // 8.29 AMD SEV-SNP Encodings + .PVALIDATE = { // rAX=addr, ECX=size, EDX=validate; EAX<-rc, flags set + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .RMPADJUST = { // privileged; rAX=addr, RCX=attrs, RDX=level; EAX<-rc + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .RMPUPDATE = { // privileged; rAX=addr, RCX=ptr to RMP state; EAX<-rc + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .PSMASH = { // privileged; rAX=addr; EAX<-rc; splits 2M RMP entry + {implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + + // 8.30 AMD Miscellaneous Encodings + .CLZERO = { // zeroes the cache line at [rAX] + {implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}}, + }, + .MONITORX = { // arms address monitor for [rAX] with timer (EBX) + {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, + }, + .MWAITX = { // EAX=hints, ECX=extensions, EBX=timer; enters wait + {implicit_rd={.RAX, .RCX, .RBX}, side_effects={.HALT}}, + }, + .RDPRU = { // ECX selects register; EDX:EAX <- value + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + }, + .MCOMMIT = { // commits pending stores; CF <- error status + {flags_wr={.CF}, side_effects={.FENCE}}, + }, } diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index 9fc398807..9390789f7 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -4917,4 +4917,183 @@ ENCODING_TABLE := [Mnemonic][]Encoding{ {.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, }, + // ------------------------------------------------------------------------- + // SECTION: 8.23 Additional System / GPR Encodings + // ------------------------------------------------------------------------- + .SWAPGS = { // 0F 01 F8 + {.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF8, {esc=._0F}}, + }, + .MONITOR = { // 0F 01 C8 + {.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC8, {esc=._0F}}, + }, + .MWAIT = { // 0F 01 C9 + {.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC9, {esc=._0F}}, + }, + .CLAC = { // 0F 01 CA + {.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCA, {esc=._0F}}, + }, + .STAC = { // 0F 01 CB + {.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCB, {esc=._0F}}, + }, + .RDFSBASE = { // F3 0F AE /0 + {.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + }, + .RDGSBASE = { // F3 0F AE /1 + {.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + }, + .WRFSBASE = { // F3 0F AE /2 + {.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + }, + .WRGSBASE = { // F3 0F AE /3 + {.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + }, + .PTWRITE = { // F3 0F AE /4 + {.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + }, + .RDPID = { // F3 0F C7 /7 (r64 in 64-bit mode, no REX.W) + {.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + }, + .WBNOINVD = { // F3 0F 09 + {.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=PREFIX_F3}}, + }, + .SERIALIZE = { // NP 0F 01 E8 + {.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F}}, + }, + .PREFETCH = { // 0F 0D /0 + {.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.24 WAITPKG Encodings + // ------------------------------------------------------------------------- + .TPAUSE = { // 66 0F AE /6 + {.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}}, + }, + .UMONITOR = { // F3 0F AE /6 + {.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + }, + .UMWAIT = { // F2 0F AE /6 + {.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F2}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.25 Direct Store / Enqueue Store Encodings + // ------------------------------------------------------------------------- + .MOVDIRI = { // NP 0F 38 F9 /r (store r -> m) + {.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38}}, + {.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true}}, + }, + .MOVDIR64B = { // 66 0F 38 F8 /r (r=dest addr, m512=src) + {.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_66}}, + }, + .ENQCMD = { // F2 0F 38 F8 /r + {.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F2}}, + }, + .ENQCMDS = { // F3 0F 38 F8 /r + {.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F3}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.26 Remote Atomic Operation (RAO-INT) Encodings + // ------------------------------------------------------------------------- + .AADD = { // NP 0F 38 FC /r + {.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38}}, + {.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true}}, + }, + .AAND = { // 66 0F 38 FC /r + {.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66}}, + {.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, + }, + .AOR = { // F2 0F 38 FC /r + {.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2}}, + {.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, + }, + .AXOR = { // F3 0F 38 FC /r + {.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3}}, + {.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.27 Restricted Transactional Memory (RTM) Encodings + // ------------------------------------------------------------------------- + .XEND = { // NP 0F 01 D5 + {.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD5, {esc=._0F}}, + }, + .XTEST = { // NP 0F 01 D6 + {.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD6, {esc=._0F}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.28 AMD SVM Encodings + // ------------------------------------------------------------------------- + .VMRUN = { // 0F 01 D8 + {.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD8, {esc=._0F}}, + }, + .VMMCALL = { // 0F 01 D9 + {.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD9, {esc=._0F}}, + }, + .VMLOAD = { // 0F 01 DA + {.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDA, {esc=._0F}}, + }, + .VMSAVE = { // 0F 01 DB + {.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDB, {esc=._0F}}, + }, + .STGI = { // 0F 01 DC + {.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDC, {esc=._0F}}, + }, + .CLGI = { // 0F 01 DD + {.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDD, {esc=._0F}}, + }, + .SKINIT = { // 0F 01 DE + {.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDE, {esc=._0F}}, + }, + .INVLPGA = { // 0F 01 DF + {.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDF, {esc=._0F}}, + }, + .INVLPGB = { // NP 0F 01 FE + {.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F}}, + }, + .TLBSYNC = { // NP 0F 01 FF + {.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.29 AMD SEV-SNP Encodings + // ------------------------------------------------------------------------- + .PVALIDATE = { // F2 0F 01 FF + {.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F2}}, + }, + .RMPADJUST = { // F3 0F 01 FE + {.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F3}}, + }, + .RMPUPDATE = { // F2 0F 01 FE + {.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F2}}, + }, + .PSMASH = { // F3 0F 01 FF + {.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F3}}, + }, + + // ------------------------------------------------------------------------- + // SECTION: 8.30 AMD Miscellaneous Encodings + // ------------------------------------------------------------------------- + .CLZERO = { // 0F 01 FC + {.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFC, {esc=._0F}}, + }, + .MONITORX = { // NP 0F 01 FA + {.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F}}, + }, + .MWAITX = { // NP 0F 01 FB + {.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFB, {esc=._0F}}, + }, + .RDPRU = { // 0F 01 FD + {.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFD, {esc=._0F}}, + }, + .MCOMMIT = { // F3 0F 01 FA + {.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F, prefix=PREFIX_F3}}, + }, } diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 5d4939325..fc27b7a15 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -144,59 +144,59 @@ SIB_TABLE := [256]lib.SIB_Info{ } @(rodata) -LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ +LEGACY_DECODE_ENTRIES := [1326]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -210,37 +210,37 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, @@ -249,8 +249,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -260,18 +260,18 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -282,14 +282,14 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -303,9 +303,9 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -321,14 +321,14 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -336,22 +336,22 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, @@ -377,20 +377,20 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, + {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, @@ -416,28 +416,28 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, - {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, + {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, @@ -450,11 +450,11 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -482,9 +482,9 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xCC, 0xFF, .INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -565,8 +565,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0x03, .FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xC0, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -599,8 +599,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFC, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFD, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFE, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -625,8 +625,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xDB, 0xD8, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xE2, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE2, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xE3, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE3, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDB, 0xE3, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE8, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xF0, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, @@ -689,8 +689,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xDF, 0x06, .FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDF, 0xC0, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xDF, 0xE0, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE0, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDF, 0xE0, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE8, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xF0, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, @@ -760,8 +760,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -769,17 +769,17 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x05, .VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0xC0, .ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -787,26 +787,49 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0xC2, .VMLAUNCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xC3, .VMRESUME, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xC4, .VMXOFF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xC8, .MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xC9, .MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xCA, .CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xCB, .STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xCF, .ENCLS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xD0, .XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xD1, .XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xD4, .VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xD5, .XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xD6, .XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xD7, .ENCLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xD8, .VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xD9, .VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDA, .VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDB, .VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDC, .STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDD, .CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDE, .SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xDF, .INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xE8, .SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xEE, .RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xEF, .WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xF8, .SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xF9, .RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFA, .MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFB, .MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFC, .CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFD, .RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFE, .INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x01, 0xFF, .TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x08, 0xFF, .INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x09, 0xFF, .WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x0B, 0xFF, .UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x0D, 0x00, .PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -824,8 +847,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1039,12 +1062,12 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x04, .XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1057,9 +1080,9 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0xAF, 0xFF, .IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, @@ -1096,29 +1119,29 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}}, + {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 1, 0x10, 0xFF, .MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x11, 0xFF, .MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1182,6 +1205,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xAE, 0x06, .TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x07, .CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, @@ -1241,12 +1265,16 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 2, 0x01, 0x05, .RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x01, 0xE8, .SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x01, 0xEA, .SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, + {._0F, 2, 0x01, 0xFA, .MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, + {._0F, 2, 0x01, 0xFE, .RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, + {._0F, 2, 0x01, 0xFF, .PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, + {._0F, 2, 0x09, 0xFF, .WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x10, 0xFF, .MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0xFA, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x1E, 0xFB, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, @@ -1270,9 +1298,20 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 2, 0x70, 0xFF, .PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0x7E, 0xFF, .MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x7F, 0xFF, .MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x00, .RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x00, .RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x06, .UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, @@ -1284,7 +1323,10 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xC7, 0x07, .RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x01, 0xFE, .RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=3}}, + {._0F, 3, 0x01, 0xFF, .PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=3}}, {._0F, 3, 0x10, 0xFF, .MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x11, 0xFF, .MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1305,6 +1347,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xAE, 0x06, .UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=3, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 3, 0xC2, 0xFF, .CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1316,13 +1359,17 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F38, 0, 0xCC, 0xFF, .SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xCD, 0xFF, .SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xFC, 0xFF, .AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xFC, 0xFF, .AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x00, 0xFF, .PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x01, 0xFF, .PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x02, 0xFF, .PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, @@ -1382,13 +1429,22 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF8, 0xFF, .MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xFC, 0xFF, .AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xFC, 0xFF, .AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xF8, 0xFF, .ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF8, 0xFF, .ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xFC, 0xFF, .AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xFC, 0xFF, .AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x08, 0xFF, .ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, {._0F3A, 1, 0x09, 0xFF, .ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, @@ -2727,422 +2783,433 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ DECODE_INDEX_ESC_0F := [4][256]lib.Decode_Index{ { // prefix = none 0x00 = { 614, 10}, - 0x01 = { 624, 26}, - 0x02 = { 650, 3}, - 0x03 = { 653, 3}, - 0x05 = { 656, 1}, - 0x06 = { 657, 1}, - 0x07 = { 658, 1}, - 0x08 = { 659, 1}, - 0x09 = { 660, 1}, - 0x0B = { 661, 1}, - 0x0D = { 662, 1}, - 0x10 = { 663, 1}, - 0x11 = { 664, 1}, - 0x12 = { 665, 2}, - 0x13 = { 667, 1}, - 0x14 = { 668, 1}, - 0x15 = { 669, 1}, - 0x16 = { 670, 2}, - 0x17 = { 672, 1}, - 0x18 = { 673, 4}, - 0x1C = { 677, 1}, - 0x1F = { 678, 3}, - 0x20 = { 681, 1}, - 0x21 = { 682, 1}, - 0x22 = { 683, 1}, - 0x23 = { 684, 1}, - 0x28 = { 685, 1}, - 0x29 = { 686, 1}, - 0x2B = { 687, 1}, - 0x2E = { 688, 1}, - 0x2F = { 689, 1}, - 0x30 = { 690, 1}, - 0x31 = { 691, 1}, - 0x32 = { 692, 1}, - 0x33 = { 693, 1}, - 0x34 = { 694, 1}, - 0x35 = { 695, 1}, - 0x40 = { 696, 3}, - 0x41 = { 699, 3}, - 0x42 = { 702, 9}, - 0x43 = { 711, 9}, - 0x44 = { 720, 6}, - 0x45 = { 726, 6}, - 0x46 = { 732, 6}, - 0x47 = { 738, 6}, - 0x48 = { 744, 3}, - 0x49 = { 747, 3}, - 0x4A = { 750, 6}, - 0x4B = { 756, 6}, - 0x4C = { 762, 6}, - 0x4D = { 768, 6}, - 0x4E = { 774, 6}, - 0x4F = { 780, 6}, - 0x50 = { 786, 2}, - 0x51 = { 788, 1}, - 0x52 = { 789, 1}, - 0x53 = { 790, 1}, - 0x54 = { 791, 1}, - 0x55 = { 792, 1}, - 0x56 = { 793, 1}, - 0x57 = { 794, 1}, - 0x58 = { 795, 1}, - 0x59 = { 796, 1}, - 0x5A = { 797, 1}, - 0x5B = { 798, 1}, - 0x5C = { 799, 1}, - 0x5D = { 800, 1}, - 0x5E = { 801, 1}, - 0x5F = { 802, 1}, - 0x6E = { 803, 1}, - 0x6F = { 804, 1}, - 0x70 = { 805, 1}, - 0x78 = { 806, 1}, - 0x79 = { 807, 1}, - 0x7E = { 808, 1}, - 0x7F = { 809, 1}, - 0x80 = { 810, 1}, - 0x81 = { 811, 1}, - 0x82 = { 812, 3}, - 0x83 = { 815, 3}, - 0x84 = { 818, 2}, - 0x85 = { 820, 2}, - 0x86 = { 822, 2}, - 0x87 = { 824, 2}, - 0x88 = { 826, 1}, - 0x89 = { 827, 1}, - 0x8A = { 828, 2}, - 0x8B = { 830, 2}, - 0x8C = { 832, 2}, - 0x8D = { 834, 2}, - 0x8E = { 836, 2}, - 0x8F = { 838, 2}, - 0x90 = { 840, 1}, - 0x91 = { 841, 1}, - 0x92 = { 842, 3}, - 0x93 = { 845, 3}, - 0x94 = { 848, 2}, - 0x95 = { 850, 2}, - 0x96 = { 852, 2}, - 0x97 = { 854, 2}, - 0x98 = { 856, 1}, - 0x99 = { 857, 1}, - 0x9A = { 858, 2}, - 0x9B = { 860, 2}, - 0x9C = { 862, 2}, - 0x9D = { 864, 2}, - 0x9E = { 866, 2}, - 0x9F = { 868, 2}, - 0xA0 = { 870, 1}, - 0xA1 = { 871, 1}, - 0xA2 = { 872, 1}, - 0xA3 = { 873, 3}, - 0xA4 = { 876, 3}, - 0xA5 = { 879, 3}, - 0xA8 = { 882, 1}, - 0xA9 = { 883, 1}, - 0xAA = { 884, 1}, - 0xAB = { 885, 3}, - 0xAC = { 888, 3}, - 0xAD = { 891, 3}, - 0xAE = { 894, 14}, - 0xAF = { 908, 3}, - 0xB0 = { 911, 1}, - 0xB1 = { 912, 3}, - 0xB3 = { 915, 3}, - 0xB6 = { 918, 3}, - 0xB7 = { 921, 2}, - 0xB9 = { 923, 1}, - 0xBA = { 924, 12}, - 0xBB = { 936, 3}, - 0xBC = { 939, 3}, - 0xBD = { 942, 3}, - 0xBE = { 945, 3}, - 0xBF = { 948, 2}, - 0xC0 = { 950, 1}, - 0xC1 = { 951, 3}, - 0xC2 = { 954, 1}, - 0xC6 = { 955, 1}, - 0xC7 = { 956, 16}, - 0xC8 = { 972, 2}, - 0xFF = { 974, 1}, + 0x01 = { 624, 48}, + 0x02 = { 672, 3}, + 0x03 = { 675, 3}, + 0x05 = { 678, 1}, + 0x06 = { 679, 1}, + 0x07 = { 680, 1}, + 0x08 = { 681, 1}, + 0x09 = { 682, 1}, + 0x0B = { 683, 1}, + 0x0D = { 684, 2}, + 0x10 = { 686, 1}, + 0x11 = { 687, 1}, + 0x12 = { 688, 2}, + 0x13 = { 690, 1}, + 0x14 = { 691, 1}, + 0x15 = { 692, 1}, + 0x16 = { 693, 2}, + 0x17 = { 695, 1}, + 0x18 = { 696, 4}, + 0x1C = { 700, 1}, + 0x1F = { 701, 3}, + 0x20 = { 704, 1}, + 0x21 = { 705, 1}, + 0x22 = { 706, 1}, + 0x23 = { 707, 1}, + 0x28 = { 708, 1}, + 0x29 = { 709, 1}, + 0x2B = { 710, 1}, + 0x2E = { 711, 1}, + 0x2F = { 712, 1}, + 0x30 = { 713, 1}, + 0x31 = { 714, 1}, + 0x32 = { 715, 1}, + 0x33 = { 716, 1}, + 0x34 = { 717, 1}, + 0x35 = { 718, 1}, + 0x40 = { 719, 3}, + 0x41 = { 722, 3}, + 0x42 = { 725, 9}, + 0x43 = { 734, 9}, + 0x44 = { 743, 6}, + 0x45 = { 749, 6}, + 0x46 = { 755, 6}, + 0x47 = { 761, 6}, + 0x48 = { 767, 3}, + 0x49 = { 770, 3}, + 0x4A = { 773, 6}, + 0x4B = { 779, 6}, + 0x4C = { 785, 6}, + 0x4D = { 791, 6}, + 0x4E = { 797, 6}, + 0x4F = { 803, 6}, + 0x50 = { 809, 2}, + 0x51 = { 811, 1}, + 0x52 = { 812, 1}, + 0x53 = { 813, 1}, + 0x54 = { 814, 1}, + 0x55 = { 815, 1}, + 0x56 = { 816, 1}, + 0x57 = { 817, 1}, + 0x58 = { 818, 1}, + 0x59 = { 819, 1}, + 0x5A = { 820, 1}, + 0x5B = { 821, 1}, + 0x5C = { 822, 1}, + 0x5D = { 823, 1}, + 0x5E = { 824, 1}, + 0x5F = { 825, 1}, + 0x6E = { 826, 1}, + 0x6F = { 827, 1}, + 0x70 = { 828, 1}, + 0x78 = { 829, 1}, + 0x79 = { 830, 1}, + 0x7E = { 831, 1}, + 0x7F = { 832, 1}, + 0x80 = { 833, 1}, + 0x81 = { 834, 1}, + 0x82 = { 835, 3}, + 0x83 = { 838, 3}, + 0x84 = { 841, 2}, + 0x85 = { 843, 2}, + 0x86 = { 845, 2}, + 0x87 = { 847, 2}, + 0x88 = { 849, 1}, + 0x89 = { 850, 1}, + 0x8A = { 851, 2}, + 0x8B = { 853, 2}, + 0x8C = { 855, 2}, + 0x8D = { 857, 2}, + 0x8E = { 859, 2}, + 0x8F = { 861, 2}, + 0x90 = { 863, 1}, + 0x91 = { 864, 1}, + 0x92 = { 865, 3}, + 0x93 = { 868, 3}, + 0x94 = { 871, 2}, + 0x95 = { 873, 2}, + 0x96 = { 875, 2}, + 0x97 = { 877, 2}, + 0x98 = { 879, 1}, + 0x99 = { 880, 1}, + 0x9A = { 881, 2}, + 0x9B = { 883, 2}, + 0x9C = { 885, 2}, + 0x9D = { 887, 2}, + 0x9E = { 889, 2}, + 0x9F = { 891, 2}, + 0xA0 = { 893, 1}, + 0xA1 = { 894, 1}, + 0xA2 = { 895, 1}, + 0xA3 = { 896, 3}, + 0xA4 = { 899, 3}, + 0xA5 = { 902, 3}, + 0xA8 = { 905, 1}, + 0xA9 = { 906, 1}, + 0xAA = { 907, 1}, + 0xAB = { 908, 3}, + 0xAC = { 911, 3}, + 0xAD = { 914, 3}, + 0xAE = { 917, 14}, + 0xAF = { 931, 3}, + 0xB0 = { 934, 1}, + 0xB1 = { 935, 3}, + 0xB3 = { 938, 3}, + 0xB6 = { 941, 3}, + 0xB7 = { 944, 2}, + 0xB9 = { 946, 1}, + 0xBA = { 947, 12}, + 0xBB = { 959, 3}, + 0xBC = { 962, 3}, + 0xBD = { 965, 3}, + 0xBE = { 968, 3}, + 0xBF = { 971, 2}, + 0xC0 = { 973, 1}, + 0xC1 = { 974, 3}, + 0xC2 = { 977, 1}, + 0xC6 = { 978, 1}, + 0xC7 = { 979, 16}, + 0xC8 = { 995, 2}, + 0xFF = { 997, 1}, }, { // prefix = 66 - 0x10 = { 975, 1}, - 0x11 = { 976, 1}, - 0x12 = { 977, 1}, - 0x13 = { 978, 1}, - 0x14 = { 979, 1}, - 0x15 = { 980, 1}, - 0x16 = { 981, 1}, - 0x17 = { 982, 1}, - 0x28 = { 983, 1}, - 0x29 = { 984, 1}, - 0x2B = { 985, 1}, - 0x2E = { 986, 1}, - 0x2F = { 987, 1}, - 0x50 = { 988, 2}, - 0x51 = { 990, 1}, - 0x54 = { 991, 1}, - 0x55 = { 992, 1}, - 0x56 = { 993, 1}, - 0x57 = { 994, 1}, - 0x58 = { 995, 1}, - 0x59 = { 996, 1}, - 0x5A = { 997, 1}, - 0x5B = { 998, 1}, - 0x5C = { 999, 1}, - 0x5D = {1000, 1}, - 0x5E = {1001, 1}, - 0x5F = {1002, 1}, - 0x60 = {1003, 1}, - 0x61 = {1004, 1}, - 0x62 = {1005, 1}, - 0x63 = {1006, 1}, - 0x64 = {1007, 1}, - 0x65 = {1008, 1}, - 0x66 = {1009, 1}, - 0x67 = {1010, 1}, - 0x68 = {1011, 1}, - 0x69 = {1012, 1}, - 0x6A = {1013, 1}, - 0x6B = {1014, 1}, - 0x6C = {1015, 1}, - 0x6D = {1016, 1}, - 0x6E = {1017, 2}, - 0x6F = {1019, 1}, - 0x70 = {1020, 1}, - 0x71 = {1021, 3}, - 0x72 = {1024, 3}, - 0x73 = {1027, 2}, - 0x74 = {1029, 1}, - 0x75 = {1030, 1}, - 0x76 = {1031, 1}, - 0x7C = {1032, 1}, - 0x7D = {1033, 1}, - 0x7E = {1034, 2}, - 0x7F = {1036, 1}, - 0xAE = {1037, 2}, - 0xC2 = {1039, 1}, - 0xC4 = {1040, 2}, - 0xC5 = {1042, 2}, - 0xC6 = {1044, 1}, - 0xC7 = {1045, 1}, - 0xD0 = {1046, 1}, - 0xD1 = {1047, 1}, - 0xD2 = {1048, 1}, - 0xD3 = {1049, 1}, - 0xD4 = {1050, 1}, - 0xD5 = {1051, 1}, - 0xD6 = {1052, 1}, - 0xD7 = {1053, 2}, - 0xD8 = {1055, 1}, - 0xD9 = {1056, 1}, - 0xDA = {1057, 1}, - 0xDB = {1058, 1}, - 0xDC = {1059, 1}, - 0xDD = {1060, 1}, - 0xDE = {1061, 1}, - 0xDF = {1062, 1}, - 0xE0 = {1063, 1}, - 0xE1 = {1064, 1}, - 0xE2 = {1065, 1}, - 0xE3 = {1066, 1}, - 0xE4 = {1067, 1}, - 0xE5 = {1068, 1}, - 0xE6 = {1069, 1}, - 0xE7 = {1070, 1}, - 0xE8 = {1071, 1}, - 0xE9 = {1072, 1}, - 0xEA = {1073, 1}, - 0xEB = {1074, 1}, - 0xEC = {1075, 1}, - 0xED = {1076, 1}, - 0xEE = {1077, 1}, - 0xEF = {1078, 1}, - 0xF1 = {1079, 1}, - 0xF2 = {1080, 1}, - 0xF3 = {1081, 1}, - 0xF4 = {1082, 1}, - 0xF5 = {1083, 1}, - 0xF6 = {1084, 1}, - 0xF7 = {1085, 1}, - 0xF8 = {1086, 1}, - 0xF9 = {1087, 1}, - 0xFA = {1088, 1}, - 0xFB = {1089, 1}, - 0xFC = {1090, 1}, - 0xFD = {1091, 1}, - 0xFE = {1092, 1}, + 0x10 = { 998, 1}, + 0x11 = { 999, 1}, + 0x12 = {1000, 1}, + 0x13 = {1001, 1}, + 0x14 = {1002, 1}, + 0x15 = {1003, 1}, + 0x16 = {1004, 1}, + 0x17 = {1005, 1}, + 0x28 = {1006, 1}, + 0x29 = {1007, 1}, + 0x2B = {1008, 1}, + 0x2E = {1009, 1}, + 0x2F = {1010, 1}, + 0x50 = {1011, 2}, + 0x51 = {1013, 1}, + 0x54 = {1014, 1}, + 0x55 = {1015, 1}, + 0x56 = {1016, 1}, + 0x57 = {1017, 1}, + 0x58 = {1018, 1}, + 0x59 = {1019, 1}, + 0x5A = {1020, 1}, + 0x5B = {1021, 1}, + 0x5C = {1022, 1}, + 0x5D = {1023, 1}, + 0x5E = {1024, 1}, + 0x5F = {1025, 1}, + 0x60 = {1026, 1}, + 0x61 = {1027, 1}, + 0x62 = {1028, 1}, + 0x63 = {1029, 1}, + 0x64 = {1030, 1}, + 0x65 = {1031, 1}, + 0x66 = {1032, 1}, + 0x67 = {1033, 1}, + 0x68 = {1034, 1}, + 0x69 = {1035, 1}, + 0x6A = {1036, 1}, + 0x6B = {1037, 1}, + 0x6C = {1038, 1}, + 0x6D = {1039, 1}, + 0x6E = {1040, 2}, + 0x6F = {1042, 1}, + 0x70 = {1043, 1}, + 0x71 = {1044, 3}, + 0x72 = {1047, 3}, + 0x73 = {1050, 2}, + 0x74 = {1052, 1}, + 0x75 = {1053, 1}, + 0x76 = {1054, 1}, + 0x7C = {1055, 1}, + 0x7D = {1056, 1}, + 0x7E = {1057, 2}, + 0x7F = {1059, 1}, + 0xAE = {1060, 3}, + 0xC2 = {1063, 1}, + 0xC4 = {1064, 2}, + 0xC5 = {1066, 2}, + 0xC6 = {1068, 1}, + 0xC7 = {1069, 1}, + 0xD0 = {1070, 1}, + 0xD1 = {1071, 1}, + 0xD2 = {1072, 1}, + 0xD3 = {1073, 1}, + 0xD4 = {1074, 1}, + 0xD5 = {1075, 1}, + 0xD6 = {1076, 1}, + 0xD7 = {1077, 2}, + 0xD8 = {1079, 1}, + 0xD9 = {1080, 1}, + 0xDA = {1081, 1}, + 0xDB = {1082, 1}, + 0xDC = {1083, 1}, + 0xDD = {1084, 1}, + 0xDE = {1085, 1}, + 0xDF = {1086, 1}, + 0xE0 = {1087, 1}, + 0xE1 = {1088, 1}, + 0xE2 = {1089, 1}, + 0xE3 = {1090, 1}, + 0xE4 = {1091, 1}, + 0xE5 = {1092, 1}, + 0xE6 = {1093, 1}, + 0xE7 = {1094, 1}, + 0xE8 = {1095, 1}, + 0xE9 = {1096, 1}, + 0xEA = {1097, 1}, + 0xEB = {1098, 1}, + 0xEC = {1099, 1}, + 0xED = {1100, 1}, + 0xEE = {1101, 1}, + 0xEF = {1102, 1}, + 0xF1 = {1103, 1}, + 0xF2 = {1104, 1}, + 0xF3 = {1105, 1}, + 0xF4 = {1106, 1}, + 0xF5 = {1107, 1}, + 0xF6 = {1108, 1}, + 0xF7 = {1109, 1}, + 0xF8 = {1110, 1}, + 0xF9 = {1111, 1}, + 0xFA = {1112, 1}, + 0xFB = {1113, 1}, + 0xFC = {1114, 1}, + 0xFD = {1115, 1}, + 0xFE = {1116, 1}, }, { // prefix = F3 - 0x01 = {1093, 3}, - 0x10 = {1096, 1}, - 0x11 = {1097, 1}, - 0x12 = {1098, 1}, - 0x16 = {1099, 1}, - 0x1E = {1100, 4}, - 0x2A = {1104, 2}, - 0x2C = {1106, 2}, - 0x2D = {1108, 2}, - 0x51 = {1110, 1}, - 0x52 = {1111, 1}, - 0x53 = {1112, 1}, - 0x58 = {1113, 1}, - 0x59 = {1114, 1}, - 0x5A = {1115, 1}, - 0x5B = {1116, 1}, - 0x5C = {1117, 1}, - 0x5D = {1118, 1}, - 0x5E = {1119, 1}, - 0x5F = {1120, 1}, - 0x6F = {1121, 1}, - 0x70 = {1122, 1}, - 0x7E = {1123, 1}, - 0x7F = {1124, 1}, - 0xAE = {1125, 3}, - 0xB8 = {1128, 3}, - 0xBC = {1131, 3}, - 0xBD = {1134, 3}, - 0xC2 = {1137, 1}, - 0xC7 = {1138, 1}, - 0xE6 = {1139, 1}, + 0x01 = {1117, 6}, + 0x09 = {1123, 1}, + 0x10 = {1124, 1}, + 0x11 = {1125, 1}, + 0x12 = {1126, 1}, + 0x16 = {1127, 1}, + 0x1E = {1128, 4}, + 0x2A = {1132, 2}, + 0x2C = {1134, 2}, + 0x2D = {1136, 2}, + 0x51 = {1138, 1}, + 0x52 = {1139, 1}, + 0x53 = {1140, 1}, + 0x58 = {1141, 1}, + 0x59 = {1142, 1}, + 0x5A = {1143, 1}, + 0x5B = {1144, 1}, + 0x5C = {1145, 1}, + 0x5D = {1146, 1}, + 0x5E = {1147, 1}, + 0x5F = {1148, 1}, + 0x6F = {1149, 1}, + 0x70 = {1150, 1}, + 0x7E = {1151, 1}, + 0x7F = {1152, 1}, + 0xAE = {1153, 14}, + 0xB8 = {1167, 3}, + 0xBC = {1170, 3}, + 0xBD = {1173, 3}, + 0xC2 = {1176, 1}, + 0xC7 = {1177, 2}, + 0xE6 = {1179, 1}, }, { // prefix = F2 - 0x10 = {1140, 1}, - 0x11 = {1141, 1}, - 0x12 = {1142, 1}, - 0x2A = {1143, 2}, - 0x2C = {1145, 2}, - 0x2D = {1147, 2}, - 0x51 = {1149, 1}, - 0x58 = {1150, 1}, - 0x59 = {1151, 1}, - 0x5A = {1152, 1}, - 0x5C = {1153, 1}, - 0x5D = {1154, 1}, - 0x5E = {1155, 1}, - 0x5F = {1156, 1}, - 0x70 = {1157, 1}, - 0x7C = {1158, 1}, - 0x7D = {1159, 1}, - 0xC2 = {1160, 1}, - 0xD0 = {1161, 1}, - 0xE6 = {1162, 1}, - 0xF0 = {1163, 1}, + 0x01 = {1180, 2}, + 0x10 = {1182, 1}, + 0x11 = {1183, 1}, + 0x12 = {1184, 1}, + 0x2A = {1185, 2}, + 0x2C = {1187, 2}, + 0x2D = {1189, 2}, + 0x51 = {1191, 1}, + 0x58 = {1192, 1}, + 0x59 = {1193, 1}, + 0x5A = {1194, 1}, + 0x5C = {1195, 1}, + 0x5D = {1196, 1}, + 0x5E = {1197, 1}, + 0x5F = {1198, 1}, + 0x70 = {1199, 1}, + 0x7C = {1200, 1}, + 0x7D = {1201, 1}, + 0xAE = {1202, 1}, + 0xC2 = {1203, 1}, + 0xD0 = {1204, 1}, + 0xE6 = {1205, 1}, + 0xF0 = {1206, 1}, }, } @(rodata) DECODE_INDEX_ESC_0F38 := [4][256]lib.Decode_Index{ { // prefix = none - 0xC8 = {1164, 1}, - 0xC9 = {1165, 1}, - 0xCA = {1166, 1}, - 0xCB = {1167, 1}, - 0xCC = {1168, 1}, - 0xCD = {1169, 1}, - 0xF0 = {1170, 3}, - 0xF1 = {1173, 3}, - 0xF6 = {1176, 2}, + 0xC8 = {1207, 1}, + 0xC9 = {1208, 1}, + 0xCA = {1209, 1}, + 0xCB = {1210, 1}, + 0xCC = {1211, 1}, + 0xCD = {1212, 1}, + 0xF0 = {1213, 3}, + 0xF1 = {1216, 3}, + 0xF6 = {1219, 2}, + 0xF9 = {1221, 2}, + 0xFC = {1223, 2}, }, { // prefix = 66 - 0x00 = {1178, 1}, - 0x01 = {1179, 1}, - 0x02 = {1180, 1}, - 0x03 = {1181, 1}, - 0x04 = {1182, 1}, - 0x05 = {1183, 1}, - 0x06 = {1184, 1}, - 0x07 = {1185, 1}, - 0x08 = {1186, 1}, - 0x09 = {1187, 1}, - 0x0A = {1188, 1}, - 0x0B = {1189, 1}, - 0x10 = {1190, 1}, - 0x14 = {1191, 1}, - 0x15 = {1192, 1}, - 0x17 = {1193, 1}, - 0x1C = {1194, 1}, - 0x1D = {1195, 1}, - 0x1E = {1196, 1}, - 0x20 = {1197, 1}, - 0x21 = {1198, 1}, - 0x22 = {1199, 1}, - 0x23 = {1200, 1}, - 0x24 = {1201, 1}, - 0x25 = {1202, 1}, - 0x28 = {1203, 1}, - 0x29 = {1204, 1}, - 0x2A = {1205, 1}, - 0x2B = {1206, 1}, - 0x30 = {1207, 1}, - 0x31 = {1208, 1}, - 0x32 = {1209, 1}, - 0x33 = {1210, 1}, - 0x34 = {1211, 1}, - 0x35 = {1212, 1}, - 0x37 = {1213, 1}, - 0x38 = {1214, 1}, - 0x39 = {1215, 1}, - 0x3A = {1216, 1}, - 0x3B = {1217, 1}, - 0x3C = {1218, 1}, - 0x3D = {1219, 1}, - 0x3E = {1220, 1}, - 0x3F = {1221, 1}, - 0x40 = {1222, 1}, - 0x41 = {1223, 1}, - 0x80 = {1224, 1}, - 0x81 = {1225, 1}, - 0x82 = {1226, 2}, - 0xDB = {1228, 1}, - 0xDC = {1229, 1}, - 0xDD = {1230, 1}, - 0xDE = {1231, 1}, - 0xDF = {1232, 1}, - 0xF5 = {1233, 2}, - 0xF6 = {1235, 2}, + 0x00 = {1225, 1}, + 0x01 = {1226, 1}, + 0x02 = {1227, 1}, + 0x03 = {1228, 1}, + 0x04 = {1229, 1}, + 0x05 = {1230, 1}, + 0x06 = {1231, 1}, + 0x07 = {1232, 1}, + 0x08 = {1233, 1}, + 0x09 = {1234, 1}, + 0x0A = {1235, 1}, + 0x0B = {1236, 1}, + 0x10 = {1237, 1}, + 0x14 = {1238, 1}, + 0x15 = {1239, 1}, + 0x17 = {1240, 1}, + 0x1C = {1241, 1}, + 0x1D = {1242, 1}, + 0x1E = {1243, 1}, + 0x20 = {1244, 1}, + 0x21 = {1245, 1}, + 0x22 = {1246, 1}, + 0x23 = {1247, 1}, + 0x24 = {1248, 1}, + 0x25 = {1249, 1}, + 0x28 = {1250, 1}, + 0x29 = {1251, 1}, + 0x2A = {1252, 1}, + 0x2B = {1253, 1}, + 0x30 = {1254, 1}, + 0x31 = {1255, 1}, + 0x32 = {1256, 1}, + 0x33 = {1257, 1}, + 0x34 = {1258, 1}, + 0x35 = {1259, 1}, + 0x37 = {1260, 1}, + 0x38 = {1261, 1}, + 0x39 = {1262, 1}, + 0x3A = {1263, 1}, + 0x3B = {1264, 1}, + 0x3C = {1265, 1}, + 0x3D = {1266, 1}, + 0x3E = {1267, 1}, + 0x3F = {1268, 1}, + 0x40 = {1269, 1}, + 0x41 = {1270, 1}, + 0x80 = {1271, 1}, + 0x81 = {1272, 1}, + 0x82 = {1273, 2}, + 0xDB = {1275, 1}, + 0xDC = {1276, 1}, + 0xDD = {1277, 1}, + 0xDE = {1278, 1}, + 0xDF = {1279, 1}, + 0xF5 = {1280, 2}, + 0xF6 = {1282, 2}, + 0xF8 = {1284, 1}, + 0xFC = {1285, 2}, }, { // prefix = F3 - 0xF6 = {1237, 2}, + 0xF6 = {1287, 2}, + 0xF8 = {1289, 1}, + 0xFC = {1290, 2}, }, { // prefix = F2 - 0xF0 = {1239, 2}, - 0xF1 = {1241, 3}, + 0xF0 = {1292, 2}, + 0xF1 = {1294, 3}, + 0xF8 = {1297, 1}, + 0xFC = {1298, 2}, }, } @(rodata) DECODE_INDEX_ESC_0F3A := [4][256]lib.Decode_Index{ { // prefix = none - 0xCC = {1244, 1}, + 0xCC = {1300, 1}, }, { // prefix = 66 - 0x08 = {1245, 1}, - 0x09 = {1246, 1}, - 0x0A = {1247, 1}, - 0x0B = {1248, 1}, - 0x0C = {1249, 1}, - 0x0D = {1250, 1}, - 0x0E = {1251, 1}, - 0x0F = {1252, 1}, - 0x14 = {1253, 1}, - 0x16 = {1254, 2}, - 0x17 = {1256, 1}, - 0x20 = {1257, 1}, - 0x21 = {1258, 1}, - 0x22 = {1259, 2}, - 0x40 = {1261, 1}, - 0x41 = {1262, 1}, - 0x42 = {1263, 1}, - 0x44 = {1264, 1}, - 0x60 = {1265, 1}, - 0x61 = {1266, 1}, - 0x62 = {1267, 1}, - 0x63 = {1268, 1}, - 0xDF = {1269, 1}, + 0x08 = {1301, 1}, + 0x09 = {1302, 1}, + 0x0A = {1303, 1}, + 0x0B = {1304, 1}, + 0x0C = {1305, 1}, + 0x0D = {1306, 1}, + 0x0E = {1307, 1}, + 0x0F = {1308, 1}, + 0x14 = {1309, 1}, + 0x16 = {1310, 2}, + 0x17 = {1312, 1}, + 0x20 = {1313, 1}, + 0x21 = {1314, 1}, + 0x22 = {1315, 2}, + 0x40 = {1317, 1}, + 0x41 = {1318, 1}, + 0x42 = {1319, 1}, + 0x44 = {1320, 1}, + 0x60 = {1321, 1}, + 0x61 = {1322, 1}, + 0x62 = {1323, 1}, + 0x63 = {1324, 1}, + 0xDF = {1325, 1}, }, { // prefix = F3 }, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 71b6831ec..83a1046f6 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_x86_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2395]lib.Encoding{ +ENCODE_FORMS := [2451]lib.Encoding{ // .MOV {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {explicit_count=2}}, {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}}, @@ -3595,10 +3595,112 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, {.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .SWAPGS + {.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 248, {esc=._0F}}, + // .MONITOR + {.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 200, {esc=._0F}}, + // .MWAIT + {.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 201, {esc=._0F}}, + // .CLAC + {.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 202, {esc=._0F}}, + // .STAC + {.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 203, {esc=._0F}}, + // .RDFSBASE + {.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + {.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .RDGSBASE + {.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + {.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .WRFSBASE + {.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + {.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .WRGSBASE + {.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + {.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .PTWRITE + {.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + {.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + // .RDPID + {.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + // .WBNOINVD + {.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=2}}, + // .SERIALIZE + {.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 232, {esc=._0F}}, + // .PREFETCH + {.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + // .TPAUSE + {.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=1}}, + // .UMONITOR + {.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, + // .UMWAIT + {.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=3, modrm_reg_ext=true, explicit_count=1}}, + // .MOVDIRI + {.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, explicit_count=2}}, + {.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}}, + // .MOVDIR64B + {.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=1, explicit_count=2}}, + // .ENQCMD + {.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=3, explicit_count=2}}, + // .ENQCMDS + {.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=2, explicit_count=2}}, + // .AADD + {.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, explicit_count=2}}, + {.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}}, + // .AAND + {.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=1, explicit_count=2}}, + {.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=1, force_rex_w=true, explicit_count=2}}, + // .AOR + {.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=3, explicit_count=2}}, + {.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=3, force_rex_w=true, explicit_count=2}}, + // .AXOR + {.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=2, explicit_count=2}}, + {.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=2, force_rex_w=true, explicit_count=2}}, + // .XEND + {.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 213, {esc=._0F}}, + // .XTEST + {.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 214, {esc=._0F}}, + // .VMRUN + {.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 216, {esc=._0F}}, + // .VMMCALL + {.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 217, {esc=._0F}}, + // .VMLOAD + {.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 218, {esc=._0F}}, + // .VMSAVE + {.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 219, {esc=._0F}}, + // .STGI + {.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 220, {esc=._0F}}, + // .CLGI + {.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 221, {esc=._0F}}, + // .SKINIT + {.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 222, {esc=._0F}}, + // .INVLPGA + {.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 223, {esc=._0F}}, + // .INVLPGB + {.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F}}, + // .TLBSYNC + {.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F}}, + // .PVALIDATE + {.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F, prefix=3}}, + // .RMPADJUST + {.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F, prefix=2}}, + // .RMPUPDATE + {.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 254, {esc=._0F, prefix=3}}, + // .PSMASH + {.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 255, {esc=._0F, prefix=2}}, + // .CLZERO + {.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 252, {esc=._0F}}, + // .MONITORX + {.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 250, {esc=._0F}}, + // .MWAITX + {.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 251, {esc=._0F}}, + // .RDPRU + {.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 253, {esc=._0F}}, + // .MCOMMIT + {.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 250, {esc=._0F, prefix=2}}, } @(rodata) -CLOBBER_FORMS := [2395]lib.Clobber{ +CLOBBER_FORMS := [2451]lib.Clobber{ // .MOV {written={0}, read={1}, writes_mem=true, reads_mem=true}, {written={0}, read={1}, writes_mem=true, reads_mem=true}, @@ -7185,6 +7287,108 @@ CLOBBER_FORMS := [2395]lib.Clobber{ {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .SWAPGS + {side_effects={.PRIVILEGED}}, + // .MONITOR + {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, + // .MWAIT + {implicit_rd={.RAX, .RCX}, side_effects={.HALT}}, + // .CLAC + {side_effects={.PRIVILEGED}}, + // .STAC + {side_effects={.PRIVILEGED}}, + // .RDFSBASE + {written={0}}, + {written={0}}, + // .RDGSBASE + {written={0}}, + {written={0}}, + // .WRFSBASE + {read={0}}, + {read={0}}, + // .WRGSBASE + {read={0}}, + {read={0}}, + // .PTWRITE + {read={0}, reads_mem=true}, + {read={0}, reads_mem=true}, + // .RDPID + {written={0}}, + // .WBNOINVD + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SERIALIZE + {side_effects={.SERIALIZING}}, + // .PREFETCH + {read={0}, reads_mem=true, side_effects={.HINT}}, + // .TPAUSE + {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, + // .UMONITOR + {read={0}, reads_mem=true}, + // .UMWAIT + {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, + // .MOVDIRI + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .MOVDIR64B + {read={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + // .ENQCMD + {read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .ENQCMDS + {read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .AADD + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + // .AAND + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + // .AOR + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + // .AXOR + {read={0, 1}, writes_mem=true, reads_mem=true}, + {read={0, 1}, writes_mem=true, reads_mem=true}, + // .XEND + {side_effects={.CONTROL}}, + // .XTEST + {flags_wr={.ZF}}, + // .VMRUN + {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMMCALL + {side_effects={.PRIVILEGED}}, + // .VMLOAD + {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMSAVE + {implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .STGI + {side_effects={.PRIVILEGED}}, + // .CLGI + {side_effects={.PRIVILEGED}}, + // .SKINIT + {implicit_rd={.RAX}, side_effects={.PRIVILEGED}}, + // .INVLPGA + {implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}}, + // .INVLPGB + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}}, + // .TLBSYNC + {side_effects={.PRIVILEGED}}, + // .PVALIDATE + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .RMPADJUST + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .RMPUPDATE + {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + // .PSMASH + {implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .CLZERO + {implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}}, + // .MONITORX + {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, + // .MWAITX + {implicit_rd={.RAX, .RBX, .RCX}, side_effects={.HALT}}, + // .RDPRU + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + // .MCOMMIT + {flags_wr={.CF}, side_effects={.FENCE}}, } @(rodata) @@ -8381,10 +8585,56 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .MOVBE = { 2383, 6}, .RDRAND = { 2389, 3}, .RDSEED = { 2392, 3}, + .SWAPGS = { 2395, 1}, + .MONITOR = { 2396, 1}, + .MWAIT = { 2397, 1}, + .CLAC = { 2398, 1}, + .STAC = { 2399, 1}, + .RDFSBASE = { 2400, 2}, + .RDGSBASE = { 2402, 2}, + .WRFSBASE = { 2404, 2}, + .WRGSBASE = { 2406, 2}, + .PTWRITE = { 2408, 2}, + .RDPID = { 2410, 1}, + .WBNOINVD = { 2411, 1}, + .SERIALIZE = { 2412, 1}, + .PREFETCH = { 2413, 1}, + .TPAUSE = { 2414, 1}, + .UMONITOR = { 2415, 1}, + .UMWAIT = { 2416, 1}, + .MOVDIRI = { 2417, 2}, + .MOVDIR64B = { 2419, 1}, + .ENQCMD = { 2420, 1}, + .ENQCMDS = { 2421, 1}, + .AADD = { 2422, 2}, + .AAND = { 2424, 2}, + .AOR = { 2426, 2}, + .AXOR = { 2428, 2}, + .XEND = { 2430, 1}, + .XTEST = { 2431, 1}, + .VMRUN = { 2432, 1}, + .VMMCALL = { 2433, 1}, + .VMLOAD = { 2434, 1}, + .VMSAVE = { 2435, 1}, + .STGI = { 2436, 1}, + .CLGI = { 2437, 1}, + .SKINIT = { 2438, 1}, + .INVLPGA = { 2439, 1}, + .INVLPGB = { 2440, 1}, + .TLBSYNC = { 2441, 1}, + .PVALIDATE = { 2442, 1}, + .RMPADJUST = { 2443, 1}, + .RMPUPDATE = { 2444, 1}, + .PSMASH = { 2445, 1}, + .CLZERO = { 2446, 1}, + .MONITORX = { 2447, 1}, + .MWAITX = { 2448, 1}, + .RDPRU = { 2449, 1}, + .MCOMMIT = { 2450, 1}, } // Emit descriptor per form (derived from ENCODE_FORMS via lib.form_to_recipe). -ENCODE_RECIPES: [2395]lib.Form_Recipe +ENCODE_RECIPES: [2451]lib.Form_Recipe @(init) _fill_recipes :: proc "contextless" () { for i in 0 ..< len(ENCODE_FORMS) { ENCODE_RECIPES[i] = lib.form_to_recipe(&ENCODE_FORMS[i]) diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index 59f12ef4c569d68083aae103a22081a25fce2344..546c6e2a6d8394c13e39acd1c313a450f3e96821 100644 GIT binary patch delta 913 zcmdn6nrXu(rVSgW)~{e;fC9!Jj0_A6D-rw?ApR-@|0IaN8o@sW;;%vQPlNbtS(q6Z z7(lFb44e$C3~O0H3ZQ%rR)%#5c}7kK)_R6@2nCFs9IOoM5ek?<2CPTOGlAqcAmo`r z@*5EH%pm!VEbK4`uz=(@vTz{y9IOnR;OdXFb28MkGHeDp5F7@a44e!M3|ruQ#up%W zZ)M?v8o7efsu)U;U@zV0|&!S z7G4%Ozn+7GVHXRFAOiyvBLl+^1~vu`hTTYfJ_ZhkJxF{m1`dY3a0CB<4crSi@DBqM z2M5DGBzcf|`;g?>I5-&gBgxl;EZC2vfRBTN;Q*2Xkc9`3Wi9{tXcS2!ekT#6ODQ*WUsO9771)2Jw$0_;*136A1oY5dS2Ce-Fezh2Y-@@lPZ8 z|3LgR2>yQ%|16we&-kC0fq~&1T!8T(C=HxP;)CQbAo%}5@)r^OKOh4yA^5*Q{L2Xb WZxH_qg8vu9zY62CGcf)F83+Ini)A4I delta 9 Rcmdn6iD|=XrVSgW0st3V1h)VH diff --git a/core/rexcode/isa/x86/tables/x86.encode_recipes.bin b/core/rexcode/isa/x86/tables/x86.encode_recipes.bin index 2bc0e47c0bfd5133d7e07363efe778c96a0f1fb8..fad8dd6a8256527604e0a3bdc2c914c6182e3d59 100644 GIT binary patch delta 687 zcmX@|fbq#w#tkk7^$h%s3`{@%|NsA=fdR}ufy6$E#6E?@J`G`i=3mFa#J~X3%Z|k6 z2eTQG#35{mI1`dM6GJ^nGem+JNdm%#h_fJxL)iSE`HwR&vBShU8Ng=#XJ7<-;045S z4E($>$BCzb9Lfe$zm9p@#Ppj9vd9Y$!|-?`N3Ae+E`0HZRy`S7AP5WMI06#J+*V zzKO)Xg~Yy%#J+=I*E8KkaG35PvF{_X{~@tK%>N7wpFrsb%Ki*uL)C!Ap=_`?R1Mez de?S~)I{O7?t3ndpZ!ibK{tID)HA56J005$z4etN| delta 9 QcmaFzl<~*|#tkk702@FA)Bpeg diff --git a/core/rexcode/isa/x86/tables/x86.encode_runs.bin b/core/rexcode/isa/x86/tables/x86.encode_runs.bin index 1120cea501d91f9d075b7b0bdb8b4aade243d5fc..9431e7617331a678c9d1fcde78d40bd9b505ea20 100644 GIT binary patch delta 378 zcmX@$wZV6TgKB*=Cj$c`0|P@0l#YecaZoxQN+)nKFfcJNFeE|g6eyhrr8A&(7F2yU zl+J0!mjw=^7|q2US-Or5m7hBb07} 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M_ENDBR64, M_ENDBR32, M_XSAVE, M_XSAVE64, M_XRSTOR, M_XRSTOR64, M_XSAVEOPT, M_XSAVEOPT64, M_XSAVEC, M_XSAVEC64, M_XSAVES, M_XSAVES64, M_XRSTORS, M_XRSTORS64, M_PREFETCHT0, M_PREFETCHT1, M_PREFETCHT2, M_PREFETCHNTA, M_PREFETCHW, M_CLFLUSHOPT, M_CLWB, M_CLDEMOTE, M_BSWAP, M_CMPXCHG, M_CMPXCHG8B, M_CMPXCHG16B, M_XADD, - M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, + M_BOUND, M_ENTER, M_LEAVE, M_XLAT, M_XLATB, M_MOVBE, M_RDRAND, M_RDSEED, M_SWAPGS, M_MONITOR, M_MWAIT, M_CLAC, M_STAC, M_RDFSBASE, M_RDGSBASE, M_WRFSBASE, + M_WRGSBASE, M_PTWRITE, M_RDPID, M_WBNOINVD, M_SERIALIZE, M_PREFETCH, M_TPAUSE, M_UMONITOR, M_UMWAIT, M_MOVDIRI, M_MOVDIR64B, M_ENQCMD, M_ENQCMDS, M_AADD, M_AAND, M_AOR, + M_AXOR, M_XEND, M_XTEST, M_VMRUN, M_VMMCALL, M_VMLOAD, M_VMSAVE, M_STGI, M_CLGI, M_SKINIT, M_INVLPGA, M_INVLPGB, M_TLBSYNC, M_PVALIDATE, M_RMPADJUST, M_RMPUPDATE, + M_PSMASH, M_CLZERO, M_MONITORX, M_MWAITX, M_RDPRU, M_MCOMMIT, MNEMONIC_COUNT }; @@ -407,9 +410,9 @@ struct Asm_amd64 { }; - static EncodeRun const raw_encode_runs [1192]; - static u8 const raw_encode_forms [38320]; - static u8 const raw_clobber_forms[38320]; + static EncodeRun const raw_encode_runs [1238]; + static u8 const raw_encode_forms [39216]; + static u8 const raw_clobber_forms[39216]; StringMap mnemonic_map; StringMap prefix_map; @@ -733,7 +736,10 @@ String const Asm_amd64::mnemonic_strings[Asm_amd64::MNEMONIC_COUNT] { str_lit("vmwrite"), str_lit("vmfunc"), str_lit("invept"), str_lit("invvpid"), str_lit("encls"), str_lit("enclu"), str_lit("enclv"), str_lit("rdpkru"), str_lit("wrpkru"), str_lit("incsspd"), str_lit("incsspq"), str_lit("rdsspd"), str_lit("rdsspq"), str_lit("saveprevssp"), str_lit("rstorssp"), str_lit("wrssd"), str_lit("wrssq"), str_lit("wrussd"), str_lit("wrussq"), str_lit("setssbsy"), str_lit("clrssbsy"), str_lit("endbr64"), str_lit("endbr32"), str_lit("xsave"), str_lit("xsave64"), str_lit("xrstor"), str_lit("xrstor64"), str_lit("xsaveopt"), str_lit("xsaveopt64"), str_lit("xsavec"), str_lit("xsavec64"), str_lit("xsaves"), str_lit("xsaves64"), str_lit("xrstors"), str_lit("xrstors64"), str_lit("prefetcht0"), str_lit("prefetcht1"), str_lit("prefetcht2"), str_lit("prefetchnta"), str_lit("prefetchw"), str_lit("clflushopt"), str_lit("clwb"), str_lit("cldemote"), str_lit("bswap"), str_lit("cmpxchg"), str_lit("cmpxchg8b"), str_lit("cmpxchg16b"), str_lit("xadd"), - str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), + str_lit("bound"), str_lit("enter"), str_lit("leave"), str_lit("xlat"), str_lit("xlatb"), str_lit("movbe"), str_lit("rdrand"), str_lit("rdseed"), str_lit("swapgs"), str_lit("monitor"), str_lit("mwait"), str_lit("clac"), str_lit("stac"), str_lit("rdfsbase"), str_lit("rdgsbase"), str_lit("wrfsbase"), + str_lit("wrgsbase"), str_lit("ptwrite"), str_lit("rdpid"), str_lit("wbnoinvd"), str_lit("serialize"), str_lit("prefetch"), str_lit("tpause"), str_lit("umonitor"), str_lit("umwait"), str_lit("movdiri"), str_lit("movdir64b"), str_lit("enqcmd"), str_lit("enqcmds"), str_lit("aadd"), str_lit("aand"), str_lit("aor"), + str_lit("axor"), str_lit("xend"), str_lit("xtest"), str_lit("vmrun"), str_lit("vmmcall"), str_lit("vmload"), str_lit("vmsave"), str_lit("stgi"), str_lit("clgi"), str_lit("skinit"), str_lit("invlpga"), str_lit("invlpgb"), str_lit("tlbsync"), str_lit("pvalidate"), str_lit("rmpadjust"), str_lit("rmpupdate"), + str_lit("psmash"), str_lit("clzero"), str_lit("monitorx"), str_lit("mwaitx"), str_lit("rdpru"), str_lit("mcommit"), }; String const Asm_amd64::prefix_strings[Asm_amd64::PREFIX_COUNT] { str_lit(""), str_lit("es"), str_lit("cs"), str_lit("ss"), str_lit("ds"), str_lit("rex"), str_lit("evex"), str_lit("fs"), str_lit("gs"), str_lit("vex"), str_lit("lock"), str_lit("repne"), str_lit("rep"), @@ -770,7 +776,7 @@ String const Asm_amd64::register_strings[Asm_amd64::REG_COUNT] { str_lit("bnd2"), str_lit("bnd3"), str_lit("mm0"), str_lit("mm1"), str_lit("mm2"), str_lit("mm3"), str_lit("mm4"), str_lit("mm5"), str_lit("mm6"), str_lit("mm7"), str_lit("st0"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("st5"), str_lit("st6"), str_lit("st7"), str_lit("rip"), }; -Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1192] = { +Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1238] = { { 0, 0}, { 0, 32}, { 32, 9}, { 41, 5}, { 46, 5}, { 51, 1}, { 52, 7}, { 59, 9}, { 68, 6}, { 74, 3}, { 77, 19}, { 96, 19}, { 115, 19}, { 134, 19}, { 153, 4}, { 157, 13}, { 170, 4}, { 174, 4}, { 178, 6}, { 184, 6}, { 190, 4}, { 194, 19}, { 213, 19}, { 232, 19}, { 251, 19}, { 270, 4}, { 274, 12}, { 286, 12}, { 298, 12}, { 310, 12}, { 322, 12}, { 334, 12}, { 346, 12}, { 358, 12}, { 370, 6}, { 376, 6}, { 382, 6}, { 388, 6}, { 394, 6}, { 400, 6}, { 406, 3}, { 409, 3}, { 412, 3}, { 415, 3}, { 418, 3}, { 421, 6}, { 427, 2}, { 429, 2}, @@ -845,9 +851,12 @@ Asm_amd64::EncodeRun const Asm_amd64::raw_encode_runs[1192] = { {2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, {2336, 1}, {2337, 1}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 2}, {2367, 4}, {2371, 1}, {2372, 1}, {2373, 4}, - {2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, + {2377, 2}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 6}, {2389, 3}, {2392, 3}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 1}, {2399, 1}, {2400, 2}, {2402, 2}, {2404, 2}, + {2406, 2}, {2408, 2}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 2}, {2419, 1}, {2420, 1}, {2421, 1}, {2422, 2}, {2424, 2}, {2426, 2}, + {2428, 2}, {2430, 1}, {2431, 1}, {2432, 1}, {2433, 1}, {2434, 1}, {2435, 1}, {2436, 1}, {2437, 1}, {2438, 1}, {2439, 1}, {2440, 1}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 1}, + {2445, 1}, {2446, 1}, {2447, 1}, {2448, 1}, {2449, 1}, {2450, 1}, }; -u8 const Asm_amd64::raw_encode_forms[38320] = { +u8 const Asm_amd64::raw_encode_forms[39216] = { 0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x06, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x07, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x89, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x05, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x06, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x07, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x08, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x00, 0x01, 0x12, 0x00, 0x00, 0x04, 0x05, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x02, 0x13, 0x00, 0x00, 0x04, 0x06, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x03, 0x14, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x04, 0x15, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x08, 0x08, 0x00, @@ -1446,9 +1455,23 @@ u8 const Asm_amd64::raw_encode_forms[38320] = { 0xa2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa5, 0x04, 0x02, 0x0b, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x03, 0x0c, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x04, 0x0d, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf0, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa5, 0x04, 0x0b, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x00, 0x08, 0x00, 0xa5, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf1, 0x00, 0x02, 0x08, 0x08, 0x00, 0xa6, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa6, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x00, 0x05, 0x00, 0xa6, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x06, 0x01, 0x08, 0x05, 0x00, - 0xa7, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, + 0xa7, 0x04, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x00, 0x05, 0x00, 0xa7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x01, 0x08, 0x05, 0x00, 0xa8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf8, 0x01, 0x00, 0x00, 0x00, + 0xa9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc8, 0x01, 0x00, 0x00, 0x00, 0xaa, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc9, 0x01, 0x00, 0x00, 0x00, 0xab, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xca, 0x01, 0x00, 0x00, 0x00, 0xac, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xcb, 0x01, 0x00, 0x00, 0x00, + 0xad, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x00, 0x09, 0x00, 0x05, 0x00, 0xad, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x00, 0x09, 0x08, 0x05, 0x00, 0xae, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x01, 0x09, 0x00, 0x05, 0x00, 0xae, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x01, 0x09, 0x08, 0x05, 0x00, + 0xaf, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x02, 0x09, 0x00, 0x05, 0x00, 0xaf, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x02, 0x09, 0x08, 0x05, 0x00, 0xb0, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x03, 0x09, 0x00, 0x05, 0x00, 0xb0, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x03, 0x09, 0x08, 0x05, 0x00, + 0xb1, 0x04, 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x04, 0x09, 0x00, 0x05, 0x00, 0xb1, 0x04, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x04, 0x09, 0x08, 0x05, 0x00, 0xb2, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xc7, 0x07, 0x09, 0x00, 0x05, 0x00, 0xb3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, + 0xb4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe8, 0x01, 0x00, 0x00, 0x00, 0xb5, 0x04, 0x0a, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x01, 0x00, 0x05, 0x00, 0xb6, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x05, 0x00, 0x05, 0x00, 0xb7, 0x04, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x09, 0x00, 0x05, 0x00, + 0xb8, 0x04, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xae, 0x06, 0x0d, 0x00, 0x05, 0x00, 0xb9, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x08, 0x00, 0xb9, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x08, 0x08, 0x00, 0xba, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x06, 0x00, 0x08, 0x00, + 0xbb, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x0e, 0x00, 0x08, 0x00, 0xbc, 0x04, 0x04, 0x11, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x0a, 0x00, 0x08, 0x00, 0xbd, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x02, 0x00, 0x08, 0x00, 0xbd, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x02, 0x08, 0x08, 0x00, + 0xbe, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x06, 0x00, 0x08, 0x00, 0xbe, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x06, 0x08, 0x08, 0x00, 0xbf, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0e, 0x00, 0x08, 0x00, 0xbf, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0e, 0x08, 0x08, 0x00, + 0xc0, 0x04, 0x0c, 0x03, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0a, 0x00, 0x08, 0x00, 0xc0, 0x04, 0x0d, 0x04, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0xfc, 0x00, 0x0a, 0x08, 0x08, 0x00, 0xc1, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd5, 0x01, 0x00, 0x00, 0x00, 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd6, 0x01, 0x00, 0x00, 0x00, + 0xc3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd8, 0x01, 0x00, 0x00, 0x00, 0xc4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xd9, 0x01, 0x00, 0x00, 0x00, 0xc5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xda, 0x01, 0x00, 0x00, 0x00, 0xc6, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdb, 0x01, 0x00, 0x00, 0x00, + 0xc7, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdc, 0x01, 0x00, 0x00, 0x00, 0xc8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdd, 0x01, 0x00, 0x00, 0x00, 0xc9, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xde, 0x01, 0x00, 0x00, 0x00, 0xca, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xdf, 0x01, 0x00, 0x00, 0x00, + 0xcb, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x01, 0x00, 0x00, 0x00, 0xcc, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x01, 0x00, 0x00, 0x00, 0xcd, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x0d, 0x00, 0x00, 0x00, 0xce, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x09, 0x00, 0x00, 0x00, + 0xcf, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x0d, 0x00, 0x00, 0x00, 0xd0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x09, 0x00, 0x00, 0x00, 0xd1, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfc, 0x01, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x01, 0x00, 0x00, 0x00, + 0xd3, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfb, 0x01, 0x00, 0x00, 0x00, 0xd4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfd, 0x01, 0x00, 0x00, 0x00, 0xd5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xfa, 0x09, 0x00, 0x00, 0x00, }; -u8 const Asm_amd64::raw_clobber_forms[38320] = { +u8 const Asm_amd64::raw_clobber_forms[39216] = { 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2047,5 +2070,19 @@ u8 const Asm_amd64::raw_clobber_forms[38320] = { 0x00, 0x00, 0xc0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x0d, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x0d, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x05, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x09, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, }; From 12c89ee2bfa2664f583bc008ca4049568000e20a Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 14:11:01 +0100 Subject: [PATCH 86/92] Allow for `[base - disp]` --- src/check_asm.cpp | 23 +++++++++++++++++++++++ src/llvm_backend_asm.cpp | 29 ++++++++++++++++++++++++++--- src/parser.cpp | 15 ++++++++++++--- src/parser.hpp | 2 ++ 4 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index ce15e2cd1..ee79c240d 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1107,6 +1107,29 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * check_asm_instruction_operand(asm_ctx, ctx, entity, &scale, mem_op->scale, false); check_asm_instruction_operand(asm_ctx, ctx, entity, &disp, mem_op->disp, false); + // NOTE(bill): if the index is actually an immediate and there is no scale nor disp, + // then treat it as a disp, and modify the AST too + if (index.expr != nullptr && scale.expr == nullptr && disp.expr == nullptr) { + bool do_swap = index.mode == Addressing_Constant; + if (!do_swap) { + Entity *param_entity = entity_of_node(index.expr); + if (param_entity != nullptr && param_entity->kind == Entity_Variable) { + auto kind = check_asm_find_kind(param_entity, ate->decls); + do_swap = kind == AsmTemplateEntityDecl_Immediate; + } + } + if (do_swap) { + disp = index; + index = {}; + + mem_op->disp = mem_op->index; + mem_op->index = nullptr; + + mem_op->disp_op = mem_op->index_op; + mem_op->index_op = {}; + } + } + i32 base_w = 0; i32 index_w = 0; bool have_base = false; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 4016ad839..b77cf83ae 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -8,6 +8,9 @@ struct lbAsmGenerate { WriteOperandFlag_IsScale = 1<<1, WriteOperandFlag_IsScaleLog2 = 1<<2, + WriteOperandFlag_Negate = 1<<3, + + WriteOperandFlag_NONE = 0, WriteOperandFlag_DEFAULT = WriteOperandFlag_PrintPrefixes, }; @@ -77,6 +80,10 @@ struct lbAsmGenerate { asm_string = gb_string_appendc(asm_string, "$$"); } + if (flags & WriteOperandFlag_Negate) { + val = -val; + } + asm_string = gb_string_append_fmt(asm_string, "%d", cast(int)val); break; } @@ -97,6 +104,11 @@ struct lbAsmGenerate { return write_constant_operand(asm_string, op, flags); } + if (flags & WriteOperandFlag_Negate) { + flags &= ~WriteOperandFlag_Negate; + asm_string = gb_string_appendc(asm_string, "-"); + } + switch (op->kind) { case_ast_node(i, Ident, op); Entity *e = entity_of_node(op); @@ -276,14 +288,25 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { gbString write_memory_operand(gbString asm_string, Slice const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { if (mem_op->disp) { - asm_string = this->write_operand(asm_string, op_number, mem_op->disp, flags&~WriteOperandFlag_PrintPrefixes); + u32 disp_flags = flags; + disp_flags &= ~WriteOperandFlag_PrintPrefixes; + if (mem_op->disp_op.kind == Token_Sub) { + disp_flags |= WriteOperandFlag_Negate; + } + + asm_string = this->write_operand(asm_string, op_number, mem_op->disp, disp_flags); } asm_string = gb_string_appendc(asm_string, "("); GB_ASSERT(mem_op->base != nullptr); asm_string = this->write_operand(asm_string, op_number, mem_op->base, flags); if (mem_op->index) { + u32 index_flags = flags; + if (mem_op->index_op.kind == Token_Sub) { + index_flags |= WriteOperandFlag_Negate; + } asm_string = gb_string_appendc(asm_string, ","); - asm_string = this->write_operand(asm_string, op_number, mem_op->index, flags); + asm_string = this->write_operand(asm_string, op_number, mem_op->index, index_flags); + if (mem_op->scale) { asm_string = gb_string_appendc(asm_string, ","); switch (mem_op->scale_op.kind) { @@ -634,7 +657,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (false) { + if (true) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! diff --git a/src/parser.cpp b/src/parser.cpp index 99175c3fa..cb84d7e10 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2489,16 +2489,21 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { Ast *disp = nullptr; Ast *type = nullptr; + Token index_op = {}; Token scale_op = {}; + Token disp_op = {}; base = parse_asm_operand(f, false); // [base] // [base + index] + // [base - index] // [base + index + disp] // [base + index*scale] // *, <<, >> // [base + index*scale + disp] - if (allow_token(f, Token_Add)) { + if (allow_token(f, Token_Add) || + allow_token(f, Token_Sub)) { + index_op = f->prev_token; index = parse_asm_operand(f, false); if (allow_token(f, Token_Mul) || allow_token(f, Token_Shl) || @@ -2506,7 +2511,9 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { scale_op = f->prev_token; scale = parse_asm_operand(f, false); } - if (allow_token(f, Token_Add)) { + if (allow_token(f, Token_Add) || + allow_token(f, Token_Sub)) { + disp_op = f->prev_token; disp = parse_asm_operand(f, false); } } @@ -2521,9 +2528,11 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { Ast *mem = alloc_ast_node(f, Ast_AsmMemoryOperand); mem->AsmMemoryOperand.open = open; mem->AsmMemoryOperand.base = base; + mem->AsmMemoryOperand.index_op = index_op; mem->AsmMemoryOperand.index = index; - mem->AsmMemoryOperand.scale = scale; mem->AsmMemoryOperand.scale_op = scale_op; + mem->AsmMemoryOperand.scale = scale; + mem->AsmMemoryOperand.disp_op = disp_op; mem->AsmMemoryOperand.disp = disp; mem->AsmMemoryOperand.close = close; mem->AsmMemoryOperand.type = type; diff --git a/src/parser.hpp b/src/parser.hpp index e945cadc3..8b6b72278 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -511,9 +511,11 @@ struct AstSplitArgs { AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ Token open; \ Ast * base; \ + Token index_op; \ Ast * index; \ Token scale_op; \ Ast * scale; \ + Token disp_op; \ Ast * disp; \ Ast * type; \ Token close; \ From fd9ccd7b10f49983e2b4977cc16d84a04e1e4004 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 14:44:24 +0100 Subject: [PATCH 87/92] Support segment overrides on `asm` memory operands --- src/check_asm.cpp | 39 ++++++++++++++++++++++++++++++++++++++- src/llvm_backend_asm.cpp | 17 ++++++++++++++--- src/parser.cpp | 33 +++++++++++++++++++++++---------- src/parser.hpp | 1 + 4 files changed, 76 insertions(+), 14 deletions(-) diff --git a/src/check_asm.cpp b/src/check_asm.cpp index ee79c240d..1b1cc4bd9 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1098,6 +1098,26 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * break; } + Operand segment_override = {}; + check_asm_instruction_operand(asm_ctx, ctx, entity, &segment_override, mem_op->segment_override, false); + + if (segment_override.expr == nullptr) { + // okay + } else if (segment_override.expr->kind == Ast_AsmRegister) { + String reg_name = segment_override.expr->AsmRegister.name.string; + auto reg = asm_ctx->register_lookup(reg_name); + auto reg_class = asm_ctx->reg_class(asm_ctx->register_codes[reg]); + if (reg_class != asm_ctx->REG_CLASS_SEG) { + gbString s = expr_to_string(segment_override.expr); + error(segment_override.expr, "A segment override must be a selector register parameter, got %s", s); + gb_string_free(s); + } + } else { + gbString s = expr_to_string(segment_override.expr); + error(segment_override.expr, "A segment override must be a selector register parameter, got %s", s); + gb_string_free(s); + } + Operand base = {}; Operand index = {}; Operand scale = {}; @@ -1107,7 +1127,7 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * check_asm_instruction_operand(asm_ctx, ctx, entity, &scale, mem_op->scale, false); check_asm_instruction_operand(asm_ctx, ctx, entity, &disp, mem_op->disp, false); - // NOTE(bill): if the index is actually an immediate and there is no scale nor disp, + // NOTE(bill): if the base/index is actually an immediate and there is no scale nor disp, // then treat it as a disp, and modify the AST too if (index.expr != nullptr && scale.expr == nullptr && disp.expr == nullptr) { bool do_swap = index.mode == Addressing_Constant; @@ -1129,6 +1149,23 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * mem_op->index_op = {}; } } + if (base.expr != nullptr && index.expr == nullptr && scale.expr == nullptr && disp.expr == nullptr) { + bool do_swap = base.mode == Addressing_Constant; + if (!do_swap) { + Entity *param_entity = entity_of_node(base.expr); + if (param_entity != nullptr && param_entity->kind == Entity_Variable) { + auto kind = check_asm_find_kind(param_entity, ate->decls); + do_swap = kind == AsmTemplateEntityDecl_Immediate; + } + } + if (do_swap) { + disp = base; + base = {}; + + mem_op->disp = mem_op->base; + mem_op->base = nullptr; + } + } i32 base_w = 0; i32 index_w = 0; diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index b77cf83ae..2e5e93d00 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -146,6 +146,11 @@ struct lbAsmGenerate { case_ast_node(label, AsmLabelDecl, op); asm_string = write_label(asm_string, &label->name->Ident); case_end; + + case_ast_node(reg, AsmRegister, op); + asm_string = gb_string_appendc(asm_string, "%"); + asm_string = gb_string_append_length(asm_string, reg->name.string.text, reg->name.string.len); + case_end; default: GB_PANIC("TODO(bill): write_operand for '%s'", expr_to_string(op)); break; @@ -287,6 +292,11 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { gbString write_memory_operand(gbString asm_string, Slice const &op_number, AstAsmMemoryOperand *mem_op, u32 flags) override { + if (mem_op->segment_override != nullptr) { + asm_string = this->write_operand(asm_string, op_number, mem_op->segment_override, flags); + asm_string = gb_string_appendc(asm_string, ":"); + } + if (mem_op->disp) { u32 disp_flags = flags; disp_flags &= ~WriteOperandFlag_PrintPrefixes; @@ -297,8 +307,9 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { asm_string = this->write_operand(asm_string, op_number, mem_op->disp, disp_flags); } asm_string = gb_string_appendc(asm_string, "("); - GB_ASSERT(mem_op->base != nullptr); - asm_string = this->write_operand(asm_string, op_number, mem_op->base, flags); + if (mem_op->base != nullptr) { + asm_string = this->write_operand(asm_string, op_number, mem_op->base, flags); + } if (mem_op->index) { u32 index_flags = flags; if (mem_op->index_op.kind == Token_Sub) { @@ -657,7 +668,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (true) { + if (false) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!! diff --git a/src/parser.cpp b/src/parser.cpp index cb84d7e10..543e89d0e 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -548,6 +548,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmInstruction.operands = clone_ast_array(n->AsmInstruction.operands, f); break; case Ast_AsmMemoryOperand: + n->AsmMemoryOperand.segment_override = clone_ast(n->AsmMemoryOperand.segment_override, f); n->AsmMemoryOperand.base = clone_ast(n->AsmMemoryOperand.base, f); n->AsmMemoryOperand.index = clone_ast(n->AsmMemoryOperand.index, f); n->AsmMemoryOperand.scale = clone_ast(n->AsmMemoryOperand.scale, f); @@ -2483,6 +2484,7 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { case Token_OpenBracket: if (allow_memory_operand) { Token open = expect_token(f, Token_OpenBracket); + Ast *segment_override = nullptr; Ast *base = nullptr; Ast *index = nullptr; Ast *scale = nullptr; @@ -2495,6 +2497,16 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { base = parse_asm_operand(f, false); + if (allow_token(f, Token_Colon)) { + // [segment: ...] + segment_override = base; + if (segment_override != nullptr && + segment_override->kind != Ast_AsmRegister) { + error(segment_override, "Expected an asm register as the segment override"); + } + base = parse_asm_operand(f, false); + } + // [base] // [base + index] // [base - index] @@ -2526,16 +2538,17 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { } Ast *mem = alloc_ast_node(f, Ast_AsmMemoryOperand); - mem->AsmMemoryOperand.open = open; - mem->AsmMemoryOperand.base = base; - mem->AsmMemoryOperand.index_op = index_op; - mem->AsmMemoryOperand.index = index; - mem->AsmMemoryOperand.scale_op = scale_op; - mem->AsmMemoryOperand.scale = scale; - mem->AsmMemoryOperand.disp_op = disp_op; - mem->AsmMemoryOperand.disp = disp; - mem->AsmMemoryOperand.close = close; - mem->AsmMemoryOperand.type = type; + mem->AsmMemoryOperand.open = open; + mem->AsmMemoryOperand.segment_override = segment_override; + mem->AsmMemoryOperand.base = base; + mem->AsmMemoryOperand.index_op = index_op; + mem->AsmMemoryOperand.index = index; + mem->AsmMemoryOperand.scale_op = scale_op; + mem->AsmMemoryOperand.scale = scale; + mem->AsmMemoryOperand.disp_op = disp_op; + mem->AsmMemoryOperand.disp = disp; + mem->AsmMemoryOperand.close = close; + mem->AsmMemoryOperand.type = type; return mem; } diff --git a/src/parser.hpp b/src/parser.hpp index 8b6b72278..2dfb8be21 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -510,6 +510,7 @@ struct AstSplitArgs { }) \ AST_KIND(AsmMemoryOperand, "asm memory operand", struct { \ Token open; \ + Ast * segment_override; \ Ast * base; \ Token index_op; \ Ast * index; \ From 0bc9e6072510b4392a4942d98d14dd1bba15f718 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 14:44:59 +0100 Subject: [PATCH 88/92] Use new inline `asm` for `__chkstk` on Windows AMD64 --- base/runtime/procs_windows_amd64.odin | 50 +++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/base/runtime/procs_windows_amd64.odin b/base/runtime/procs_windows_amd64.odin index cedbc2bd8..18322e38f 100644 --- a/base/runtime/procs_windows_amd64.odin +++ b/base/runtime/procs_windows_amd64.odin @@ -22,6 +22,52 @@ windows_trap_type_assertion :: proc "contextless" () -> ! { } when ODIN_NO_CRT { - @(require) - foreign import crt_lib "procs_windows_amd64.asm" + @(export, link_name="_tls_index", private="file") + _tls_index: u32 = 0 + + @(export, link_name="_fltused", private="file") + _fltused: u32 = 0x9875 + + @(export, link_name="__chkstk", private="file") + __chkstk :: proc "naked" () { + internal :: asm() { + // Allocate 16 bytes to store values of r10 and r11 + sub %rsp, 0x10 + mov [%rsp], %r10 + mov [%rsp + 0x8], %r11 + // Set r10 to point to the stack as of the moment of the function call + lea %r10, [%rsp+0x18] + // Subtract r10 til the bottom of the stack allocation, if we overflow + // reset r10 to 0, we'll crash with segfault anyway + xor %r11, %r11 + sub %r10, %rax + cmovb %r10, %r11 + // Load r11 with the bottom of the stack (lowest allocated address) + mov %r11, [%gs:0x10] + // If the bottom of the allocation is above the bottom of the stack, + // we don't need to probe + cmp %r10, %r11 + jnb .end + // Align the bottom of the allocation down to page size + and %r10w, 0xf000 + .loop: + // Move the pointer to the next guard page, and touch it by loading 0 + // into that page + lea %r11, [%r11 - 0x1000] + mov [%r11]:u8, 0x0 + // Did we reach the bottom of the allocation? + cmp %r10, %r11 + jnz .loop + .end: + // Restore previous r10 and r11 and return + mov %r10, [%rsp] + mov %r11, [%rsp + 0x8] + add %rsp, 0x10 + ret + } + + internal() + } + // @(require) + // foreign import crt_lib "procs_windows_amd64.asm" } From a86e523053545fec8255d4fb75ab51b1e84ae123 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 14:57:34 +0100 Subject: [PATCH 89/92] Allow for inlineable asm calls --- base/runtime/procs_windows_amd64.odin | 6 ++---- src/check_asm.cpp | 8 ++++++++ src/check_decl.cpp | 6 +----- src/check_expr.cpp | 15 ++++++++++++--- src/checker.cpp | 3 +++ src/checker.hpp | 2 ++ src/parser.cpp | 1 + src/parser.hpp | 1 + 8 files changed, 30 insertions(+), 12 deletions(-) diff --git a/base/runtime/procs_windows_amd64.odin b/base/runtime/procs_windows_amd64.odin index 18322e38f..00b1ffc05 100644 --- a/base/runtime/procs_windows_amd64.odin +++ b/base/runtime/procs_windows_amd64.odin @@ -30,7 +30,7 @@ when ODIN_NO_CRT { @(export, link_name="__chkstk", private="file") __chkstk :: proc "naked" () { - internal :: asm() { + asm() { // Allocate 16 bytes to store values of r10 and r11 sub %rsp, 0x10 mov [%rsp], %r10 @@ -64,9 +64,7 @@ when ODIN_NO_CRT { mov %r11, [%rsp + 0x8] add %rsp, 0x10 ret - } - - internal() + }() } // @(require) // foreign import crt_lib "procs_windows_amd64.asm" diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 1b1cc4bd9..4443fc8a7 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -1681,4 +1681,12 @@ gb_internal void check_asm_template(AsmCtx *asm_ctx, CheckerContext *ctx, Entity if (previous_prefix != 0) { error(previous_prefix_instr, "A prefix must be immediately followed by an instruction, but the template ended"); } +} + +gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, DeclInfo *d) { + if (build_context.metrics.arch == TargetArch_amd64) { + check_asm_template(&g_asm_amd64, c, e, d); + } else { + error(e->token, "asm templates are not currently supported for this target"); + } } \ No newline at end of file diff --git a/src/check_decl.cpp b/src/check_decl.cpp index 72b4a5892..68553c25f 100644 --- a/src/check_decl.cpp +++ b/src/check_decl.cpp @@ -2202,11 +2202,7 @@ gb_internal void check_entity_decl(CheckerContext *ctx, Entity *e, DeclInfo *d, break; case Entity_AsmTemplate: - if (build_context.metrics.arch == TargetArch_amd64) { - check_asm_template(&g_asm_amd64, &c, e, d); - } else { - error(e->token, "asm templates are not currently supported for this target"); - } + check_asm_template_from_entity(&c, e, d); break; } diff --git a/src/check_expr.cpp b/src/check_expr.cpp index 1bc79a10a..9c04ee362 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -12432,9 +12432,18 @@ gb_internal ExprKind check_expr_base_internal(CheckerContext *c, Operand *o, Ast return kind; case_end; - case_ast_node(asm_template, AsmTemplate, node); - error(node, "Illegal use of an asm template outside of a named constant value declaration"); - o->mode = Addressing_Invalid; + case_ast_node(at, AsmTemplate, node); + Token token = at->token; + DeclInfo *d = make_decl_info(c->scope, c->decl); + Entity *e = alloc_entity_asm_template(d->scope, token, nullptr, node); + d->init_expr = node; + at->anonymous_entity = e; + + check_asm_template_from_entity(c, e, d); + + o->mode = Addressing_Value; + o->type = e->type; + o->expr = node; case_end; case_ast_node(i, Implicit, node); diff --git a/src/checker.cpp b/src/checker.cpp index d6ca0b350..25bbc0f56 100644 --- a/src/checker.cpp +++ b/src/checker.cpp @@ -1837,6 +1837,9 @@ retry:; case_ast_node(label, AsmLabelDecl, expr); return entity_of_node(label->name); case_end; + case_ast_node(at, AsmTemplate, expr); + return at->anonymous_entity; + case_end; } return nullptr; } diff --git a/src/checker.hpp b/src/checker.hpp index 1a53018e3..bdfd2c9c3 100644 --- a/src/checker.hpp +++ b/src/checker.hpp @@ -928,3 +928,5 @@ gb_internal GenTypesData *ensure_polymorphic_record_entity_has_gen_types(Checker gb_internal void init_map_internal_types(Type *type); + +gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, DeclInfo *d); diff --git a/src/parser.cpp b/src/parser.cpp index 543e89d0e..24e16102a 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -528,6 +528,7 @@ gb_internal Ast *clone_ast(Ast *node, AstFile *f) { n->AsmTemplate.specs = clone_ast_array(n->AsmTemplate.specs, f); n->AsmTemplate.clobbers = clone_ast_array(n->AsmTemplate.clobbers, f); n->AsmTemplate.instructions = clone_ast_array(n->AsmTemplate.instructions, f); + n->AsmTemplate.anonymous_entity = nullptr; break; case Ast_AsmRegister: break; diff --git a/src/parser.hpp b/src/parser.hpp index 2dfb8be21..4779e09a8 100644 --- a/src/parser.hpp +++ b/src/parser.hpp @@ -481,6 +481,7 @@ struct AstSplitArgs { Slice clobbers; \ Slice instructions; \ Token end; \ + Entity * anonymous_entity; \ }) \ AST_KIND(AsmRegister, "asm register", struct { \ Token token; \ From d06c25cada7e05840835753c1892eb59fb12a58b Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 15:01:49 +0100 Subject: [PATCH 90/92] Restrict usage of `asm` templates to be declarations or called directly --- src/check_expr.cpp | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/check_expr.cpp b/src/check_expr.cpp index 9c04ee362..c0474b955 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -8879,7 +8879,26 @@ gb_internal ExprKind check_call_expr(CheckerContext *c, Operand *operand, Ast *c } } else { if (proc != nullptr) { - check_expr_or_type(c, operand, proc); + Ast *unnested_proc = unparen_expr(proc); + if (unnested_proc->kind == Ast_AsmTemplate) { + // NOTE(bill): asm templates can only be used within as a declaration OR within a procedure call directly + ast_node(at, AsmTemplate, unnested_proc); + Token token = at->token; + DeclInfo *d = make_decl_info(c->scope, c->decl); + Entity *e = alloc_entity_asm_template(d->scope, token, nullptr, unnested_proc); + d->init_expr = unnested_proc; + at->anonymous_entity = e; + + check_asm_template_from_entity(c, e, d); + + operand->mode = Addressing_Value; + operand->type = e->type; + operand->value = {}; + operand->expr = proc; + add_type_and_value(c, proc, operand->mode, operand->type, operand->value); + } else { + check_expr_or_type(c, operand, proc); + } } else { GB_ASSERT(operand->expr != nullptr); } @@ -12433,17 +12452,11 @@ gb_internal ExprKind check_expr_base_internal(CheckerContext *c, Operand *o, Ast case_end; case_ast_node(at, AsmTemplate, node); - Token token = at->token; - DeclInfo *d = make_decl_info(c->scope, c->decl); - Entity *e = alloc_entity_asm_template(d->scope, token, nullptr, node); - d->init_expr = node; - at->anonymous_entity = e; - - check_asm_template_from_entity(c, e, d); - - o->mode = Addressing_Value; - o->type = e->type; + error(node, "'asm' templates must either be defined as a declaration or within a procedure call directly"); + o->mode = Addressing_NoValue; + o->type = nullptr; o->expr = node; + return kind; case_end; case_ast_node(i, Implicit, node); From 14184744ee04492ac7235693eb4e5895b84b102c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 18 Aug 2026 15:13:37 +0100 Subject: [PATCH 91/92] Add missing x86.clobber_forms.bin --- .../isa/x86/tables/x86.clobber_forms.bin | Bin 0 -> 39216 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deletion(-) diff --git a/src/llvm_backend_asm.cpp b/src/llvm_backend_asm.cpp index 2e5e93d00..972d763ea 100644 --- a/src/llvm_backend_asm.cpp +++ b/src/llvm_backend_asm.cpp @@ -1,3 +1,5 @@ +#define LLVM_ASM_DEBUG_PRINT false + struct lbAsmGenerate { Entity * tmpl_entity; AstAsmTemplate * tmpl_node; @@ -306,6 +308,10 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { asm_string = this->write_operand(asm_string, op_number, mem_op->disp, disp_flags); } + if (mem_op->base == nullptr && mem_op->index == nullptr) { + GB_ASSERT(mem_op->scale == nullptr); + return asm_string; + } asm_string = gb_string_appendc(asm_string, "("); if (mem_op->base != nullptr) { asm_string = this->write_operand(asm_string, op_number, mem_op->base, flags); @@ -668,7 +674,7 @@ struct lbAsmGenerate_amd64 : lbAsmGenerate { LLVMValueRef call = LLVMBuildCall2(p->builder, fn_ty, ia, call_args.data, cast(unsigned)call_args.count, ""); - if (false) { + if (LLVM_ASM_DEBUG_PRINT) { // DEBUG PRINT!!! // DEBUG PRINT!!! // DEBUG PRINT!!!