asm: Add support for constraint checks such as division by zero or overshifting

core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin

@@ -805,6 +805,22 @@ main :: proc() {
 		}
 	""")
 
+	strings.write_string(&sb, "\n")
+
+	strings.write_string(&sb, """
+		AsmOperandConstraint operand_value_constraint(u16 m, int op) const {
+			switch (m) {
+			case M_SLLI: case M_SRLI: case M_SRAI:
+				if (op == 2) return {AsmOperandConstraint_ShiftCount, /*XLEN*/-1};
+				break;
+			case M_DIV: case M_DIVU: case M_REM: case M_REMU:
+				if (op == 2) return {AsmOperandConstraint_NonZeroDivisor, -1};
+				break;
+			}
+			return {AsmOperandConstraint_None, -1};
+		}
+	""")
+
 	strings.write_string(&sb, "\n};\n")
 
 	strings.write_string(&sb, "\n\n\n")

core/rexcode/isa/x86/mnemonics.odin

@@ -53,6 +53,7 @@ Mnemonic :: enum u16 {
 	SHL,
 	SHR,
 	SAR,
+	SAL,
 	ROL,
 	ROR,
 	RCL,

core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin

@@ -807,6 +807,23 @@ main :: proc() {
 		}
 	""")
 
+	strings.write_string(&sb, "\n")
+
+	strings.write_string(&sb, """
+		AsmOperandConstraint operand_value_constraint(u16 m, int op) const {
+			switch (m) {
+			case M_SHL: case M_SHR: case M_SAR: case M_SAL:
+			case M_ROL: case M_ROR: case M_RCL: case M_RCR:
+				if (op == 1) return {AsmOperandConstraint_ShiftCount, /*width_operand*/0};
+				break;
+			case M_DIV: case M_IDIV:
+				if (op == 0) return {AsmOperandConstraint_NonZeroDivisor, -1};
+				break;
+			}
+			return {AsmOperandConstraint_None, -1};
+		}
+	""")
+
 	strings.write_string(&sb, "\n};\n")
 
 	strings.write_string(&sb, "\n\n\n")

core/rexcode/isa/x86/tablegen/instruction_table.odin

@@ -462,6 +462,20 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{
 		{{.SAR, {.RM64, .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
 		{{.SAR, {.RM64, .IMM8,     .NONE, .NONE}, {.MR, .IB,   .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
 	},
+	.SAL = {
+		{{.SAL, {.RM8,  .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM8,  .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM8,  .IMM8,     .NONE, .NONE}, {.MR, .IB,   .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true}},                   {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM16, .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM16, .IMM8,     .NONE, .NONE}, {.MR, .IB,   .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}},                   {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM32, .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}},                   {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM32, .IMM8,     .NONE, .NONE}, {.MR, .IB,   .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}},                   {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM64, .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+		{{.SAL, {.RM64, .IMM8,     .NONE, .NONE}, {.MR, .IB,   .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}},
+	},
 	.ROL = {
 		{{.ROL, {.RM8,  .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true}},                   {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}},
 		{{.ROL, {.RM8,  .CL_IMPL,  .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true}},                   {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}},