diff --git a/core/rexcode/isa/x86/mnemonic_builders.odin b/core/rexcode/isa/x86/mnemonic_builders.odin index c7b518e03..2957a1264 100644 --- a/core/rexcode/isa/x86/mnemonic_builders.odin +++ b/core/rexcode/isa/x86/mnemonic_builders.odin @@ -2159,12 +2159,6 @@ inst_movss_m32_xmm :: #force_inline proc "contextless" (dst: Me emit_movss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movss_xmm_xmm(dst, src)) } emit_movss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_movss_xmm_m32(dst, src)) } emit_movss_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_movss_m32_xmm(dst, src)) } -inst_movsd_sse_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 733) } -inst_movsd_sse_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 733) } -inst_movsd_sse_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD_SSE, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 734) } -emit_movsd_sse_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movsd_sse_xmm_xmm(dst, src)) } -emit_movsd_sse_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movsd_sse_xmm_m64(dst, src)) } -emit_movsd_sse_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movsd_sse_m64_xmm(dst, src)) } inst_movdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 735) } inst_movdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 735) } inst_movdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 736) } @@ -2417,10 +2411,6 @@ inst_cmpss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XM inst_cmpss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 809) } emit_cmpss_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpss_xmm_xmm_imm8(dst, src, imm)) } emit_cmpss_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_cmpss_xmm_m32_imm8(dst, src, imm)) } -inst_cmpsd_sse_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD_SSE, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 810) } -inst_cmpsd_sse_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD_SSE, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 810) } -emit_cmpsd_sse_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpsd_sse_xmm_xmm_imm8(dst, src, imm)) } -emit_cmpsd_sse_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64, imm: i8) { append(instructions, inst_cmpsd_sse_xmm_m64_imm8(dst, src, imm)) } inst_comiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 811) } inst_comiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 811) } emit_comiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_comiss_xmm_xmm(dst, src)) } @@ -8030,8 +8020,6 @@ inst_movupd :: proc{ inst_movupd_xmm_xmm, inst_movu emit_movupd :: proc{ emit_movupd_xmm_xmm, emit_movupd_xmm_m128, emit_movupd_m128_xmm } inst_movss :: proc{ inst_movss_xmm_xmm, inst_movss_xmm_m32, inst_movss_m32_xmm } emit_movss :: proc{ emit_movss_xmm_xmm, emit_movss_xmm_m32, emit_movss_m32_xmm } -inst_movsd_sse :: proc{ inst_movsd_sse_xmm_xmm, inst_movsd_sse_xmm_m64, inst_movsd_sse_m64_xmm } -emit_movsd_sse :: proc{ emit_movsd_sse_xmm_xmm, emit_movsd_sse_xmm_m64, emit_movsd_sse_m64_xmm } inst_movdqa :: proc{ inst_movdqa_xmm_xmm, inst_movdqa_xmm_m128, inst_movdqa_m128_xmm } emit_movdqa :: proc{ emit_movdqa_xmm_xmm, emit_movdqa_xmm_m128, emit_movdqa_m128_xmm } inst_movdqu :: proc{ inst_movdqu_xmm_xmm, inst_movdqu_xmm_m128, inst_movdqu_m128_xmm } @@ -8150,8 +8138,6 @@ inst_cmppd :: proc{ inst_cmppd_xmm_xmm_imm8, inst_ emit_cmppd :: proc{ emit_cmppd_xmm_xmm_imm8, emit_cmppd_xmm_m128_imm8 } inst_cmpss :: proc{ inst_cmpss_xmm_xmm_imm8, inst_cmpss_xmm_m32_imm8 } emit_cmpss :: proc{ emit_cmpss_xmm_xmm_imm8, emit_cmpss_xmm_m32_imm8 } -inst_cmpsd_sse :: proc{ inst_cmpsd_sse_xmm_xmm_imm8, inst_cmpsd_sse_xmm_m64_imm8 } -emit_cmpsd_sse :: proc{ emit_cmpsd_sse_xmm_xmm_imm8, emit_cmpsd_sse_xmm_m64_imm8 } inst_comiss :: proc{ inst_comiss_xmm_xmm, inst_comiss_xmm_m32 } emit_comiss :: proc{ emit_comiss_xmm_xmm, emit_comiss_xmm_m32 } inst_comisd :: proc{ inst_comisd_xmm_xmm, inst_comisd_xmm_m64 } diff --git a/core/rexcode/isa/x86/mnemonics.odin b/core/rexcode/isa/x86/mnemonics.odin index 7428b208a..e654bcd95 100644 --- a/core/rexcode/isa/x86/mnemonics.odin +++ b/core/rexcode/isa/x86/mnemonics.odin @@ -300,7 +300,6 @@ Mnemonic :: enum u16 { MOVAPD, MOVUPD, MOVSS, - MOVSD_SSE, // distinguish from string MOVSD MOVDQA, MOVDQU, MOVQ, @@ -360,7 +359,6 @@ Mnemonic :: enum u16 { CMPPS, CMPPD, CMPSS, - CMPSD_SSE, COMISS, COMISD, UCOMISS, diff --git a/core/rexcode/isa/x86/printer.odin b/core/rexcode/isa/x86/printer.odin index 687fbf55f..30ea392a9 100644 --- a/core/rexcode/isa/x86/printer.odin +++ b/core/rexcode/isa/x86/printer.odin @@ -51,9 +51,7 @@ Print_Result :: isa.Print_Result mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool) -> string { #partial switch m { - case .INVALID: return "???" - case .MOVSD_SSE: return lowercase ? "movsd" : "MOVSD" - case .CMPSD_SSE: return lowercase ? "cmpsd" : "CMPSD" + case .INVALID: return "???" } if name, ok := reflect.enum_name_from_value(m); ok { return lowercase ? strings.to_lower(name, context.temp_allocator) : name diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index 857b604be..3bc0a9b19 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -1,1275 +1,4867 @@ -// clobber_table.odin -- auxiliary side-effect table for rexcode_x86_tablegen +// clobber_table.odin -- PER-FORM side-effect table for rexcode_x86_tablegen // -// DERIVED, NOT EXTRACTED. The ENCODING_TABLE describes how bytes are laid out -// (opcode, ModRM roles, prefixes, REX). It carries no read/write direction and -// no implicit side effects, so this table cannot be produced from it alone -- -// it is a hand-authored semantics layer sourced from the Intel SDM Vol.2 -// ("Operation" + "Flags Affected") applied per instruction family. +// Type: [Mnemonic][]x86.Clobber (parallel to [Mnemonic][]Encoding) // -// Conventions: -// written / read explicit operand slots (OP0..OP3). rmw = written & read. -// implicit_wr / _rd registers touched that are NOT explicit operands -// (widths follow operand size; e.g. RAX means AL/AX/EAX/RAX). -// flags_wr EFLAGS set to a DEFINED value (a cleared flag counts). -// flags_undef EFLAGS left ARCHITECTURALLY UNDEFINED (must be treated -// as clobbered by a compiler, value not guaranteed). -// flags_rd EFLAGS consumed by the instruction. -// writes_mem/reads_mem memory VALUE touched (explicit mem operand or -// implicit: PUSH/CALL/string ops/gather/scatter/etc). -// side_effects effects that are NOT clobbers but still make the -// instruction non-eliminable and/or non-reorderable -// (fences, serialization, traps, control flow, ...). -// This is what separates MFENCE -- orders memory, -// clobbers nothing -- from a genuine no-op. -// FPU_ST/FPU_SW = x87 stack / status word; MXCSR = SSE control-status; -// VECTOR = the whole SIMD register file (VZEROALL/VZEROUPPER). +// HOW EACH FORM IS SPECIALISED FROM THE UNION: +// 1. Implicit-operand normalisation. An operand that is an implicit register +// (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, +// ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from the +// OP0..OP3 slot set and, if that slot was written/read, folded into +// implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an +// operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) +// are inherent and kept on every form. +// 2. Slot trimming. OP slots that are .NONE in a given form are dropped from +// written/read. +// 3. Per-form memory. writes_mem/reads_mem keep the union's DIRECTION but are +// asserted on a form only when that form actually carries a memory-capable +// operand, OR the instruction addresses memory implicitly (stack, string, +// XLAT table, MASKMOVDQU/[rDI] store, VMCS, shadow stack). Consequently +// register-only forms of otherwise-memory instructions (e.g. MOV r,imm; +// FADD ST(0),ST(i); FST ST(i); MOVLHPS; PEXTRW r32,xmm) no longer carry the +// blanket memory flag the union used. +// 4. Family splits that the union could only approximate: +// IMUL -- 1-operand form writes RDX:RAX implicitly (r/m8 -> AX only); +// 2-operand form is OP0 *= OP1; 3-operand form is OP0 = OP1 * imm +// (OP0 not read); neither multi-operand form touches RAX/RDX. +// MUL/DIV/IDIV -- the r/m8 form uses the A-register only and does not +// touch (R)DX. +// SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD -- only the CL form reads RCX; +// the 1/imm8 forms do not. +// Flags and side_effects are uniform across a mnemonic's forms and are carried +// through unchanged. // -// INVARIANT: an instruction is a pure, freely-eliminable no-op iff every -// clobber set is empty AND side_effects == {}. In this table only .NOP -// (and the .INVALID sentinel) satisfy that. +// INVARIANT preserved: a form is a freely-eliminable no-op iff every clobber set +// is empty AND side_effects == {} (only .NOP and the .INVALID sentinel qualify). package rexcode_x86_tablegen import "core:rexcode/isa/x86" @(rodata) -CLOBBER_TABLE := [Mnemonic]x86.Clobber{ +CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .INVALID = {}, - // ---- 8.1 Data Transfer Encodings ---- - .MOV = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - .MOVABS = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - .MOVZX = {written={.OP0}, read={.OP1}, reads_mem=true}, - .MOVSX = {written={.OP0}, read={.OP1}, reads_mem=true}, - .MOVSXD = {written={.OP0}, read={.OP1}, reads_mem=true}, - .XCHG = {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, // asserts LOCK when a mem operand is used - .PUSH = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - .POP = {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - .LEA = {written={.OP0}}, // no memory access: computes effective address only - // ---- 8.2 Arithmetic Encodings ---- - .ADD = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .ADC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .SUB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .SBB = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .MUL = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // RAX/RDX widths follow operand size (r/m8 -> AX only) - .IMUL = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.SF, .ZF, .AF, .PF}, reads_mem=true}, // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit - .DIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only - .IDIV = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // RDX:RAX = quotient/remainder; r/m8 uses AX only - .INC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected - .DEC = {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // CF deliberately NOT affected - .NEG = {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - .CMP = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // no operand written; flags only + // 8.1 Data Transfer Encodings + .MOV = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVABS = { + {written={.OP0}, read={.OP1}}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + }, + .MOVZX = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSX = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSXD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XCHG = { // asserts LOCK when a mem operand is used + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + }, + .PUSH = { + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + }, + .POP = { + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + }, + .LEA = { // no memory access: computes effective address only + {written={.OP0}}, + {written={.OP0}}, + {written={.OP0}}, + }, - // ---- 8.3 Logical Encodings ---- - .AND = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .OR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .XOR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - .NOT = {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - .TEST = {read={.OP0, .OP1}, flags_wr={.OF, .CF, .SF, .ZF, .PF}, flags_undef={.AF}, reads_mem=true}, // no operand written; flags only + // 8.2 Arithmetic Encodings + .ADD = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .ADC = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .SUB = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .SBB = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .MUL = { // RAX/RDX widths follow operand size (r/m8 -> AX only) + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + }, + .IMUL = { // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + }, + .DIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .IDIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .INC = { // CF deliberately NOT affected + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .DEC = { // CF deliberately NOT affected + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .NEG = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .CMP = { // no operand written; flags only + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, - // ---- 8.4 Shift/Rotate Encodings ---- - .SHL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .SHR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .SAR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // OF defined only for 1-bit count; count==0 leaves flags unchanged - .ROL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged - .ROR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // only CF/OF affected; count==0 leaves flags unchanged - .RCL = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .RCR = {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - .SHLD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, - .SHRD = {written={.OP0}, read={.OP0, .OP1, .OP2}, implicit_rd={.RCX}, flags_wr={.CF, .SF, .ZF, .PF}, flags_undef={.OF, .AF}, writes_mem=true, reads_mem=true}, + // 8.3 Logical Encodings + .AND = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .OR = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .XOR = { + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .NOT = { + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + }, + .TEST = { // no operand written; flags only + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + }, - // ---- 8.5 Bit Operation Encodings ---- - .BT = {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF unaffected - .BTS = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BTR = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BTC = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.OF, .SF, .AF, .PF}, writes_mem=true, reads_mem=true}, // ZF unaffected - .BSF = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 - .BSR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .OF, .SF, .AF, .PF}, reads_mem=true}, // destination undefined when source == 0 - .POPCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // ZF per source; CF/OF/SF/AF/PF cleared - .LZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, - .TZCNT = {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, + // 8.4 Shift/Rotate Encodings + .SHL = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .SHR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .SAR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + }, + .ROL = { // only CF/OF affected; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + }, + .ROR = { // only CF/OF affected; count==0 leaves flags unchanged + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + }, + .RCL = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .RCR = { + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + }, + .SHLD = { + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + }, + .SHRD = { + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.6 Control Flow Encodings ---- - .JMP = {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, // indirect forms read reg/mem; writes RIP - .JA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNA = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNAE = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNB = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNBE = {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNC = {flags_rd={.CF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNE = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNZ = {flags_rd={.ZF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNG = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNGE = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNL = {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNLE = {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JNS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JO = {flags_rd={.OF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JP = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JPE = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JPO = {flags_rd={.PF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JS = {flags_rd={.SF}, side_effects={.CONTROL}}, // reads flags; writes RIP on taken branch - .JCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads CX - .JECXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads ECX - .JRCXZ = {implicit_rd={.RCX}, side_effects={.CONTROL}}, // reads RCX - .LOOP = {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, - .LOOPE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - .LOOPNE = {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - .CALL = {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, // pushes return address - .RET = {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, // pops return address (+imm16 form adjusts RSP) - .IRET = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .IRETD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .IRETQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // pops RIP/CS/RFLAGS (privileged bits conditionally) - .INT = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate - .INT3 = {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // pushes RFLAGS/CS/RIP; clears TF/IF via gate - .INTO = {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.OF, .CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // #OF only if OF=1 - .SYSCALL = {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK - .SYSRET = {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // RIP<-RCX, RFLAGS<-R11 - .SYSENTER = {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, // privileged; RSP/RIP from MSRs - .SYSEXIT = {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX + // 8.5 Bit Operation Encodings + .BT = { // ZF unaffected + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .BTS = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BTR = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BTC = { // ZF unaffected + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .BSF = { // destination undefined when source == 0 + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .BSR = { // destination undefined when source == 0 + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .POPCNT = { // ZF per source; CF/OF/SF/AF/PF cleared + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .LZCNT = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .TZCNT = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, - // ---- 8.7 Conditional Set/Move Encodings ---- - .SETA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNA = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETNAE = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNB = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNBE = {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, - .SETNC = {written={.OP0}, flags_rd={.CF}, writes_mem=true}, - .SETNE = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETNG = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNGE = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETNL = {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, - .SETNLE = {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - .SETNO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, - .SETNP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETNS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, - .SETNZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .SETO = {written={.OP0}, flags_rd={.OF}, writes_mem=true}, - .SETP = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETPE = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETPO = {written={.OP0}, flags_rd={.PF}, writes_mem=true}, - .SETS = {written={.OP0}, flags_rd={.SF}, writes_mem=true}, - .SETZ = {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, - .CMOVA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNA = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNAE = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNB = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNBE = {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNC = {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, // conditional write of OP0 - .CMOVNE = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVNG = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNGE = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNL = {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNLE = {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 - .CMOVNP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVNS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 - .CMOVNZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 - .CMOVO = {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, // conditional write of OP0 - .CMOVP = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVPE = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVPO = {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, // conditional write of OP0 - .CMOVS = {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, // conditional write of OP0 - .CMOVZ = {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, // conditional write of OP0 + // 8.6 Control Flow Encodings + .JMP = { // indirect forms read reg/mem; writes RIP + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + }, + .JA = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JAE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JB = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JBE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JC = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JZ = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JG = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JGE = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JL = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JLE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNA = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JNAE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNB = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNBE = { // reads flags; writes RIP on taken branch + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + }, + .JNC = { // reads flags; writes RIP on taken branch + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + }, + .JNE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JNZ = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .JNG = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNGE = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JNL = { // reads flags; writes RIP on taken branch + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + }, + .JNLE = { // reads flags; writes RIP on taken branch + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + }, + .JNO = { // reads flags; writes RIP on taken branch + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + }, + .JNP = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JNS = { // reads flags; writes RIP on taken branch + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + }, + .JO = { // reads flags; writes RIP on taken branch + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + }, + .JP = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JPE = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JPO = { // reads flags; writes RIP on taken branch + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + }, + .JS = { // reads flags; writes RIP on taken branch + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + }, + .JCXZ = { // reads CX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .JECXZ = { // reads ECX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .JRCXZ = { // reads RCX + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .LOOP = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, + }, + .LOOPE = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .LOOPNE = { + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + }, + .CALL = { // pushes return address + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + }, + .RET = { // pops return address (+imm16 form adjusts RSP) + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + }, + .IRET = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .IRETD = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .IRETQ = { // pops RIP/CS/RFLAGS (privileged bits conditionally) + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + }, + .INT = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate + {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .INT3 = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .INTO = { // #OF only if OF=1 + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSCALL = { // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK + {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSRET = { // RIP<-RCX, RFLAGS<-R11 + {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + }, + .SYSENTER = { // privileged; RSP/RIP from MSRs + {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, + }, + .SYSEXIT = { // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX + {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + }, - // ---- 8.8 String Operation Encodings ---- - .MOVS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .MOVSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPS = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSB = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSW = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSD = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .CMPSQ = {implicit_wr={.RSI, .RDI, .RCX}, implicit_rd={.RSI, .RDI, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCAS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .SCASQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODS = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSB = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSW = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSD = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .LODSQ = {implicit_wr={.RSI, .RAX}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOS = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSB = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSW = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSD = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX - .STOSQ = {implicit_wr={.RDI, .RCX}, implicit_rd={.RDI, .RAX, .RCX}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // REP/REPZ/REPNZ forms read+write RCX + // 8.7 Conditional Set/Move Encodings + .SETA = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETAE = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETB = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETBE = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETC = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETE = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETG = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETGE = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETL = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETLE = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNA = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETNAE = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNB = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNBE = { + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + }, + .SETNC = { + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + }, + .SETNE = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETNG = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNGE = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETNL = { + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + }, + .SETNLE = { + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + }, + .SETNO = { + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + }, + .SETNP = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETNS = { + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + }, + .SETNZ = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .SETO = { + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + }, + .SETP = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETPE = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETPO = { + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + }, + .SETS = { + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + }, + .SETZ = { + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + }, + .CMOVA = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVAE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVB = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVBE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVC = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVG = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVGE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVL = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVLE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNA = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVNAE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNB = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNBE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + }, + .CMOVNC = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + }, + .CMOVNE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVNG = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNGE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVNL = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + }, + .CMOVNLE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + }, + .CMOVNO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + }, + .CMOVNP = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVNS = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + }, + .CMOVNZ = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, + .CMOVO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + }, + .CMOVP = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVPE = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVPO = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + }, + .CMOVS = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + }, + .CMOVZ = { // conditional write of OP0 + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + }, - // ---- 8.9 Flag Operation Encodings ---- - .CLC = {flags_wr={.CF}}, - .STC = {flags_wr={.CF}}, - .CMC = {flags_wr={.CF}, flags_rd={.CF}}, - .CLD = {flags_wr={.DF}}, - .STD = {flags_wr={.DF}}, - .CLI = {flags_wr={.IF}}, - .STI = {flags_wr={.IF}}, - .LAHF = {implicit_wr={.RAX}, flags_rd={.SF, .ZF, .AF, .PF, .CF}}, // AH <- flags - .SAHF = {implicit_rd={.RAX}, flags_wr={.SF, .ZF, .AF, .PF, .CF}}, // flags <- AH - .PUSHF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .PUSHFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .PUSHFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - .POPF = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - .POPFD = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - .POPFQ = {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // 8.8 String Operation Encodings + .MOVS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .MOVSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // SSE variants + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .CMPS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .CMPSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCAS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .SCASQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + }, + .LODS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .LODSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + }, + .STOS = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSB = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSW = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSD = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, + .STOSQ = { // REP/REPZ/REPNZ forms read+write RCX + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.10 Miscellaneous Encodings ---- - .NOP = {}, // no register/flag/memory clobber - .HLT = {side_effects={.HALT, .PRIVILEGED}}, // no register/flag/memory clobber - .WAIT = {implicit_rd={.FPU_SW}}, // waits on pending x87 exception - .LOCK = {side_effects={.FENCE}}, // no register/flag/memory clobber - .UD0 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .UD1 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .UD2 = {side_effects={.TRAP}}, // no register/flag/memory clobber - .CPUID = {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, - .RDTSC = {implicit_wr={.RAX, .RDX}}, - .RDTSCP = {implicit_wr={.RAX, .RDX, .RCX}}, - .RDPMC = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - .XGETBV = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - .XSETBV = {implicit_rd={.RCX, .RDX, .RAX}}, // privileged; writes XCR[ECX] - .CBW = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CWDE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CDQE = {implicit_wr={.RAX}, implicit_rd={.RAX}}, - .CWD = {implicit_wr={.RDX}, implicit_rd={.RAX}}, - .CDQ = {implicit_wr={.RDX}, implicit_rd={.RAX}}, - .CQO = {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // 8.9 Flag Operation Encodings + .CLC = { + {flags_wr={.CF}}, + }, + .STC = { + {flags_wr={.CF}}, + }, + .CMC = { + {flags_wr={.CF}, flags_rd={.CF}}, + }, + .CLD = { + {flags_wr={.DF}}, + }, + .STD = { + {flags_wr={.DF}}, + }, + .CLI = { + {flags_wr={.IF}}, + }, + .STI = { + {flags_wr={.IF}}, + }, + .LAHF = { // AH <- flags + {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}, + }, + .SAHF = { // flags <- AH + {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}, + }, + .PUSHF = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .PUSHFD = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .PUSHFQ = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + }, + .POPF = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, + .POPFD = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, + .POPFQ = { + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + }, - // ---- 8.11 BMI/ADX Encodings ---- - .ANDN = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.SF, .ZF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BEXTR = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .CF, .OF}, flags_undef={.SF, .AF, .PF}, reads_mem=true}, - .BLSI = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BLSMSK = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BLSR = {written={.OP0}, read={.OP1}, flags_wr={.CF, .SF, .ZF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .BZHI = {written={.OP0}, read={.OP1, .OP2}, flags_wr={.ZF, .SF, .CF, .OF}, flags_undef={.AF, .PF}, reads_mem=true}, - .PDEP = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected - .PEXT = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected - .RORX = {written={.OP0}, read={.OP1}, reads_mem=true}, // no flags affected - .SARX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .SHLX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .SHRX = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // no flags affected (unlike SAR/SHL/SHR) - .MULX = {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, // no flags affected; implicit multiplicand in rDX - .ADCX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, // only CF (chains with ADCX) - .ADOX = {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, // only OF (chains with ADOX) + // 8.10 Miscellaneous Encodings + .NOP = { // no register/flag/memory clobber + {}, + {}, + {}, + {}, + }, + .HLT = { // no register/flag/memory clobber + {side_effects={.HALT, .PRIVILEGED}}, + }, + .WAIT = { // waits on pending x87 exception + {implicit_rd={.FPU_SW}}, + }, + .LOCK = { // no register/flag/memory clobber + {side_effects={.FENCE}}, + }, + .UD0 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .UD1 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .UD2 = { // no register/flag/memory clobber + {side_effects={.TRAP}}, + }, + .CPUID = { + {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + }, + .RDTSC = { + {implicit_wr={.RAX, .RDX}}, + }, + .RDTSCP = { + {implicit_wr={.RAX, .RCX, .RDX}}, + }, + .RDPMC = { + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + }, + .XGETBV = { + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + }, + .XSETBV = { // privileged; writes XCR[ECX] + {implicit_rd={.RAX, .RCX, .RDX}}, + }, + .CBW = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CWDE = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CDQE = { + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + }, + .CWD = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, + .CDQ = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, + .CQO = { + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + }, - // ---- 8.12 SSE Encodings ---- - .MOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR - .MOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR - .MOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .MOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .SQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .RSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .ORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .XORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .XORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CMPSD_SSE = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .COMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .COMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .UCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .UCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .SHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .UNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .CVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .CVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .PADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PADDUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBUSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSUBUSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .POR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR - .PAVGB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PAVGW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] - .LFENCE = {side_effects={.FENCE, .SERIALIZING}}, // ordering/hint; no clobber - .SFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber - .MFENCE = {side_effects={.FENCE}}, // ordering/hint; no clobber - .PAUSE = {side_effects={.HINT}}, // ordering/hint; no clobber - .CLFLUSH = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // flushes cache line for the addressed byte - .ADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .HSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .MOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .LDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .BLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .DPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .DPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .EXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .INSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .MPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .PHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .ROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .ROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .PCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .CRC32 = {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, // accumulates CRC into OP0; no flags - .PCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .PCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .PCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - .PCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - .PCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .PCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .AESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1NEXTE = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA1RNDS4 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256MSG1 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256MSG2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .SHA256RNDS2 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // 8.11 BMI/ADX Encodings + .ANDN = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BEXTR = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + }, + .BLSI = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BLSMSK = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BLSR = { + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .BZHI = { + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + }, + .PDEP = { // no flags affected + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PEXT = { // no flags affected + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .RORX = { // no flags affected + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SARX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHLX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHRX = { // no flags affected (unlike SAR/SHL/SHR) + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .MULX = { // no flags affected; implicit multiplicand in rDX + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + }, + .ADCX = { // only CF (chains with ADCX) + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + }, + .ADOX = { // only OF (chains with ADOX) + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + }, - // ---- 8.13 AVX/AVX2 Encodings ---- - .VADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSUBSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMULSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDIVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSQRTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDNPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VANDNPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VXORPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VXORPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCMPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCMPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VUCOMISS = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VUCOMISD = {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}, reads_mem=true}, // OF/SF/AF cleared - .VSHUFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VSHUFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VUNPCKHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VDPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VDPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VROUNDSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VEXTRACTPS = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VINSERTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVAPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVUPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVAPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVUPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVHPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVLHPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVHLPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVMSKPS = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VMOVMSKPD = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VMOVNTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMOVNTDQA = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VADDSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VADDSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHADDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHADDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHSUBPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VHSUBPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VLDDQU = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVSLDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVSHDUP = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPESTRI = {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .VPCMPESTRM = {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - .VPCMPISTRI = {implicit_wr={.RCX}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - .VPCMPISTRM = {implicit_wr={.XMM0}, flags_wr={.CF, .ZF, .SF, .OF, .AF, .PF}, reads_mem=true}, // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - .VPBROADCASTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBROADCASTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCVTPS2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPD2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSS2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSD2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTDQ2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTDQ2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTSI2SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTSI2SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTPS2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTPD2DQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTTSS2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VCVTTSD2SI = {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, // destination is a GPR - .VPADDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPADDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSUBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULUDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMADDWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPAND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPANDN = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPXOR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPEQQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPGTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKSSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKSSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPACKUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKLQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPUNPCKHQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFHW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSHUFLW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXTRB = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRW = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRD = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPEXTRQ = {written={.OP0}, read={.OP1}, writes_mem=true}, // destination may be memory - .VPINSRB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPINSRQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVMSKB = {written={.OP0}, read={.OP1}}, // destination is a GPR - .VPTEST = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VPSHUFB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHADDSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHSUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMADDUBSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULHRSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGNB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGNW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPABSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPALIGNR = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDVB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPHMINPOSUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMAXUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINSB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINUW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMINUD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXBQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXWD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXWQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVZXDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMASKMOVDQU = {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // byte-masked store to DS:[rDI] - .VPCLMULQDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESDEC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESDECLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESENC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESENCLAST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESIMC = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VAESKEYGENASSIST = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBROADCASTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXTRACTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VINSERTF128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERM2F128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMASKMOVPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VMASKMOVPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VTESTPS = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VTESTPD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF}, flags_undef={.OF, .SF, .AF, .PF}, reads_mem=true}, // ZF from AND, CF from ANDN; others cleared - .VZEROALL = {implicit_wr={.VECTOR}}, // zeroes the entire vector register file (YMM/ZMM) - .VZEROUPPER = {implicit_wr={.VECTOR}}, // zeroes bits [MAXVL-1:128] of every vector register - .VBROADCASTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXTRACTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VINSERTI128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERM2I128 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMASKMOVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VPMASKMOVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, writes_mem=true, reads_mem=true}, - .VGATHERDPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERDPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERQPS = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VGATHERQPD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERDD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERDQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERQD = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered - .VPGATHERQQ = {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, // mask operand (OP2) is zeroed as elements are gathered + // 8.12 SSE Encodings + .MOVAPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVUPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVAPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVUPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVSS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVDQA = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVDQU = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVHPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVHPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVLHPS = { + {written={.OP0}, read={.OP1}}, + }, + .MOVHLPS = { + {written={.OP0}, read={.OP1}}, + }, + .MOVMSKPS = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVMSKPD = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .MOVNTPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTDQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .MOVNTDQA = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SUBSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MULSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DIVSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .SQRTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RCPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RCPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .RSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MAXSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MINSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ANDPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDNPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ANDNPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ORPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .ORPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XORPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .XORPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CMPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CMPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .COMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .COMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .UCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .UCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .SHUFPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHUFPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .UNPCKLPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKHPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKLPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .UNPCKHPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CVTPS2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPD2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSS2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSD2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTDQ2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTDQ2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSI2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTSI2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .CVTTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .PADDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDUSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PADDUSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBUSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSUBUSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULUDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMADDWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PAND = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PANDN = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .POR = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PXOR = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSLLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSLLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSLLQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRLQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRAW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PSRAD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .PCMPEQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPEQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPEQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCMPGTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKSSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKSSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PACKUSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKLQDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PUNPCKHQDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSHUFD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PSHUFW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PEXTRW = { // destination may be memory + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .PINSRW = { + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PMOVMSKB = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .PAVGB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PAVGW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSADBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MASKMOVDQU = { // byte-masked store to DS:[rDI] + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + }, + .LFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE, .SERIALIZING}}, + }, + .SFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE}}, + }, + .MFENCE = { // ordering/hint; no clobber + {side_effects={.FENCE}}, + }, + .PAUSE = { // ordering/hint; no clobber + {side_effects={.HINT}}, + }, + .CLFLUSH = { // flushes cache line for the addressed byte + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .ADDSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ADDSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .HSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .MOVDDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSLDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .MOVSHDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .LDDQU = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSHUFB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHADDSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PHSUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMADDUBSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULHRSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGNB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGNW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PSIGND = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PABSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PALIGNR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .BLENDVPS = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .BLENDVPD = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .PBLENDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PBLENDVB = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, + .DPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .DPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .EXTRACTPS = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .INSERTPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .MPSADBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PACKUSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PEXTRB = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PEXTRD = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PEXTRQ = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .PHMINPOSUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PINSRB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PINSRD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PINSRQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .PMAXSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMAXUD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMINUD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVSXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXBQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMOVZXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PMULLD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PTEST = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .ROUNDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .ROUNDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .PCMPEQQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .CRC32 = { // accumulates CRC into OP0; no flags + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + }, + .PCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .PCMPGTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .PCLMULQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .AESDEC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESDECLAST = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESENC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESENCLAST = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESIMC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .AESKEYGENASSIST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHA1MSG1 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1MSG2 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1NEXTE = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA1RNDS4 = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .SHA256MSG1 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA256MSG2 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .SHA256RNDS2 = { + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + }, - // ---- 8.14 FMA Encodings ---- - .VFMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMADD231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB132SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB213SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFNMSUB231SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMADDSUB231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD132PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD213PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD231PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD132PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD213PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFMSUBADD231PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPH2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VCVTPS2PH = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, // may set MXCSR exception/status bits + // 8.13 AVX/AVX2 Encodings + .VADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSUBSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMULSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDIVSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSQRTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMAXSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VMINSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VANDPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDNPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VANDNPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VORPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VORPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VXORPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VXORPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VCMPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCMPSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VUCOMISS = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VUCOMISD = { // OF/SF/AF cleared + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + }, + .VSHUFPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VSHUFPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VUNPCKLPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKHPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKLPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VUNPCKHPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDVPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VBLENDVPD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VDPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VDPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VROUNDSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VEXTRACTPS = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VINSERTPS = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMOVAPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVUPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVAPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVUPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVSS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVSD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVDQA = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVDQU = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVHPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVHPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVLHPS = { + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVHLPS = { + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VMOVMSKPS = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVMSKPD = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VMOVNTPS = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTPD = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTDQ = { + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .VMOVNTDQA = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VADDSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VADDSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHADDPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHADDPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHSUBPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VHSUBPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VLDDQU = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVSLDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVSHDUP = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + }, + .VPBROADCASTB = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTW = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTD = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBROADCASTQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCVTPS2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPD2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSS2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSD2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTDQ2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTDQ2PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSI2SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTSI2SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTPS2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTPD2DQ = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTSS2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTTSD2SI = { // destination is a GPR + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VPADDB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPADDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSUBQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULUDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMADDWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPAND = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPANDN = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPOR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPXOR = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSLLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSLLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRAW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPSRAD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + }, + .VPCMPEQB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPEQQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPGTQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKSSWB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKSSDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKUSWB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPACKUSDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKLQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHWD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPUNPCKHQDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFHW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSHUFLW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPEXTRB = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRW = { // destination may be memory + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRD = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPEXTRQ = { // destination may be memory + {written={.OP0}, read={.OP1}, writes_mem=true}, + }, + .VPINSRB = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPINSRQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPMOVMSKB = { // destination is a GPR + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPTEST = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VPSHUFB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHADDSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPHSUBSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMADDUBSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULHRSW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGNB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGNW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSIGND = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPABSB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPABSW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPABSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPALIGNR = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPBLENDW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPBLENDVB = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMPSADBW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPHMINPOSUW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMAXSB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXSD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMAXUD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINSB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINSD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINUW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMINUD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMOVSXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXBQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXBQ = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXWD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXWQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVZXDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMULDQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMULLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VMASKMOVDQU = { // byte-masked store to DS:[rDI] + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + }, + .VPCLMULQDQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VAESDEC = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESDECLAST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESENC = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESENCLAST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VAESIMC = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VAESKEYGENASSIST = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBROADCASTSS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VBROADCASTSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + }, + .VBROADCASTF128 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXTRACTF128 = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VINSERTF128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERM2F128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VMASKMOVPS = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VMASKMOVPD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VTESTPS = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VTESTPD = { // ZF from AND, CF from ANDN; others cleared + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + }, + .VZEROALL = { // zeroes the entire vector register file (YMM/ZMM) + {implicit_wr={.VECTOR}}, + }, + .VZEROUPPER = { // zeroes bits [MAXVL-1:128] of every vector register + {implicit_wr={.VECTOR}}, + }, + .VBROADCASTI128 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXTRACTI128 = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VINSERTI128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERM2I128 = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPERMD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPSLLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRAVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMASKMOVD = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VPMASKMOVQ = { + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + }, + .VGATHERDPS = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERDPD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERQPS = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VGATHERQPD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERDD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERDQ = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERQD = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, + .VPGATHERQQ = { // mask operand (OP2) is zeroed as elements are gathered + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + }, - // ---- 8.15 AVX-512 Encodings ---- - .VMOVDQA32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQA64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU8 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU16 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU32 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VMOVDQU64 = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPBLENDMQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VBLENDMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCMPB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCMPUQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMB = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMW = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMD = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPTESTNMQ = {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, // result written to an opmask register (k1), not EFLAGS - .VPCOMPRESSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCOMPRESSQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCOMPRESSPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VCOMPRESSPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXPANDD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPEXPANDQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXPANDPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VEXPANDPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCONFLICTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPCONFLICTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPLZCNTD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPLZCNTQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMI2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMT2PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPERMW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVB2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVW2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVD2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVQ2M = {written={.OP0}, read={.OP1}}, // sign bits -> opmask register - .VPMOVM2B = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2W = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2D = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVM2Q = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSQD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSDB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSDW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMOVUSWB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPROLVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORVD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPRORVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSCATTERDD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERDQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERQD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSCATTERQQ = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERDPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERDPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERQPS = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VSCATTERQPD = {read={.OP0, .OP1}, writes_mem=true}, // opmask k1 is consumed and cleared per element - .VPSRAVQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRAVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSLLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPSRLVW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VRANGEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRANGESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VREDUCESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALEPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALEPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALESS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRNDSCALESD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRSQRT14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14PS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14PD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14SS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VRCP14SD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VSCALEFSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETEXPSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VGETMANTSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMPS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMPD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMSS = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFIXUPIMMSD = {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, // may set MXCSR exception/status bits - .VFPCLASSPS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSPD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSSS = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VFPCLASSSD = {written={.OP0}, read={.OP1}, reads_mem=true}, // class predicate written to an opmask register - .VALIGNQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VALIGND = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VDBPSADBW = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPTERNLOGD = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPTERNLOGQ = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .VPMULTISHIFTQB = {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - .KADDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KADDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDNQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KANDND = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KMOVW = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVB = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVQ = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KMOVD = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // opmask <-> GPR/mem/opmask - .KNOTW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KNOTD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KORTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KORTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KSHIFTLW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTLD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KSHIFTRD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KTESTW = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTB = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTQ = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KTESTD = {read={.OP0, .OP1}, flags_wr={.ZF, .CF, .PF, .SF, .OF, .AF}}, // sets ZF/CF from mask test - .KUNPCKBW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KUNPCKWD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KUNPCKDQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXNORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORW = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORB = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORQ = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation - .KXORD = {written={.OP0}, read={.OP1, .OP2}}, // opmask register operation + // 8.14 FMA Encodings + .VFMADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADD231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUB231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMADD231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB132SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB213SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFNMSUB231SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMADDSUB231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD132PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD213PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD231PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD132PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD213PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFMSUBADD231PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPH2PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VCVTPS2PH = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + }, - // ---- 8.16 x87 FPU Encodings ---- - .FADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FADDP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FIADD = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FISUB = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSUBRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FISUBR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FMULP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FIMUL = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FIDIV = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDIVRP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FIDIVR = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSQRT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FABS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FCHS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPREM = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPREM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FRNDINT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FSCALE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FXTRACT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FXAM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FILD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FBLD = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // push onto x87 stack - .FST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FIST = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FISTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FISTTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FBSTP = {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, // store (FSTP/FISTP/FBSTP pop the stack) - .FXCH = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FCMOVB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS - .FCMOVE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS - .FCMOVNB = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, // conditional x87 move; reads EFLAGS - .FCMOVNE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVNBE = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, // conditional x87 move; reads EFLAGS - .FCMOVNU = {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, // conditional x87 move; reads EFLAGS - .FCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FICOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FICOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOMI = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOMIP = {implicit_rd={.FPU_ST}, flags_wr={.ZF, .PF, .CF}, flags_undef={.OF, .SF, .AF}}, // compares ST(0):ST(i) into EFLAGS - .FUCOM = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FUCOMP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FUCOMPP = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FTST = {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // sets x87 condition codes C0-C3 (status word), not EFLAGS - .FLDZ = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLD1 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDPI = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDL2T = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDL2E = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDLG2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FLDLN2 = {implicit_wr={.FPU_ST, .FPU_SW}}, // push onto x87 stack - .FSIN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FSINCOS = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FPTAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FPATAN = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .F2XM1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FYL2X = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FYL2XP1 = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FNINIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FINCSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FDECSTP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FFREE = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FFREEP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FNOP = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FWAIT = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // x87 arithmetic: updates ST(0) and status word C1 - .FCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FNCLEX = {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, // x87 arithmetic: updates ST(0) and status word C1 - .FSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSTCW = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FLDCW = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSTENV = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FLDENV = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FNSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory - .FNSTSW = {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, // AX form writes AX; m2byte form writes memory - .FXSAVE = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FXSAVE64 = {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, // stores x87 (and SSE) state to memory - .FXRSTOR = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory - .FXRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // loads x87 (and SSE) state from memory + // 8.15 AVX-512 Encodings + .VMOVDQA32 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQA64 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU8 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU16 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU32 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VMOVDQU64 = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPBLENDMB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPBLENDMQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDMPS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VBLENDMPD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCMPUQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTMQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMB = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMW = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMD = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPTESTNMQ = { // result written to an opmask register (k1), not EFLAGS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPCOMPRESSD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCOMPRESSQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCOMPRESSPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VCOMPRESSPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPEXPANDD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPEXPANDQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXPANDPS = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VEXPANDPD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCONFLICTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPCONFLICTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPLZCNTD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPLZCNTQ = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPERMI2B = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2W = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2D = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2Q = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2PS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMI2PD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2B = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2W = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2D = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2Q = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2PS = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMT2PD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPERMW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPMOVB2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVW2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVD2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVQ2M = { // sign bits -> opmask register + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2B = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2W = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2D = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVM2Q = { + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .VPMOVQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSQD = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSDB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSDW = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPMOVUSWB = { + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VPROLD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPROLVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORVD = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPRORVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSCATTERDD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERDQ = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERQD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSCATTERQQ = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERDPS = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERDPD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERQPS = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VSCATTERQPD = { // opmask k1 is consumed and cleared per element + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + }, + .VPSRAVQ = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRAVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSLLVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VPSRLVW = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .VRANGEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRANGESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VREDUCESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALEPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALEPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALESS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRNDSCALESD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRSQRT14SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14PS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14PD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14SS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VRCP14SD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VSCALEFSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETEXPSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VGETMANTSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMPS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMPD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMSS = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFIXUPIMMSD = { // may set MXCSR exception/status bits + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + }, + .VFPCLASSPS = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSPD = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSSS = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VFPCLASSSD = { // class predicate written to an opmask register + {written={.OP0}, read={.OP1}, reads_mem=true}, + }, + .VALIGNQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VALIGND = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VDBPSADBW = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPTERNLOGD = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPTERNLOGQ = { + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + }, + .VPMULTISHIFTQB = { + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + }, + .KADDW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KADDD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDNQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KANDND = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KMOVW = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVB = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVQ = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KMOVD = { // opmask <-> GPR/mem/opmask + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + }, + .KNOTW = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTB = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTQ = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KNOTD = { // opmask register operation + {written={.OP0}, read={.OP1}}, + }, + .KORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KORTESTW = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTB = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTQ = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KORTESTD = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KSHIFTLW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTLD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KSHIFTRD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KTESTW = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTB = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTQ = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KTESTD = { // sets ZF/CF from mask test + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .KUNPCKBW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KUNPCKWD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KUNPCKDQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXNORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORW = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORB = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORQ = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, + .KXORD = { // opmask register operation + {written={.OP0}, read={.OP1, .OP2}}, + }, - // ---- 8.17 System Instruction Encodings ---- - .LGDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SGDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LIDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SIDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LLDT = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SLDT = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LTR = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .STR = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .LMSW = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged load - .SMSW = {written={.OP0}, writes_mem=true}, // stores descriptor/register to r/m (privileged for some) - .CLTS = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .ARPL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // legacy; adjusts RPL, sets ZF - .LAR = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure - .LSL = {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 on success; OP0 undefined on failure - .VERR = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable - .VERW = {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, // ZF=1 if segment is readable/writable - .INVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .WBINVD = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVLPG = {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVPCID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .RSM = {side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .RDMSR = {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, // privileged; EDX:EAX <- MSR[ECX] - .WRMSR = {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, // privileged; MSR[ECX] <- EDX:EAX - .VMCALL = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .VMLAUNCH = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMRESUME = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMXOFF = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .VMXON = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMCLEAR = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMPTRLD = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMPTRST = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .VMREAD = {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF - .VMWRITE = {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX status in ZF/CF - .VMFUNC = {side_effects={.PRIVILEGED}}, // privileged; no GPR/EFLAGS clobber modeled - .INVEPT = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF - .INVVPID = {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // VMX/INVx status reported in ZF/CF + // 8.16 x87 FPU Encodings + .FADD = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FADDP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIADD = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSUB = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSUBP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FISUB = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSUBR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSUBRP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FISUBR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FMUL = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FMULP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIMUL = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FDIV = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDIVP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIDIV = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FDIVR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDIVRP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FIDIVR = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FSQRT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FABS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCHS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPREM = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPREM1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FRNDINT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSCALE = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FXTRACT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FXAM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FLD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FILD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FBLD = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FST = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FSTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FIST = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FISTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FISTTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FBSTP = { // store (FSTP/FISTP/FBSTP pop the stack) + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXCH = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCMOVB = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + }, + .FCMOVE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + }, + .FCMOVBE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + }, + .FCMOVU = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + }, + .FCMOVNB = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + }, + .FCMOVNE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + }, + .FCMOVNBE = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + }, + .FCMOVNU = { // conditional x87 move; reads EFLAGS + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + }, + .FCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FICOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FICOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + }, + .FCOMI = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FCOMIP = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOMI = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOMIP = { // compares ST(0):ST(i) into EFLAGS + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + }, + .FUCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FUCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FUCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FTST = { // sets x87 condition codes C0-C3 (status word), not EFLAGS + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FLDZ = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLD1 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDPI = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDL2T = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDL2E = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDLG2 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FLDLN2 = { // push onto x87 stack + {implicit_wr={.FPU_ST, .FPU_SW}}, + }, + .FSIN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCOS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSINCOS = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPTAN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FPATAN = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .F2XM1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FYL2X = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FYL2XP1 = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FINIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNINIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FINCSTP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FDECSTP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FFREE = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FFREEP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNOP = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FWAIT = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FCLEX = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FNCLEX = { // x87 arithmetic: updates ST(0) and status word C1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + }, + .FSTCW = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSTCW = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FLDCW = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSTENV = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSTENV = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FLDENV = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FNSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FRSTOR = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FSTSW = { // AX form writes AX; m2byte form writes memory + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + }, + .FNSTSW = { // AX form writes AX; m2byte form writes memory + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + }, + .FXSAVE = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXSAVE64 = { // stores x87 (and SSE) state to memory + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + }, + .FXRSTOR = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, + .FXRSTOR64 = { // loads x87 (and SSE) state from memory + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + }, - // ---- 8.18 Security and Memory Protection Encodings ---- - .ENCLS = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .ENCLU = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .ENCLV = {side_effects={.PRIVILEGED}}, // SGX enclave leaf; behaviour selected by EAX - .RDPKRU = {implicit_wr={.RAX}, implicit_rd={.RCX}}, // EAX <- PKRU (EDX cleared); reads ECX - .WRPKRU = {implicit_rd={.RAX, .RCX, .RDX}}, // PKRU <- EAX; ECX/EDX must be 0 - .INCSSPD = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP - .INCSSPQ = {read={.OP0}, writes_mem=true, side_effects={.CET}}, // advances SSP - .RDSSPD = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 - .RDSSPQ = {written={.OP0}, side_effects={.CET}}, // reads shadow-stack pointer into OP0 - .SAVEPREVSSP = {side_effects={.CET}}, // CET shadow-stack management - .RSTORSSP = {side_effects={.CET}}, // CET shadow-stack management - .WRSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRUSSD = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .WRUSSQ = {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, // writes to shadow stack - .SETSSBSY = {side_effects={.CET}}, // CET shadow-stack management - .CLRSSBSY = {side_effects={.CET}}, // CET shadow-stack management - .ENDBR64 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like - .ENDBR32 = {side_effects={.HINT, .CET}}, // CET landing pad; NOP-like + // 8.17 System Instruction Encodings + .LGDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SGDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + }, + .LIDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SIDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + }, + .LLDT = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SLDT = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .LTR = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .STR = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .LMSW = { // privileged load + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .SMSW = { // stores descriptor/register to r/m (privileged for some) + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + }, + .CLTS = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .ARPL = { // legacy; adjusts RPL, sets ZF + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .LAR = { // ZF=1 on success; OP0 undefined on failure + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + }, + .LSL = { // ZF=1 on success; OP0 undefined on failure + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + }, + .VERR = { // ZF=1 if segment is readable/writable + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + }, + .VERW = { // ZF=1 if segment is readable/writable + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + }, + .INVD = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .WBINVD = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .INVLPG = { // privileged; no GPR/EFLAGS clobber modeled + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .INVPCID = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .RSM = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .RDMSR = { // privileged; EDX:EAX <- MSR[ECX] + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, + }, + .WRMSR = { // privileged; MSR[ECX] <- EDX:EAX + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, + }, + .VMCALL = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .VMLAUNCH = { // VMX/INVx status reported in ZF/CF + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMRESUME = { // VMX/INVx status reported in ZF/CF + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMXOFF = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .VMXON = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMCLEAR = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMPTRLD = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMPTRST = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMREAD = { // VMX status in ZF/CF + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMWRITE = { // VMX status in ZF/CF + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .VMFUNC = { // privileged; no GPR/EFLAGS clobber modeled + {side_effects={.PRIVILEGED}}, + }, + .INVEPT = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .INVVPID = { // VMX/INVx status reported in ZF/CF + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, - // ---- 8.19 XSAVE/XRSTOR State Management Encodings ---- - .XSAVE = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVE64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XRSTOR = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX - .XRSTOR64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true}, // restores state components selected by EDX:EAX - .XSAVEOPT = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEOPT64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEC = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVEC64 = {implicit_rd={.RAX, .RDX}, writes_mem=true}, // saves state components selected by EDX:EAX - .XSAVES = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX - .XSAVES64 = {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, // saves state components selected by EDX:EAX - .XRSTORS = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX - .XRSTORS64 = {implicit_wr={.FPU_ST, .FPU_SW, .MXCSR}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // restores state components selected by EDX:EAX + // 8.18 Security and Memory Protection Encodings + .ENCLS = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .ENCLU = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .ENCLV = { // SGX enclave leaf; behaviour selected by EAX + {side_effects={.PRIVILEGED}}, + }, + .RDPKRU = { // EAX <- PKRU (EDX cleared); reads ECX + {implicit_wr={.RAX}, implicit_rd={.RCX}}, + }, + .WRPKRU = { // PKRU <- EAX; ECX/EDX must be 0 + {implicit_rd={.RAX, .RCX, .RDX}}, + }, + .INCSSPD = { // advances SSP + {read={.OP0}, side_effects={.CET}}, + }, + .INCSSPQ = { // advances SSP + {read={.OP0}, side_effects={.CET}}, + }, + .RDSSPD = { // reads shadow-stack pointer into OP0 + {written={.OP0}, side_effects={.CET}}, + }, + .RDSSPQ = { // reads shadow-stack pointer into OP0 + {written={.OP0}, side_effects={.CET}}, + }, + .SAVEPREVSSP = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .RSTORSSP = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .WRSSD = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRSSQ = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRUSSD = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .WRUSSQ = { // writes to shadow stack + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + }, + .SETSSBSY = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .CLRSSBSY = { // CET shadow-stack management + {side_effects={.CET}}, + }, + .ENDBR64 = { // CET landing pad; NOP-like + {side_effects={.HINT, .CET}}, + }, + .ENDBR32 = { // CET landing pad; NOP-like + {side_effects={.HINT, .CET}}, + }, - // ---- 8.20 Cache and Prefetch Encodings ---- - .PREFETCHT0 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHT1 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHT2 = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHNTA = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .PREFETCHW = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber - .CLFLUSHOPT = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber - .CLWB = {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, // cache hint/maintenance; no register or flag clobber - .CLDEMOTE = {read={.OP0}, reads_mem=true, side_effects={.HINT}}, // cache hint/maintenance; no register or flag clobber + // 8.19 XSAVE/XRSTOR State Management Encodings + .XSAVE = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVE64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XRSTOR = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + }, + .XRSTOR64 = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + }, + .XSAVEOPT = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEOPT64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEC = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVEC64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + }, + .XSAVES = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .XSAVES64 = { // saves state components selected by EDX:EAX + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + }, + .XRSTORS = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, + .XRSTORS64 = { // restores state components selected by EDX:EAX + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + }, - // ---- 8.21 Atomic and Byte Swap Encodings ---- - .BSWAP = {written={.OP0}, read={.OP0}}, - .CMPXCHG = {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // ZF set on match; on mismatch RAX <- dest - .CMPXCHG8B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - .CMPXCHG16B = {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX, .RBX, .RCX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - .XADD = {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // 8.20 Cache and Prefetch Encodings + .PREFETCHT0 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHT1 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHT2 = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHNTA = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .PREFETCHW = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, + .CLFLUSHOPT = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .CLWB = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + }, + .CLDEMOTE = { // cache hint/maintenance; no register or flag clobber + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + }, - // ---- 8.22 Miscellaneous Encodings ---- - .BOUND = {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, // #BR if out of bounds - .ENTER = {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, // builds stack frame - .LEAVE = {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, - .XLAT = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] - .XLATB = {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // AL <- [rBX + AL] - .MOVBE = {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, // byte-swapping load/store - .RDRAND = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - .RDSEED = {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + // 8.21 Atomic and Byte Swap Encodings + .BSWAP = { + {written={.OP0}, read={.OP0}}, + {written={.OP0}, read={.OP0}}, + }, + .CMPXCHG = { // ZF set on match; on mismatch RAX <- dest + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + .CMPXCHG8B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .CMPXCHG16B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + }, + .XADD = { + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + }, + + // 8.22 Miscellaneous Encodings + .BOUND = { // #BR if out of bounds + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + }, + .ENTER = { // builds stack frame + {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, + }, + .LEAVE = { + {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, + }, + .XLAT = { // AL <- [rBX + AL] + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + }, + .XLATB = { // AL <- [rBX + AL] + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + }, + .MOVBE = { // byte-swapping load/store + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + }, + .RDRAND = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, + .RDSEED = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + }, } diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index 9793858ee..9fc398807 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -12,7 +12,7 @@ package rexcode_x86_tablegen // Operand_Type list satisfies the user's Instruction operands. @(rodata) -ENCODING_TABLE: [Mnemonic][]Encoding = { +ENCODING_TABLE := [Mnemonic][]Encoding{ .INVALID = {}, // ------------------------------------------------------------------------- @@ -1000,6 +1000,8 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { }, .MOVSD = { {.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, + {.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, + {.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, }, .MOVSQ = { {.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true, force_rex_w=true}}, @@ -1014,7 +1016,8 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, opsize_16=true}}, }, .CMPSD = { - {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, }, .CMPSQ = { {.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, force_rex_w=true}}, @@ -1265,10 +1268,6 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3}}, {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3}}, }, - .MOVSD_SSE = { - {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, - }, .MOVDQA = { {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66}}, {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66}}, @@ -1462,9 +1461,6 @@ ENCODING_TABLE: [Mnemonic][]Encoding = { .CMPSS = { {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3}}, }, - .CMPSD_SSE = { - {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, - }, .COMISS = { {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F}}, }, diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index fbd0af645..10225cd7d 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -34,6 +34,7 @@ import lib "../" // `Mnemonic`/`Encoding` unqualified — its body stays byte-for-byte unedited. Encoding :: lib.Encoding Mnemonic :: lib.Mnemonic +Clobber :: lib.Clobber PREFIX_66 :: lib.PREFIX_66 PREFIX_F3 :: lib.PREFIX_F3 PREFIX_F2 :: lib.PREFIX_F2 @@ -47,22 +48,22 @@ BLOBS := [?]Blob{ {"ENCODE_FORMS", "x86.encode_forms.bin", "Encoding"}, {"ENCODE_RUNS", "x86.encode_runs.bin", "Encode_Run"}, {"ENCODE_RECIPES", "x86.encode_recipes.bin", "Form_Recipe"}, - {"MODRM_TABLE", "x86.modrm.bin", "ModRM_Info"}, - {"SIB_TABLE", "x86.sib.bin", "SIB_Info"}, - {"LEGACY_DECODE_ENTRIES", "x86.legacy.bin", "Decode_Entry"}, - {"VEX_DECODE_ENTRIES", "x86.vex.bin", "VEX_Decode_Entry"}, - {"EVEX_DECODE_ENTRIES", "x86.evex.bin", "VEX_Decode_Entry"}, - {"DECODE_INDEX_LEGACY", "x86.idx_legacy.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F", "x86.idx_0f.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F38", "x86.idx_0f38.bin", "Decode_Index"}, - {"DECODE_INDEX_ESC_0F3A", "x86.idx_0f3a.bin", "Decode_Index"}, - {"VEX_INDEX_0F", "x86.vex_idx_0f.bin", "Decode_Index"}, - {"VEX_INDEX_0F38", "x86.vex_idx_0f38.bin", "Decode_Index"}, - {"VEX_INDEX_0F3A", "x86.vex_idx_0f3a.bin", "Decode_Index"}, - {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, - {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin","Decode_Index"}, - {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin","Decode_Index"}, - {"CLOBBER_TABLE", "x86.clobber_table.bin","Clobber"}, + {"MODRM_TABLE", "x86.modrm.bin", "ModRM_Info"}, + {"SIB_TABLE", "x86.sib.bin", "SIB_Info"}, + {"LEGACY_DECODE_ENTRIES", "x86.legacy.bin", "Decode_Entry"}, + {"VEX_DECODE_ENTRIES", "x86.vex.bin", "VEX_Decode_Entry"}, + {"EVEX_DECODE_ENTRIES", "x86.evex.bin", "VEX_Decode_Entry"}, + {"DECODE_INDEX_LEGACY", "x86.idx_legacy.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F", "x86.idx_0f.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F38", "x86.idx_0f38.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F3A", "x86.idx_0f3a.bin", "Decode_Index"}, + {"VEX_INDEX_0F", "x86.vex_idx_0f.bin", "Decode_Index"}, + {"VEX_INDEX_0F38", "x86.vex_idx_0f38.bin", "Decode_Index"}, + {"VEX_INDEX_0F3A", "x86.vex_idx_0f3a.bin", "Decode_Index"}, + {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, + {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin", "Decode_Index"}, + {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin", "Decode_Index"}, + {"CLOBBER_FORMS", "x86.clobber_forms.bin", "Clobber"}, } DIR_GEN :: #directory + "/generated/" @@ -110,6 +111,17 @@ emit_encode_tables :: proc() { } strings.write_string(&sb, "}\n\n") + strings.write_string(&sb, "@(rodata)\n") + fmt.sbprintfln(&sb, "CLOBBER_FORMS := [%d]lib.Clobber{{", total_forms()) + for m in Mnemonic { + forms := CLOBBER_TABLE[m] + assert(len(forms) == len(ENCODING_TABLE[m])) + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { write_clobber(&sb, f, max_name) } + } + strings.write_string(&sb, "}\n\n") + // Run index, one entry per mnemonic (dense, enum-ordinal order). run_name := 0 for m in Mnemonic { run_name = max(run_name, len(reflect.enum_string(m))) } @@ -153,6 +165,59 @@ write_encoding :: proc(sb: ^strings.Builder, e: lib.Encoding, max_name: int) { strings.write_string(sb, "},\n") } +write_clobber :: proc(sb: ^strings.Builder, c: lib.Clobber, max_name: int) { + i := 0 + sep :: proc(sb: ^strings.Builder, i: ^int) { + if i^ > 0 { strings.write_string(sb, ", ") } + i^ += 1 + } + write_flags :: proc(sb: ^strings.Builder, name: string, flags: $T) { + strings.write_string(sb, name) + strings.write_string(sb, "={") + i := 0 + for flag in flags { + if i > 0 { strings.write_string(sb, ", ") } + fmt.sbprintf(sb, ".%s", flag) + i += 1 + } + strings.write_string(sb, "}") + } + + strings.write_string(sb, "\t{") + if c.written != nil { + sep(sb, &i); write_flags(sb, "written", c.written) + } + if c.read != nil { + sep(sb, &i); write_flags(sb, "read", c.read) + } + if c.implicit_wr != nil { + sep(sb, &i); write_flags(sb, "implicit_wr", c.implicit_wr) + } + if c.implicit_rd != nil { + sep(sb, &i); write_flags(sb, "implicit_rd", c.implicit_rd) + } + if c.flags_wr != nil { + sep(sb, &i); write_flags(sb, "flags_wr", c.flags_wr) + } + if c.flags_undef != nil { + sep(sb, &i); write_flags(sb, "flags_undef", c.flags_undef) + } + if c.flags_rd != nil { + sep(sb, &i); write_flags(sb, "flags_rd", c.flags_rd) + } + if c.writes_mem { + sep(sb, &i); strings.write_string(sb, "writes_mem=true") + } + if c.reads_mem { + sep(sb, &i); strings.write_string(sb, "reads_mem=true") + } + if c.side_effects != nil { + sep(sb, &i); write_flags(sb, "side_effects", c.side_effects) + } + + strings.write_string(sb, "},\n") +} + // ----------------------------------------------------------------------------- // Decode side // ----------------------------------------------------------------------------- @@ -548,6 +613,14 @@ encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { return ENCODE_FORMS[r.start:][:r.count] } +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +clobber_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Clobber { + r := ENCODE_RUNS[u16(m)] + return CLOBBER_FORMS[r.start:][:r.count] +} + // Flat [prefix][opcode] lookup into a logical [4][256] index table. @(private, require_results) didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 6821eb95a..5d4939325 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -146,57 +146,57 @@ SIB_TABLE := [256]lib.SIB_Info{ @(rodata) LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -206,21 +206,21 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -231,18 +231,18 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -255,25 +255,25 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -282,16 +282,16 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -303,9 +303,9 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -313,17 +313,17 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -336,8 +336,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -373,24 +373,24 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, + {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, @@ -409,35 +409,35 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, - {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, + {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, @@ -451,11 +451,11 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -483,8 +483,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -599,8 +599,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFC, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFD, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFE, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -650,8 +650,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0xC0, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD0, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD8, .FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -760,8 +760,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -775,11 +775,11 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0xC0, .ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -795,12 +795,12 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0xEE, .RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xEF, .WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xF9, .RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -823,8 +823,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -931,8 +931,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x52, 0xFF, .RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x53, 0xFF, .RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1133,8 +1133,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 1, 0x2B, 0xFF, .MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2E, 0xFF, .UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x2F, 0xFF, .COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x51, 0xFF, .SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x54, 0xFF, .ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x55, 0xFF, .ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1285,8 +1285,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x10, 0xFF, .MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x11, 0xFF, .MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x10, 0xFF, .MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x11, 0xFF, .MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1305,7 +1305,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0xC2, 0xFF, .CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, + {._0F, 3, 0xC2, 0xFF, .CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, {._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0xF0, 0xFF, .LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1380,8 +1380,8 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index fa4a01692..74eda1187 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -800,6 +800,8 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {opsize_16=true, rep_ok=true}}, // .MOVSD {.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, + {.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVSQ {.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {force_rex_w=true, rep_ok=true}}, // .CMPS @@ -810,6 +812,7 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {opsize_16=true, rep_ok=true}}, // .CMPSD {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, + {.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .CMPSQ {.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {force_rex_w=true, rep_ok=true}}, // .SCAS @@ -973,9 +976,6 @@ ENCODE_FORMS := [2395]lib.Encoding{ // .MOVSS {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2, explicit_count=2}}, {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2, explicit_count=2}}, - // .MOVSD_SSE - {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, explicit_count=2}}, - {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVDQA {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, explicit_count=2}}, {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, explicit_count=2}}, @@ -1110,8 +1110,6 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .CMPSS {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=2, explicit_count=3}}, - // .CMPSD_SSE - {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .COMISS {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, explicit_count=2}}, // .COMISD @@ -3599,6 +3597,3596 @@ ENCODE_FORMS := [2395]lib.Encoding{ {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, } +@(rodata) +CLOBBER_FORMS := [2395]lib.Clobber{ + // .MOV + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVABS + {written={.OP0}, read={.OP1}}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + // .MOVZX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSXD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XCHG + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + // .PUSH + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + // .POP + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + // .LEA + {written={.OP0}}, + {written={.OP0}}, + {written={.OP0}}, + // .ADD + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .ADC + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .SUB + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .SBB + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .MUL + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + // .IMUL + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + // .DIV + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .IDIV + {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .INC + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .DEC + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .NEG + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .CMP + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .AND + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .OR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .XOR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .NOT + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + // .TEST + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + // .SHL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .SHR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .SAR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + // .ROL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + // .ROR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + // .RCL + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .RCR + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + // .SHLD + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + // .SHRD + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + // .BT + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .BTS + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BTR + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BTC + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BSF + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + // .BSR + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + // .POPCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .LZCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .TZCNT + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .JMP + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + // .JA + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JAE + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JB + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JBE + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JC + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JE + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JZ + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JG + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JGE + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JL + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JLE + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNA + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JNAE + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNB + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNBE + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, + // .JNC + {flags_rd={.CF}, side_effects={.CONTROL}}, + {flags_rd={.CF}, side_effects={.CONTROL}}, + // .JNE + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JNZ + {flags_rd={.ZF}, side_effects={.CONTROL}}, + {flags_rd={.ZF}, side_effects={.CONTROL}}, + // .JNG + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNGE + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JNL + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, + // .JNLE + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, + // .JNO + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + // .JNP + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JNS + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + // .JO + {flags_rd={.OF}, side_effects={.CONTROL}}, + {flags_rd={.OF}, side_effects={.CONTROL}}, + // .JP + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JPE + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JPO + {flags_rd={.PF}, side_effects={.CONTROL}}, + {flags_rd={.PF}, side_effects={.CONTROL}}, + // .JS + {flags_rd={.SF}, side_effects={.CONTROL}}, + {flags_rd={.SF}, side_effects={.CONTROL}}, + // .JCXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .JECXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .JRCXZ + {implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .LOOP + {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, + // .LOOPE + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + // .LOOPNE + {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, + // .CALL + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + // .RET + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, + // .IRET + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .IRETD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .IRETQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, + // .INT + {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .INT3 + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .INTO + {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSCALL + {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSRET + {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + // .SYSENTER + {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, + // .SYSEXIT + {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, + // .SETA + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETAE + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETB + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETBE + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETC + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETE + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETG + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETGE + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETL + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETLE + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNA + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETNAE + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNB + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNBE + {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + // .SETNC + {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + // .SETNE + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETNG + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNGE + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETNL + {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + // .SETNLE + {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + // .SETNO + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + // .SETNP + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETNS + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + // .SETNZ + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .SETO + {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + // .SETP + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETPE + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETPO + {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + // .SETS + {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + // .SETZ + {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + // .CMOVA + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVAE + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVB + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVBE + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVC + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVE + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVG + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVGE + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVL + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVLE + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNA + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVNAE + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNB + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNBE + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + // .CMOVNC + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + // .CMOVNE + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVNG + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNGE + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVNL + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + // .CMOVNLE + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + // .CMOVNO + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + // .CMOVNP + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVNS + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + // .CMOVNZ + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .CMOVO + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + // .CMOVP + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVPE + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVPO + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + // .CMOVS + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + // .CMOVZ + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + // .MOVS + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSB + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSW + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .MOVSD + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVSQ + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .CMPS + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSB + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSW + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .CMPSD + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPSQ + {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCAS + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASB + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASW + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASD + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .SCASQ + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, + // .LODS + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSB + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSW + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSD + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .LODSQ + {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, + // .STOS + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSB + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSW + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSD + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .STOSQ + {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, + // .CLC + {flags_wr={.CF}}, + // .STC + {flags_wr={.CF}}, + // .CMC + {flags_wr={.CF}, flags_rd={.CF}}, + // .CLD + {flags_wr={.DF}}, + // .STD + {flags_wr={.DF}}, + // .CLI + {flags_wr={.IF}}, + // .STI + {flags_wr={.IF}}, + // .LAHF + {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}, + // .SAHF + {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}, + // .PUSHF + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .PUSHFD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .PUSHFQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, + // .POPF + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .POPFD + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .POPFQ + {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, + // .NOP + {}, + {}, + {}, + {}, + // .HLT + {side_effects={.HALT, .PRIVILEGED}}, + // .WAIT + {implicit_rd={.FPU_SW}}, + // .LOCK + {side_effects={.FENCE}}, + // .UD0 + {side_effects={.TRAP}}, + // .UD1 + {side_effects={.TRAP}}, + // .UD2 + {side_effects={.TRAP}}, + // .CPUID + {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, + // .RDTSC + {implicit_wr={.RAX, .RDX}}, + // .RDTSCP + {implicit_wr={.RAX, .RCX, .RDX}}, + // .RDPMC + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + // .XGETBV + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, + // .XSETBV + {implicit_rd={.RAX, .RCX, .RDX}}, + // .CBW + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CWDE + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CDQE + {implicit_wr={.RAX}, implicit_rd={.RAX}}, + // .CWD + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .CDQ + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .CQO + {implicit_wr={.RDX}, implicit_rd={.RAX}}, + // .ANDN + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BEXTR + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + // .BLSI + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BLSMSK + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BLSR + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .BZHI + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + // .PDEP + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PEXT + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .RORX + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SARX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHLX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHRX + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .MULX + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + // .ADCX + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + // .ADOX + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + // .MOVAPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVUPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVAPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVUPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVSS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVDQA + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVDQU + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVHPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVHPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVLHPS + {written={.OP0}, read={.OP1}}, + // .MOVHLPS + {written={.OP0}, read={.OP1}}, + // .MOVMSKPS + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVMSKPD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .MOVNTPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTDQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .MOVNTDQA + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ADDPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SUBSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MULSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DIVSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .SQRTSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RCPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RCPSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .RSQRTSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MAXSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINSS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MINSD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ANDPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDNPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ANDNPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ORPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .ORPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XORPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .XORPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CMPPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CMPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .COMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .COMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .UCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .UCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .SHUFPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHUFPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .UNPCKLPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKHPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKLPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .UNPCKHPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CVTPS2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPD2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSS2SD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSD2SS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTDQ2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTDQ2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSI2SS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTSI2SD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .CVTTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .PADDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDUSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PADDUSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBUSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSUBUSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULUDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMADDWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PAND + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PANDN + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .POR + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PXOR + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSLLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSLLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSLLQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRLQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRAW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PSRAD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .PCMPEQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPEQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPEQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCMPGTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKSSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKSSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PACKUSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKLQDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PUNPCKHQDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSHUFD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PSHUFW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PEXTRW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .PINSRW + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PMOVMSKB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .PAVGB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PAVGW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSADBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MASKMOVDQU + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + // .LFENCE + {side_effects={.FENCE, .SERIALIZING}}, + // .SFENCE + {side_effects={.FENCE}}, + // .MFENCE + {side_effects={.FENCE}}, + // .PAUSE + {side_effects={.HINT}}, + // .CLFLUSH + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .ADDSUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ADDSUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HADDPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HADDPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HSUBPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .HSUBPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .MOVDDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSLDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .MOVSHDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .LDDQU + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSHUFB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHADDSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PHSUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMADDUBSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULHRSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGNB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGNW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PSIGND + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PABSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PALIGNR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .BLENDVPS + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .BLENDVPD + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .PBLENDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PBLENDVB + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .DPPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .DPPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .EXTRACTPS + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .INSERTPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .MPSADBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PACKUSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PEXTRB + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PEXTRD + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PEXTRQ + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .PHMINPOSUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PINSRB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PINSRD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PINSRQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .PMAXSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMAXUD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMINUD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVSXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXBQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMOVZXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PMULLD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PTEST + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .ROUNDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .ROUNDSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .PCMPEQQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .CRC32 + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + // .PCMPESTRI + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPESTRM + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPISTRI + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPISTRM + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .PCMPGTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .PCLMULQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .AESDEC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESDECLAST + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESENC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESENCLAST + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESIMC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .AESKEYGENASSIST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHA1MSG1 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1MSG2 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1NEXTE + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA1RNDS4 + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .SHA256MSG1 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA256MSG2 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .SHA256RNDS2 + {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + // .VADDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSUBSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMULSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDIVSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSQRTSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRTPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRTSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMAXSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VMINSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VANDPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDNPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VANDNPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VORPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VORPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VXORPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VXORPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VCMPPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCMPSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VUCOMISS + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VUCOMISD + {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + // .VSHUFPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VSHUFPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VUNPCKLPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKHPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKLPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VUNPCKHPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDVPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VBLENDVPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VDPPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VDPPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VROUNDSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VEXTRACTPS + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VINSERTPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMOVAPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVUPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVAPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVUPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVSS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVSD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVDQA + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVDQU + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVHPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVHPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVLHPS + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVHLPS + {written={.OP0}, read={.OP1, .OP2}}, + // .VMOVMSKPS + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVMSKPD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VMOVNTPS + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTPD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTDQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .VMOVNTDQA + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VADDSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VADDSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHADDPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHADDPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHSUBPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VHSUBPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VLDDQU + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVSLDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVSHDUP + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCMPESTRI + {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPESTRM + {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPISTRI + {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPCMPISTRM + {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + // .VPBROADCASTB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTD + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBROADCASTQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCVTPS2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPD2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSS2SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSD2SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTDQ2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTDQ2PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSI2SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTSI2SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTPS2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTPD2DQ + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTSS2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTTSD2SI + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VPADDB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPADDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSUBQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULUDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMADDWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPAND + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPANDN + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPOR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPXOR + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSLLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSLLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRAW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPSRAD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}}, + // .VPCMPEQB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPEQQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPGTQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKSSWB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKSSDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKUSWB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPACKUSDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKLQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHWD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPUNPCKHQDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFHW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSHUFLW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPEXTRB + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRW + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRD + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPEXTRQ + {written={.OP0}, read={.OP1}, writes_mem=true}, + // .VPINSRB + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPINSRQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPMOVMSKB + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPTEST + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VPSHUFB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHADDSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPHSUBSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMADDUBSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULHRSW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGNB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGNW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSIGND + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPABSB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPABSW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPABSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPALIGNR + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPBLENDW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPBLENDVB + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMPSADBW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPHMINPOSUW + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMAXSB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXSD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMAXUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINSB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINSD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMINUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMOVSXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXBQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXBQ + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXWD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXWQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVZXDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMULDQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMULLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VMASKMOVDQU + {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + // .VPCLMULQDQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VAESDEC + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESDECLAST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESENC + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESENCLAST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VAESIMC + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VAESKEYGENASSIST + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBROADCASTSS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VBROADCASTSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + // .VBROADCASTF128 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXTRACTF128 + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VINSERTF128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERM2F128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VMASKMOVPS + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VMASKMOVPD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VTESTPS + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VTESTPD + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + // .VZEROALL + {implicit_wr={.VECTOR}}, + // .VZEROUPPER + {implicit_wr={.VECTOR}}, + // .VBROADCASTI128 + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXTRACTI128 + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VINSERTI128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERM2I128 + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPERMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPSLLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRAVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMASKMOVD + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VPMASKMOVQ + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + // .VGATHERDPS + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERDPD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERQPS + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VGATHERQPD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERDD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERDQ + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERQD + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VPGATHERQQ + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + // .VFMADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADD231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUB231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMADD231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB132SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB213SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFNMSUB231SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMADDSUB231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD132PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD213PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD231PS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD132PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD213PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFMSUBADD231PD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPH2PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VCVTPS2PH + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + // .VMOVDQA32 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQA64 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU8 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU16 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU32 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VMOVDQU64 + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPBLENDMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPBLENDMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDMPS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VBLENDMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCMPUQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPTESTNMQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPCOMPRESSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCOMPRESSQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCOMPRESSPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VCOMPRESSPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPEXPANDD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPEXPANDQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXPANDPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VEXPANDPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCONFLICTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPCONFLICTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPLZCNTD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPLZCNTQ + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPERMI2B + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2W + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2D + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2Q + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2PS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMI2PD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2B + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2W + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2D + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2Q + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2PS + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMT2PD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPERMW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPMOVB2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVW2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVD2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVQ2M + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2B + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2W + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2D + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVM2Q + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .VPMOVQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSQD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSDB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSDW + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPMOVUSWB + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VPROLD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPROLVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORVD + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPRORVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSCATTERDD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERDQ + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERQD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSCATTERQQ + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERDPS + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERDPD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERQPS + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VSCATTERQPD + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + {read={.OP0, .OP1}, writes_mem=true}, + // .VPSRAVQ + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRAVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSLLVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VPSRLVW + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .VRANGEPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGEPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRANGESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCEPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCEPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VREDUCESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALEPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALEPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALESS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRNDSCALESD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRSQRT14SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14PS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14PD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14SS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VRCP14SD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VSCALEFSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPPS + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPPD + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPSS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETEXPSD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTPS + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTPD + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VGETMANTSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMPS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMPD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMSS + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFIXUPIMMSD + {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + // .VFPCLASSPS + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSPD + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSSS + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VFPCLASSSD + {written={.OP0}, read={.OP1}, reads_mem=true}, + // .VALIGNQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VALIGND + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VDBPSADBW + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPTERNLOGD + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPTERNLOGQ + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + // .VPMULTISHIFTQB + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + // .KADDW + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDB + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KADDD + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDW + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDB + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDD + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNW + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNB + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDNQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KANDND + {written={.OP0}, read={.OP1, .OP2}}, + // .KMOVW + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVB + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVQ + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KMOVD + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}}, + {written={.OP0}, read={.OP1}}, + // .KNOTW + {written={.OP0}, read={.OP1}}, + // .KNOTB + {written={.OP0}, read={.OP1}}, + // .KNOTQ + {written={.OP0}, read={.OP1}}, + // .KNOTD + {written={.OP0}, read={.OP1}}, + // .KORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KORD + {written={.OP0}, read={.OP1, .OP2}}, + // .KORTESTW + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTB + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTQ + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KORTESTD + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KSHIFTLW + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLB + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTLD + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRW + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRB + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KSHIFTRD + {written={.OP0}, read={.OP1, .OP2}}, + // .KTESTW + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTB + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTQ + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KTESTD + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .KUNPCKBW + {written={.OP0}, read={.OP1, .OP2}}, + // .KUNPCKWD + {written={.OP0}, read={.OP1, .OP2}}, + // .KUNPCKDQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXNORD + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORW + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORB + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORQ + {written={.OP0}, read={.OP1, .OP2}}, + // .KXORD + {written={.OP0}, read={.OP1, .OP2}}, + // .FADD + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FADDP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIADD + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSUB + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSUBP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FISUB + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSUBR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSUBRP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FISUBR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FMUL + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FMULP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIMUL + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FDIV + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDIVP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIDIV + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FDIVR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDIVRP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FIDIVR + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FSQRT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FABS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCHS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPREM + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPREM1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FRNDINT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSCALE + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FXTRACT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FXAM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FLD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FILD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FBLD + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FST + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FSTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FIST + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FISTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FISTTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FBSTP + {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXCH + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCMOVB + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + // .FCMOVE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + // .FCMOVBE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + // .FCMOVU + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + // .FCMOVNB + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, + // .FCMOVNE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, + // .FCMOVNBE + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, + // .FCMOVNU + {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, + // .FCOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOMPP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FICOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FICOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, + // .FCOMI + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FCOMIP + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOMI + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOMIP + {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, + // .FUCOM + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FUCOMP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FUCOMPP + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FTST + {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, + // .FLDZ + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLD1 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDPI + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDL2T + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDL2E + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDLG2 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FLDLN2 + {implicit_wr={.FPU_ST, .FPU_SW}}, + // .FSIN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCOS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSINCOS + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPTAN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FPATAN + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .F2XM1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FYL2X + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FYL2XP1 + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FINIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNINIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FINCSTP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FDECSTP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FFREE + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FFREEP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNOP + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FWAIT + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FCLEX + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FNCLEX + {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, + // .FSTCW + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSTCW + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FLDCW + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSTENV + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSTENV + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FLDENV + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FNSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FRSTOR + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FSTSW + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + // .FNSTSW + {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, + {implicit_wr={.RAX, .FPU_SW}}, + // .FXSAVE + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXSAVE64 + {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, + // .FXRSTOR + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .FXRSTOR64 + {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, + // .LGDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SGDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + // .LIDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SIDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}, writes_mem=true}, + // .LLDT + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SLDT + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .LTR + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .STR + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .LMSW + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .SMSW + {written={.OP0}, writes_mem=true}, + {written={.OP0}}, + {written={.OP0}}, + // .CLTS + {side_effects={.PRIVILEGED}}, + // .ARPL + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .LAR + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + // .LSL + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + // .VERR + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + // .VERW + {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + // .INVD + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .WBINVD + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .INVLPG + {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .INVPCID + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .RSM + {side_effects={.SERIALIZING, .PRIVILEGED}}, + // .RDMSR + {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, + // .WRMSR + {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, + // .VMCALL + {side_effects={.PRIVILEGED}}, + // .VMLAUNCH + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMRESUME + {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMXOFF + {side_effects={.PRIVILEGED}}, + // .VMXON + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMCLEAR + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMPTRLD + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMPTRST + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMREAD + {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMWRITE + {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .VMFUNC + {side_effects={.PRIVILEGED}}, + // .INVEPT + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .INVVPID + {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .ENCLS + {side_effects={.PRIVILEGED}}, + // .ENCLU + {side_effects={.PRIVILEGED}}, + // .ENCLV + {side_effects={.PRIVILEGED}}, + // .RDPKRU + {implicit_wr={.RAX}, implicit_rd={.RCX}}, + // .WRPKRU + {implicit_rd={.RAX, .RCX, .RDX}}, + // .INCSSPD + {read={.OP0}, side_effects={.CET}}, + // .INCSSPQ + {read={.OP0}, side_effects={.CET}}, + // .RDSSPD + {written={.OP0}, side_effects={.CET}}, + // .RDSSPQ + {written={.OP0}, side_effects={.CET}}, + // .SAVEPREVSSP + {side_effects={.CET}}, + // .RSTORSSP + {side_effects={.CET}}, + // .WRSSD + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRSSQ + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRUSSD + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .WRUSSQ + {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + // .SETSSBSY + {side_effects={.CET}}, + // .CLRSSBSY + {side_effects={.CET}}, + // .ENDBR64 + {side_effects={.HINT, .CET}}, + // .ENDBR32 + {side_effects={.HINT, .CET}}, + // .XSAVE + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVE64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XRSTOR + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + // .XRSTOR64 + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, + // .XSAVEOPT + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEOPT64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEC + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVEC64 + {implicit_rd={.RAX, .RDX}, writes_mem=true}, + // .XSAVES + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .XSAVES64 + {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, + // .XRSTORS + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .XRSTORS64 + {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, + // .PREFETCHT0 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHT1 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHT2 + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHNTA + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .PREFETCHW + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .CLFLUSHOPT + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .CLWB + {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + // .CLDEMOTE + {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + // .BSWAP + {written={.OP0}, read={.OP0}}, + {written={.OP0}, read={.OP0}}, + // .CMPXCHG + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .CMPXCHG8B + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .CMPXCHG16B + {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + // .XADD + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + // .BOUND + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + // .ENTER + {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, + // .LEAVE + {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, + // .XLAT + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + // .XLATB + {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, + // .MOVBE + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + // .RDRAND + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + // .RDSEED + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, +} + @(rodata) ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .INVALID = { 0, 0}, @@ -3758,143 +7346,141 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .MOVS = { 630, 1}, .MOVSB = { 631, 1}, .MOVSW = { 632, 1}, - .MOVSD = { 633, 1}, - .MOVSQ = { 634, 1}, - .CMPS = { 635, 1}, - .CMPSB = { 636, 1}, - .CMPSW = { 637, 1}, - .CMPSD = { 638, 1}, - .CMPSQ = { 639, 1}, - .SCAS = { 640, 1}, - .SCASB = { 641, 1}, - .SCASW = { 642, 1}, - .SCASD = { 643, 1}, - .SCASQ = { 644, 1}, - .LODS = { 645, 1}, - .LODSB = { 646, 1}, - .LODSW = { 647, 1}, - .LODSD = { 648, 1}, - .LODSQ = { 649, 1}, - .STOS = { 650, 1}, - .STOSB = { 651, 1}, - .STOSW = { 652, 1}, - .STOSD = { 653, 1}, - .STOSQ = { 654, 1}, - .CLC = { 655, 1}, - .STC = { 656, 1}, - .CMC = { 657, 1}, - .CLD = { 658, 1}, - .STD = { 659, 1}, - .CLI = { 660, 1}, - .STI = { 661, 1}, - .LAHF = { 662, 1}, - .SAHF = { 663, 1}, - .PUSHF = { 664, 1}, - .PUSHFD = { 665, 1}, - .PUSHFQ = { 666, 1}, - .POPF = { 667, 1}, - .POPFD = { 668, 1}, - .POPFQ = { 669, 1}, - .NOP = { 670, 4}, - .HLT = { 674, 1}, - .WAIT = { 675, 1}, - .LOCK = { 676, 1}, - .UD0 = { 677, 1}, - .UD1 = { 678, 1}, - .UD2 = { 679, 1}, - .CPUID = { 680, 1}, - .RDTSC = { 681, 1}, - .RDTSCP = { 682, 1}, - .RDPMC = { 683, 1}, - .XGETBV = { 684, 1}, - .XSETBV = { 685, 1}, - .CBW = { 686, 1}, - .CWDE = { 687, 1}, - .CDQE = { 688, 1}, - .CWD = { 689, 1}, - .CDQ = { 690, 1}, - .CQO = { 691, 1}, - .ANDN = { 692, 2}, - .BEXTR = { 694, 2}, - .BLSI = { 696, 2}, - .BLSMSK = { 698, 2}, - .BLSR = { 700, 2}, - .BZHI = { 702, 2}, - .PDEP = { 704, 2}, - .PEXT = { 706, 2}, - .RORX = { 708, 2}, - .SARX = { 710, 2}, - .SHLX = { 712, 2}, - .SHRX = { 714, 2}, - .MULX = { 716, 2}, - .ADCX = { 718, 2}, - .ADOX = { 720, 2}, - .MOVAPS = { 722, 2}, - .MOVUPS = { 724, 2}, - .MOVAPD = { 726, 2}, - .MOVUPD = { 728, 2}, - .MOVSS = { 730, 2}, - .MOVSD_SSE = { 732, 2}, - .MOVDQA = { 734, 2}, - .MOVDQU = { 736, 2}, - .MOVQ = { 738, 6}, - .MOVD = { 744, 4}, - .MOVLPS = { 748, 2}, - .MOVHPS = { 750, 2}, - .MOVLPD = { 752, 2}, - .MOVHPD = { 754, 2}, - .MOVLHPS = { 756, 1}, - .MOVHLPS = { 757, 1}, - .MOVMSKPS = { 758, 2}, - .MOVMSKPD = { 760, 2}, - .MOVNTPS = { 762, 1}, - .MOVNTPD = { 763, 1}, - .MOVNTDQ = { 764, 1}, - .MOVNTDQA = { 765, 1}, - .ADDPS = { 766, 1}, - .ADDPD = { 767, 1}, - .ADDSS = { 768, 1}, - .ADDSD = { 769, 1}, - .SUBPS = { 770, 1}, - .SUBPD = { 771, 1}, - .SUBSS = { 772, 1}, - .SUBSD = { 773, 1}, - .MULPS = { 774, 1}, - .MULPD = { 775, 1}, - .MULSS = { 776, 1}, - .MULSD = { 777, 1}, - .DIVPS = { 778, 1}, - .DIVPD = { 779, 1}, - .DIVSS = { 780, 1}, - .DIVSD = { 781, 1}, - .SQRTPS = { 782, 1}, - .SQRTPD = { 783, 1}, - .SQRTSS = { 784, 1}, - .SQRTSD = { 785, 1}, - .RCPPS = { 786, 1}, - .RCPSS = { 787, 1}, - .RSQRTPS = { 788, 1}, - .RSQRTSS = { 789, 1}, - .MAXPS = { 790, 1}, - .MAXPD = { 791, 1}, - .MAXSS = { 792, 1}, - .MAXSD = { 793, 1}, - .MINPS = { 794, 1}, - .MINPD = { 795, 1}, - .MINSS = { 796, 1}, - .MINSD = { 797, 1}, - .ANDPS = { 798, 1}, - .ANDPD = { 799, 1}, - .ANDNPS = { 800, 1}, - .ANDNPD = { 801, 1}, - .ORPS = { 802, 1}, - .ORPD = { 803, 1}, - .XORPS = { 804, 1}, - .XORPD = { 805, 1}, - .CMPPS = { 806, 1}, - .CMPPD = { 807, 1}, - .CMPSS = { 808, 1}, - .CMPSD_SSE = { 809, 1}, + .MOVSD = { 633, 3}, + .MOVSQ = { 636, 1}, + .CMPS = { 637, 1}, + .CMPSB = { 638, 1}, + .CMPSW = { 639, 1}, + .CMPSD = { 640, 2}, + .CMPSQ = { 642, 1}, + .SCAS = { 643, 1}, + .SCASB = { 644, 1}, + .SCASW = { 645, 1}, + .SCASD = { 646, 1}, + .SCASQ = { 647, 1}, + .LODS = { 648, 1}, + .LODSB = { 649, 1}, + .LODSW = { 650, 1}, + .LODSD = { 651, 1}, + .LODSQ = { 652, 1}, + .STOS = { 653, 1}, + .STOSB = { 654, 1}, + .STOSW = { 655, 1}, + .STOSD = { 656, 1}, + .STOSQ = { 657, 1}, + .CLC = { 658, 1}, + .STC = { 659, 1}, + .CMC = { 660, 1}, + .CLD = { 661, 1}, + .STD = { 662, 1}, + .CLI = { 663, 1}, + .STI = { 664, 1}, + .LAHF = { 665, 1}, + .SAHF = { 666, 1}, + .PUSHF = { 667, 1}, + .PUSHFD = { 668, 1}, + .PUSHFQ = { 669, 1}, + .POPF = { 670, 1}, + .POPFD = { 671, 1}, + .POPFQ = { 672, 1}, + .NOP = { 673, 4}, + .HLT = { 677, 1}, + .WAIT = { 678, 1}, + .LOCK = { 679, 1}, + .UD0 = { 680, 1}, + .UD1 = { 681, 1}, + .UD2 = { 682, 1}, + .CPUID = { 683, 1}, + .RDTSC = { 684, 1}, + .RDTSCP = { 685, 1}, + .RDPMC = { 686, 1}, + .XGETBV = { 687, 1}, + .XSETBV = { 688, 1}, + .CBW = { 689, 1}, + .CWDE = { 690, 1}, + .CDQE = { 691, 1}, + .CWD = { 692, 1}, + .CDQ = { 693, 1}, + .CQO = { 694, 1}, + .ANDN = { 695, 2}, + .BEXTR = { 697, 2}, + .BLSI = { 699, 2}, + .BLSMSK = { 701, 2}, + .BLSR = { 703, 2}, + .BZHI = { 705, 2}, + .PDEP = { 707, 2}, + .PEXT = { 709, 2}, + .RORX = { 711, 2}, + .SARX = { 713, 2}, + .SHLX = { 715, 2}, + .SHRX = { 717, 2}, + .MULX = { 719, 2}, + .ADCX = { 721, 2}, + .ADOX = { 723, 2}, + .MOVAPS = { 725, 2}, + .MOVUPS = { 727, 2}, + .MOVAPD = { 729, 2}, + .MOVUPD = { 731, 2}, + .MOVSS = { 733, 2}, + .MOVDQA = { 735, 2}, + .MOVDQU = { 737, 2}, + .MOVQ = { 739, 6}, + .MOVD = { 745, 4}, + .MOVLPS = { 749, 2}, + .MOVHPS = { 751, 2}, + .MOVLPD = { 753, 2}, + .MOVHPD = { 755, 2}, + .MOVLHPS = { 757, 1}, + .MOVHLPS = { 758, 1}, + .MOVMSKPS = { 759, 2}, + .MOVMSKPD = { 761, 2}, + .MOVNTPS = { 763, 1}, + .MOVNTPD = { 764, 1}, + .MOVNTDQ = { 765, 1}, + .MOVNTDQA = { 766, 1}, + .ADDPS = { 767, 1}, + .ADDPD = { 768, 1}, + .ADDSS = { 769, 1}, + .ADDSD = { 770, 1}, + .SUBPS = { 771, 1}, + .SUBPD = { 772, 1}, + .SUBSS = { 773, 1}, + .SUBSD = { 774, 1}, + .MULPS = { 775, 1}, + .MULPD = { 776, 1}, + .MULSS = { 777, 1}, + .MULSD = { 778, 1}, + .DIVPS = { 779, 1}, + .DIVPD = { 780, 1}, + .DIVSS = { 781, 1}, + .DIVSD = { 782, 1}, + .SQRTPS = { 783, 1}, + .SQRTPD = { 784, 1}, + .SQRTSS = { 785, 1}, + .SQRTSD = { 786, 1}, + .RCPPS = { 787, 1}, + .RCPSS = { 788, 1}, + .RSQRTPS = { 789, 1}, + .RSQRTSS = { 790, 1}, + .MAXPS = { 791, 1}, + .MAXPD = { 792, 1}, + .MAXSS = { 793, 1}, + .MAXSD = { 794, 1}, + .MINPS = { 795, 1}, + .MINPD = { 796, 1}, + .MINSS = { 797, 1}, + .MINSD = { 798, 1}, + .ANDPS = { 799, 1}, + .ANDPD = { 800, 1}, + .ANDNPS = { 801, 1}, + .ANDNPD = { 802, 1}, + .ORPS = { 803, 1}, + .ORPD = { 804, 1}, + .XORPS = { 805, 1}, + .XORPD = { 806, 1}, + .CMPPS = { 807, 1}, + .CMPPD = { 808, 1}, + .CMPSS = { 809, 1}, .COMISS = { 810, 1}, .COMISD = { 811, 1}, .UCOMISS = { 812, 1}, diff --git a/core/rexcode/isa/x86/tablegen/generated/writer.odin b/core/rexcode/isa/x86/tablegen/generated/writer.odin index 85bcd8a48..cae51a210 100644 --- a/core/rexcode/isa/x86/tablegen/generated/writer.odin +++ b/core/rexcode/isa/x86/tablegen/generated/writer.odin @@ -42,5 +42,5 @@ main :: proc() { w(TABLES + "x86.evex_idx_0f.bin", raw(&EVEX_INDEX_0F, size_of(EVEX_INDEX_0F))) w(TABLES + "x86.evex_idx_0f38.bin", raw(&EVEX_INDEX_0F38, size_of(EVEX_INDEX_0F38))) w(TABLES + "x86.evex_idx_0f3a.bin", raw(&EVEX_INDEX_0F3A, size_of(EVEX_INDEX_0F3A))) - w(TABLES + "x86.clobber_table.bin", raw(&tablegen.CLOBBER_TABLE, size_of(tablegen.CLOBBER_TABLE))) + w(TABLES + "x86.clobber_forms.bin", raw(&CLOBBER_FORMS, size_of(CLOBBER_FORMS))) } diff --git a/core/rexcode/isa/x86/tables.odin b/core/rexcode/isa/x86/tables.odin index 13482ddbc..4bd5710a2 100644 --- a/core/rexcode/isa/x86/tables.odin +++ b/core/rexcode/isa/x86/tables.odin @@ -94,7 +94,7 @@ Decode_Index :: struct { @(rodata) EVEX_INDEX_0F := #load("tables/x86.evex_idx_0f.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F38 := #load("tables/x86.evex_idx_0f38.bin", []Decode_Index) @(rodata) EVEX_INDEX_0F3A := #load("tables/x86.evex_idx_0f3a.bin", []Decode_Index) -@(rodata) CLOBBER_TABLE := #load("tables/x86.clobber_table.bin", []Clobber) +@(rodata) CLOBBER_FORMS := #load("tables/x86.clobber_forms.bin", []Clobber) // ----------------------------------------------------------------------------- // Accessors @@ -108,6 +108,14 @@ encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { return ENCODE_FORMS[r.start:][:r.count] } +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +clobber_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Clobber { + r := ENCODE_RUNS[u16(m)] + return CLOBBER_FORMS[r.start:][:r.count] +} + // Flat [prefix][opcode] lookup into a logical [4][256] index table. @(private, require_results) didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { diff --git a/core/rexcode/isa/x86/tables/x86.clobber_table.bin b/core/rexcode/isa/x86/tables/x86.clobber_table.bin deleted file mode 100644 index 338d8d857..000000000 Binary files a/core/rexcode/isa/x86/tables/x86.clobber_table.bin and /dev/null differ diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index 71049b89b..59f12ef4c 100644 Binary files a/core/rexcode/isa/x86/tables/x86.encode_forms.bin and b/core/rexcode/isa/x86/tables/x86.encode_forms.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.encode_recipes.bin b/core/rexcode/isa/x86/tables/x86.encode_recipes.bin index c72162a4f..2bc0e47c0 100644 Binary files a/core/rexcode/isa/x86/tables/x86.encode_recipes.bin and b/core/rexcode/isa/x86/tables/x86.encode_recipes.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.encode_runs.bin b/core/rexcode/isa/x86/tables/x86.encode_runs.bin index 6caeccef7..1120cea50 100644 Binary files a/core/rexcode/isa/x86/tables/x86.encode_runs.bin and b/core/rexcode/isa/x86/tables/x86.encode_runs.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.evex.bin b/core/rexcode/isa/x86/tables/x86.evex.bin index fc5db3218..520bffe41 100644 Binary files a/core/rexcode/isa/x86/tables/x86.evex.bin and b/core/rexcode/isa/x86/tables/x86.evex.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.legacy.bin b/core/rexcode/isa/x86/tables/x86.legacy.bin index fde28b76d..73677b5da 100644 Binary files a/core/rexcode/isa/x86/tables/x86.legacy.bin and b/core/rexcode/isa/x86/tables/x86.legacy.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.vex.bin b/core/rexcode/isa/x86/tables/x86.vex.bin index fca9d0eea..34b01319e 100644 Binary files a/core/rexcode/isa/x86/tables/x86.vex.bin and b/core/rexcode/isa/x86/tables/x86.vex.bin differ