From a4f08f8307966146c76f48ad08803029dad88370 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fl=C4=81vius?= Date: Mon, 15 Jun 2026 07:43:29 -0400 Subject: [PATCH] Load rexcode encode/decode tables from committed binary blobs Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them. --- .gitignore | 7 + core/rexcode/arm32/decoder.odin | 2 + core/rexcode/arm32/decoding_tables.odin | 2656 ---- core/rexcode/arm32/encoder.odin | 4 +- core/rexcode/arm32/encoding_types.odin | 2 + core/rexcode/arm32/immediates.odin | 2 + core/rexcode/arm32/instructions.odin | 2 + core/rexcode/arm32/mnemonics.odin | 2 + core/rexcode/arm32/operands.odin | 2 + core/rexcode/arm32/printer.odin | 2 + core/rexcode/arm32/registers.odin | 2 + core/rexcode/arm32/reloc.odin | 2 + .../arm32/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/arm32/tablegen/gen.odin | 477 + .../tablegen/generated/decode_tables.odin | 2628 ++++ .../tablegen/generated/encode_tables.odin | 2795 +++++ .../arm32/tablegen/generated/writer.odin | 34 + core/rexcode/arm32/tables.odin | 70 + .../arm32/tables/arm32.bucket_list.bin | Bin 0 -> 10282 bytes .../arm32/tables/arm32.encode_forms.bin | Bin 0 -> 32613 bytes .../arm32/tables/arm32.encode_runs.bin | Bin 0 -> 5088 bytes core/rexcode/arm32/tables/arm32.entries.bin | Bin 0 -> 32613 bytes core/rexcode/arm32/tables/arm32.form_idx.bin | Bin 0 -> 3106 bytes core/rexcode/arm32/tables/arm32.idx_a32.bin | Bin 0 -> 1024 bytes core/rexcode/arm32/tables/arm32.idx_t16.bin | Bin 0 -> 256 bytes core/rexcode/arm32/tables/arm32.idx_t32.bin | Bin 0 -> 512 bytes .../arm32/tables/arm32.idx_t32_sub.bin | Bin 0 -> 16384 bytes core/rexcode/arm32/tests/pipeline.odin | 2 + core/rexcode/arm32/tests/smoke.odin | 5 +- core/rexcode/arm32/tests/sweep.odin | 5 +- .../arm32/tools/dump_verify_input.odin | 5 +- .../arm32/tools/gen_decode_tables.odin | 381 - core/rexcode/arm32/tools/llvm_per_line.sh | 2 + .../arm32/tools/verify_against_llvm.odin | 2 + core/rexcode/arm64/bitmask.odin | 2 + core/rexcode/arm64/decoder.odin | 2 + core/rexcode/arm64/decoding_tables.odin | 1248 -- core/rexcode/arm64/encoder.odin | 4 +- core/rexcode/arm64/encoding_types.odin | 2 + core/rexcode/arm64/instructions.odin | 2 + core/rexcode/arm64/mnemonics.odin | 2 + core/rexcode/arm64/operands.odin | 2 + core/rexcode/arm64/printer.odin | 2 + core/rexcode/arm64/registers.odin | 2 + core/rexcode/arm64/reloc.odin | 2 + core/rexcode/arm64/sysregs.odin | 2 + .../arm64/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/arm64/tablegen/gen.odin | 293 + .../tablegen/generated/decode_tables.odin | 1227 ++ .../tablegen/generated/encode_tables.odin | 3107 +++++ .../arm64/tablegen/generated/writer.odin | 29 + core/rexcode/arm64/tables.odin | 62 + .../arm64/tables/arm64.encode_forms.bin | Bin 0 -> 23920 bytes .../arm64/tables/arm64.encode_runs.bin | Bin 0 -> 8960 bytes core/rexcode/arm64/tables/arm64.entries.bin | Bin 0 -> 23960 bytes core/rexcode/arm64/tables/arm64.idx_op0.bin | Bin 0 -> 64 bytes core/rexcode/arm64/tests/pipeline_smoke.odin | 2 + core/rexcode/arm64/tests/smoke.odin | 5 +- .../arm64/tools/dump_verify_input.odin | 5 +- .../arm64/tools/gen_decode_tables.odin | 185 - core/rexcode/arm64/tools/llvm_per_line.sh | 2 + .../arm64/tools/verify_against_llvm.odin | 2 + core/rexcode/build.lua | 434 + core/rexcode/doc.odin | 54 +- core/rexcode/docs/cross_arch_design.md | 507 +- core/rexcode/docs/mips_platforms.md | 2 + core/rexcode/docs/table_migration.md | 184 + core/rexcode/docs/x86_api.md | 85 +- core/rexcode/isa/label_infer.odin | 2 + core/rexcode/isa/labels.odin | 2 + core/rexcode/isa/print.odin | 2 + core/rexcode/isa/status.odin | 2 + core/rexcode/mips/decoder.odin | 4 +- core/rexcode/mips/encoder.odin | 4 +- core/rexcode/mips/encoding_types.odin | 2 + core/rexcode/mips/instructions.odin | 2 + core/rexcode/mips/mnemonics.odin | 2 + core/rexcode/mips/operands.odin | 2 + core/rexcode/mips/printer.odin | 2 + core/rexcode/mips/registers.odin | 2 + core/rexcode/mips/reloc.odin | 2 + .../mips/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/mips/tablegen/gen.odin | 315 + .../generated/decode_tables.odin} | 467 +- .../tablegen/generated/encode_tables.odin | 2608 ++++ .../mips/tablegen/generated/writer.odin | 34 + core/rexcode/mips/tables.odin | 67 + .../rexcode/mips/tables/mips.encode_forms.bin | Bin 0 -> 15660 bytes core/rexcode/mips/tables/mips.encode_runs.bin | Bin 0 -> 8224 bytes core/rexcode/mips/tables/mips.entries.bin | Bin 0 -> 15660 bytes core/rexcode/mips/tables/mips.idx_cop1.bin | Bin 0 -> 128 bytes core/rexcode/mips/tables/mips.idx_primary.bin | Bin 0 -> 256 bytes core/rexcode/mips/tables/mips.idx_regimm.bin | Bin 0 -> 128 bytes core/rexcode/mips/tables/mips.idx_special.bin | Bin 0 -> 256 bytes .../rexcode/mips/tables/mips.idx_special2.bin | Bin 0 -> 256 bytes .../rexcode/mips/tables/mips.idx_special3.bin | Bin 0 -> 256 bytes core/rexcode/mips/tests/decode_smoke.odin | 2 + core/rexcode/mips/tests/encode_smoke.odin | 2 + core/rexcode/mips/tests/print_smoke.odin | 2 + core/rexcode/mips/tests/smoke.odin | 5 +- .../rexcode/mips/tools/dump_verify_input.odin | 7 +- .../rexcode/mips/tools/gen_decode_tables.odin | 246 - core/rexcode/mips/tools/llvm_per_line.sh | 2 + .../mips/tools/verify_against_llvm.odin | 2 + core/rexcode/mos6502/decoder.odin | 2 + core/rexcode/mos6502/decoding_tables.odin | 608 - core/rexcode/mos6502/encoder.odin | 4 +- core/rexcode/mos6502/encoding_types.odin | 2 + core/rexcode/mos6502/instructions.odin | 2 + core/rexcode/mos6502/mnemonics.odin | 2 + core/rexcode/mos6502/operands.odin | 2 + core/rexcode/mos6502/printer.odin | 2 + core/rexcode/mos6502/registers.odin | 2 + core/rexcode/mos6502/reloc.odin | 2 + .../{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/mos6502/tablegen/gen.odin | 306 + .../tablegen/generated/decode_tables.odin | 588 + .../tablegen/generated/encode_tables.odin | 624 + .../mos6502/tablegen/generated/writer.odin | 29 + core/rexcode/mos6502/tables.odin | 64 + .../mos6502/tables/mos6502.encode_forms.bin | Bin 0 -> 4494 bytes .../mos6502/tables/mos6502.encode_runs.bin | Bin 0 -> 1160 bytes .../mos6502/tables/mos6502.entries.bin | Bin 0 -> 3852 bytes .../mos6502/tables/mos6502.idx_opcode.bin | Bin 0 -> 1024 bytes .../rexcode/mos6502/tests/pipeline_smoke.odin | 2 + core/rexcode/mos6502/tests/smoke.odin | 8 +- .../mos6502/tools/dump_verify_input.odin | 5 +- .../mos6502/tools/gen_decode_tables.odin | 181 - .../mos6502/tools/verify_against_xa.sh | 2 + core/rexcode/mos65816/decoder.odin | 2 + core/rexcode/mos65816/encoder.odin | 4 +- core/rexcode/mos65816/encoding_types.odin | 2 + core/rexcode/mos65816/instructions.odin | 2 + core/rexcode/mos65816/mnemonics.odin | 2 + core/rexcode/mos65816/operands.odin | 2 + core/rexcode/mos65816/printer.odin | 2 + core/rexcode/mos65816/registers.odin | 2 + core/rexcode/mos65816/reloc.odin | 2 + .../{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/mos65816/tablegen/gen.odin | 294 + .../generated/decode_tables.odin} | 546 +- .../tablegen/generated/encode_tables.odin | 467 + .../mos65816/tablegen/generated/writer.odin | 29 + core/rexcode/mos65816/tables.odin | 61 + .../mos65816/tables/mos65816.encode_forms.bin | Bin 0 -> 3484 bytes .../mos65816/tables/mos65816.encode_runs.bin | Bin 0 -> 744 bytes .../mos65816/tables/mos65816.entries.bin | Bin 0 -> 2412 bytes .../mos65816/tables/mos65816.idx_opcode.bin | Bin 0 -> 1024 bytes core/rexcode/mos65816/tests/smoke.odin | 2 + .../mos65816/tools/dump_verify_input.odin | 5 +- .../mos65816/tools/gen_decode_tables.odin | 160 - .../mos65816/tools/verify_against_ca65.sh | 2 + core/rexcode/ppc/decoder.odin | 4 +- core/rexcode/ppc/decoding_tables.odin | 4793 -------- core/rexcode/ppc/encoder.odin | 6 +- core/rexcode/ppc/encoding_types.odin | 2 + core/rexcode/ppc/instructions.odin | 2 + core/rexcode/ppc/mnemonics.odin | 2 + core/rexcode/ppc/operands.odin | 2 + core/rexcode/ppc/printer.odin | 2 + core/rexcode/ppc/registers.odin | 2 + core/rexcode/ppc/reloc.odin | 2 + .../ppc/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/ppc/tablegen/gen.odin | 447 + .../ppc/tablegen/generated/decode_tables.odin | 4768 ++++++++ .../ppc/tablegen/generated/encode_tables.odin | 10060 ++++++++++++++++ .../ppc/tablegen/generated/writer.odin | 33 + core/rexcode/ppc/tables.odin | 70 + core/rexcode/ppc/tables/ppc.bucket_list.bin | Bin 0 -> 69934 bytes core/rexcode/ppc/tables/ppc.encode_forms.bin | Bin 0 -> 73194 bytes core/rexcode/ppc/tables/ppc.encode_runs.bin | Bin 0 -> 26624 bytes core/rexcode/ppc/tables/ppc.entries.bin | Bin 0 -> 73194 bytes core/rexcode/ppc/tables/ppc.form_idx.bin | Bin 0 -> 6654 bytes core/rexcode/ppc/tables/ppc.idx_primary.bin | Bin 0 -> 512 bytes core/rexcode/ppc/tables/ppc.idx_sub.bin | Bin 0 -> 131072 bytes core/rexcode/ppc/tables/ppc.prefix_bits.bin | Bin 0 -> 13312 bytes core/rexcode/ppc/tests/branch_reloc.odin | 2 + core/rexcode/ppc/tests/decode_sweep.odin | 7 +- core/rexcode/ppc/tests/full_sweep.odin | 5 +- core/rexcode/ppc/tests/printer.odin | 2 + core/rexcode/ppc/tests/roundtrip.odin | 2 + core/rexcode/ppc/tests/smoke.odin | 5 +- core/rexcode/ppc/tools/dump_verify_input.odin | 7 +- core/rexcode/ppc/tools/gen_decode_tables.odin | 378 - core/rexcode/ppc/tools/llvm_per_line.sh | 2 + .../ppc/tools/verify_against_llvm.odin | 2 + core/rexcode/ppc_vle/decoder.odin | 2 + core/rexcode/ppc_vle/encoder.odin | 4 +- core/rexcode/ppc_vle/encoding_types.odin | 2 + core/rexcode/ppc_vle/instructions.odin | 2 + core/rexcode/ppc_vle/mnemonics.odin | 2 + core/rexcode/ppc_vle/operands.odin | 2 + core/rexcode/ppc_vle/printer.odin | 2 + core/rexcode/ppc_vle/registers.odin | 2 + core/rexcode/ppc_vle/reloc.odin | 2 + .../{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/ppc_vle/tablegen/gen.odin | 379 + .../generated/decode_tables.odin} | 109 +- .../tablegen/generated/encode_tables.odin | 681 ++ .../ppc_vle/tablegen/generated/writer.odin | 32 + core/rexcode/ppc_vle/tables.odin | 67 + .../ppc_vle/tables/ppc_vle.bucket_list.bin | Bin 0 -> 444 bytes .../ppc_vle/tables/ppc_vle.encode_forms.bin | Bin 0 -> 4662 bytes .../ppc_vle/tables/ppc_vle.encode_runs.bin | Bin 0 -> 1784 bytes .../ppc_vle/tables/ppc_vle.entries.bin | Bin 0 -> 4662 bytes .../ppc_vle/tables/ppc_vle.form_idx.bin | Bin 0 -> 444 bytes .../ppc_vle/tables/ppc_vle.idx_long.bin | Bin 0 -> 512 bytes .../ppc_vle/tables/ppc_vle.idx_short.bin | Bin 0 -> 512 bytes core/rexcode/ppc_vle/tests/branch_test.odin | 2 + core/rexcode/ppc_vle/tests/cond_branch.odin | 2 + core/rexcode/ppc_vle/tests/e2e.odin | 2 + core/rexcode/ppc_vle/tests/extension.odin | 2 + core/rexcode/ppc_vle/tests/full_sweep.odin | 6 +- core/rexcode/ppc_vle/tests/operand_test.odin | 2 + core/rexcode/ppc_vle/tests/printer.odin | 2 + core/rexcode/ppc_vle/tests/roundtrip.odin | 2 + core/rexcode/ppc_vle/tests/smoke.odin | 10 +- .../ppc_vle/tools/dump_verify_input.odin | 5 +- .../ppc_vle/tools/gen_decode_tables.odin | 230 - .../ppc_vle/tools/verify_against_vle_as.sh | 2 + core/rexcode/riscv/decoder.odin | 2 + core/rexcode/riscv/decoding_tables.odin | 307 - core/rexcode/riscv/encoder.odin | 4 +- core/rexcode/riscv/encoding_types.odin | 2 + core/rexcode/riscv/instructions.odin | 2 + core/rexcode/riscv/mnemonics.odin | 2 + core/rexcode/riscv/operands.odin | 2 + core/rexcode/riscv/printer.odin | 2 + core/rexcode/riscv/registers.odin | 2 + core/rexcode/riscv/reloc.odin | 2 + .../riscv/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/riscv/tablegen/gen.odin | 348 + .../tablegen/generated/decode_tables.odin | 285 + .../tablegen/generated/encode_tables.odin | 597 + .../riscv/tablegen/generated/writer.odin | 31 + core/rexcode/riscv/tables.odin | 64 + .../riscv/tables/riscv.encode_forms.bin | Bin 0 -> 3880 bytes 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core/rexcode/rsp/tablegen/gen.odin | 312 + .../generated/decode_tables.odin} | 279 +- .../rsp/tablegen/generated/encode_tables.odin | 363 + .../rsp/tablegen/generated/writer.odin | 34 + core/rexcode/rsp/tables.odin | 67 + core/rexcode/rsp/tables/rsp.encode_forms.bin | Bin 0 -> 2320 bytes core/rexcode/rsp/tables/rsp.encode_runs.bin | Bin 0 -> 936 bytes core/rexcode/rsp/tables/rsp.entries.bin | Bin 0 -> 2320 bytes core/rexcode/rsp/tables/rsp.idx_cop2.bin | Bin 0 -> 256 bytes core/rexcode/rsp/tables/rsp.idx_lwc2.bin | Bin 0 -> 128 bytes core/rexcode/rsp/tables/rsp.idx_primary.bin | Bin 0 -> 256 bytes core/rexcode/rsp/tables/rsp.idx_regimm.bin | Bin 0 -> 128 bytes core/rexcode/rsp/tables/rsp.idx_special.bin | Bin 0 -> 256 bytes core/rexcode/rsp/tables/rsp.idx_swc2.bin | Bin 0 -> 128 bytes core/rexcode/rsp/tests/pipeline_smoke.odin | 2 + core/rexcode/rsp/tests/smoke.odin | 5 +- core/rexcode/rsp/tools/armips_lwv_patch.sh | 2 + core/rexcode/rsp/tools/dump_verify_input.odin | 5 +- core/rexcode/rsp/tools/gen_decode_tables.odin | 219 - .../rsp/tools/verify_against_armips.sh | 2 + core/rexcode/x86/decoder.odin | 30 +- core/rexcode/x86/encoder.odin | 4 +- core/rexcode/x86/encoding_types.odin | 2 + core/rexcode/x86/instructions.odin | 2 + core/rexcode/x86/labels.odin | 2 + core/rexcode/x86/mnemonic_builders.odin | 2 + core/rexcode/x86/mnemonics.odin | 2 + core/rexcode/x86/operands.odin | 2 + core/rexcode/x86/printer.odin | 10 +- core/rexcode/x86/registers.odin | 2 + core/rexcode/x86/reloc.odin | 2 + .../x86/{ => tablegen}/encoding_table.odin | 4 +- core/rexcode/x86/tablegen/gen.odin | 530 + .../generated/decode_tables.odin} | 2315 ++-- .../x86/tablegen/generated/encode_tables.odin | 4720 ++++++++ .../x86/tablegen/generated/writer.odin | 42 + core/rexcode/x86/tables.odin | 113 + core/rexcode/x86/tables/x86.encode_forms.bin | Bin 0 -> 37680 bytes core/rexcode/x86/tables/x86.encode_runs.bin | Bin 0 -> 9408 bytes core/rexcode/x86/tables/x86.evex.bin | Bin 0 -> 8360 bytes core/rexcode/x86/tables/x86.evex_idx_0f.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.evex_idx_0f38.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.evex_idx_0f3a.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.idx_0f.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.idx_0f38.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.idx_0f3a.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.idx_legacy.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.legacy.bin | Bin 0 -> 25400 bytes core/rexcode/x86/tables/x86.modrm.bin | Bin 0 -> 1280 bytes core/rexcode/x86/tables/x86.sib.bin | Bin 0 -> 768 bytes core/rexcode/x86/tables/x86.vex.bin | Bin 0 -> 13340 bytes core/rexcode/x86/tables/x86.vex_idx_0f.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.vex_idx_0f38.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tables/x86.vex_idx_0f3a.bin | Bin 0 -> 4096 bytes core/rexcode/x86/tests/test.odin | 4 + core/rexcode/x86/tests32/test_32bit.odin | 2 + core/rexcode/x86/tools/dump_verify_input.odin | 5 +- core/rexcode/x86/tools/gen_decode_tables.odin | 568 - .../x86/tools/gen_mnemonic_builders.odin | 9 +- .../x86/tools/verify_against_llvm.odin | 2 + core/rexcode/x86/tools/verify_tables.odin | 13 +- 319 files changed, 43305 insertions(+), 14840 deletions(-) delete mode 100644 core/rexcode/arm32/decoding_tables.odin rename core/rexcode/arm32/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/arm32/tablegen/gen.odin create mode 100644 core/rexcode/arm32/tablegen/generated/decode_tables.odin create mode 100644 core/rexcode/arm32/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/arm32/tablegen/generated/writer.odin create mode 100644 core/rexcode/arm32/tables.odin create mode 100644 core/rexcode/arm32/tables/arm32.bucket_list.bin create mode 100644 core/rexcode/arm32/tables/arm32.encode_forms.bin create mode 100644 core/rexcode/arm32/tables/arm32.encode_runs.bin create mode 100644 core/rexcode/arm32/tables/arm32.entries.bin create mode 100644 core/rexcode/arm32/tables/arm32.form_idx.bin create mode 100644 core/rexcode/arm32/tables/arm32.idx_a32.bin create mode 100644 core/rexcode/arm32/tables/arm32.idx_t16.bin create mode 100644 core/rexcode/arm32/tables/arm32.idx_t32.bin create mode 100644 core/rexcode/arm32/tables/arm32.idx_t32_sub.bin delete mode 100644 core/rexcode/arm32/tools/gen_decode_tables.odin delete mode 100644 core/rexcode/arm64/decoding_tables.odin rename core/rexcode/arm64/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/arm64/tablegen/gen.odin create mode 100644 core/rexcode/arm64/tablegen/generated/decode_tables.odin create mode 100644 core/rexcode/arm64/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/arm64/tablegen/generated/writer.odin create mode 100644 core/rexcode/arm64/tables.odin create mode 100644 core/rexcode/arm64/tables/arm64.encode_forms.bin create mode 100644 core/rexcode/arm64/tables/arm64.encode_runs.bin create mode 100644 core/rexcode/arm64/tables/arm64.entries.bin create mode 100644 core/rexcode/arm64/tables/arm64.idx_op0.bin delete mode 100644 core/rexcode/arm64/tools/gen_decode_tables.odin create mode 100755 core/rexcode/build.lua create mode 100644 core/rexcode/docs/table_migration.md rename core/rexcode/mips/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/mips/tablegen/gen.odin rename core/rexcode/mips/{decoding_tables.odin => tablegen/generated/decode_tables.odin} (94%) create mode 100644 core/rexcode/mips/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/mips/tablegen/generated/writer.odin create mode 100644 core/rexcode/mips/tables.odin create mode 100644 core/rexcode/mips/tables/mips.encode_forms.bin create mode 100644 core/rexcode/mips/tables/mips.encode_runs.bin create mode 100644 core/rexcode/mips/tables/mips.entries.bin create mode 100644 core/rexcode/mips/tables/mips.idx_cop1.bin create mode 100644 core/rexcode/mips/tables/mips.idx_primary.bin create mode 100644 core/rexcode/mips/tables/mips.idx_regimm.bin create mode 100644 core/rexcode/mips/tables/mips.idx_special.bin create mode 100644 core/rexcode/mips/tables/mips.idx_special2.bin create mode 100644 core/rexcode/mips/tables/mips.idx_special3.bin delete mode 100644 core/rexcode/mips/tools/gen_decode_tables.odin delete mode 100644 core/rexcode/mos6502/decoding_tables.odin rename core/rexcode/mos6502/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/mos6502/tablegen/gen.odin create mode 100644 core/rexcode/mos6502/tablegen/generated/decode_tables.odin create mode 100644 core/rexcode/mos6502/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/mos6502/tablegen/generated/writer.odin create mode 100644 core/rexcode/mos6502/tables.odin create mode 100644 core/rexcode/mos6502/tables/mos6502.encode_forms.bin create mode 100644 core/rexcode/mos6502/tables/mos6502.encode_runs.bin create mode 100644 core/rexcode/mos6502/tables/mos6502.entries.bin create mode 100644 core/rexcode/mos6502/tables/mos6502.idx_opcode.bin delete mode 100644 core/rexcode/mos6502/tools/gen_decode_tables.odin rename core/rexcode/mos65816/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/mos65816/tablegen/gen.odin rename core/rexcode/mos65816/{decoding_tables.odin => tablegen/generated/decode_tables.odin} (76%) create mode 100644 core/rexcode/mos65816/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/mos65816/tablegen/generated/writer.odin create mode 100644 core/rexcode/mos65816/tables.odin create mode 100644 core/rexcode/mos65816/tables/mos65816.encode_forms.bin create mode 100644 core/rexcode/mos65816/tables/mos65816.encode_runs.bin create mode 100644 core/rexcode/mos65816/tables/mos65816.entries.bin create mode 100644 core/rexcode/mos65816/tables/mos65816.idx_opcode.bin delete mode 100644 core/rexcode/mos65816/tools/gen_decode_tables.odin delete mode 100644 core/rexcode/ppc/decoding_tables.odin rename core/rexcode/ppc/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/ppc/tablegen/gen.odin create mode 100644 core/rexcode/ppc/tablegen/generated/decode_tables.odin create mode 100644 core/rexcode/ppc/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/ppc/tablegen/generated/writer.odin create mode 100644 core/rexcode/ppc/tables.odin create mode 100644 core/rexcode/ppc/tables/ppc.bucket_list.bin create mode 100644 core/rexcode/ppc/tables/ppc.encode_forms.bin create mode 100644 core/rexcode/ppc/tables/ppc.encode_runs.bin create mode 100644 core/rexcode/ppc/tables/ppc.entries.bin create mode 100644 core/rexcode/ppc/tables/ppc.form_idx.bin create mode 100644 core/rexcode/ppc/tables/ppc.idx_primary.bin create mode 100644 core/rexcode/ppc/tables/ppc.idx_sub.bin create mode 100644 core/rexcode/ppc/tables/ppc.prefix_bits.bin delete mode 100644 core/rexcode/ppc/tools/gen_decode_tables.odin rename core/rexcode/ppc_vle/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/ppc_vle/tablegen/gen.odin rename core/rexcode/ppc_vle/{decoding_tables.odin => tablegen/generated/decode_tables.odin} (95%) create mode 100644 core/rexcode/ppc_vle/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/ppc_vle/tablegen/generated/writer.odin create mode 100644 core/rexcode/ppc_vle/tables.odin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.bucket_list.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.encode_forms.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.encode_runs.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.entries.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.form_idx.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.idx_long.bin create mode 100644 core/rexcode/ppc_vle/tables/ppc_vle.idx_short.bin delete mode 100644 core/rexcode/ppc_vle/tools/gen_decode_tables.odin delete mode 100644 core/rexcode/riscv/decoding_tables.odin rename core/rexcode/riscv/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/riscv/tablegen/gen.odin create mode 100644 core/rexcode/riscv/tablegen/generated/decode_tables.odin create mode 100644 core/rexcode/riscv/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/riscv/tablegen/generated/writer.odin create mode 100644 core/rexcode/riscv/tables.odin create mode 100644 core/rexcode/riscv/tables/riscv.encode_forms.bin create mode 100644 core/rexcode/riscv/tables/riscv.encode_runs.bin create mode 100644 core/rexcode/riscv/tables/riscv.entries.bin create mode 100644 core/rexcode/riscv/tables/riscv.idx_op_fp.bin create mode 100644 core/rexcode/riscv/tables/riscv.idx_opcode.bin create mode 100644 core/rexcode/riscv/tables/riscv.idx_rvc.bin delete mode 100644 core/rexcode/riscv/tools/gen_decode_tables.odin rename core/rexcode/rsp/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/rsp/tablegen/gen.odin rename core/rexcode/rsp/{decoding_tables.odin => tablegen/generated/decode_tables.odin} (79%) create mode 100644 core/rexcode/rsp/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/rsp/tablegen/generated/writer.odin create mode 100644 core/rexcode/rsp/tables.odin create mode 100644 core/rexcode/rsp/tables/rsp.encode_forms.bin create mode 100644 core/rexcode/rsp/tables/rsp.encode_runs.bin create mode 100644 core/rexcode/rsp/tables/rsp.entries.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_cop2.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_lwc2.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_primary.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_regimm.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_special.bin create mode 100644 core/rexcode/rsp/tables/rsp.idx_swc2.bin delete mode 100644 core/rexcode/rsp/tools/gen_decode_tables.odin rename core/rexcode/x86/{ => tablegen}/encoding_table.odin (99%) create mode 100644 core/rexcode/x86/tablegen/gen.odin rename core/rexcode/x86/{decoding_tables.odin => tablegen/generated/decode_tables.odin} (60%) create mode 100644 core/rexcode/x86/tablegen/generated/encode_tables.odin create mode 100644 core/rexcode/x86/tablegen/generated/writer.odin create mode 100644 core/rexcode/x86/tables.odin create mode 100644 core/rexcode/x86/tables/x86.encode_forms.bin create mode 100644 core/rexcode/x86/tables/x86.encode_runs.bin create mode 100644 core/rexcode/x86/tables/x86.evex.bin create mode 100644 core/rexcode/x86/tables/x86.evex_idx_0f.bin create mode 100644 core/rexcode/x86/tables/x86.evex_idx_0f38.bin create mode 100644 core/rexcode/x86/tables/x86.evex_idx_0f3a.bin create mode 100644 core/rexcode/x86/tables/x86.idx_0f.bin create mode 100644 core/rexcode/x86/tables/x86.idx_0f38.bin create mode 100644 core/rexcode/x86/tables/x86.idx_0f3a.bin create mode 100644 core/rexcode/x86/tables/x86.idx_legacy.bin create mode 100644 core/rexcode/x86/tables/x86.legacy.bin create mode 100644 core/rexcode/x86/tables/x86.modrm.bin create mode 100644 core/rexcode/x86/tables/x86.sib.bin create mode 100644 core/rexcode/x86/tables/x86.vex.bin create mode 100644 core/rexcode/x86/tables/x86.vex_idx_0f.bin create mode 100644 core/rexcode/x86/tables/x86.vex_idx_0f38.bin create mode 100644 core/rexcode/x86/tables/x86.vex_idx_0f3a.bin delete mode 100644 core/rexcode/x86/tools/gen_decode_tables.odin diff --git a/.gitignore b/.gitignore index 00dbcc2a5..8b0964bfa 100644 --- a/.gitignore +++ b/.gitignore @@ -279,6 +279,13 @@ demo.bin libLLVM*.so* *.a +# core:rexcode commits its generated encode/decode tables: each arch's tablegen +# emits human-readable Odin, serialized to tables/*.bin, which the library +# #loads at compile time. The blobs (and the rexcode x86 package, caught by the +# broad x86/ rule above) must be tracked. +!/core/rexcode/x86/ +!core/rexcode/*/tables/*.bin + # WASM *.wasm diff --git a/core/rexcode/arm32/decoder.odin b/core/rexcode/arm32/decoder.odin index 6a5e11f6e..9ee267889 100644 --- a/core/rexcode/arm32/decoder.odin +++ b/core/rexcode/arm32/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 import "../isa" diff --git a/core/rexcode/arm32/decoding_tables.odin b/core/rexcode/arm32/decoding_tables.odin deleted file mode 100644 index aa9308f10..000000000 --- a/core/rexcode/arm32/decoding_tables.odin +++ /dev/null @@ -1,2656 +0,0 @@ -package rexcode_arm32 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd arm32 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - mode: Mode, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 21) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -DECODE_T32_SUB_BUCKETS :: 32 - -@(rodata) -DECODE_ENTRIES := [1553]Decode_Entry{ - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}}, - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}}, - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.UMAAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}}, - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}}, - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}}, - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}}, - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}}, - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}}, - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}}, - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}}, - {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}}, - {.HLT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}}, - {.SWP, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}}, - {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}}, - {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}}, - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLABB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLABT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLATB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLATT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}}, - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {}}, - {.TST, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}}, - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}}, - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}}, - {.BXJ, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}}, - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RM_A32, .NONE, .NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}}, - {.SMULWB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.SMULWT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {}}, - {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}}, - {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}}, - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLAWB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLAWT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}}, - {.TEQ, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}}, - {.HVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {}}, - {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}}, - {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}}, - {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}}, - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLALBB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLALBT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLALTB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}}, - {.SMLALTT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}}, - {.CMP, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}}, - {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}}, - {.SMC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}}, - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}}, - {.SMULBB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.SMULBT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.SMULTB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.SMULTT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}}, - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}}, - {.CMN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}}, - {.STL, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}}, - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STLEX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}}, - {.LDA, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}}, - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDAEX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.RRX, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}}, - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}}, - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}}, - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}}, - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}}, - {.STREXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STLEXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}}, - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}}, - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}}, - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}}, - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}}, - {.LDREXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDAEXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.STLB, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}}, - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STLEXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}}, - {.LDAB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}}, - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDAEXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.STLH, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}}, - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STLEXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDAH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}}, - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDAEXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}}, - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}}, - {.VRECPS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}}, - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}}, - {.VRHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {}}, - {.VAND, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {}}, - {.VRECPS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {}}, - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {}}, - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {}}, - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {}}, - {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {}}, - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {}}, - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}}, - {.VRSQRTS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {}}, - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {}}, - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {}}, - {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}}, - {.VRSQRTS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {}}, - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {}}, - {.VORN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {}}, - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}}, - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}}, - {.VSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}}, - {.VRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}}, - {.VQSHL, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}}, - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}}, - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}}, - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}}, - {.VQSHL, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {}}, - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMLAH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}}, - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}}, - {.VQDMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}}, - {.VFMA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}}, - {.VFMS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}}, - {.VQRDMLAH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}}, - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}}, - {.VEXT, {.QPR, .QPR, .QPR, .IMM4}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}}, - {.VEXT, {.DPR, .DPR, .DPR, .IMM4}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}}, - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}}, - {.VACGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {}}, - {.VEOR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {}}, - {.VACGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}}, - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {}}, - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {}}, - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {}}, - {.VBSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {}}, - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {}}, - {.VBSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.TST, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}}, - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}}, - {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}}, - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}}, - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}}, - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}}, - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}}, - {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}}, - {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {}}, - {.VBIT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}}, - {.VACGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}}, - {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {}}, - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {}}, - {.VBIT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {}}, - {.VACGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {}}, - {.MSR, {.PSR_FIELD, .IMM_MOD, .NONE, .NONE}, {.PSR_FIELD_MASK, .A32_IMM_MOD, .NONE, .NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {}}, - {.VBIF, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {}}, - {.VBIF, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}}, - {.TEQ, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}}, - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}}, - {.CMP, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}}, - {.CMN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VQSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}}, - {.VQRSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}}, - {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}}, - {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}}, - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}}, - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}}, - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}}, - {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}}, - {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}}, - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}}, - {.VQRDMLAH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}}, - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}}, - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}}, - {.VFMA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}}, - {.VFMS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}}, - {.VQRDMLAH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}}, - {.VQRDMLSH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}}, - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}}, - {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}}, - {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}}, - {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}}, - {.VCVT_BF16, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}}, - {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}}, - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCNT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV16, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}}, - {.VSWP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}}, - {.VSWP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}}, - {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}}, - {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}}, - {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}}, - {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}}, - {.VCEQ_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCEQ_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCEQ_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCEQ_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCGT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}}, - {.VCLT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}}, - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}}, - {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}}, - {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}}, - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}}, - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}}, - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}}, - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}}, - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}}, - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}}, - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}}, - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}}, - {.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}}, - {.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}}, - {.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}}, - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}}, - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}}, - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}}, - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {}}, - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {}}, - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {}}, - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {}}, - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}}, - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {}}, - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}}, - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}}, - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}}, - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}}, - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}}, - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}}, - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}}, - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}}, - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}}, - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}}, - {.SEL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}}, - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}}, - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}}, - {.PKHBT, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}}, - {.PKHTB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}}, - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}}, - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}}, - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}}, - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}}, - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}}, - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}}, - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}}, - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}}, - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}}, - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}}, - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}}, - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}}, - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}}, - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}}, - {.SMUAD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMUADX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMUSD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMUSDX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMLAD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}}, - {.SMLADX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}}, - {.SMLSD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}}, - {.SMLSDX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}}, - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}}, - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}}, - {.SMLALD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}}, - {.SMLALDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}}, - {.SMLSLD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}}, - {.SMLSLDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}}, - {.SMMUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMMULR, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}}, - {.SMMLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}}, - {.SMMLAR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}}, - {.SMMLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}}, - {.SMMLSR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}}, - {.USAD8, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}}, - {.USADA8, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}}, - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}}, - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD, .BFI_LSB, .BFI_MSB, .NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}}, - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}}, - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}}, - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}}, - {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}}, - {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}}, - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}}, - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}}, - {.BLX, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}}, - {.B, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, - {.BL, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, - {.VDOT_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {}}, - {.VMMLA_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {}}, - {.VDOT_BF16, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {}}, - {.STC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {}}, - {.STC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}}, - {.LDC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {}}, - {.LDC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}}, - {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}}, - {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}}, - {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}}, - {.VSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {}}, - {.VUMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {}}, - {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}}, - {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}}, - {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}}, - {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}}, - {.VFMA_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}}, - {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.MCRR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}}, - {.MCRR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}}, - {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.MRRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}}, - {.MRRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}}, - {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}}, - {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}}, - {.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}}, - {.VUSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}}, - {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}}, - {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}}, - {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}}, - {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}}, - {.VPOP, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPOP, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VPUSH, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VMOV, {.SPR, .GPR, .NONE, .NONE}, {.VN_S, .RT_A32, .NONE, .NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}}, - {.VCMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}}, - {.VCMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}}, - {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}}, - {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}}, - {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}}, - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.MCR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}}, - {.CDP2, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {}}, - {.MCR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}}, - {.CDP, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}}, - {.VMOV, {.GPR, .SPR, .NONE, .NONE}, {.RT_A32, .VN_S, .NONE, .NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}}, - {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}}, - {.VNMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.MRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}}, - {.MRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}}, - {.VSDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}}, - {.VUDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}}, - {.VSDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}}, - {.VUDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}}, - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VSUDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}}, - {.VUSDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}}, - {.VMAXNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}}, - {.VMAXNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}}, - {.VMINNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}}, - {.VMINNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}}, - {.VUSDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}}, - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VDIV, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VFNMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}}, - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}}, - {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VRINTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}}, - {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VSQRT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VMOV, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VMOV, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VRINTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTR, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTZ, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTX, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT_FIXED, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}}, - {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, - {.VMOV, {.SPR, .IMM8, .NONE, .NONE}, {.VD_S, .VFP_IMM8, .NONE, .NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}}, - {.VMOV, {.DPR, .IMM8, .NONE, .NONE}, {.VD_D, .VFP_IMM8, .NONE, .NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}}, - {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}}, - {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}}, - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}}, - {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}}, - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.A32_IMM24, .NONE, .NONE, .NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}}, - {.SG, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}}, - {.TBB, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}}, - {.TBH, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}}, - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}}, - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}}, - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}}, - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}}, - {.LDREXD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true}}, - {.TT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}}, - {.TTT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}}, - {.TTA, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}}, - {.TTAT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}}, - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true}}, - {.STREXD, {.GPR, .GPR, .GPR, .MEM}, {.RD_T32, .RT_T32, .RT2_T32, .RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}}, - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}}, - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}}, - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}}, - {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}}, - {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}}, - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}}, - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}}, - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}}, - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true}}, - {.VSTRH_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRW_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRD_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRB_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}}, - {.VMOV_2GPR_Q, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}}, - {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}}, - {.VCX1, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX1, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX2, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX2, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX3, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX3, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VADDLV, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VADDLVA, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMAXNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VMAXNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VMINNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VMINNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VQMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQMOVUNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQMOVUNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VADDV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VADDVA, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMAXV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMAXAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMINV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMINAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VDDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}}, - {.VIDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}}, - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLADAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLADAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLALDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLALDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}}, - {.VSHLC, {.QPR, .GPR, .IMM5, .NONE}, {.VD_Q, .RM_T32, .A32_IMM_SHIFT, .NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VMOV_Q_R, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}}, - {.VMOV_R_Q, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}}, - {.VADD, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}}, - {.VSUB, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}}, - {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}}, - {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VMLADAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLADAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLALDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLALDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VCMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VBRSR, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VDWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}}, - {.VIWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}}, - {.VSHLLB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VSHLLT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMULLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMULLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLALT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQRDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQRDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSLDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}}, - {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}}, - {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}}, - {.VABAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.CX2, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX2D, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX3, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX3D, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX1, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true}}, - {.CX1D, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true}}, - {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}}, - {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true}}, - {.VCTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true}}, - {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true}}, - {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}}, - {.LETP, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}}, - {.WLS, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true}}, - {.TST, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}}, - {.TEQ, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}}, - {.CMP, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}}, - {.CMN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}}, - {.MVN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}}, - {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {branch=true, thumb32=true}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}}, - {.EOR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.RSB, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.ADC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.SBC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.ORR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.BIC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true}}, - {.B, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}}, - {.B, {.REL20, .COND, .NONE, .NONE}, {.BRANCH_20_T32, .NONE, .NONE, .NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true}}, - {.BL, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true}}, - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}}, - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true}}, - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true}}, - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true}}, - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true}}, - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true}}, - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true}}, - {.PAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}}, - {.PACBTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}}, - {.AUT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}}, - {.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}}, - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true}}, - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true}}, - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true}}, - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true}}, - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RN_T32, .NONE, .NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}}, - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD_T32, .BFI_LSB_T32, .BFI_MSB, .NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}}, - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}}, - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}}, - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}}, - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}}, - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}}, - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true}}, - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true}}, - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}}, - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}}, - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true}}, - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true}}, - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}}, - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}}, - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}}, - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}}, - {.AUTG, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true}}, - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}}, - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}}, - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}}, - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}}, - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}}, - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}}, - {.VLD20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLD21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLD40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLD41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLD42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLD43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VST43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRH_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRW_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRD_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VLDRB_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VCX1A, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX1A, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX2A, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX2A, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX3A, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VCX3A, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}}, - {.VPST, {.MVE_VPT_MASK, .NONE, .NONE, .NONE}, {.MVE_VPT_MASK_FIELD, .NONE, .NONE, .NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}}, - {.VPNOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}}, - {.VRINTA, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VRINTN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VRINTP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VRINTM, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VRINTZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}}, - {.VMOVX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}}, - {.VINS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}}, - {.VMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}}, - {.VQABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VPSEL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true}}, - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true}}, - {.VRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQRSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQRSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}}, - {.VQDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQRDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VQRDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true}}, - {.VPT, {.MVE_VPT_MASK, .COND, .QPR, .QPR}, {.MVE_VPT_MASK_FIELD, .NONE, .VN_Q, .VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSDAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSDAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSDAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VMLSDAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLSLDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLSLDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLSLDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.VRMLSLDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}}, - {.CX2A, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX2DA, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX3A, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX3DA, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}}, - {.CX1A, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true}}, - {.CX1DA, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true}}, - {.LSL, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}}, - {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}}, - {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}}, - {.SUB, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {}}, - {.ADD, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {}}, - {.SUB, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {}}, - {.ADD, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {}}, - {.MOV, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}}, - {.CMP, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {}}, - {.ADD, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {}}, - {.SUB, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {}}, - {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}}, - {.EOR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {}}, - {.ADC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {}}, - {.SBC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {}}, - {.TST, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {}}, - {.CMP, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {}}, - {.CMN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {}}, - {.ORR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {}}, - {.BIC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {}}, - {.MVN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {}}, - {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}}, - {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}}, - {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}}, - {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}}, - {.NEG, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {}}, - {.MUL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {}}, - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true}}, - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true}}, - {.BXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {branch=true}}, - {.BLXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {branch=true}}, - {.ADD, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {}}, - {.CMP, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}}, - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {}}, - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {}}, - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {}}, - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {}}, - {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}}, - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}}, - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {}}, - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}}, - {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}}, - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}}, - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}}, - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {}}, - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}}, - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}}, - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {}}, - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}}, - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {}}, - {.ADR, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {}}, - {.ADD, {.GPR_LOW, .GPR, .IMM8, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {}}, - {.SXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}}, - {.SXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {}}, - {.UXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {}}, - {.UXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {}}, - {.SUB, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {}}, - {.ADD, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {}}, - {.CBZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}}, - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {}}, - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}}, - {.REV, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {}}, - {.REV16, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {}}, - {.REVSH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {}}, - {.CBNZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}}, - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {}}, - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {}}, - {.IT, {.COND, .IMM4, .NONE, .NONE}, {.NONE, .IT_MASK, .NONE, .NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}}, - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {}}, - {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}}, - {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}}, - {.B, {.REL8, .COND, .NONE, .NONE}, {.BRANCH_8_T16, .NONE, .NONE, .NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true}}, - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {}}, - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}}, - {.B, {.REL11, .NONE, .NONE, .NONE}, {.BRANCH_11_T16, .NONE, .NONE, .NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true}}, -} - -@(rodata) -DECODE_FORM_IDX := [1553]u16{ - 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 5, - 4, 0, 2, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, - 5, 4, 0, 2, 2, 2, 2, 1, 1, 2, 2, 2, 5, 4, 0, 2, - 1, 1, 5, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 2, - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, - 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 3, 3, 2, 1, 0, 0, - 0, 3, 3, 3, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 0, 0, 0, 2, 1, 0, - 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 1, 1, 1, 0, - 0, 0, 5, 4, 1, 1, 1, 14, 9, 8, 6, 10, 4, 3, 3, 1, - 4, 4, 3, 3, 1, 3, 7, 3, 3, 9, 3, 3, 1, 4, 1, 1, - 0, 5, 13, 5, 9, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 4, - 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 11, 4, - 4, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 11, 14, 10, 8, 10, 4, - 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 5, 5, 9, 1, 0, - 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, - 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 12, 4, 7, 7, 1, 11, - 5, 0, 8, 3, 3, 3, 0, 10, 3, 3, 0, 3, 0, 3, 0, 24, - 22, 25, 23, 21, 10, 11, 12, 19, 20, 16, 13, 18, 17, 11, 15, 14, - 10, 6, 0, 0, 0, 9, 8, 2, 4, 7, 5, 3, 6, 0, 0, 0, - 0, 0, 1, 1, 1, 5, 0, 0, 0, 4, 0, 1, 1, 1, 1, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2, 2, - 2, 2, 1, 1, 1, 1, 4, 1, 4, 1, 4, 1, 1, 1, 1, 1, - 1, 0, 0, 1, 1, 0, 1, 0, 3, 0, 3, 0, 3, 9, 14, 12, - 6, 7, 7, 9, 9, 7, 7, 1, 3, 9, 7, 7, 1, 7, 7, 7, - 3, 3, 0, 5, 13, 11, 3, 6, 6, 8, 8, 6, 6, 0, 0, 6, - 8, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 10, 4, 7, - 2, 2, 2, 1, 4, 11, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 8, 3, - 3, 3, 9, 1, 5, 9, 1, 0, 7, 5, 1, 1, 1, 8, 0, 2, - 8, 0, 4, 0, 12, 1, 11, 8, 0, 10, 0, 0, 0, 0, 3, 3, - 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1, 2, 2, 2, 0, - 0, 0, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, - 5, 5, 5, 3, 5, 3, 5, 3, 5, 3, 3, 3, 1, 1, 3, 3, - 0, 1, 0, 2, 3, 2, 3, 0, 1, 0, 0, 0, 0, 9, 7, 3, - 6, 5, 8, 2, 4, 7, 3, 9, 4, 5, 8, 6, 2, 0, 1, 0, - 1, 2, 4, 1, 5, 0, 3, 2, 0, 1, 2, 1, 3, 2, 0, 5, - 4, 2, 0, 1, 3, 4, 2, 3, 3, 4, 1, 0, 5, 2, 1, 5, - 3, 0, 4, 2, 0, 1, 0, 1, 0, 1, 2, 3, 0, 4, 3, 2, - 5, 1, 0, 4, 5, 3, 2, 1, 4, 1, 3, 0, 2, 3, 4, 2, - 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 2, 3, 1, 0, 3, 2, - 2, 3, 0, 1, 3, 2, 0, 1, 1, 2, 3, 0, 1, 3, 0, 2, - 3, 0, 1, 2, 3, 2, 3, 0, 3, 0, 3, 1, 2, 0, 3, 0, - 1, 2, 1, 0, 1, 0, 2, 1, 0, 3, 0, 1, 2, 0, 1, 0, - 1, 5, 6, 4, 1, 0, 2, 1, 0, 2, 1, 2, 0, 1, 2, 0, - 2, 2, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0, 0, 1, 2, 1, - 2, 0, 2, 1, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, - 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 3, 3, 0, - 0, 3, 0, 3, 0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, - 0, 1, 0, 0, 7, 9, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, - 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, - 4, 1, 0, 1, 0, 27, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, - 5, 26, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 2, 0, 1, 0, - 1, 2, 2, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 2, 0, - 1, 2, 2, 1, 0, 1, 0, 2, 2, 1, 0, 1, 0, 2, 3, 5, - 3, 2, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, - 1, 0, 0, 1, 1, 0, 0, 1, 2, 1, 0, 2, 4, 3, 5, 6, - 7, 9, 8, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, - 2, 1, 0, 9, 6, 8, 3, 7, 4, 1, 0, 1, 0, 5, 4, 2, - 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, - 0, 0, 1, 1, 2, 2, 1, 7, 6, 6, 7, 4, 4, 4, 4, 4, - 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, - 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 4, 0, 0, 0, 0, 7, 2, 2, 2, 2, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, 4, 6, 0, 0, 4, 4, - 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, - 3, 6, 4, 8, 9, 7, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, - 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, - 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, - 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, - 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, - 0, 1, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, - 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, - 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, - 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, - 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, - 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 5, 5, 1, 1, 1, - 2, -} - -@(rodata) -DECODE_BUCKET_LIST := [5141]u16{ - 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, - 11, 8, 12, 35, 36, 37, 13, 14, 41, 42, 43, 15, 13, 16, 14, 17, - 18, 19, 20, 21, 18, 19, 22, 23, 24, 25, 22, 26, 23, 27, 24, 28, - 29, 30, 31, 28, 32, 33, 29, 30, 34, 35, 36, 37, 38, 39, 40, 34, - 41, 42, 43, 44, 38, 45, 39, 46, 47, 48, 49, 46, 50, 47, 51, 48, - 52, 53, 54, 55, 56, 57, 58, 105, 106, 107, 59, 60, 61, 62, 63, 64, - 113, 114, 115, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, - 78, 79, 80, 53, 81, 82, 83, 84, 85, 86, 87, 88, 89, 138, 139, 140, - 90, 91, 146, 147, 148, 92, 93, 94, 70, 95, 96, 97, 98, 99, 156, 157, - 158, 100, 101, 164, 165, 166, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, - 112, 113, 114, 115, 116, 108, 117, 109, 118, 119, 120, 121, 122, 123, 124, 125, - 126, 127, 128, 129, 130, 131, 132, 133, 129, 134, 130, 135, 136, 137, 138, 139, - 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 141, 142, 151, 152, 153, - 154, 155, 156, 157, 158, 159, 160, 161, 162, 154, 163, 155, 164, 165, 166, 167, - 168, 169, 171, 170, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, - 184, 186, 185, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 212, 211, 213, 214, 215, - 216, 217, 218, 219, 220, 221, 223, 222, 224, 225, 226, 227, 228, 229, 230, 231, - 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 243, 242, 244, 245, 246, 247, - 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 259, 258, 260, 261, 262, 263, - 264, 265, 221, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, - 279, 280, 281, 282, 283, 285, 284, 286, 287, 288, 289, 290, 291, 292, 293, 294, - 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 307, 306, 308, 309, 310, - 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, - 327, 328, 329, 313, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, - 179, 180, 181, 182, 183, 184, 186, 185, 187, 188, 189, 190, 191, 192, 194, 193, - 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, - 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 330, 222, 223, 224, 225, 226, - 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, - 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 259, - 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1192, 1204, 1207, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1254, - 1161, 1162, 1163, 1164, 1174, 1175, 1176, 1187, 1189, 1190, 1191, 1192, 1193, 1202, 1204, 1207, - 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1254, 1174, 1175, 1188, - 1190, 1191, 1192, 1203, 1204, 1207, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, - 1230, 1231, 1250, 1254, 1174, 1175, 1189, 1190, 1191, 1192, 1204, 1207, 1210, 1211, 1214, 1215, - 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1250, 1254, 1174, 1175, 1188, 1190, 1191, 1192, - 1204, 1207, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1250, 1254, - 1161, 1162, 1163, 1164, 1174, 1175, 1176, 1189, 1190, 1191, 1192, 1193, 1202, 1204, 1207, 1210, - 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1250, 1254, 1155, 1156, 1171, - 1172, 1173, 1183, 1184, 1185, 1186, 1196, 1197, 1198, 1199, 1212, 1213, 1220, 1221, 1222, 1223, - 1224, 1225, 1226, 1227, 1244, 1245, 1249, 1252, 1255, 1212, 1213, 1220, 1221, 1222, 1223, 1224, - 1225, 1226, 1227, 1252, 1255, 1171, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, - 1252, 1255, 1181, 1182, 1194, 1195, 1200, 1201, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, - 1226, 1227, 1252, 1255, 1171, 1172, 1173, 1183, 1184, 1185, 1186, 1196, 1197, 1198, 1199, 1212, - 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1244, 1245, 1249, 1251, 1253, 1255, 1212, - 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1251, 1253, 1255, 1157, 1158, 1159, 1160, - 1167, 1168, 1169, 1170, 1171, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1251, - 1253, 1255, 1165, 1166, 1181, 1182, 1194, 1195, 1200, 1201, 1212, 1213, 1220, 1221, 1222, 1223, - 1224, 1225, 1226, 1227, 1251, 1253, 1255, 1177, 1205, 1208, 1232, 1233, 1234, 1235, 1236, 1237, - 1238, 1239, 1240, 1241, 1242, 1243, 1178, 1205, 1208, 1232, 1233, 1234, 1235, 1236, 1237, 1238, - 1239, 1240, 1241, 1242, 1243, 1179, 1206, 1209, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, - 1240, 1241, 1242, 1243, 1180, 1206, 1209, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, - 1241, 1242, 1243, 1177, 1205, 1208, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, - 1242, 1243, 1178, 1205, 1208, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, - 1243, 1179, 1206, 1209, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, - 1180, 1206, 1209, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1246, - 1247, 1248, 1246, 1247, 1248, 1246, 1247, 1248, 1246, 1247, 1248, 1246, 1247, 1248, 1246, 1247, - 1248, 1246, 1247, 1248, 1246, 1247, 1248, 1256, 1258, 1259, 1260, 1270, 1272, 1271, 1280, 1279, - 1281, 1258, 1259, 1261, 1263, 1270, 1272, 1271, 1280, 1279, 1281, 1258, 1259, 1270, 1278, 1280, - 1279, 1281, 1258, 1259, 1270, 1278, 1279, 1280, 1281, 1257, 1259, 1262, 1268, 1267, 1270, 1277, - 1279, 1280, 1281, 1259, 1268, 1267, 1270, 1277, 1279, 1280, 1281, 1259, 1269, 1270, 1280, 1279, - 1281, 1259, 1269, 1270, 1280, 1279, 1281, 1273, 1280, 1279, 1281, 1264, 1273, 1280, 1279, 1281, - 1280, 1279, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1280, - 1279, 1281, 1259, 1270, 1279, 1280, 1281, 1259, 1266, 1270, 1280, 1279, 1281, 1259, 1270, 1280, - 1279, 1281, 1259, 1270, 1279, 1280, 1281, 1259, 1270, 1275, 1279, 1280, 1281, 1259, 1270, 1275, - 1280, 1279, 1281, 1259, 1270, 1276, 1280, 1279, 1281, 1259, 1270, 1276, 1279, 1280, 1281, 1280, - 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1265, 1280, 1279, 1281, 1274, 1279, 1280, 1281, - 1274, 1279, 1280, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, 1281, - 1279, 1280, 1281, 1280, 1279, 1281, 1310, 1279, 1280, 1281, 1279, 1280, 1281, 1279, 1280, 1281, - 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1311, - 1280, 1279, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1308, 1280, 1279, 1281, - 1279, 1280, 1281, 1302, 1308, 1280, 1279, 1281, 1280, 1279, 1281, 1306, 1280, 1279, 1281, 1280, - 1279, 1281, 1304, 1305, 1279, 1280, 1281, 1280, 1279, 1281, 1301, 1309, 1280, 1279, 1281, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1288, 1289, 1290, 1291, 1293, 1294, 1295, 1296, 1303, - 1309, 1279, 1280, 1281, 1287, 1292, 1298, 1299, 1300, 1279, 1280, 1281, 1307, 1280, 1279, 1281, - 1279, 1280, 1281, 1297, 1280, 1279, 1281, 1280, 1279, 1281, 1272, 1271, 1280, 1279, 1281, 1263, - 1272, 1271, 1280, 1279, 1281, 1278, 1279, 1280, 1281, 1278, 1280, 1279, 1281, 1267, 1268, 1277, - 1280, 1279, 1281, 1267, 1268, 1277, 1280, 1279, 1281, 1269, 1280, 1279, 1281, 1269, 1280, 1279, - 1281, 1273, 1280, 1279, 1281, 1264, 1273, 1280, 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, - 1280, 1279, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1266, - 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1275, 1280, 1279, 1281, 1275, 1280, 1279, - 1281, 1276, 1280, 1279, 1281, 1276, 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, - 1280, 1281, 1265, 1280, 1279, 1281, 1274, 1279, 1280, 1281, 1274, 1279, 1280, 1281, 1279, 1280, - 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1279, 1280, 1281, - 1310, 1280, 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, - 1280, 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1311, 1280, 1279, 1281, 1280, 1279, 1281, - 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1280, - 1279, 1281, 1280, 1279, 1281, 1280, 1279, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, - 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1279, 1280, 1281, 1280, 1279, 1281, 1279, 1280, 1281, - 1280, 1279, 1281, 1312, 1279, 1280, 1281, 1316, 1315, 1318, 1317, 1322, 1314, 1313, 1324, 1328, - 1321, 1327, 1330, 1329, 1326, 1324, 1325, 1319, 1320, 1323, 1331, 1332, 1335, 1388, 1394, 1338, - 1388, 1397, 1334, 1389, 1393, 1337, 1389, 1396, 1333, 1390, 1392, 1336, 1390, 1395, 1391, 1391, - 1344, 1345, 1346, 1347, 1348, 1354, 1360, 1366, 1372, 1378, 1340, 1341, 1342, 1343, 1349, 1355, - 1361, 1367, 1373, 1379, 1350, 1356, 1362, 1368, 1374, 1380, 1339, 1352, 1358, 1364, 1370, 1376, - 1382, 1353, 1359, 1365, 1371, 1377, 1383, 1351, 1357, 1363, 1369, 1375, 1381, 1384, 1398, 1399, - 1387, 1402, 1385, 1400, 1386, 1403, 1401, 1424, 1425, 1421, 1423, 1420, 1422, 1424, 1425, 1421, - 1423, 1420, 1422, 1410, 1411, 1412, 1413, 1414, 1415, 1424, 1404, 1405, 1406, 1407, 1408, 1409, - 1416, 1417, 1418, 1419, 1425, 1421, 1423, 1420, 1422, 1410, 1411, 1412, 1413, 1414, 1415, 1424, - 1404, 1405, 1406, 1407, 1408, 1409, 1425, 1421, 1423, 1420, 1422, 1416, 1417, 1418, 1419, 1442, - 1174, 1175, 1190, 1191, 1192, 1448, 1203, 1204, 1453, 1454, 1455, 1456, 1207, 1458, 1210, 1211, - 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1471, 1174, 1175, 1190, 1191, 1192, - 1448, 1204, 1453, 1454, 1455, 1456, 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, - 1228, 1229, 1230, 1231, 1471, 1174, 1175, 1190, 1191, 1192, 1448, 1204, 1453, 1454, 1455, 1456, - 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1471, 1427, - 1436, 1437, 1174, 1175, 1176, 1190, 1191, 1192, 1193, 1448, 1202, 1204, 1453, 1454, 1455, 1456, - 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1471, 1442, - 1174, 1175, 1190, 1191, 1192, 1448, 1203, 1204, 1453, 1454, 1455, 1456, 1207, 1458, 1210, 1211, - 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, 1467, 1471, 1174, 1175, 1190, 1191, - 1192, 1448, 1204, 1453, 1454, 1455, 1456, 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, - 1219, 1228, 1229, 1230, 1231, 1467, 1471, 1174, 1175, 1190, 1191, 1192, 1448, 1204, 1453, 1454, - 1455, 1456, 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, 1231, - 1467, 1471, 1426, 1436, 1437, 1174, 1175, 1176, 1190, 1191, 1192, 1193, 1448, 1202, 1204, 1453, - 1454, 1455, 1456, 1207, 1458, 1210, 1211, 1214, 1215, 1216, 1217, 1218, 1219, 1228, 1229, 1230, - 1231, 1467, 1471, 1155, 1156, 1183, 1184, 1185, 1186, 1196, 1197, 1198, 1199, 1449, 1450, 1451, - 1452, 1458, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1463, 1464, 1465, 1466, - 1249, 1469, 1472, 1449, 1450, 1451, 1452, 1458, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, - 1226, 1227, 1469, 1472, 1449, 1450, 1451, 1452, 1458, 1212, 1213, 1220, 1221, 1222, 1223, 1224, - 1225, 1226, 1227, 1469, 1472, 1434, 1435, 1181, 1182, 1194, 1195, 1200, 1201, 1449, 1450, 1451, - 1452, 1458, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1459, 1460, 1461, 1462, - 1469, 1472, 1183, 1184, 1185, 1186, 1196, 1197, 1198, 1199, 1449, 1450, 1451, 1452, 1458, 1212, - 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1463, 1464, 1465, 1466, 1249, 1468, 1470, - 1472, 1449, 1450, 1451, 1452, 1458, 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, - 1468, 1470, 1472, 1157, 1158, 1159, 1160, 1167, 1168, 1169, 1170, 1449, 1450, 1451, 1452, 1458, - 1212, 1213, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1468, 1470, 1472, 1434, 1435, 1165, - 1166, 1181, 1182, 1194, 1195, 1200, 1201, 1449, 1450, 1451, 1452, 1458, 1212, 1213, 1220, 1221, - 1222, 1223, 1224, 1225, 1226, 1227, 1459, 1460, 1461, 1462, 1468, 1470, 1472, 1446, 1447, 1448, - 1205, 1457, 1208, 1458, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, - 1447, 1448, 1205, 1457, 1208, 1458, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, - 1242, 1243, 1448, 1457, 1206, 1209, 1458, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, - 1241, 1242, 1243, 1448, 1457, 1206, 1209, 1458, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, - 1240, 1241, 1242, 1243, 1446, 1447, 1448, 1205, 1457, 1208, 1458, 1232, 1233, 1234, 1235, 1236, - 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1447, 1448, 1205, 1457, 1208, 1458, 1232, 1233, 1234, - 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1448, 1457, 1206, 1209, 1458, 1232, 1233, - 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1448, 1457, 1206, 1209, 1458, 1232, - 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1458, 1246, 1247, 1248, 1458, - 1246, 1247, 1248, 1458, 1246, 1247, 1248, 1428, 1429, 1430, 1431, 1432, 1433, 1438, 1439, 1440, - 1441, 1443, 1444, 1445, 1458, 1246, 1247, 1248, 1458, 1246, 1247, 1248, 1458, 1246, 1247, 1248, - 1458, 1246, 1247, 1248, 1428, 1429, 1430, 1431, 1432, 1433, 1438, 1439, 1440, 1441, 1443, 1444, - 1445, 1458, 1246, 1247, 1248, -} - -@(rodata) -DECODE_INDEX_A32 := [256]Decode_Index{ - 0x00 = {0, 3}, - 0x01 = {3, 6}, - 0x02 = {9, 3}, - 0x03 = {12, 6}, - 0x04 = {18, 6}, - 0x05 = {24, 7}, - 0x06 = {31, 3}, - 0x07 = {34, 4}, - 0x08 = {38, 3}, - 0x09 = {41, 6}, - 0x0A = {47, 3}, - 0x0B = {50, 6}, - 0x0C = {56, 6}, - 0x0D = {62, 9}, - 0x0E = {71, 3}, - 0x0F = {74, 6}, - 0x10 = {80, 15}, - 0x11 = {95, 6}, - 0x12 = {101, 12}, - 0x13 = {113, 2}, - 0x14 = {115, 13}, - 0x15 = {128, 5}, - 0x16 = {133, 12}, - 0x17 = {145, 5}, - 0x18 = {150, 8}, - 0x19 = {158, 10}, - 0x1A = {168, 13}, - 0x1B = {181, 6}, - 0x1C = {187, 8}, - 0x1D = {195, 10}, - 0x1E = {205, 8}, - 0x1F = {213, 10}, - 0x20 = {223, 55}, - 0x21 = {278, 45}, - 0x22 = {323, 48}, - 0x23 = {371, 17}, - 0x24 = {388, 55}, - 0x25 = {443, 45}, - 0x26 = {488, 48}, - 0x27 = {536, 17}, - 0x28 = {553, 58}, - 0x29 = {611, 46}, - 0x2A = {657, 50}, - 0x2B = {707, 30}, - 0x2C = {737, 58}, - 0x2D = {795, 46}, - 0x2E = {841, 50}, - 0x2F = {891, 30}, - 0x30 = {921, 48}, - 0x31 = {969, 20}, - 0x32 = {989, 35}, - 0x33 = {1024, 7}, - 0x34 = {1031, 48}, - 0x35 = {1079, 20}, - 0x36 = {1099, 23}, - 0x37 = {1122, 7}, - 0x38 = {1129, 59}, - 0x39 = {1188, 42}, - 0x3A = {1230, 46}, - 0x3B = {1276, 163}, - 0x3C = {1439, 59}, - 0x3D = {1498, 42}, - 0x3E = {1540, 46}, - 0x3F = {1586, 163}, - 0x40 = {1749, 12}, - 0x41 = {1761, 1}, - 0x42 = {1762, 11}, - 0x44 = {1773, 1}, - 0x45 = {1774, 2}, - 0x48 = {1776, 16}, - 0x49 = {1792, 1}, - 0x4A = {1793, 19}, - 0x4C = {1812, 16}, - 0x4D = {1828, 2}, - 0x4E = {1830, 19}, - 0x50 = {1849, 1}, - 0x51 = {1850, 1}, - 0x52 = {1851, 1}, - 0x53 = {1852, 1}, - 0x54 = {1853, 1}, - 0x55 = {1854, 1}, - 0x56 = {1855, 1}, - 0x57 = {1856, 6}, - 0x58 = {1862, 1}, - 0x59 = {1863, 1}, - 0x5A = {1864, 1}, - 0x5B = {1865, 1}, - 0x5C = {1866, 1}, - 0x5D = {1867, 3}, - 0x5E = {1870, 1}, - 0x5F = {1871, 1}, - 0x61 = {1872, 6}, - 0x62 = {1878, 6}, - 0x63 = {1884, 6}, - 0x65 = {1890, 6}, - 0x66 = {1896, 6}, - 0x67 = {1902, 6}, - 0x68 = {1908, 5}, - 0x6A = {1913, 4}, - 0x6B = {1917, 5}, - 0x6C = {1922, 2}, - 0x6E = {1924, 4}, - 0x6F = {1928, 5}, - 0x70 = {1933, 9}, - 0x71 = {1942, 2}, - 0x73 = {1944, 1}, - 0x74 = {1945, 5}, - 0x75 = {1950, 7}, - 0x78 = {1957, 3}, - 0x79 = {1960, 1}, - 0x7A = {1961, 1}, - 0x7B = {1962, 1}, - 0x7C = {1963, 3}, - 0x7D = {1966, 3}, - 0x7E = {1969, 1}, - 0x7F = {1970, 2}, - 0x80 = {1972, 1}, - 0x81 = {1973, 2}, - 0x82 = {1975, 1}, - 0x83 = {1976, 2}, - 0x84 = {1978, 1}, - 0x85 = {1979, 1}, - 0x86 = {1980, 1}, - 0x87 = {1981, 1}, - 0x88 = {1982, 2}, - 0x89 = {1984, 3}, - 0x8A = {1987, 2}, - 0x8B = {1989, 4}, - 0x8C = {1993, 1}, - 0x8D = {1994, 1}, - 0x8E = {1995, 1}, - 0x8F = {1996, 1}, - 0x90 = {1997, 1}, - 0x91 = {1998, 2}, - 0x92 = {2000, 2}, - 0x93 = {2002, 2}, - 0x94 = {2004, 1}, - 0x95 = {2005, 1}, - 0x96 = {2006, 1}, - 0x97 = {2007, 1}, - 0x98 = {2008, 1}, - 0x99 = {2009, 2}, - 0x9A = {2011, 1}, - 0x9B = {2012, 2}, - 0x9C = {2014, 1}, - 0x9D = {2015, 1}, - 0x9E = {2016, 1}, - 0x9F = {2017, 1}, - 0xA0 = {2018, 2}, - 0xA1 = {2020, 2}, - 0xA2 = {2022, 2}, - 0xA3 = {2024, 2}, - 0xA4 = {2026, 2}, - 0xA5 = {2028, 2}, - 0xA6 = {2030, 2}, - 0xA7 = {2032, 2}, - 0xA8 = {2034, 2}, - 0xA9 = {2036, 2}, - 0xAA = {2038, 2}, - 0xAB = {2040, 2}, - 0xAC = {2042, 2}, - 0xAD = {2044, 2}, - 0xAE = {2046, 2}, - 0xAF = {2048, 2}, - 0xB0 = {2050, 2}, - 0xB1 = {2052, 2}, - 0xB2 = {2054, 2}, - 0xB3 = {2056, 2}, - 0xB4 = {2058, 2}, - 0xB5 = {2060, 2}, - 0xB6 = {2062, 2}, - 0xB7 = {2064, 2}, - 0xB8 = {2066, 2}, - 0xB9 = {2068, 2}, - 0xBA = {2070, 2}, - 0xBB = {2072, 2}, - 0xBC = {2074, 2}, - 0xBD = {2076, 2}, - 0xBE = {2078, 2}, - 0xBF = {2080, 2}, - 0xC0 = {2082, 7}, - 0xC1 = {2089, 4}, - 0xC2 = {2093, 12}, - 0xC3 = {2105, 5}, - 0xC4 = {2110, 11}, - 0xC5 = {2121, 8}, - 0xC6 = {2129, 12}, - 0xC7 = {2141, 5}, - 0xC8 = {2146, 6}, - 0xC9 = {2152, 6}, - 0xCA = {2158, 12}, - 0xCB = {2170, 8}, - 0xCC = {2178, 6}, - 0xCD = {2184, 6}, - 0xCE = {2190, 12}, - 0xCF = {2202, 6}, - 0xD0 = {2208, 4}, - 0xD1 = {2212, 4}, - 0xD2 = {2216, 4}, - 0xD3 = {2220, 2}, - 0xD4 = {2222, 4}, - 0xD5 = {2226, 4}, - 0xD6 = {2230, 2}, - 0xD7 = {2232, 2}, - 0xD8 = {2234, 4}, - 0xD9 = {2238, 4}, - 0xDA = {2242, 2}, - 0xDB = {2244, 2}, - 0xDC = {2246, 4}, - 0xDD = {2250, 4}, - 0xDE = {2254, 2}, - 0xDF = {2256, 2}, - 0xE0 = {2258, 18}, - 0xE1 = {2276, 14}, - 0xE2 = {2290, 18}, - 0xE3 = {2308, 15}, - 0xE4 = {2323, 17}, - 0xE5 = {2340, 13}, - 0xE6 = {2353, 18}, - 0xE7 = {2371, 15}, - 0xE8 = {2386, 15}, - 0xE9 = {2401, 11}, - 0xEA = {2412, 11}, - 0xEB = {2423, 73}, - 0xEC = {2496, 16}, - 0xED = {2512, 11}, - 0xEE = {2523, 13}, - 0xEF = {2536, 74}, - 0xF0 = {2610, 3}, - 0xF1 = {2613, 3}, - 0xF2 = {2616, 3}, - 0xF3 = {2619, 3}, - 0xF4 = {2622, 3}, - 0xF5 = {2625, 3}, - 0xF6 = {2628, 3}, - 0xF7 = {2631, 3}, - 0xF8 = {2634, 1}, - 0xF9 = {2635, 1}, - 0xFA = {2636, 1}, - 0xFB = {2637, 1}, - 0xFC = {2638, 1}, - 0xFD = {2639, 1}, - 0xFE = {2640, 1}, - 0xFF = {2641, 1}, -} - -@(rodata) -DECODE_INDEX_T32 := [128]Decode_Index{ - 0x74 = {2642, 23}, - 0x75 = {2665, 19}, - 0x76 = {2684, 19}, - 0x77 = {2703, 101}, - 0x78 = {2804, 26}, - 0x79 = {2830, 33}, - 0x7A = {2863, 18}, - 0x7B = {2881, 6}, - 0x7C = {2887, 20}, - 0x7D = {2907, 71}, - 0x7E = {2978, 22}, - 0x7F = {3000, 126}, -} - -@(rodata) -DECODE_INDEX_T16 := [64]Decode_Index{ - 0x00 = {3126, 1}, - 0x01 = {3127, 1}, - 0x02 = {3128, 1}, - 0x03 = {3129, 1}, - 0x04 = {3130, 1}, - 0x05 = {3131, 1}, - 0x06 = {3132, 2}, - 0x07 = {3134, 2}, - 0x08 = {3136, 1}, - 0x09 = {3137, 1}, - 0x0A = {3138, 1}, - 0x0B = {3139, 1}, - 0x0C = {3140, 1}, - 0x0D = {3141, 1}, - 0x0E = {3142, 1}, - 0x0F = {3143, 1}, - 0x10 = {3144, 16}, - 0x11 = {3160, 7}, - 0x12 = {3167, 1}, - 0x13 = {3168, 1}, - 0x14 = {3169, 2}, - 0x15 = {3171, 2}, - 0x16 = {3173, 2}, - 0x17 = {3175, 2}, - 0x18 = {3177, 1}, - 0x19 = {3178, 1}, - 0x1A = {3179, 1}, - 0x1B = {3180, 1}, - 0x1C = {3181, 1}, - 0x1D = {3182, 1}, - 0x1E = {3183, 1}, - 0x1F = {3184, 1}, - 0x20 = {3185, 1}, - 0x21 = {3186, 1}, - 0x22 = {3187, 1}, - 0x23 = {3188, 1}, - 0x24 = {3189, 1}, - 0x25 = {3190, 1}, - 0x26 = {3191, 1}, - 0x27 = {3192, 1}, - 0x28 = {3193, 1}, - 0x29 = {3194, 1}, - 0x2A = {3195, 1}, - 0x2B = {3196, 1}, - 0x2C = {3197, 7}, - 0x2D = {3204, 2}, - 0x2E = {3206, 4}, - 0x2F = {3210, 8}, - 0x30 = {3218, 1}, - 0x31 = {3219, 1}, - 0x32 = {3220, 1}, - 0x33 = {3221, 1}, - 0x34 = {3222, 1}, - 0x35 = {3223, 1}, - 0x36 = {3224, 1}, - 0x37 = {3225, 3}, - 0x38 = {3228, 1}, - 0x39 = {3229, 1}, -} - -@(rodata) -DECODE_INDEX_T32_SUB := [4096]Decode_Index{ - 0xE84 = {3230, 6}, - 0xE85 = {3236, 2}, - 0xE86 = {3238, 1}, - 0xE87 = {3239, 1}, - 0xE88 = {3240, 1}, - 0xE89 = {3241, 1}, - 0xE8A = {3242, 1}, - 0xE8B = {3243, 2}, - 0xE8C = {3245, 4}, - 0xE8D = {3249, 6}, - 0xE8E = {3255, 1}, - 0xE8F = {3256, 1}, - 0xE90 = {3257, 1}, - 0xE91 = {3258, 1}, - 0xE92 = {3259, 2}, - 0xE93 = {3261, 1}, - 0xE94 = {3262, 1}, - 0xE95 = {3263, 1}, - 0xE96 = {3264, 1}, - 0xE97 = {3265, 2}, - 0xE9C = {3267, 1}, - 0xE9D = {3268, 1}, - 0xE9E = {3269, 1}, - 0xE9F = {3270, 1}, - 0xEA0 = {3271, 2}, - 0xEA1 = {3273, 3}, - 0xEA2 = {3276, 1}, - 0xEA3 = {3277, 1}, - 0xEA4 = {3278, 7}, - 0xEA5 = {3285, 7}, - 0xEA6 = {3292, 1}, - 0xEA7 = {3293, 1}, - 0xEA8 = {3294, 1}, - 0xEA9 = {3295, 2}, - 0xEB1 = {3297, 1}, - 0xEB4 = {3298, 1}, - 0xEB5 = {3299, 1}, - 0xEB6 = {3300, 1}, - 0xEB7 = {3301, 1}, - 0xEBB = {3302, 1}, - 0xEBC = {3303, 1}, - 0xEBD = {3304, 1}, - 0xEC0 = {3305, 2}, - 0xEC1 = {3307, 1}, - 0xEC2 = {3308, 3}, - 0xEC3 = {3311, 2}, - 0xEC4 = {3313, 2}, - 0xEC5 = {3315, 1}, - 0xEC6 = {3316, 7}, - 0xEC7 = {3323, 2}, - 0xEC8 = {3325, 1}, - 0xEC9 = {3326, 1}, - 0xECA = {3327, 2}, - 0xECB = {3329, 2}, - 0xECC = {3331, 1}, - 0xECD = {3332, 1}, - 0xECE = {3333, 2}, - 0xECF = {3335, 2}, - 0xED6 = {3337, 4}, - 0xED8 = {3341, 4}, - 0xED9 = {3345, 4}, - 0xEDC = {3349, 4}, - 0xEDD = {3353, 4}, - 0xEE0 = {3357, 23}, - 0xEE1 = {3380, 22}, - 0xEE2 = {3402, 22}, - 0xEE3 = {3424, 29}, - 0xEE4 = {3453, 23}, - 0xEE5 = {3476, 22}, - 0xEE6 = {3498, 22}, - 0xEE7 = {3520, 29}, - 0xEE8 = {3549, 28}, - 0xEE9 = {3577, 12}, - 0xEEA = {3589, 13}, - 0xEEB = {3602, 18}, - 0xEEC = {3620, 27}, - 0xEED = {3647, 13}, - 0xEEE = {3660, 22}, - 0xEEF = {3682, 21}, - 0xEF0 = {3703, 15}, - 0xEF1 = {3718, 15}, - 0xEF2 = {3733, 15}, - 0xEF3 = {3748, 15}, - 0xEF4 = {3763, 15}, - 0xEF5 = {3778, 15}, - 0xEF6 = {3793, 15}, - 0xEF7 = {3808, 15}, - 0xEF8 = {3823, 3}, - 0xEF9 = {3826, 3}, - 0xEFA = {3829, 3}, - 0xEFB = {3832, 3}, - 0xEFC = {3835, 3}, - 0xEFD = {3838, 3}, - 0xEFE = {3841, 3}, - 0xEFF = {3844, 3}, - 0xF00 = {3847, 10}, - 0xF01 = {3857, 10}, - 0xF02 = {3867, 7}, - 0xF03 = {3874, 7}, - 0xF04 = {3881, 10}, - 0xF05 = {3891, 8}, - 0xF06 = {3899, 6}, - 0xF07 = {3905, 6}, - 0xF08 = {3911, 4}, - 0xF09 = {3915, 5}, - 0xF0A = {3920, 3}, - 0xF0B = {3923, 3}, - 0xF0C = {3926, 3}, - 0xF0D = {3929, 3}, - 0xF0E = {3932, 3}, - 0xF0F = {3935, 3}, - 0xF10 = {3938, 5}, - 0xF11 = {3943, 6}, - 0xF12 = {3949, 5}, - 0xF13 = {3954, 5}, - 0xF14 = {3959, 6}, - 0xF15 = {3965, 6}, - 0xF16 = {3971, 6}, - 0xF17 = {3977, 6}, - 0xF18 = {3983, 3}, - 0xF19 = {3986, 3}, - 0xF1A = {3989, 3}, - 0xF1B = {3992, 4}, - 0xF1C = {3996, 4}, - 0xF1D = {4000, 4}, - 0xF1E = {4004, 3}, - 0xF1F = {4007, 3}, - 0xF20 = {4010, 3}, - 0xF21 = {4013, 3}, - 0xF22 = {4016, 3}, - 0xF23 = {4019, 3}, - 0xF24 = {4022, 4}, - 0xF25 = {4026, 3}, - 0xF26 = {4029, 3}, - 0xF27 = {4032, 3}, - 0xF28 = {4035, 3}, - 0xF29 = {4038, 3}, - 0xF2A = {4041, 3}, - 0xF2B = {4044, 3}, - 0xF2C = {4047, 4}, - 0xF2D = {4051, 3}, - 0xF2E = {4054, 3}, - 0xF2F = {4057, 3}, - 0xF30 = {4060, 4}, - 0xF31 = {4064, 3}, - 0xF32 = {4067, 5}, - 0xF33 = {4072, 3}, - 0xF34 = {4075, 4}, - 0xF35 = {4079, 3}, - 0xF36 = {4082, 5}, - 0xF37 = {4087, 3}, - 0xF38 = {4090, 5}, - 0xF39 = {4095, 3}, - 0xF3A = {4098, 18}, - 0xF3B = {4116, 8}, - 0xF3C = {4124, 4}, - 0xF3D = {4128, 3}, - 0xF3E = {4131, 4}, - 0xF3F = {4135, 3}, - 0xF40 = {4138, 5}, - 0xF41 = {4143, 6}, - 0xF42 = {4149, 4}, - 0xF43 = {4153, 4}, - 0xF44 = {4157, 6}, - 0xF45 = {4163, 6}, - 0xF46 = {4169, 4}, - 0xF47 = {4173, 4}, - 0xF48 = {4177, 4}, - 0xF49 = {4181, 5}, - 0xF4A = {4186, 3}, - 0xF4B = {4189, 3}, - 0xF4C = {4192, 3}, - 0xF4D = {4195, 3}, - 0xF4E = {4198, 3}, - 0xF4F = {4201, 3}, - 0xF50 = {4204, 3}, - 0xF51 = {4207, 4}, - 0xF52 = {4211, 3}, - 0xF53 = {4214, 3}, - 0xF54 = {4217, 4}, - 0xF55 = {4221, 4}, - 0xF56 = {4225, 4}, - 0xF57 = {4229, 4}, - 0xF58 = {4233, 3}, - 0xF59 = {4236, 3}, - 0xF5A = {4239, 3}, - 0xF5B = {4242, 4}, - 0xF5C = {4246, 4}, - 0xF5D = {4250, 4}, - 0xF5E = {4254, 3}, - 0xF5F = {4257, 3}, - 0xF60 = {4260, 3}, - 0xF61 = {4263, 3}, - 0xF62 = {4266, 3}, - 0xF63 = {4269, 3}, - 0xF64 = {4272, 4}, - 0xF65 = {4276, 3}, - 0xF66 = {4279, 3}, - 0xF67 = {4282, 3}, - 0xF68 = {4285, 3}, - 0xF69 = {4288, 3}, - 0xF6A = {4291, 3}, - 0xF6B = {4294, 3}, - 0xF6C = {4297, 4}, - 0xF6D = {4301, 3}, - 0xF6E = {4304, 3}, - 0xF6F = {4307, 3}, - 0xF70 = {4310, 3}, - 0xF71 = {4313, 3}, - 0xF72 = {4316, 3}, - 0xF73 = {4319, 3}, - 0xF74 = {4322, 3}, - 0xF75 = {4325, 3}, - 0xF76 = {4328, 3}, - 0xF77 = {4331, 3}, - 0xF78 = {4334, 3}, - 0xF79 = {4337, 3}, - 0xF7A = {4340, 3}, - 0xF7B = {4343, 3}, - 0xF7C = {4346, 3}, - 0xF7D = {4349, 3}, - 0xF7E = {4352, 3}, - 0xF7F = {4355, 4}, - 0xF80 = {4359, 1}, - 0xF81 = {4360, 1}, - 0xF82 = {4361, 1}, - 0xF83 = {4362, 2}, - 0xF84 = {4364, 1}, - 0xF85 = {4365, 2}, - 0xF88 = {4367, 1}, - 0xF89 = {4368, 2}, - 0xF8A = {4370, 1}, - 0xF8B = {4371, 1}, - 0xF8C = {4372, 1}, - 0xF8D = {4373, 2}, - 0xF91 = {4375, 1}, - 0xF93 = {4376, 1}, - 0xF99 = {4377, 2}, - 0xF9B = {4379, 1}, - 0xFA0 = {4380, 3}, - 0xFA1 = {4383, 3}, - 0xFA2 = {4386, 3}, - 0xFA3 = {4389, 3}, - 0xFA4 = {4392, 3}, - 0xFA5 = {4395, 3}, - 0xFA6 = {4398, 1}, - 0xFA7 = {4399, 1}, - 0xFA8 = {4400, 10}, - 0xFA9 = {4410, 10}, - 0xFAA = {4420, 6}, - 0xFAB = {4426, 1}, - 0xFAC = {4427, 6}, - 0xFAD = {4433, 6}, - 0xFAE = {4439, 6}, - 0xFB0 = {4445, 3}, - 0xFB5 = {4448, 1}, - 0xFB8 = {4449, 1}, - 0xFB9 = {4450, 1}, - 0xFBA = {4451, 1}, - 0xFBB = {4452, 1}, - 0xFBC = {4453, 1}, - 0xFBE = {4454, 1}, - 0xFC0 = {4455, 1}, - 0xFC1 = {4456, 1}, - 0xFC2 = {4457, 2}, - 0xFC3 = {4459, 2}, - 0xFC4 = {4461, 1}, - 0xFC5 = {4462, 1}, - 0xFC6 = {4463, 2}, - 0xFC7 = {4465, 2}, - 0xFC8 = {4467, 7}, - 0xFC9 = {4474, 11}, - 0xFCA = {4485, 2}, - 0xFCB = {4487, 2}, - 0xFCC = {4489, 7}, - 0xFCD = {4496, 7}, - 0xFCE = {4503, 2}, - 0xFCF = {4505, 2}, - 0xFD9 = {4507, 4}, - 0xFE0 = {4511, 28}, - 0xFE1 = {4539, 26}, - 0xFE2 = {4565, 26}, - 0xFE3 = {4591, 32}, - 0xFE4 = {4623, 29}, - 0xFE5 = {4652, 27}, - 0xFE6 = {4679, 27}, - 0xFE7 = {4706, 33}, - 0xFE8 = {4739, 32}, - 0xFE9 = {4771, 17}, - 0xFEA = {4788, 17}, - 0xFEB = {4805, 29}, - 0xFEC = {4834, 31}, - 0xFED = {4865, 18}, - 0xFEE = {4883, 26}, - 0xFEF = {4909, 32}, - 0xFF0 = {4941, 19}, - 0xFF1 = {4960, 18}, - 0xFF2 = {4978, 17}, - 0xFF3 = {4995, 17}, - 0xFF4 = {5012, 19}, - 0xFF5 = {5031, 18}, - 0xFF6 = {5049, 17}, - 0xFF7 = {5066, 17}, - 0xFF8 = {5083, 4}, - 0xFF9 = {5087, 4}, - 0xFFA = {5091, 4}, - 0xFFB = {5095, 17}, - 0xFFC = {5112, 4}, - 0xFFD = {5116, 4}, - 0xFFE = {5120, 4}, - 0xFFF = {5124, 17}, -} - diff --git a/core/rexcode/arm32/encoder.odin b/core/rexcode/arm32/encoder.odin index 2eb4770a4..94dcf851b 100644 --- a/core/rexcode/arm32/encoder.odin +++ b/core/rexcode/arm32/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= @@ -115,7 +117,7 @@ encode_one_inline :: #force_inline proc( return 0, 0, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, 0, false diff --git a/core/rexcode/arm32/encoding_types.odin b/core/rexcode/arm32/encoding_types.odin index fde59c9db..f8614cb88 100644 --- a/core/rexcode/arm32/encoding_types.odin +++ b/core/rexcode/arm32/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 import "../isa" diff --git a/core/rexcode/arm32/immediates.odin b/core/rexcode/arm32/immediates.odin index 07a87625a..e5cf15ebe 100644 --- a/core/rexcode/arm32/immediates.odin +++ b/core/rexcode/arm32/immediates.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/instructions.odin b/core/rexcode/arm32/instructions.odin index 1cbeaa08e..690eeddf0 100644 --- a/core/rexcode/arm32/instructions.odin +++ b/core/rexcode/arm32/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/mnemonics.odin b/core/rexcode/arm32/mnemonics.odin index 39b709233..ce5401f19 100644 --- a/core/rexcode/arm32/mnemonics.odin +++ b/core/rexcode/arm32/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/operands.odin b/core/rexcode/arm32/operands.odin index d7405d843..513716156 100644 --- a/core/rexcode/arm32/operands.odin +++ b/core/rexcode/arm32/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/printer.odin b/core/rexcode/arm32/printer.odin index f453cec58..110ed668b 100644 --- a/core/rexcode/arm32/printer.odin +++ b/core/rexcode/arm32/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 import "core:strings" diff --git a/core/rexcode/arm32/registers.odin b/core/rexcode/arm32/registers.odin index bde92fa74..9bdb102c4 100644 --- a/core/rexcode/arm32/registers.odin +++ b/core/rexcode/arm32/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/reloc.odin b/core/rexcode/arm32/reloc.odin index 1c6bacefe..ce72f0086 100644 --- a/core/rexcode/arm32/reloc.odin +++ b/core/rexcode/arm32/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32 // ============================================================================= diff --git a/core/rexcode/arm32/encoding_table.odin b/core/rexcode/arm32/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/arm32/encoding_table.odin rename to core/rexcode/arm32/tablegen/encoding_table.odin index 34aed16bb..00a78d1fb 100644 --- a/core/rexcode/arm32/encoding_table.odin +++ b/core/rexcode/arm32/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_arm32 +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm32_tablegen // ============================================================================= // AArch32 ENCODING TABLE diff --git a/core/rexcode/arm32/tablegen/gen.odin b/core/rexcode/arm32/tablegen/gen.odin new file mode 100644 index 000000000..cc16d9478 --- /dev/null +++ b/core/rexcode/arm32/tablegen/gen.odin @@ -0,0 +1,477 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm32_tablegen + +// ============================================================================= +// AArch32 TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_FORM_IDX + +// DECODE_BUCKET_LIST + A32/T32/T16/T32_SUB index +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run arm32/tablegen # Stage A +// odin run arm32/tablegen/generated # Stage B +// +// AArch32 is fixed-width-per-mode (A32 = 4 bytes, T16 = 2 bytes, T32 = 4 bytes +// packed as low_halfword | high_halfword << 16). Three primary dispatch tables +// (one per mode/size) with a secondary T32 sub-bucket; the decode bucketing +// below is ported verbatim from the old tools/gen_decode_tables.odin. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "arm32.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "arm32.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "arm32.entries.bin", "Decode_Entry"}, + {"DECODE_FORM_IDX", "arm32.form_idx.bin", "u16"}, + {"DECODE_BUCKET_LIST", "arm32.bucket_list.bin", "u16"}, + {"DECODE_INDEX_A32", "arm32.idx_a32.bin", "Decode_Index"}, + {"DECODE_INDEX_T32", "arm32.idx_t32.bin", "Decode_Index"}, + {"DECODE_INDEX_T16", "arm32.idx_t16.bin", "Decode_Index"}, + {"DECODE_INDEX_T32_SUB", "arm32.idx_t32_sub.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +A32_BUCKETS :: 256 // bits[27:20] +T32_BUCKETS :: 128 // bits[31:25] +T16_BUCKETS :: 64 // bits[15:10] +T32_SUB_BUCKETS :: 32 // bits[24:20] of u32 + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + mode: lib.Mode, + flags: lib.Encoding_Flags, + is_thumb32: bool, + key: u16, // primary dispatch key (8 bits A32, 7 bits T32, 6 bits T16) + ilen: u8, + form_idx: u16, // index of this form within ENCODING_TABLE[mnemonic] +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("arm32 tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm32_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. int { + if e.mode == .A32 { return 0 } + if e.is_thumb32 || e.ilen == 4 { return 1 } + return 2 +} + +// Variable bits within the bucket-key range. For each combination of those +// variable bits we emit a separate bucket key, so a single entry is reachable +// via every word that can match its mask. fixed_key must be sanitized via +// `bits & mask` — entry bits often carry a default value at variable positions +// (e.g. U=1 in LDR's base 0x05900000), and those defaults must not pre-set bits +// in the key or we'd skip the zero-side bucket during enumeration. +enumerate_keys :: proc(bits, mask: u32, key_shift: u32, key_bits: u32, out: ^[dynamic]u16) { + clear(out) + key_mask := (u32(1) << key_bits) - 1 + fixed_key := ((bits & mask) >> key_shift) & key_mask + var_bits := (~mask >> key_shift) & key_mask + // Enumerate submasks of var_bits via the classic Gosper-style walk. + sub: u32 = 0 + for { + append(out, u16(fixed_key | sub)) + if var_bits == 0 { break } + if sub == var_bits { break } + sub = (sub - var_bits) & var_bits // next non-zero submask + } +} + +emit_decode_tables :: proc() -> (total: int) { + all: [dynamic]Entry + defer delete(all) + + for mn in Mnemonic { + for f, fi in ENCODING_TABLE[mn] { + ilen := lib.inst_size_from_bits(f.bits, f.mode) + e := Entry{ + mnemonic = mn, + ops = f.ops, + enc = f.enc, + bits = f.bits, + mask = f.mask, + feature = f.feature, + mode = f.mode, + flags = f.flags, + is_thumb32 = f.flags.thumb32, + ilen = ilen, + form_idx = u16(fi), + } + // Compute dispatch key per mode/size. + if e.mode == .A32 { + e.key = u16((f.bits >> 20) & 0xFF) + } else if e.is_thumb32 || ilen == 4 { + // T32 32-bit: bits[31:25] of packed u32 (top 7 bits of high halfword) + e.key = u16((f.bits >> 25) & 0x7F) + } else { + // T16: bits[15:10] of the halfword (stored in low 16 of u32) + e.key = u16((f.bits >> 10) & 0x3F) + } + append(&all, e) + } + } + + // Sort: by mode group (A32 first, then T32-wide, then T16), then by key, + // then by mask popcount descending so more-specific forms match first. + slice.sort_by(all[:], proc(x, y: Entry) -> bool { + mx := mode_rank(x) + my := mode_rank(y) + if mx != my { return mx < my } + if x.key != y.key { return x.key < y.key } + xc := bits.count_ones(x.mask) + yc := bits.count_ones(y.mask) + if xc != yc { return xc > yc } + return u16(x.mnemonic) < u16(y.mnemonic) + }) + + // First pass: collect (entry_idx, bucket_key) pairs across modes, expanding + // variable bits within the bucket-key range. Then group by bucket. + A32_Pair :: struct { bucket: u16, entry_idx: u16 } + a32_pairs: [dynamic]A32_Pair + t32_pairs: [dynamic]A32_Pair + t16_pairs: [dynamic]A32_Pair + t32_sub_pairs: [dynamic]A32_Pair + defer delete(a32_pairs); defer delete(t32_pairs) + defer delete(t16_pairs); defer delete(t32_sub_pairs) + + keys: [dynamic]u16 + defer delete(keys) + + for e, i in all { + if e.mode == .A32 { + enumerate_keys(e.bits, e.mask, 20, 8, &keys) + for k in keys { append(&a32_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } + } else if e.is_thumb32 || e.ilen == 4 { + enumerate_keys(e.bits, e.mask, 25, 7, &keys) + for k in keys { append(&t32_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } + // Sub-bucket: bits 24:20 of word + sub_keys: [dynamic]u16 + defer delete(sub_keys) + enumerate_keys(e.bits, e.mask, 20, 5, &sub_keys) + for k in keys { + for sk in sub_keys { + append(&t32_sub_pairs, A32_Pair{ + bucket = k * T32_SUB_BUCKETS + sk, + entry_idx = u16(i), + }) + } + } + } else { + enumerate_keys(e.bits, e.mask, 10, 6, &keys) + for k in keys { append(&t16_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } + } + } + + // Within each bucket we want most-specific (highest mask popcount) first, + // tiebreak by mnemonic, so the decoder's linear scan picks the most specific + // encoding before falling through to a more general one. Encode + // (bucket, -popcount, mnemonic) into a single u64 sort key. + Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u16 } + rebuild :: proc(pairs: ^[dynamic]A32_Pair, all: []Entry) { + sortable := make([dynamic]Sort_Pair, 0, len(pairs)) + defer delete(sortable) + for p in pairs^ { + e := all[p.entry_idx] + pop := u64(bits.count_ones(e.mask)) + key := (u64(p.bucket) << 48) | ((255 - pop) << 32) | u64(e.mnemonic) + append(&sortable, Sort_Pair{ + sort_key = key, entry_idx = p.entry_idx, bucket = p.bucket, + }) + } + slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) + clear(pairs) + for s in sortable { append(pairs, A32_Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } + } + rebuild(&a32_pairs, all[:]) + rebuild(&t32_pairs, all[:]) + rebuild(&t16_pairs, all[:]) + rebuild(&t32_sub_pairs, all[:]) + + // Build a flat u16 dispatch list (DECODE_BUCKET_LIST). Each bucket points to + // a contiguous run of entry indices in that list. + a32_idx: [A32_BUCKETS]Range + t32_idx: [T32_BUCKETS]Range + t16_idx: [T16_BUCKETS]Range + t32_sub_idx: [T32_BUCKETS * T32_SUB_BUCKETS]Range + + bucket_list: [dynamic]u16 + defer delete(bucket_list) + + emit_pairs :: proc(pairs: []A32_Pair, idx: []Range, list: ^[dynamic]u16) { + prev_bucket: i32 = -1 + for p in pairs { + cur_bucket := i32(p.bucket) + if cur_bucket != prev_bucket { + idx[cur_bucket].start = u16(len(list)) + idx[cur_bucket].count = 0 + prev_bucket = cur_bucket + } + append(list, p.entry_idx) + idx[cur_bucket].count += 1 + } + } + emit_pairs(a32_pairs[:], a32_idx[:], &bucket_list) + emit_pairs(t32_pairs[:], t32_idx[:], &bucket_list) + emit_pairs(t16_pairs[:], t16_idx[:], &bucket_list) + emit_pairs(t32_sub_pairs[:], t32_sub_idx[:], &bucket_list) + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm32_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by mode + primary key.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_u16_array(&sb, "DECODE_FORM_IDX", form_idx_slice(all[:])) + emit_u16_array(&sb, "DECODE_BUCKET_LIST", bucket_list[:]) + + emit_range(&sb, "DECODE_INDEX_A32", a32_idx[:]) + emit_range(&sb, "DECODE_INDEX_T32", t32_idx[:]) + emit_range(&sb, "DECODE_INDEX_T16", t16_idx[:]) + emit_range(&sb, "DECODE_INDEX_T32_SUB", t32_sub_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +form_idx_slice :: proc(entries: []Entry) -> []u16 { + out := make([]u16, len(entries), context.temp_allocator) + for e, i in entries { out[i] = e.form_idx } + return out +} + +emit_u16_array :: proc(sb: ^strings.Builder, name: string, items: []u16) { + fmt.sbprintfln(sb, "%s := [%d]u16{{", name, len(items)) + for v, i in items { + if i % 16 == 0 { + if i > 0 { strings.write_string(sb, "\n") } + strings.write_string(sb, "\t") + } + fmt.sbprintf(sb, " %d,", v) + } + strings.write_string(sb, "\n}\n\n") +} + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 5d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, + feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], + bits, mask, feature, mode, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.sets_flags { append(&parts, "sets_flags=true") } + if f.cond_in_28 { append(&parts, "cond_in_28=true") } + if f.branch { append(&parts, "branch=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + if f.writes_pc { append(&parts, "writes_pc=true") } + if f.thumb32 { append(&parts, "thumb32=true") } + if f.deprecated { append(&parts, "deprecated=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm32_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 21) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +DECODE_T32_SUB_BUCKETS :: 32 +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm32\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "arm32.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "arm32.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "arm32.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "arm32.form_idx.bin", raw(&DECODE_FORM_IDX, size_of(DECODE_FORM_IDX))) + w(TABLES + "arm32.bucket_list.bin", raw(&DECODE_BUCKET_LIST, size_of(DECODE_BUCKET_LIST))) + w(TABLES + "arm32.idx_a32.bin", raw(&DECODE_INDEX_A32, size_of(DECODE_INDEX_A32))) + w(TABLES + "arm32.idx_t32.bin", raw(&DECODE_INDEX_T32, size_of(DECODE_INDEX_T32))) + w(TABLES + "arm32.idx_t16.bin", raw(&DECODE_INDEX_T16, size_of(DECODE_INDEX_T16))) + w(TABLES + "arm32.idx_t32_sub.bin", raw(&DECODE_INDEX_T32_SUB, size_of(DECODE_INDEX_T32_SUB))) +} diff --git a/core/rexcode/arm32/tables.odin b/core/rexcode/arm32/tables.odin new file mode 100644 index 000000000..0798b0603 --- /dev/null +++ b/core/rexcode/arm32/tables.odin @@ -0,0 +1,70 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm32 + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 21) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +DECODE_T32_SUB_BUCKETS :: 32 + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/arm32.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/arm32.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/arm32.entries.bin", []Decode_Entry) +@(rodata) DECODE_FORM_IDX := #load("tables/arm32.form_idx.bin", []u16) +@(rodata) DECODE_BUCKET_LIST := #load("tables/arm32.bucket_list.bin", []u16) +@(rodata) DECODE_INDEX_A32 := #load("tables/arm32.idx_a32.bin", []Decode_Index) +@(rodata) DECODE_INDEX_T32 := #load("tables/arm32.idx_t32.bin", []Decode_Index) +@(rodata) DECODE_INDEX_T16 := #load("tables/arm32.idx_t16.bin", []Decode_Index) +@(rodata) DECODE_INDEX_T32_SUB := #load("tables/arm32.idx_t32_sub.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/arm32/tables/arm32.bucket_list.bin b/core/rexcode/arm32/tables/arm32.bucket_list.bin new file mode 100644 index 0000000000000000000000000000000000000000..aaca502304601005ac6c7532a818a255efdd94b3 GIT binary patch literal 10282 zcmZQzU}RuoU}j)oU}0cnU}a!pU}Ios;9%fnU}NB7U}xZF;9%fkP-akJP-Wm{;A7Ba z&|=VL;Ah}v5MbbA5M&Ty5M~fz5Czj>4B`wD43Z3D3{ni@4AKk|3^EL|3~~(e3^EJ~ z42od364Wd;26YAv1|_I@It*$Ix(wLWw47lD!%BwL467K{ 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Brendan Punsky (dotbmp@github), original author + package rexcode_arm32_tests import "core:fmt" @@ -8,7 +10,8 @@ ok_count, fail_count: int @(private="file") check :: proc(name: string, mn: a.Mnemonic, idx: int, want_bits, want_mask: u32) { - enc := a.ENCODING_TABLE[mn] + _run := a.ENCODE_RUNS[u16(mn)] + enc := a.ENCODE_FORMS[_run.start:][:_run.count] if idx >= len(enc) { fmt.printf(" [FAIL] %s: entry %d not present (have %d entries)\n", name, idx, len(enc)) fail_count += 1 diff --git a/core/rexcode/arm32/tests/sweep.odin b/core/rexcode/arm32/tests/sweep.odin index 069b509e5..cc52a971e 100644 --- a/core/rexcode/arm32/tests/sweep.odin +++ b/core/rexcode/arm32/tests/sweep.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm32_tests import "core:fmt" @@ -41,7 +43,8 @@ run_sweep_tests :: proc() { only_print_kind: string = "" for mn in a.Mnemonic { - forms := a.ENCODING_TABLE[mn] + _run := a.ENCODE_RUNS[u16(mn)] + forms := a.ENCODE_FORMS[_run.start:][:_run.count] for &f, idx in forms { ilen := a.inst_size_from_bits(f.bits, f.mode) diff --git a/core/rexcode/arm32/tools/dump_verify_input.odin b/core/rexcode/arm32/tools/dump_verify_input.odin index 8b802bea5..d019a6c79 100644 --- a/core/rexcode/arm32/tools/dump_verify_input.odin +++ b/core/rexcode/arm32/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -39,7 +41,8 @@ main :: proc() { n_a32, n_t32, n_t16 := 0, 0, 0 for mn in a.Mnemonic { - for &f in a.ENCODING_TABLE[mn] { + _run := a.ENCODE_RUNS[u16(mn)] + for &f in a.ENCODE_FORMS[_run.start:][:_run.count] { bits := fill_safe_operands(&f) ilen := a.inst_size_from_bits(f.bits, f.mode) if f.mode == .A32 { diff --git a/core/rexcode/arm32/tools/gen_decode_tables.odin b/core/rexcode/arm32/tools/gen_decode_tables.odin deleted file mode 100644 index 2095ba3a6..000000000 --- a/core/rexcode/arm32/tools/gen_decode_tables.odin +++ /dev/null @@ -1,381 +0,0 @@ -package main - -// ============================================================================= -// AArch32 DECODE-TABLE GENERATOR -// ============================================================================= -// -// Three primary dispatch tables (one per Mode/size): -// -// A32 (4-byte instructions): -// key = bits[27:20] of the 32-bit word (256 buckets). -// This is the natural major-opcode + S-bit + sub-op field. -// -// T32 32-bit (Thumb-2 wide): -// key = bits[31:25] of the packed u32 (high halfword top 7 bits; -// 128 buckets). Top 5 bits of the first halfword are 11101, 11110, -// or 11111 -- T32 32-bit identifier. -// -// T16 (Thumb-1, 16-bit): -// key = bits[15:10] of the halfword (64 buckets). Adequate spread for -// the ~120 T16 forms. -// -// Within each bucket, entries are sorted by mask-popcount descending so -// the most-specific encoding wins on first match. Linear scan inside the -// bucket is fine (worst-case ~50 entries on A32 data-proc, ~30 on T32). -// -// Run with: cd arm32 && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import a "../" - -Entry :: struct { - mnemonic: a.Mnemonic, - ops: [4]a.Operand_Type, - enc: [4]a.Operand_Encoding, - bits: u32, - mask: u32, - feature: a.Feature, - mode: a.Mode, - flags: a.Encoding_Flags, - is_thumb32: bool, - key: u16, // primary dispatch key (8 bits A32, 7 bits T32, 6 bits T16) - ilen: u8, - form_idx: u16, // index of this form within ENCODING_TABLE[mnemonic] -} - -Range :: struct { - start: u16, - count: u16, -} - -A32_BUCKETS :: 256 // bits[27:20] -T32_BUCKETS :: 128 // bits[31:25] -T16_BUCKETS :: 64 // bits[15:10] - -// T32 wide instructions cluster around top-bit patterns 11101/11110/11111 -// (bits[31:27] in {0x1D, 0x1E, 0x1F}). The primary bucket can hit ~100 -// entries; we sub-bucket the densest primary buckets on bits[24:20] (32 -// values) to bring per-bucket scan to <= 10. -T32_SUB_BUCKETS :: 32 // bits[24:20] of u32 - -main :: proc() { - fmt.println("Generating AArch32 decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mn in a.Mnemonic { - for f, fi in a.ENCODING_TABLE[mn] { - ilen := a.inst_size_from_bits(f.bits, f.mode) - e := Entry{ - mnemonic = mn, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - mode = f.mode, - flags = f.flags, - is_thumb32 = f.flags.thumb32, - ilen = ilen, - form_idx = u16(fi), - } - // Compute dispatch key per mode/size. - if e.mode == .A32 { - e.key = u16((f.bits >> 20) & 0xFF) - } else if e.is_thumb32 || ilen == 4 { - // T32 32-bit: bits[31:25] of packed u32 (i.e. top 7 bits of - // the high halfword) - e.key = u16((f.bits >> 25) & 0x7F) - } else { - // T16: bits[15:10] of the halfword (stored in low 16 of u32) - e.key = u16((f.bits >> 10) & 0x3F) - } - append(&all, e) - } - } - - // Sort: by mode group (A32 first, then T32-wide, then T16), then by key, - // then by mask popcount descending so more-specific forms match first. - slice.sort_by(all[:], proc(x, y: Entry) -> bool { - mx := mode_rank(x) - my := mode_rank(y) - if mx != my { return mx < my } - if x.key != y.key { return x.key < y.key } - xc := bits.count_ones(x.mask) - yc := bits.count_ones(y.mask) - if xc != yc { return xc > yc } - return u16(x.mnemonic) < u16(y.mnemonic) - }) - - // First pass: collect (entry_idx, bucket_key) pairs across modes, expanding - // variable bits within the bucket-key range. Then group by bucket. - // Secondary T32 index keyed on bits 24:20 of u32 (the densest primary - // T32 bucket has > 100 entries; this brings the inner scan to ~10). - A32_Pair :: struct { bucket: u16, entry_idx: u16 } - a32_pairs: [dynamic]A32_Pair - t32_pairs: [dynamic]A32_Pair - t16_pairs: [dynamic]A32_Pair - t32_sub_pairs: [dynamic]A32_Pair - defer delete(a32_pairs); defer delete(t32_pairs) - defer delete(t16_pairs); defer delete(t32_sub_pairs) - - enumerate_keys :: proc(bits, mask: u32, key_shift: u32, key_bits: u32, out: ^[dynamic]u16) { - clear(out) - // Variable bits within the bucket-key range. For each combination of - // those variable bits we emit a separate bucket key, so a single entry - // is reachable via every word that can match its mask. fixed_key must - // be sanitized via `bits & mask` — entry bits often carry a default - // value at variable positions (e.g. U=1 in LDR's base 0x05900000), and - // those defaults must not pre-set bits in the key or we'd skip the - // zero-side bucket during enumeration. - key_mask := (u32(1) << key_bits) - 1 - fixed_key := ((bits & mask) >> key_shift) & key_mask - var_bits := (~mask >> key_shift) & key_mask - // Enumerate submasks of var_bits via the classic Gosper-style walk. - sub: u32 = 0 - for { - append(out, u16(fixed_key | sub)) - if var_bits == 0 { break } - if sub == var_bits { break } - sub = (sub - var_bits) & var_bits // next non-zero submask - } - } - - keys: [dynamic]u16 - defer delete(keys) - - for e, i in all { - if e.mode == .A32 { - enumerate_keys(e.bits, e.mask, 20, 8, &keys) - for k in keys { append(&a32_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } - } else if e.is_thumb32 || e.ilen == 4 { - enumerate_keys(e.bits, e.mask, 25, 7, &keys) - for k in keys { append(&t32_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } - // Sub-bucket: bits 24:20 of word - sub_keys: [dynamic]u16 - defer delete(sub_keys) - enumerate_keys(e.bits, e.mask, 20, 5, &sub_keys) - for k in keys { - for sk in sub_keys { - append(&t32_sub_pairs, A32_Pair{ - bucket = k * T32_SUB_BUCKETS + sk, - entry_idx = u16(i), - }) - } - } - } else { - enumerate_keys(e.bits, e.mask, 10, 6, &keys) - for k in keys { append(&t16_pairs, A32_Pair{bucket = k, entry_idx = u16(i)}) } - } - } - - // The original entry array `all` is already sorted by (mode, key, popcount, - // mnemonic). We need to emit a single linear DECODE_ENTRIES array where - // each bucket points to a contiguous slice. Because an entry can appear in - // multiple buckets, we duplicate entries in the emitted array — bucket - // (start, count) addresses the duplicated region. - - // Within each bucket we want most-specific (highest mask popcount) first, - // tiebreak by mnemonic, so the decoder's linear scan picks the most - // specific encoding before falling through to a more general one. Encode - // (bucket, -popcount, mnemonic) into a single u64 sort key so we don't - // need a closure-capturing comparator. - Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u16 } - rebuild :: proc(pairs: ^[dynamic]A32_Pair, all: []Entry) { - sortable := make([dynamic]Sort_Pair, 0, len(pairs)) - defer delete(sortable) - for p in pairs^ { - e := all[p.entry_idx] - pop := u64(bits.count_ones(e.mask)) - // bucket << 48 | (255 - pop) << 32 | mnemonic - key := (u64(p.bucket) << 48) | ((255 - pop) << 32) | u64(e.mnemonic) - append(&sortable, Sort_Pair{ - sort_key = key, entry_idx = p.entry_idx, bucket = p.bucket, - }) - } - slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) - clear(pairs) - for s in sortable { append(pairs, A32_Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } - } - rebuild(&a32_pairs, all[:]) - rebuild(&t32_pairs, all[:]) - rebuild(&t16_pairs, all[:]) - rebuild(&t32_sub_pairs, all[:]) - - // Build a flat u16 dispatch list (DECODE_BUCKET_LIST). Each bucket - // points to a contiguous run of entry indices in that list. Duplicating - // small u16 indices instead of full 21-byte entries keeps the LLVM - // initializer manageable (the previous "duplicate full entries" approach - // produced ~108KB of initializer and broke codegen). - a32_idx: [A32_BUCKETS]Range - t32_idx: [T32_BUCKETS]Range - t16_idx: [T16_BUCKETS]Range - t32_sub_idx: [T32_BUCKETS * T32_SUB_BUCKETS]Range - - bucket_list: [dynamic]u16 - defer delete(bucket_list) - - emit_pairs :: proc( - pairs: []A32_Pair, idx: []Range, list: ^[dynamic]u16, - ) { - prev_bucket: i32 = -1 - for p in pairs { - cur_bucket := i32(p.bucket) - if cur_bucket != prev_bucket { - idx[cur_bucket].start = u16(len(list)) - idx[cur_bucket].count = 0 - prev_bucket = cur_bucket - } - append(list, p.entry_idx) - idx[cur_bucket].count += 1 - } - } - emit_pairs(a32_pairs[:], a32_idx[:], &bucket_list) - emit_pairs(t32_pairs[:], t32_idx[:], &bucket_list) - emit_pairs(t16_pairs[:], t16_idx[:], &bucket_list) - emit_pairs(t32_sub_pairs[:], t32_sub_idx[:], &bucket_list) - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_form_idx(&sb, all[:]) - emit_bucket_list(&sb, bucket_list[:]) - emit_range_table(&sb, "DECODE_INDEX_A32", a32_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_T32", t32_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_T16", t16_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_T32_SUB", t32_sub_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - max_a32, max_t32, max_t16: u16 - pop_a32, pop_t32, pop_t16: int - for r in a32_idx { if r.count > max_a32 { max_a32 = r.count }; if r.count > 0 { pop_a32 += 1 } } - for r in t32_idx { if r.count > max_t32 { max_t32 = r.count }; if r.count > 0 { pop_t32 += 1 } } - for r in t16_idx { if r.count > max_t16 { max_t16 = r.count }; if r.count > 0 { pop_t16 += 1 } } - fmt.printfln("OK -- %d entries: A32 %d buckets (max=%d); T32 %d buckets (max=%d); T16 %d buckets (max=%d)", - len(all), pop_a32, max_a32, pop_t32, max_t32, pop_t16, max_t16) -} - -mode_rank :: proc(e: Entry) -> int { - if e.mode == .A32 { return 0 } - if e.is_thumb32 || e.ilen == 4 { return 1 } - return 2 -} - -push_range :: proc(r: ^Range, i: u16) { - if r.count == 0 { r.start = i } - r.count += 1 -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_arm32 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd arm32 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - mode: Mode, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 21) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -DECODE_T32_SUB_BUCKETS :: 32 -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "") - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{.%v, {{.%v, .%v, .%v, .%v}}, {{.%v, .%v, .%v, .%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}}}},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, e.mode, flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: a.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.sets_flags { write(&sb, &first, "sets_flags=true") } - if f.cond_in_28 { write(&sb, &first, "cond_in_28=true") } - if f.branch { write(&sb, &first, "branch=true") } - if f.cond_branch { write(&sb, &first, "cond_branch=true") } - if f.writes_pc { write(&sb, &first, "writes_pc=true") } - if f.thumb32 { write(&sb, &first, "thumb32=true") } - if f.deprecated { write(&sb, &first, "deprecated=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintf(sb, "%s := [%d]Decode_Index{{\n", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintf(sb, "\t0x%02X = {{%d, %d}},\n", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} - -emit_form_idx :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintf(sb, "DECODE_FORM_IDX := [%d]u16{{\n", len(entries)) - for e, i in entries { - if i > 0 && i % 16 == 0 { strings.write_string(sb, "\n") } - fmt.sbprintf(sb, " %d,", e.form_idx) - } - strings.write_string(sb, "\n}\n\n") -} - -emit_bucket_list :: proc(sb: ^strings.Builder, items: []u16) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintf(sb, "DECODE_BUCKET_LIST := [%d]u16{{\n", len(items)) - for v, i in items { - if i > 0 && i % 16 == 0 { strings.write_string(sb, "\n") } - fmt.sbprintf(sb, " %d,", v) - } - strings.write_string(sb, "\n}\n\n") -} diff --git a/core/rexcode/arm32/tools/llvm_per_line.sh b/core/rexcode/arm32/tools/llvm_per_line.sh index 57b22e607..b6d959fa4 100644 --- a/core/rexcode/arm32/tools/llvm_per_line.sh +++ b/core/rexcode/arm32/tools/llvm_per_line.sh @@ -1,4 +1,6 @@ #!/bin/bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # Per-line llvm-mc disassembly wrapper. # # llvm-mc reads the entire stdin as a stream and decodes greedily, so a diff --git a/core/rexcode/arm32/tools/verify_against_llvm.odin b/core/rexcode/arm32/tools/verify_against_llvm.odin index 5f88b4143..da9e76d92 100644 --- a/core/rexcode/arm32/tools/verify_against_llvm.odin +++ b/core/rexcode/arm32/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= diff --git a/core/rexcode/arm64/bitmask.odin b/core/rexcode/arm64/bitmask.odin index ba04ce21c..601106675 100644 --- a/core/rexcode/arm64/bitmask.odin +++ b/core/rexcode/arm64/bitmask.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/decoder.odin b/core/rexcode/arm64/decoder.odin index 271fc3c67..86992aa09 100644 --- a/core/rexcode/arm64/decoder.odin +++ b/core/rexcode/arm64/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 import "../isa" diff --git a/core/rexcode/arm64/decoding_tables.odin b/core/rexcode/arm64/decoding_tables.odin deleted file mode 100644 index c0b43c17a..000000000 --- a/core/rexcode/arm64/decoding_tables.odin +++ /dev/null @@ -1,1248 +0,0 @@ -package rexcode_arm64 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd arm64 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - - -@(rodata) -DECODE_ENTRIES := [1198]Decode_Entry{ - {.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, - {.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, - {.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, - {.SME_ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, - {.SME2_ZIP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, - {.SME2_UZP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, - {.SME2_ZIP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, - {.SME2_UZP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, - {.SME2_LUTI2_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, - {.SME2_LUTI4_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, - {.SME2_LD1B_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1H_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1W_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1D_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, - {.SME2_LD1B_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1H_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1W_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, - {.SME2_LD1D_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, - {.SME2_ST1B_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1H_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1W_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1D_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, - {.SME2_ST1B_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1H_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1W_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, - {.SME2_ST1D_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, - {.SME_FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, - {.SME_FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, - {.SME_BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, - {.SME_BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, - {.SME_SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, - {.SME_SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, - {.SME_SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, - {.SME_SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, - {.SME_UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, - {.SME_UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, - {.SME_UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, - {.SME_UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, - {.SME_USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, - {.SME_SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, - {.SME_MOVA_Z_FROM_TILE, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, - {.SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, - {.SME_LDR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, - {.SME_STR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, - {.SME_LD1B_TILE, {.SME_SLICE_B, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, - {.SME_LD1H_TILE, {.SME_SLICE_H, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, - {.SME_LD1W_TILE, {.SME_SLICE_W, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, - {.SME_LD1D_TILE, {.SME_SLICE_D, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, - {.SME_LD1Q_TILE, {.SME_SLICE_Q, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, - {.SME_ST1B_TILE, {.SME_SLICE_B, .P_REG, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, - {.SME_ST1H_TILE, {.SME_SLICE_H, .P_REG, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, - {.SME_ST1W_TILE, {.SME_SLICE_W, .P_REG, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, - {.SME_ST1D_TILE, {.SME_SLICE_D, .P_REG, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, - {.SME_ST1Q_TILE, {.SME_SLICE_Q, .P_REG, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, - {.SVE_PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, - {.SVE_AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, - {.SVE_AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, - {.SVE_PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, - {.SVE_PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, - {.SVE_REV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, - {.SVE_PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, - {.SVE_PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, - {.SVE_DUP_Z, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, - {.SVE_DUP_Z, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, - {.SVE_DUP_Z, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, - {.SVE_DUP_Z, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, - {.SVE_REV_Z, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, - {.SVE_AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, - {.SVE_AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, - {.SME_RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, - {.SVE_AND_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, - {.SVE_ORR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, - {.SVE_EOR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, - {.SVE_BIC_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, - {.SVE_ZIP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, - {.SVE_ZIP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, - {.SVE_UZP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, - {.SVE_UZP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, - {.SVE_TRN1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, - {.SVE_TRN2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, - {.SVE_SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, - {.SVE_BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, - {.SVE_BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_ADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_SUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_SQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_SQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_SQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, - {.SVE_FADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, - {.SVE_FSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, - {.SVE_FSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMUL_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMUL_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FMUL_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_ZIP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_ZIP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_UZP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_UZP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_TRN1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_TRN2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, - {.SVE_TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, - {.SVE_HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_FMLA_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMLA_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_FMLS_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMLS_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, - {.SVE_INDEX_II, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, - {.SVE_INDEX_IR, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, - {.SVE_INDEX_RI, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, - {.SVE_INDEX_RR, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_PMUL_VEC, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, - {.SVE_BFADD_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_BFSUB_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_BFMUL_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, - {.SVE_BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - {.SVE_FMLA_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, - {.SVE_FMLS_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, - {.SVE_AND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, - {.SVE_BIC_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, - {.SVE_ORR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, - {.SVE_EOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, - {.SVE_NAND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, - {.SVE_NOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, - {.SVE_ORN_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, - {.SVE_SEL_P, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, - {.SVE_ANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, - {.SVE_BICS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, - {.SVE_ORRS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, - {.SVE_EORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_LDR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, - {.SVE_STR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, - {.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_ADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_ADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, - {.SVE_ADD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, - {.SVE_ADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SUBR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_MUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_UMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_UMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, - {.SVE_SDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, - {.SVE_UDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, - {.SVE_UDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_UMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_UMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_SABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_UABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_ASR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_LSL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_LSR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_NEG_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_NEG_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, - {.SVE_NEG_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, - {.SVE_NEG_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_CLZ_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLZ_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_CLZ_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLZ_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_CNT_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, - {.SVE_FADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FDIV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, - {.SVE_FDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, - {.SVE_FDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAXNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAXNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMAXNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMINNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMINNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMINNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, - {.SVE_FABS_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FABS_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FABS_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNEG_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNEG_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNEG_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FSQRT_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSQRT_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FSQRT_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, - {.SVE_LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, - {.SVE_LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, - {.SVE_LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, - {.SVE_LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, - {.SVE_LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_ST1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, - {.SVE_ST1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, - {.SVE_ST1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, - {.SVE_ST1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_LDR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, - {.SVE_STR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, - {.SVE_HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, - {.SVE_PRFB, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, - {.SVE_PRFH, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, - {.SVE_PRFW, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, - {.SVE_PRFD, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, - {.SVE_LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_STNT1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, - {.SVE_STNT1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, - {.SVE_STNT1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, - {.SVE_STNT1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, - {.SVE_EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, - {.SVE_BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, - {.SVE_BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, - {.SVE_LD1B_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, - {.SVE_LD1B_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1H_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, - {.SVE_LD1H_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1W_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, - {.SVE_LD1W_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1D_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1SB_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, - {.SVE_LD1SB_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1SH_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, - {.SVE_LD1SH_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_LD1SW_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_ST1B_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, - {.SVE_ST1B_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_ST1H_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, - {.SVE_ST1H_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_ST1W_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, - {.SVE_ST1W_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, - {.SVE_ST1D_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, - {.LDAR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, - {.LDAR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, - {.STLR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, - {.STLR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, - {.LDARB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, - {.STLRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, - {.LDARH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, - {.STLRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, - {.LDXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.LDXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, - {.STXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.STXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, - {.LDAXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.LDAXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, - {.STLXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, - {.STLXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.LDXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, - {.LDXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, - {.LDAXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, - {.LDAXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, - {.LDXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, - {.STXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, - {.LDAXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, - {.STLXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, - {.LDXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, - {.STXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, - {.LDAXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, - {.STLXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, - {.CAS, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CAS, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, - {.CASA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, - {.CASA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, - {.CASAB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, - {.CASLB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASALB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, - {.CASAH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, - {.CASLH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASALH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, - {.CASPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, - {.CASPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, - {.CASPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CASPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, - {.STXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, - {.STXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, - {.STLXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, - {.STLXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, - {.LDP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, - {.LDP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, - {.STP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, - {.STP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDPSW, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, - {.LDP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, - {.STP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, - {.STP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, - {.LDP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, - {.LDP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, - {.STP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, - {.STP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDPSW_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDPSW_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, - {.LDNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, - {.STNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, - {.STNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, - {.STGP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, - {.MOV_REG, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, - {.MOV_REG, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - {.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, - {.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - {.CMP_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, - {.CMP_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, - {.CMN_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, - {.CMN_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, - {.NEG_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, - {.NEG_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, - {.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, - {.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, - {.CMP_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - {.CMP_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.CMN_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - {.CMN_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.TST_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.TST_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - {.ADD_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, - {.ADD_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, - {.ADDS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, - {.ADDS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, - {.SUB_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, - {.SUB_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, - {.SUBS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, - {.SUBS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, - {.ADD_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, - {.ADD_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, - {.ADDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.ADDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - {.SUB_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, - {.SUB_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, - {.SUBS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.SUBS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - {.AND_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, - {.AND_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, - {.ANDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.ANDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - {.ORR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, - {.ORR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, - {.EOR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, - {.EOR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, - {.BIC_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, - {.BIC_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, - {.BICS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - {.BICS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, - {.ORN_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, - {.ORN_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, - {.EON_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, - {.EON_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, - {.LD1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, - {.ST1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, - {.LD1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, - {.LD1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, - {.ST1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, - {.ST1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, - {.LD1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, - {.ST1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, - {.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, - {.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, - {.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, - {.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, - {.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, - {.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, - {.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, - {.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, - {.NOT_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, - {.NOT_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, - {.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, - {.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, - {.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, - {.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, - {.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, - {.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, - {.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, - {.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, - {.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, - {.ADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, - {.MUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, - {.MUL_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, - {.MUL_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, - {.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, - {.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, - {.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, - {.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, - {.FADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, - {.FSUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, - {.FSUB_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, - {.FSUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, - {.FMUL_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMUL_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, - {.FDIV_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FDIV_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FDIV_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, - {.FMLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, - {.FMLA_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, - {.FMLS_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, - {.FMLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, - {.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, - {.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, - {.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, - {.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, - {.AND_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, - {.ORR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, - {.EOR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, - {.BIC_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, - {.ORN_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, - {.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, - {.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, - {.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, - {.MOV_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, - {.MOV_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, - {.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, - {.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, - {.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, - {.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, - {.FCADD_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, - {.FCADD_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, - {.FCADD_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, - {.FCADD_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, - {.FCMLA_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, - {.FCMLA_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, - {.FCMLA_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, - {.FCMLA_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, - {.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, - {.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, - {.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, - {.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, - {.CMP_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - {.CMP_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, - {.CMN_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - {.CMN_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, - {.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, - {.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, - {.ADD_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, - {.ADD_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, - {.ADDS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - {.ADDS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, - {.SUB_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, - {.SUB_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, - {.SUBS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, - {.SUBS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - {.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, - {.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, - {.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, - {.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, - {.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, - {.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, - {.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, - {.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, - {.LSR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, - {.LSR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, - {.ASR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, - {.ASR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, - {.TST_IMM, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, - {.MOV_BITMASK, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, - {.TST_IMM, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - {.MOV_BITMASK, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, - {.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, - {.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, - {.ROR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, - {.ROR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, - {.AND_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, - {.ANDS_IMM, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, - {.ORR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, - {.EOR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, - {.LSL_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, - {.LSL_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, - {.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, - {.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, - {.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, - {.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, - {.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, - {.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, - {.AND_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, - {.ANDS_IMM, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - {.ORR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, - {.EOR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, - {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, - {.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, - {.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, - {.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, - {.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, - {.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, - {.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, - {.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, - {.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, - {.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, - {.SME_SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, - {.SME_SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, - {.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, - {.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, - {.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, - {.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, - {.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, - {.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, - {.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, - {.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, - {.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, - {.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, - {.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, - {.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, - {.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, - {.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, - {.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, - {.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, - {.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, - {.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, - {.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, - {.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, - {.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, - {.MSR_REG, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, - {.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, - {.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, - {.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, - {.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, - {.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, - {.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, - {.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, - {.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, - {.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, - {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, - {.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, - {.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, - {.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, - {.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, - {.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, - {.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, - {.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, - {.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, - {.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, - {.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, - {.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, - {.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, - {.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, - {.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, - {.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, - {.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, - {.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, - {.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, - {.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, - {.LDAPR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, - {.LDAPR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, - {.LDAPRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, - {.LDAPRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, - {.LDADD, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, - {.LDADD, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDADDA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDADDA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, - {.LDADDL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, - {.LDADDL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDADDAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDADDAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, - {.LDCLR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDCLR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDCLRL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDCLRL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDCLRAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, - {.LDEOR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDEOR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, - {.LDEORA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, - {.LDEORA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDEORL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, - {.LDEORL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDEORAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDEORAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, - {.LDSET, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSET, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, - {.LDSETA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSETA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, - {.LDSETL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, - {.LDSETL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSETAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSETAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, - {.LDSMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDSMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, - {.LDUMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.LDUMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.SWP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.SWP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, - {.SWPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.SWPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, - {.SWPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.SWPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, - {.SWPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, - {.SWPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, - {.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, - {.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, - {.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, - {.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, - {.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, - {.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, - {.LDUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, - {.LDUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, - {.STUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, - {.STUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, - {.LDURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, - {.STURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, - {.LDURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, - {.LDURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, - {.STURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, - {.LDURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, - {.LDURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, - {.STR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, - {.STR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, - {.LDR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, - {.STR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, - {.STR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, - {.STR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, - {.STR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, - {.STG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, - {.ST2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, - {.STZG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, - {.STZ2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, - {.LDGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, - {.STGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, - {.STZGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, - {.LDAPUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, - {.LDAPUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, - {.STLUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, - {.STLUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDAPURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, - {.STLURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, - {.LDAPURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, - {.STLURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, - {.LDAPURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, - {.LDAPURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDAPURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, - {.LDAPURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDAPURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.PRFUM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDRAA, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, - {.LDRAB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, - {.LDRAA_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, - {.LDRAB_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, - {.LDR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, - {.LDR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, - {.STR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, - {.STR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, - {.LDRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, - {.STRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, - {.LDRSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDRSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, - {.LDRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, - {.STRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, - {.LDRSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDRSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, - {.LDRSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, - {.PRFM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDR_LIT, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, - {.LDR_LIT, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, - {.PRFM_LIT, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, - {.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, - {.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, - {.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, - {.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, - {.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, - {.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, - {.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, - {.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, - {.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, - {.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, - {.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, - {.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, - {.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, - {.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, - {.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, - {.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, - {.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, - {.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, - {.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, - {.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, - {.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - {.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, - {.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, - {.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, - {.LSLV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, - {.LSLV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, - {.LSRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, - {.LSRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, - {.ASRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, - {.ASRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, - {.RORV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, - {.RORV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, - {.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, - {.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, - {.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, - {.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, - {.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, - {.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, - {.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, - {.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, - {.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, - {.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, - {.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, - {.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, - {.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, - {.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, - {.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, - {.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, - {.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, - {.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, - {.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, - {.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, - {.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, - {.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, - {.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, - {.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, - {.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, - {.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, - {.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, - {.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, - {.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, - {.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, - {.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, - {.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, - {.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, - {.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, - {.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, - {.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, - {.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, - {.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, - {.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, - {.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, - {.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, - {.LDR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, - {.STR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, - {.FMOV_REG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, - {.FMOV_REG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, - {.FMOV_GEN, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, - {.FMOV_GEN, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, - {.FMOV_GEN, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FMOV_GEN, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, - {.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, - {.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, - {.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, - {.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, - {.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, - {.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, - {.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, - {.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, - {.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, - {.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, - {.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, - {.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, - {.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, - {.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, - {.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, - {.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, - {.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, - {.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, - {.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, - {.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, - {.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, - {.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, - {.FABS_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, - {.FNEG_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, - {.FSQRT_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, - {.FCMP_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, - {.FCMPE_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, - {.FCVT_H_S, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, - {.FCVT_H_D, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, - {.FCVT_S_H, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, - {.FCVT_D_H, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, - {.FMOV_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, - {.SCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, - {.UCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, - {.FCVTZS_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, - {.FCVTZU_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, - {.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, - {.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, - {.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, - {.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, - {.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, - {.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, - {.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, - {.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, - {.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, - {.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, - {.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, - {.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, - {.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, - {.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, - {.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, - {.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, - {.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, - {.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, - {.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, - {.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, - {.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, - {.FADD_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, - {.FSUB_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, - {.FMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, - {.FDIV_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, - {.FNMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, - {.FMAX_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, - {.FMIN_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, - {.FMAXNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, - {.FMINNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, - {.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, - {.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, - {.FCSEL_H, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, - {.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, - {.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, - {.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, - {.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, - {.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, - {.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, - {.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, - {.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, - {.FMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, - {.FMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, - {.FNMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, - {.FNMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, -} - -@(rodata) -DECODE_INDEX_OP0 := [16]Decode_Index{ - 0x00 = {0, 75}, - 0x02 = {75, 379}, - 0x04 = {454, 76}, - 0x05 = {530, 50}, - 0x06 = {580, 8}, - 0x07 = {588, 93}, - 0x08 = {681, 16}, - 0x09 = {697, 34}, - 0x0A = {731, 98}, - 0x0B = {829, 21}, - 0x0C = {850, 150}, - 0x0D = {1000, 84}, - 0x0E = {1084, 13}, - 0x0F = {1097, 101}, -} - diff --git a/core/rexcode/arm64/encoder.odin b/core/rexcode/arm64/encoder.odin index 62abe7a01..ea381edb6 100644 --- a/core/rexcode/arm64/encoder.odin +++ b/core/rexcode/arm64/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= @@ -104,7 +106,7 @@ encode_one_inline :: #force_inline proc( append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, false diff --git a/core/rexcode/arm64/encoding_types.odin b/core/rexcode/arm64/encoding_types.odin index 84f18112e..9f575f34d 100644 --- a/core/rexcode/arm64/encoding_types.odin +++ b/core/rexcode/arm64/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 import "../isa" diff --git a/core/rexcode/arm64/instructions.odin b/core/rexcode/arm64/instructions.odin index 5c5cb7857..2a508009d 100644 --- a/core/rexcode/arm64/instructions.odin +++ b/core/rexcode/arm64/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/mnemonics.odin b/core/rexcode/arm64/mnemonics.odin index 62edcabc0..4934c400e 100644 --- a/core/rexcode/arm64/mnemonics.odin +++ b/core/rexcode/arm64/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/operands.odin b/core/rexcode/arm64/operands.odin index 5a27ef79a..ab8ca89b8 100644 --- a/core/rexcode/arm64/operands.odin +++ b/core/rexcode/arm64/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/printer.odin b/core/rexcode/arm64/printer.odin index 18dfc2f50..1c470c774 100644 --- a/core/rexcode/arm64/printer.odin +++ b/core/rexcode/arm64/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 import "core:strings" diff --git a/core/rexcode/arm64/registers.odin b/core/rexcode/arm64/registers.odin index 17ddaba79..857880864 100644 --- a/core/rexcode/arm64/registers.odin +++ b/core/rexcode/arm64/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/reloc.odin b/core/rexcode/arm64/reloc.odin index 0a343ee7c..09edceed2 100644 --- a/core/rexcode/arm64/reloc.odin +++ b/core/rexcode/arm64/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/sysregs.odin b/core/rexcode/arm64/sysregs.odin index b0da984c7..32522a820 100644 --- a/core/rexcode/arm64/sysregs.odin +++ b/core/rexcode/arm64/sysregs.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64 // ============================================================================= diff --git a/core/rexcode/arm64/encoding_table.odin b/core/rexcode/arm64/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/arm64/encoding_table.odin rename to core/rexcode/arm64/tablegen/encoding_table.odin index 50664ece8..daec6ad10 100644 --- a/core/rexcode/arm64/encoding_table.odin +++ b/core/rexcode/arm64/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_arm64 +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm64_tablegen // ============================================================================= // AArch64 ENCODING_TABLE (v1: base integer + FP scalar) diff --git a/core/rexcode/arm64/tablegen/gen.odin b/core/rexcode/arm64/tablegen/gen.odin new file mode 100644 index 000000000..f8447adb4 --- /dev/null +++ b/core/rexcode/arm64/tablegen/gen.odin @@ -0,0 +1,293 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm64_tablegen + +// ============================================================================= +// AArch64 TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_INDEX_OP0 index table +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run arm64/tablegen # Stage A +// odin run arm64/tablegen/generated # Stage B + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "arm64.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "arm64.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "arm64.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_OP0", "arm64.idx_op0.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + flags: lib.Encoding_Flags, + op0: u8, // bits[28:25] +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("arm64 tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm64_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for mn in Mnemonic { + for f in ENCODING_TABLE[mn] { + op0_static := u8((f.bits >> 25) & 0xF) + op0_mask := u8((f.mask >> 25) & 0xF) + // Enumerate every 4-bit bucket B such that (B & op0_mask) == op0_static. + for b: u8 = 0; b < 16; b += 1 { + if (b & op0_mask) != op0_static { continue } + append(&all, Entry{f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags, b}) + } + } + } + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.op0 != b.op0 { return a.op0 < b.op0 } + ac := bits.count_ones(a.mask); bc := bits.count_ones(b.mask) + if ac != bc { return ac > bc } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + op0_idx: [16]Range + for e, i in all { push(&op0_idx[e.op0], u16(i)) } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm64_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by op0 (bits 28:25).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_OP0", op0_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting (compact, matching arm64's original generator) +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.branch { append(&parts, "branch=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + if f.writes_pc { append(&parts, "writes_pc=true") } + if f.sets_flags { append(&parts, "sets_flags=true") } + if f.is_64 { append(&parts, "is_64=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm64_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_arm64\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "arm64.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "arm64.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "arm64.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "arm64.idx_op0.bin", raw(&DECODE_INDEX_OP0, size_of(DECODE_INDEX_OP0))) +} diff --git a/core/rexcode/arm64/tables.odin b/core/rexcode/arm64/tables.odin new file mode 100644 index 000000000..b7bf2baff --- /dev/null +++ b/core/rexcode/arm64/tables.odin @@ -0,0 +1,62 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_arm64 + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/arm64.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/arm64.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/arm64.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_OP0 := #load("tables/arm64.idx_op0.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/arm64/tables/arm64.encode_forms.bin b/core/rexcode/arm64/tables/arm64.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..19ca350d2ea5689db2427253d012592d61ae925d GIT binary patch literal 23920 zcmZQ%U}m;rU}E85U|?VnWMF9c&%nUQz`_C-n+O&YU}9iIs51nMaWFA3A=GUIi%Bpe zn->TcV_-%$?;==CfCbsSLa-PI3$l41!D14u42;$;3{0Fn3=9knL0~ZkRt6@7*d?%- z02{J8A+Q(&8?w4dU@-x9WOYSgF$Q*Ib)Udu0vrrXUJMLOilAU&5MW?nn9sn#i7Yk& zBF4qQ$jHjT#KI0z$j!i@@SlN!i-C!W4JOtN78Bq`R;LXXsN^2?1nv zT3|5-0c3Tnz+wV|$m+bnVhn=F>P~^h1cZ>(DL~yPgrrUZ>ONs)bx`*SBddeDPXt*V z)O{kz>Y(luMOFuOpD40AsQbhin3>t3ajC$~!0_Nd1A`a?3kwHKtQ#yQAkM&uP^S$R z;}8euD@fWQzwT|#{p9(k5I=0Qzws5#{*NR08+=u#KO+Tz`!8Q&;atU0!SSbRBSd_ zOh6H#t^uY_5uvVu0jf@kfr*h3s#gIjri>74fQhLf#26Mp)u|%H8en2-AUh!OQR6Th z687pyVh5mN8Vrn#3=B*x3=9kc2cj7M{Qu9upuxbz1Q)vn78B4!s1t#y(?qBfIRI6s zg;2);Q>TSc#{g5OjZnt{Q>Tqk#{*NRgHXo;Q>TMa#{yHQixA_0iRppD-iL{W9aNu4 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rexcode_arm64_tests // End-to-end AArch64 pipeline tests: encode -> decode -> print round-trips diff --git a/core/rexcode/arm64/tests/smoke.odin b/core/rexcode/arm64/tests/smoke.odin index 46aafb92a..56bddcb92 100644 --- a/core/rexcode/arm64/tests/smoke.odin +++ b/core/rexcode/arm64/tests/smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_arm64_tests // Spot-check ENCODING_TABLE entries against canonical bit patterns from @@ -15,7 +17,8 @@ import a "../" @(private="file") check :: proc(name: string, m: a.Mnemonic, idx: int, want_bits, want_mask: u32) { - encs := a.ENCODING_TABLE[m] + _run := a.ENCODE_RUNS[u16(m)] + encs := a.ENCODE_FORMS[_run.start:][:_run.count] if idx >= len(encs) { fmt.printfln(" [FAIL] %s: no encoding at idx %d", name, idx) failures += 1 diff --git a/core/rexcode/arm64/tools/dump_verify_input.odin b/core/rexcode/arm64/tools/dump_verify_input.odin index 25611c7e4..95cd082be 100644 --- a/core/rexcode/arm64/tools/dump_verify_input.odin +++ b/core/rexcode/arm64/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -33,7 +35,8 @@ main :: proc() { count := 0 for mn in a.Mnemonic { - for f in a.ENCODING_TABLE[mn] { + _run := a.ENCODE_RUNS[u16(mn)] + for f in a.ENCODE_FORMS[_run.start:][:_run.count] { b0 := u8( f.bits & 0xFF) b1 := u8((f.bits >> 8) & 0xFF) b2 := u8((f.bits >> 16) & 0xFF) diff --git a/core/rexcode/arm64/tools/gen_decode_tables.odin b/core/rexcode/arm64/tools/gen_decode_tables.odin deleted file mode 100644 index 6ac09a025..000000000 --- a/core/rexcode/arm64/tools/gen_decode_tables.odin +++ /dev/null @@ -1,185 +0,0 @@ -package main - -// ============================================================================= -// AArch64 DECODE-TABLE GENERATOR -// ============================================================================= -// -// AArch64 doesn't have a single primary-opcode field; the ARM ARM divides -// the ISA by `op0` at bits[28:25] into 8 top-level encoding classes plus -// SVE/reserved. For v1 we use that 4-bit field directly as a 16-slot -// dispatch index and linear-scan within each bucket. Mask popcount -// descending sort lets the most-specific entry match first. -// -// 16 buckets * ~7 entries average in the v1 table is fine; the densest -// bucket (DPR at op0=x101) holds ~35 entries which is one cache line of -// linear scan -- under 100 cycles per decode worst case. Sub-bucketing -// can be added later if profiling shows it matters. -// -// Run with: cd arm64 && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import a "../" - -Entry :: struct { - mnemonic: a.Mnemonic, - ops: [4]a.Operand_Type, - enc: [4]a.Operand_Encoding, - bits: u32, - mask: u32, - feature: a.Feature, - flags: a.Encoding_Flags, - op0: u8, // bits[28:25] -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating AArch64 decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - // For each encoding, enumerate every op0 bucket (bits 28:25) that - // matches the entry's static pattern. Entries with mask bits *outside* - // the op0 range fixed (e.g. B/BL with mask 0xFC000000 = bits 31:26 - // static, bit 25 part of imm26) replicate across all matching buckets. - for mn in a.Mnemonic { - for f in a.ENCODING_TABLE[mn] { - op0_static := u8((f.bits >> 25) & 0xF) - op0_mask := u8((f.mask >> 25) & 0xF) - // Enumerate every 4-bit bucket B such that (B & op0_mask) == op0_static. - for b: u8 = 0; b < 16; b += 1 { - if (b & op0_mask) != op0_static { continue } - append(&all, Entry{ - mnemonic = mn, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - flags = f.flags, - op0 = b, - }) - } - } - } - - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.op0 != b.op0 { return a.op0 < b.op0 } - ac := bits.count_ones(a.mask) - bc := bits.count_ones(b.mask) - if ac != bc { return ac > bc } - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - op0_idx: [16]Range - for e, i in all { - if op0_idx[e.op0].count == 0 { - op0_idx[e.op0].start = u16(i) - } - op0_idx[e.op0].count += 1 - } - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_range_table(&sb, "DECODE_INDEX_OP0", op0_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - max_bucket: u16 - for r in op0_idx { if r.count > max_bucket { max_bucket = r.count } } - fmt.printfln("OK -- %d entries across 16 op0 buckets; max bucket = %d", - len(all), max_bucket) -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_arm64 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd arm64 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "") - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{.%v, {{.%v, .%v, .%v, .%v}}, {{.%v, .%v, .%v, .%v}}, 0x%08X, 0x%08X, .%v, {{%s}}}},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: a.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.branch { write(&sb, &first, "branch=true") } - if f.cond_branch { write(&sb, &first, "cond_branch=true") } - if f.writes_pc { write(&sb, &first, "writes_pc=true") } - if f.sets_flags { write(&sb, &first, "sets_flags=true") } - if f.is_64 { write(&sb, &first, "is_64=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/arm64/tools/llvm_per_line.sh b/core/rexcode/arm64/tools/llvm_per_line.sh index 57b22e607..b6d959fa4 100644 --- a/core/rexcode/arm64/tools/llvm_per_line.sh +++ b/core/rexcode/arm64/tools/llvm_per_line.sh @@ -1,4 +1,6 @@ #!/bin/bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # Per-line llvm-mc disassembly wrapper. # # llvm-mc reads the entire stdin as a stream and decodes greedily, so a diff --git a/core/rexcode/arm64/tools/verify_against_llvm.odin b/core/rexcode/arm64/tools/verify_against_llvm.odin index ff54a9189..a6fd71602 100644 --- a/core/rexcode/arm64/tools/verify_against_llvm.odin +++ b/core/rexcode/arm64/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= diff --git a/core/rexcode/build.lua b/core/rexcode/build.lua new file mode 100755 index 000000000..05f29cc3b --- /dev/null +++ b/core/rexcode/build.lua @@ -0,0 +1,434 @@ +#!/usr/bin/env luajit +-- rexcode · Brendan Punsky (dotbmp@github), original author + +--[[============================================================================ + rexcode build driver + + Drives the pre-build metaprograms (table generation), validations, and tests + for every `core:rexcode` ISA, with cross-platform (Linux / macOS / Windows) + gating and a clear report. + + USAGE + luajit build.lua # no flags -> this help screen + luajit build.lua all # do everything (gen + check + test), all ISAs + luajit build.lua --gen --isa x86 # only (re)generate x86's tables + luajit build.lua --check --test # validate + test all ISAs (using committed blobs) + luajit build.lua --verify --isa mips # external-tool verification where available + luajit build.lua --list # ISA x task availability for THIS platform + + TASKS + --gen run the two metaprograms: ENCODING_TABLE -> generated Odin -> tables/*.bin + --check `odin check` (compiles against the #loaded blobs) + structural invariants + --test run each ISA's test suite + --verify round-trip against an external assembler/disassembler (llvm-mc, da65, ...) + --idempotent re-run --gen and confirm the generated files + blobs are byte-stable + all shorthand for `--gen --check --test` + + OPTIONS + --isa comma/space-separated ISAs (default: all). e.g. --isa x86,arm64 + --odin compiler to use (default: the in-repo ./odin — it has fixes not in + a released/system odin, so prefer it) + --root rexcode root (default: auto-detected from this script's location) + --no-color disable ANSI color + -h, --help this screen + --list availability matrix for the current platform + + PLATFORM NOTES + * The in-repo compiler must be built first (./build_odin.sh, or build.bat on Windows). + * `--test` for x86 JIT-executes x86-64 machine code, so it only runs on an x86-64 + host; it is skipped (with a message) elsewhere. All other ISAs' tests are portable. + * `--verify` needs the matching external tool in PATH; the retro ISAs use shell + scripts and are skipped on Windows. Missing tools are skipped, never fatal. +============================================================================]]-- + +-- ---------------------------------------------------------------------------- +-- platform +-- ---------------------------------------------------------------------------- +local OS = jit.os -- "Linux" | "OSX" | "Windows" | "BSD" | ... +local ARCH = jit.arch -- "x64" | "x86" | "arm64" | "arm" | ... +local WIN = (OS == "Windows") +local HOST_X64 = (ARCH == "x64") +local EXE = WIN and ".exe" or "" + +local use_color = not WIN or os.getenv("WT_SESSION") ~= nil or os.getenv("ANSICON") ~= nil + +local function paint(code, s) return use_color and ("\27["..code.."m"..s.."\27[0m") or s end +local function bold(s) return paint("1", s) end +local function green(s) return paint("32", s) end +local function red(s) return paint("31", s) end +local function yellow(s)return paint("33", s) end +local function dim(s) return paint("2", s) end + +-- ---------------------------------------------------------------------------- +-- small utilities +-- ---------------------------------------------------------------------------- +local function q(s) return '"' .. s .. '"' end + +-- Run a command; capture combined output; success via a shell-portable sentinel +-- (works in both POSIX sh and Windows cmd, regardless of popen close() quirks). +local function run(cmd) + local p = io.popen(cmd .. " 2>&1 && echo __RX_OK__ || echo __RX_FAIL__") + local out = p:read("*a") or "" + p:close() + local ok = out:match("__RX_OK__%s*$") ~= nil + out = out:gsub("__RX_OK__%s*$", ""):gsub("__RX_FAIL__%s*$", "") + return ok, out +end + +local function file_exists(path) + local f = io.open(path, "rb"); if f then f:close(); return true end; return false +end + +local function read_file(path) + local f = io.open(path, "rb"); if not f then return nil end + local d = f:read("*a"); f:close(); return d +end + +local function cwd() + local p = io.popen(WIN and "cd" or "pwd") + local d = p:read("*l"); p:close() + return (d or "."):gsub("\\", "/") +end + +-- Is a tool present in PATH? +local function have_tool(name) + local probe = WIN and ("where " .. q(name)) or ("command -v " .. q(name)) + local ok = run(probe) + return ok +end + +-- ---------------------------------------------------------------------------- +-- locate the rexcode root and the in-repo compiler +-- ---------------------------------------------------------------------------- +local function script_dir() + local s = (arg and arg[0] or ""):gsub("\\", "/") + return s:match("^(.*)/[^/]*$") or "." +end + +local function find_root(override) + local function ok_root(d) return d and file_exists(d .. "/isa/labels.odin") end + if override then return override end + local sd, here = script_dir(), cwd() + local cands = { sd, here, here .. "/" .. sd, here .. "/core/rexcode", "core/rexcode", "." } + for _, d in ipairs(cands) do if ok_root(d) then return (d:gsub("/%.$","")) end end + return sd -- best effort +end + +-- ---------------------------------------------------------------------------- +-- ISA catalog +-- ---------------------------------------------------------------------------- +-- test_x64: test suite JIT-executes target code -> needs an x86-64 host (x86 only). +-- verify: {tool=, kind="odin"|"sh", harness=} +local ISAS = { + { name="x86", test_x64=true, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="arm32", test_x64=false, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="arm64", test_x64=false, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="mips", test_x64=false, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="riscv", test_x64=false, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="ppc", test_x64=false, verify={tool="llvm-mc", kind="odin", harness="verify_against_llvm.odin"} }, + { name="ppc_vle", test_x64=false, verify={tool="powerpc-eabivle-as", kind="sh", harness="verify_against_vle_as.sh"} }, + { name="rsp", test_x64=false, verify={tool="armips", kind="sh", harness="verify_against_armips.sh"} }, + { name="mos6502", test_x64=false, verify={tool="xa", kind="sh", harness="verify_against_xa.sh"} }, + { name="mos65816", test_x64=false, verify={tool="ca65", kind="sh", harness="verify_against_ca65.sh"} }, +} +local ISA_BY_NAME = {}; for _, a in ipairs(ISAS) do ISA_BY_NAME[a.name] = a end + +-- ---------------------------------------------------------------------------- +-- argument parsing +-- ---------------------------------------------------------------------------- +local function parse_args(argv) + local o = { tasks={}, isas=nil, odin=nil, root=nil, help=false, list=false } + local i = 1 + local function val(flag) + i = i + 1 + if not argv[i] then io.stderr:write("error: "..flag.." needs a value\n"); os.exit(2) end + return argv[i] + end + while argv[i] do + local a = argv[i] + if a == "-h" or a == "--help" then o.help = true + elseif a == "--list" then o.list = true + elseif a == "all" or a == "--all" then o.tasks.gen=true; o.tasks.check=true; o.tasks.test=true + elseif a == "--gen" or a == "--generate" then o.tasks.gen = true + elseif a == "--check" or a == "--validate" then o.tasks.check = true + elseif a == "--test" then o.tasks.test = true + elseif a == "--verify" then o.tasks.verify = true + elseif a == "--idempotent" or a == "--idem" then o.tasks.idempotent = true + elseif a == "--no-color" then use_color = false + elseif a == "--isa" then o.isas = val("--isa") + elseif a == "--odin" then o.odin = val("--odin") + elseif a == "--root" then o.root = val("--root") + elseif a:match("^%-%-isa=") then o.isas = a:sub(7) + elseif a:match("^%-%-odin=") then o.odin = a:sub(8) + elseif a:match("^%-%-root=") then o.root = a:sub(8) + else io.stderr:write("error: unknown argument '"..a.."' (try --help)\n"); os.exit(2) end + i = i + 1 + end + return o +end + +local function selected_isas(spec) + if not spec then local t={}; for _,a in ipairs(ISAS) do t[#t+1]=a end; return t end + local t = {} + for name in spec:gmatch("[%w_]+") do + local a = ISA_BY_NAME[name] + if not a then io.stderr:write("error: unknown ISA '"..name.."'\n"); os.exit(2) end + t[#t+1] = a + end + return t +end + +-- ---------------------------------------------------------------------------- +-- availability for the current platform +-- ---------------------------------------------------------------------------- +-- returns ok(bool), reason(string|nil) +local function avail(isa, task, ctx) + if task == "test" and isa.test_x64 and not HOST_X64 then + return false, "needs x86-64 host (this is "..ARCH..")" + end + if task == "verify" then + local v = isa.verify + if v.kind == "sh" and WIN then return false, v.harness.." (shell script) unsupported on Windows" end + if not ctx.tools[v.tool] then return false, v.tool.." not in PATH" end + end + return true, nil +end + +-- ---------------------------------------------------------------------------- +-- tasks +-- ---------------------------------------------------------------------------- +local ODIN, ROOT, OUT -- set in main + +local function pkg(isa, sub) return ROOT .. "/" .. isa.name .. (sub and ("/"..sub) or "") end + +local function odin_run(target) return q(ODIN).." run "..q(target).." -out:"..q(OUT) end +local function odin_check(target)return q(ODIN).." check "..q(target).." -no-entry-point" end + +-- structural invariants for the migrated layout +local function structural(isa) + local p, bad = pkg(isa), {} + local function must(rel) if not file_exists(p.."/"..rel) then bad[#bad+1]="missing "..rel end end + local function absent(rel) if file_exists(p.."/"..rel) then bad[#bad+1]="stray "..rel end end + must("tables.odin"); must("tablegen/encoding_table.odin"); must("tablegen/gen.odin") + must("tablegen/generated/encode_tables.odin"); must("tablegen/generated/decode_tables.odin") + must("tablegen/generated/writer.odin") + absent("encoding_table.odin"); absent("decoding_tables.odin"); absent("tools/gen_decode_tables.odin") + if #bad == 0 then return true end + return false, table.concat(bad, "; ") +end + +-- blob paths an ISA's tables.odin #loads (parsed from the loader) +local function blob_paths(isa) + local txt = read_file(pkg(isa).."/tables.odin") or "" + local t = {} + for name in txt:gmatch('#load%("(tables/[%w%._%-]+)"') do t[#t+1] = pkg(isa).."/"..name end + return t +end + +local function gen_files(isa) + local t = { pkg(isa).."/tables.odin", + pkg(isa).."/tablegen/generated/encode_tables.odin", + pkg(isa).."/tablegen/generated/decode_tables.odin" } + for _, b in ipairs(blob_paths(isa)) do t[#t+1] = b end + return t +end + +local function do_gen(isa) + local okA, outA = run(odin_run(pkg(isa, "tablegen"))) + if not okA then return false, "Stage A failed:\n"..outA end + local okB, outB = run(odin_run(pkg(isa, "tablegen/generated"))) + if not okB then return false, "Stage B failed:\n"..outB end + -- counts line from Stage A (e.g. "x86 tablegen: 2355 encode forms, ...") + return true, (outA:match("tablegen:%s*(.-)\n") or ""):gsub("%s+$","") +end + +local function do_check(isa) + local s_ok, s_why = structural(isa) + if not s_ok then return false, "structure: "..s_why end + local c_ok, c_out = run(odin_check(pkg(isa))) + if not c_ok then return false, "odin check failed:\n"..(c_out:match("(.-Error:.-)\n") or c_out) end + return true, "structure + compile" +end + +local function do_test(isa) + local ok, out = run(odin_run(pkg(isa, "tests"))) + local fails = out:match("([1-9]%d* failed)") + if not ok or fails then return false, (fails or "test run failed").."\n"..out:sub(-400) end + local cases = out:match("(%d+ cases? validated)") + if not cases then + local n = 0; for p in out:gmatch("(%d+) passed") do n = n + tonumber(p) end + if n > 0 then cases = n .. " passed" end + end + return true, cases or "passed" +end + +local function do_verify(isa) + local v = isa.verify + local cmd + if v.kind == "odin" then + cmd = q(ODIN).." run "..q(pkg(isa, "tools/"..v.harness)).." -file -out:"..q(OUT) + else + cmd = "sh "..q(pkg(isa, "tools/"..v.harness)) + end + local ok, out = run(cmd) + if not ok then return false, "verify failed:\n"..out:sub(-400) end + return true, "matched "..v.tool +end + +local function do_idempotent(isa) + local files = gen_files(isa) + local before = {} + for _, f in ipairs(files) do before[f] = read_file(f) end + local ok, why = do_gen(isa) + if not ok then return false, "re-gen failed: "..why end + local changed = {} + for _, f in ipairs(files) do + if read_file(f) ~= before[f] then changed[#changed+1] = f:match("[^/]+$") end + end + if #changed == 0 then return true, "byte-stable ("..#files.." artifacts)" end + return false, "changed on re-gen: "..table.concat(changed, ", ") +end + +local TASK_FN = { gen=do_gen, check=do_check, test=do_test, verify=do_verify, idempotent=do_idempotent } +local TASK_ORDER = { "gen", "check", "test", "verify", "idempotent" } +local TASK_LABEL = { gen="generate", check="validate", test="test", verify="verify", idempotent="idempotent" } + +-- ---------------------------------------------------------------------------- +-- help / list +-- ---------------------------------------------------------------------------- +local function platform_line() + return ("%s / %s (luajit %s)"):format(OS, ARCH, (jit.version:match("LuaJIT (%S+)") or "?")) +end + +local function print_help(ctx) + print(bold("rexcode build driver") .. " — generate tables, validate, and test the core:rexcode ISAs") + print() + print(" Platform : " .. platform_line()) + local cstat = ctx.odin_ok and green("[found] "..ODIN) or red("[NOT BUILT] expected "..ODIN.." — run ./build_odin.sh") + print(" Compiler : " .. cstat) + print() + print(bold("USAGE")) + print(" luajit build.lua " .. dim("# no flags -> this help")) + print(" luajit build.lua all " .. dim("# everything (gen + check + test), all ISAs")) + print(" luajit build.lua --gen --isa x86 " .. dim("# only regenerate x86's tables")) + print(" luajit build.lua --check --test " .. dim("# validate + test (using committed blobs)")) + print(" luajit build.lua --list " .. dim("# availability matrix for this platform")) + print() + print(bold("TASKS") .. dim(" (availability on " .. OS .. "/" .. ARCH .. ")")) + print(" --gen metaprograms: ENCODING_TABLE -> generated Odin -> tables/*.bin " .. green("all ISAs")) + print(" --check odin check (compiles vs #loaded blobs) + structural invariants " .. green("all ISAs")) + local tnote = HOST_X64 and green("all ISAs") or yellow("x86 skipped (needs x86-64 host)") + print(" --test run each ISA's test suite " .. tnote) + print(" --verify round-trip vs external assembler/disassembler " .. yellow("per-tool (see --list)")) + print(" --idempotent re-run --gen and confirm byte-stable output " .. green("all ISAs")) + print(" all = --gen --check --test") + print() + print(bold("OPTIONS")) + print(" --isa comma/space ISAs (default: all): " .. dim("x86 arm32 arm64 mips riscv ppc ppc_vle rsp mos6502 mos65816")) + print(" --odin compiler (default: in-repo ./odin) --root rexcode root") + print(" --no-color plain output -h, --help this screen --list availability matrix") + print() + print(dim("The in-repo ./odin is required (it has fixes not in released/system odin).")) +end + +local function print_list(ctx) + print(bold("ISA availability on ") .. bold(OS .. "/" .. ARCH)) + print(dim((" %-10s %-7s %-7s %-18s %s"):format("ISA","gen","check","test","verify"))) + for _, isa in ipairs(ISAS) do + local t_ok, t_why = avail(isa, "test", ctx) + local v_ok, v_why = avail(isa, "verify", ctx) + local tcol = t_ok and green("yes") or yellow("skip") + local vcol = v_ok and green("yes ("..isa.verify.tool..")") or yellow("skip: "..(v_why or "?")) + print((" %-10s %-7s %-7s %-18s %s"):format( + isa.name, green("yes"), green("yes"), tcol .. (t_ok and "" or " "..dim(t_why or "")), vcol)) + end +end + +-- ---------------------------------------------------------------------------- +-- main +-- ---------------------------------------------------------------------------- +local function main() + local o = parse_args(arg) + + ROOT = (find_root(o.root)):gsub("/+$","") + ODIN = o.odin or (ROOT .. "/../.." .. "/odin" .. EXE) + -- normalize ../.. once for tidy messages + ODIN = ODIN:gsub("/core/rexcode/%.%./%.%./", "/") + local ctx = { odin_ok = file_exists(ODIN) or o.odin ~= nil, tools = {} } + -- probe each distinct verify tool once + local probed = {} + for _, isa in ipairs(ISAS) do + local tname = isa.verify.tool + if probed[tname] == nil then probed[tname] = have_tool(tname) end + ctx.tools[tname] = probed[tname] + end + + local temp = (WIN and (os.getenv("TEMP") or os.getenv("TMP")) or (os.getenv("TMPDIR") or "/tmp")) or "." + OUT = (temp:gsub("\\","/"):gsub("/+$","")) .. "/rexcode_build" .. EXE + + if o.help then print_help(ctx); return 0 end + if o.list then print_list(ctx); return 0 end + + local tasks = {} + for _, t in ipairs(TASK_ORDER) do if o.tasks[t] then tasks[#tasks+1] = t end end + if #tasks == 0 then print_help(ctx); return 0 end + + if not ctx.odin_ok then + print(red("error: the in-repo compiler was not found at:\n ") .. ODIN) + print("Build it first: " .. (WIN and "build.bat" or "./build_odin.sh") .. + " (or pass --odin ).") + return 2 + end + + local isas = selected_isas(o.isas) + print(bold("rexcode") .. " " .. dim(platform_line()) .. " odin=" .. dim(ODIN)) + print(dim(("tasks: %s isas: %d"):format(table.concat(tasks, " "), #isas))) + + local t0 = os.time() + local results, nfail, nskip = {}, 0, 0 + for _, task in ipairs(tasks) do + print() + print(bold("== " .. TASK_LABEL[task]:upper() .. " ==")) + for _, isa in ipairs(isas) do + results[isa.name] = results[isa.name] or {} + local ok_av, why = avail(isa, task, ctx) + io.write((" %-10s %-11s "):format(isa.name, task)) + io.flush() + if not ok_av then + results[isa.name][task] = "skip"; nskip = nskip + 1 + print(yellow("skip") .. " " .. dim(why)) + else + local ok, detail = TASK_FN[task](isa) + results[isa.name][task] = ok and "ok" or "fail" + if ok then print(green("ok") .. " " .. dim(detail or "")) + else nfail = nfail + 1; print(red("FAIL") .. " " .. (detail or ""):gsub("\n", "\n ")) end + end + end + end + + -- summary matrix + print() + print(bold("== REPORT ==") .. dim((" %ds"):format(os.time() - t0))) + io.write(dim((" %-10s"):format("ISA"))) + for _, t in ipairs(tasks) do io.write(dim(("%-12s"):format(t))) end + print() + for _, isa in ipairs(isas) do + io.write((" %-10s"):format(isa.name)) + for _, t in ipairs(tasks) do + local s = results[isa.name][t] or "--" + local c = (s == "ok" and green("ok")) or (s == "fail" and red("FAIL")) or (s == "skip" and yellow("skip")) or dim("--") + io.write(c .. string.rep(" ", math.max(2, 12 - #s))) + end + print() + end + print() + if nfail == 0 then + print(green(bold("PASS")) .. (" (%d skipped)"):format(nskip)) + return 0 + else + print(red(bold("FAIL")) .. (" %d failed, %d skipped"):format(nfail, nskip)) + return 1 + end +end + +os.exit(main()) diff --git a/core/rexcode/doc.odin b/core/rexcode/doc.odin index 55b32cd82..d22442873 100644 --- a/core/rexcode/doc.odin +++ b/core/rexcode/doc.odin @@ -1,8 +1,10 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + /* # rexcode High-performance multi-architecture instruction encoder/decoder/printer -library written in Odin. Developed by dotbmp/Br. +library written in Odin. Original author: Brendan Punsky (dotbmp@github). ## Architectures @@ -28,8 +30,8 @@ Every package follows the same API contract (see `docs/cross_arch_design.md`). - **Decoder**: disassembles machine code back to structured instructions. - **Printer**: emits assembly text output with optional syntax-highlighting tokens. -- **Table-driven**: O(1) opcode lookup via precomputed encoding/decoding - tables. +- **Table-driven**: O(1) opcode lookup via precomputed encode/decode tables, + serialized to committed binary blobs and `#load`ed into `@(rodata)`. - **Zero allocations** on the hot path: caller provides all buffers. The `isa/` package owns the parts that are the same on every ISA — labels, @@ -38,6 +40,20 @@ formatting helpers. Each architecture package owns its registers, memory model, operand types, mnemonics, encoding tables, and the actual `encode_one`/`decode_one` bytes. +## Encoding tables + +Each arch's `ENCODING_TABLE` (the hand-written single source of truth) lives in +`/tablegen/`, not in the library. A two-stage metaprogram flattens it and +emits committed binary blobs that the library `#load`s into `@(rodata)` at +compile time — no table is built during a normal library build: + +```sh +odin run /tablegen # ENCODING_TABLE -> generated Odin + /tables.odin +odin run /tablegen/generated # -> /tables/.*.bin +``` + +Regenerate after editing `ENCODING_TABLE`. See `docs/table_migration.md`. + ## Performance (x86) With `-o:speed -microarch:native -no-bounds-check`: @@ -133,6 +149,31 @@ for name, id in lm.names { id_to_name[id] = name } x86.print(decoded_insts[:], decoded_info[:], lm.labels[:], label_names = &id_to_name) ``` +## Driver script (`build.lua`) + +`build.lua` (LuaJIT) drives the pre-build metaprograms, validations, and tests +across every ISA, with cross-platform gating (Linux / macOS / Windows) and a +clear report. With no flags it prints help, including what's available on the +current platform. + +```sh +luajit build.lua # help + platform availability +luajit build.lua all # everything: generate -> validate -> test, all ISAs +luajit build.lua --gen --isa x86 # only regenerate one ISA's tables +luajit build.lua --check --test # validate + test the committed tables +luajit build.lua --verify # external-tool round-trip where the tool is installed +luajit build.lua --list # ISA x task availability matrix for this platform +``` + +Tasks: `--gen` (table metaprograms), `--check` (compile + structural invariants), +`--test` (run the suites), `--verify` (round-trip vs `llvm-mc`/`da65`/`ca65`/ +`armips`/…), `--idempotent` (re-gen and confirm byte-stable). Scope with +`--isa `. It uses the in-repo `./odin` — build that first. + +> Gating: x86's `--test` JIT-executes x86-64 code, so it runs only on an x86-64 +> host; `--verify` needs the matching tool in PATH (retro ISAs use shell scripts, +> skipped on Windows). Anything unavailable is skipped with a note, never fatal. + ## Running Tests Each package has its own test suite: @@ -187,12 +228,13 @@ Per-package layout (canonical, enforced by the cross-arch contract): operands.odin # Operand, Memory, Operand_Kind, op_* constructors instructions.odin # Instruction, inst_* builders encoding_types.odin # Encoding, Encoding_Flags, isa re-exports - encoding_table.odin # ENCODING_TABLE: [Mnemonic][]Encoding - decoding_tables.odin # generated dispatch tables + tables.odin # generated: #load()s the binary tables into @(rodata) + accessors + tables/ # committed binary blobs (.*.bin) the library #loads mnemonics.odin # Mnemonic enum (u16, INVALID=0) reloc.odin # Relocation_Type + Relocation + tablegen/ # ENCODING_TABLE (source of truth) + gen.odin metaprogram tests/ # smoke, pipeline_smoke, sweep - tools/ # gen_decode_tables, dump_verify_input, verify_against_* + tools/ # dump_verify_input, verify_against_* ``` ## Cross-architecture API design diff --git a/core/rexcode/docs/cross_arch_design.md b/core/rexcode/docs/cross_arch_design.md index 02b710a86..f0ae3fe12 100644 --- a/core/rexcode/docs/cross_arch_design.md +++ b/core/rexcode/docs/cross_arch_design.md @@ -1,46 +1,40 @@ -# rexcode — Cross-Architecture API Design + -> How to grow rexcode from an x86-only encoder/decoder into a multi-target -> library (x86, RISC-V, ARM64, MIPS, …) **without** flattening every -> architecture to a lowest common denominator and **without** adding +# rexcode — Cross-Architecture Design + +> Why the rexcode family (`x86`, `arm32`, `arm64`, `mips`, `riscv`, `ppc`, +> `ppc_vle`, `rsp`, `mos6502`, `mos65816`) shares one shape **without** +> flattening every ISA to a lowest common denominator and **without** adding > runtime overhead to the single-target hot path. -> -> Companion to [x86_api.md](x86_api.md). Written ahead of the RISC-V -> subpackage. --- -## 0. The guiding principle +## The guiding principle > **Share the bookkeeping, specialize the bytes.** An encoder/decoder is two things stitched together: 1. **Orchestration & bookkeeping** — labels, relocations, the two-pass - encode/decode loops, error/result reporting, the print framework, - buffer management, the table-gen tooling pattern. This is *the same - problem on every ISA* and should be written once. + encode/decode loops, error/result reporting, the print framework, and the + table-gen tooling pattern. This is *the same problem on every ISA*. 2. **The instruction model & the bytes** — what a register/memory/operand - *is*, what the encoding tables look like, and the actual - bit/byte-twiddling of `encode_one`/`decode_one`. This is *irreducibly - per-architecture* and must stay native and zero-cost. + *is*, what the encoding tables look like, and the actual bit/byte-twiddling + of `encode_one`/`decode_one`. This is *irreducibly per-architecture* and + must stay native and zero-cost. -Every decision below follows from drawing the line in exactly that place. -We do **not** try to invent one `Instruction` type that fits all ISAs — -that path forces x86's `segment`/SIB and ARM's writeback and RISC-V's -split immediates into one bloated struct, and it is precisely the -"compromise performance/effectiveness" outcome to avoid. Instead, each -arch owns its concrete types, and uniformity comes from a **naming -contract** (§6) plus a small **shared core** (§4) plus **opt-in** -generic glue (§5, §7). +We do **not** invent one `Instruction` type that fits all ISAs — that path +forces x86's `segment`/SIB, ARM's writeback, and RISC-V's split immediates into +one bloated struct. Instead each arch owns its concrete types, and uniformity +comes from a **naming contract** (§4) plus a small **shared core** (§3). --- ## 1. The universal shape -Strip away the x86 specifics and every target needs the same nine things: +Strip away the specifics and every target needs the same nine things: -| # | Concept | Example in x86 | +| # | Concept | x86 example | |---|---|---| | 1 | A **register** = (class, hw number, size) | `Register` distinct u16 | | 2 | **Operands** tagged reg / mem / imm / relative | `Operand` + `Operand_Kind` | @@ -52,282 +46,123 @@ Strip away the x86 specifics and every target needs the same nine things: | 8 | `decode(bytes) -> []Inst (+info +labels +errors)` | `decode()` | | 9 | `print([]Inst) -> text (+tokens)` | `print()`/`tprint()`/… | -Plus two cross-cutting concerns: **errors/result** reporting and a -**table-driven core** fed by **codegen tooling**. - -The *shape* of items 5–9 (their signatures and the types they pass around) -is architecture-independent. That is the surface we standardize. +The *shape* of items 5–9 (their signatures and the types they pass around) is +architecture-independent. That is the surface the naming contract standardizes. --- ## 2. Where architectures actually diverge -This is the heart of the analysis. Ranked from "diverges hardest" to -"barely diverges." +Ranked from "diverges hardest" to "barely diverges": -### 2.1 Encoding mechanics — **maximal divergence** - -| ISA | Width | Mechanism | -|---|---|---| -| x86 | 1–15 B, variable | legacy prefixes → REX/VEX/EVEX → escape → opcode → ModRM → SIB → disp → imm | -| RISC-V | 4 B (2 B for "C") | pack fixed bitfields; ~6 formats (R/I/S/B/U/J) | -| ARM64 | 4 B fixed | pack per-class bitfields; many classes; bitmask-imm encoder | -| MIPS | 4 B fixed | 3 formats (R/I/J), very regular | - -`encode()`'s ~500-line body and the whole `Encoding`/`Encoding_Flags` -schema (esc/prefix/vex_*) are **x86-only**. RISC-V's `encode_one` is a -dozen lines of shifts. **Conclusion: the `encode_one`/`decode_one` core -and the `Encoding` struct do not generalize — but the loop that drives -them does (§7).** - -### 2.2 Memory addressing — **high divergence** - -| ISA | Addressing modes | -|---|---| -| x86 | `[base + index*scale + disp32]`, RIP-relative, segment override, addr-size override | -| RISC-V | `disp12(base)` only — no index, no scale | -| MIPS | `imm16(base)` only | -| ARM64 | `[base]`, `[base,#imm]`, `[base,Xm{,LSL#n}]`, `[base,Wm,SXTW]`, pre/post-index `[base,#imm]!` / `[base],#imm`, PC-rel literal | - -The x86 `Memory` bit_field (with `segment`, `addr_size_override`, -index+scale) is deeply x86-flavored. RISC-V's memory is `{base, i32 disp}`. -ARM adds **writeback** (a mode x86 cannot express) and extend/shift on the -index. **Conclusion: `Memory` is per-arch.** What generalizes is only the -*role*: a `MEMORY`-kind operand carrying an arch-defined payload. - -### 2.3 Immediates & operand size — **moderate divergence** - -- The *value* (an `i64`) generalizes perfectly. -- The *encoding* does not: RISC-V scatters immediate bits across fields - (B-type, J-type) and shifts them; ARM has bitmask-immediate and shifted - forms. All of that lives inside `encode_one`; the `Operand` just holds - the clean value. -- **Size association differs:** x86 carries an explicit `size: u8` and - uses it to select an encoding; RISC-V/ARM bake width into the mnemonic - (`LW` vs `LD`, `W0` vs `X0`). Keep `size` in the shared operand shape as - a *carrier*; let each arch decide how much it matters. - -### 2.4 Relocations — **moderate divergence (structurally aligned)** - -The `Relocation` *struct* (offset, symbol/label, addend, type, size) -mirrors ELF `rela` and is universal. The *type enum* is per-arch and much -larger on RISC-V (paired `PCREL_HI20`/`PCREL_LO12`, `CALL`, `BRANCH`, -`JAL`, `HI20`, `LO12_I/S`, …) because PC-relative addressing needs -instruction *pairs* (AUIPC+ADDI). **Conclusion: share the struct shape, -make the type enum a per-arch parameter.** - -### 2.5 Registers — **low/structural divergence** - -The `(class, hw_number)`-packed `distinct u16` scheme generalizes well. -What differs: -- x86: REX/EVEX extension bits, AH↔SPL aliasing, RIP pseudo-reg. -- RISC-V: clean 5-bit fields, `x0`=hardwired zero, ABI names - (`zero/ra/sp/gp/tp/t0../s0../a0..`), separate `f`/`v` files. -- ARM64: reg #31 means **SP or XZR depending on instruction** (a - decode/print-time disambiguation x86 never needs); `w`/`x` and - `b/h/s/d/q` views. -**Conclusion: share the *layout convention* + `reg_hw`/`reg_class` -accessors; per-arch owns classes, enums, names, and extension semantics.** - -### 2.6 Mnemonics — **content differs, shape identical** - -Per-arch `enum u16`, `INVALID=0`. Nothing to share but the convention. - -### 2.7 Labels — **no divergence** - -`labels.odin` is pure bookkeeping. The array-index model -(`Label_Definition`, `label`, `label_forward`, `label_set_at`, -`Label_Map`, `label_named`, `label_reserve`, `label_set`) lives in -`isa/labels.odin` and is parametric over the Instruction type. **Fully -shared.** Each arch's `encode()` rewrites label_defs from instruction -indices to byte offsets between pass 1 and pass 2. - -### 2.8 Errors / Result — **low divergence** - -`Result` is universal. `Error` is universal in shape. `Error_Code` splits -into a **shared core** (`NONE, BUFFER_OVERFLOW, INVALID_MNEMONIC, -NO_MATCHING_ENCODING, BUFFER_TOO_SHORT, INVALID_OPCODE, LABEL_OUT_OF_RANGE, -…`) and **arch-specific** extras (`INVALID_MODRM/SIB/VEX/EVEX, -TOO_MANY_PREFIXES` on x86; RISC-V would add `MISALIGNED_IMMEDIATE`, -`INVALID_ROUNDING_MODE`, …). - -### 2.9 Printer — **framework universal, formatting per-arch** - -Shareable: `Token`, `Token_Kind` (the kinds are generic), `Print_Options`, -the builder/number-formatting helpers, and the whole family of output -sinks (`sbprint/print/aprint/tprint/bprint/fprint/wprint` + `ln`). Per-arch: -`register_name`, `print_memory` (syntax differs wildly), -`mnemonic_to_string`, and the size-suffix convention (x86's `.b/.w/.d` is -x86-only; RISC-V puts width in the mnemonic). +- **Encoding mechanics — maximal.** x86 is 1–15 B variable (prefixes → REX/VEX/ + EVEX → escape → opcode → ModRM → SIB → disp → imm); RISC-V/ARM64/MIPS/PPC are + fixed 4 B bitfield packs; the 6502/65816 are 1–N B opcode + operand bytes. + `encode_one`/`decode_one` and the `Encoding` schema do **not** generalize. +- **Memory addressing — high.** x86 `[base+index*scale+disp32]` + segment + + addr-size; RISC-V `disp12(base)`; MIPS `imm16(base)`; ARM adds writeback and + extend/shift. `Memory` is per-arch; only the *role* (a `MEMORY`-kind operand + carrying an arch-defined payload) generalizes. +- **Immediates / operand size — moderate.** The *value* (`i64`) generalizes; the + *encoding* (split B/J immediates, bitmask-imm) lives inside `encode_one`. x86 + carries an explicit `size`; RISC-V/ARM bake width into the mnemonic. +- **Relocations — moderate, structurally aligned.** The `Relocation` struct + (offset, label, addend, type, size) mirrors ELF `rela` and is universal in + *shape*; the **type enum** is per-arch (larger on RISC-V/PPC for paired + PC-relative forms). +- **Registers — low/structural.** The `(class, hw_number)`-packed `distinct u16` + scheme + `reg_hw`/`reg_class` accessors generalize; classes, enums, names, and + extension semantics (REX/EVEX, ARM's SP/XZR #31) are per-arch. +- **Mnemonics — content differs, shape identical.** Per-arch `enum u16`, + `INVALID=0`. +- **Labels — no divergence.** Pure bookkeeping; lives in `isa/`. +- **Errors / Result — low.** `Result`/`Error` shapes universal; `Error_Code` + has a shared core plus arch-specific extras. +- **Printer — framework universal, formatting per-arch.** Tokens, options, and + the output sinks are shared; `register_name`/`print_memory`/mnemonic + formatting are per-arch. ### Divergence summary -| Component | Verdict | What's shared | What's per-arch | +| Component | Verdict | Shared | Per-arch | |---|---|---|---| | Labels | ✅ shared | everything | — | | Result / Error struct | ✅ shared | struct shapes | error-code extras | -| Relocation struct | ✅ shared | struct shape | type enum | | Printer framework | ◑ split | tokens, options, sinks, num-fmt | reg/mem/mnemonic formatting | -| Register scheme | ◑ split | layout + `reg_hw`/`reg_class` | classes, enums, names, ext bits | -| Operand model | ◑ split | kind tag + union discipline + `size` carrier | `Memory`, `flags` payloads | -| Encode/decode **driver** | ◑ shared via generics | two-pass loops, label/reloc resolution | the per-instruction hook | +| Relocation | ◑ split | struct shape (convention) | type enum (per-arch file) | +| Register scheme | ◑ split | layout + `reg_hw`/`reg_class` convention | classes, enums, names, ext bits | +| Operand model | ◑ split | kind tag + `size` carrier convention | `Memory`, `flags` payloads | | `Instruction` | ✗ per-arch | shape convention only | concrete struct | | `Mnemonic` | ✗ per-arch | convention (u16, INVALID=0) | the enum | -| `Encoding` + tables | ✗ per-arch | codegen *pattern* | schema + data | +| `Encoding` + tables | ✗ per-arch | codegen *pattern* (§5) | schema + data | +| `encode`/`decode` driver | ✗ per-arch | — | the whole loop | | `encode_one`/`decode_one` | ✗ per-arch | nothing | all of it | | Memory addressing | ✗ per-arch | operand *role* | the model | --- -## 3. Why not the "obvious" unifications +## 3. The shared core (`isa/`) and why nothing else is shared -Three tempting designs that **violate** the no-compromise rule: +`isa/` depends on nothing and owns only the parts that are byte-for-byte the +same problem on every ISA: -1. **One universal `Operand`/`Memory` for all ISAs.** Forces the union of - x86 SIB+segment, ARM writeback+extend, and RISC-V's nothing into a - single struct. Bloats every operand, leaks `segment` into RISC-V, and - still can't represent ARM writeback cleanly. ✗ +- `labels.odin` — `Label`, `Label_Definition`, `Label_Map`, resolution + (parametric over the Instruction type, so it works for any arch unchanged). +- `label_infer.odin` — branch-target → label inference used by `decode`. +- `status.odin` — `Result`, `Error`, the shared `Error_Code` core. +- `print.odin` — `Token`/`Token_Kind`, `Print_Options`, the output sinks, and + the number-formatting helpers. -2. **A runtime `interface`/vtable the encoder calls per instruction.** - Adds an indirect call to the hottest loop (x86 does ~17 M inst/s — a - per-instruction `proc` pointer is a measurable tax) and defeats - inlining. ✗ on the default path. +Each arch package **re-exports** these (e.g. `x86.Result`, `x86.Label_Map`) so a +consumer sees one coherent namespace and never imports `isa` directly unless +writing arch-generic tooling. -3. **`any`/tagged-union `Instruction` passed through a generic `encode`.** - Same monomorphization loss + runtime type checks in the hot loop. ✗ +Everything else is deliberately **per-arch**, even where it looks shareable: +registers, the memory model, operands, mnemonics, the `Encoding`/table schema, +the `Relocation` type enum, and — notably — the `encode`/`decode` **driver +loops**. The drivers were left native rather than factored behind a generic hook +because they diverge too much to share cleanly (x86's ~500-line prefix/ModRM/SIB +body vs a fixed-width arch's dozen-line bitfield packer), and the hot path must +not pay for indirection. -The design instead gets uniformity from **compile-time** mechanisms -(naming contract + parametric polymorphism), and reserves runtime dispatch -for an **opt-in** facade (§5.3) that only multi-target *tools* pay for. +### Three unifications we deliberately rejected + +1. **One universal `Operand`/`Memory`.** Would force x86 SIB+segment, ARM + writeback+extend, and RISC-V's nothing into one struct — bloats every operand + and still can't represent ARM writeback cleanly. +2. **A runtime `interface`/vtable called per instruction.** Adds an indirect + call to the hottest loop (x86 does ~17 M inst/s) and defeats inlining. +3. **An `any`/tagged-union `Instruction` through a generic `encode`.** Same + monomorphization loss + runtime type checks in the hot loop. --- -## 4. Proposed package layout +## 4. The naming contract -``` -rexcode/ - isa/ # shared, architecture-independent core - labels.odin # Label, Label_Definition, Label_Map, resolution - reloc.odin # Relocation (type field is generic/u8) - status.odin # Result, Error, shared Error_Code core - print.odin # Token, Token_Kind, Print_Options, sinks, num-fmt - register.odin # distinct-u16 layout convention + reg_hw/reg_class - pipeline.odin # parametric encode_stream/decode_stream (§7) - target.odin # optional runtime Target vtable (§5.3) +Every architecture package exposes these names with these signatures. This is +what makes the family feel like one library and what each new ISA is built +against as a checklist. - x86/ # exists today; refactor to import isa - registers.odin operands.odin instructions.odin mnemonics.odin - encoding_types.odin encoder.odin decoder.odin printer.odin - encoding_table.odin decoding_tables.odin mnemonic_builders.odin - tests/ tools/ +**Types (concrete per arch, identical names):** +`Register Memory Operand Operand_Kind Instruction Mnemonic Encoding +Instruction_Info` - riscv/ # next: same shape as x86/ - registers.odin operands.odin instructions.odin mnemonics.odin - encoding_types.odin encoder.odin decoder.odin printer.odin - encoding_table.odin decoding_tables.odin mnemonic_builders.odin - tests/ tools/ +**Re-exported shared types (from `isa`):** +`Label Label_Definition Label_Map LABEL_UNDEFINED Relocation +Relocation_Type Error Error_Code Result Token Token_Kind Print_Options +DEFAULT_PRINT_OPTIONS` - arm64/ mips/ … # future, same template -``` +**Operand constructors:** `op_reg(r) op_mem(m, size) op_imm(v, size) +op_label(id, size)`, an arch-specific `mem_*` set (at minimum `mem_base_disp`), +and `op_(typed)` where the arch has typed register classes. -- **`isa` depends on nothing.** Each arch package depends on `isa` and - **re-exports** the shared types (e.g. `x86.Result`, `x86.Label_Map`) - so a consumer of `x86` sees one coherent namespace and never imports - `isa` directly unless writing arch-generic tooling. -- Each arch package is **self-contained** (its own tests/tools), matching - the move already done for x86. +**Instruction builders & emitters** (operand-kind suffixes spelled out): +`inst_none / inst_r / inst_r_r / inst_r_i / inst_r_m / inst_m_r / …` and +`emit_none / emit_r / emit_rr / emit_ri / …` (concatenated suffixes). x86 also +ships generated typed overloads `inst_` / `emit_`; other +arches may add them. ---- - -## 5. Three layers of generality (pick per use case) - -### 5.1 Layer A — direct single-arch use (default, zero overhead) - -```odin -import "rexcode/x86" -code: [4096]u8 -res := x86.encode(insts[:], labels[:], code[:], &relocs, &errors) -``` -Fully static, fully inlined, exactly as fast as today. **99% of consumers -live here.** - -### 5.2 Layer B — source-portable code via the naming contract - -Because every arch package exposes the *same names with the same -signatures* (§6), code that only touches the shared vocabulary -(`Label_Map`, `encode`, `tprint`, `Result`, `Relocation`) can be written -against `import arch "rexcode/x86"` and re-pointed at `rexcode/riscv` by -changing one import — as long as the arch-specific operand construction is -isolated (e.g. behind your own per-arch helper). Still 100% compile-time, -zero overhead. - -### 5.3 Layer C — runtime multi-target facade (opt-in, for tools) - -For a disassembler or JIT that selects the arch *at runtime*, `isa` -provides a vtable populated by each arch: - -```odin -// isa/target.odin -Target :: struct { - name: string, - decode: proc(data: []u8, out: ^Decoded) -> Result, // bytes → generic Decoded - print: proc(d: ^Decoded, opts: ^Print_Options) -> string, - inst_align: u32, // 1 for x86, 4 for riscv/arm64/mips - max_inst: u32, // 15 for x86, 4 for riscv (8 for C-pairs), 4 for arm64 -} -// each arch: x86.TARGET: isa.Target = { … } -``` -This boundary trades in **bytes and a generic `Decoded` view**, not the -concrete `Instruction`, so it never forces a unified instruction struct. -It carries a proc-pointer indirection — acceptable for a tool that has -already paid a `switch arch` somewhere, and never on Layer A's path. - ---- - -## 6. The naming contract (the most important artifact) - -Every architecture package **MUST** expose these names with these -signatures. This is what makes the family feel like one library and what -the RISC-V implementation is built against as a checklist. - -### Types (concrete per arch, identical names) - -``` -Register Memory Operand Operand_Kind -Instruction Mnemonic Encoding Instruction_Info -``` - -### Re-exported shared types (from `isa`) - -``` -Label Label_Definition Label_Map LABEL_UNDEFINED -Relocation Relocation_Type Error Error_Code Result -Token Token_Kind Print_Options DEFAULT_PRINT_OPTIONS -``` - -### Operand constructors - -``` -op_reg(r) op_mem(m, size) op_imm(v, size) op_label(id, size) -mem_*(…) # arch-specific set; at minimum mem_base_disp - # (mem_base in x86 is an accessor, not a constructor; - # use mem_base_only for the no-displacement case) -op_(typed) # typed safe constructors where the arch has classes -``` - -### Instruction builders & emitters - -Builder names spell out each operand kind separated by underscores -(matches x86's existing convention): - -``` -inst_none / inst_r / inst_r_r / inst_r_i / inst_r_m / inst_m_r / … -emit_none / emit_r / emit_rr / emit_ri / emit_rm / emit_mr / … - # NB: emit_* uses concatenated suffixes (legacy x86 spelling) -inst_(…) / emit_(…) # generated typed overloads -``` - -### Entry points (identical signatures across arches) +**Entry points (identical signatures across arches):** ```odin encode(instructions: []Instruction, label_defs: []Label_Definition, @@ -339,132 +174,36 @@ decode(data: []u8, relocs: []Relocation, label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error) -> Result print/println/aprint/tprint/bprint/fprint/wprint(+ln)( - instructions: []Instruction, inst_info: []Instruction_Info, - label_defs: []Label_Definition, tokens=nil, options=nil, label_names=nil) + instructions: []Instruction, inst_info: []Instruction_Info, + label_defs: []Label_Definition, tokens=nil, options=nil, label_names=nil) ``` -### Register/label/print helpers +**Register/label/print helpers:** `reg_hw reg_class reg_size register_name +mnemonic_to_string label label_forward label_named label_reserve +label_set`. -``` -reg_hw reg_class reg_size register_name mnemonic_to_string -label label_forward label_named label_reserve label_set -``` - -> Anything an arch genuinely lacks (e.g. RISC-V has no `mem_base_index`) -> is simply **absent**, not stubbed. Portable (Layer B) code stays within -> the intersection; arch-aware code uses the extras. +> Anything an arch genuinely lacks (e.g. RISC-V has no `mem_base_index`) is +> simply **absent**, not stubbed. Source-portable code stays within the +> intersection; arch-aware code uses the extras. --- -## 7. Zero-cost code reuse via parametric polymorphism +## 5. Tables -The encode/decode **drivers** are arch-independent control flow. Factor -them into `isa` as procedures generic over the instruction type `$I`, -parameterized by an arch-provided per-instruction hook. Odin monomorphizes -these at compile time → **no runtime cost, real code sharing.** - -```odin -// isa/pipeline.odin (sketch) -encode_stream :: proc( - instructions: []$I, - label_defs: []Label_Definition, - code: []u8, - relocs: ^[dynamic]Relocation, - errors: ^[dynamic]Error, - encode_one: proc(inst: ^I, out: []u8, code_pos: u32, - relocs: ^[dynamic]Relocation, errors: ^[dynamic]Error) -> (n: u32, ok: bool), - resolve := true, - base_address: u64 = 0, -) -> Result { - // PASS 1: for each inst → record offset, call encode_one, advance - // PASS 1.5: rewrite label_defs inst-index → byte-offset (identical on every arch) - // PASS 2: resolve relocations / patch / spill unresolved (identical on every arch) -} -``` - -x86's current `encode()` becomes a thin wrapper that passes its -`encode_one` (the prefix/ModRM/SIB body); RISC-V's wrapper passes its -12-line bitfield packer. The label/relocation machinery — the part that's -easy to get subtly wrong — is written and tested **once**. - -Caveats (arch-specific passes that stay out of the shared driver): -- **RISC-V pseudo-ops** (`li`, `call`, `la`, `j`) expand to 1–2 real - instructions; needs an arch pre-lowering pass. -- **Branch relaxation** (short↔long form) is arch-specific. -- **ARM literal pools / constant islands** are an extra emission phase. - -These plug in *around* the shared driver, not inside it. +The `Encoding` schema and the tables are per-arch, but the table **pipeline** is +a shared pattern. Each arch's hand-written `ENCODING_TABLE` (the single source of +truth) lives in `/tablegen/`, a two-stage metaprogram flattens it and emits +committed binary blobs, and the library `#load`s them into `@(rodata)` — no table +is compiled into the library. See [table_migration.md](table_migration.md). --- -## 8. Concrete RISC-V mapping (RV64GC as the first target) +## 6. One-paragraph summary -What each contract item becomes, to validate the design before coding: - -| Contract item | RISC-V realization | -|---|---| -| `Register` | `distinct u16`, classes `REG_X` (x0–31), `REG_F` (f0–31), `REG_V` (v0–31). No REX/EVEX bits. `x0` semantic = zero. | -| typed enums | `XREG{ZERO,RA,SP,GP,TP,T0,T1,T2,S0,S1,A0..A7,S2..S11,T3..T6}`, `FREG`, `VREG` | -| `Memory` | `struct { base: Register, disp: i32 }` — no index/scale/segment | -| `mem_*` | `mem_base(base)`, `mem_base_disp(base, disp)` only | -| `Operand` | same kind-tagged shape; `size` mostly informational (width is in the mnemonic) | -| `Mnemonic` | `enum u16` — RV32I/64I + M,A,F,D,C,V (`ADDI, LW, LD, BEQ, JAL, AUIPC, FADD_D, …`) | -| `Encoding` | `struct { format: Format, opcode, funct3, funct7: u8, … }`, `Format{R,I,S,B,U,J,R4,…}` | -| `encode_one` | switch on `format`, pack fields, scatter immediate bits | -| `Encoding_Flags` | tiny (e.g. `is_compressible`, `rounding_ok`) vs x86's 11 fields | -| `Relocation_Type` | `R_RISCV_BRANCH, JAL, CALL, PCREL_HI20, PCREL_LO12_I/S, HI20, LO12_I/S, RVC_BRANCH/JUMP, …` | -| `Instruction_Info` | `offset`, `is_compressed: bool`, rounding mode — no prefix/VEX fields | -| printer | `register_name` uses ABI names; `print_memory` emits `disp(base)`; width lives in the mnemonic (no `.b/.w` suffix) | -| tables | `gen_decode_tables` becomes near-trivial: a fixed-field instruction decodes by `(opcode, funct3, funct7)` keys | -| `MAX_INST_SIZE` | `4` (or `8` to cover a compressed pair); `inst_align` = 2 | - -Notable RISC-V-only concerns the design already accommodates: -- **Split immediates** → hidden in `encode_one`; operand stays a clean value. -- **Paired PC-relative relocs** (AUIPC+ADDI) → expressed via the shared - `Relocation` struct with RISC-V's type enum; resolution of the *pair* is - a RISC-V detail layered on the shared reloc list. -- **Compressed (C) extension** → variable 2/4-byte width handled by - `decode_one` returning a length, exactly like x86's variable length — - the shared decode driver already threads instruction length. - -If RISC-V slots cleanly into the contract (it does above), the contract is -sound for the regular fixed-width ISAs (ARM64, MIPS) too. - ---- - -## 9. Recommended next steps - -1. **Stabilize x86 first.** Resolve the constructor-rename drift noted in - [x86_api.md](x86_api.md#known-drift) (tests/README vs `operands.odin`) - so x86 is the clean reference the contract is extracted from. -2. **Extract `isa`** by lifting the *already-arch-independent* files: - `labels.odin`, the `Relocation`/`Error`/`Result` types, and the printer - framework (tokens/options/sinks/number-formatting). Make `x86` - re-export them. This is a low-risk refactor that proves the split. -3. **Add the parametric `encode_stream`/`decode_stream`** to `isa` and - reduce x86's `encode`/`decode` to wrappers. Validate against the - existing test suite (same bytes out). -4. **Write the RISC-V package against the contract** (§6) and the mapping - (§8), reusing `isa` wholesale. Build its `encoding_table.odin` by hand, - then port the two generators. -5. **Only if a runtime-multi-target tool appears**, add the `Target` - vtable (§5.3). Don't build it speculatively. - -The deliverable order matters: every step is independently shippable, and -x86 keeps working (and keeps its performance) throughout. - ---- - -## 10. One-paragraph summary - -Make `isa` own the parts that are the same on every ISA — labels, -relocations, errors/result, the print framework, and (via Odin -parametric polymorphism) the encode/decode driver loops. Make each arch -package own its registers, memory model, operands, mnemonics, encoding -tables, and the actual `encode_one`/`decode_one` bytes. Bind the family -together with a strict **naming contract** so packages are drop-in -swappable at source level with zero runtime cost, and reserve a single -opt-in runtime `Target` vtable for the rare tool that needs to choose an -architecture dynamically. x86 keeps every cycle of its current -performance; RISC-V (and later ARM/MIPS) gets the boring 60% for free and -writes only the 40% that is genuinely its own. +Make `isa` own the parts that are the same on every ISA — labels, errors/result, +and the print framework. Make each arch package own its registers, memory model, +operands, mnemonics, encoding tables, and the actual `encode_one`/`decode_one` +bytes. Bind the family together with a strict **naming contract** so packages are +drop-in swappable at source level with zero runtime cost. x86 keeps every cycle +of its performance; each new ISA gets the boring shared vocabulary for free and +writes only the part that is genuinely its own. diff --git a/core/rexcode/docs/mips_platforms.md b/core/rexcode/docs/mips_platforms.md index b91cc8aa3..327fd9de5 100644 --- a/core/rexcode/docs/mips_platforms.md +++ b/core/rexcode/docs/mips_platforms.md @@ -1,3 +1,5 @@ + + # MIPS targets and extensions — platform catalog > What's worth supporting in `rexcode/mips/` (or a sibling subpackage) and diff --git a/core/rexcode/docs/table_migration.md b/core/rexcode/docs/table_migration.md new file mode 100644 index 000000000..bc69b98fc --- /dev/null +++ b/core/rexcode/docs/table_migration.md @@ -0,0 +1,184 @@ + + +# rexcode — `#load`ed Table Migration (per-arch checklist) + +> Move every arch's encode/decode tables out of the compiled library and into +> committed binary blobs that the library `#load`s into `@(rodata)`. The +> hand-written `ENCODING_TABLE` stays the single source of truth; it just +> moves into a per-arch `tablegen` metaprogram that emits the blobs through a +> human-readable, type-checked intermediate. +> +> **Reference implementations:** `x86/` (CISC, variable-length, 2-D opcode +> index) and `mips/` (fixed-width bits/mask, 1-D bucket index). Read those two +> before doing a new arch — copy whichever paradigm matches. +> +> **Status (2026-06-15): all 10 arches migrated.** This doc now doubles as the +> reference for the table pipeline and for **regenerating** blobs after editing +> an `ENCODING_TABLE` (follow §3, or just the two `odin run` commands in §2). + +--- + +## 0. Prerequisites + +- **Use the in-repo compiler**, not the system `odin`. gingerBill's fix that + lets a `bit_field`-bearing struct const-init under `@(rodata)` across a + package boundary is in this branch's `src/` but not in master/system odin. + Build once: `./build_odin.sh release` → use `./odin` for everything. + (With the system odin, both the original tables *and* the moved SoT fail to + compile with `@(rodata) must have constant initialization`.) + +## 1. End state per arch + +``` +/ + encoding_types.odin UNCHANGED (Encoding, enums, flags, Feature/Mode) + mnemonics.odin UNCHANGED + encoder.odin 1-line edit: ENCODING_TABLE[m] -> encoding_forms(m) + decoder.odin x86: 2-D index -> didx(); fixed-width: NO change + tables.odin NEW (generated): subsidiary types + #load globals + accessors + tables/.*.bin NEW: committed blobs (raw packed struct images) + tablegen/ NEW package rexcode__tablegen — exactly two files: + encoding_table.odin the SoT, moved here, byte-identical but the package clause + gen.odin Stage A driver (+ package-scope aliases) + generated/ machine-written subpackage rexcode__generated: + encode_tables.odin ENCODE_FORMS + ENCODE_RUNS typed literals + decode_tables.odin decode entries + index tables typed literals + writer.odin Stage B main: serialize the globals to ../../tables/*.bin + tools/ gen_decode_tables.odin REMOVED; others rewritten (see §6) + tests/ ENCODING_TABLE references rewritten (see §6) +``` + +Deleted: `encoding_table.odin` (moved), `decoding_tables.odin` (now blobs), +`tools/gen_decode_tables.odin` (superseded by `tablegen/`). + +## 2. The two-stage pipeline + +``` +ENCODING_TABLE (SoT, untouched) + --Stage A (odin run /tablegen)--> generated/*.odin + tables.odin + --Stage B (odin run /tablegen/generated)--> tables/.*.bin + --#load (library build)--> @(rodata) globals +``` + +Stage A emits human-readable, **type-checked** Odin (reusing gingerBill's +`print_enum_buffered`/alignment helpers); Stage B compiles those literals and +dumps their raw bytes. The compiler validates the flattened tables before they +become opaque blobs. + +## 3. Step-by-step + +1. `mkdir -p /tablegen/tables` (well, `/tablegen` and `/tables`). +2. `git mv /encoding_table.odin /tablegen/encoding_table.odin`. + Change **only** its package clause → `package rexcode__tablegen`. + Keep `@(rodata)` and every encoding row byte-identical. +3. `git rm /decoding_tables.odin /tools/gen_decode_tables.odin`. +4. Write `/tablegen/gen.odin` (§4). It needs package-scope aliases so the + moved SoT resolves its top-level type names: + ```odin + Encoding :: lib.Encoding + Mnemonic :: lib.Mnemonic + ``` + **Also alias any package-level constant the SoT references** — grep the SoT: + `grep -oE "=[A-Za-z_][A-Za-z0-9_]*" tablegen/encoding_table.odin | grep -vE "=true|=false" | sort -u` + (x86 needed `PREFIX_66/F3/F2`; mips needed none.) Bare `.ENUM` selectors and + `{field=...}` flag literals need no alias — they infer from field types. +5. Bootstrap so the library compiles before Stage A can run (it imports the + library for types): create empty blobs `for n in ; do : > tables/.$n.bin; done` + (a 0-byte file `#load`s as a len-0 slice), and write a first `tables.odin` + (or let Stage A overwrite a stub). Then `mkdir -p tablegen/generated`. +6. `encoder.odin`: `ENCODING_TABLE[inst.mnemonic]` → `encoding_forms(inst.mnemonic)`. +7. `decoder.odin`: **x86 only** — flatten the `[4][256]` index access + `T[prefix][opcode]` → `didx(T, prefix, opcode)`. Fixed-width index tables are + already 1-D, so the decoder is unchanged. +8. `odin run /tablegen` (Stage A) then `odin run /tablegen/generated` + (Stage B). Stage A should print form/entry counts matching the old + `decoding_tables.odin` array sizes. +9. Rewrite tool/test consumers of the (formerly public) `ENCODING_TABLE` (§6). +10. `odin run /tests` → green. Confirm idempotence (re-run Stage A+B; the + committed files must not change). + +## 4. `gen.odin` anatomy (copy from x86 or mips) + +A single `BLOBS` manifest drives both the loader's `#load` lines and the +writer's dumps, so they can't drift: +```odin +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ {"ENCODE_FORMS",".encode_forms.bin","Encoding"}, ... } +``` +Emitters: +- `emit_encode_tables` — identical on every arch: walk `ENCODING_TABLE` in + `Mnemonic` order → `ENCODE_FORMS: [N]lib.Encoding` + `ENCODE_RUNS: + [lib.Mnemonic]lib.Encode_Run` (run = `{start, count}` into ENCODE_FORMS). +- `emit_decode_tables` — **arch-specific**; port the bucketing from the arch's + old `tools/gen_decode_tables.odin` (Entry struct, sort key, index ranges). +- `emit_writer` — identical: `raw(&G, size_of(G))` → `os.write_entire_file`. +- `emit_loader` — identical shape: emit the subsidiary type defs + a `#load` + line per blob + the accessors. +Use `#directory`-relative output paths so it runs from anywhere. + +`Encode_Run :: struct { start: u32, count: u32 }` (8 B; same footprint as a +padded `{u16,u16}`, no caps). The `encoding_forms`/`didx` accessors are +`@(private, require_results)` — **keep them private**; consumers outside the +package use the public `ENCODE_FORMS`/`ENCODE_RUNS` globals instead. + +## 5. The three decode paradigms + +| Paradigm | Arches | Index tables | decoder.odin | Reference | +|---|---|---|---|---| +| CISC variable | `x86` | 2-D `[4][256]` → load flat `[]Decode_Index`, `didx` | flatten 2-D→`didx` | **x86 (done)** | +| Fixed-width bits/mask | `arm32 arm64 mips riscv ppc ppc_vle rsp` | 1-D bucket arrays | unchanged | **mips (done)** | +| 8-bit opcode/length | `mos6502 mos65816` | 256-entry opcode→entry | unchanged | none yet — by analogy | + +For fixed-width, `Decode_Entry` == `Encoding` shape, so one `write_row` helper +serves both ENCODE_FORMS and DECODE_ENTRIES. Each arch's bucket structure +differs (mips: primary + SPECIAL/REGIMM/COP1/SPECIAL2/SPECIAL3; ppc: primary ++ sub(16384) + bucket_list + form_idx; arm/riscv/rsp/ppc_vle: read their gen). + +## 6. Consumers of the (formerly public) `ENCODING_TABLE` + +`ENCODING_TABLE` was public API. Every `.ENCODING_TABLE[m]` outside the +library becomes: +```odin +_run := .ENCODE_RUNS[u16(m)] +forms := .ENCODE_FORMS[_run.start:][:_run.count] +``` +Sweep with `grep -rn "ENCODING_TABLE\[" ` and hit: +- `tools/dump_verify_input.odin` (every arch), `tools/gen_mnemonic_builders.odin` + + `tools/verify_tables.odin` (x86). +- `tests/smoke.odin`, `tests/sweep.odin`, `tests/full_sweep.odin`, + `tests/decode_sweep.odin` (varies by arch). +Watch for two traps the recompile exposes: +- **2-D index access in tools** (x86 `verify_tables`): `T[prefix][opcode]` → + `T[(int(prefix) << 8) | int(opcode)]` (didx is private). +- **stale field names** (mips `dump_verify_input` used `f.isa`; the field is + `f.feature`) — pre-existing rot, just fix it. + +## 7. `.gitignore` + +The repo ignores `*.bin`, so blobs need a negation (added once, covers all): +``` +!core/rexcode/*/tables/*.bin +``` +`x86/` additionally hits the broad VS-style `x86/` rule, so it also needs +`!/core/rexcode/x86/`. No other arch needs the directory negation. + +## 8. Tests — pre-existing bugs the suite hits once it runs further + +Only **x86** JIT-executes its encoded output, so only x86 needed these (both +fixed in the x86 pass; reuse if another arch adds execution): +- `tests/test.odin alloc_exec` mapped memory R/W only on Linux — add + `virtual.protect(..., {.Read,.Write,.Execute})` so the page is executable. +- `printer.odin` dereferenced a nil `label_names` (`label_names^[k]`); guard + `if label_names != nil`. Check each arch's printer for the same pattern. + +## 9. Done-criteria per arch + +- `/` contains `tables.odin` and **no** `encoding_table.odin` / + `decoding_tables.odin`; `tablegen/` has exactly `encoding_table.odin` + `gen.odin`. +- Stage A counts == old `decoding_tables.odin` array sizes; Stage B blob sizes + == count × `size_of(struct)`. +- `odin run /tests` green; all `tools/*.odin` compile (`odin build T.odin -file`). +- Re-running Stage A+B produces no diff (idempotent). + +> `doc.odin`, `cross_arch_design.md`, and `x86_api.md` were updated to this +> layout when the migration completed. diff --git a/core/rexcode/docs/x86_api.md b/core/rexcode/docs/x86_api.md index b15b3888c..358367e8e 100644 --- a/core/rexcode/docs/x86_api.md +++ b/core/rexcode/docs/x86_api.md @@ -1,3 +1,5 @@ + + # rexcode `x86` — Complete API Extraction > Snapshot of the entire public surface of the `x86` subpackage @@ -6,19 +8,19 @@ > is built against. The package is **table-driven**: a hand-written master encoding table -(`ENCODING_TABLE`) is the single source of truth, from which the decode -tables and the typed builder procedures are *generated*. The runtime is -zero-allocation (caller owns every buffer) and the hot paths are fully -inlined. +(`ENCODING_TABLE`, in `tablegen/`) is the single source of truth, from which the +encode/decode tables (committed binary blobs, `#load`ed into `@(rodata)`) and the +typed builder procedures are *generated*. The runtime is zero-allocation (caller +owns every buffer) and the hot paths are fully inlined. ``` ENCODING_TABLE (hand-written, source of truth) │ ┌───────────────┼────────────────┐ - gen_decode_tables gen_mnemonic_builders + tablegen (2-stage) gen_mnemonic_builders │ │ - decoding_tables.odin mnemonic_builders.odin - (decode() reads these) (typed inst_*/emit_* helpers) + tables/*.bin → tables.odin mnemonic_builders.odin + (#loaded into @(rodata)) (typed inst_*/emit_* helpers) ``` Pipeline at a glance: @@ -131,10 +133,8 @@ MEM_BASE_RIP :: 30 MEM_BASE_NONE :: 31 MEM_INDEX_NONE :: 31 `mem_base_index(base, index, scale)`, `mem_base_index_disp(base, index, scale, disp)`, `mem_rip_disp(disp)`. -> ⚠️ The README and `tests/test.odin` still use the *old* names -> (`mem_base`, `mem_base_displacement`, `mem_base_index_displacement`, -> `mem_rip_relative`). `mem_base` is now an **accessor**, not a -> constructor. See the "Known drift" note at the end. +> ⚠️ `mem_base` is an **accessor** (returns the base `Register`), not a +> constructor — use `mem_base_only` for the no-displacement case. **Accessors:** `mem_scale`, `mem_is_rip_relative`, `mem_has_base`, `mem_has_index` `(Memory) -> …`; `mem_base`, `mem_index` `(Memory) -> Register`. @@ -295,7 +295,7 @@ VEX_Type :: enum u8 { NONE, VEX, EVEX, XOP } VEX_W :: enum u8 { WIG, W0, W1 } VEX_L :: enum u8 { LIG, L0, L1, L2 } -Encoding_Flags :: bit_field u16 { +Encoding_Flags :: bit_field u32 { esc: Escape | 2, prefix: u8 | 2, vex_type: VEX_Type | 2, @@ -307,9 +307,10 @@ Encoding_Flags :: bit_field u16 { lock_ok: bool | 1, rep_ok: bool | 1, modrm_reg_ext: bool | 1, + mode_32_only: bool | 1, } -Encoding :: struct #packed { // 14 bytes — one encoding form +Encoding :: struct #packed { // 16 bytes — one encoding form mnemonic: Mnemonic, ops: [4]Operand_Type, enc: [4]Operand_Encoding, @@ -455,33 +456,41 @@ label_defs: []Label_Definition, …)`. --- -## 10. Generated tables & builders +## 10. Tables & builders -### `encoding_table.odin` (hand-written master) +### `tablegen/encoding_table.odin` (hand-written master — the source of truth) ```odin ENCODING_TABLE: [Mnemonic][]Encoding = { .MOV = { …forms… }, … } ``` -The single source of truth. `encode()` does `ENCODING_TABLE[mnemonic]` -(O(1)) then linear-scans the forms via `encoding_matches_inline`. +Lives in `x86/tablegen/` (a metaprogram package), **not** in the library. A +two-stage pipeline flattens it and serializes committed binary blobs +(`odin run x86/tablegen` → generated Odin + `tables.odin`; then +`odin run x86/tablegen/generated` → `tables/x86.*.bin`). See +[table_migration.md](table_migration.md). -### `decoding_tables.odin` (generated from `ENCODING_TABLE`) +### `tables.odin` (generated — `#load`s the blobs into `@(rodata)`) + +The library compiles no table body; `tables.odin` `#load`s `tables/x86.*.bin` +and defines the subsidiary types + accessors: ```odin -ModRM_Info :: struct #packed { mod, reg, rm: u8, has_sib: bool, disp_size: u8 } -SIB_Info :: struct #packed { /* scale, index, base */ } +Encode_Run :: struct { start: u32, count: u32 } // run into ENCODE_FORMS +ModRM_Info :: struct #packed { mod, reg, rm: u8, has_sib: bool, disp_size: u8 } +SIB_Info :: struct #packed { scale, index, base: u8 } Decode_Entry :: struct { esc: Escape, prefix, opcode, ext: u8, mnemonic: Mnemonic, ops: [4]Operand_Type, enc: [4]Operand_Encoding, flags: Encoding_Flags } VEX_Decode_Entry :: struct { …Decode_Entry fields + vex_w: VEX_W, vex_l: VEX_L } -Decode_Index :: struct { start: u16, count: u8 } // range into entries +Decode_Index :: struct { start: u16, count: u8 } // range into entries -MODRM_TABLE[256], SIB_TABLE[256] -LEGACY_DECODE_ENTRIES[1266], VEX_DECODE_ENTRIES[667], EVEX_DECODE_ENTRIES[418] -DECODE_INDEX_LEGACY[4][256], DECODE_INDEX_ESC_0F/_0F38/_0F3A[4][256] -VEX_INDEX_0F/_0F38/_0F3A[4][256], EVEX_INDEX_0F/_0F38/_0F3A[4][256] +ENCODE_FORMS: []Encoding, ENCODE_RUNS: []Encode_Run // encode via encoding_forms(m) +MODRM_TABLE, SIB_TABLE, LEGACY/VEX/EVEX_DECODE_ENTRIES (1270/667/418) +DECODE_INDEX_* / VEX_INDEX_* / EVEX_INDEX_* ([]Decode_Index, flat 4×256) ``` -`[prefix][opcode] -> Decode_Index` gives O(1) opcode resolution; the +`encode()` does `encoding_forms(mnemonic)` (a run into `ENCODE_FORMS`) then +linear-scans the forms via `encoding_matches_inline`. `decode()` does +`didx(table, prefix, opcode) -> Decode_Index` for O(1) opcode resolution; the small `count` range is scanned for ModR/M-ext, operand-size, or VEX.W/L disambiguation. @@ -505,26 +514,10 @@ with full type checking, no runtime dispatch. | File | Package | Role | |---|---|---| -| `gen_decode_tables.odin` | `main` (`-file`) | walk `ENCODING_TABLE` → emit `decoding_tables.odin` | -| `gen_mnemonic_builders.odin` | `main` (`-file`) | walk `ENCODING_TABLE` → emit `mnemonic_builders.odin` | -| `verify_tables.odin` | `main`, imports `x86 "../"` | check decode tables consistent with `ENCODING_TABLE` | +| `tablegen/gen.odin` | `main` | flatten `ENCODING_TABLE` → generated Odin → `tables/*.bin` (2-stage) | +| `tools/gen_mnemonic_builders.odin` | `main` (`-file`) | walk the encode forms → emit `mnemonic_builders.odin` | +| `tools/verify_tables.odin` | `main`, imports `x86 "../"` | check decode tables consistent with the encode forms | +| `tools/dump_verify_input.odin`, `verify_against_llvm.odin` | `main` | LLVM-mc verification harness | Tests live in `x86/tests/test.odin` (`package x86_tests`, `import x86 "../"`), run with `odin run x86/tests`. - ---- - -## Known drift (pre-existing, not from the move) - -The working tree had uncommitted edits to `operands.odin`/`printer.odin` -that **renamed the memory constructors** but did not update callers: - -- `mem_base_displacement` → `mem_base_disp` -- `mem_base_index_displacement` → `mem_base_index_disp` -- `mem_rip_relative` → `mem_rip_disp` -- `mem_base` repurposed from *constructor* to *accessor* - -Result: the library compiles, but `tests/test.odin` (and the README -examples) reference the old names and currently fail to type-check. -Fixing requires either restoring the old constructor names or sweeping -the tests/README to the new ones — a deliberate decision left to you. diff --git a/core/rexcode/isa/label_infer.odin b/core/rexcode/isa/label_infer.odin index b4e23835c..793f735ba 100644 --- a/core/rexcode/isa/label_infer.odin +++ b/core/rexcode/isa/label_infer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_isa // ============================================================================= diff --git a/core/rexcode/isa/labels.odin b/core/rexcode/isa/labels.odin index 65539e810..b598a39e7 100644 --- a/core/rexcode/isa/labels.odin +++ b/core/rexcode/isa/labels.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_isa // ============================================================================= diff --git a/core/rexcode/isa/print.odin b/core/rexcode/isa/print.odin index b1fb1cc24..90d4b7f56 100644 --- a/core/rexcode/isa/print.odin +++ b/core/rexcode/isa/print.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_isa // ============================================================================= diff --git a/core/rexcode/isa/status.odin b/core/rexcode/isa/status.odin index 044d5e745..9ccff1663 100644 --- a/core/rexcode/isa/status.odin +++ b/core/rexcode/isa/status.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_isa // ============================================================================= diff --git a/core/rexcode/mips/decoder.odin b/core/rexcode/mips/decoder.odin index 04f2a2c6b..3210a512d 100644 --- a/core/rexcode/mips/decoder.odin +++ b/core/rexcode/mips/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips import "../isa" @@ -10,7 +12,7 @@ import "../isa" // // PASS 1 - read each instruction word in the given endianness, dispatch // via the generated tables (DECODE_INDEX_PRIMARY plus the five -// sub-tables in decoding_tables.odin), and emit one Instruction +// sub-tables in tables.odin), and emit one Instruction // + one Instruction_Info. Branch/jump operands are emitted as // RELATIVE-kind operands carrying the *absolute* target byte // offset within the decoded region. diff --git a/core/rexcode/mips/encoder.odin b/core/rexcode/mips/encoder.odin index cb05e674b..04c7913f5 100644 --- a/core/rexcode/mips/encoder.odin +++ b/core/rexcode/mips/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= @@ -142,7 +144,7 @@ encode_one_inline :: #force_inline proc( return 0, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, false diff --git a/core/rexcode/mips/encoding_types.odin b/core/rexcode/mips/encoding_types.odin index 6b1b45dbf..15ee9c450 100644 --- a/core/rexcode/mips/encoding_types.odin +++ b/core/rexcode/mips/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips import "../isa" diff --git a/core/rexcode/mips/instructions.odin b/core/rexcode/mips/instructions.odin index 692a1c5e6..26a4e5357 100644 --- a/core/rexcode/mips/instructions.odin +++ b/core/rexcode/mips/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= diff --git a/core/rexcode/mips/mnemonics.odin b/core/rexcode/mips/mnemonics.odin index a0affe669..ea2bd32c8 100644 --- a/core/rexcode/mips/mnemonics.odin +++ b/core/rexcode/mips/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= diff --git a/core/rexcode/mips/operands.odin b/core/rexcode/mips/operands.odin index 3a1c741d7..a4619efbe 100644 --- a/core/rexcode/mips/operands.odin +++ b/core/rexcode/mips/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= diff --git a/core/rexcode/mips/printer.odin b/core/rexcode/mips/printer.odin index 6111886fc..8f30b60d0 100644 --- a/core/rexcode/mips/printer.odin +++ b/core/rexcode/mips/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips import "core:strings" diff --git a/core/rexcode/mips/registers.odin b/core/rexcode/mips/registers.odin index 4cc15bc5e..4e5e27b4e 100644 --- a/core/rexcode/mips/registers.odin +++ b/core/rexcode/mips/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= diff --git a/core/rexcode/mips/reloc.odin b/core/rexcode/mips/reloc.odin index 9019f0224..b408e779a 100644 --- a/core/rexcode/mips/reloc.odin +++ b/core/rexcode/mips/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips // ============================================================================= diff --git a/core/rexcode/mips/encoding_table.odin b/core/rexcode/mips/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/mips/encoding_table.odin rename to core/rexcode/mips/tablegen/encoding_table.odin index 8466accf8..1ae9c3dd0 100644 --- a/core/rexcode/mips/encoding_table.odin +++ b/core/rexcode/mips/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_mips +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mips_tablegen // ============================================================================= // MIPS ENCODING_TABLE diff --git a/core/rexcode/mips/tablegen/gen.odin b/core/rexcode/mips/tablegen/gen.odin new file mode 100644 index 000000000..fcd301238 --- /dev/null +++ b/core/rexcode/mips/tablegen/gen.odin @@ -0,0 +1,315 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mips_tablegen + +// ============================================================================= +// MIPS TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + primary/SPECIAL/REGIMM/COP1/ +// SPECIAL2/SPECIAL3 index tables +// generated/writer.odin Stage B: serialize those globals to ../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run mips/tablegen # Stage A +// odin run mips/tablegen/generated # Stage B + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "mips.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "mips.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "mips.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_PRIMARY", "mips.idx_primary.bin", "Decode_Index"}, + {"DECODE_INDEX_SPECIAL", "mips.idx_special.bin", "Decode_Index"}, + {"DECODE_INDEX_REGIMM", "mips.idx_regimm.bin", "Decode_Index"}, + {"DECODE_INDEX_COP1", "mips.idx_cop1.bin", "Decode_Index"}, + {"DECODE_INDEX_SPECIAL2", "mips.idx_special2.bin", "Decode_Index"}, + {"DECODE_INDEX_SPECIAL3", "mips.idx_special3.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + flags: lib.Encoding_Flags, + primary_op: u8, + sub_key: u8, +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("mips tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mips_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f in ENCODING_TABLE[m] { + primary := u8((f.bits >> 26) & 0x3F) + sub: u8 + switch primary { + case 0x00, 0x1C, 0x1F: sub = u8(f.bits & 0x3F) + case 0x01: sub = u8((f.bits >> 16) & 0x1F) + case 0x11: sub = u8((f.bits >> 21) & 0x1F) + } + append(&all, Entry{f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags, primary, sub}) + } + } + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } + if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } + ac := bits.count_ones(a.mask); bc := bits.count_ones(b.mask) + if ac != bc { return ac > bc } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + primary_idx: [64]Range + special_idx: [64]Range + regimm_idx: [32]Range + cop1_idx: [32]Range + special2_idx: [64]Range + special3_idx: [64]Range + for e, i in all { + push(&primary_idx[e.primary_op], u16(i)) + switch e.primary_op { + case 0x00: push(&special_idx [e.sub_key], u16(i)) + case 0x01: push(®imm_idx [e.sub_key], u16(i)) + case 0x11: push(&cop1_idx [e.sub_key], u16(i)) + case 0x1C: push(&special2_idx[e.sub_key], u16(i)) + case 0x1F: push(&special3_idx[e.sub_key], u16(i)) + } + } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mips_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by primary opcode + sub-field.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) + emit_range(&sb, "DECODE_INDEX_SPECIAL", special_idx[:]) + emit_range(&sb, "DECODE_INDEX_REGIMM", regimm_idx[:]) + emit_range(&sb, "DECODE_INDEX_COP1", cop1_idx[:]) + emit_range(&sb, "DECODE_INDEX_SPECIAL2", special2_idx[:]) + emit_range(&sb, "DECODE_INDEX_SPECIAL3", special3_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting (compact, matching mips' original generator) +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.delay_slot { append(&parts, "delay_slot=true") } + if f.likely { append(&parts, "likely=true") } + if f.only_64 { append(&parts, "only_64=true") } + if f.writes_hilo { append(&parts, "writes_hilo=true") } + if f.compact { append(&parts, "compact=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mips_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mips\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "mips.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "mips.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "mips.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "mips.idx_primary.bin", raw(&DECODE_INDEX_PRIMARY, size_of(DECODE_INDEX_PRIMARY))) + w(TABLES + "mips.idx_special.bin", raw(&DECODE_INDEX_SPECIAL, size_of(DECODE_INDEX_SPECIAL))) + w(TABLES + "mips.idx_regimm.bin", raw(&DECODE_INDEX_REGIMM, size_of(DECODE_INDEX_REGIMM))) + w(TABLES + "mips.idx_cop1.bin", raw(&DECODE_INDEX_COP1, size_of(DECODE_INDEX_COP1))) + w(TABLES + "mips.idx_special2.bin", raw(&DECODE_INDEX_SPECIAL2, size_of(DECODE_INDEX_SPECIAL2))) + w(TABLES + "mips.idx_special3.bin", raw(&DECODE_INDEX_SPECIAL3, size_of(DECODE_INDEX_SPECIAL3))) +} diff --git a/core/rexcode/mips/tables.odin b/core/rexcode/mips/tables.odin new file mode 100644 index 000000000..4fc5bb27d --- /dev/null +++ b/core/rexcode/mips/tables.odin @@ -0,0 +1,67 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mips + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/mips.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/mips.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/mips.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_PRIMARY := #load("tables/mips.idx_primary.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SPECIAL := #load("tables/mips.idx_special.bin", []Decode_Index) +@(rodata) DECODE_INDEX_REGIMM := #load("tables/mips.idx_regimm.bin", []Decode_Index) +@(rodata) DECODE_INDEX_COP1 := #load("tables/mips.idx_cop1.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SPECIAL2 := #load("tables/mips.idx_special2.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SPECIAL3 := #load("tables/mips.idx_special3.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/mips/tables/mips.encode_forms.bin b/core/rexcode/mips/tables/mips.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..b60d2002a1d345f409128642d065e04b81e9f7c6 GIT binary patch literal 15660 zcmZQ%U}R)uU}j`uP+(wS_|MMphk=0!E~W?<85F-f=>J6uc(F2(^DlZK0NGB7eQFfcPPFbIIe*#G}$VBms_3Bkp-*c1x4{61_mi)F;Fo4VPKF(7Smv00Hp&NWHB9xm@ES$qZrIQ1BjR$ zvX}`(OdeUx0wSisz$nJRzyx**gAD^X3=|m{8KoE)nRr3&14Z#421X@hF%hs{Mr8&@ zDFy~curg56lK;cNsDdme!@vL%Q$-eIfrzOgi7`UO)RDvlpkf+GVuDaHO$Ja}YfQT6*i_L(DnIMZTfQXqQi!FhOnIVg< zfryzSi>-i&Ss;t;fQVT#h%WX}PPOGX9Y661r4xq{;yRQ`c7$N&Efe;66u;9`cLd#e$H;grQ==kg|!9i2+oQfa)10mJqm@F32D341btdLg8Y1aIrABm_A%A z9Jy>t0QrrHB?4J21tJy+4=Wjv-v11Ln0TV#VzO|tXt;Q*B5?lBwRk5U~tou^fn4CbHNZh*%b~*dK^kHnP|Th*%D? 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Drives encode -> decode round-trips and checks diff --git a/core/rexcode/mips/tests/encode_smoke.odin b/core/rexcode/mips/tests/encode_smoke.odin index 05777c43b..393ef77dd 100644 --- a/core/rexcode/mips/tests/encode_smoke.odin +++ b/core/rexcode/mips/tests/encode_smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips_tests // Encoder smoke tests. Exercises encode() end-to-end across all the diff --git a/core/rexcode/mips/tests/print_smoke.odin b/core/rexcode/mips/tests/print_smoke.odin index 6de63a5ee..f346a38c6 100644 --- a/core/rexcode/mips/tests/print_smoke.odin +++ b/core/rexcode/mips/tests/print_smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips_tests // Printer smoke tests. Encode a stream, decode it, print it, and check the diff --git a/core/rexcode/mips/tests/smoke.odin b/core/rexcode/mips/tests/smoke.odin index 31d9ac447..66f1c41d6 100644 --- a/core/rexcode/mips/tests/smoke.odin +++ b/core/rexcode/mips/tests/smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mips_tests // Spot-check that ENCODING_TABLE entries are present and have the @@ -14,7 +16,8 @@ import mips "../" @(private="file") failures := 0 check :: proc(name: string, m: mips.Mnemonic, want_bits, want_mask: u32) { - encs := mips.ENCODING_TABLE[m] + r := mips.ENCODE_RUNS[u16(m)] + encs := mips.ENCODE_FORMS[r.start:][:r.count] if len(encs) == 0 { fmt.printfln(" [FAIL] %s: no encoding in table", name) failures += 1 diff --git a/core/rexcode/mips/tools/dump_verify_input.odin b/core/rexcode/mips/tools/dump_verify_input.odin index c87f17857..8ba049e1f 100644 --- a/core/rexcode/mips/tools/dump_verify_input.odin +++ b/core/rexcode/mips/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -31,14 +33,15 @@ main :: proc() { count := 0 for mn in m.Mnemonic { - for f in m.ENCODING_TABLE[mn] { + _run := m.ENCODE_RUNS[u16(mn)] + for f in m.ENCODE_FORMS[_run.start:][:_run.count] { b3 := u8((f.bits >> 24) & 0xFF) b2 := u8((f.bits >> 16) & 0xFF) b1 := u8((f.bits >> 8) & 0xFF) b0 := u8( f.bits & 0xFF) // MIPS big-endian byte order: most-significant byte first fmt.sbprintf(&hex_buf, "0x%02x,0x%02x,0x%02x,0x%02x\n", b3, b2, b1, b0) - fmt.sbprintf(&meta_buf, "%v\t%08x\t%08x\t%v\n", mn, f.bits, f.mask, f.isa) + fmt.sbprintf(&meta_buf, "%v\t%08x\t%08x\t%v\n", mn, f.bits, f.mask, f.feature) count += 1 } } diff --git a/core/rexcode/mips/tools/gen_decode_tables.odin b/core/rexcode/mips/tools/gen_decode_tables.odin deleted file mode 100644 index ddefd3fbc..000000000 --- a/core/rexcode/mips/tools/gen_decode_tables.odin +++ /dev/null @@ -1,246 +0,0 @@ -package main - -// ============================================================================= -// MIPS DECODE-TABLE GENERATOR -// ============================================================================= -// -// Walks the encoder's ENCODING_TABLE (the single source of truth) and emits -// `decoding_tables.odin` -- a flat Decode_Entry array plus a hierarchical set -// of Decode_Index tables so the runtime decoder can pinpoint candidate -// entries in O(1) average and never scan more than a handful of forms. -// -// Run with: cd mips && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin (current working directory) -// -// Dispatch tree (top to bottom): -// -// primary = bits[31:26] -- 64 buckets, indexed by primary opcode -// -// For the five dense primary opcodes we add a secondary table: -// -// 0x00 SPECIAL -> DECODE_INDEX_SPECIAL [funct=bits[5:0]] -// 0x01 REGIMM -> DECODE_INDEX_REGIMM [rt=bits[20:16]] -// 0x11 COP1 -> DECODE_INDEX_COP1 [rs(fmt)=bits[25:21]] -// 0x1C SPECIAL2 -> DECODE_INDEX_SPECIAL2 [funct=bits[5:0]] -// 0x1F SPECIAL3 -> DECODE_INDEX_SPECIAL3 [funct=bits[5:0]] -// -// Everything else (J-type, normal I-type, COP0, COP2) sits in -// DECODE_INDEX_PRIMARY and is linearly scanned within its primary bucket -// (worst case ~25 entries for COP2/GTE). -// -// Within every Decode_Index range, entries are sorted by mask-popcount -// descending so the most-specific encoding form is checked first. That -// makes the linear scan return the right answer when an instruction -// would match both a strict form (e.g. NOP = SLL $0,$0,0) and a relaxed -// one (general SLL). - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import mips "../" - -Entry :: struct { - mnemonic: mips.Mnemonic, - ops: [4]mips.Operand_Type, - enc: [4]mips.Operand_Encoding, - bits: u32, - mask: u32, - feature: mips.Feature, - flags: mips.Encoding_Flags, - primary_op: u8, - sub_key: u8, -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating MIPS decoder tables from ENCODING_TABLE...") - - // ---- 1. Collect all encoding forms ------------------------------------ - all: [dynamic]Entry - defer delete(all) - - for mnem in mips.Mnemonic { - forms := mips.ENCODING_TABLE[mnem] - for f in forms { - primary := u8((f.bits >> 26) & 0x3F) - sub: u8 - switch primary { - case 0x00, 0x1C, 0x1F: - sub = u8(f.bits & 0x3F) // funct - case 0x01: - sub = u8((f.bits >> 16) & 0x1F) // rt - case 0x11: - sub = u8((f.bits >> 21) & 0x1F) // rs (fmt) - } - append(&all, Entry{ - mnemonic = mnem, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - flags = f.flags, - primary_op = primary, - sub_key = sub, - }) - } - } - - // ---- 2. Sort: primary asc, sub_key asc, mask-popcount desc ----------- - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } - if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } - ac := bits.count_ones(a.mask) - bc := bits.count_ones(b.mask) - if ac != bc { return ac > bc } - // Stable tie-break by mnemonic for reproducible output. - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - // ---- 3. Compute indexes ------------------------------------------------ - primary_idx: [64]Range - special_idx: [64]Range - regimm_idx: [32]Range - cop1_idx: [32]Range - special2_idx: [64]Range - special3_idx: [64]Range - - for e, i in all { - push_range(&primary_idx[e.primary_op], u16(i)) - - switch e.primary_op { - case 0x00: push_range(&special_idx [e.sub_key], u16(i)) - case 0x01: push_range(®imm_idx [e.sub_key], u16(i)) - case 0x11: push_range(&cop1_idx [e.sub_key], u16(i)) - case 0x1C: push_range(&special2_idx[e.sub_key], u16(i)) - case 0x1F: push_range(&special3_idx[e.sub_key], u16(i)) - } - } - - // ---- 4. Emit the file -------------------------------------------------- - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - fmt.sbprintfln(&sb, "") - emit_range_table(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SPECIAL", special_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_REGIMM", regimm_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_COP1", cop1_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SPECIAL2", special2_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SPECIAL3", special3_idx[:]) - - output := strings.to_string(sb) - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)output) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - // Stats for the human. - total := len(all) - max_primary, max_special, max_regimm, max_cop1, max_special2, max_special3: u16 - for r in primary_idx { if r.count > max_primary { max_primary = r.count } } - for r in special_idx { if r.count > max_special { max_special = r.count } } - for r in regimm_idx { if r.count > max_regimm { max_regimm = r.count } } - for r in cop1_idx { if r.count > max_cop1 { max_cop1 = r.count } } - for r in special2_idx { if r.count > max_special2 { max_special2 = r.count } } - for r in special3_idx { if r.count > max_special3 { max_special3 = r.count } } - - fmt.printfln("OK -- %d entries", total) - fmt.printfln(" max bucket sizes: primary=%d special=%d regimm=%d cop1=%d special2=%d special3=%d", - max_primary, max_special, max_regimm, max_cop1, max_special2, max_special3) -} - -push_range :: proc(r: ^Range, i: u16) { - if r.count == 0 { r.start = i } - r.count += 1 -} - -// ============================================================================= -// emit helpers -// ============================================================================= - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_mips - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd mips && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 - bits: u32, // 4 - mask: u32, // 4 - feature: Feature, // 1 - flags: Encoding_Flags, // 1 -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "") - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, flags_str) - } - strings.write_string(sb, "}") -} - -encode_flags_literal :: proc(f: mips.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.delay_slot { write(&sb, &first, "delay_slot=true") } - if f.likely { write(&sb, &first, "likely=true") } - if f.only_64 { write(&sb, &first, "only_64=true") } - if f.writes_hilo { write(&sb, &first, "writes_hilo=true") } - if f.compact { write(&sb, &first, "compact=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/mips/tools/llvm_per_line.sh b/core/rexcode/mips/tools/llvm_per_line.sh index 57b22e607..b6d959fa4 100644 --- a/core/rexcode/mips/tools/llvm_per_line.sh +++ b/core/rexcode/mips/tools/llvm_per_line.sh @@ -1,4 +1,6 @@ #!/bin/bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # Per-line llvm-mc disassembly wrapper. # # llvm-mc reads the entire stdin as a stream and decodes greedily, so a diff --git a/core/rexcode/mips/tools/verify_against_llvm.odin b/core/rexcode/mips/tools/verify_against_llvm.odin index bc8394919..191e3bb5c 100644 --- a/core/rexcode/mips/tools/verify_against_llvm.odin +++ b/core/rexcode/mips/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main import "core:fmt" diff --git a/core/rexcode/mos6502/decoder.odin b/core/rexcode/mos6502/decoder.odin index b9b948103..4e1327fe2 100644 --- a/core/rexcode/mos6502/decoder.odin +++ b/core/rexcode/mos6502/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 import "../isa" diff --git a/core/rexcode/mos6502/decoding_tables.odin b/core/rexcode/mos6502/decoding_tables.odin deleted file mode 100644 index c998025c2..000000000 --- a/core/rexcode/mos6502/decoding_tables.odin +++ /dev/null @@ -1,608 +0,0 @@ -package rexcode_mos6502 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd mos6502 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [3]Operand_Type, - enc: [3]Operand_Encoding, - opcode: u8, - length: u8, - cpu: CPU, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 12) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - - -@(rodata) -DECODE_ENTRIES := [321]Decode_Entry{ - {.BRK, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x00, 1, .NMOS, {branch=true}}, - {.ORA, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x01, 2, .NMOS, {}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x02, 1, .NMOS_UNDOC, {}}, - {.SXY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x02, 1, .HUC6280, {}}, - {.SLO, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x03, 2, .NMOS_UNDOC, {}}, - {.ST0, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x03, 2, .HUC6280, {}}, - {.DOP, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x04, 2, .NMOS_UNDOC, {}}, - {.TSB, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x04, 2, .CMOS_65C02, {}}, - {.ORA, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x05, 2, .NMOS, {}}, - {.ASL, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x06, 2, .NMOS, {}}, - {.SLO, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x07, 2, .NMOS_UNDOC, {}}, - {.RMB0, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x07, 2, .CMOS_65C02, {}}, - {.PHP, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x08, 1, .NMOS, {}}, - {.ORA, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x09, 2, .NMOS, {}}, - {.ASL, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x0A, 1, .NMOS, {}}, - {.ANC, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x0B, 2, .NMOS_UNDOC, {}}, - {.TOP, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x0C, 3, .NMOS_UNDOC, {}}, - {.TSB, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x0C, 3, .CMOS_65C02, {}}, - {.ORA, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x0D, 3, .NMOS, {}}, - {.ASL, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x0E, 3, .NMOS, {}}, - {.SLO, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x0F, 3, .NMOS_UNDOC, {}}, - {.BBR0, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x0F, 3, .CMOS_65C02, {cond_branch=true}}, - {.BPL, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x10, 2, .NMOS, {cond_branch=true}}, - {.ORA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x11, 2, .NMOS, {page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x12, 1, .NMOS_UNDOC, {}}, - {.ORA, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x12, 2, .CMOS_65C02, {}}, - {.SLO, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x13, 2, .NMOS_UNDOC, {}}, - {.ST1, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x13, 2, .HUC6280, {}}, - {.DOP, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x14, 2, .NMOS_UNDOC, {}}, - {.TRB, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x14, 2, .CMOS_65C02, {}}, - {.ORA, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x15, 2, .NMOS, {}}, - {.ASL, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x16, 2, .NMOS, {}}, - {.SLO, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x17, 2, .NMOS_UNDOC, {}}, - {.RMB1, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x17, 2, .CMOS_65C02, {}}, - {.CLC, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x18, 1, .NMOS, {}}, - {.ORA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x19, 3, .NMOS, {page_cross=true}}, - {.INC, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x1A, 1, .CMOS_65C02, {}}, - {.INA, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x1A, 1, .CMOS_65C02, {}}, - {.SLO, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1B, 3, .NMOS_UNDOC, {}}, - {.TOP, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1C, 3, .NMOS_UNDOC, {page_cross=true}}, - {.TRB, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1C, 3, .CMOS_65C02, {}}, - {.ORA, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1D, 3, .NMOS, {page_cross=true}}, - {.ASL, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1E, 3, .NMOS, {}}, - {.SLO, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x1F, 3, .NMOS_UNDOC, {}}, - {.BBR1, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x1F, 3, .CMOS_65C02, {cond_branch=true}}, - {.JSR, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x20, 3, .NMOS, {branch=true}}, - {.AND, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x21, 2, .NMOS, {}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x22, 1, .NMOS_UNDOC, {}}, - {.SAX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x22, 1, .HUC6280, {}}, - {.RLA, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x23, 2, .NMOS_UNDOC, {}}, - {.ST2, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x23, 2, .HUC6280, {}}, - {.BIT, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x24, 2, .NMOS, {}}, - {.AND, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x25, 2, .NMOS, {}}, - {.ROL, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x26, 2, .NMOS, {}}, - {.RLA, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x27, 2, .NMOS_UNDOC, {}}, - {.RMB2, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x27, 2, .CMOS_65C02, {}}, - {.PLP, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x28, 1, .NMOS, {}}, - {.AND, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x29, 2, .NMOS, {}}, - {.ROL, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x2A, 1, .NMOS, {}}, - {.ANC, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x2B, 2, .NMOS_UNDOC, {}}, - {.BIT, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x2C, 3, .NMOS, {}}, - {.AND, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x2D, 3, .NMOS, {}}, - {.ROL, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x2E, 3, .NMOS, {}}, - {.RLA, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x2F, 3, .NMOS_UNDOC, {}}, - {.BBR2, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x2F, 3, .CMOS_65C02, {cond_branch=true}}, - {.BMI, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x30, 2, .NMOS, {cond_branch=true}}, - {.AND, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x31, 2, .NMOS, {page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x32, 1, .NMOS_UNDOC, {}}, - {.AND, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x32, 2, .CMOS_65C02, {}}, - {.RLA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x33, 2, .NMOS_UNDOC, {}}, - {.BIT, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x34, 2, .CMOS_65C02, {}}, - {.AND, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x35, 2, .NMOS, {}}, - {.ROL, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x36, 2, .NMOS, {}}, - {.RLA, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x37, 2, .NMOS_UNDOC, {}}, - {.RMB3, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x37, 2, .CMOS_65C02, {}}, - {.SEC, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x38, 1, .NMOS, {}}, - {.AND, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x39, 3, .NMOS, {page_cross=true}}, - {.DEC, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x3A, 1, .CMOS_65C02, {}}, - {.DEA, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x3A, 1, .CMOS_65C02, {}}, - {.RLA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x3B, 3, .NMOS_UNDOC, {}}, - {.BIT, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x3C, 3, .CMOS_65C02, {page_cross=true}}, - {.AND, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x3D, 3, .NMOS, {page_cross=true}}, - {.ROL, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x3E, 3, .NMOS, {}}, - {.RLA, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x3F, 3, .NMOS_UNDOC, {}}, - {.BBR3, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x3F, 3, .CMOS_65C02, {cond_branch=true}}, - {.RTI, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x40, 1, .NMOS, {branch=true}}, - {.EOR, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x41, 2, .NMOS, {}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x42, 1, .NMOS_UNDOC, {}}, - {.SAY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x42, 1, .HUC6280, {}}, - {.SRE, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x43, 2, .NMOS_UNDOC, {}}, - {.TMA, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x43, 2, .HUC6280, {}}, - {.BSR, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x44, 2, .HUC6280, {branch=true}}, - {.EOR, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x45, 2, .NMOS, {}}, - {.LSR, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x46, 2, .NMOS, {}}, - {.SRE, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x47, 2, .NMOS_UNDOC, {}}, - {.RMB4, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x47, 2, .CMOS_65C02, {}}, - {.PHA, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x48, 1, .NMOS, {}}, - {.EOR, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x49, 2, .NMOS, {}}, - {.LSR, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x4A, 1, .NMOS, {}}, - {.ALR, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x4B, 2, .NMOS_UNDOC, {}}, - {.JMP, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x4C, 3, .NMOS, {branch=true}}, - {.EOR, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x4D, 3, .NMOS, {}}, - {.LSR, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x4E, 3, .NMOS, {}}, - {.SRE, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x4F, 3, .NMOS_UNDOC, {}}, - {.BBR4, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x4F, 3, .CMOS_65C02, {cond_branch=true}}, - {.BVC, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x50, 2, .NMOS, {cond_branch=true}}, - {.EOR, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x51, 2, .NMOS, {page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x52, 1, .NMOS_UNDOC, {}}, - {.EOR, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x52, 2, .CMOS_65C02, {}}, - {.SRE, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x53, 2, .NMOS_UNDOC, {}}, - {.TAM, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x53, 2, .HUC6280, {}}, - {.CSL, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x54, 1, .HUC6280, {}}, - {.EOR, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x55, 2, .NMOS, {}}, - {.LSR, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x56, 2, .NMOS, {}}, - {.SRE, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x57, 2, .NMOS_UNDOC, {}}, - {.RMB5, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x57, 2, .CMOS_65C02, {}}, - {.CLI, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x58, 1, .NMOS, {}}, - {.EOR, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x59, 3, .NMOS, {page_cross=true}}, - {.PHY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x5A, 1, .CMOS_65C02, {}}, - {.SRE, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x5B, 3, .NMOS_UNDOC, {}}, - {.EOR, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x5D, 3, .NMOS, {page_cross=true}}, - {.LSR, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x5E, 3, .NMOS, {}}, - {.SRE, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x5F, 3, .NMOS_UNDOC, {}}, - {.BBR5, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x5F, 3, .CMOS_65C02, {cond_branch=true}}, - {.RTS, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x60, 1, .NMOS, {branch=true}}, - {.ADC, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x61, 2, .NMOS, {decimal=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x62, 1, .NMOS_UNDOC, {}}, - {.CLA, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x62, 1, .HUC6280, {}}, - {.RRA, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x63, 2, .NMOS_UNDOC, {decimal=true}}, - {.STZ, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x64, 2, .CMOS_65C02, {}}, - {.ADC, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x65, 2, .NMOS, {decimal=true}}, - {.ROR, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x66, 2, .NMOS, {}}, - {.RRA, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x67, 2, .NMOS_UNDOC, {decimal=true}}, - {.RMB6, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x67, 2, .CMOS_65C02, {}}, - {.PLA, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x68, 1, .NMOS, {}}, - {.ADC, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x69, 2, .NMOS, {decimal=true}}, - {.ROR, {.A_IMPL, .NONE, .NONE}, {.IMPL, .NONE, .NONE}, 0x6A, 1, .NMOS, {}}, - {.ARR, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x6B, 2, .NMOS_UNDOC, {decimal=true}}, - {.JMP, {.MEM_IND, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x6C, 3, .NMOS, {branch=true}}, - {.ADC, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x6D, 3, .NMOS, {decimal=true}}, - {.ROR, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x6E, 3, .NMOS, {}}, - {.RRA, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x6F, 3, .NMOS_UNDOC, {decimal=true}}, - {.BBR6, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x6F, 3, .CMOS_65C02, {cond_branch=true}}, - {.BVS, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x70, 2, .NMOS, {cond_branch=true}}, - {.ADC, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x71, 2, .NMOS, {decimal=true, page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x72, 1, .NMOS_UNDOC, {}}, - {.ADC, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x72, 2, .CMOS_65C02, {decimal=true}}, - {.RRA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x73, 2, .NMOS_UNDOC, {decimal=true}}, - {.TII, {.IMM_16, .IMM_16, .IMM_16}, {.WORD_1, .WORD_3, .WORD_5}, 0x73, 7, .HUC6280, {}}, - {.STZ, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x74, 2, .CMOS_65C02, {}}, - {.ADC, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x75, 2, .NMOS, {decimal=true}}, - {.ROR, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x76, 2, .NMOS, {}}, - {.RRA, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x77, 2, .NMOS_UNDOC, {decimal=true}}, - {.RMB7, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x77, 2, .CMOS_65C02, {}}, - {.SEI, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x78, 1, .NMOS, {}}, - {.ADC, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x79, 3, .NMOS, {decimal=true, page_cross=true}}, - {.PLY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x7A, 1, .CMOS_65C02, {}}, - {.RRA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x7B, 3, .NMOS_UNDOC, {decimal=true}}, - {.JMP, {.MEM_IND_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x7C, 3, .CMOS_65C02, {branch=true}}, - {.ADC, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x7D, 3, .NMOS, {decimal=true, page_cross=true}}, - {.ROR, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x7E, 3, .NMOS, {}}, - {.RRA, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x7F, 3, .NMOS_UNDOC, {decimal=true}}, - {.BBR7, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x7F, 3, .CMOS_65C02, {cond_branch=true}}, - {.DOP, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x80, 2, .NMOS_UNDOC, {}}, - {.BRA, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x80, 2, .CMOS_65C02, {branch=true}}, - {.STA, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x81, 2, .NMOS, {}}, - {.CLX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x82, 1, .HUC6280, {}}, - {.SAX_NMOS, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x83, 2, .NMOS_UNDOC, {}}, - {.TST, {.IMM_8, .MEM_ZP, .NONE}, {.BYTE_1_IMM, .BYTE_2_ADDR, .NONE}, 0x83, 3, .HUC6280, {}}, - {.STY, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x84, 2, .NMOS, {}}, - {.STA, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x85, 2, .NMOS, {}}, - {.STX, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x86, 2, .NMOS, {}}, - {.SAX_NMOS, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x87, 2, .NMOS_UNDOC, {}}, - {.SMB0, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x87, 2, .CMOS_65C02, {}}, - {.DEY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x88, 1, .NMOS, {}}, - {.BIT, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x89, 2, .CMOS_65C02, {}}, - {.TXA, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x8A, 1, .NMOS, {}}, - {.ANE, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0x8B, 2, .NMOS_UNDOC, {}}, - {.STY, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x8C, 3, .NMOS, {}}, - {.STA, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x8D, 3, .NMOS, {}}, - {.STX, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x8E, 3, .NMOS, {}}, - {.SAX_NMOS, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x8F, 3, .NMOS_UNDOC, {}}, - {.BBS0, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x8F, 3, .CMOS_65C02, {cond_branch=true}}, - {.BCC, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0x90, 2, .NMOS, {cond_branch=true}}, - {.STA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x91, 2, .NMOS, {}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x92, 1, .NMOS_UNDOC, {}}, - {.STA, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x92, 2, .CMOS_65C02, {}}, - {.SHA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x93, 2, .NMOS_UNDOC, {}}, - {.TST, {.IMM_8, .MEM_ABS, .NONE}, {.BYTE_1_IMM, .WORD_2_ADDR, .NONE}, 0x93, 4, .HUC6280, {}}, - {.STY, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x94, 2, .NMOS, {}}, - {.STA, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x95, 2, .NMOS, {}}, - {.STX, {.MEM_ZP_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x96, 2, .NMOS, {}}, - {.SAX_NMOS, {.MEM_ZP_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x97, 2, .NMOS_UNDOC, {}}, - {.SMB1, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0x97, 2, .CMOS_65C02, {}}, - {.TYA, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x98, 1, .NMOS, {}}, - {.STA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x99, 3, .NMOS, {}}, - {.TXS, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0x9A, 1, .NMOS, {}}, - {.TAS, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9B, 3, .NMOS_UNDOC, {}}, - {.SHY, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9C, 3, .NMOS_UNDOC, {}}, - {.STZ, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9C, 3, .CMOS_65C02, {}}, - {.STA, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9D, 3, .NMOS, {}}, - {.SHX, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9E, 3, .NMOS_UNDOC, {}}, - {.STZ, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9E, 3, .CMOS_65C02, {}}, - {.SHA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0x9F, 3, .NMOS_UNDOC, {}}, - {.BBS1, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0x9F, 3, .CMOS_65C02, {cond_branch=true}}, - {.LDY, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xA0, 2, .NMOS, {}}, - {.LDA, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA1, 2, .NMOS, {}}, - {.LDX, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xA2, 2, .NMOS, {}}, - {.LAX, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA3, 2, .NMOS_UNDOC, {}}, - {.TST, {.IMM_8, .MEM_ZP_X, .NONE}, {.BYTE_1_IMM, .BYTE_2_ADDR, .NONE}, 0xA3, 3, .HUC6280, {}}, - {.LDY, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA4, 2, .NMOS, {}}, - {.LDA, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA5, 2, .NMOS, {}}, - {.LDX, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA6, 2, .NMOS, {}}, - {.LAX, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA7, 2, .NMOS_UNDOC, {}}, - {.SMB2, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xA7, 2, .CMOS_65C02, {}}, - {.TAY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xA8, 1, .NMOS, {}}, - {.LDA, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xA9, 2, .NMOS, {}}, - {.TAX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xAA, 1, .NMOS, {}}, - {.LXA, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xAB, 2, .NMOS_UNDOC, {}}, - {.LDY, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xAC, 3, .NMOS, {}}, - {.LDA, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xAD, 3, .NMOS, {}}, - {.LDX, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xAE, 3, .NMOS, {}}, - {.LAX, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xAF, 3, .NMOS_UNDOC, {}}, - {.BBS2, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xAF, 3, .CMOS_65C02, {cond_branch=true}}, - {.BCS, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0xB0, 2, .NMOS, {cond_branch=true}}, - {.LDA, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB1, 2, .NMOS, {page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xB2, 1, .NMOS_UNDOC, {}}, - {.LDA, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB2, 2, .CMOS_65C02, {}}, - {.LAX, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB3, 2, .NMOS_UNDOC, {page_cross=true}}, - {.TST, {.IMM_8, .MEM_ABS_X, .NONE}, {.BYTE_1_IMM, .WORD_2_ADDR, .NONE}, 0xB3, 4, .HUC6280, {}}, - {.LDY, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB4, 2, .NMOS, {}}, - {.LDA, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB5, 2, .NMOS, {}}, - {.LDX, {.MEM_ZP_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB6, 2, .NMOS, {}}, - {.LAX, {.MEM_ZP_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB7, 2, .NMOS_UNDOC, {}}, - {.SMB3, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xB7, 2, .CMOS_65C02, {}}, - {.CLV, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xB8, 1, .NMOS, {}}, - {.LDA, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xB9, 3, .NMOS, {page_cross=true}}, - {.TSX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xBA, 1, .NMOS, {}}, - {.LAS, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xBB, 3, .NMOS_UNDOC, {page_cross=true}}, - {.LDY, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xBC, 3, .NMOS, {page_cross=true}}, - {.LDA, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xBD, 3, .NMOS, {page_cross=true}}, - {.LDX, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xBE, 3, .NMOS, {page_cross=true}}, - {.LAX, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xBF, 3, .NMOS_UNDOC, {page_cross=true}}, - {.BBS3, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xBF, 3, .CMOS_65C02, {cond_branch=true}}, - {.CPY, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xC0, 2, .NMOS, {}}, - {.CMP, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC1, 2, .NMOS, {}}, - {.CLY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xC2, 1, .HUC6280, {}}, - {.DCP, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC3, 2, .NMOS_UNDOC, {}}, - {.TDD, {.IMM_16, .IMM_16, .IMM_16}, {.WORD_1, .WORD_3, .WORD_5}, 0xC3, 7, .HUC6280, {}}, - {.CPY, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC4, 2, .NMOS, {}}, - {.CMP, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC5, 2, .NMOS, {}}, - {.DEC, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC6, 2, .NMOS, {}}, - {.DCP, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC7, 2, .NMOS_UNDOC, {}}, - {.SMB4, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xC7, 2, .CMOS_65C02, {}}, - {.INY, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xC8, 1, .NMOS, {}}, - {.CMP, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xC9, 2, .NMOS, {}}, - {.DEX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xCA, 1, .NMOS, {}}, - {.AXS, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xCB, 2, .NMOS_UNDOC, {}}, - {.WAI, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xCB, 1, .CMOS_65C02, {}}, - {.CPY, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xCC, 3, .NMOS, {}}, - {.CMP, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xCD, 3, .NMOS, {}}, - {.DEC, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xCE, 3, .NMOS, {}}, - {.DCP, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xCF, 3, .NMOS_UNDOC, {}}, - {.BBS4, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xCF, 3, .CMOS_65C02, {cond_branch=true}}, - {.BNE, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0xD0, 2, .NMOS, {cond_branch=true}}, - {.CMP, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD1, 2, .NMOS, {page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xD2, 1, .NMOS_UNDOC, {}}, - {.CMP, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD2, 2, .CMOS_65C02, {}}, - {.DCP, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD3, 2, .NMOS_UNDOC, {}}, - {.TIN, {.IMM_16, .IMM_16, .IMM_16}, {.WORD_1, .WORD_3, .WORD_5}, 0xD3, 7, .HUC6280, {}}, - {.CSH, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xD4, 1, .HUC6280, {}}, - {.CMP, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD5, 2, .NMOS, {}}, - {.DEC, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD6, 2, .NMOS, {}}, - {.DCP, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD7, 2, .NMOS_UNDOC, {}}, - {.SMB5, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xD7, 2, .CMOS_65C02, {}}, - {.CLD, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xD8, 1, .NMOS, {}}, - {.CMP, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xD9, 3, .NMOS, {page_cross=true}}, - {.PHX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xDA, 1, .CMOS_65C02, {}}, - {.DCP, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xDB, 3, .NMOS_UNDOC, {}}, - {.STP, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xDB, 1, .CMOS_65C02, {}}, - {.CMP, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xDD, 3, .NMOS, {page_cross=true}}, - {.DEC, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xDE, 3, .NMOS, {}}, - {.DCP, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xDF, 3, .NMOS_UNDOC, {}}, - {.BBS5, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xDF, 3, .CMOS_65C02, {cond_branch=true}}, - {.CPX, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xE0, 2, .NMOS, {}}, - {.SBC, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE1, 2, .NMOS, {decimal=true}}, - {.ISC, {.MEM_IND_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE3, 2, .NMOS_UNDOC, {decimal=true}}, - {.TIA, {.IMM_16, .IMM_16, .IMM_16}, {.WORD_1, .WORD_3, .WORD_5}, 0xE3, 7, .HUC6280, {}}, - {.CPX, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE4, 2, .NMOS, {}}, - {.SBC, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE5, 2, .NMOS, {decimal=true}}, - {.INC, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE6, 2, .NMOS, {}}, - {.ISC, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE7, 2, .NMOS_UNDOC, {decimal=true}}, - {.SMB6, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xE7, 2, .CMOS_65C02, {}}, - {.INX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xE8, 1, .NMOS, {}}, - {.SBC, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xE9, 2, .NMOS, {decimal=true}}, - {.NOP, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xEA, 1, .NMOS, {}}, - {.USBC, {.IMM_8, .NONE, .NONE}, {.BYTE_1_IMM, .NONE, .NONE}, 0xEB, 2, .NMOS_UNDOC, {decimal=true}}, - {.CPX, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xEC, 3, .NMOS, {}}, - {.SBC, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xED, 3, .NMOS, {decimal=true}}, - {.INC, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xEE, 3, .NMOS, {}}, - {.ISC, {.MEM_ABS, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xEF, 3, .NMOS_UNDOC, {decimal=true}}, - {.BBS6, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xEF, 3, .CMOS_65C02, {cond_branch=true}}, - {.BEQ, {.REL, .NONE, .NONE}, {.BYTE_1_REL, .NONE, .NONE}, 0xF0, 2, .NMOS, {cond_branch=true}}, - {.SBC, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF1, 2, .NMOS, {decimal=true, page_cross=true}}, - {.JAM, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xF2, 1, .NMOS_UNDOC, {}}, - {.SBC, {.MEM_IND_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF2, 2, .CMOS_65C02, {decimal=true}}, - {.ISC, {.MEM_IND_Y, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF3, 2, .NMOS_UNDOC, {decimal=true}}, - {.TAI, {.IMM_16, .IMM_16, .IMM_16}, {.WORD_1, .WORD_3, .WORD_5}, 0xF3, 7, .HUC6280, {}}, - {.SET, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xF4, 1, .HUC6280, {}}, - {.SBC, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF5, 2, .NMOS, {decimal=true}}, - {.INC, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF6, 2, .NMOS, {}}, - {.ISC, {.MEM_ZP_X, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF7, 2, .NMOS_UNDOC, {decimal=true}}, - {.SMB7, {.MEM_ZP, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE}, 0xF7, 2, .CMOS_65C02, {}}, - {.SED, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xF8, 1, .NMOS, {}}, - {.SBC, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xF9, 3, .NMOS, {decimal=true, page_cross=true}}, - {.PLX, {.NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE}, 0xFA, 1, .CMOS_65C02, {}}, - {.ISC, {.MEM_ABS_Y, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xFB, 3, .NMOS_UNDOC, {decimal=true}}, - {.SBC, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xFD, 3, .NMOS, {decimal=true, page_cross=true}}, - {.INC, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xFE, 3, .NMOS, {}}, - {.ISC, {.MEM_ABS_X, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE}, 0xFF, 3, .NMOS_UNDOC, {decimal=true}}, - {.BBS7, {.MEM_ZP, .REL, .NONE}, {.BYTE_1_ADDR, .BYTE_2_REL, .NONE}, 0xFF, 3, .CMOS_65C02, {cond_branch=true}}, -} - -DECODE_INDEX_OPCODE := [256]Decode_Index{ - 0x00 = {0, 1}, - 0x01 = {1, 1}, - 0x02 = {2, 2}, - 0x03 = {4, 2}, - 0x04 = {6, 2}, - 0x05 = {8, 1}, - 0x06 = {9, 1}, - 0x07 = {10, 2}, - 0x08 = {12, 1}, - 0x09 = {13, 1}, - 0x0A = {14, 1}, - 0x0B = {15, 1}, - 0x0C = {16, 2}, - 0x0D = {18, 1}, - 0x0E = {19, 1}, - 0x0F = {20, 2}, - 0x10 = {22, 1}, - 0x11 = {23, 1}, - 0x12 = {24, 2}, - 0x13 = {26, 2}, - 0x14 = {28, 2}, - 0x15 = {30, 1}, - 0x16 = {31, 1}, - 0x17 = {32, 2}, - 0x18 = {34, 1}, - 0x19 = {35, 1}, - 0x1A = {36, 2}, - 0x1B = {38, 1}, - 0x1C = {39, 2}, - 0x1D = {41, 1}, - 0x1E = {42, 1}, - 0x1F = {43, 2}, - 0x20 = {45, 1}, - 0x21 = {46, 1}, - 0x22 = {47, 2}, - 0x23 = {49, 2}, - 0x24 = {51, 1}, - 0x25 = {52, 1}, - 0x26 = {53, 1}, - 0x27 = {54, 2}, - 0x28 = {56, 1}, - 0x29 = {57, 1}, - 0x2A = {58, 1}, - 0x2B = {59, 1}, - 0x2C = {60, 1}, - 0x2D = {61, 1}, - 0x2E = {62, 1}, - 0x2F = {63, 2}, - 0x30 = {65, 1}, - 0x31 = {66, 1}, - 0x32 = {67, 2}, - 0x33 = {69, 1}, - 0x34 = {70, 1}, - 0x35 = {71, 1}, - 0x36 = {72, 1}, - 0x37 = {73, 2}, - 0x38 = {75, 1}, - 0x39 = {76, 1}, - 0x3A = {77, 2}, - 0x3B = {79, 1}, - 0x3C = {80, 1}, - 0x3D = {81, 1}, - 0x3E = {82, 1}, - 0x3F = {83, 2}, - 0x40 = {85, 1}, - 0x41 = {86, 1}, - 0x42 = {87, 2}, - 0x43 = {89, 2}, - 0x44 = {91, 1}, - 0x45 = {92, 1}, - 0x46 = {93, 1}, - 0x47 = {94, 2}, - 0x48 = {96, 1}, - 0x49 = {97, 1}, - 0x4A = {98, 1}, - 0x4B = {99, 1}, - 0x4C = {100, 1}, - 0x4D = {101, 1}, - 0x4E = {102, 1}, - 0x4F = {103, 2}, - 0x50 = {105, 1}, - 0x51 = {106, 1}, - 0x52 = {107, 2}, - 0x53 = {109, 2}, - 0x54 = {111, 1}, - 0x55 = {112, 1}, - 0x56 = {113, 1}, - 0x57 = {114, 2}, - 0x58 = {116, 1}, - 0x59 = {117, 1}, - 0x5A = {118, 1}, - 0x5B = {119, 1}, - 0x5D = {120, 1}, - 0x5E = {121, 1}, - 0x5F = {122, 2}, - 0x60 = {124, 1}, - 0x61 = {125, 1}, - 0x62 = {126, 2}, - 0x63 = {128, 1}, - 0x64 = {129, 1}, - 0x65 = {130, 1}, - 0x66 = {131, 1}, - 0x67 = {132, 2}, - 0x68 = {134, 1}, - 0x69 = {135, 1}, - 0x6A = {136, 1}, - 0x6B = {137, 1}, - 0x6C = {138, 1}, - 0x6D = {139, 1}, - 0x6E = {140, 1}, - 0x6F = {141, 2}, - 0x70 = {143, 1}, - 0x71 = {144, 1}, - 0x72 = {145, 2}, - 0x73 = {147, 2}, - 0x74 = {149, 1}, - 0x75 = {150, 1}, - 0x76 = {151, 1}, - 0x77 = {152, 2}, - 0x78 = {154, 1}, - 0x79 = {155, 1}, - 0x7A = {156, 1}, - 0x7B = {157, 1}, - 0x7C = {158, 1}, - 0x7D = {159, 1}, - 0x7E = {160, 1}, - 0x7F = {161, 2}, - 0x80 = {163, 2}, - 0x81 = {165, 1}, - 0x82 = {166, 1}, - 0x83 = {167, 2}, - 0x84 = {169, 1}, - 0x85 = {170, 1}, - 0x86 = {171, 1}, - 0x87 = {172, 2}, - 0x88 = {174, 1}, - 0x89 = {175, 1}, - 0x8A = {176, 1}, - 0x8B = {177, 1}, - 0x8C = {178, 1}, - 0x8D = {179, 1}, - 0x8E = {180, 1}, - 0x8F = {181, 2}, - 0x90 = {183, 1}, - 0x91 = {184, 1}, - 0x92 = {185, 2}, - 0x93 = {187, 2}, - 0x94 = {189, 1}, - 0x95 = {190, 1}, - 0x96 = {191, 1}, - 0x97 = {192, 2}, - 0x98 = {194, 1}, - 0x99 = {195, 1}, - 0x9A = {196, 1}, - 0x9B = {197, 1}, - 0x9C = {198, 2}, - 0x9D = {200, 1}, - 0x9E = {201, 2}, - 0x9F = {203, 2}, - 0xA0 = {205, 1}, - 0xA1 = {206, 1}, - 0xA2 = {207, 1}, - 0xA3 = {208, 2}, - 0xA4 = {210, 1}, - 0xA5 = {211, 1}, - 0xA6 = {212, 1}, - 0xA7 = {213, 2}, - 0xA8 = {215, 1}, - 0xA9 = {216, 1}, - 0xAA = {217, 1}, - 0xAB = {218, 1}, - 0xAC = {219, 1}, - 0xAD = {220, 1}, - 0xAE = {221, 1}, - 0xAF = {222, 2}, - 0xB0 = {224, 1}, - 0xB1 = {225, 1}, - 0xB2 = {226, 2}, - 0xB3 = {228, 2}, - 0xB4 = {230, 1}, - 0xB5 = {231, 1}, - 0xB6 = {232, 1}, - 0xB7 = {233, 2}, - 0xB8 = {235, 1}, - 0xB9 = {236, 1}, - 0xBA = {237, 1}, - 0xBB = {238, 1}, - 0xBC = {239, 1}, - 0xBD = {240, 1}, - 0xBE = {241, 1}, - 0xBF = {242, 2}, - 0xC0 = {244, 1}, - 0xC1 = {245, 1}, - 0xC2 = {246, 1}, - 0xC3 = {247, 2}, - 0xC4 = {249, 1}, - 0xC5 = {250, 1}, - 0xC6 = {251, 1}, - 0xC7 = {252, 2}, - 0xC8 = {254, 1}, - 0xC9 = {255, 1}, - 0xCA = {256, 1}, - 0xCB = {257, 2}, - 0xCC = {259, 1}, - 0xCD = {260, 1}, - 0xCE = {261, 1}, - 0xCF = {262, 2}, - 0xD0 = {264, 1}, - 0xD1 = {265, 1}, - 0xD2 = {266, 2}, - 0xD3 = {268, 2}, - 0xD4 = {270, 1}, - 0xD5 = {271, 1}, - 0xD6 = {272, 1}, - 0xD7 = {273, 2}, - 0xD8 = {275, 1}, - 0xD9 = {276, 1}, - 0xDA = {277, 1}, - 0xDB = {278, 2}, - 0xDD = {280, 1}, - 0xDE = {281, 1}, - 0xDF = {282, 2}, - 0xE0 = {284, 1}, - 0xE1 = {285, 1}, - 0xE3 = {286, 2}, - 0xE4 = {288, 1}, - 0xE5 = {289, 1}, - 0xE6 = {290, 1}, - 0xE7 = {291, 2}, - 0xE8 = {293, 1}, - 0xE9 = {294, 1}, - 0xEA = {295, 1}, - 0xEB = {296, 1}, - 0xEC = {297, 1}, - 0xED = {298, 1}, - 0xEE = {299, 1}, - 0xEF = {300, 2}, - 0xF0 = {302, 1}, - 0xF1 = {303, 1}, - 0xF2 = {304, 2}, - 0xF3 = {306, 2}, - 0xF4 = {308, 1}, - 0xF5 = {309, 1}, - 0xF6 = {310, 1}, - 0xF7 = {311, 2}, - 0xF8 = {313, 1}, - 0xF9 = {314, 1}, - 0xFA = {315, 1}, - 0xFB = {316, 1}, - 0xFD = {317, 1}, - 0xFE = {318, 1}, - 0xFF = {319, 2}, -} - diff --git a/core/rexcode/mos6502/encoder.odin b/core/rexcode/mos6502/encoder.odin index 4bf8727fe..b8cd3deec 100644 --- a/core/rexcode/mos6502/encoder.odin +++ b/core/rexcode/mos6502/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 import "../isa" @@ -121,7 +123,7 @@ find_form_inline :: #force_inline proc( append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return nil, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return nil, false diff --git a/core/rexcode/mos6502/encoding_types.odin b/core/rexcode/mos6502/encoding_types.odin index 3571f98e8..504185655 100644 --- a/core/rexcode/mos6502/encoding_types.odin +++ b/core/rexcode/mos6502/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 import "../isa" diff --git a/core/rexcode/mos6502/instructions.odin b/core/rexcode/mos6502/instructions.odin index cd2758537..10cf8704f 100644 --- a/core/rexcode/mos6502/instructions.odin +++ b/core/rexcode/mos6502/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 // ============================================================================= diff --git a/core/rexcode/mos6502/mnemonics.odin b/core/rexcode/mos6502/mnemonics.odin index c55c551d8..db88cdc11 100644 --- a/core/rexcode/mos6502/mnemonics.odin +++ b/core/rexcode/mos6502/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 // ============================================================================= diff --git a/core/rexcode/mos6502/operands.odin b/core/rexcode/mos6502/operands.odin index 76e130d0a..e3b3ec383 100644 --- a/core/rexcode/mos6502/operands.odin +++ b/core/rexcode/mos6502/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 // ============================================================================= diff --git a/core/rexcode/mos6502/printer.odin b/core/rexcode/mos6502/printer.odin index 6c93918db..e337ae956 100644 --- a/core/rexcode/mos6502/printer.odin +++ b/core/rexcode/mos6502/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 import "core:strings" diff --git a/core/rexcode/mos6502/registers.odin b/core/rexcode/mos6502/registers.odin index 1a3ae61b4..fb4bedda9 100644 --- a/core/rexcode/mos6502/registers.odin +++ b/core/rexcode/mos6502/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 // ============================================================================= diff --git a/core/rexcode/mos6502/reloc.odin b/core/rexcode/mos6502/reloc.odin index e0dbd3353..0c4235ab2 100644 --- a/core/rexcode/mos6502/reloc.odin +++ b/core/rexcode/mos6502/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos6502 // ============================================================================= diff --git a/core/rexcode/mos6502/encoding_table.odin b/core/rexcode/mos6502/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/mos6502/encoding_table.odin rename to core/rexcode/mos6502/tablegen/encoding_table.odin index 927771df5..84c1344a2 100644 --- a/core/rexcode/mos6502/encoding_table.odin +++ b/core/rexcode/mos6502/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_mos6502 +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos6502_tablegen // ============================================================================= // MOS 6502 ENCODING_TABLE diff --git a/core/rexcode/mos6502/tablegen/gen.odin b/core/rexcode/mos6502/tablegen/gen.odin new file mode 100644 index 000000000..e257be5b7 --- /dev/null +++ b/core/rexcode/mos6502/tablegen/gen.odin @@ -0,0 +1,306 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos6502_tablegen + +// ============================================================================= +// MOS 6502 TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_INDEX_OPCODE +// generated/writer.odin Stage B: serialize those globals to ../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run mos6502/tablegen # Stage A +// odin run mos6502/tablegen/generated # Stage B +// +// 6502 paradigm note: dispatch is by a single first opcode byte, so the decode +// side is ONE 256-slot opcode->range index (DECODE_INDEX_OPCODE), not the +// multi-bucket scheme MIPS uses. Each bucket is filtered by the caller's CPU +// tier at decode time; within a bucket entries are ordered (cpu, mnemonic). +// +// Decode_Entry is NOT the same shape as Encoding: it carries the per-instruction +// `length` and only [3] operand slots (no real 6502 instruction uses the 4th), +// so it has a dedicated row writer (write_entry) separate from write_row. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "mos6502.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "mos6502.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "mos6502.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_OPCODE", "mos6502.idx_opcode.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + opcode: u8, + length: u8, + cpu: lib.CPU, + flags: lib.Encoding_Flags, +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("mos6502 tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos6502_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.opcode, f.length, f.cpu, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0..range index. Sorting CPU within an opcode bucket puts the +// NMOS-official entry before NMOS_UNDOC / 65C02 / HuC, so the decoder's CPU +// tier filter selects the right meaning for a given target. + +emit_decode_tables :: proc() -> (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f in ENCODING_TABLE[m] { + append(&all, Entry{f.mnemonic, f.ops, f.enc, f.opcode, f.length, f.cpu, f.flags}) + } + } + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.opcode != b.opcode { return a.opcode < b.opcode } + if a.cpu != b.cpu { return u8(a.cpu) < u8(b.cpu) } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + opcode_idx: [256]Range + for e, i in all { + push(&opcode_idx[e.opcode], u16(i)) + } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos6502_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by the first opcode byte.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_entry(&sb, e.mnemonic, e.ops, e.enc, e.opcode, e.length, e.cpu, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_OPCODE", opcode_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row/flags formatting (compact, matching mos6502's original generators) +// ----------------------------------------------------------------------------- + +// Encoding row: full [4] operand slots (matches lib.Encoding, 14 bytes). +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, opcode, length: u8, cpu: lib.CPU, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%02X, %d, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], opcode, length, cpu, flags_lit(flags)) +} + +// Decode entry row: only [3] operand slots (matches lib.Decode_Entry, 12 bytes; +// the 4th operand slot is always .NONE on the 6502 and is dropped). +write_entry :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, opcode, length: u8, cpu: lib.CPU, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v}}, {{.%v,.%v,.%v}}, 0x%02X, %d, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], enc[0], enc[1], enc[2], opcode, length, cpu, flags_lit(flags)) +} + +// Emit the FULL Encoding_Flags -- dropping any field silently corrupts encoding. +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.decimal { append(&parts, "decimal=true") } + if f.page_cross { append(&parts, "page_cross=true") } + if f.branch { append(&parts, "branch=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos6502_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +// One reverse-decode entry. Differs from Encoding: carries the instruction's +// total byte length and only [3] operand slots (no 6502 instruction uses 4). +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [3]Operand_Type, // 3 + enc: [3]Operand_Encoding, // 3 + opcode: u8, // 1 + length: u8, // 1 + cpu: CPU, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 12) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos6502\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "mos6502.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "mos6502.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "mos6502.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "mos6502.idx_opcode.bin", raw(&DECODE_INDEX_OPCODE, size_of(DECODE_INDEX_OPCODE))) +} diff --git a/core/rexcode/mos6502/tables.odin b/core/rexcode/mos6502/tables.odin new file mode 100644 index 000000000..7796913fa --- /dev/null +++ b/core/rexcode/mos6502/tables.odin @@ -0,0 +1,64 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos6502 + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +// One reverse-decode entry. Differs from Encoding: carries the instruction's +// total byte length and only [3] operand slots (no 6502 instruction uses 4). +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [3]Operand_Type, // 3 + enc: [3]Operand_Encoding, // 3 + opcode: u8, // 1 + length: u8, // 1 + cpu: CPU, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 12) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/mos6502.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/mos6502.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/mos6502.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_OPCODE := #load("tables/mos6502.idx_opcode.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/mos6502/tables/mos6502.encode_forms.bin b/core/rexcode/mos6502/tables/mos6502.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..0b656fdb96b7525d9b0a262a48c7cfdb4deb3739 GIT binary patch literal 4494 zcmZQ%U}9hZ<4h(7Mn(n}1_lOZ1_p*yFpm|=D+Tk|85kHqBDu^Ul^jrBEi(f%BLgRt zR|)2EL-i$s_3=P?g-jroyii^d6B8p7*k+ImG?_rIfZ47J=7H=2xy2OBgW0aj3{nZR z-Ikewi3x7IC71`ZT@kDgX1gI1NF~g6BPJ#WW(GzE1~BGg1o;|fI~x;-2eVxa%!Ap^ z#|)B#*)GS-z`z0zGZiKf52jKFEC=!%2zN3uF|dF`59A{gFb`&m4KouHD?B7lGJ!%F z=9Z&i9?UIQ!917^XPH4NVW!+=W?*84hr~@V4;B&!!TMk!aghn65*8Adn3x#Y;I=$CyAom>;fzc`%jdz$#&W zxCiFJV#SIP60;0oaEg(EfeXw65gm*S4BT+Hcrt-_Ft@mZc`*Az!919KzRVz%F#BSe z8JM`?VHOGI!NSZDtPd7uflMHkurLc^Vq)Nd`|lYO0|O5{Zoh$fF#FyygXCcL{R8u0 z{*z*4VgQ*4@(%;U3q}S8J_wV6f#C!r0|P%eZGu#Lfq5|hxiNv{VEzjO^I-P*F@xk_ z_Qf$XFbKdyiIWM$gPFn#=D|!61@mC0@PhThOp#?~U=o0bk|dZ13nfOdK3FITGJ#Zr z`~*tnLQG5yf^a`*F)}a+!oy6B3B-fhZU*MTY}aE3$-!*5V`g9wf}4`X2;#x~kj4b! z!AvOw^I)drf%U;msbgkf5Qc}uOC|+ikjp19F>r{&c^jA*IK<$*4@?Xk;&7e;69b0? zoOgkVfkP6`6JTQCkb?69m>4*u;k*JS1`Zhpm>+zY8CYb%c?aaj954@*(m=c#W+oO{ zxJm_P1{OJZ8gyV}V3CLO5*Qg+6yQ7tMg|r|I8TC+fk6q*yTQo7pbY0lFfuTxzHO~;HE5KVqnmMo3aGVgZW_#mtG&C-+5+`N?1(a2lHSqyA9^S%sdR%2XonFCPoGuxDC&l z7#VHgY3Vzd2eaWlGe{0*!+$UjX2WkV4`#z-us)a#pP3jLZQ(YkGchvQ!fh}I^I$gU zGlS${HrRuCFdMAFJeUp2V0|zfjF}i2?BF(}GchvS!EGo9^I$gQGlS${Hq?W8FdM4D zJeUp1V0|zfikTQ0?cp}CGchvQ!)*`;^I$gcGlS${Hpqi{FdL-7JeUp4V0|zfgqau_ z9N;#%gL$mb5+xkWgW2HE3{nZRAs)x0=4%*4px2rqlQnHU+I;5=>= zo;DLBgEL$%n~9Op14gy!5c0&o0*Zp2c9>X7?F8GC_E(;o)HSq356Gg!b?Ko6`}AZ zq3|}L@Ghb7J~1*f_`?1Enu(Fo56){~Vr1}x$1Mw(2a8(~CPoH-czw&m4C28;LWY@< zDF9xFH!v}=1j5@rptfQVoCj(d2g5_@79$fw2%Hzi$ixr|=lx=2VhDrtsu-CV!r?AU zVFK}BE-L}^V5x2nGe{2RvU$u*3=wdBB1|A2Or;Dn6GJ3ij)e)tgURtQGciQLZNJUP z#1IYVon~ZWh=J>4XJTTAh4aLjm>A;VJar}}hIly7oQa7c0nT%0Vq!>y^TL^!7?R+; zbS5T-WH_&!iHRWv&TD64Vn~JarZX`yq``U1nV1;T;k@lkObi)t-f<=-hDh_J~I0#jK=VxH&;AALfXJ+Vy^A58!GxWiEm)V&a`r*9C?92=k;JnZ5%nSg? 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encs := m.ENCODING_TABLE[mn] + _run := m.ENCODE_RUNS[u16(mn)] + encs := m.ENCODE_FORMS[_run.start:][:_run.count] if len(encs) <= want_mode_idx { fmt.printfln(" [FAIL] %-12s no encoding at idx %d", name, want_mode_idx) failures += 1 @@ -44,7 +47,8 @@ check :: proc( @(private="file") check_mode :: proc(name: string, mn: m.Mnemonic, want_mode: m.Operand_Type, want_opcode: u8) { // Find the form whose first Operand_Type matches `want_mode`. - for e in m.ENCODING_TABLE[mn] { + _run := m.ENCODE_RUNS[u16(mn)] + for e in m.ENCODE_FORMS[_run.start:][:_run.count] { if e.ops[0] == want_mode { if e.opcode == want_opcode { fmt.printfln(" [ok] %-22s op=%02x", name, want_opcode) diff --git a/core/rexcode/mos6502/tools/dump_verify_input.odin b/core/rexcode/mos6502/tools/dump_verify_input.odin index 3c333d9f0..cdd937e3f 100644 --- a/core/rexcode/mos6502/tools/dump_verify_input.odin +++ b/core/rexcode/mos6502/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -30,7 +32,8 @@ main :: proc() { n: int for mn in m.Mnemonic { - for &f in m.ENCODING_TABLE[mn] { + _run := m.ENCODE_RUNS[u16(mn)] + for &f in m.ENCODE_FORMS[_run.start:][:_run.count] { bytes: [7]u8 bytes[0] = f.opcode // Safe-fill the operand bytes: byte1 = 0x42, byte2 = 0x12 (page 0x12, offset 0x42) diff --git a/core/rexcode/mos6502/tools/gen_decode_tables.odin b/core/rexcode/mos6502/tools/gen_decode_tables.odin deleted file mode 100644 index 9055e12e2..000000000 --- a/core/rexcode/mos6502/tools/gen_decode_tables.odin +++ /dev/null @@ -1,181 +0,0 @@ -package main - -// ============================================================================= -// MOS 6502 DECODE-TABLE GENERATOR -// ============================================================================= -// -// 6502 dispatch is dead simple: the opcode is the first byte; everything -// else is operand bytes. Generate a flat 256-slot table where each entry -// is a (start, count) range into DECODE_ENTRIES. -// -// Most opcodes have exactly one entry. Collisions happen between CPU tiers: -// $07 SLO zp (NMOS_UNDOC) vs RMB0 zp (CMOS_65C02) -// $02 JAM (NMOS_UNDOC) vs SXY (HUC6280) -// $22 JAM (NMOS_UNDOC) vs SAX (HUC6280) -// ... and many more across the bit-op / undoc grid. -// -// The decoder filters within a bucket by the caller's target CPU tier so a -// disassembler can ask "what does $07 mean if this is an NES ROM?" vs -// "...if this is an Apple IIe binary?". -// -// Run with: cd mos6502 && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" - -import m "../" - -Entry :: struct { - mnemonic: m.Mnemonic, - ops: [4]m.Operand_Type, - enc: [4]m.Operand_Encoding, - opcode: u8, - length: u8, - cpu: m.CPU, - flags: m.Encoding_Flags, -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating MOS 6502 decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mn in m.Mnemonic { - forms := m.ENCODING_TABLE[mn] - for f in forms { - append(&all, Entry{ - mnemonic = mn, - ops = f.ops, - enc = f.enc, - opcode = f.opcode, - length = f.length, - cpu = f.cpu, - flags = f.flags, - }) - } - } - - // Sort by (opcode asc, cpu asc, mnemonic asc). Sorting by CPU within - // an opcode bucket means NMOS-official entries come before NMOS_UNDOC, - // 65C02, HuC -- the decoder's CPU-tier filter picks the right one. - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.opcode != b.opcode { return a.opcode < b.opcode } - if a.cpu != b.cpu { return u8(a.cpu) < u8(b.cpu) } - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - opcode_idx: [256]Range - for e, i in all { - if opcode_idx[e.opcode].count == 0 { - opcode_idx[e.opcode].start = u16(i) - } - opcode_idx[e.opcode].count += 1 - } - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_range_table(&sb, "DECODE_INDEX_OPCODE", opcode_idx[:]) - - output := strings.to_string(sb) - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)output) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - // Stats - max_bucket: u16 - populated: int - for r in opcode_idx { - if r.count > max_bucket { max_bucket = r.count } - if r.count > 0 { populated += 1 } - } - fmt.printfln("OK -- %d entries across %d/256 opcode slots; max bucket = %d", - len(all), populated, max_bucket) -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_mos6502 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd mos6502 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [3]Operand_Type, - enc: [3]Operand_Encoding, - opcode: u8, - length: u8, - cpu: CPU, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 12) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "") - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{.%v, {{.%v, .%v, .%v}}, {{.%v, .%v, .%v}}, 0x%02X, %d, .%v, {{%s}}}},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], - e.enc[0], e.enc[1], e.enc[2], - e.opcode, e.length, e.cpu, flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: m.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.decimal { write(&sb, &first, "decimal=true") } - if f.page_cross { write(&sb, &first, "page_cross=true") } - if f.branch { write(&sb, &first, "branch=true") } - if f.cond_branch { write(&sb, &first, "cond_branch=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/mos6502/tools/verify_against_xa.sh b/core/rexcode/mos6502/tools/verify_against_xa.sh index f63b2e2f0..3d5ccbb98 100644 --- a/core/rexcode/mos6502/tools/verify_against_xa.sh +++ b/core/rexcode/mos6502/tools/verify_against_xa.sh @@ -1,4 +1,6 @@ #!/usr/bin/env bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # ============================================================================= # MOS 6502 verification harness — disassembles via `da65` (cc65) # ============================================================================= diff --git a/core/rexcode/mos65816/decoder.odin b/core/rexcode/mos65816/decoder.odin index b88f6f00e..3790f7f61 100644 --- a/core/rexcode/mos65816/decoder.odin +++ b/core/rexcode/mos65816/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 import "../isa" diff --git a/core/rexcode/mos65816/encoder.odin b/core/rexcode/mos65816/encoder.odin index 569bb8907..70379d8af 100644 --- a/core/rexcode/mos65816/encoder.odin +++ b/core/rexcode/mos65816/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 import "../isa" @@ -103,7 +105,7 @@ find_form_inline :: #force_inline proc( append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return nil, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return nil, false diff --git a/core/rexcode/mos65816/encoding_types.odin b/core/rexcode/mos65816/encoding_types.odin index 247a641d4..37cd7b24e 100644 --- a/core/rexcode/mos65816/encoding_types.odin +++ b/core/rexcode/mos65816/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 import "../isa" diff --git a/core/rexcode/mos65816/instructions.odin b/core/rexcode/mos65816/instructions.odin index 478be8560..d510631fa 100644 --- a/core/rexcode/mos65816/instructions.odin +++ b/core/rexcode/mos65816/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 // ============================================================================= diff --git a/core/rexcode/mos65816/mnemonics.odin b/core/rexcode/mos65816/mnemonics.odin index 2bd189efa..86081d3e5 100644 --- a/core/rexcode/mos65816/mnemonics.odin +++ b/core/rexcode/mos65816/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 // ============================================================================= diff --git a/core/rexcode/mos65816/operands.odin b/core/rexcode/mos65816/operands.odin index a8d7c34af..5469c6492 100644 --- a/core/rexcode/mos65816/operands.odin +++ b/core/rexcode/mos65816/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 // ============================================================================= diff --git a/core/rexcode/mos65816/printer.odin b/core/rexcode/mos65816/printer.odin index f62979e7c..c10a5fa16 100644 --- a/core/rexcode/mos65816/printer.odin +++ b/core/rexcode/mos65816/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 import "core:strings" diff --git a/core/rexcode/mos65816/registers.odin b/core/rexcode/mos65816/registers.odin index 0a66d93c3..a2ca618ff 100644 --- a/core/rexcode/mos65816/registers.odin +++ b/core/rexcode/mos65816/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 // ============================================================================= diff --git a/core/rexcode/mos65816/reloc.odin b/core/rexcode/mos65816/reloc.odin index c8574ae69..460a3ba48 100644 --- a/core/rexcode/mos65816/reloc.odin +++ b/core/rexcode/mos65816/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_mos65816 // ============================================================================= diff --git a/core/rexcode/mos65816/encoding_table.odin b/core/rexcode/mos65816/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/mos65816/encoding_table.odin rename to core/rexcode/mos65816/tablegen/encoding_table.odin index a84322769..61a676b18 100644 --- a/core/rexcode/mos65816/encoding_table.odin +++ b/core/rexcode/mos65816/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_mos65816 +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos65816_tablegen // ============================================================================= // W65C816S ENCODING_TABLE diff --git a/core/rexcode/mos65816/tablegen/gen.odin b/core/rexcode/mos65816/tablegen/gen.odin new file mode 100644 index 000000000..195d4a248 --- /dev/null +++ b/core/rexcode/mos65816/tablegen/gen.odin @@ -0,0 +1,294 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos65816_tablegen + +// ============================================================================= +// W65C816S TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_INDEX_OPCODE index table +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run mos65816/tablegen # Stage A +// odin run mos65816/tablegen/generated # Stage B +// +// 8-bit opcode/length paradigm (sibling of mos6502): single-level dispatch -- +// the opcode byte directly indexes a 256-slot table. Most opcodes have one +// entry; the mode-dependent immediates (LDA #imm, etc.) have two entries +// sharing the same opcode, sorted so the 8-bit (length 2) form precedes the +// 16-bit (length 3) form. The decoder picks based on Assumed_State. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "mos65816.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "mos65816.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "mos65816.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_OPCODE", "mos65816.idx_opcode.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + opcode: u8, + length: u8, + flags: lib.Encoding_Flags, +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("mos65816 tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos65816_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.opcode, f.length, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f in ENCODING_TABLE[m] { + append(&all, Entry{f.mnemonic, f.ops, f.enc, f.opcode, f.length, f.flags}) + } + } + + // Sort: opcode asc; within an opcode, place the 8-bit immediate forms + // (IMM_X8/IMM_M8, length 2) before the 16-bit forms (length 3) by + // ascending length, then mnemonic for stability. + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.opcode != b.opcode { return a.opcode < b.opcode } + if a.length != b.length { return a.length < b.length } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + opcode_idx: [256]Range + for e, i in all { + push(&opcode_idx[e.opcode], u16(i)) + } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos65816_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by opcode byte.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_decode_entry(&sb, e.mnemonic, e.ops, e.enc, e.opcode, e.length, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_OPCODE", opcode_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting +// ----------------------------------------------------------------------------- + +// ENCODE_FORMS row: full [4]ops / [4]enc Encoding shape (opcode + length). +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, opcode: u8, length: u8, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%02X, %d, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], opcode, length, flags_lit(flags)) +} + +// DECODE_ENTRIES row: narrower [2]ops / [2]enc Decode_Entry shape. +write_decode_entry :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, opcode: u8, length: u8, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v, .%v}}, {{.%v, .%v}}, 0x%02X, %d, {{%s}} }},\n", + mn, ops[0], ops[1], enc[0], enc[1], opcode, length, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.branch { append(&parts, "branch=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + if f.page_cross { append(&parts, "page_cross=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos65816_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [2]Operand_Type, // 2 + enc: [2]Operand_Encoding, // 2 + opcode: u8, // 1 + length: u8, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 9) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_mos65816\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "mos65816.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "mos65816.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "mos65816.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "mos65816.idx_opcode.bin", raw(&DECODE_INDEX_OPCODE, size_of(DECODE_INDEX_OPCODE))) +} diff --git a/core/rexcode/mos65816/tables.odin b/core/rexcode/mos65816/tables.odin new file mode 100644 index 000000000..0d61a90f9 --- /dev/null +++ b/core/rexcode/mos65816/tables.odin @@ -0,0 +1,61 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_mos65816 + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [2]Operand_Type, // 2 + enc: [2]Operand_Encoding, // 2 + opcode: u8, // 1 + length: u8, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 9) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/mos65816.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/mos65816.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/mos65816.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_OPCODE := #load("tables/mos65816.idx_opcode.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/mos65816/tables/mos65816.encode_forms.bin b/core/rexcode/mos65816/tables/mos65816.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..ceb89cacb02945c5be6b2d48c70e6156680d4aed GIT binary patch literal 3484 zcmZQ%;ALQ7U}0cjNMvGQWRQe%l0h6!C?^%f;fHe4K^$fV1_mYu28K)!2c#J!kjc!z z$RNnTz`)ADz>o{#h%+!SurV+&@B4i}VD3gQSr zIprXZFx2QuW)?;UAtFPRU}IunW`G$j2I9a1o{yP<8E%>!GXo1;j|vk5 z3tW#0hy&B315ySHQ5$9!khPEq?gS}=1xP0|11mgu4>B>Z!h`oPhy!!mQ4j|fyvIQt zSn!?%abTvM1epeN!C4Ro7QE+K7+B%Spaw4NvjDAPy`_ z{8<>d;ZYLE#KH}ak|2-)uqX)zabQsr3gW<`Bpk$nMM)$x3pYGUVnG~Ol*F?z@W6vg z3RF(OyzmT^$zVo*194zM^^Tc=2X5LwW^iyoLgxjf)PZnLFf#DNjrIa@U`D$!G4O-K z6ci3&AP&rEKV}AgxY2RU3<6-oLCP4J7zE&9%?#qeOk)LcU}4P;;=sb16T|^&1_^M2 zOoQ3O3*x}SnxBP103OzYOe_NMuoeOt01Inj5C;|@q96_|ti?ebSXfIkvk1VwAPeHa z!djk%K@c7wTA-pE<^?rSxd$`a48(ysRF9cK5N?_ssGtF*X%Nl=mB}yz(m(|o%z!cw z2WCJXNDnMs*D*5)!$b5T6N4~3L?44VFw>rbIIs|X4&s0U5R`gff;g}ceF-uRX3tv? z2Nt65Sr~-jA^MStMHn8UpFjq{Li96;19SCP5C;~b-$5K$i2h_|5r&7sUl0ctqW@VK zMBx5e$iyH5_s?Pw2j-upAP&qw%RwBNe^!DxF#oJ%W)Okr#e zaQ|!q836OoW)KJFpRFJc%s<;f9GHK0GP8)l{j(Ruf%#`Y3xg=Uuv^5$APO(+7BMr3 z!b`DbAQ^6GRlN^fK12e6cnL(TZ7NY$u4C3$Q2$MrUAR)P&2tVr0-_U}sa83XdlOdc_z{F$(w^V|W!5GfD!N_0&=R`0v zn8GG_8evgD|kMg z$IM_2*CWEjU=0sm8D<6>xC{#ugAH7Uhnc|^?t)v440do%6eEK@ob!v3!2!;xVq|cH zb8a&-IKerm85x`zI2ahfxQUt31s+*UOpLDZoE5{u=*l1pO$T?F8QtJAN-T`-4AL?T z3|yQH3?a-69&nBeGlM7G)nAwyyx`^A6($C6u!SItlb9KN;Lho0WblP^xEUGz;2dv8 z27fqbH6ud+oTJUi5D0hmAtr_(IOh=)Loi%fHX~yQoD<(uq*040xHk7^trSC%NdrQB+|3K-# vQ2HN~{tu-=i3gN^7#ShyhzUwFLunQ$%?hR2pfo#_=77?iP?`%$b32}W3|1xvW-x;d zB*M?Y!obeNpvV9M9E=PC49pBn44fb-7LYn-24)6E21W)hMh0Jy5(aKY1{(%J237_h zW(EN;gBPR*B*F(05ocgy;AdgbXJBVwXAodw5@6tCU||qsVi92AVPIhp0+}quz``KR z#9$3}h6qT6i-Cnf6yz`vLkuJ$z`(*F&ct8@wp0S-FkuE(21#ZX91Q$=zu~L6h68jH6Vr_NCafNJ_~~`IG_xen3%u;Wyr+B1P&-8kjbEcG6p#e z6f7nn5fH-^yD03zTGq9x=Acuhh%95Fd1MD6vMuu>(lr_jbpkT3KW?=${ zk1aEcAednXat|n=>{%Gpz=|Ch8M(m$<;cVk1x`^;Obp!MfO2MH@L-UZ;o@{*X5a>g zk1G=cKbYYLQUeMocP0h}usI%#4BX%pev=PI?$PEskSY{S}Fe46R zGAN+pSs2v8iW3+a8NmUS$i(2yz`?-5kOaywpcIwN#9##umJ}uiMld546z-s;l?D<4 z1yni{gA&-B3{WNmMMEY?3KUS8phOH3&0=H-2CK}gVPIv*VP<3m2UIRd4Je@U zK$e06DxZbH5FAhiOiYa6fGT8SVFU+M5y)gvKox@=1`3uEkO+uT3UU~TQ3etL1ynf` zg9X^q3Xl^(0aeM&;s6$@Vq^#fGpa!mC&s|aPy=!gC~4I)vj~9$st)8HP(anQFj#`! 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Single-level -// dispatch (opcode byte directly indexes a 256-slot table). Most -// opcodes have one entry; the mode-dependent immediates (LDA #imm, -// ADC #imm, etc.) have two entries sharing the same opcode, sorted so -// the 8-bit form is at lower index than the 16-bit form. The decoder -// picks based on Assumed_State. - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" - -import m "../" - -Entry :: struct { - mnemonic: m.Mnemonic, - ops: [4]m.Operand_Type, - enc: [4]m.Operand_Encoding, - opcode: u8, - length: u8, - flags: m.Encoding_Flags, -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating W65C816S decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mn in m.Mnemonic { - for f in m.ENCODING_TABLE[mn] { - append(&all, Entry{ - mnemonic = mn, ops = f.ops, enc = f.enc, - opcode = f.opcode, length = f.length, flags = f.flags, - }) - } - } - - // Sort: opcode asc; within an opcode, place IMM_X8/IMM_M8 (length 2) - // before IMM_X16/IMM_M16 (length 3) by ascending length, then mnemonic - // for stability. - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.opcode != b.opcode { return a.opcode < b.opcode } - if a.length != b.length { return a.length < b.length } - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - opcode_idx: [256]Range - for e, i in all { - if opcode_idx[e.opcode].count == 0 { - opcode_idx[e.opcode].start = u16(i) - } - opcode_idx[e.opcode].count += 1 - } - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_range_table(&sb, "DECODE_INDEX_OPCODE", opcode_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - max_bucket: u16 - populated: int - for r in opcode_idx { - if r.count > max_bucket { max_bucket = r.count } - if r.count > 0 { populated += 1 } - } - fmt.printfln("OK -- %d entries across %d/256 opcode slots; max bucket = %d", - len(all), populated, max_bucket) -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_mos65816 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd mos65816 && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [2]Operand_Type, - enc: [2]Operand_Encoding, - opcode: u8, - length: u8, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 9) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "") - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{ .%v, {{.%v, .%v}}, {{.%v, .%v}}, 0x%02X, %d, {{%s}} }},", - e.mnemonic, - e.ops[0], e.ops[1], - e.enc[0], e.enc[1], - e.opcode, e.length, flags_str) - } - strings.write_string(sb, "}\n") -} - -encode_flags_literal :: proc(f: m.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.branch { write(&sb, &first, "branch=true") } - if f.cond_branch { write(&sb, &first, "cond_branch=true") } - if f.page_cross { write(&sb, &first, "page_cross=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/mos65816/tools/verify_against_ca65.sh b/core/rexcode/mos65816/tools/verify_against_ca65.sh index 6a0ff81e8..9e81512ba 100644 --- a/core/rexcode/mos65816/tools/verify_against_ca65.sh +++ b/core/rexcode/mos65816/tools/verify_against_ca65.sh @@ -1,4 +1,6 @@ #!/usr/bin/env bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # ============================================================================= # W65C816 verification harness — assembles via ca65, compares bytes # ============================================================================= diff --git a/core/rexcode/ppc/decoder.odin b/core/rexcode/ppc/decoder.odin index 06e28b68c..f0996f241 100644 --- a/core/rexcode/ppc/decoder.odin +++ b/core/rexcode/ppc/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc import "../isa" @@ -127,7 +129,7 @@ try_bucket :: proc(word, prefix: u32, prefixed: bool, mode: Mode, r: Decode_Inde // the 8-bit template at bits 24..21 LSB). Only the IMM18+R fields // (bits 0..18 LSB) are variable in the prefix. if prefixed { - expected_prefix := PREFIX_BITS_TABLE[e.mnemonic] + expected_prefix := PREFIX_BITS_TABLE[u16(e.mnemonic)] // Mask covers primary (bits 26..31) and template/R (bits 19..25). // IMM18 occupies bits 0..17 — leave those free. prefix_mask: u32 = 0xFFFC0000 diff --git a/core/rexcode/ppc/decoding_tables.odin b/core/rexcode/ppc/decoding_tables.odin deleted file mode 100644 index e684c1abd..000000000 --- a/core/rexcode/ppc/decoding_tables.odin +++ /dev/null @@ -1,4793 +0,0 @@ -package rexcode_ppc - -// ============================================================================= -// GENERATED FILE — DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd ppc && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - mode: Mode, - flags: Encoding_Flags, -} - -Decode_Index :: struct #packed { - start: u32, - count: u16, - _: u16, -} - -DECODE_SUB_BUCKETS :: 256 // per primary - -@(rodata) -DECODE_ENTRIES := [3327]Decode_Entry{ - {.ATTN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00000200, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.TDGTI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09030064, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.TDLTI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0A030064, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.TDEQI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x08830064, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.TDNEI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0B030064, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.TDUI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0BE30064, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.TDI, {.IMM, .GPR, .SIMM, .NONE}, {.TO_FIELD, .RA, .D16, .NONE}, 0x08000000, 0xFC000000, .P64, .PPC64, {}}, - {.TWGTI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0D030064, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TWLTI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0E030064, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TWEQI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0C830064, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TWNEI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0F030064, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TWUI, {.GPR, .SIMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0FE30064, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x0C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.TWI, {.IMM, .GPR, .SIMM, .NONE}, {.TO_FIELD, .RA, .D16, .NONE}, 0x0C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.VSTRIBL_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10401C0D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSTRIBR_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10411C0D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSTRIHL_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10421C0D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSTRIHR_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10431C0D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VMSUMCUD, {.VR, .VR, .VR, .VR}, {.NONE, .NONE, .NONE, .NONE}, 0x10432157, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCFUGED, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043254D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VPDEPD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104325CD, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VPEXTD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043258D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VGNB, {.GPR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106224CC, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCLZDM, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432784, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCTZDM, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104327C4, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCLRLB, {.VR, .VR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043218D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCLRRB, {.VR, .VR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104321CD, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXPANDBM, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10401E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXPANDHM, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10411E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXPANDWM, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10421E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXPANDDM, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10431E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXPANDQM, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10441E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTRACTBM, {.GPR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10682642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTRACTHM, {.GPR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10692642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTRACTWM, {.GPR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106A2642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTRACTDM, {.GPR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106B2642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTRACTQM, {.GPR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106C2642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCNTMBB, {.GPR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10781642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCNTMBH, {.GPR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x107A1642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCNTMBW, {.GPR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x107C1642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCNTMBD, {.GPR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x107E1642, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MTVSRBM, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10101E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MTVSRHM, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10111E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MTVSRWM, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10121E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MTVSRDM, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10131E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MTVSRQM, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10141E42, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUBLX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043260D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUHLX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043264D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUWLX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043268D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUBRX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043270D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUHRX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043274D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTUWRX, {.GPR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043278D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSBVLX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043200F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSHVLX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043204F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSWVLX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043208F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSBVRX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043210F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSHVRX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043214F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSWVRX, {.VR, .GPR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043218F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSBLX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043220F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSHLX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043224F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSWLX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043228F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSDLX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104322CF, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSBRX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043230F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSHRX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043234F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSWRX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043238F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSDRX, {.VR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104323CF, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSW, {.VR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104018CF, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VINSD, {.VR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x104019CF, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUBVLX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x10432018, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUHVLX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201A, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUWVLX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201C, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDDVLX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUBVRX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x10432019, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUHVRX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201B, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDUWVRX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201D, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VEXTDDVRX, {.VR, .VR, .VR, .GPR}, {.NONE, .NONE, .NONE, .NONE}, 0x1043201F, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VRLQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432005, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VRLQMI, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432045, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VRLQNM, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432145, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSLQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432105, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSRQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432205, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSRAQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432305, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VSUMSWS, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642F88, 0xFFFFFFFF, .ALTIVEC, .PPC32, {}}, - {.VSUM2SWS, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E88, 0xFFFFFFFF, .ALTIVEC, .PPC32, {}}, - {.VSUM4SBS, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642F08, 0xFFFFFFFF, .ALTIVEC, .PPC32, {}}, - {.VSUM4SHS, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E48, 0xFFFFFFFF, .ALTIVEC, .PPC32, {}}, - {.VSUM4UBS, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E08, 0xFFFFFFFF, .ALTIVEC, .PPC32, {}}, - {.BCDADD_DOT, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x10432401, 0xFFFFFFFF, .POWER8, .PPC32, {sets_cr0=true}}, - {.BCDSUB_DOT, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x10432441, 0xFFFFFFFF, .POWER8, .PPC32, {sets_cr0=true}}, - {.BCDS_DOT, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x104324C1, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDUS_DOT, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432481, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDSR_DOT, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x104325C1, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCFN_DOT, {.VR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10471D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCTN_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10451D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCFZ_DOT, {.VR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10461D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCTZ_DOT, {.VR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10441D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCPSGN_DOT, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432341, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDTRUNC_DOT, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x10432501, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDUTRUNC_DOT, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10432541, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCFSQ_DOT, {.VR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10421D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.BCDCTSQ_DOT, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10401D81, 0xFFFFFFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.VEXTSD2Q, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x105B1E02, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.EVADDW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A00, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDIW, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10652202, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBIFW, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A06, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEXTSH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064020B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEXTSB, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064020A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCNTLZW, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064020D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCNTLSW, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064020E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A28, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A24, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A26, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATI, {.GPR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFI, {.GPR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064022B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A20, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A21, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRWIU, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A22, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRWIS, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A23, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAND, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A11, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVOR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A17, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVXOR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A16, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNAND, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A1E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNOR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVANDC, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A12, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVORC, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A1B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEQV, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A19, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPGTS, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A31, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPGTU, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A30, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPLTS, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A33, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPLTU, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A32, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A34, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSEL, {.GPR, .GPR, .GPR, .CR_FIELD}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A78, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMERGEHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMERGELO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMERGEHILO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMERGELOHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMRA, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106404C4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDD, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640301, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDDX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B00, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDW, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640303, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B02, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDH, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640305, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDD, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640321, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDDX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B20, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDW, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640323, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B22, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDH, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640325, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B24, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWWSPLAT, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640319, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLAT, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064031D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHESPLAT, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640309, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOSSPLAT, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064030F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOUSPLAT, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064030D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHE, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640311, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOU, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640315, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOS, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640317, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHEX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B10, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWE, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640339, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWO, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064033D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHE, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640331, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHO, {.GPR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640335, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHEX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B30, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A80, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A81, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640284, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSNABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640285, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSNEG, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640286, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMUL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A88, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSDIV, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A89, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCMPGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A8C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCMPLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A8D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCMPEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A8E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSTSTGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A9C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSTSTLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A9D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSTSTEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842A9E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCFUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1060228A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCFSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602291, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCFUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602292, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCFSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602293, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602294, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602295, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602296, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602297, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTUIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10602298, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTSIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1060229A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402C4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSNABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSNEG, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402C6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSMUL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSDIV, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCMPGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ACC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCMPLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ACD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCMPEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ACE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSTSTGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ADC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSTSTLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ADD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSTSTEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842ADE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTUIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022D8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTSIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022DA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFD, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022CF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402E4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDNABS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402E5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDNEG, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402E6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDMUL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDDIV, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCMPGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AEC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCMPLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AED, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCMPEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AEE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDTSTGT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AFC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDTSTLT, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AFD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDTSTEQ, {.CR_FIELD, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x11842AFE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTUI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTSI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTUF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTSF, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTUIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022F8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTSIZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022FA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFS, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022EF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFSID, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022E3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFUID, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022E2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTSIDZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022EB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTUIDZ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106022EA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C07, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C27, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D07, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D87, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D05, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D85, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D89, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C03, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C23, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D03, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D83, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D01, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D81, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C08, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C28, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D08, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D88, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D00, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEUSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D80, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOUSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D84, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D2F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DAF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D2D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGSMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DAD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D2C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOGUMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DAC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DAB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGSMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DA9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D28, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHEGUMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DA8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C47, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C67, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D41, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C4F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C6F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C4D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C6D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C4C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C6C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D49, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C48, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C68, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D48, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D40, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C5B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C7B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D5B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DDB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C59, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C79, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D59, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C53, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C73, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D53, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C58, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C78, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D58, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.BRINC, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A0F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWWSPLATX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHESPLATX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B08, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOSSPLATX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B0E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOUSPLATX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOUX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B14, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOSX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B16, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWEX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B38, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWOX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B3C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHOX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B34, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A82, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A83, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSNMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A8A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSNMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A8B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSNMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ACA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSNMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ACB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AE3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDNMADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AEA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDNMSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AEB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSQRT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640287, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMAX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMIN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCFH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A91, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSCTH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A95, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSADDSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUBADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUM, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSDIFF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUMDIFF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSDIFFSUM, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSADDX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AA9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSADDSUBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AAA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSSUBADDX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AAB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMULX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AAC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMULE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AAE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVFSMULO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AAF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSSQRT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402C7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSMAX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AB0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSMIN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AB1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCFH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFSCTH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDSQRT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106402E7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDMAX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AB8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDMIN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AB9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCFH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AF1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EFDCTH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AF5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBIW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A06, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEG, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A17, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSSUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSABS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSNABS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSNEG, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSMUL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSDIV, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AC9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCMPGT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ACC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSGMPLT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ACD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSGMPEQ, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ACE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCFUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCFSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCFUF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCFSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTUF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTUIZ, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642AD8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSCTSIZ, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ADA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTSTGT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ADC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTSTLT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ADD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTSTEQ, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642ADE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C43, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C4B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C63, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C6B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D43, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D44, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSMAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D45, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D47, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D64, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D65, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSSFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D67, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D6F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUSIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHUMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGUMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DE4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSMIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DE5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSSFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DE7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHGSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DEF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642880, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642881, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642882, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642883, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642888, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642889, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064288F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642890, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642891, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642892, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642893, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642898, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642899, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFRAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFRAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFRAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFRAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064289F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428A9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428AF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWCSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428B9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGASMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGASMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWGSSMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWXGSSMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106428BF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642900, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642901, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642902, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642903, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642908, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642909, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064290A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064290B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642910, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642911, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642912, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642913, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642918, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642919, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064291A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064291B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642920, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642921, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642922, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642923, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642928, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642929, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064292A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064292B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642930, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642931, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642932, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642933, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642938, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642939, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHIHCSSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064293A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPLOHCSSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064293B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642940, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642941, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642942, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642943, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642947, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642948, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642949, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064294A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064294B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064294D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064294D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064294F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642950, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642951, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642952, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642953, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642955, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642957, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642958, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642959, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064295A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064295B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064295D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064295F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642960, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642961, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642962, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642963, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642967, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642968, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642969, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064296A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064296B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064296D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064296D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064296F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642970, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642971, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642972, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642973, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642975, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642977, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHAUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642978, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642979, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064297A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHASSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064297B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064297D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPHSSSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064297F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGAUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642980, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642981, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642982, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642983, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642984, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642985, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642986, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642987, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBAUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642988, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642989, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064298A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064298E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064298F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGAUMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642990, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642991, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASUMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642992, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642993, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642994, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642995, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642996, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642997, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBAUMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642998, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642999, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASUMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064299A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064299E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMFAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064299F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGAUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBAUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429A9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429AA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429AE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429AF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGAUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGASMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HGSSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGASMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBAUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429B9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPBASUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429BA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429BE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTP4HXGSSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429BF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429C0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429C1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429C2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429C8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429C9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429CA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429CD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429CD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUSIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASSIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUSIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSSIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429D9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429DA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSMIAA3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429DD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429E0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429E1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429E2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429E8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429E9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429EA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429ED, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSSIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429ED, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWAUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429F9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWASUMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429FA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDOTPWSSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106429FD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDIB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A03, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDIH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A01, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBIFH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A05, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBIFB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A07, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10645208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10647208, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGWO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGBO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGHO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGWOS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10645209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGBOS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10645A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGHOS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646A09, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVNEGDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10647209, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEXTZB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A0A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEXTSBH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064220A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVEXTSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064320B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064020C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064220C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064320C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWHUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064420C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644A0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHBUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064620C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHBSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646A0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDWUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064720C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10647A0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWNH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064820C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHNB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064A20C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDNW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064B20C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWNHUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064C20C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDWNHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064CA0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHNBUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064E20C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDHNBSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064EA0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDNWUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064F20C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRNDDNWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064FA0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCNTLZH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064220D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCNTLSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064220E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPOPCNTB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064D20E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.CIRCINC, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A10, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIBUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064021C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIBSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIHUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064121C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIHSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOBUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064221C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOBSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOHUI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064321C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOHSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOHF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064421C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIHF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKLOWGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064621C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVUNPKHIWGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSDUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064821C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSDSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10648A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSHUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064921C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSHSB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10649A1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUWUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064A21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSWSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064AA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSWUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064B21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUHUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064BA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUDUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064C21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUWSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064CA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSHUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064D21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUHSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064DA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSWUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064E21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSWGSDF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064EA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATSBUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064F21C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSATUBSB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064FA1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXHPUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064021D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXHPSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXBPUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064221D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXBPSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXWPUD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064321D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXWPSD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINHPUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064421D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINHPSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10644A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINBPUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064621D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINBPSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINWPUD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064721D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINWPSD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10647A1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXMAGWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A1F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A25, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A27, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIBE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641A29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIHE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATID, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10648229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIEA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10648A29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIBA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10649229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIBEA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10649A29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIHA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064A229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIHEA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064AA29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATIDA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064B229, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640A2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064122B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIBO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641A2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064222B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIHO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFID, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064322B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064822B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIOA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10648A2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIBA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064922B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIBOA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10649A2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIHA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064A22B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIHOA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064AA2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATFIDA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064B22B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPGTDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10242A30, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPGTDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10242A31, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPLTDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10242A32, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPLTDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10242A33, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCMPEQD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10242A34, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPBHILO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A38, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPBLOHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A39, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHHILO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHLOHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHLO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSWAPHO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A3F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVINSB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A48, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVXTRB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A4A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064024C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSPLATB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064124C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVINSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A4D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCLRBE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064024E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCLRBO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064824E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVCLRH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064824F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVXTRH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A4F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSELBITM0, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A50, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSELBITM1, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A51, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSELBIT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A52, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPERM, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A54, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPERM2, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A55, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPERM3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A56, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVXTRD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A58, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A60, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A61, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRBIU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A62, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRBIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A63, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A64, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A65, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLBI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A66, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLBI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A67, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A68, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A69, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRHIU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRHIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVRLHI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A6F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A70, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A71, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRIU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A72, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSRIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A73, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLVSL, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A74, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLVSR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A75, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSROIU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642A77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSROIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10646A77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSLOI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064AA77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B06, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B07, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHSPLATHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B0A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHSPLATH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B0B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBSPLATWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B12, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBSPLATW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B13, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B1A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B1B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLBBSPLATBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B1E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLBBSPLATB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B1F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B26, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B27, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBEX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOUX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOSX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B2F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBEX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B32, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBE, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B33, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBOX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B36, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBO, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B37, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B3A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B3B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTHBX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B3E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTHB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B3F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDDMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B40, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B41, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDWMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B42, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B43, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDHMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B44, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B45, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDBMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B46, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLDBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B47, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHESPLATMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B48, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHESPLATU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B49, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHSPLATHMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHSPLATHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOUSPLATMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOUSPLATU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOSSPLATMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLHHOSSPLATU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B4F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHEMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B50, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHEU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B51, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBSPLATWMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B52, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBSPLATWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B53, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOUMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B54, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOUU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B55, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOSMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B56, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHOSU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B57, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWWSPLATMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B58, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWWSPLATU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B59, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATWMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWHSPLATU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLBBSPLATBMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLBBSPLATBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B5F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDDMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B60, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B61, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDWMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B62, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B63, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDHMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B64, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B65, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDBMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B66, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTDBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B67, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBEMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBEU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOUMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOUU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOSMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVLWBOSU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B6F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHEMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B70, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHEU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B71, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBEMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B72, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBEU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B73, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHOMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B74, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWHOU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B75, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBOMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B76, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBOU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWEMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B78, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWEU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B79, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWOMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTWWOU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTHBMX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSTHBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642B7F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C00, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHSSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C01, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHSUSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C02, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHSSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C05, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C06, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C0E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C19, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C1A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUMI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C1E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C2E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C38, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C39, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C3A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C3C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C3D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUMIA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C3E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUSIW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C40, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSIW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C41, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C46, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C56, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C57, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C5E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C5F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C66, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C76, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFRA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C7E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C7F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640480, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640481, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640482, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFSSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640483, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640484, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFSMIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640486, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C88, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C89, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C8F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C90, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDDSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C91, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C92, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFDSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C93, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C94, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDBSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C95, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C96, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFBSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C97, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C98, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C99, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDHSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFHXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDHX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDHXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642C9F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDDUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDBUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFDUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFBUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWXUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWXUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADD2SUBF2H, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADD2SUBF2HSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CA9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBF2ADD2H, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBF2ADD2HSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHXUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHXUS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CAF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CB9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDWSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDSUBFWXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDWX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFADDWXSS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CBF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640CC4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106404C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10640CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106414C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10641CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106424C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIFF2HIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106434C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HIS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10643CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWUA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106484C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWSA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10648CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BUA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x106494C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BSA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10649CC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HUA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064A4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HSA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064ACC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIFF2HISA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064B4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HISA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064BCC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWUAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064C4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUMWSAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064CCC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BUAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064D4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM4BSAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064DCC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HUAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064E4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HSAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064ECC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIFF2HISAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064F4C5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUM2HISAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1064FCC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVWSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVWUF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDIVU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CCF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWEGSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWEGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWEGSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWEGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWOGSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDWOGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWOGSI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFWOGSF, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHHIUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD8, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHHISW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CD9, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHHIUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHHISW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHLOUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDC, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVADDHLOSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDD, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHLOUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSUBFHLOSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642CDF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D02, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUSIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D06, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUMIAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D0E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D10, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D11, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D12, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D14, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D15, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUSIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D16, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D19, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D1A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D1D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUMIAAH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D1E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D42, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D43, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFRAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D44, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D45, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFRAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D46, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D47, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMIAAW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D4B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D50, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSIAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D51, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D56, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D57, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFRAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D5E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D5F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D82, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUSIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D86, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHESUMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMHOSUMIANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D8E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D90, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D91, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D92, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D94, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D95, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUSIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D96, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBEUMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D98, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D99, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBESUMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D9A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOUMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D9C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D9D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMBOSUMIANH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642D9E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUSIANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC2, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSSIANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC3, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFRANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC4, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC5, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFRANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWHSSFANW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DC7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLUMIANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCA, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWLSMIANW3, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DCB, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWUSIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD0, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWSSIAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD1, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFRAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD6, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWEHGSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DD7, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFRAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DDE, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMWOHGSMFAN, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642DDF, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETEQB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E00, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETEQH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E02, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETEQW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E04, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E08, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E0A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E0C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E0E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E10, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETGTBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E12, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E14, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E16, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E18, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E1A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E1C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSETLTWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E1E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E20, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E21, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4UB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E22, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4SB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E23, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2UH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E24, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2SH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E25, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADUWA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E28, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADSWA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E29, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4UBA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E2A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4SBA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E2B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2UHA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E2C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2SHA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E2D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFUW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E30, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFSW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E31, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E32, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFSB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E33, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFUH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E34, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVABSDIFSH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E35, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADUWAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E38, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSADSWAA, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E39, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4UBAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E3A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD4SBAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E3B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2UHAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E3C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVSAD2SHAAW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E3D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSHUBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E40, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSHSBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E41, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWUHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E42, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWSHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E43, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKUHUBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E44, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKUWUHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E45, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWSHILVS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E46, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWGSHEFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E47, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWSHFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E48, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWSHILVFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E49, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSDSWFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E4A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSDSHEFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E4B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKUDUWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E4C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSDSWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E4D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVPKSWGSWFRS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E4E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVEH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E50, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVEOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E51, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVHIH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E52, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVHILOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E53, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVLOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E54, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVLOHIH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E55, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVOEH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E56, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVILVOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E57, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVEB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E58, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVEH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E59, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVEOB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVEOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVOB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVOH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVOEB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVDLVOEH, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E5F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E60, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E61, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E62, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E63, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E64, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E65, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E66, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMAXDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E67, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E68, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E69, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVMINDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E6F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGWU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E70, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGWS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E71, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGBU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E72, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGBS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E73, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGHU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E74, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGHS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E75, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGDU, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E76, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGDS, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E77, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGWUR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E78, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGWSR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E79, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGBUR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7A, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGBSR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7B, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGHUR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7C, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGHSR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7D, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGDUR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7E, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.EVAVGDSR, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10642E7F, 0xFFFFFFFF, .SPE, .PPC32, {}}, - {.VSTRIBL, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1040180D, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.VSTRIBR, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1041180D, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.VSTRIHL, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1042180D, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.VSTRIHR, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1043180D, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.VSLDBI, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x10432016, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.VSRDBI, {.VR, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x10432216, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.MFVSCR, {.VR, .NONE, .NONE, .NONE}, {.VRT, .NONE, .NONE, .NONE}, 0x10000604, 0xFC1FFFFF, .ALTIVEC, .PPC32, {}}, - {.MTVSCR, {.VR, .NONE, .NONE, .NONE}, {.VRB, .NONE, .NONE, .NONE}, 0x10000644, 0xFFFF07FF, .ALTIVEC, .PPC32, {}}, - {.VSPLTISB, {.VR, .SIMM, .NONE, .NONE}, {.VRT, .SIMM_5, .NONE, .NONE}, 0x1000030C, 0xFC00FFFF, .ALTIVEC, .PPC32, {}}, - {.VSPLTISH, {.VR, .SIMM, .NONE, .NONE}, {.VRT, .SIMM_5, .NONE, .NONE}, 0x1000034C, 0xFC00FFFF, .ALTIVEC, .PPC32, {}}, - {.VSPLTISW, {.VR, .SIMM, .NONE, .NONE}, {.VRT, .SIMM_5, .NONE, .NONE}, 0x1000038C, 0xFC00FFFF, .ALTIVEC, .PPC32, {}}, - {.VUPKHSB, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000020E, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VUPKHSH, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000024E, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VUPKHSW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000064E, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VUPKLSB, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000028E, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VUPKLSH, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100002CE, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VUPKLSW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100006CE, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VUPKHPX, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000034E, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VUPKLPX, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100003CE, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VSBOX, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRA, .NONE, .NONE}, 0x100005C8, 0xFC00FFFF, .POWER8, .PPC32, {}}, - {.VRFIM, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100002CA, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VRFIN, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000020A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VRFIP, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000028A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VRFIZ, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000024A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VEXPTEFP, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000018A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VLOGEFP, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100001CA, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VREFP, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000010A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VRSQRTEFP, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x1000014A, 0xFC1F07FF, .ALTIVEC, .PPC32, {}}, - {.VEXTSB2W, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10100602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VEXTSH2W, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10110602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VEXTSB2D, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10180602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VEXTSH2D, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10190602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VEXTSW2D, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x101A0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VPRTYBW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10080602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VPRTYBD, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10090602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VPRTYBQ, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100A0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VCLZB, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000702, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VCLZH, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000742, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VCLZW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000782, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VCLZD, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100007C2, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VCTZB, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x101C0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VCTZH, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x101D0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VCTZW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x101E0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VCTZD, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x101F0602, 0xFC1F07FF, .POWER9, .PPC32, {}}, - {.VPOPCNTB, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000703, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VPOPCNTH, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000743, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VPOPCNTW, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x10000783, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VPOPCNTD, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRB, .NONE, .NONE}, 0x100007C3, 0xFC1F07FF, .POWER8, .PPC32, {}}, - {.VMUL10UQ, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRA, .NONE, .NONE}, 0x10000201, 0xFC00FFFF, .POWER9, .PPC32, {}}, - {.VMUL10CUQ, {.VR, .VR, .NONE, .NONE}, {.VRT, .VRA, .NONE, .NONE}, 0x10000001, 0xFC00FFFF, .POWER9, .PPC32, {}}, - {.PS_RES_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000031, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_RSQRTE_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000035, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_NEG_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000051, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MR_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000091, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_NABS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000111, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_ABS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000211, 0xFC1F07FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_RES, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000030, 0xFC1F07FE, .PS, .PPC32, {}}, - {.PS_RSQRTE, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000034, 0xFC1F07FE, .PS, .PPC32, {}}, - {.PS_NEG, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000050, 0xFC1F07FE, .PS, .PPC32, {}}, - {.PS_MR, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000090, 0xFC1F07FE, .PS, .PPC32, {}}, - {.PS_NABS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000110, 0xFC1F07FE, .PS, .PPC32, {}}, - {.PS_ABS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0x10000210, 0xFC1F07FE, .PS, .PPC32, {}}, - {.VSPLTW, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000028C, 0xFC1C07FF, .ALTIVEC, .PPC32, {}}, - {.VSPLTH, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000024C, 0xFC1807FF, .ALTIVEC, .PPC32, {}}, - {.VSPLTB, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000020C, 0xFC1007FF, .ALTIVEC, .PPC32, {}}, - {.VEXTRACTUB, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000020D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VEXTRACTUH, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000024D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VEXTRACTUW, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000028D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VEXTRACTD, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x100002CD, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VINSERTB, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000030D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VINSERTH, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000034D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VINSERTW, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x1000038D, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.VINSERTD, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_4, .NONE}, 0x100003CD, 0xFC1007FF, .POWER9, .PPC32, {}}, - {.PS_CMPU0, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0x10000000, 0xFC6007FE, .PS, .PPC32, {}}, - {.PS_CMPU1, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0x10000080, 0xFC6007FE, .PS, .PPC32, {}}, - {.PS_CMPO0, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0x10000040, 0xFC6007FE, .PS, .PPC32, {}}, - {.PS_CMPO1, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0x100000C0, 0xFC6007FE, .PS, .PPC32, {}}, - {.VAND, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000404, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VANDC, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000444, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VOR, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000484, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VORC, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000544, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VNOR, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000504, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VXOR, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004C4, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VEQV, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000684, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VNAND, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000584, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VADDUBM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000000, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDUHM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000040, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDUWM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000080, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDUDM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C0, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VADDFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000000A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUBM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000400, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUHM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000440, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUWM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000480, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUDM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004C0, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSUBFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000004A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDCUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000180, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDCUQ, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000140, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSUBCUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000580, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBCUQ, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000540, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VADDUBS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000200, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDUHS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000240, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDUWS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000280, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDSBS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000300, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDSHS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000340, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VADDSWS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000380, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUBS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000600, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUHS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000640, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBUWS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000680, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBSBS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000700, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBSHS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000740, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSUBSWS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000780, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULESB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000308, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULESH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000348, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULESW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000388, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMULEUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000208, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULEUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000248, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULEUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000288, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMULOSB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000108, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULOSH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000148, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULOSW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000188, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMULOUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000008, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULOUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000048, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMULOUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000088, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMULUWM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000089, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPEQUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000006, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUB_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000406, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000046, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUH_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000446, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000086, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUW_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000486, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQUD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPEQUD_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPNEB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000007, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEB_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000407, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000047, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEH_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000447, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000087, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEW_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000487, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPGTSB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000306, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSB_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000706, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000346, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSH_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000746, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000386, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSW_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000786, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTSD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100003C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPGTSD_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100007C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPGTUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000206, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUB_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000606, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000246, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUH_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000646, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000286, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUW_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000686, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTUD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100002C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPGTUD_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100006C7, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCMPEQFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPEQFP_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGEFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100001C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGEFP_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100005C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100002C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPGTFP_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100006C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPBFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100003C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCMPBFP_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100007C6, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXSB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000102, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXSH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000142, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXSW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000182, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXSD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100001C2, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMAXUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000002, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000042, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000082, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMAXUD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C2, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMAXFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000040A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINSB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000302, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINSH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000342, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINSW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000382, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINSD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100003C2, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMINUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000202, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000242, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000282, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMINUD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100002C2, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMINFP, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000044A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGSB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000502, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGSH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000542, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGSW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000582, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000402, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000442, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VAVGUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000482, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSL, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100001C4, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSR, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100002C4, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSLO, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000040C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRO, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000044C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSLB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000104, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSLH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000144, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSLW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000184, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSLD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100005C4, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSRB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000204, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000244, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000284, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100006C4, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSRAB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000304, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRAH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000344, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRAW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000384, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VSRAD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100003C4, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VRLB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000004, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VRLH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000044, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VRLW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000084, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VRLD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C4, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VBPERMQ, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000054C, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VBPERMD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100005CC, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VMRGHB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000000C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGHH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000004C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGHW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000008C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGLB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000010C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGLH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000014C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGLW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000018C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VMRGEW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000078C, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VMRGOW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000068C, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPKPX, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000030E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKUHUM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000000E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKUWUM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000004E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKUDUM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000044E, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPKUHUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000008E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKUWUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKUDUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004CE, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPKSHUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000010E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKSWUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000014E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKSDUS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000054E, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPKSHSS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x1000018E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKSWSS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100001CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VPKSDSS, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100005CE, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCIPHER, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000508, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCIPHERLAST, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000509, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VNCIPHER, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000548, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VNCIPHERLAST, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000549, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSHASIGMAW, {.VR, .VR, .IMM, .IMM}, {.VRT, .VRA, .NONE, .NONE}, 0x10000682, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VSHASIGMAD, {.VR, .VR, .IMM, .IMM}, {.VRT, .VRA, .NONE, .NONE}, 0x100006C2, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPMSUMB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000408, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPMSUMH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000448, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPMSUMW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000488, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VPMSUMD, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100004C8, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.VCFSX, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_5, .NONE}, 0x1000034A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCFUX, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_5, .NONE}, 0x1000030A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCTSXS, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_5, .NONE}, 0x100003CA, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VCTUXS, {.VR, .VR, .IMM, .NONE}, {.VRT, .VRB, .UIMM_5, .NONE}, 0x1000038A, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.VABSDUB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000403, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VABSDUH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000443, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VABSDUW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000483, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VRLWNM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000185, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VRLDNM, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100001C5, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VRLWMI, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000085, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VRLDMI, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x100000C5, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZB, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000107, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZB_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000507, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZH, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000147, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZH_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000547, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZW, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000187, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VCMPNEZW_DOT, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000587, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VSLV, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000744, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VSRV, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000704, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VMUL10EUQ, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000241, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VMUL10ECUQ, {.VR, .VR, .VR, .NONE}, {.VRT, .VRA, .VRB, .NONE}, 0x10000041, 0xFC0007FF, .POWER9, .PPC32, {}}, - {.VMULESD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100003C8, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULEUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100002C8, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULOSD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100001C8, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULOUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100000C8, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULLD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100001C9, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULHSW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10000389, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULHSD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100003C9, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULHUW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x10000289, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMULHUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100002C9, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVSW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000018B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVUW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000008B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVSD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100001CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100000CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVSQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000010B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVUQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000000B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVESW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000038B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVEUW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000028B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVESD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100003CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVEUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100002CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVESQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000030B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VDIVEUQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000020B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODSW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000078B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODUW, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000068B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODSD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100007CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODUD, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x100006CB, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODSQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000070B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.VMODUQ, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1000060B, 0xFC0007FF, .POWER10, .PPC32, {}}, - {.PS_DIV_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000025, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_SUB_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000029, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_ADD_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x1000002B, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MUL_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x10000033, 0xFC00F83F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MULS0_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x10000019, 0xFC00F83F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MULS1_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x1000001B, 0xFC00F83F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MERGE00_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000421, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MERGE01_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000461, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MERGE10_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x100004A1, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MERGE11_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x100004E1, 0xFC0007FF, .PS, .PPC32, {sets_cr1=true}}, - {.MULHHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000011, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000019, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULHHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000051, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000059, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACHHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000005D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWSU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000099, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100000D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACHHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100000DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULCHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000111, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000119, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULCHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000151, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000159, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACCHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000015D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWSU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000199, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100001D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACCHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100001DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULLHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000311, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000319, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULLHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000351, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000359, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACLHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000035D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWSU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000399, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100003D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACLHWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100003DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000419, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000459, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACHHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000045D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWSUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000499, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACHHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100004D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACHHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100004DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000519, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000559, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACCHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000055D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWSUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000599, 0xFC0007FF, .BASE, .PPC32, {}}, - {.VCMPEQUQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100005C7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACCHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100005D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACCHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100005DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.VCMPGTUQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000687, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000719, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000759, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACLHWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000075D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.VCMPGTSQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000787, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWSUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000799, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MACLHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100007D9, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NMACLHWSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100007DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETEQB_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000601, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETEQH_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000603, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETEQW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000605, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTHU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000609, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTHS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000060B, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000060D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000060F, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTBU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000611, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETGTBS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000613, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTBU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000615, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTBS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000617, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTHU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000619, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTHS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000061B, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000061D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EVSETLTWS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000061F, 0xFC0007FF, .BASE, .PPC32, {}}, - {.PS_DIV, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000024, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_SUB, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000028, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_ADD, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x1000002A, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_MUL, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x10000032, 0xFC00F83E, .PS, .PPC32, {}}, - {.PS_MULS0, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x10000018, 0xFC00F83E, .PS, .PPC32, {}}, - {.PS_MULS1, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0x1000001A, 0xFC00F83E, .PS, .PPC32, {}}, - {.PS_MERGE00, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000420, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_MERGE01, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x10000460, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_MERGE10, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x100004A0, 0xFC0007FE, .PS, .PPC32, {}}, - {.PS_MERGE11, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0x100004E0, 0xFC0007FE, .PS, .PPC32, {}}, - {.PSQ_LX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x1000000C, 0xFC0007FE, .PS, .PPC32, {}}, - {.PSQ_LUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x1000004C, 0xFC0007FE, .PS, .PPC32, {}}, - {.PSQ_STX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x1000000E, 0xFC0007FE, .PS, .PPC32, {}}, - {.PSQ_STUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x1000004E, 0xFC0007FE, .PS, .PPC32, {}}, - {.MULHHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000010, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000018, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULHHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000050, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000058, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACHHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000005C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWSU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000098, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100000D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACHHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100000DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VADDUQM, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000100, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCMPUQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000101, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULCHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000110, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000118, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCMPSQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000141, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULCHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000150, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000158, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACCHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000015C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWSU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000198, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCMPEQUQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100001C7, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100001D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACCHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100001DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCMPGTUQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000287, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCUXWFP, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000030A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000310, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000318, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCSXWFP, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000034A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000350, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000358, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACLHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000035C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCMPGTSQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000387, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCFPUXWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000038A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWSU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000398, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VCFPSXWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100003CA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100003D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACLHWS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100003DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000418, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000458, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACHHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000045C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VMR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000484, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWSUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000498, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACHHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100004D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACHHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100004DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VSUBUQM, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000500, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VNOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000504, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VGBBD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000050C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000518, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000558, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACCHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000055C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWSUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000598, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACCHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100005D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACCHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100005DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000718, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000758, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACLHWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x1000075C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWSUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x10000798, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MACLHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100007D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NMACLHWSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100007DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBZ_L, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x100007EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.VSLDOI, {.VR, .VR, .VR, .IMM}, {.VRT, .VRA, .VRB, .UIMM_4}, 0x1000002C, 0xFC00043F, .ALTIVEC, .PPC32, {}}, - {.MADDLD, {.GPR, .GPR, .GPR, .GPR}, {.RT, .RA, .RC, .RB}, 0x10000033, 0xFC00003F, .POWER9, .PPC64, {}}, - {.MADDHD, {.GPR, .GPR, .GPR, .GPR}, {.RT, .RA, .RC, .RB}, 0x10000030, 0xFC00003F, .POWER9, .PPC64, {}}, - {.MADDHDU, {.GPR, .GPR, .GPR, .GPR}, {.RT, .RA, .RC, .RB}, 0x10000031, 0xFC00003F, .POWER9, .PPC64, {}}, - {.VSEL, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000002A, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VADDECUQ, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000003D, 0xFC00003F, .POWER8, .PPC32, {}}, - {.VADDEUQM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000003C, 0xFC00003F, .POWER8, .PPC32, {}}, - {.VSUBECUQ, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000003F, 0xFC00003F, .POWER8, .PPC32, {}}, - {.VSUBEUQM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000003E, 0xFC00003F, .POWER8, .PPC32, {}}, - {.VMSUMUBM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000024, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMMBM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000025, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMUHM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000026, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMSHM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000028, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMUHS, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000027, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMSHS, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000029, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VMSUMUDM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x10000023, 0xFC00003F, .POWER8, .PPC32, {}}, - {.VPERM, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000002B, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VPERMR, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRB, .VRC}, 0x1000003B, 0xFC00003F, .POWER9, .PPC32, {}}, - {.VMADDFP, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRC, .VRB}, 0x1000002E, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.VNMSUBFP, {.VR, .VR, .VR, .VR}, {.VRT, .VRA, .VRC, .VRB}, 0x1000002F, 0xFC00003F, .ALTIVEC, .PPC32, {}}, - {.PS_SEL_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000002F, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MSUB_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000039, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MADD_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003B, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_NMSUB_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003D, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_NMADD_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003F, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_SUM0_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000015, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_SUM1_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000017, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MADDS0_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000001D, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_MADDS1_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000001F, 0xFC00003F, .PS, .PPC32, {sets_cr1=true}}, - {.PS_SEL, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000002E, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_MSUB, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000038, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_MADD, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003A, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_NMSUB, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003C, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_NMADD, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000003E, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_SUM0, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000014, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_SUM1, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x10000016, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_MADDS0, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000001C, 0xFC00003E, .PS, .PPC32, {}}, - {.PS_MADDS1, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0x1000001E, 0xFC00003E, .PS, .PPC32, {}}, - {.VADDFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642010, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSUBFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642050, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMULFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642090, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMADDFP128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642110, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMADDCFP128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642190, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VNMSUBFP128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642210, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMSUM3FP128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642290, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMSUM4FP128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642310, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMAXFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642390, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMINFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146423D0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VREFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600630, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRSQRTEFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600670, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VEXPTEFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146006B0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VLOGEFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146006F0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VAND128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642410, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VANDC128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642450, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VOR128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642490, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VXOR128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146424D0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VNOR128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642510, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSEL128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642550, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRFIM128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600030, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRFIN128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600070, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRFIP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146000B0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRFIZ128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146000F0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCFPSXWS128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600230, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCFPUXWS128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14600270, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCSXWFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146002B0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCUXWFP128, {.VR128, .VR128, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146002F0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMRGHW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642330, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VMRGLW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642370, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VPERM128, {.VR128, .VR128, .VR128, .VR128}, {.NONE, .NONE, .NONE, .NONE}, 0x14642D90, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSLDOI128, {.VR128, .VR128, .VR128, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x14642010, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRLW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642210, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSLW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642250, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSRW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x14642290, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSRAW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x146422D0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.LXVP, {.VSR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18C30000, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.STXVP, {.VSR, .MEM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18C30001, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.VCMPEQFP128_DOT, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642001, 0xFFFFFFFF, .VMX128, .PPC32, {sets_cr0=true}}, - {.VCMPGEFP128_DOT, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642041, 0xFFFFFFFF, .VMX128, .PPC32, {sets_cr0=true}}, - {.VCMPGTFP128_DOT, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642081, 0xFFFFFFFF, .VMX128, .PPC32, {sets_cr0=true}}, - {.VCMPBFP128_DOT, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x186420C1, 0xFFFFFFFF, .VMX128, .PPC32, {sets_cr0=true}}, - {.VCMPEQUW128_DOT, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642101, 0xFFFFFFFF, .VMX128, .PPC32, {sets_cr0=true}}, - {.VCMPEQFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642000, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCMPGEFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642040, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCMPGTFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642080, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCMPBFP128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x186420C0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VCMPEQUW128, {.VR128, .VR128, .VR128, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642100, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSPLTW128, {.VR128, .VR128, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642330, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VSPLTISW128, {.VR128, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18601370, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VPKD3D128, {.VR128, .VR128, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x18642630, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VUPKD3D128, {.VR128, .VR128, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x186023F0, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VPERMWI128, {.VR128, .VR128, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x18642730, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.VRLIMI128, {.VR128, .VR128, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x18642790, 0xFFFFFFFE, .VMX128, .PPC32, {}}, - {.MULI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x1C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLI, {.GPR, .GPR_OR_ZERO, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x1C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.SFI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x20000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFIC, {.GPR, .GPR, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x20000000, 0xFC000000, .BASE, .PPC32, {}}, - {.DOZI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x24000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CMPLWI, {.CR_FIELD, .GPR, .UIMM, .NONE}, {.BF, .RA, .UI16, .NONE}, 0x28000000, 0xFC600000, .BASE, .PPC32, {}}, - {.CMPLDI, {.CR_FIELD, .GPR, .UIMM, .NONE}, {.BF, .RA, .UI16, .NONE}, 0x28200000, 0xFC600000, .P64, .PPC64, {}}, - {.CMPLI, {.CR_FIELD, .IMM, .GPR, .UIMM}, {.BF, .L_FIELD, .RA, .UI16}, 0x28000000, 0xFC400000, .BASE, .PPC32, {}}, - {.CMPWI, {.CR_FIELD, .GPR, .SIMM, .NONE}, {.BF, .RA, .D16, .NONE}, 0x2C000000, 0xFC600000, .BASE, .PPC32, {}}, - {.CMPDI, {.CR_FIELD, .GPR, .SIMM, .NONE}, {.BF, .RA, .D16, .NONE}, 0x2C200000, 0xFC600000, .P64, .PPC64, {}}, - {.CMPI, {.CR_FIELD, .IMM, .GPR, .SIMM}, {.BF, .L_FIELD, .RA, .D16}, 0x2C000000, 0xFC400000, .BASE, .PPC32, {}}, - {.AI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x30000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBIC, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x30000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDIC, {.GPR, .GPR, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x30000000, 0xFC000000, .BASE, .PPC32, {}}, - {.AI_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x34000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBIC_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x34000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ADDIC_DOT, {.GPR, .GPR, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x34000000, 0xFC000000, .BASE, .PPC32, {sets_cr0=true}}, - {.PSUBI, {.GPR, .GPR, .SIMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x3864FF9C, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.LIL, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x38000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CAL, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x38000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x38000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.PLI, {.GPR, .SIMM, .NONE, .NONE}, {.RT, .D16, .NONE, .NONE}, 0x38000000, 0xFC1F0000, .POWER10, .PPC32, {prefixed=true}}, - {.LI, {.GPR, .SIMM, .NONE, .NONE}, {.RT, .D16, .NONE, .NONE}, 0x38000000, 0xFC1F0000, .BASE, .PPC32, {}}, - {.ADDI, {.GPR, .GPR_OR_ZERO, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x38000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PADDI, {.GPR, .GPR_OR_ZERO, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x38000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LA, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x38000000, 0xFC000000, .BASE, .PPC32, {}}, - {.LIU, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x3C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CAU, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x3C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBIS, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x3C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LIS, {.GPR, .SIMM, .NONE, .NONE}, {.RT, .D16, .NONE, .NONE}, 0x3C000000, 0xFC1F0000, .BASE, .PPC32, {}}, - {.ADDIS, {.GPR, .GPR_OR_ZERO, .SIMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x3C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.BEQ, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41820000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BNE, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40820000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BLT, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41800000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BLE, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40810000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BGT, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41810000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BGE, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40800000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BSO, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41830000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BNS, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40830000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BEQL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41820001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BNEL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40820001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BLTL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41800001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BLEL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40810001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BGTL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41810001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BGEL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40800001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BSOL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x41830001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BNSL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x40830001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZ, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x42400000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZ, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x42000000, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true}}, - {.BDZL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x42400001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDNZL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_BD, .NONE, .NONE, .NONE}, 0x42000001, 0xFFFF0003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDNZTL, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x41000001, 0xFFE00003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZTL, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x41400001, 0xFFE00003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDNZFL, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x40000001, 0xFFE00003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZFL, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x40400001, 0xFFE00003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZF, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x40400000, 0xFFE00003, .BASE, .PPC32, {cond_branch=true}}, - {.BDZT, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x41400000, 0xFFE00003, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZF, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x40000000, 0xFFE00003, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZT, {.CR_BIT, .REL, .NONE, .NONE}, {.BI_FIELD, .BRANCH_BD, .NONE, .NONE}, 0x41000000, 0xFFE00003, .BASE, .PPC32, {cond_branch=true}}, - {.BC, {.BO, .CR_BIT, .REL, .NONE}, {.BO_FIELD, .BI_FIELD, .BRANCH_BD, .NONE}, 0x40000000, 0xFC000003, .BASE, .PPC32, {cond_branch=true}}, - {.BCL, {.BO, .CR_BIT, .REL, .NONE}, {.BO_FIELD, .BI_FIELD, .BRANCH_BD, .NONE}, 0x40000001, 0xFC000003, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BCA, {.BO, .CR_BIT, .REL, .NONE}, {.BO_FIELD, .BI_FIELD, .BRANCH_BD, .NONE}, 0x40000002, 0xFC000003, .BASE, .PPC32, {cond_branch=true, abs_branch=true}}, - {.BCLA, {.BO, .CR_BIT, .REL, .NONE}, {.BO_FIELD, .BI_FIELD, .BRANCH_BD, .NONE}, 0x40000003, 0xFC000003, .BASE, .PPC32, {cond_branch=true, writes_lr=true, abs_branch=true}}, - {.SC, {.IMM, .NONE, .NONE, .NONE}, {.LEV_FIELD, .NONE, .NONE, .NONE}, 0x44000002, 0xFFFFFFFD, .BASE, .PPC32, {}}, - {.SC_HV, {.IMM, .NONE, .NONE, .NONE}, {.LEV_FIELD, .NONE, .NONE, .NONE}, 0x44000022, 0xFFFFFFFD, .HV, .PPC32, {}}, - {.SCV, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x44000021, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.B, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_LI, .NONE, .NONE, .NONE}, 0x48000000, 0xFC000003, .BASE, .PPC32, {branch=true}}, - {.BL, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_LI, .NONE, .NONE, .NONE}, 0x48000001, 0xFC000003, .BASE, .PPC32, {branch=true, writes_lr=true}}, - {.BA, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_LI, .NONE, .NONE, .NONE}, 0x48000002, 0xFC000003, .BASE, .PPC32, {branch=true, abs_branch=true}}, - {.BLA, {.REL, .NONE, .NONE, .NONE}, {.BRANCH_LI, .NONE, .NONE, .NONE}, 0x48000003, 0xFC000003, .BASE, .PPC32, {branch=true, writes_lr=true, abs_branch=true}}, - {.ISYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C00012C, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.NAP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C000364, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.RFEBB, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C000124, 0xFFFFFFFF, .POWER8, .PPC32, {}}, - {.RFDI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C00004E, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.STOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C0002E4, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.RFMCI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C00004C, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.BLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E800020, 0xFFFFFFFF, .BASE, .PPC32, {branch=true}}, - {.BLRL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E800021, 0xFFFFFFFF, .BASE, .PPC32, {branch=true, writes_lr=true}}, - {.BCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E800420, 0xFFFFFFFF, .BASE, .PPC32, {branch=true}}, - {.BCTRL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E800421, 0xFFFFFFFF, .BASE, .PPC32, {branch=true, writes_lr=true}}, - {.BEQLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D820020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BNELR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C820020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BLTLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D800020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BLELR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C810020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BGTLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D810020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BGELR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C800020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BSOLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D830020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BNSLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C830020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BEQCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D820420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BNECTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C820420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BLTCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D800420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BLECTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C810420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BGTCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D810420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BGECTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C800420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BSOCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4D830420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BNSCTR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C830420, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDZLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E400020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E000020, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDZLRL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E400021, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDNZLRL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4E000021, 0xFFFFFFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.RFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C000064, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.RFID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C000024, 0xFFFFFFFE, .SUPV, .PPC64, {}}, - {.HRFID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x4C000224, 0xFFFFFFFE, .HV, .PPC64, {}}, - {.BDNZTLR, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4D000020, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDZTLR, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4D400020, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZFLR, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4C000020, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDZFLR, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4C400020, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true}}, - {.BDNZTLRL, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4D000021, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZTLRL, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4D400021, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDNZFLRL, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4C000021, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BDZFLRL, {.CR_BIT, .NONE, .NONE, .NONE}, {.BI_FIELD, .NONE, .NONE, .NONE}, 0x4C400021, 0xFFE0FFFF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.MCRF, {.CR_FIELD, .CR_FIELD, .NONE, .NONE}, {.BF, .BFA, .NONE, .NONE}, 0x4C000000, 0xFC63FFFF, .BASE, .PPC32, {}}, - {.BCLR, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000020, 0xFC0007FF, .BASE, .PPC32, {cond_branch=true}}, - {.BCLRL, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000021, 0xFC0007FF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BCCTR, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000420, 0xFC0007FF, .BASE, .PPC32, {cond_branch=true}}, - {.BCCTRL, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000421, 0xFC0007FF, .BASE, .PPC32, {cond_branch=true, writes_lr=true}}, - {.BCTAR, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000460, 0xFC0007FF, .POWER8, .PPC32, {cond_branch=true}}, - {.BCTARL, {.BO, .CR_BIT, .BH, .NONE}, {.BO_FIELD, .BI_FIELD, .BH_FIELD, .NONE}, 0x4C000461, 0xFC0007FF, .POWER8, .PPC32, {cond_branch=true, writes_lr=true}}, - {.CRAND, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000202, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRNAND, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C0001C2, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CROR, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000382, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRNOR, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000042, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRXOR, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000182, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CREQV, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000242, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRANDC, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000102, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRORC, {.CR_BIT, .CR_BIT, .CR_BIT, .NONE}, {.BT, .BA, .BB, .NONE}, 0x4C000342, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CRNOT, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RFCI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.RFSCV, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RFSVC, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RFGI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.ICS, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CRCLR, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DNH, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.CRSET, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.URFID, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DOZE, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CRMOVE, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLEEP, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RVWINKLE, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x4C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDPCIS, {.GPR, .SIMM, .NONE, .NONE}, {.RT, .D16, .NONE, .NONE}, 0x4C000004, 0xFC00003E, .POWER9, .PPC32, {}}, - {.INSLWI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x5083C216, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.INSRWI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x5083A216, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.RLWIMI, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH5, .MB5}, 0x50000000, 0xFC000001, .BASE, .PPC32, {}}, - {.RLWIMI_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH5, .MB5}, 0x50000001, 0xFC000001, .BASE, .PPC32, {sets_cr0=true}}, - {.SLWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x54832036, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.SRWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x5483E13E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.CLRRWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x54830036, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.CLRLWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x5483013E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.EXTLWI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x54834006, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.EXTRWI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x5483673E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.ROTLWI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x5483203E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.RLWINM, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH5, .MB5}, 0x54000000, 0xFC000001, .BASE, .PPC32, {}}, - {.RLWINM_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH5, .MB5}, 0x54000001, 0xFC000001, .BASE, .PPC32, {sets_cr0=true}}, - {.ROTLW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x5C83283E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.ROTRW, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x5C83283E, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.RLWNM, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB5}, 0x5C000000, 0xFC000001, .BASE, .PPC32, {}}, - {.RLWNM_DOT, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB5}, 0x5C000001, 0xFC000001, .BASE, .PPC32, {sets_cr0=true}}, - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x60000000, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.ORIL, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x60000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ORI, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x60000000, 0xFC000000, .BASE, .PPC32, {}}, - {.ORIU, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x64000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ORIS, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x64000000, 0xFC000000, .BASE, .PPC32, {}}, - {.XNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x68000000, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.XORIL, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x68000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.XORI, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x68000000, 0xFC000000, .BASE, .PPC32, {}}, - {.XORIU, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x6C000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.XORIS, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x6C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.ANDIL_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x70000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ANDI_DOT, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x70000000, 0xFC000000, .BASE, .PPC32, {sets_cr0=true}}, - {.ANDIU_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .D16, .NONE}, 0x74000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ANDIS_DOT, {.GPR, .GPR, .UIMM, .NONE}, {.RA, .RS, .UI16, .NONE}, 0x74000000, 0xFC000000, .BASE, .PPC32, {sets_cr0=true}}, - {.ROTLDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642801, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.ROTRDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642801, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.CLRLDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642801, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.SRDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642801, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.EXTRDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642801, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.CLRRDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642805, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.SLDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642805, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.EXTLDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642805, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.CLRLSLDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642809, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.INSRDI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7864280D, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.ROTLD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642811, 0xFFFFFFFF, .P64, .PPC64, {}}, - {.SLDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x788326E4, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.SRDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7883E102, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.CLRRDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x788306E4, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.CLRLDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78830100, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.EXTLDI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x788340C4, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.EXTRDI, {.GPR, .GPR, .IMM, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0x78836720, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.ROTLD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78832810, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.ROTLDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78832000, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.ROTRDI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7883E002, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.CLRLSLDI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x78642808, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.INSRDI, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7864280C, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.RLDCL, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB6}, 0x78000010, 0xFC00003F, .P64, .PPC64, {}}, - {.RLDCL_DOT, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB6}, 0x78000011, 0xFC00003F, .P64, .PPC64, {sets_cr0=true}}, - {.RLDCR, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB6}, 0x78000012, 0xFC00003F, .P64, .PPC64, {}}, - {.RLDCR_DOT, {.GPR, .GPR, .GPR, .IMM}, {.RA, .RS, .RB, .MB6}, 0x78000013, 0xFC00003F, .P64, .PPC64, {sets_cr0=true}}, - {.RLDICL, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000000, 0xFC00001D, .P64, .PPC64, {}}, - {.RLDICL_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000001, 0xFC00001D, .P64, .PPC64, {sets_cr0=true}}, - {.RLDICR, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000004, 0xFC00001D, .P64, .PPC64, {}}, - {.RLDICR_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000005, 0xFC00001D, .P64, .PPC64, {sets_cr0=true}}, - {.RLDIC, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000008, 0xFC00001D, .P64, .PPC64, {}}, - {.RLDIC_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x78000009, 0xFC00001D, .P64, .PPC64, {sets_cr0=true}}, - {.RLDIMI, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x7800000C, 0xFC00001D, .P64, .PPC64, {}}, - {.RLDIMI_DOT, {.GPR, .GPR, .IMM, .IMM}, {.RA, .RS, .SH6, .MB6}, 0x7800000D, 0xFC00001D, .P64, .PPC64, {sets_cr0=true}}, - {.SYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0004AC, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.LWSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2004AC, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.PTESYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4004AC, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.EIEIO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0006AC, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.MSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0004AC, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00046C, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.XXMTACC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C010162, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXMFACC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C000162, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXSETACCZ, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C030162, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.COPY, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C23260C, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.PASTE_DOT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C20070D, 0xFFFFFFFF, .POWER10, .PPC32, {sets_cr0=true}}, - {.TBEGIN_DOT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00051D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TEND_DOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00055D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TABORT_DOT, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03071D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TABORTWC_DOT, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03261D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TABORTWCI_DOT, {.IMM, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03269D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TABORTDC_DOT, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03265D, 0xFFFFFFFF, .HTM, .PPC64, {sets_cr0=true}}, - {.TABORTDCI_DOT, {.IMM, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0326DD, 0xFFFFFFFF, .HTM, .PPC64, {sets_cr0=true}}, - {.TRECLAIM_DOT, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03075D, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TRECHKPT_DOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0007DD, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TSUSPEND_DOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0005DD, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TRESUME_DOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2005DD, 0xFFFFFFFF, .HTM, .PPC32, {sets_cr0=true}}, - {.TCHECK, {.CR_FIELD, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00059C, 0xFFFFFFFF, .HTM, .PPC32, {}}, - {.MSGSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0006EC, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.ISEL, {.GPR, .GPR_OR_ZERO, .GPR, .CR_BIT}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64299E, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.DCBTT, {.MEM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E03222C, 0xFFFFFFFF, .POWER8, .PPC32, {}}, - {.DCBTSTT, {.MEM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E0321EC, 0xFFFFFFFF, .POWER8, .PPC32, {}}, - {.SETB, {.GPR, .CR_FIELD, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4C0100, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.MCRXRX, {.CR_FIELD, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C000480, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.LXVPX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC42A9A, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.STXVPX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC42B9A, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.DCCCI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00038C, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.ICCCI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00078C, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.TLBRE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C000764, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.TLBWE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0007A4, 0xFFFFFFFF, .SUPV, .PPC32, {}}, - {.CPABORT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00068C, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.MFVSRLD, {.GPR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C230267, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.MTVSRDD, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C232366, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.MTVSRWS, {.VSR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C230326, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.EXTSWSLI_DOT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C8306F5, 0xFFFFFFFF, .POWER9, .PPC64, {sets_cr0=true}}, - {.ISELLT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64281E, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.ISELGT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64285E, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.ISELEQ, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64289E, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.MR_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C601B79, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.NOT_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C6018F9, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.TRAP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7FE00008, 0xFFFFFFFF, .BASE, .PPC32, {}}, - {.SUB_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652051, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUB_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652451, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBC_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652011, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBC_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652411, 0xFFFFFFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.ICBTLS, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642BCC, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.ICBLC, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6429CC, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.DCBST, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03206C, 0xFFFFFFFF, .CACHE, .PPC32, {}}, - {.MBAR, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6006AC, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.MTDCR, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C830386, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.MFDCR, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C640286, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.TLBILXVA, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C632024, 0xFFFFFFFF, .BOOKE, .PPC32, {}}, - {.PDEPD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832938, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.PEXTD, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832978, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.CNTLZDM, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832876, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.CNTTZDM, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832C76, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.CFUGED, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C8329B8, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.BRH, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C8301B6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.BRW, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C830136, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.BRD, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C830176, 0xFFFFFFFF, .POWER10, .PPC64, {}}, - {.LVEBX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44280D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVEHX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44284D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVEWX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44288D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4428CD, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4428CF, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVLX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D0D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVRX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D4D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVLXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D0F, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.LVRXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D4F, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVEBX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44290D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVEHX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44294D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVEWX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C44298D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4429CD, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C4429CF, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVLX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D8D, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVRX128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442DCD, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVLXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442D8F, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.STVRXL128, {.VR128, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C442DCF, 0xFFFFFFFF, .VMX128, .PPC32, {}}, - {.WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00003C, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.SLBIA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0003E4, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.SLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0002A4, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.LBZCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642EAA, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.LHZCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642E6A, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.LWZCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642E2A, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.LDCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642EEA, 0xFFFFFFFE, .HV, .PPC64, {}}, - {.STBCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642FAA, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.STHCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642F6A, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.STWCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642F2A, 0xFFFFFFFE, .HV, .PPC32, {}}, - {.STDCIX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642FEA, 0xFFFFFFFE, .HV, .PPC64, {}}, - {.ADDG6S, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642894, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.CBCDTD, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C830274, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.CDTBCD, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C830234, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.LXVRBX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03201A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVRHX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03205A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVRWX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03209A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVRDX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0320DA, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRBX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03211A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRHX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03215A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRWX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C03219A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRDX, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0321DA, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.DCBI, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0323AC, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.ICBIEP, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0327BE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.DCBTEP, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64027E, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.DCBTSTEP, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6401FE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.LBEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6428BE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.LHEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642A3E, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.LWEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64283E, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.STBEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6429BE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.STHEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C642B3E, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.STWEPX, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64293E, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.LFDEPX, {.FPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2324BE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.STFDEPX, {.FPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2325BE, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.TLBSX, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C032724, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.WRTEE, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C600106, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.WRTEEI, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C008146, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.TLBIVAX, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C032624, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.TLBILX, {.IMM, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C032024, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.TLBLD, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C001FA4, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.TLBLI, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C001FE4, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.MFPMR, {.GPR, .SPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64029C, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.MTPMR, {.SPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64039C, 0xFFFFFFFE, .SUPV, .PPC32, {}}, - {.DST, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0322AC, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.DSTT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E0322AC, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.DSTST, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C0322EC, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.DSTSTT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E0322EC, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.DSS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C00066C, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.DSSALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E00066C, 0xFFFFFFFE, .ALTIVEC, .PPC32, {}}, - {.MTFPRD, {.FPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C230166, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.MFFPRD, {.GPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C230066, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.MTFPRWA, {.FPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2301A6, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.MTFPRWZ, {.FPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2301E6, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.MFFPRWZ, {.GPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C2300E6, 0xFFFFFFFE, .POWER8, .PPC32, {}}, - {.EXTSWSLI, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C8306F4, 0xFFFFFFFE, .POWER9, .PPC64, {}}, - {.TWEQ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832008, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.TWNE, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7F032008, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.TWGT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7D032008, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.TWLT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E032008, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.TDEQ, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C832088, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.TDNE, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7F032088, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.TDGT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7D032088, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.TDLT, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7E032088, 0xFFFFFFFE, .P64, .PPC64, {}}, - {.LWAT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6400CC, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.LDAT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6404CC, 0xFFFFFFFE, .POWER9, .PPC64, {}}, - {.STWAT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C64058C, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.STDAT, {.GPR, .GPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6405CC, 0xFFFFFFFE, .POWER9, .PPC64, {}}, - {.LXVPRL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3249A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVPRLL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC324DA, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVPRL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3259A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVPRLL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC325DA, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVRL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3241A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.LXVRLL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3245A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3251A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.STXVRLL, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7CC3255A, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.MR, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C601B78, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.NOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C6018F8, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.SUB, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652050, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.SUB_O, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652450, 0xFFFFFFFE, .BASE, .PPC32, {has_oe=true}}, - {.SUBC, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652010, 0xFFFFFFFE, .BASE, .PPC32, {}}, - {.SUBC_O, {.GPR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C652410, 0xFFFFFFFE, .BASE, .PPC32, {has_oe=true}}, - {.TLBIEL, {.GPR, .NONE, .NONE, .NONE}, {.RB, .NONE, .NONE, .NONE}, 0x7C000224, 0xFFFF07FF, .SUPV, .PPC32, {}}, - {.SLBIE, {.GPR, .NONE, .NONE, .NONE}, {.RB, .NONE, .NONE, .NONE}, 0x7C000364, 0xFFFF07FF, .SUPV, .PPC32, {}}, - {.MTCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6FF120, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MFDSCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7102A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MTDSCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7103A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MFCFAR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7C02A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MTCFAR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7C03A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MFPPR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C60E2A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MTPPR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C60E3A6, 0xFC1FFFFF, .POWER8, .PPC32, {}}, - {.MFDEC, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7602A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTDEC, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7603A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFSRR0, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7A02A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTSRR0, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7A03A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFSRR1, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7B02A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTSRR1, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7B03A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFDAR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7302A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTDAR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7303A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFDSISR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7202A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTDSISR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7203A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFASR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7842A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTASR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7843A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFAMR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7D02A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTAMR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7D03A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFTCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7AF2A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTTCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7AF3A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFESR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C74F2A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTESR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C74F3A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFDCCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7AFAA6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTDCCR, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7AFBA6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTBR0, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C602386, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTBR1, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C612386, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTTBL, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7C43A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MTTBU, {.GPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C7D43A6, 0xFC1FFFFF, .SUPV, .PPC32, {}}, - {.MFLR, {.GPR, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x7C0802A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MTLR, {.GPR, .NONE, .NONE, .NONE}, {.RS, .NONE, .NONE, .NONE}, 0x7C0803A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MFCTR, {.GPR, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x7C0902A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MTCTR, {.GPR, .NONE, .NONE, .NONE}, {.RS, .NONE, .NONE, .NONE}, 0x7C0903A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MFXER, {.GPR, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x7C0102A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MTXER, {.GPR, .NONE, .NONE, .NONE}, {.RS, .NONE, .NONE, .NONE}, 0x7C0103A6, 0xFC1FFFFF, .BASE, .PPC32, {}}, - {.MFCR, {.GPR, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x7C000026, 0xFC1FFFFE, .BASE, .PPC32, {}}, - {.MTMSR, {.GPR, .NONE, .NONE, .NONE}, {.RS, .NONE, .NONE, .NONE}, 0x7C000124, 0xFC1FFFFE, .SUPV, .PPC32, {}}, - {.MFMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x7C0000A6, 0xFC1FFFFE, .SUPV, .PPC32, {}}, - {.MTMSRD, {.GPR, .NONE, .NONE, .NONE}, {.RS, .NONE, .NONE, .NONE}, 0x7C000164, 0xFC1FFFFE, .SUPV, .PPC64, {}}, - {.DARN, {.GPR, .IMM, .NONE, .NONE}, {.RT, .L_FIELD, .NONE, .NONE}, 0x7C0005E6, 0xFC1CFFFE, .POWER9, .PPC32, {}}, - {.ADDME_O_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0005D5, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.ADDZE_O_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000595, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBFME_O_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0005D1, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBFZE_O_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000591, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.NEG_O_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0004D1, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.EXTSB_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000775, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.EXTSH_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000735, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.EXTSW_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C0007B5, 0xFC00FFFF, .P64, .PPC64, {sets_cr0=true}}, - {.CNTLZW_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000035, 0xFC00FFFF, .BASE, .PPC32, {sets_cr0=true}}, - {.CNTLZD_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000075, 0xFC00FFFF, .P64, .PPC64, {sets_cr0=true}}, - {.CNTTZW_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000435, 0xFC00FFFF, .POWER9, .PPC32, {sets_cr0=true}}, - {.CNTTZD_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000475, 0xFC00FFFF, .POWER9, .PPC64, {sets_cr0=true}}, - {.TLBIE, {.GPR, .GPR, .NONE, .NONE}, {.RS, .RB, .NONE, .NONE}, 0x7C000264, 0xFC1F07FF, .SUPV, .PPC32, {}}, - {.SLBMTE, {.GPR, .GPR, .NONE, .NONE}, {.RS, .RB, .NONE, .NONE}, 0x7C000324, 0xFC1F07FF, .SUPV, .PPC32, {}}, - {.SLBMFEE, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RB, .NONE, .NONE}, 0x7C000726, 0xFC1F07FF, .SUPV, .PPC32, {}}, - {.SLBMFEV, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RB, .NONE, .NONE}, 0x7C0006A6, 0xFC1F07FF, .SUPV, .PPC32, {}}, - {.MFSR, {.GPR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6404A6, 0xFC10FFFE, .SUPV, .PPC32, {}}, - {.MTSR, {.IMM, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C6401A4, 0xFC10FFFE, .SUPV, .PPC32, {}}, - {.ADDME_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0001D5, 0xFC00FBFF, .BASE, .PPC32, {sets_cr0=true}}, - {.ADDME_O, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0005D4, 0xFC00FFFE, .BASE, .PPC32, {has_oe=true}}, - {.ADDZE_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000195, 0xFC00FBFF, .BASE, .PPC32, {sets_cr0=true}}, - {.ADDZE_O, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000594, 0xFC00FFFE, .BASE, .PPC32, {has_oe=true}}, - {.SUBFME_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0001D1, 0xFC00FBFF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBFME_O, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0005D0, 0xFC00FFFE, .BASE, .PPC32, {has_oe=true}}, - {.SUBFZE_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000191, 0xFC00FBFF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBFZE_O, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000590, 0xFC00FFFE, .BASE, .PPC32, {has_oe=true}}, - {.NEG_DOT, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0000D1, 0xFC00FBFF, .BASE, .PPC32, {sets_cr0=true}}, - {.NEG_O, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0004D0, 0xFC00FFFE, .BASE, .PPC32, {has_oe=true}}, - {.EXTSB, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000774, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.EXTSH, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000734, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.EXTSW, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C0007B4, 0xFC00FFFE, .P64, .PPC64, {}}, - {.CNTLZW, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000034, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.CNTLZD, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000074, 0xFC00FFFE, .P64, .PPC64, {}}, - {.CNTTZW, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000434, 0xFC00FFFE, .POWER9, .PPC32, {}}, - {.CNTTZD, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000474, 0xFC00FFFE, .POWER9, .PPC64, {}}, - {.POPCNTB, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C0000F4, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.POPCNTW, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C0002F4, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.POPCNTD, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C0003F4, 0xFC00FFFE, .P64, .PPC64, {}}, - {.PRTYW, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000134, 0xFC00FFFE, .BASE, .PPC32, {}}, - {.PRTYD, {.GPR, .GPR, .NONE, .NONE}, {.RA, .RS, .NONE, .NONE}, 0x7C000174, 0xFC00FFFE, .P64, .PPC64, {}}, - {.MFSRIN, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C602526, 0xFC00FFFE, .SUPV, .PPC32, {}}, - {.MTSRIN, {.GPR, .GPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x7C8019E4, 0xFC00FFFE, .SUPV, .PPC32, {}}, - {.ADDME, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0001D4, 0xFC00FBFE, .BASE, .PPC32, {}}, - {.ADDZE, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000194, 0xFC00FBFE, .BASE, .PPC32, {}}, - {.SUBFME, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0001D0, 0xFC00FBFE, .BASE, .PPC32, {}}, - {.SUBFZE, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C000190, 0xFC00FBFE, .BASE, .PPC32, {}}, - {.NEG, {.GPR, .GPR, .NONE, .NONE}, {.RT, .RA, .NONE, .NONE}, 0x7C0000D0, 0xFC00FBFE, .BASE, .PPC32, {}}, - {.MTOCRF, {.IMM, .GPR, .NONE, .NONE}, {.CRM, .RS, .NONE, .NONE}, 0x7C100120, 0xFC101FFE, .BASE, .PPC32, {}}, - {.MFOCRF, {.GPR, .IMM, .NONE, .NONE}, {.RT, .CRM, .NONE, .NONE}, 0x7C100026, 0xFC101FFE, .BASE, .PPC32, {}}, - {.CMPEQB, {.CR_FIELD, .GPR, .GPR, .NONE}, {.BF, .RA, .RB, .NONE}, 0x7C0001C0, 0xFC6007FE, .POWER9, .PPC32, {}}, - {.MTCRF, {.IMM, .GPR, .NONE, .NONE}, {.CRM, .RS, .NONE, .NONE}, 0x7C000120, 0xFC100FFE, .BASE, .PPC32, {}}, - {.DCBZ, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C0007EC, 0xFE2007FE, .BASE, .PPC32, {}}, - {.DCBZL, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C2007EC, 0xFE2007FE, .POWER8, .PPC32, {}}, - {.CMPW, {.CR_FIELD, .GPR, .GPR, .NONE}, {.BF, .RA, .RB, .NONE}, 0x7C000000, 0xFC6007FE, .BASE, .PPC32, {}}, - {.CMPLW, {.CR_FIELD, .GPR, .GPR, .NONE}, {.BF, .RA, .RB, .NONE}, 0x7C000040, 0xFC6007FE, .BASE, .PPC32, {}}, - {.CMPD, {.CR_FIELD, .GPR, .GPR, .NONE}, {.BF, .RA, .RB, .NONE}, 0x7C200000, 0xFC6007FE, .P64, .PPC64, {}}, - {.CMPLD, {.CR_FIELD, .GPR, .GPR, .NONE}, {.BF, .RA, .RB, .NONE}, 0x7C200040, 0xFC6007FE, .P64, .PPC64, {}}, - {.STBCX_DOT, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00056D, 0xFC0007FF, .POWER8, .PPC32, {sets_cr0=true}}, - {.STHCX_DOT, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0005AD, 0xFC0007FF, .POWER8, .PPC32, {sets_cr0=true}}, - {.STWCX_DOT, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00012D, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.STDCX_DOT, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0001AD, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.STQCX_DOT, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00016D, 0xFC0007FF, .POWER8, .PPC64, {sets_cr0=true}}, - {.ADD_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000615, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.ADDC_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000415, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.ADDE_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000515, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBF_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000451, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBFC_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000411, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.SUBFE_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000511, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.MULHW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000097, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.MULHWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000017, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.MULLW_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D7, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.MULLD_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D3, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true, has_oe=true}}, - {.MULHD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000093, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.MULHDU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000013, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.DIVW_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D7, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.DIVWU_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000797, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.DIVD_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D3, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true, has_oe=true}}, - {.DIVDU_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000793, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true, has_oe=true}}, - {.DIVWE_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000757, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.DIVWEU_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000717, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.DIVDE_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000753, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.DIVDEU_O_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000713, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true, has_oe=true}}, - {.AND_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000039, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.OR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000379, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.XOR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000279, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.NAND_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0003B9, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.NOR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0000F9, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.EQV_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000239, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.ANDC_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000079, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.ORC_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000339, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SLW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000031, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SRW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000431, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SRAW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000631, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SRAWI_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RA, .RS, .SH5, .NONE}, 0x7C000671, 0xFC0007FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SLD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000037, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.SRD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000437, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.SRAD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000635, 0xFC0007FF, .P64, .PPC64, {sets_cr0=true}}, - {.CMP, {.CR_FIELD, .IMM, .GPR, .GPR}, {.BF, .L_FIELD, .RA, .RB}, 0x7C000000, 0xFC4007FE, .BASE, .PPC32, {}}, - {.CMPL, {.CR_FIELD, .IMM, .GPR, .GPR}, {.BF, .L_FIELD, .RA, .RB}, 0x7C000040, 0xFC4007FE, .BASE, .PPC32, {}}, - {.CMPRB, {.CR_FIELD, .IMM, .GPR, .GPR}, {.BF, .L_FIELD, .RA, .RB}, 0x7C000180, 0xFC4007FE, .POWER9, .PPC32, {}}, - {.LVX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0000CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVXL, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0002CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVEBX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00000E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVEHX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00004E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVEWX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00008E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVSL, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00000C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.LVSR, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00004C, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.STVX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0001CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.STVXL, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0003CE, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.STVEBX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00010E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.STVEHX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00014E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.STVEWX, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00018E, 0xFC0007FF, .ALTIVEC, .PPC32, {}}, - {.SF_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000011, 0xFC0007FF, .BASE, .PPC32, {}}, - {.A_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000015, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SL_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000031, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CNTLZ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000035, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MASKG_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00003B, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBWUS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000091, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBDUS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000491, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFUS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000091, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DLMZB_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00009D, 0xFC0007FF, .BOOKE, .PPC32, {}}, - {.MUL_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0000D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000111, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000115, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ERATSX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000127, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.SLQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000131, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SLE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000133, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SLIQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000171, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ICBLQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00018D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFZE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000191, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AZE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000195, 0xFC0007FF, .BASE, .PPC32, {}}, - {.LDAWX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001A9, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.SLLQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001B1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SLEQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001B3, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFME_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AME_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D5, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SLLIQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001F1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MFDCRX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000207, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.DOZ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000211, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CAX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000215, 0xFC0007FF, .BASE, .PPC32, {}}, - {.LSCBX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00022B, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MFDCR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000287, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.DIV_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000297, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ABS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MTDCRX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000307, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.PBT_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000329, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ICSWX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00032D, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.DCBLQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00034D, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MTDCR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000387, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.NABS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFCO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000411, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000411, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBCO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000411, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ADDCO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000415, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000415, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000431, 0xFC0007FF, .BASE, .PPC32, {}}, - {.RRIB_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000433, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MASKIR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00043B, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000451, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000451, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NEGO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000511, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000511, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ADDEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000515, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000515, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000531, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000533, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRIQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000571, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFZEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000591, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFZEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000591, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ADDZEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000595, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AZEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000595, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRLQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005B1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SREQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005B3, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SUBFMEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SFMEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULLDO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D3, 0xFC0007FF, .P64, .PPC64, {}}, - {.ADDMEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D5, 0xFC0007FF, .BASE, .PPC32, {}}, - {.AMEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D5, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULLWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.MULSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.TSR_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005DD, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRLIQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005F1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DOZO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000611, 0xFC0007FF, .BASE, .PPC32, {}}, - {.ADDO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000615, 0xFC0007FF, .BASE, .PPC32, {}}, - {.CAXO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000615, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRA_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000631, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SRAI_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000671, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000697, 0xFC0007FF, .BASE, .PPC32, {}}, - {.TLBSRX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006A5, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.ABSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVDEUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000713, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.DIVWEUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000717, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.TLBSX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000725, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.SRAQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000731, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SREA_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000733, 0xFC0007FF, .BASE, .PPC32, {}}, - {.EXTS_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000735, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVDEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000753, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.DIVWEO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000757, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.ICSWEPX_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00076D, 0xFC0007FF, .POWER8, .PPC32, {}}, - {.SRAIQ_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000771, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVDUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000793, 0xFC0007FF, .P64, .PPC64, {}}, - {.DIVWUO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000797, 0xFC0007FF, .BASE, .PPC32, {}}, - {.SLBFEE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007A7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.NABSO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D1, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DIVDO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D3, 0xFC0007FF, .P64, .PPC64, {}}, - {.DIVWO_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D7, 0xFC0007FF, .BASE, .PPC32, {}}, - {.LBZX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0000AE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LBZUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0000EE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHZX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00022E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHZUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00026E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHAX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0002AE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHAUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0002EE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWZX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00002E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWZUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00006E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWAX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0002AA, 0xFC0007FE, .P64, .PPC64, {}}, - {.LWAUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0002EA, 0xFC0007FE, .P64, .PPC64, {}}, - {.LDX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00002A, 0xFC0007FE, .P64, .PPC64, {}}, - {.LDUX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00006A, 0xFC0007FE, .P64, .PPC64, {}}, - {.LHBRX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00062C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWBRX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00042C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LDBRX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C000428, 0xFC0007FE, .POWER8, .PPC64, {}}, - {.LSWI, {.GPR, .GPR, .IMM, .NONE}, {.RT, .RA, .NB_FIELD, .NONE}, 0x7C0004AA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LSWX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00042A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STBX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0001AE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STBUX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0001EE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STHX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00032E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STHUX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00036E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00012E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWUX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00016E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STDX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00012A, 0xFC0007FE, .P64, .PPC64, {}}, - {.STDUX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00016A, 0xFC0007FE, .P64, .PPC64, {}}, - {.STHBRX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00072C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWBRX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00052C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STDBRX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C000528, 0xFC0007FE, .POWER8, .PPC64, {}}, - {.STSWI, {.GPR, .GPR, .IMM, .NONE}, {.RS, .RA, .NB_FIELD, .NONE}, 0x7C0005AA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STSWX, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00052A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LBARX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C000068, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.LHARX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0000E8, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.LWARX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C000028, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LDARX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0000A8, 0xFC0007FE, .P64, .PPC64, {}}, - {.LQARX, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C000228, 0xFC0007FE, .POWER8, .PPC64, {}}, - {.ADD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000215, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.ADD_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000614, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.ADDC_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000015, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.ADDC_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000414, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.ADDE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000115, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.ADDE_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000514, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.ADDEX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000154, 0xFC0007FE, .POWER9, .PPC32, {}}, - {.SUBF_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000051, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBF_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000450, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.SUBFC_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000011, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBFC_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000410, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.SUBFE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000111, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.SUBFE_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000510, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.MULHW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000096, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULHWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000016, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D7, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.MULLW_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D6, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.MULLD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D3, 0xFC0003FF, .P64, .PPC64, {sets_cr0=true}}, - {.MULLD_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D2, 0xFC0007FE, .P64, .PPC64, {has_oe=true}}, - {.MULHD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000092, 0xFC0007FE, .P64, .PPC64, {}}, - {.MULHDU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000012, 0xFC0007FE, .P64, .PPC64, {}}, - {.DIVW_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D7, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVW_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D6, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.DIVWU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000397, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVWU_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000796, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.DIVD_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D3, 0xFC0003FF, .P64, .PPC64, {sets_cr0=true}}, - {.DIVD_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D2, 0xFC0007FE, .P64, .PPC64, {has_oe=true}}, - {.DIVDU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000393, 0xFC0003FF, .P64, .PPC64, {sets_cr0=true}}, - {.DIVDU_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000792, 0xFC0007FE, .P64, .PPC64, {has_oe=true}}, - {.DIVWE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000357, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVWE_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000756, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.DIVWEU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000317, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVWEU_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000716, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.DIVDE_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000353, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVDE_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000752, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.DIVDEU_DOT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000313, 0xFC0003FF, .BASE, .PPC32, {sets_cr0=true}}, - {.DIVDEU_O, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000712, 0xFC0007FE, .BASE, .PPC32, {has_oe=true}}, - {.MODSW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000616, 0xFC0007FE, .POWER9, .PPC32, {}}, - {.MODUW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000216, 0xFC0007FE, .POWER9, .PPC32, {}}, - {.MODSD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000612, 0xFC0007FE, .POWER9, .PPC64, {}}, - {.MODUD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000212, 0xFC0007FE, .POWER9, .PPC64, {}}, - {.TW, {.IMM, .GPR, .GPR, .NONE}, {.TO_FIELD, .RA, .RB, .NONE}, 0x7C000008, 0xFC0007FE, .BASE, .PPC32, {}}, - {.TD, {.IMM, .GPR, .GPR, .NONE}, {.TO_FIELD, .RA, .RB, .NONE}, 0x7C000088, 0xFC0007FE, .P64, .PPC64, {}}, - {.AND, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000038, 0xFC0007FE, .BASE, .PPC32, {}}, - {.OR, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000378, 0xFC0007FE, .BASE, .PPC32, {}}, - {.XOR, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000278, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NAND, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0003B8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NOR, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0000F8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.EQV, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000238, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ANDC, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000078, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ORC, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000338, 0xFC0007FE, .BASE, .PPC32, {}}, - {.BPERMD, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0001F8, 0xFC0007FE, .P64, .PPC64, {}}, - {.CMPB, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C0003F8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLW, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000030, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRW, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000430, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRAW, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000630, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRAWI, {.GPR, .GPR, .IMM, .NONE}, {.RA, .RS, .SH5, .NONE}, 0x7C000670, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLD, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000036, 0xFC0007FE, .P64, .PPC64, {}}, - {.SRD, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000436, 0xFC0007FE, .P64, .PPC64, {}}, - {.SRAD, {.GPR, .GPR, .GPR, .NONE}, {.RA, .RS, .RB, .NONE}, 0x7C000634, 0xFC0007FE, .P64, .PPC64, {}}, - {.SRADI_DOT, {.GPR, .GPR, .IMM, .NONE}, {.RA, .RS, .SH6, .NONE}, 0x7C000675, 0xFC0007FD, .P64, .PPC64, {sets_cr0=true}}, - {.LFSX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00042E, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFSUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00046E, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFDX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0004AE, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFDUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0004EE, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFIWAX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0006AE, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFIWZX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0006EE, 0xFC0007FE, .FP, .PPC32, {}}, - {.LFDPX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00062E, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFSX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00052E, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFSUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00056E, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFDX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0005AE, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFDUX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0005EE, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFIWX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C0007AE, 0xFC0007FE, .FP, .PPC32, {}}, - {.STFDPX, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_X, .NONE, .NONE}, 0x7C00072E, 0xFC0007FE, .FP, .PPC32, {}}, - {.MFSPR, {.GPR, .SPR, .NONE, .NONE}, {.RT, .SPR_FIELD, .NONE, .NONE}, 0x7C0002A6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTSPR, {.SPR, .GPR, .NONE, .NONE}, {.SPR_FIELD, .RS, .NONE, .NONE}, 0x7C0003A6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFTB, {.GPR, .SPR, .NONE, .NONE}, {.RT, .SPR_FIELD, .NONE, .NONE}, 0x7C0002E6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBT, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C00022C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTST, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C0001EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBA, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C0005EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBF, {.MEM, .NONE, .NONE, .NONE}, {.OFFSET_BASE_X, .NONE, .NONE, .NONE}, 0x7C0000AC, 0xFC0007FE, .BASE, .PPC32, {}}, - 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{.SFE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000110, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000114, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTSTLSE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00011C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTSLE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000126, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ERATSX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000126, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.STX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00012E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000130, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000132, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STDEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00013A, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.DCBTLS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00014C, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.DCBTLSE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00015C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTVSRD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000166, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ERATRE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000166, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.WCHKALL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00016C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.STUX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00016E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLIQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000170, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFZE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000190, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AZE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000194, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTVSRWA, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001A6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ERATWE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001A6, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.SLLQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001B0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLEQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001B2, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFME, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AME, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICBLCE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTSRI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001E4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTVSRWZ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001E6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTSTCT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTSTDS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLLIQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001F0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFDCRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000206, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.LVEXBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00020A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVEPXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00020E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DOZ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000210, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CAX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000214, 0xFC0007FE, .BASE, .PPC32, {}}, - {.EHPRIV, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00021C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.MFAPIDI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000226, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LSCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00022A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTCT, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00022C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBTDS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00022C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFDCRUX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000246, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LVEXHX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00024A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00024E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFBHRBE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00025C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.TLBI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000264, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ECIWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00026C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVEXWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00028A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCREAD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00028C, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.DIV, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000296, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFTMR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ABS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DIVS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LXVWSX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002D8, 0xFC0007FE, .BASE, .PPC32, {}}, - {.TLBIA, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0002E4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SETBC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000300, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTDCRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000306, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.STVEXBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00030A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCBLC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00030C, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.DCBLCE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00031C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICSWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00032C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.SETBCR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000340, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MTDCRUX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000346, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVEXHX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00034A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CLRBHRB, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00035C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ECOWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00036C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SETNBC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000380, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVEXWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00038A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00038C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.MTTMR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SETNBCR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003C0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DSN, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003C6, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.NABS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICBTLSE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003DC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CLI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MCRXR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000400, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LBDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000404, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LBDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000406, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.BBLELS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00040C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVLX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00040E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFCO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000410, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000410, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBCO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000410, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDCO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000414, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000414, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CLCS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000426, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LSX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00042A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LBRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00042C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RRIB, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000432, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MASKIR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00043A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000444, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LHDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000446, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LVTRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00044A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.BBELR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00044C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00044E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000450, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000450, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000484, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000486, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LVTLX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00048A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LSI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004AA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004AC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFFGPR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004BE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LDDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004C6, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LVSWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004CA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.NEGO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFSRI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004E6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCLST, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0004EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STBDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000504, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STBDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000506, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVLX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00050E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000510, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000510, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000514, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000514, 0xFC0007FE, .BASE, .PPC32, {}}, - {.HASHSTP, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000524, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STSX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00052A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STBRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00052C, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000530, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000532, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STHDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000544, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STHDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000546, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVFRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00054A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVRX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00054E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.HASHCHKP, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000564, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRIQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000570, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWDCBX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000584, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000586, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVFLX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00058A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFZEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000590, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFZEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000590, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDZEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000594, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AZEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000594, 0xFC0007FE, .BASE, .PPC32, {}}, - {.HASHST, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005A4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STSI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005AA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRLQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005B0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SREQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005B2, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MFTGPR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005BE, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STDDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005C6, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVSWX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005CA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SUBFMEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SFMEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLDO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D2, 0xFC0007FE, .P64, .PPC64, {}}, - {.ADDMEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.AMEO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULLWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.MULSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.HASHCHK, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005E4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRLIQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0005F0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVSM, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00060A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVEPXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00060E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVLXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00060E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DOZO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000610, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADDO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000614, 0xFC0007FE, .BASE, .PPC32, {}}, - {.CAXO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000614, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LFQX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00062E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRA, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000630, 0xFC0007FE, .BASE, .PPC32, {}}, - {.EVLDDEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00063E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LFDDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000646, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.LVTRXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00064A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00064E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVRXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00064E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RAC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000664, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ERATIVAX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000666, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.LFQUX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00066E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRAI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000670, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVTLXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00068A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DIVO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000696, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SLBIAG, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006A4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LVSWXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006CA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ABSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DIVSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.RMIEG, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0006E4, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVLXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00070E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STFQX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00072E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRAQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000730, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SREA, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000732, 0xFC0007FE, .BASE, .PPC32, {}}, - {.EXTS, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000734, 0xFC0007FE, .BASE, .PPC32, {}}, - {.EVSTDDEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00073E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STFDDX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000746, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.STVFRXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00074A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.WCLRALL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00074C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.WCLR, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00074C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.STVRXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00074E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICSWEPX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00076C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.STFQUX, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00076E, 0xFC0007FE, .BASE, .PPC32, {}}, - {.SRAIQ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000770, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVFLXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00078A, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICI, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C00078C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.DIVDUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000792, 0xFC0007FE, .P64, .PPC64, {}}, - {.DIVWUO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000796, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STVSWXL, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007CA, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ICREAD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007CC, 0xFC0007FE, .BOOKE, .PPC32, {}}, - {.NABSO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D0, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DIVDO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D2, 0xFC0007FE, .P64, .PPC64, {}}, - {.DIVWO, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007D6, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DCLZ, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0007EC, 0xFC0007FE, .BASE, .PPC32, {}}, - {.ADD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000214, 0xFC0003FE, .BASE, .PPC32, {}}, - {.ADDC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000014, 0xFC0003FE, .BASE, .PPC32, {}}, - {.ADDE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000114, 0xFC0003FE, .BASE, .PPC32, {}}, - {.SUBF, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000050, 0xFC0003FE, .BASE, .PPC32, {}}, - {.SUBFC, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000010, 0xFC0003FE, .BASE, .PPC32, {}}, - {.SUBFE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000110, 0xFC0003FE, .BASE, .PPC32, {}}, - {.MULLW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D6, 0xFC0003FE, .BASE, .PPC32, {}}, - {.MULLD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0001D2, 0xFC0003FE, .P64, .PPC64, {}}, - {.DIVW, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D6, 0xFC0003FE, .BASE, .PPC32, {}}, - {.DIVWU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000396, 0xFC0003FE, .BASE, .PPC32, {}}, - {.DIVD, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C0003D2, 0xFC0003FE, .P64, .PPC64, {}}, - {.DIVDU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000392, 0xFC0003FE, .P64, .PPC64, {}}, - {.DIVWE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000356, 0xFC0003FE, .BASE, .PPC32, {}}, - {.DIVWEU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000316, 0xFC0003FE, .BASE, .PPC32, {}}, - {.DIVDE, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000352, 0xFC0003FE, .P64, .PPC64, {}}, - {.DIVDEU, {.GPR, .GPR, .GPR, .NONE}, {.RT, .RA, .RB, .NONE}, 0x7C000312, 0xFC0003FE, .P64, .PPC64, {}}, - {.SRADI, {.GPR, .GPR, .IMM, .NONE}, {.RA, .RS, .SH6, .NONE}, 0x7C000674, 0xFC0007FC, .P64, .PPC64, {}}, - {.XXSPLTIW, {.VSR, .SIMM, .NONE, .NONE}, {.XT, .D16, .NONE, .NONE}, 0x80060000, 0xFC070000, .POWER10, .PPC32, {prefixed=true}}, - {.XXSPLTIDP, {.VSR, .SIMM, .NONE, .NONE}, {.XT, .D16, .NONE, .NONE}, 0x80040000, 0xFC070000, .POWER10, .PPC32, {prefixed=true}}, - {.XXSPLTI32DX, {.VSR, .SIMM, .NONE, .NONE}, {.XT, .D16, .NONE, .NONE}, 0x80000000, 0xFC070000, .POWER10, .PPC32, {prefixed=true}}, - {.LWZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x80000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLWZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x80000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.XXBLENDVB, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x84221900, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.XXBLENDVH, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x84221910, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.XXBLENDVW, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x84221920, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.XXBLENDVD, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x84221930, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.LU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x84000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LWZU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x84000000, 0xFC000000, .BASE, .PPC32, {}}, - {.XXPERMX, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x88221900, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.XXEVAL, {.VSR, .VSR, .VSR, .VSR}, {.NONE, .NONE, .NONE, .NONE}, 0x88221910, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.LBZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x88000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLBZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x88000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LBZU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x8C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.ST, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x90000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STW, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x90000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PSTW, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x90000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0x94000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STWU, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, .PPC32, {}}, - {.STB, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x98000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PSTB, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x98000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STBU, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0x9C000000, 0xFC000000, .BASE, .PPC32, {}}, - {.LHZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA0000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLHZ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA0000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LHZU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA4000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLWA, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA4000000, 0xFC000000, .POWER10, .PPC64, {prefixed=true}}, - {.LHA, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA8000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLHA, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.PLXSD, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xA8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LHAU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xAC000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PLXSSP, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xAC000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STH, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0xB0000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PSTH, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0xB0000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STHU, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0xB4000000, 0xFC000000, .BASE, .PPC32, {}}, - {.LM, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xB8000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LMW, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xB8000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PSTXSD, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xB8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STM, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xBC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.STMW, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0xBC000000, 0xFC000000, .BASE, .PPC32, {}}, - {.PSTXSSP, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xBC000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LFS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC0000000, 0xFC000000, .FP, .PPC32, {}}, - {.PLFS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC0000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LFSU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC4000000, 0xFC000000, .FP, .PPC32, {}}, - {.LFD, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC8000000, 0xFC000000, .FP, .PPC32, {}}, - {.PLFD, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.PLXV, {.VSR, .MEM, .NONE, .NONE}, {.XT, .OFFSET_BASE_D, .NONE, .NONE}, 0xC8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.LFDU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xCC000000, 0xFC000000, .FP, .PPC32, {}}, - {.STFS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD0000000, 0xFC000000, .FP, .PPC32, {}}, - {.PSTFS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD0000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STFSU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD4000000, 0xFC000000, .FP, .PPC32, {}}, - {.STFD, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD8000000, 0xFC000000, .FP, .PPC32, {}}, - {.PSTFD, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.PSTXV, {.VSR, .MEM, .NONE, .NONE}, {.XT, .OFFSET_BASE_D, .NONE, .NONE}, 0xD8000000, 0xFC000000, .POWER10, .PPC32, {prefixed=true}}, - {.STFDU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xDC000000, 0xFC000000, .FP, .PPC32, {}}, - {.LFQ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xE0000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.LQ, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_DQ, .NONE, .NONE}, 0xE0000000, 0xFC00000F, .POWER8, .PPC64, {}}, - {.PSQ_L, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xE0000000, 0xFC00F000, .PS, .PPC32, {}}, - {.LFQU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xE4000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.PSQ_LU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xE4000000, 0xFC00F000, .PS, .PPC32, {}}, - {.LFDP, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE4000000, 0xFC000003, .FP, .PPC32, {}}, - {.LXSD, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE4000002, 0xFC000003, .VSX_P9, .PPC32, {}}, - {.LXSSP, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE4000003, 0xFC000003, .VSX_P9, .PPC32, {}}, - {.PLD, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_D, .NONE, .NONE}, 0xE4000000, 0xFC000000, .POWER10, .PPC64, {prefixed=true}}, - {.LWA, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE8000002, 0xFC000003, .P64, .PPC64, {}}, - {.LD, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE8000000, 0xFC000003, .P64, .PPC64, {}}, - {.LDU, {.GPR, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xE8000001, 0xFC000003, .P64, .PPC64, {}}, - {.DADD_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221805, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DSUB_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221C05, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DMUL_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221845, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DDIV_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221C45, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DRSP_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201605, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DCTDP_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201205, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DXEX_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2012C5, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DIEX_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221EC5, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DRRND_DOT, {.FPR, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221847, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DRINTX_DOT, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2010C7, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DRINTN_DOT, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2011C7, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DQUA_DOT, {.FPR, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221807, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DQUAI_DOT, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201087, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DSCLI_DOT, {.FPR, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC220085, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DSCRI_DOT, {.FPR, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2200C5, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DCFFIX_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201645, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DCTFIX_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201245, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DENBCD_DOT, {.IMM, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201685, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DDEDPD_DOT, {.IMM, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201285, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.XVF16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00089E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000896, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF16GER2PN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000C96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF16GER2NP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000A96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF16GER2NN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000E96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF32GER, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0008DE, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF32GERPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0008D6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF32GERPN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000CD6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF32GERNP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000AD6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF32GERNN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000ED6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF64GER, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0009DE, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF64GERPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0009D6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF64GERPN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000DD6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF64GERNP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000BD6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVF64GERNN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000FD6, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVBF16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00099E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVBF16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000996, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVBF16GER2PN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000D96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVBF16GER2NP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVBF16GER2NN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000F96, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI4GER8, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00091E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI4GER8PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000916, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI8GER4, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00081E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI8GER4PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000816, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI8GER4SPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B1E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000A5E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B5E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI16GER2S, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00095E, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVI16GER2SPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000956, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.PMXVF32GER, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0008DE, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF64GER, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0009DE, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI4GER8, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00091E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI8GER4, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00081E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000A5E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00089E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000896, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF16GER2PN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000C96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF16GER2NP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000A96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF16GER2NN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000E96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF32GERPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0008D6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF32GERPN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000CD6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF32GERNP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000AD6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF32GERNN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000ED6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF64GERPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0009D6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF64GERPN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000DD6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF64GERNP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000BD6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVF64GERNN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000FD6, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVBF16GER2, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00099E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVBF16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000996, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVBF16GER2PN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000D96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVBF16GER2NP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVBF16GER2NN, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000F96, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI4GER8PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000916, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI8GER4PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000816, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI8GER4SPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B1E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI16GER2PP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000B5E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI16GER2S, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC00095E, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.PMXVI16GER2SPP, {.IMM, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC000956, 0xFFFFFFFF, .POWER10, .PPC32, {prefixed=true}}, - {.DADD, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221804, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DSUB, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221C04, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DMUL, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221844, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DDIV, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221C44, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCMPU, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC011504, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCMPO, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC011104, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DRSP, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201604, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCTDP, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201204, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DXEX, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2012C4, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DIEX, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221EC4, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DRRND, {.FPR, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221846, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DRINTX, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2010C6, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DRINTN, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2011C6, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DQUA, {.FPR, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC221806, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DQUAI, {.IMM, .FPR, .FPR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201086, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DSCLI, {.FPR, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC220084, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DSCRI, {.FPR, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC2200C4, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCFFIX, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201644, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCTFIX, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201244, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DTSTDC, {.CR_FIELD, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC010184, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DTSTDG, {.CR_FIELD, .FPR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC0101C4, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DTSTEX, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC011144, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DTSTSF, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC011544, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DENBCD, {.IMM, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201684, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DDEDPD, {.IMM, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xEC201284, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.FSQRTS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00002D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRES_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC000031, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRSQRTES_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC000035, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCFIDS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00069D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCFIDUS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00079D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FSQRTS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00002C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRES, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC000030, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRSQRTES, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC000034, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCFIDS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00069C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCFIDUS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xEC00079C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FADDS_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC00002B, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FSUBS_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC000029, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FMULS_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0xEC000033, 0xFC00F83F, .FP, .PPC32, {sets_cr1=true}}, - {.FDIVS_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC000025, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FADDS, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC00002A, 0xFC0007FE, .FP, .PPC32, {}}, - {.FSUBS, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC000028, 0xFC0007FE, .FP, .PPC32, {}}, - {.FMULS, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0xEC000032, 0xFC00F83E, .FP, .PPC32, {}}, - {.FDIVS, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xEC000024, 0xFC0007FE, .FP, .PPC32, {}}, - {.FMADDS_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003B, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FMSUBS_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC000039, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FNMADDS_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003F, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FNMSUBS_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003D, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FMADDS, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003A, 0xFC00003E, .FP, .PPC32, {}}, - {.FMSUBS, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC000038, 0xFC00003E, .FP, .PPC32, {}}, - {.FNMADDS, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003E, 0xFC00003E, .FP, .PPC32, {}}, - {.FNMSUBS, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xEC00003C, 0xFC00003E, .FP, .PPC32, {}}, - {.LXVKQ, {.VSR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF03F02D0, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVCVBF16SPN, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF030176C, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XVCVSPBF16, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF031176C, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXGENPCVBM, {.VSR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0201728, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXGENPCVHM, {.VSR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF020172A, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXGENPCVWM, {.VSR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0201768, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XXGENPCVDM, {.VSR, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF020176A, 0xFFFFFFFF, .POWER10, .PPC32, {}}, - {.XSCVSXDSP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF06024E0, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XSCVUXDSP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF06024A0, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XXBRH, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF067276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XXBRW, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF06F276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XXBRD, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF077276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XXBRQ, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF07F276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XVTLSBB, {.CR_FIELD, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF182276C, 0xFFFFFFFF, .VSX_P10, .PPC32, {}}, - {.XVCVHPSP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF078276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XVCVSPHP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF079276C, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XXPERMR, {.VSR, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF06429D0, 0xFFFFFFFF, .VSX_P9, .PPC32, {}}, - {.XSCVDPHP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF031156C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSCVHPDP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF030156C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSIEXPDP, {.VSR, .GPR, .GPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0221F2C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSXEXPDP, {.GPR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF020156C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSXSIGDP, {.GPR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF021156C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVIEXPSP, {.VSR, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0221EC0, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVIEXPDP, {.VSR, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0221FC0, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVXEXPSP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF028176C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVXEXPDP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF020176C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVXSIGSP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF029176C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVXSIGDP, {.VSR, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF021176C, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTSTDCSP, {.VSR, .VSR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF02016A8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTSTDCDP, {.VSR, .VSR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF02017A8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSTSTDCSP, {.CR_FIELD, .VSR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0000CA8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSTSTDCDP, {.CR_FIELD, .VSR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0000DA8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSTSQRTDP, {.CR_FIELD, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00009A8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTSQRTSP, {.CR_FIELD, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0000AA8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTSQRTDP, {.CR_FIELD, .VSR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0000BA8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XSTDIVDP, {.CR_FIELD, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00111E8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTDIVSP, {.CR_FIELD, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00112E8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XVTDIVDP, {.CR_FIELD, .VSR, .VSR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00113E8, 0xFFFFFFFE, .VSX_P9, .PPC32, {}}, - {.XXSPLTIB, {.VSR, .UIMM, .NONE, .NONE}, {.XT, .UIMM_5, .NONE, .NONE}, 0xF00002D0, 0xFC18FFFC, .VSX_P9, .PPC32, {}}, - {.XSSQRTSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000002C, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XSSQRTDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000012C, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRESP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000068, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XSREDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000168, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRSQRTESP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000028, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XSRSQRTEDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000128, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSABSDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000564, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSNABSDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00005A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSNEGDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00005E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVDPSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000424, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVSPDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000524, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVDPSXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000560, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVDPUXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000520, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVSXDDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00005E0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVUXDDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00005A0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVDPSXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000160, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVDPUXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000120, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSCVSPDPN, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000052C, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XSCVDPSPN, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000042C, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XSRDPI, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000124, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRDPIM, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00001E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRDPIP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00001A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRDPIZ, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000164, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRDPIC, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00001AC, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XSRSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000464, 0xFC1F07FC, .POWER8, .PPC32, {}}, - {.XVSQRTSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000022C, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVSQRTDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF000032C, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRESP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000268, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVREDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000368, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSQRTESP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000228, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSQRTEDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000328, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVABSSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000664, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVABSDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000764, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVNABSSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00006A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVNABSDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00007A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVNEGSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00006E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVNEGDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00007E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSPDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000724, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVDPSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000624, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSPSXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000660, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSPUXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000620, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVDPSXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000760, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVDPUXDS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000720, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSPSXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000260, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSPUXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000220, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVDPSXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000360, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVDPUXWS, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000320, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSXDSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00006E0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVUXDSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00006A0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSXDDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00007E0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVUXDDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00007A0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSXWSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00002E0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVUXWSP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00002A0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVSXWDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00003E0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVCVUXWDP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00003A0, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSPI, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000224, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSPIM, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00002E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSPIP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00002A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSPIZ, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000264, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRSPIC, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00002AC, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRDPI, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000324, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRDPIM, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00003E4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRDPIP, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00003A4, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRDPIZ, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF0000364, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XVRDPIC, {.VSR, .VSR, .NONE, .NONE}, {.XT, .XB, .NONE, .NONE}, 0xF00003AC, 0xFC1F07FC, .VSX, .PPC32, {}}, - {.XXSPLTW, {.VSR, .VSR, .IMM, .NONE}, {.XT, .XB, .UIMM_2, .NONE}, 0xF0000290, 0xFC1C07FC, .VSX, .PPC32, {}}, - {.XSCMPODP, {.CR_FIELD, .VSR, .VSR, .NONE}, {.BF, .XA, .XB, .NONE}, 0xF0000158, 0xFC6007FC, .VSX, .PPC32, {}}, - {.XSCMPUDP, {.CR_FIELD, .VSR, .VSR, .NONE}, {.BF, .XA, .XB, .NONE}, 0xF0000118, 0xFC6007FC, .VSX, .PPC32, {}}, - {.XXEXTRACTUW, {.VSR, .VSR, .IMM, .NONE}, {.XT, .XB, .UIMM_4, .NONE}, 0xF0000294, 0xFC1007FC, .VSX_P9, .PPC32, {}}, - {.XXINSERTW, {.VSR, .VSR, .IMM, .NONE}, {.XT, .XB, .UIMM_4, .NONE}, 0xF00002D4, 0xFC1007FC, .VSX_P9, .PPC32, {}}, - {.STFQ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xF0000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.XSADDSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000000, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSADDDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000100, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSSUBSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000040, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSSUBDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000140, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMULSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000080, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSMULDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000180, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSDIVSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00000C0, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSDIVDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00001C0, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMADDASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000008, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSMADDADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000108, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMADDMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000048, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSMADDMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000148, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMSUBASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000088, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSMSUBADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000188, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMSUBMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00000C8, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSMSUBMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00001C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSNMADDASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000408, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSNMADDADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000508, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSNMADDMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000448, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSNMADDMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000548, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSNMSUBASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000488, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSNMSUBADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000588, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSNMSUBMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00004C8, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XSNMSUBMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00005C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMAXDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000500, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMINDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000540, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XSMAXCDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000400, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSMINCDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000440, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSMAXJDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000480, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSMINJDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00004C0, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSCMPEQDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000018, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSCMPGTDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000058, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSCMPGEDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000098, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XSCPSGNDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000580, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVADDSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000200, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVADDDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000300, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVSUBSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000240, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVSUBDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000340, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMULSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000280, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMULDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000380, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVDIVSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00002C0, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVDIVDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00003C0, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMADDASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000208, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMADDADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000308, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMADDMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000248, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMADDMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000348, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMSUBASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000288, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMSUBADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000388, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMSUBMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00002C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMSUBMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00003C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMADDASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000608, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMADDADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000708, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMADDMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000648, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMADDMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000748, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMSUBASP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000688, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMSUBADP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000788, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMSUBMSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00006C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVNMSUBMDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00007C8, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMAXSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000600, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMAXDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000700, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMINSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000640, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVMINDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000740, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPEQSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000218, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPEQSP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000618, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPEQDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000318, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPEQDP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000718, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGTSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000258, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGTSP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000658, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGTDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000358, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGTDP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000758, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGESP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000298, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGESP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000698, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGEDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000398, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCMPGEDP_DOT, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000798, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCPSGNSP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000680, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XVCPSGNDP, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000780, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLAND, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000410, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLANDC, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000450, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLOR, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000490, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLXOR, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00004D0, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLNOR, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000510, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXLEQV, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00005D0, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XXLNAND, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000590, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XXLORC, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000550, 0xFC0007F8, .POWER8, .PPC32, {}}, - {.XXMRGHW, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000090, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXMRGLW, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF0000190, 0xFC0007F8, .VSX, .PPC32, {}}, - {.XXPERM, {.VSR, .VSR, .VSR, .NONE}, {.XT, .XA, .XB, .NONE}, 0xF00000D0, 0xFC0007F8, .VSX_P9, .PPC32, {}}, - {.XXSLDWI, {.VSR, .VSR, .VSR, .IMM}, {.XT, .XA, .XB, .UIMM_2}, 0xF0000010, 0xFC0003F8, .VSX, .PPC32, {}}, - {.XXPERMDI, {.VSR, .VSR, .VSR, .IMM}, {.XT, .XA, .XB, .UIMM_2}, 0xF0000050, 0xFC0003F8, .VSX, .PPC32, {}}, - {.PSQ_ST, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xF0000000, 0xFC00F000, .PS, .PPC32, {}}, - {.XXSEL, {.VSR, .VSR, .VSR, .VSR}, {.XT, .XA, .XB, .XC}, 0xF0000030, 0xFC000030, .VSX, .PPC32, {}}, - {.STFQU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xF4000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.PSQ_STU, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xF4000000, 0xFC00F000, .PS, .PPC32, {}}, - {.LXV, {.VSR, .MEM, .NONE, .NONE}, {.XT, .OFFSET_BASE_DQ, .NONE, .NONE}, 0xF4000001, 0xFC000007, .VSX_P9, .PPC32, {}}, - {.STXV, {.VSR, .MEM, .NONE, .NONE}, {.XT, .OFFSET_BASE_DQ, .NONE, .NONE}, 0xF4000005, 0xFC000007, .VSX_P9, .PPC32, {}}, - {.STFDP, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF4000000, 0xFC000003, .FP, .PPC32, {}}, - {.STXSD, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF4000002, 0xFC000003, .VSX_P9, .PPC32, {}}, - {.STXSSP, {.VR, .MEM, .NONE, .NONE}, {.VRT, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF4000003, 0xFC000003, .VSX_P9, .PPC32, {}}, - {.PSTD, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_D, .NONE, .NONE}, 0xF4000000, 0xFC000000, .POWER10, .PPC64, {prefixed=true}}, - {.STD, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF8000000, 0xFC000003, .P64, .PPC64, {}}, - {.STDU, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF8000001, 0xFC000003, .P64, .PPC64, {}}, - {.STQ, {.GPR, .MEM, .NONE, .NONE}, {.RS, .OFFSET_BASE_DS, .NONE, .NONE}, 0xF8000002, 0xFC000003, .POWER8, .PPC64, {}}, - {.XSADDQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221809, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSSUBQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221C09, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSMULQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221849, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSDIVQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221C49, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSSQRTQPO, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC3B1649, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSMADDQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B09, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSMSUBQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B49, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSNMADDQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B89, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSNMSUBQPO, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221BC9, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSRQPIX, {.IMM, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xFC20100B, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.XSCVQPDPO, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC341689, 0xFFFFFFFF, .POWER9, .PPC32, {}}, - {.DADDQ_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443005, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DSUBQ_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443405, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DMULQ_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443045, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DDIVQ_DOT, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443445, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.DCTFIXQ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC402245, 0xFFFFFFFF, .DFP, .PPC32, {sets_cr1=true}}, - {.MFFSCE, {.FPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC21048E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.MFFSCDRN, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC34048E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.MFFSCDRNI, {.FPR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC35048E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.MFFSCRN, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC36148E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.MFFSCRNI, {.FPR, .IMM, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC37148E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.MFFSL, {.FPR, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC38048E, 0xFFFFFFFF, .FP, .PPC32, {}}, - {.XSADDQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221808, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSSUBQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221C08, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSMULQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221848, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSDIVQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221C48, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSSQRTQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC3B1648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSMADDQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B08, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSMSUBQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B48, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSNMADDQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221B88, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSNMSUBQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221BC8, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSABSQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC201648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSNABSQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC281648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSNEGQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC301648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCPSGNQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC2218C8, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCMPOQP, {.CR_FIELD, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC011108, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCMPUQP, {.CR_FIELD, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC011508, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSTSTDCQP, {.CR_FIELD, .VR, .IMM, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC000D88, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSRQPI, {.IMM, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xFC20100A, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSRQPXP, {.IMM, .VR, .VR, .IMM}, {.NONE, .NONE, .NONE, .NONE}, 0xFC20104A, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSXEXPQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSXSIGQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC321648, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSIEXPQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221EC8, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVQPDP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC341688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVDPQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC361688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVQPSDZ, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC391688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVQPSWZ, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC291688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVQPUDZ, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC311688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVQPUWZ, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC211688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVSDQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC2A1688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.XSCVUDQP, {.VR, .VR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221688, 0xFFFFFFFE, .POWER9, .PPC32, {}}, - {.DADDQ, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443004, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DSUBQ, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443404, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DMULQ, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443044, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DDIVQ, {.FPR, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC443444, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCMPUQ, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC022504, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCMPOQ, {.CR_FIELD, .FPR, .FPR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC022104, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.DCTFIXQ, {.FPR, .FPR, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC402244, 0xFFFFFFFE, .DFP, .PPC32, {}}, - {.XSMAXCQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221D48, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.XSMINCQP, {.VR, .VR, .VR, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC221DC8, 0xFFFFFFFE, .POWER10, .PPC32, {}}, - {.MFFS_DOT, {.FPR, .NONE, .NONE, .NONE}, {.FRT, .NONE, .NONE, .NONE}, 0xFC00048F, 0xFC1FFFFF, .FP, .PPC32, {sets_cr1=true}}, - {.MTFSB0_DOT, {.CR_BIT, .NONE, .NONE, .NONE}, {.BT, .NONE, .NONE, .NONE}, 0xFC00008D, 0xFC1FFFFF, .FP, .PPC32, {sets_cr1=true}}, - {.MTFSB1_DOT, {.CR_BIT, .NONE, .NONE, .NONE}, {.BT, .NONE, .NONE, .NONE}, 0xFC00004D, 0xFC1FFFFF, .FP, .PPC32, {sets_cr1=true}}, - {.MFFS, {.FPR, .NONE, .NONE, .NONE}, {.FRT, .NONE, .NONE, .NONE}, 0xFC00048E, 0xFC1FFFFE, .FP, .PPC32, {}}, - {.MTFSB0, {.CR_BIT, .NONE, .NONE, .NONE}, {.BT, .NONE, .NONE, .NONE}, 0xFC00008C, 0xFC1FFFFE, .FP, .PPC32, {}}, - {.MTFSB1, {.CR_BIT, .NONE, .NONE, .NONE}, {.BT, .NONE, .NONE, .NONE}, 0xFC00004C, 0xFC1FFFFE, .FP, .PPC32, {}}, - {.MCRFS, {.CR_FIELD, .CR_FIELD, .NONE, .NONE}, {.BF, .BFA, .NONE, .NONE}, 0xFC000080, 0xFC63FFFE, .FP, .PPC32, {}}, - {.MTFSFI_DOT, {.CR_FIELD, .IMM, .NONE, .NONE}, {.BF, .UIMM_4, .NONE, .NONE}, 0xFC00010D, 0xFC7E0FFF, .FP, .PPC32, {sets_cr1=true}}, - {.FTSQRT, {.CR_FIELD, .FPR, .NONE, .NONE}, {.BF, .FRB, .NONE, .NONE}, 0xFC000140, 0xFC7F07FE, .FP, .PPC32, {}}, - {.MTFSFI, {.CR_FIELD, .IMM, .NONE, .NONE}, {.BF, .UIMM_4, .NONE, .NONE}, 0xFC00010C, 0xFC7E0FFE, .FP, .PPC32, {}}, - {.FSQRT_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00002D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRE_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000031, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRSQRTE_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000035, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FNEG_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000051, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FABS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000211, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FNABS_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000111, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FMR_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000091, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRSP_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000019, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTID_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00065D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIDU_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00075D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIDZ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00065F, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIDUZ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00075F, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIW_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00001D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIWU_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00011D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIWZ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00001F, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCTIWUZ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00011F, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCFID_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00069D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCFIDU_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00079D, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRIN_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000311, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRIZ_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000351, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRIP_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000391, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FRIM_DOT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC0003D1, 0xFC1F07FF, .FP, .PPC32, {sets_cr1=true}}, - {.FSQRT, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00002C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRE, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000030, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRSQRTE, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000034, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FNEG, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000050, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FABS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000210, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FNABS, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000110, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FMR, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000090, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRSP, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000018, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTID, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00065C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIDU, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00075C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIDZ, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00065E, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIDUZ, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00075E, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIW, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00001C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIWU, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00011C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIWZ, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00001E, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCTIWUZ, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00011E, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCFID, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00069C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FCFIDU, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC00079C, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRIN, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000310, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRIZ, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000350, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRIP, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC000390, 0xFC1F07FE, .FP, .PPC32, {}}, - {.FRIM, {.FPR, .FPR, .NONE, .NONE}, {.FRT, .FRB, .NONE, .NONE}, 0xFC0003D0, 0xFC1F07FE, .FP, .PPC32, {}}, - {.MTFSF_DOT, {.IMM, .FPR, .NONE, .NONE}, {.FXM, .FRB, .NONE, .NONE}, 0xFC00058F, 0xFE0107FF, .FP, .PPC32, {sets_cr1=true}}, - {.XSCMPEQQP, {.CR_FIELD, .VR, .VR, .NONE}, {.BF, .VRA, .VRB, .NONE}, 0xFC000088, 0xFC6007FF, .POWER10, .PPC32, {}}, - {.XSCMPGTQP, {.CR_FIELD, .VR, .VR, .NONE}, {.BF, .VRA, .VRB, .NONE}, 0xFC0001C8, 0xFC6007FF, .POWER10, .PPC32, {}}, - {.XSCMPGEQP, {.CR_FIELD, .VR, .VR, .NONE}, {.BF, .VRA, .VRB, .NONE}, 0xFC000188, 0xFC6007FF, .POWER10, .PPC32, {}}, - {.FCMPU, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0xFC000000, 0xFC6007FE, .FP, .PPC32, {}}, - {.FCMPO, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0xFC000040, 0xFC6007FE, .FP, .PPC32, {}}, - {.FTDIV, {.CR_FIELD, .FPR, .FPR, .NONE}, {.BF, .FRA, .FRB, .NONE}, 0xFC000100, 0xFC6007FE, .FP, .PPC32, {}}, - {.MTFSF, {.IMM, .FPR, .NONE, .NONE}, {.FXM, .FRB, .NONE, .NONE}, 0xFC00058E, 0xFE0107FE, .FP, .PPC32, {}}, - {.FADD_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC00002B, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FSUB_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000029, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FMUL_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0xFC000033, 0xFC00F83F, .FP, .PPC32, {sets_cr1=true}}, - {.FDIV_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000025, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCPSGN_DOT, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000011, 0xFC0007FF, .FP, .PPC32, {sets_cr1=true}}, - {.FCIR_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FCIRZ_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FD_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FS_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FA_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FM_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FMS_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FMA_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FNMS_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FNMA_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.DXEXQ_DOT, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FF, .BASE, .PPC32, {}}, - {.FADD, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC00002A, 0xFC0007FE, .FP, .PPC32, {}}, - {.FSUB, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000028, 0xFC0007FE, .FP, .PPC32, {}}, - {.FMUL, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRC, .NONE}, 0xFC000032, 0xFC00F83E, .FP, .PPC32, {}}, - {.FDIV, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000024, 0xFC0007FE, .FP, .PPC32, {}}, - {.FCPSGN, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC000010, 0xFC0007FE, .FP, .PPC32, {}}, - {.FMRGEW, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC00078C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.FMRGOW, {.FPR, .FPR, .FPR, .NONE}, {.FRT, .FRA, .FRB, .NONE}, 0xFC00068C, 0xFC0007FE, .POWER8, .PPC32, {}}, - {.FCIR, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FCIRZ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FD, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FA, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FM, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FMS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FMA, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FNMS, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FNMA, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DTSTEXQ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.XSCMPEXPQP, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DXEXQ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.DTSTSFQ, {.FPR, .MEM, .NONE, .NONE}, {.FRT, .OFFSET_BASE_D, .NONE, .NONE}, 0xFC000000, 0xFC0007FE, .BASE, .PPC32, {}}, - {.FMADD_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003B, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FMSUB_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC000039, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FNMADD_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003F, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FNMSUB_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003D, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FSEL_DOT, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00002F, 0xFC00003F, .FP, .PPC32, {sets_cr1=true}}, - {.FMADD, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003A, 0xFC00003E, .FP, .PPC32, {}}, - {.FMSUB, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC000038, 0xFC00003E, .FP, .PPC32, {}}, - {.FNMADD, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003E, 0xFC00003E, .FP, .PPC32, {}}, - {.FNMSUB, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00003C, 0xFC00003E, .FP, .PPC32, {}}, - {.FSEL, {.FPR, .FPR, .FPR, .FPR}, {.FRT, .FRA, .FRC, .FRB}, 0xFC00002E, 0xFC00003E, .FP, .PPC32, {}}, -} - -@(rodata) -DECODE_FORM_IDX: [3327]u16 - -@(rodata) -DECODE_BUCKET_LIST := [34967]u16{ - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, - 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, - 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3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, - 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, - 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3155, 3156, 3157, 3276, 3285, 3286, 3287, 3288, 3289, 3290, 3291, 3292, 3293, 3294, 3295, 3303, 3304, 3305, 3306, 3307, 3308, 3309, 3310, 3311, 3312, 3313, 3314, 3315, 3316, 3169, 3170, 3209, 3210, 3158, 3159, 3180, 3181, 3167, 3196, 3232, 3254, - 3284, 3300, 3235, 3257, 3240, 3262, 3242, 3264, 3283, 3299, 3281, 3297, 3280, 3296, 3228, 3250, 3321, 3326, 3229, 3251, 3282, 3298, 3230, 3252, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3277, 3171, 3172, 3173, 3211, 3212, 3215, 3160, 3161, 3162, 3182, 3183, 3184, 3189, 3190, 3191, 3198, 3199, 3197, 3220, 3223, 3231, 3253, 3236, 3258, 3238, 3260, 3321, 3326, 3282, 3298, 3318, - 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3224, 3168, 3201, 3202, 3203, 3204, 3205, 3206, 3207, 3208, 3273, 3219, 3222, 3302, 3174, 3175, 3176, 3177, 3178, 3179, 3218, 3221, 3234, 3256, 3244, 3266, 3321, 3326, 3282, 3298, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3192, 3200, 3321, 3326, 3282, 3298, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3278, 3213, 3214, 3163, 3185, - 3193, 3194, 3225, 3227, 3233, 3246, 3255, 3268, 3241, 3263, 3243, 3265, 3321, 3326, 3282, 3298, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3226, 3164, 3186, 3216, 3247, 3269, 3237, 3259, 3239, 3261, 3321, 3326, 3282, 3298, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, 3165, 3187, 3195, 3275, 3301, 3272, 3279, 3248, 3270, 3245, 3267, 3321, 3326, 3282, 3298, 3318, 3323, 3317, - 3322, 3320, 3325, 3319, 3324, 3166, 3188, 3217, 3274, 3249, 3271, 3321, 3326, 3282, 3298, 3318, 3323, 3317, 3322, 3320, 3325, 3319, 3324, -} - -@(rodata) -DECODE_INDEX_PRIMARY := [64]Decode_Index{ - 0x0000 = { 0, 1, 0}, 0x0002 = { 1, 6, 0}, 0x0003 = { 7, 7, 0}, 0x0004 = { 14, 1670, 0}, 0x0005 = { 1684, 36, 0}, 0x0006 = { 1720, 18, 0}, 0x0007 = { 1738, 2, 0}, 0x0008 = { 1740, 2, 0}, 0x0009 = { 1742, 1, 0}, 0x000A = { 1743, 3, 0}, 0x000B = { 1746, 3, 0}, 0x000C = { 1749, 3, 0}, 0x000D = { 1752, 3, 0}, 0x000E = { 1755, 9, 0}, 0x000F = { 1764, 5, 0}, 0x0010 = { 1769, 32, 0}, - 0x0011 = { 1801, 3, 0}, 0x0012 = { 1804, 4, 0}, 0x0013 = { 1808, 71, 0}, 0x0014 = { 1879, 4, 0}, 0x0015 = { 1883, 9, 0}, 0x0017 = { 1892, 4, 0}, 0x0018 = { 1896, 3, 0}, 0x0019 = { 1899, 2, 0}, 0x001A = { 1901, 3, 0}, 0x001B = { 1904, 2, 0}, 0x001C = { 1906, 2, 0}, 0x001D = { 1908, 2, 0}, 0x001E = { 1910, 34, 0}, 0x001F = { 1944, 806, 0}, 0x0020 = { 2750, 5, 0}, 0x0021 = { 2755, 6, 0}, - 0x0022 = { 2761, 4, 0}, 0x0023 = { 2765, 1, 0}, 0x0024 = { 2766, 3, 0}, 0x0025 = { 2769, 2, 0}, 0x0026 = { 2771, 2, 0}, 0x0027 = { 2773, 1, 0}, 0x0028 = { 2774, 2, 0}, 0x0029 = { 2776, 2, 0}, 0x002A = { 2778, 3, 0}, 0x002B = { 2781, 2, 0}, 0x002C = { 2783, 2, 0}, 0x002D = { 2785, 1, 0}, 0x002E = { 2786, 3, 0}, 0x002F = { 2789, 3, 0}, 0x0030 = { 2792, 2, 0}, 0x0031 = { 2794, 1, 0}, - 0x0032 = { 2795, 3, 0}, 0x0033 = { 2798, 1, 0}, 0x0034 = { 2799, 2, 0}, 0x0035 = { 2801, 1, 0}, 0x0036 = { 2802, 3, 0}, 0x0037 = { 2805, 1, 0}, 0x0038 = { 2806, 3, 0}, 0x0039 = { 2809, 6, 0}, 0x003A = { 2815, 3, 0}, 0x003B = { 2818, 128, 0}, 0x003C = { 2946, 201, 0}, 0x003D = { 3147, 8, 0}, 0x003E = { 3155, 3, 0}, 0x003F = { 3158, 169, 0}, -} - -@(rodata) -DECODE_INDEX_SUB := [16384]Decode_Index{ - 0x0000 = { 3327, 1, 0}, 0x0200 = { 3328, 1, 0}, 0x0201 = { 3329, 1, 0}, 0x0202 = { 3330, 1, 0}, 0x0203 = { 3331, 1, 0}, 0x0204 = { 3332, 1, 0}, 0x0205 = { 3333, 1, 0}, 0x0206 = { 3334, 1, 0}, 0x0207 = { 3335, 1, 0}, 0x0208 = { 3336, 1, 0}, 0x0209 = { 3337, 1, 0}, 0x020A = { 3338, 1, 0}, 0x020B = { 3339, 1, 0}, 0x020C = { 3340, 1, 0}, 0x020D = { 3341, 1, 0}, 0x020E = { 3342, 1, 0}, - 0x020F = { 3343, 1, 0}, 0x0210 = { 3344, 1, 0}, 0x0211 = { 3345, 1, 0}, 0x0212 = { 3346, 1, 0}, 0x0213 = { 3347, 1, 0}, 0x0214 = { 3348, 1, 0}, 0x0215 = { 3349, 1, 0}, 0x0216 = { 3350, 1, 0}, 0x0217 = { 3351, 1, 0}, 0x0218 = { 3352, 1, 0}, 0x0219 = { 3353, 1, 0}, 0x021A = { 3354, 1, 0}, 0x021B = { 3355, 1, 0}, 0x021C = { 3356, 1, 0}, 0x021D = { 3357, 1, 0}, 0x021E = { 3358, 1, 0}, - 0x021F = { 3359, 1, 0}, 0x0220 = { 3360, 1, 0}, 0x0221 = { 3361, 1, 0}, 0x0222 = { 3362, 1, 0}, 0x0223 = { 3363, 1, 0}, 0x0224 = { 3364, 1, 0}, 0x0225 = { 3365, 1, 0}, 0x0226 = { 3366, 1, 0}, 0x0227 = { 3367, 1, 0}, 0x0228 = { 3368, 1, 0}, 0x0229 = { 3369, 1, 0}, 0x022A = { 3370, 1, 0}, 0x022B = { 3371, 1, 0}, 0x022C = { 3372, 1, 0}, 0x022D = { 3373, 1, 0}, 0x022E = { 3374, 1, 0}, - 0x022F = { 3375, 1, 0}, 0x0230 = { 3376, 1, 0}, 0x0231 = { 3377, 1, 0}, 0x0232 = { 3378, 6, 0}, 0x0233 = { 3384, 1, 0}, 0x0234 = { 3385, 1, 0}, 0x0235 = { 3386, 1, 0}, 0x0236 = { 3387, 1, 0}, 0x0237 = { 3388, 1, 0}, 0x0238 = { 3389, 1, 0}, 0x0239 = { 3390, 1, 0}, 0x023A = { 3391, 1, 0}, 0x023B = { 3392, 1, 0}, 0x023C = { 3393, 1, 0}, 0x023D = { 3394, 1, 0}, 0x023E = { 3395, 1, 0}, - 0x023F = { 3396, 1, 0}, 0x0240 = { 3397, 1, 0}, 0x0241 = { 3398, 1, 0}, 0x0242 = { 3399, 1, 0}, 0x0243 = { 3400, 1, 0}, 0x0244 = { 3401, 1, 0}, 0x0245 = { 3402, 1, 0}, 0x0246 = { 3403, 1, 0}, 0x0247 = { 3404, 1, 0}, 0x0248 = { 3405, 1, 0}, 0x0249 = { 3406, 1, 0}, 0x024A = { 3407, 1, 0}, 0x024B = { 3408, 1, 0}, 0x024C = { 3409, 1, 0}, 0x024D = { 3410, 1, 0}, 0x024E = { 3411, 1, 0}, - 0x024F = { 3412, 1, 0}, 0x0250 = { 3413, 1, 0}, 0x0251 = { 3414, 1, 0}, 0x0252 = { 3415, 1, 0}, 0x0253 = { 3416, 1, 0}, 0x0254 = { 3417, 1, 0}, 0x0255 = { 3418, 1, 0}, 0x0256 = { 3419, 1, 0}, 0x0257 = { 3420, 1, 0}, 0x0258 = { 3421, 1, 0}, 0x0259 = { 3422, 1, 0}, 0x025A = { 3423, 1, 0}, 0x025B = { 3424, 1, 0}, 0x025C = { 3425, 1, 0}, 0x025D = { 3426, 1, 0}, 0x025E = { 3427, 1, 0}, - 0x025F = { 3428, 1, 0}, 0x0260 = { 3429, 1, 0}, 0x0261 = { 3430, 1, 0}, 0x0262 = { 3431, 1, 0}, 0x0263 = { 3432, 1, 0}, 0x0264 = { 3433, 1, 0}, 0x0265 = { 3434, 1, 0}, 0x0266 = { 3435, 1, 0}, 0x0267 = { 3436, 1, 0}, 0x0268 = { 3437, 1, 0}, 0x0269 = { 3438, 1, 0}, 0x026A = { 3439, 1, 0}, 0x026B = { 3440, 1, 0}, 0x026C = { 3441, 1, 0}, 0x026D = { 3442, 1, 0}, 0x026E = { 3443, 1, 0}, - 0x026F = { 3444, 1, 0}, 0x0270 = { 3445, 1, 0}, 0x0271 = { 3446, 1, 0}, 0x0272 = { 3447, 1, 0}, 0x0273 = { 3448, 1, 0}, 0x0274 = { 3449, 1, 0}, 0x0275 = { 3450, 1, 0}, 0x0276 = { 3451, 1, 0}, 0x0277 = { 3452, 1, 0}, 0x0278 = { 3453, 1, 0}, 0x0279 = { 3454, 1, 0}, 0x027A = { 3455, 1, 0}, 0x027B = { 3456, 1, 0}, 0x027C = { 3457, 1, 0}, 0x027D = { 3458, 1, 0}, 0x027E = { 3459, 1, 0}, - 0x027F = { 3460, 1, 0}, 0x0280 = { 3461, 1, 0}, 0x0281 = { 3462, 1, 0}, 0x0282 = { 3463, 1, 0}, 0x0283 = { 3464, 1, 0}, 0x0284 = { 3465, 1, 0}, 0x0285 = { 3466, 1, 0}, 0x0286 = { 3467, 1, 0}, 0x0287 = { 3468, 1, 0}, 0x0288 = { 3469, 1, 0}, 0x0289 = { 3470, 1, 0}, 0x028A = { 3471, 1, 0}, 0x028B = { 3472, 1, 0}, 0x028C = { 3473, 1, 0}, 0x028D = { 3474, 1, 0}, 0x028E = { 3475, 1, 0}, - 0x028F = { 3476, 1, 0}, 0x0290 = { 3477, 1, 0}, 0x0291 = { 3478, 1, 0}, 0x0292 = { 3479, 1, 0}, 0x0293 = { 3480, 1, 0}, 0x0294 = { 3481, 1, 0}, 0x0295 = { 3482, 1, 0}, 0x0296 = { 3483, 1, 0}, 0x0297 = { 3484, 1, 0}, 0x0298 = { 3485, 1, 0}, 0x0299 = { 3486, 1, 0}, 0x029A = { 3487, 1, 0}, 0x029B = { 3488, 1, 0}, 0x029C = { 3489, 1, 0}, 0x029D = { 3490, 1, 0}, 0x029E = { 3491, 1, 0}, - 0x029F = { 3492, 1, 0}, 0x02A0 = { 3493, 1, 0}, 0x02A1 = { 3494, 1, 0}, 0x02A2 = { 3495, 1, 0}, 0x02A3 = { 3496, 1, 0}, 0x02A4 = { 3497, 1, 0}, 0x02A5 = { 3498, 1, 0}, 0x02A6 = { 3499, 1, 0}, 0x02A7 = { 3500, 1, 0}, 0x02A8 = { 3501, 1, 0}, 0x02A9 = { 3502, 1, 0}, 0x02AA = { 3503, 1, 0}, 0x02AB = { 3504, 1, 0}, 0x02AC = { 3505, 1, 0}, 0x02AD = { 3506, 1, 0}, 0x02AE = { 3507, 1, 0}, - 0x02AF = { 3508, 1, 0}, 0x02B0 = { 3509, 1, 0}, 0x02B1 = { 3510, 1, 0}, 0x02B2 = { 3511, 1, 0}, 0x02B3 = { 3512, 1, 0}, 0x02B4 = { 3513, 1, 0}, 0x02B5 = { 3514, 1, 0}, 0x02B6 = { 3515, 1, 0}, 0x02B7 = { 3516, 1, 0}, 0x02B8 = { 3517, 1, 0}, 0x02B9 = { 3518, 1, 0}, 0x02BA = { 3519, 1, 0}, 0x02BB = { 3520, 1, 0}, 0x02BC = { 3521, 1, 0}, 0x02BD = { 3522, 1, 0}, 0x02BE = { 3523, 1, 0}, - 0x02BF = { 3524, 1, 0}, 0x02C0 = { 3525, 1, 0}, 0x02C1 = { 3526, 1, 0}, 0x02C2 = { 3527, 1, 0}, 0x02C3 = { 3528, 1, 0}, 0x02C4 = { 3529, 1, 0}, 0x02C5 = { 3530, 1, 0}, 0x02C6 = { 3531, 1, 0}, 0x02C7 = { 3532, 1, 0}, 0x02C8 = { 3533, 1, 0}, 0x02C9 = { 3534, 1, 0}, 0x02CA = { 3535, 1, 0}, 0x02CB = { 3536, 1, 0}, 0x02CC = { 3537, 1, 0}, 0x02CD = { 3538, 1, 0}, 0x02CE = { 3539, 1, 0}, - 0x02CF = { 3540, 1, 0}, 0x02D0 = { 3541, 1, 0}, 0x02D1 = { 3542, 1, 0}, 0x02D2 = { 3543, 1, 0}, 0x02D3 = { 3544, 1, 0}, 0x02D4 = { 3545, 1, 0}, 0x02D5 = { 3546, 1, 0}, 0x02D6 = { 3547, 1, 0}, 0x02D7 = { 3548, 1, 0}, 0x02D8 = { 3549, 1, 0}, 0x02D9 = { 3550, 1, 0}, 0x02DA = { 3551, 1, 0}, 0x02DB = { 3552, 1, 0}, 0x02DC = { 3553, 1, 0}, 0x02DD = { 3554, 1, 0}, 0x02DE = { 3555, 1, 0}, - 0x02DF = { 3556, 1, 0}, 0x02E0 = { 3557, 1, 0}, 0x02E1 = { 3558, 1, 0}, 0x02E2 = { 3559, 1, 0}, 0x02E3 = { 3560, 1, 0}, 0x02E4 = { 3561, 1, 0}, 0x02E5 = { 3562, 1, 0}, 0x02E6 = { 3563, 1, 0}, 0x02E7 = { 3564, 1, 0}, 0x02E8 = { 3565, 1, 0}, 0x02E9 = { 3566, 1, 0}, 0x02EA = { 3567, 1, 0}, 0x02EB = { 3568, 1, 0}, 0x02EC = { 3569, 1, 0}, 0x02ED = { 3570, 1, 0}, 0x02EE = { 3571, 1, 0}, - 0x02EF = { 3572, 1, 0}, 0x02F0 = { 3573, 1, 0}, 0x02F1 = { 3574, 1, 0}, 0x02F2 = { 3575, 1, 0}, 0x02F3 = { 3576, 1, 0}, 0x02F4 = { 3577, 1, 0}, 0x02F5 = { 3578, 1, 0}, 0x02F6 = { 3579, 1, 0}, 0x02F7 = { 3580, 1, 0}, 0x02F8 = { 3581, 1, 0}, 0x02F9 = { 3582, 1, 0}, 0x02FA = { 3583, 1, 0}, 0x02FB = { 3584, 1, 0}, 0x02FC = { 3585, 1, 0}, 0x02FD = { 3586, 1, 0}, 0x02FE = { 3587, 1, 0}, - 0x02FF = { 3588, 1, 0}, 0x0300 = { 3589, 2, 0}, 0x0301 = { 3591, 1, 0}, 0x0302 = { 3592, 1, 0}, 0x0303 = { 3593, 1, 0}, 0x0304 = { 3594, 1, 0}, 0x0305 = { 3595, 1, 0}, 0x0306 = { 3596, 1, 0}, 0x0307 = { 3597, 1, 0}, 0x0308 = { 3598, 1, 0}, 0x0309 = { 3599, 1, 0}, 0x030A = { 3600, 1, 0}, 0x030B = { 3601, 1, 0}, 0x030C = { 3602, 1, 0}, 0x030D = { 3603, 1, 0}, 0x030E = { 3604, 1, 0}, - 0x030F = { 3605, 1, 0}, 0x0310 = { 3606, 1, 0}, 0x0311 = { 3607, 1, 0}, 0x0312 = { 3608, 1, 0}, 0x0313 = { 3609, 1, 0}, 0x0314 = { 3610, 1, 0}, 0x0315 = { 3611, 1, 0}, 0x0316 = { 3612, 1, 0}, 0x0317 = { 3613, 1, 0}, 0x0318 = { 3614, 1, 0}, 0x0319 = { 3615, 1, 0}, 0x031A = { 3616, 1, 0}, 0x031B = { 3617, 1, 0}, 0x031C = { 3618, 1, 0}, 0x031D = { 3619, 1, 0}, 0x031E = { 3620, 1, 0}, - 0x031F = { 3621, 1, 0}, 0x0320 = { 3622, 1, 0}, 0x0321 = { 3623, 1, 0}, 0x0322 = { 3624, 1, 0}, 0x0323 = { 3625, 1, 0}, 0x0324 = { 3626, 1, 0}, 0x0325 = { 3627, 1, 0}, 0x0326 = { 3628, 1, 0}, 0x0327 = { 3629, 1, 0}, 0x0328 = { 3630, 1, 0}, 0x0329 = { 3631, 1, 0}, 0x032A = { 3632, 1, 0}, 0x032B = { 3633, 1, 0}, 0x032C = { 3634, 1, 0}, 0x032D = { 3635, 1, 0}, 0x032E = { 3636, 1, 0}, - 0x032F = { 3637, 1, 0}, 0x0330 = { 3638, 1, 0}, 0x0331 = { 3639, 1, 0}, 0x0332 = { 3640, 6, 0}, 0x0333 = { 3646, 1, 0}, 0x0334 = { 3647, 1, 0}, 0x0335 = { 3648, 1, 0}, 0x0336 = { 3649, 1, 0}, 0x0337 = { 3650, 1, 0}, 0x0338 = { 3651, 1, 0}, 0x0339 = { 3652, 1, 0}, 0x033A = { 3653, 1, 0}, 0x033B = { 3654, 1, 0}, 0x033C = { 3655, 1, 0}, 0x033D = { 3656, 1, 0}, 0x033E = { 3657, 1, 0}, - 0x033F = { 3658, 1, 0}, 0x0340 = { 3659, 1, 0}, 0x0341 = { 3660, 1, 0}, 0x0342 = { 3661, 1, 0}, 0x0343 = { 3662, 1, 0}, 0x0344 = { 3663, 1, 0}, 0x0345 = { 3664, 1, 0}, 0x0346 = { 3665, 1, 0}, 0x0347 = { 3666, 1, 0}, 0x0348 = { 3667, 1, 0}, 0x0349 = { 3668, 1, 0}, 0x034A = { 3669, 1, 0}, 0x034B = { 3670, 1, 0}, 0x034C = { 3671, 1, 0}, 0x034D = { 3672, 1, 0}, 0x034E = { 3673, 1, 0}, - 0x034F = { 3674, 1, 0}, 0x0350 = { 3675, 1, 0}, 0x0351 = { 3676, 1, 0}, 0x0352 = { 3677, 1, 0}, 0x0353 = { 3678, 1, 0}, 0x0354 = { 3679, 1, 0}, 0x0355 = { 3680, 1, 0}, 0x0356 = { 3681, 1, 0}, 0x0357 = { 3682, 1, 0}, 0x0358 = { 3683, 1, 0}, 0x0359 = { 3684, 1, 0}, 0x035A = { 3685, 1, 0}, 0x035B = { 3686, 1, 0}, 0x035C = { 3687, 1, 0}, 0x035D = { 3688, 1, 0}, 0x035E = { 3689, 1, 0}, - 0x035F = { 3690, 1, 0}, 0x0360 = { 3691, 1, 0}, 0x0361 = { 3692, 1, 0}, 0x0362 = { 3693, 1, 0}, 0x0363 = { 3694, 1, 0}, 0x0364 = { 3695, 1, 0}, 0x0365 = { 3696, 1, 0}, 0x0366 = { 3697, 1, 0}, 0x0367 = { 3698, 1, 0}, 0x0368 = { 3699, 1, 0}, 0x0369 = { 3700, 1, 0}, 0x036A = { 3701, 1, 0}, 0x036B = { 3702, 1, 0}, 0x036C = { 3703, 1, 0}, 0x036D = { 3704, 1, 0}, 0x036E = { 3705, 1, 0}, - 0x036F = { 3706, 1, 0}, 0x0370 = { 3707, 1, 0}, 0x0371 = { 3708, 1, 0}, 0x0372 = { 3709, 1, 0}, 0x0373 = { 3710, 1, 0}, 0x0374 = { 3711, 1, 0}, 0x0375 = { 3712, 1, 0}, 0x0376 = { 3713, 1, 0}, 0x0377 = { 3714, 1, 0}, 0x0378 = { 3715, 1, 0}, 0x0379 = { 3716, 1, 0}, 0x037A = { 3717, 1, 0}, 0x037B = { 3718, 1, 0}, 0x037C = { 3719, 1, 0}, 0x037D = { 3720, 1, 0}, 0x037E = { 3721, 1, 0}, - 0x037F = { 3722, 1, 0}, 0x0380 = { 3723, 1, 0}, 0x0381 = { 3724, 1, 0}, 0x0382 = { 3725, 1, 0}, 0x0383 = { 3726, 1, 0}, 0x0384 = { 3727, 1, 0}, 0x0385 = { 3728, 1, 0}, 0x0386 = { 3729, 1, 0}, 0x0387 = { 3730, 1, 0}, 0x0388 = { 3731, 1, 0}, 0x0389 = { 3732, 1, 0}, 0x038A = { 3733, 1, 0}, 0x038B = { 3734, 1, 0}, 0x038C = { 3735, 1, 0}, 0x038D = { 3736, 1, 0}, 0x038E = { 3737, 1, 0}, - 0x038F = { 3738, 1, 0}, 0x0390 = { 3739, 1, 0}, 0x0391 = { 3740, 1, 0}, 0x0392 = { 3741, 1, 0}, 0x0393 = { 3742, 1, 0}, 0x0394 = { 3743, 1, 0}, 0x0395 = { 3744, 1, 0}, 0x0396 = { 3745, 1, 0}, 0x0397 = { 3746, 1, 0}, 0x0398 = { 3747, 1, 0}, 0x0399 = { 3748, 1, 0}, 0x039A = { 3749, 1, 0}, 0x039B = { 3750, 1, 0}, 0x039C = { 3751, 1, 0}, 0x039D = { 3752, 1, 0}, 0x039E = { 3753, 1, 0}, - 0x039F = { 3754, 1, 0}, 0x03A0 = { 3755, 1, 0}, 0x03A1 = { 3756, 1, 0}, 0x03A2 = { 3757, 1, 0}, 0x03A3 = { 3758, 1, 0}, 0x03A4 = { 3759, 1, 0}, 0x03A5 = { 3760, 1, 0}, 0x03A6 = { 3761, 1, 0}, 0x03A7 = { 3762, 1, 0}, 0x03A8 = { 3763, 1, 0}, 0x03A9 = { 3764, 1, 0}, 0x03AA = { 3765, 1, 0}, 0x03AB = { 3766, 1, 0}, 0x03AC = { 3767, 1, 0}, 0x03AD = { 3768, 1, 0}, 0x03AE = { 3769, 1, 0}, - 0x03AF = { 3770, 1, 0}, 0x03B0 = { 3771, 1, 0}, 0x03B1 = { 3772, 1, 0}, 0x03B2 = { 3773, 1, 0}, 0x03B3 = { 3774, 1, 0}, 0x03B4 = { 3775, 1, 0}, 0x03B5 = { 3776, 1, 0}, 0x03B6 = { 3777, 1, 0}, 0x03B7 = { 3778, 1, 0}, 0x03B8 = { 3779, 1, 0}, 0x03B9 = { 3780, 1, 0}, 0x03BA = { 3781, 1, 0}, 0x03BB = { 3782, 1, 0}, 0x03BC = { 3783, 1, 0}, 0x03BD = { 3784, 1, 0}, 0x03BE = { 3785, 1, 0}, - 0x03BF = { 3786, 1, 0}, 0x03C0 = { 3787, 1, 0}, 0x03C1 = { 3788, 1, 0}, 0x03C2 = { 3789, 1, 0}, 0x03C3 = { 3790, 1, 0}, 0x03C4 = { 3791, 1, 0}, 0x03C5 = { 3792, 1, 0}, 0x03C6 = { 3793, 1, 0}, 0x03C7 = { 3794, 1, 0}, 0x03C8 = { 3795, 1, 0}, 0x03C9 = { 3796, 1, 0}, 0x03CA = { 3797, 1, 0}, 0x03CB = { 3798, 1, 0}, 0x03CC = { 3799, 1, 0}, 0x03CD = { 3800, 1, 0}, 0x03CE = { 3801, 1, 0}, - 0x03CF = { 3802, 1, 0}, 0x03D0 = { 3803, 1, 0}, 0x03D1 = { 3804, 1, 0}, 0x03D2 = { 3805, 1, 0}, 0x03D3 = { 3806, 1, 0}, 0x03D4 = { 3807, 1, 0}, 0x03D5 = { 3808, 1, 0}, 0x03D6 = { 3809, 1, 0}, 0x03D7 = { 3810, 1, 0}, 0x03D8 = { 3811, 1, 0}, 0x03D9 = { 3812, 1, 0}, 0x03DA = { 3813, 1, 0}, 0x03DB = { 3814, 1, 0}, 0x03DC = { 3815, 1, 0}, 0x03DD = { 3816, 1, 0}, 0x03DE = { 3817, 1, 0}, - 0x03DF = { 3818, 1, 0}, 0x03E0 = { 3819, 1, 0}, 0x03E1 = { 3820, 1, 0}, 0x03E2 = { 3821, 1, 0}, 0x03E3 = { 3822, 1, 0}, 0x03E4 = { 3823, 1, 0}, 0x03E5 = { 3824, 1, 0}, 0x03E6 = { 3825, 1, 0}, 0x03E7 = { 3826, 1, 0}, 0x03E8 = { 3827, 1, 0}, 0x03E9 = { 3828, 1, 0}, 0x03EA = { 3829, 1, 0}, 0x03EB = { 3830, 1, 0}, 0x03EC = { 3831, 1, 0}, 0x03ED = { 3832, 1, 0}, 0x03EE = { 3833, 1, 0}, - 0x03EF = { 3834, 1, 0}, 0x03F0 = { 3835, 1, 0}, 0x03F1 = { 3836, 1, 0}, 0x03F2 = { 3837, 1, 0}, 0x03F3 = { 3838, 1, 0}, 0x03F4 = { 3839, 1, 0}, 0x03F5 = { 3840, 1, 0}, 0x03F6 = { 3841, 1, 0}, 0x03F7 = { 3842, 1, 0}, 0x03F8 = { 3843, 1, 0}, 0x03F9 = { 3844, 1, 0}, 0x03FA = { 3845, 1, 0}, 0x03FB = { 3846, 1, 0}, 0x03FC = { 3847, 1, 0}, 0x03FD = { 3848, 1, 0}, 0x03FE = { 3849, 1, 0}, - 0x03FF = { 3850, 1, 0}, 0x0400 = { 3851, 14, 0}, 0x0401 = { 3865, 23, 0}, 0x0402 = { 3888, 13, 0}, 0x0403 = { 3901, 11, 0}, 0x0404 = { 3912, 30, 0}, 0x0405 = { 3942, 15, 0}, 0x0406 = { 3957, 39, 0}, 0x0407 = { 3996, 13, 0}, 0x0408 = { 4009, 8, 0}, 0x0409 = { 4017, 3, 0}, 0x040A = { 4020, 4, 0}, 0x040B = { 4024, 9, 0}, 0x040C = { 4033, 15, 0}, 0x040D = { 4048, 8, 0}, 0x040E = { 4056, 48, 0}, - 0x040F = { 4104, 9, 0}, 0x0410 = { 4113, 6, 0}, 0x0411 = { 4119, 6, 0}, 0x0412 = { 4125, 8, 0}, 0x0413 = { 4133, 5, 0}, 0x0414 = { 4138, 23, 0}, 0x0415 = { 4161, 23, 0}, 0x0416 = { 4184, 7, 0}, 0x0417 = { 4191, 8, 0}, 0x0418 = { 4199, 10, 0}, 0x0419 = { 4209, 9, 0}, 0x041A = { 4218, 6, 0}, 0x041C = { 4224, 8, 0}, 0x041D = { 4232, 8, 0}, 0x041E = { 4240, 10, 0}, 0x041F = { 4250, 7, 0}, - 0x0420 = { 4257, 12, 0}, 0x0421 = { 4269, 26, 0}, 0x0422 = { 4295, 7, 0}, 0x0423 = { 4302, 10, 0}, 0x0424 = { 4312, 8, 0}, 0x0425 = { 4320, 7, 0}, 0x0426 = { 4327, 13, 0}, 0x0427 = { 4340, 13, 0}, 0x0428 = { 4353, 8, 0}, 0x0429 = { 4361, 4, 0}, 0x042A = { 4365, 6, 0}, 0x042B = { 4371, 7, 0}, 0x042C = { 4378, 11, 0}, 0x042D = { 4389, 5, 0}, 0x042E = { 4394, 8, 0}, 0x042F = { 4402, 6, 0}, - 0x0430 = { 4408, 6, 0}, 0x0431 = { 4414, 6, 0}, 0x0432 = { 4420, 6, 0}, 0x0433 = { 4426, 8, 0}, 0x0434 = { 4434, 7, 0}, 0x0435 = { 4441, 7, 0}, 0x0436 = { 4448, 7, 0}, 0x0437 = { 4455, 9, 0}, 0x0438 = { 4464, 6, 0}, 0x0439 = { 4470, 8, 0}, 0x043A = { 4478, 4, 0}, 0x043B = { 4482, 7, 0}, 0x043C = { 4489, 7, 0}, 0x043D = { 4496, 6, 0}, 0x043E = { 4502, 6, 0}, 0x043F = { 4508, 8, 0}, - 0x0440 = { 4516, 12, 0}, 0x0441 = { 4528, 11, 0}, 0x0442 = { 4539, 9, 0}, 0x0443 = { 4548, 11, 0}, 0x0444 = { 4559, 12, 0}, 0x0445 = { 4571, 11, 0}, 0x0446 = { 4582, 11, 0}, 0x0447 = { 4593, 9, 0}, 0x0448 = { 4602, 8, 0}, 0x0449 = { 4610, 6, 0}, 0x044A = { 4616, 7, 0}, 0x044B = { 4623, 6, 0}, 0x044C = { 4629, 11, 0}, 0x044D = { 4640, 7, 0}, 0x044E = { 4647, 8, 0}, 0x044F = { 4655, 7, 0}, - 0x0450 = { 4662, 8, 0}, 0x0451 = { 4670, 7, 0}, 0x0452 = { 4677, 6, 0}, 0x0453 = { 4683, 6, 0}, 0x0454 = { 4689, 8, 0}, 0x0455 = { 4697, 8, 0}, 0x0456 = { 4705, 6, 0}, 0x0457 = { 4711, 10, 0}, 0x0458 = { 4721, 7, 0}, 0x0459 = { 4728, 6, 0}, 0x045A = { 4734, 2, 0}, 0x045B = { 4736, 2, 0}, 0x045C = { 4738, 8, 0}, 0x045D = { 4746, 7, 0}, 0x045E = { 4753, 8, 0}, 0x045F = { 4761, 8, 0}, - 0x0460 = { 4769, 10, 0}, 0x0461 = { 4779, 7, 0}, 0x0462 = { 4786, 35, 0}, 0x0463 = { 4821, 13, 0}, 0x0464 = { 4834, 10, 0}, 0x0465 = { 4844, 8, 0}, 0x0466 = { 4852, 8, 0}, 0x0467 = { 4860, 11, 0}, 0x0468 = { 4871, 7, 0}, 0x0469 = { 4878, 6, 0}, 0x046A = { 4884, 9, 0}, 0x046B = { 4893, 8, 0}, 0x046C = { 4901, 10, 0}, 0x046D = { 4911, 6, 0}, 0x046E = { 4917, 12, 0}, 0x046F = { 4929, 6, 0}, - 0x0470 = { 4935, 4, 0}, 0x0471 = { 4939, 5, 0}, 0x0472 = { 4944, 4, 0}, 0x0473 = { 4948, 4, 0}, 0x0474 = { 4952, 4, 0}, 0x0475 = { 4956, 6, 0}, 0x0476 = { 4962, 3, 0}, 0x0477 = { 4965, 6, 0}, 0x0478 = { 4971, 5, 0}, 0x0479 = { 4976, 5, 0}, 0x047A = { 4981, 3, 0}, 0x047B = { 4984, 2, 0}, 0x047C = { 4986, 3, 0}, 0x047D = { 4989, 4, 0}, 0x047E = { 4993, 6, 0}, 0x047F = { 4999, 5, 0}, - 0x0480 = { 5004, 12, 0}, 0x0481 = { 5016, 11, 0}, 0x0482 = { 5027, 11, 0}, 0x0483 = { 5038, 8, 0}, 0x0484 = { 5046, 11, 0}, 0x0485 = { 5057, 12, 0}, 0x0486 = { 5069, 9, 0}, 0x0487 = { 5078, 8, 0}, 0x0488 = { 5086, 12, 0}, 0x0489 = { 5098, 5, 0}, 0x048A = { 5103, 6, 0}, 0x048B = { 5109, 5, 0}, 0x048C = { 5114, 16, 0}, 0x048D = { 5130, 7, 0}, 0x048E = { 5137, 6, 0}, 0x048F = { 5143, 5, 0}, - 0x0490 = { 5148, 4, 0}, 0x0491 = { 5152, 5, 0}, 0x0492 = { 5157, 4, 0}, 0x0493 = { 5161, 4, 0}, 0x0494 = { 5165, 6, 0}, 0x0495 = { 5171, 7, 0}, 0x0496 = { 5178, 5, 0}, 0x0497 = { 5183, 7, 0}, 0x0498 = { 5190, 6, 0}, 0x0499 = { 5196, 7, 0}, 0x049A = { 5203, 2, 0}, 0x049B = { 5205, 2, 0}, 0x049C = { 5207, 6, 0}, 0x049D = { 5213, 7, 0}, 0x049E = { 5220, 6, 0}, 0x049F = { 5226, 6, 0}, - 0x04A0 = { 5232, 13, 0}, 0x04A1 = { 5245, 12, 0}, 0x04A2 = { 5257, 11, 0}, 0x04A3 = { 5268, 10, 0}, 0x04A4 = { 5278, 10, 0}, 0x04A5 = { 5288, 10, 0}, 0x04A6 = { 5298, 12, 0}, 0x04A7 = { 5310, 9, 0}, 0x04A8 = { 5319, 10, 0}, 0x04A9 = { 5329, 5, 0}, 0x04AA = { 5334, 5, 0}, 0x04AB = { 5339, 8, 0}, 0x04AC = { 5347, 16, 0}, 0x04AD = { 5363, 7, 0}, 0x04AE = { 5370, 13, 0}, 0x04AF = { 5383, 7, 0}, - 0x04B0 = { 5390, 4, 0}, 0x04B1 = { 5394, 5, 0}, 0x04B2 = { 5399, 6, 0}, 0x04B3 = { 5405, 6, 0}, 0x04B4 = { 5411, 4, 0}, 0x04B5 = { 5415, 6, 0}, 0x04B6 = { 5421, 5, 0}, 0x04B7 = { 5426, 8, 0}, 0x04B8 = { 5434, 6, 0}, 0x04B9 = { 5440, 7, 0}, 0x04BA = { 5447, 3, 0}, 0x04BB = { 5450, 3, 0}, 0x04BC = { 5453, 6, 0}, 0x04BD = { 5459, 7, 0}, 0x04BE = { 5466, 7, 0}, 0x04BF = { 5473, 7, 0}, - 0x04C0 = { 5480, 14, 0}, 0x04C1 = { 5494, 9, 0}, 0x04C2 = { 5503, 9, 0}, 0x04C3 = { 5512, 10, 0}, 0x04C4 = { 5522, 8, 0}, 0x04C5 = { 5530, 9, 0}, 0x04C6 = { 5539, 9, 0}, 0x04C7 = { 5548, 7, 0}, 0x04C8 = { 5555, 4, 0}, 0x04C9 = { 5559, 3, 0}, 0x04CA = { 5562, 6, 0}, 0x04CB = { 5568, 5, 0}, 0x04CC = { 5573, 14, 0}, 0x04CD = { 5587, 4, 0}, 0x04CE = { 5591, 4, 0}, 0x04CF = { 5595, 5, 0}, - 0x04D0 = { 5600, 2, 0}, 0x04D1 = { 5602, 3, 0}, 0x04D2 = { 5605, 4, 0}, 0x04D3 = { 5609, 4, 0}, 0x04D4 = { 5613, 6, 0}, 0x04D5 = { 5619, 4, 0}, 0x04D6 = { 5623, 3, 0}, 0x04D7 = { 5626, 7, 0}, 0x04D8 = { 5633, 4, 0}, 0x04D9 = { 5637, 5, 0}, 0x04DA = { 5642, 2, 0}, 0x04DB = { 5644, 2, 0}, 0x04DC = { 5646, 4, 0}, 0x04DD = { 5650, 4, 0}, 0x04DE = { 5654, 4, 0}, 0x04DF = { 5658, 6, 0}, - 0x04E0 = { 5664, 5, 0}, 0x04E1 = { 5669, 8, 0}, 0x04E2 = { 5677, 9, 0}, 0x04E3 = { 5686, 11, 0}, 0x04E4 = { 5697, 9, 0}, 0x04E5 = { 5706, 10, 0}, 0x04E6 = { 5716, 8, 0}, 0x04E7 = { 5724, 6, 0}, 0x04E8 = { 5730, 4, 0}, 0x04E9 = { 5734, 2, 0}, 0x04EA = { 5736, 3, 0}, 0x04EB = { 5739, 4, 0}, 0x04EC = { 5743, 14, 0}, 0x04ED = { 5757, 4, 0}, 0x04EE = { 5761, 11, 0}, 0x04EF = { 5772, 4, 0}, - 0x04F0 = { 5776, 2, 0}, 0x04F1 = { 5778, 2, 0}, 0x04F2 = { 5780, 4, 0}, 0x04F3 = { 5784, 3, 0}, 0x04F4 = { 5787, 4, 0}, 0x04F5 = { 5791, 3, 0}, 0x04F6 = { 5794, 4, 0}, 0x04F7 = { 5798, 5, 0}, 0x04F8 = { 5803, 4, 0}, 0x04F9 = { 5807, 4, 0}, 0x04FA = { 5811, 1, 0}, 0x04FC = { 5812, 4, 0}, 0x04FD = { 5816, 4, 0}, 0x04FE = { 5820, 5, 0}, 0x04FF = { 5825, 4, 0}, 0x0508 = { 5829, 5, 0}, - 0x0518 = { 5834, 3, 0}, 0x0528 = { 5837, 3, 0}, 0x0538 = { 5840, 3, 0}, 0x0548 = { 5843, 4, 0}, 0x0558 = { 5847, 3, 0}, 0x0568 = { 5850, 2, 0}, 0x0578 = { 5852, 3, 0}, 0x0588 = { 5855, 3, 0}, 0x0598 = { 5858, 1, 0}, 0x05A8 = { 5859, 1, 0}, 0x05B8 = { 5860, 1, 0}, 0x05C8 = { 5861, 3, 0}, 0x05E8 = { 5864, 1, 0}, 0x0600 = { 5865, 4, 0}, 0x0618 = { 5869, 1, 0}, 0x0620 = { 5870, 2, 0}, - 0x0640 = { 5872, 2, 0}, 0x0660 = { 5874, 2, 0}, 0x0680 = { 5876, 2, 0}, 0x0698 = { 5878, 2, 0}, 0x06B8 = { 5880, 1, 0}, 0x06C8 = { 5881, 1, 0}, 0x06F8 = { 5882, 1, 0}, 0x0700 = { 5883, 2, 0}, 0x0701 = { 5885, 1, 0}, 0x0702 = { 5886, 1, 0}, 0x0703 = { 5887, 1, 0}, 0x0704 = { 5888, 1, 0}, 0x0705 = { 5889, 1, 0}, 0x0706 = { 5890, 1, 0}, 0x0707 = { 5891, 1, 0}, 0x0708 = { 5892, 1, 0}, - 0x0709 = { 5893, 1, 0}, 0x070A = { 5894, 1, 0}, 0x070B = { 5895, 1, 0}, 0x070C = { 5896, 1, 0}, 0x070D = { 5897, 1, 0}, 0x070E = { 5898, 1, 0}, 0x070F = { 5899, 1, 0}, 0x0710 = { 5900, 1, 0}, 0x0711 = { 5901, 1, 0}, 0x0712 = { 5902, 1, 0}, 0x0713 = { 5903, 1, 0}, 0x0714 = { 5904, 1, 0}, 0x0715 = { 5905, 1, 0}, 0x0716 = { 5906, 1, 0}, 0x0717 = { 5907, 1, 0}, 0x0718 = { 5908, 1, 0}, - 0x0719 = { 5909, 1, 0}, 0x071A = { 5910, 1, 0}, 0x071B = { 5911, 1, 0}, 0x071C = { 5912, 1, 0}, 0x071D = { 5913, 1, 0}, 0x071E = { 5914, 1, 0}, 0x071F = { 5915, 1, 0}, 0x0720 = { 5916, 1, 0}, 0x0721 = { 5917, 1, 0}, 0x0722 = { 5918, 1, 0}, 0x0723 = { 5919, 1, 0}, 0x0724 = { 5920, 1, 0}, 0x0725 = { 5921, 1, 0}, 0x0726 = { 5922, 1, 0}, 0x0727 = { 5923, 1, 0}, 0x0728 = { 5924, 1, 0}, - 0x0729 = { 5925, 1, 0}, 0x072A = { 5926, 1, 0}, 0x072B = { 5927, 1, 0}, 0x072C = { 5928, 1, 0}, 0x072D = { 5929, 1, 0}, 0x072E = { 5930, 1, 0}, 0x072F = { 5931, 1, 0}, 0x0730 = { 5932, 1, 0}, 0x0731 = { 5933, 1, 0}, 0x0732 = { 5934, 1, 0}, 0x0733 = { 5935, 1, 0}, 0x0734 = { 5936, 1, 0}, 0x0735 = { 5937, 1, 0}, 0x0736 = { 5938, 1, 0}, 0x0737 = { 5939, 1, 0}, 0x0738 = { 5940, 1, 0}, - 0x0739 = { 5941, 1, 0}, 0x073A = { 5942, 1, 0}, 0x073B = { 5943, 1, 0}, 0x073C = { 5944, 1, 0}, 0x073D = { 5945, 1, 0}, 0x073E = { 5946, 1, 0}, 0x073F = { 5947, 1, 0}, 0x0740 = { 5948, 1, 0}, 0x0741 = { 5949, 1, 0}, 0x0742 = { 5950, 1, 0}, 0x0743 = { 5951, 1, 0}, 0x0744 = { 5952, 1, 0}, 0x0745 = { 5953, 1, 0}, 0x0746 = { 5954, 1, 0}, 0x0747 = { 5955, 1, 0}, 0x0748 = { 5956, 1, 0}, - 0x0749 = { 5957, 1, 0}, 0x074A = { 5958, 1, 0}, 0x074B = { 5959, 1, 0}, 0x074C = { 5960, 1, 0}, 0x074D = { 5961, 1, 0}, 0x074E = { 5962, 1, 0}, 0x074F = { 5963, 1, 0}, 0x0750 = { 5964, 1, 0}, 0x0751 = { 5965, 1, 0}, 0x0752 = { 5966, 1, 0}, 0x0753 = { 5967, 1, 0}, 0x0754 = { 5968, 1, 0}, 0x0755 = { 5969, 1, 0}, 0x0756 = { 5970, 1, 0}, 0x0757 = { 5971, 1, 0}, 0x0758 = { 5972, 1, 0}, - 0x0759 = { 5973, 1, 0}, 0x075A = { 5974, 1, 0}, 0x075B = { 5975, 1, 0}, 0x075C = { 5976, 1, 0}, 0x075D = { 5977, 1, 0}, 0x075E = { 5978, 1, 0}, 0x075F = { 5979, 1, 0}, 0x0760 = { 5980, 1, 0}, 0x0761 = { 5981, 1, 0}, 0x0762 = { 5982, 1, 0}, 0x0763 = { 5983, 1, 0}, 0x0764 = { 5984, 1, 0}, 0x0765 = { 5985, 1, 0}, 0x0766 = { 5986, 1, 0}, 0x0767 = { 5987, 1, 0}, 0x0768 = { 5988, 1, 0}, - 0x0769 = { 5989, 1, 0}, 0x076A = { 5990, 1, 0}, 0x076B = { 5991, 1, 0}, 0x076C = { 5992, 1, 0}, 0x076D = { 5993, 1, 0}, 0x076E = { 5994, 1, 0}, 0x076F = { 5995, 1, 0}, 0x0770 = { 5996, 1, 0}, 0x0771 = { 5997, 1, 0}, 0x0772 = { 5998, 1, 0}, 0x0773 = { 5999, 1, 0}, 0x0774 = { 6000, 1, 0}, 0x0775 = { 6001, 1, 0}, 0x0776 = { 6002, 1, 0}, 0x0777 = { 6003, 1, 0}, 0x0778 = { 6004, 1, 0}, - 0x0779 = { 6005, 1, 0}, 0x077A = { 6006, 1, 0}, 0x077B = { 6007, 1, 0}, 0x077C = { 6008, 1, 0}, 0x077D = { 6009, 1, 0}, 0x077E = { 6010, 1, 0}, 0x077F = { 6011, 1, 0}, 0x0780 = { 6012, 1, 0}, 0x0781 = { 6013, 1, 0}, 0x0782 = { 6014, 1, 0}, 0x0783 = { 6015, 1, 0}, 0x0784 = { 6016, 1, 0}, 0x0785 = { 6017, 1, 0}, 0x0786 = { 6018, 1, 0}, 0x0787 = { 6019, 1, 0}, 0x0788 = { 6020, 1, 0}, - 0x0789 = { 6021, 1, 0}, 0x078A = { 6022, 1, 0}, 0x078B = { 6023, 1, 0}, 0x078C = { 6024, 1, 0}, 0x078D = { 6025, 1, 0}, 0x078E = { 6026, 1, 0}, 0x078F = { 6027, 1, 0}, 0x0790 = { 6028, 1, 0}, 0x0791 = { 6029, 1, 0}, 0x0792 = { 6030, 1, 0}, 0x0793 = { 6031, 1, 0}, 0x0794 = { 6032, 1, 0}, 0x0795 = { 6033, 1, 0}, 0x0796 = { 6034, 1, 0}, 0x0797 = { 6035, 1, 0}, 0x0798 = { 6036, 1, 0}, - 0x0799 = { 6037, 1, 0}, 0x079A = { 6038, 1, 0}, 0x079B = { 6039, 1, 0}, 0x079C = { 6040, 1, 0}, 0x079D = { 6041, 1, 0}, 0x079E = { 6042, 1, 0}, 0x079F = { 6043, 1, 0}, 0x07A0 = { 6044, 1, 0}, 0x07A1 = { 6045, 1, 0}, 0x07A2 = { 6046, 1, 0}, 0x07A3 = { 6047, 1, 0}, 0x07A4 = { 6048, 1, 0}, 0x07A5 = { 6049, 1, 0}, 0x07A6 = { 6050, 1, 0}, 0x07A7 = { 6051, 1, 0}, 0x07A8 = { 6052, 1, 0}, - 0x07A9 = { 6053, 1, 0}, 0x07AA = { 6054, 1, 0}, 0x07AB = { 6055, 1, 0}, 0x07AC = { 6056, 1, 0}, 0x07AD = { 6057, 1, 0}, 0x07AE = { 6058, 1, 0}, 0x07AF = { 6059, 1, 0}, 0x07B0 = { 6060, 1, 0}, 0x07B1 = { 6061, 1, 0}, 0x07B2 = { 6062, 1, 0}, 0x07B3 = { 6063, 1, 0}, 0x07B4 = { 6064, 1, 0}, 0x07B5 = { 6065, 1, 0}, 0x07B6 = { 6066, 1, 0}, 0x07B7 = { 6067, 1, 0}, 0x07B8 = { 6068, 1, 0}, - 0x07B9 = { 6069, 1, 0}, 0x07BA = { 6070, 1, 0}, 0x07BB = { 6071, 1, 0}, 0x07BC = { 6072, 1, 0}, 0x07BD = { 6073, 1, 0}, 0x07BE = { 6074, 1, 0}, 0x07BF = { 6075, 1, 0}, 0x07C0 = { 6076, 1, 0}, 0x07C1 = { 6077, 1, 0}, 0x07C2 = { 6078, 1, 0}, 0x07C3 = { 6079, 1, 0}, 0x07C4 = { 6080, 1, 0}, 0x07C5 = { 6081, 1, 0}, 0x07C6 = { 6082, 1, 0}, 0x07C7 = { 6083, 1, 0}, 0x07C8 = { 6084, 1, 0}, - 0x07C9 = { 6085, 1, 0}, 0x07CA = { 6086, 1, 0}, 0x07CB = { 6087, 1, 0}, 0x07CC = { 6088, 1, 0}, 0x07CD = { 6089, 1, 0}, 0x07CE = { 6090, 1, 0}, 0x07CF = { 6091, 1, 0}, 0x07D0 = { 6092, 1, 0}, 0x07D1 = { 6093, 1, 0}, 0x07D2 = { 6094, 1, 0}, 0x07D3 = { 6095, 1, 0}, 0x07D4 = { 6096, 1, 0}, 0x07D5 = { 6097, 1, 0}, 0x07D6 = { 6098, 1, 0}, 0x07D7 = { 6099, 1, 0}, 0x07D8 = { 6100, 1, 0}, - 0x07D9 = { 6101, 1, 0}, 0x07DA = { 6102, 1, 0}, 0x07DB = { 6103, 1, 0}, 0x07DC = { 6104, 1, 0}, 0x07DD = { 6105, 1, 0}, 0x07DE = { 6106, 1, 0}, 0x07DF = { 6107, 1, 0}, 0x07E0 = { 6108, 1, 0}, 0x07E1 = { 6109, 1, 0}, 0x07E2 = { 6110, 1, 0}, 0x07E3 = { 6111, 1, 0}, 0x07E4 = { 6112, 1, 0}, 0x07E5 = { 6113, 1, 0}, 0x07E6 = { 6114, 1, 0}, 0x07E7 = { 6115, 1, 0}, 0x07E8 = { 6116, 1, 0}, - 0x07E9 = { 6117, 1, 0}, 0x07EA = { 6118, 1, 0}, 0x07EB = { 6119, 1, 0}, 0x07EC = { 6120, 1, 0}, 0x07ED = { 6121, 1, 0}, 0x07EE = { 6122, 1, 0}, 0x07EF = { 6123, 1, 0}, 0x07F0 = { 6124, 1, 0}, 0x07F1 = { 6125, 1, 0}, 0x07F2 = { 6126, 1, 0}, 0x07F3 = { 6127, 1, 0}, 0x07F4 = { 6128, 1, 0}, 0x07F5 = { 6129, 1, 0}, 0x07F6 = { 6130, 1, 0}, 0x07F7 = { 6131, 1, 0}, 0x07F8 = { 6132, 1, 0}, - 0x07F9 = { 6133, 1, 0}, 0x07FA = { 6134, 1, 0}, 0x07FB = { 6135, 1, 0}, 0x07FC = { 6136, 1, 0}, 0x07FD = { 6137, 1, 0}, 0x07FE = { 6138, 1, 0}, 0x07FF = { 6139, 1, 0}, 0x0800 = { 6140, 2, 0}, 0x0801 = { 6142, 1, 0}, 0x0802 = { 6143, 1, 0}, 0x0803 = { 6144, 1, 0}, 0x0804 = { 6145, 1, 0}, 0x0805 = { 6146, 1, 0}, 0x0806 = { 6147, 1, 0}, 0x0807 = { 6148, 1, 0}, 0x0808 = { 6149, 1, 0}, - 0x0809 = { 6150, 1, 0}, 0x080A = { 6151, 1, 0}, 0x080B = { 6152, 1, 0}, 0x080C = { 6153, 1, 0}, 0x080D = { 6154, 1, 0}, 0x080E = { 6155, 1, 0}, 0x080F = { 6156, 1, 0}, 0x0810 = { 6157, 1, 0}, 0x0811 = { 6158, 1, 0}, 0x0812 = { 6159, 1, 0}, 0x0813 = { 6160, 1, 0}, 0x0814 = { 6161, 1, 0}, 0x0815 = { 6162, 1, 0}, 0x0816 = { 6163, 1, 0}, 0x0817 = { 6164, 1, 0}, 0x0818 = { 6165, 1, 0}, - 0x0819 = { 6166, 1, 0}, 0x081A = { 6167, 1, 0}, 0x081B = { 6168, 1, 0}, 0x081C = { 6169, 1, 0}, 0x081D = { 6170, 1, 0}, 0x081E = { 6171, 1, 0}, 0x081F = { 6172, 1, 0}, 0x0820 = { 6173, 1, 0}, 0x0821 = { 6174, 1, 0}, 0x0822 = { 6175, 1, 0}, 0x0823 = { 6176, 1, 0}, 0x0824 = { 6177, 1, 0}, 0x0825 = { 6178, 1, 0}, 0x0826 = { 6179, 1, 0}, 0x0827 = { 6180, 1, 0}, 0x0828 = { 6181, 1, 0}, - 0x0829 = { 6182, 1, 0}, 0x082A = { 6183, 1, 0}, 0x082B = { 6184, 1, 0}, 0x082C = { 6185, 1, 0}, 0x082D = { 6186, 1, 0}, 0x082E = { 6187, 1, 0}, 0x082F = { 6188, 1, 0}, 0x0830 = { 6189, 1, 0}, 0x0831 = { 6190, 1, 0}, 0x0832 = { 6191, 1, 0}, 0x0833 = { 6192, 1, 0}, 0x0834 = { 6193, 1, 0}, 0x0835 = { 6194, 1, 0}, 0x0836 = { 6195, 1, 0}, 0x0837 = { 6196, 1, 0}, 0x0838 = { 6197, 1, 0}, - 0x0839 = { 6198, 1, 0}, 0x083A = { 6199, 1, 0}, 0x083B = { 6200, 1, 0}, 0x083C = { 6201, 1, 0}, 0x083D = { 6202, 1, 0}, 0x083E = { 6203, 1, 0}, 0x083F = { 6204, 1, 0}, 0x0840 = { 6205, 1, 0}, 0x0841 = { 6206, 1, 0}, 0x0842 = { 6207, 1, 0}, 0x0843 = { 6208, 1, 0}, 0x0844 = { 6209, 1, 0}, 0x0845 = { 6210, 1, 0}, 0x0846 = { 6211, 1, 0}, 0x0847 = { 6212, 1, 0}, 0x0848 = { 6213, 1, 0}, - 0x0849 = { 6214, 1, 0}, 0x084A = { 6215, 1, 0}, 0x084B = { 6216, 1, 0}, 0x084C = { 6217, 1, 0}, 0x084D = { 6218, 1, 0}, 0x084E = { 6219, 1, 0}, 0x084F = { 6220, 1, 0}, 0x0850 = { 6221, 1, 0}, 0x0851 = { 6222, 1, 0}, 0x0852 = { 6223, 1, 0}, 0x0853 = { 6224, 1, 0}, 0x0854 = { 6225, 1, 0}, 0x0855 = { 6226, 1, 0}, 0x0856 = { 6227, 1, 0}, 0x0857 = { 6228, 1, 0}, 0x0858 = { 6229, 1, 0}, - 0x0859 = { 6230, 1, 0}, 0x085A = { 6231, 1, 0}, 0x085B = { 6232, 1, 0}, 0x085C = { 6233, 1, 0}, 0x085D = { 6234, 1, 0}, 0x085E = { 6235, 1, 0}, 0x085F = { 6236, 1, 0}, 0x0860 = { 6237, 1, 0}, 0x0861 = { 6238, 1, 0}, 0x0862 = { 6239, 1, 0}, 0x0863 = { 6240, 1, 0}, 0x0864 = { 6241, 1, 0}, 0x0865 = { 6242, 1, 0}, 0x0866 = { 6243, 1, 0}, 0x0867 = { 6244, 1, 0}, 0x0868 = { 6245, 1, 0}, - 0x0869 = { 6246, 1, 0}, 0x086A = { 6247, 1, 0}, 0x086B = { 6248, 1, 0}, 0x086C = { 6249, 1, 0}, 0x086D = { 6250, 1, 0}, 0x086E = { 6251, 1, 0}, 0x086F = { 6252, 1, 0}, 0x0870 = { 6253, 1, 0}, 0x0871 = { 6254, 1, 0}, 0x0872 = { 6255, 1, 0}, 0x0873 = { 6256, 1, 0}, 0x0874 = { 6257, 1, 0}, 0x0875 = { 6258, 1, 0}, 0x0876 = { 6259, 1, 0}, 0x0877 = { 6260, 1, 0}, 0x0878 = { 6261, 1, 0}, - 0x0879 = { 6262, 1, 0}, 0x087A = { 6263, 1, 0}, 0x087B = { 6264, 1, 0}, 0x087C = { 6265, 1, 0}, 0x087D = { 6266, 1, 0}, 0x087E = { 6267, 1, 0}, 0x087F = { 6268, 1, 0}, 0x0880 = { 6269, 1, 0}, 0x0881 = { 6270, 1, 0}, 0x0882 = { 6271, 1, 0}, 0x0883 = { 6272, 1, 0}, 0x0884 = { 6273, 1, 0}, 0x0885 = { 6274, 1, 0}, 0x0886 = { 6275, 1, 0}, 0x0887 = { 6276, 1, 0}, 0x0888 = { 6277, 1, 0}, - 0x0889 = { 6278, 1, 0}, 0x088A = { 6279, 1, 0}, 0x088B = { 6280, 1, 0}, 0x088C = { 6281, 1, 0}, 0x088D = { 6282, 1, 0}, 0x088E = { 6283, 1, 0}, 0x088F = { 6284, 1, 0}, 0x0890 = { 6285, 1, 0}, 0x0891 = { 6286, 1, 0}, 0x0892 = { 6287, 1, 0}, 0x0893 = { 6288, 1, 0}, 0x0894 = { 6289, 1, 0}, 0x0895 = { 6290, 1, 0}, 0x0896 = { 6291, 1, 0}, 0x0897 = { 6292, 1, 0}, 0x0898 = { 6293, 1, 0}, - 0x0899 = { 6294, 1, 0}, 0x089A = { 6295, 1, 0}, 0x089B = { 6296, 1, 0}, 0x089C = { 6297, 1, 0}, 0x089D = { 6298, 1, 0}, 0x089E = { 6299, 1, 0}, 0x089F = { 6300, 1, 0}, 0x08A0 = { 6301, 1, 0}, 0x08A1 = { 6302, 1, 0}, 0x08A2 = { 6303, 1, 0}, 0x08A3 = { 6304, 1, 0}, 0x08A4 = { 6305, 1, 0}, 0x08A5 = { 6306, 1, 0}, 0x08A6 = { 6307, 1, 0}, 0x08A7 = { 6308, 1, 0}, 0x08A8 = { 6309, 1, 0}, - 0x08A9 = { 6310, 1, 0}, 0x08AA = { 6311, 1, 0}, 0x08AB = { 6312, 1, 0}, 0x08AC = { 6313, 1, 0}, 0x08AD = { 6314, 1, 0}, 0x08AE = { 6315, 1, 0}, 0x08AF = { 6316, 1, 0}, 0x08B0 = { 6317, 1, 0}, 0x08B1 = { 6318, 1, 0}, 0x08B2 = { 6319, 1, 0}, 0x08B3 = { 6320, 1, 0}, 0x08B4 = { 6321, 1, 0}, 0x08B5 = { 6322, 1, 0}, 0x08B6 = { 6323, 1, 0}, 0x08B7 = { 6324, 1, 0}, 0x08B8 = { 6325, 1, 0}, - 0x08B9 = { 6326, 1, 0}, 0x08BA = { 6327, 1, 0}, 0x08BB = { 6328, 1, 0}, 0x08BC = { 6329, 1, 0}, 0x08BD = { 6330, 1, 0}, 0x08BE = { 6331, 1, 0}, 0x08BF = { 6332, 1, 0}, 0x08C0 = { 6333, 1, 0}, 0x08C1 = { 6334, 1, 0}, 0x08C2 = { 6335, 1, 0}, 0x08C3 = { 6336, 1, 0}, 0x08C4 = { 6337, 1, 0}, 0x08C5 = { 6338, 1, 0}, 0x08C6 = { 6339, 1, 0}, 0x08C7 = { 6340, 1, 0}, 0x08C8 = { 6341, 1, 0}, - 0x08C9 = { 6342, 1, 0}, 0x08CA = { 6343, 1, 0}, 0x08CB = { 6344, 1, 0}, 0x08CC = { 6345, 1, 0}, 0x08CD = { 6346, 1, 0}, 0x08CE = { 6347, 1, 0}, 0x08CF = { 6348, 1, 0}, 0x08D0 = { 6349, 1, 0}, 0x08D1 = { 6350, 1, 0}, 0x08D2 = { 6351, 1, 0}, 0x08D3 = { 6352, 1, 0}, 0x08D4 = { 6353, 1, 0}, 0x08D5 = { 6354, 1, 0}, 0x08D6 = { 6355, 1, 0}, 0x08D7 = { 6356, 1, 0}, 0x08D8 = { 6357, 1, 0}, - 0x08D9 = { 6358, 1, 0}, 0x08DA = { 6359, 1, 0}, 0x08DB = { 6360, 1, 0}, 0x08DC = { 6361, 1, 0}, 0x08DD = { 6362, 1, 0}, 0x08DE = { 6363, 1, 0}, 0x08DF = { 6364, 1, 0}, 0x08E0 = { 6365, 1, 0}, 0x08E1 = { 6366, 1, 0}, 0x08E2 = { 6367, 1, 0}, 0x08E3 = { 6368, 1, 0}, 0x08E4 = { 6369, 1, 0}, 0x08E5 = { 6370, 1, 0}, 0x08E6 = { 6371, 1, 0}, 0x08E7 = { 6372, 1, 0}, 0x08E8 = { 6373, 1, 0}, - 0x08E9 = { 6374, 1, 0}, 0x08EA = { 6375, 1, 0}, 0x08EB = { 6376, 1, 0}, 0x08EC = { 6377, 1, 0}, 0x08ED = { 6378, 1, 0}, 0x08EE = { 6379, 1, 0}, 0x08EF = { 6380, 1, 0}, 0x08F0 = { 6381, 1, 0}, 0x08F1 = { 6382, 1, 0}, 0x08F2 = { 6383, 1, 0}, 0x08F3 = { 6384, 1, 0}, 0x08F4 = { 6385, 1, 0}, 0x08F5 = { 6386, 1, 0}, 0x08F6 = { 6387, 1, 0}, 0x08F7 = { 6388, 1, 0}, 0x08F8 = { 6389, 1, 0}, - 0x08F9 = { 6390, 1, 0}, 0x08FA = { 6391, 1, 0}, 0x08FB = { 6392, 1, 0}, 0x08FC = { 6393, 1, 0}, 0x08FD = { 6394, 1, 0}, 0x08FE = { 6395, 1, 0}, 0x08FF = { 6396, 1, 0}, 0x0900 = { 6397, 1, 0}, 0x0A00 = { 6398, 3, 0}, 0x0A01 = { 6401, 3, 0}, 0x0A02 = { 6404, 3, 0}, 0x0A03 = { 6407, 3, 0}, 0x0A04 = { 6410, 3, 0}, 0x0A05 = { 6413, 3, 0}, 0x0A06 = { 6416, 3, 0}, 0x0A07 = { 6419, 3, 0}, - 0x0A08 = { 6422, 3, 0}, 0x0A09 = { 6425, 3, 0}, 0x0A0A = { 6428, 3, 0}, 0x0A0B = { 6431, 3, 0}, 0x0A0C = { 6434, 3, 0}, 0x0A0D = { 6437, 3, 0}, 0x0A0E = { 6440, 3, 0}, 0x0A0F = { 6443, 3, 0}, 0x0A10 = { 6446, 3, 0}, 0x0A11 = { 6449, 3, 0}, 0x0A12 = { 6452, 3, 0}, 0x0A13 = { 6455, 3, 0}, 0x0A14 = { 6458, 3, 0}, 0x0A15 = { 6461, 3, 0}, 0x0A16 = { 6464, 3, 0}, 0x0A17 = { 6467, 3, 0}, - 0x0A18 = { 6470, 3, 0}, 0x0A19 = { 6473, 3, 0}, 0x0A1A = { 6476, 3, 0}, 0x0A1B = { 6479, 3, 0}, 0x0A1C = { 6482, 3, 0}, 0x0A1D = { 6485, 3, 0}, 0x0A1E = { 6488, 3, 0}, 0x0A1F = { 6491, 3, 0}, 0x0A20 = { 6494, 3, 0}, 0x0A21 = { 6497, 3, 0}, 0x0A22 = { 6500, 3, 0}, 0x0A23 = { 6503, 3, 0}, 0x0A24 = { 6506, 3, 0}, 0x0A25 = { 6509, 3, 0}, 0x0A26 = { 6512, 3, 0}, 0x0A27 = { 6515, 3, 0}, - 0x0A28 = { 6518, 3, 0}, 0x0A29 = { 6521, 3, 0}, 0x0A2A = { 6524, 3, 0}, 0x0A2B = { 6527, 3, 0}, 0x0A2C = { 6530, 3, 0}, 0x0A2D = { 6533, 3, 0}, 0x0A2E = { 6536, 3, 0}, 0x0A2F = { 6539, 3, 0}, 0x0A30 = { 6542, 3, 0}, 0x0A31 = { 6545, 3, 0}, 0x0A32 = { 6548, 3, 0}, 0x0A33 = { 6551, 3, 0}, 0x0A34 = { 6554, 3, 0}, 0x0A35 = { 6557, 3, 0}, 0x0A36 = { 6560, 3, 0}, 0x0A37 = { 6563, 3, 0}, - 0x0A38 = { 6566, 3, 0}, 0x0A39 = { 6569, 3, 0}, 0x0A3A = { 6572, 3, 0}, 0x0A3B = { 6575, 3, 0}, 0x0A3C = { 6578, 3, 0}, 0x0A3D = { 6581, 3, 0}, 0x0A3E = { 6584, 3, 0}, 0x0A3F = { 6587, 3, 0}, 0x0A40 = { 6590, 3, 0}, 0x0A41 = { 6593, 3, 0}, 0x0A42 = { 6596, 3, 0}, 0x0A43 = { 6599, 3, 0}, 0x0A44 = { 6602, 3, 0}, 0x0A45 = { 6605, 3, 0}, 0x0A46 = { 6608, 3, 0}, 0x0A47 = { 6611, 3, 0}, - 0x0A48 = { 6614, 3, 0}, 0x0A49 = { 6617, 3, 0}, 0x0A4A = { 6620, 3, 0}, 0x0A4B = { 6623, 3, 0}, 0x0A4C = { 6626, 3, 0}, 0x0A4D = { 6629, 3, 0}, 0x0A4E = { 6632, 3, 0}, 0x0A4F = { 6635, 3, 0}, 0x0A50 = { 6638, 3, 0}, 0x0A51 = { 6641, 3, 0}, 0x0A52 = { 6644, 3, 0}, 0x0A53 = { 6647, 3, 0}, 0x0A54 = { 6650, 3, 0}, 0x0A55 = { 6653, 3, 0}, 0x0A56 = { 6656, 3, 0}, 0x0A57 = { 6659, 3, 0}, - 0x0A58 = { 6662, 3, 0}, 0x0A59 = { 6665, 3, 0}, 0x0A5A = { 6668, 3, 0}, 0x0A5B = { 6671, 3, 0}, 0x0A5C = { 6674, 3, 0}, 0x0A5D = { 6677, 3, 0}, 0x0A5E = { 6680, 3, 0}, 0x0A5F = { 6683, 3, 0}, 0x0A60 = { 6686, 3, 0}, 0x0A61 = { 6689, 3, 0}, 0x0A62 = { 6692, 3, 0}, 0x0A63 = { 6695, 3, 0}, 0x0A64 = { 6698, 3, 0}, 0x0A65 = { 6701, 3, 0}, 0x0A66 = { 6704, 3, 0}, 0x0A67 = { 6707, 3, 0}, - 0x0A68 = { 6710, 3, 0}, 0x0A69 = { 6713, 3, 0}, 0x0A6A = { 6716, 3, 0}, 0x0A6B = { 6719, 3, 0}, 0x0A6C = { 6722, 3, 0}, 0x0A6D = { 6725, 3, 0}, 0x0A6E = { 6728, 3, 0}, 0x0A6F = { 6731, 3, 0}, 0x0A70 = { 6734, 3, 0}, 0x0A71 = { 6737, 3, 0}, 0x0A72 = { 6740, 3, 0}, 0x0A73 = { 6743, 3, 0}, 0x0A74 = { 6746, 3, 0}, 0x0A75 = { 6749, 3, 0}, 0x0A76 = { 6752, 3, 0}, 0x0A77 = { 6755, 3, 0}, - 0x0A78 = { 6758, 3, 0}, 0x0A79 = { 6761, 3, 0}, 0x0A7A = { 6764, 3, 0}, 0x0A7B = { 6767, 3, 0}, 0x0A7C = { 6770, 3, 0}, 0x0A7D = { 6773, 3, 0}, 0x0A7E = { 6776, 3, 0}, 0x0A7F = { 6779, 3, 0}, 0x0A80 = { 6782, 3, 0}, 0x0A81 = { 6785, 3, 0}, 0x0A82 = { 6788, 3, 0}, 0x0A83 = { 6791, 3, 0}, 0x0A84 = { 6794, 3, 0}, 0x0A85 = { 6797, 3, 0}, 0x0A86 = { 6800, 3, 0}, 0x0A87 = { 6803, 3, 0}, - 0x0A88 = { 6806, 3, 0}, 0x0A89 = { 6809, 3, 0}, 0x0A8A = { 6812, 3, 0}, 0x0A8B = { 6815, 3, 0}, 0x0A8C = { 6818, 3, 0}, 0x0A8D = { 6821, 3, 0}, 0x0A8E = { 6824, 3, 0}, 0x0A8F = { 6827, 3, 0}, 0x0A90 = { 6830, 3, 0}, 0x0A91 = { 6833, 3, 0}, 0x0A92 = { 6836, 3, 0}, 0x0A93 = { 6839, 3, 0}, 0x0A94 = { 6842, 3, 0}, 0x0A95 = { 6845, 3, 0}, 0x0A96 = { 6848, 3, 0}, 0x0A97 = { 6851, 3, 0}, - 0x0A98 = { 6854, 3, 0}, 0x0A99 = { 6857, 3, 0}, 0x0A9A = { 6860, 3, 0}, 0x0A9B = { 6863, 3, 0}, 0x0A9C = { 6866, 3, 0}, 0x0A9D = { 6869, 3, 0}, 0x0A9E = { 6872, 3, 0}, 0x0A9F = { 6875, 3, 0}, 0x0AA0 = { 6878, 3, 0}, 0x0AA1 = { 6881, 3, 0}, 0x0AA2 = { 6884, 3, 0}, 0x0AA3 = { 6887, 3, 0}, 0x0AA4 = { 6890, 3, 0}, 0x0AA5 = { 6893, 3, 0}, 0x0AA6 = { 6896, 3, 0}, 0x0AA7 = { 6899, 3, 0}, - 0x0AA8 = { 6902, 3, 0}, 0x0AA9 = { 6905, 3, 0}, 0x0AAA = { 6908, 3, 0}, 0x0AAB = { 6911, 3, 0}, 0x0AAC = { 6914, 3, 0}, 0x0AAD = { 6917, 3, 0}, 0x0AAE = { 6920, 3, 0}, 0x0AAF = { 6923, 3, 0}, 0x0AB0 = { 6926, 3, 0}, 0x0AB1 = { 6929, 3, 0}, 0x0AB2 = { 6932, 3, 0}, 0x0AB3 = { 6935, 3, 0}, 0x0AB4 = { 6938, 3, 0}, 0x0AB5 = { 6941, 3, 0}, 0x0AB6 = { 6944, 3, 0}, 0x0AB7 = { 6947, 3, 0}, - 0x0AB8 = { 6950, 3, 0}, 0x0AB9 = { 6953, 3, 0}, 0x0ABA = { 6956, 3, 0}, 0x0ABB = { 6959, 3, 0}, 0x0ABC = { 6962, 3, 0}, 0x0ABD = { 6965, 3, 0}, 0x0ABE = { 6968, 3, 0}, 0x0ABF = { 6971, 3, 0}, 0x0AC0 = { 6974, 3, 0}, 0x0AC1 = { 6977, 3, 0}, 0x0AC2 = { 6980, 3, 0}, 0x0AC3 = { 6983, 3, 0}, 0x0AC4 = { 6986, 3, 0}, 0x0AC5 = { 6989, 3, 0}, 0x0AC6 = { 6992, 3, 0}, 0x0AC7 = { 6995, 3, 0}, - 0x0AC8 = { 6998, 3, 0}, 0x0AC9 = { 7001, 3, 0}, 0x0ACA = { 7004, 3, 0}, 0x0ACB = { 7007, 3, 0}, 0x0ACC = { 7010, 3, 0}, 0x0ACD = { 7013, 3, 0}, 0x0ACE = { 7016, 3, 0}, 0x0ACF = { 7019, 3, 0}, 0x0AD0 = { 7022, 3, 0}, 0x0AD1 = { 7025, 3, 0}, 0x0AD2 = { 7028, 3, 0}, 0x0AD3 = { 7031, 3, 0}, 0x0AD4 = { 7034, 3, 0}, 0x0AD5 = { 7037, 3, 0}, 0x0AD6 = { 7040, 3, 0}, 0x0AD7 = { 7043, 3, 0}, - 0x0AD8 = { 7046, 3, 0}, 0x0AD9 = { 7049, 3, 0}, 0x0ADA = { 7052, 3, 0}, 0x0ADB = { 7055, 3, 0}, 0x0ADC = { 7058, 3, 0}, 0x0ADD = { 7061, 3, 0}, 0x0ADE = { 7064, 3, 0}, 0x0ADF = { 7067, 3, 0}, 0x0AE0 = { 7070, 3, 0}, 0x0AE1 = { 7073, 3, 0}, 0x0AE2 = { 7076, 3, 0}, 0x0AE3 = { 7079, 3, 0}, 0x0AE4 = { 7082, 3, 0}, 0x0AE5 = { 7085, 3, 0}, 0x0AE6 = { 7088, 3, 0}, 0x0AE7 = { 7091, 3, 0}, - 0x0AE8 = { 7094, 3, 0}, 0x0AE9 = { 7097, 3, 0}, 0x0AEA = { 7100, 3, 0}, 0x0AEB = { 7103, 3, 0}, 0x0AEC = { 7106, 3, 0}, 0x0AED = { 7109, 3, 0}, 0x0AEE = { 7112, 3, 0}, 0x0AEF = { 7115, 3, 0}, 0x0AF0 = { 7118, 3, 0}, 0x0AF1 = { 7121, 3, 0}, 0x0AF2 = { 7124, 3, 0}, 0x0AF3 = { 7127, 3, 0}, 0x0AF4 = { 7130, 3, 0}, 0x0AF5 = { 7133, 3, 0}, 0x0AF6 = { 7136, 3, 0}, 0x0AF7 = { 7139, 3, 0}, - 0x0AF8 = { 7142, 3, 0}, 0x0AF9 = { 7145, 3, 0}, 0x0AFA = { 7148, 3, 0}, 0x0AFB = { 7151, 3, 0}, 0x0AFC = { 7154, 3, 0}, 0x0AFD = { 7157, 3, 0}, 0x0AFE = { 7160, 3, 0}, 0x0AFF = { 7163, 3, 0}, 0x0B00 = { 7166, 3, 0}, 0x0B01 = { 7169, 3, 0}, 0x0B02 = { 7172, 3, 0}, 0x0B03 = { 7175, 3, 0}, 0x0B04 = { 7178, 3, 0}, 0x0B05 = { 7181, 3, 0}, 0x0B06 = { 7184, 3, 0}, 0x0B07 = { 7187, 3, 0}, - 0x0B08 = { 7190, 3, 0}, 0x0B09 = { 7193, 3, 0}, 0x0B0A = { 7196, 3, 0}, 0x0B0B = { 7199, 3, 0}, 0x0B0C = { 7202, 3, 0}, 0x0B0D = { 7205, 3, 0}, 0x0B0E = { 7208, 3, 0}, 0x0B0F = { 7211, 3, 0}, 0x0B10 = { 7214, 3, 0}, 0x0B11 = { 7217, 3, 0}, 0x0B12 = { 7220, 3, 0}, 0x0B13 = { 7223, 3, 0}, 0x0B14 = { 7226, 3, 0}, 0x0B15 = { 7229, 3, 0}, 0x0B16 = { 7232, 3, 0}, 0x0B17 = { 7235, 3, 0}, - 0x0B18 = { 7238, 3, 0}, 0x0B19 = { 7241, 3, 0}, 0x0B1A = { 7244, 3, 0}, 0x0B1B = { 7247, 3, 0}, 0x0B1C = { 7250, 3, 0}, 0x0B1D = { 7253, 3, 0}, 0x0B1E = { 7256, 3, 0}, 0x0B1F = { 7259, 3, 0}, 0x0B20 = { 7262, 3, 0}, 0x0B21 = { 7265, 3, 0}, 0x0B22 = { 7268, 3, 0}, 0x0B23 = { 7271, 3, 0}, 0x0B24 = { 7274, 3, 0}, 0x0B25 = { 7277, 3, 0}, 0x0B26 = { 7280, 3, 0}, 0x0B27 = { 7283, 3, 0}, - 0x0B28 = { 7286, 3, 0}, 0x0B29 = { 7289, 3, 0}, 0x0B2A = { 7292, 3, 0}, 0x0B2B = { 7295, 3, 0}, 0x0B2C = { 7298, 3, 0}, 0x0B2D = { 7301, 3, 0}, 0x0B2E = { 7304, 3, 0}, 0x0B2F = { 7307, 3, 0}, 0x0B30 = { 7310, 3, 0}, 0x0B31 = { 7313, 3, 0}, 0x0B32 = { 7316, 3, 0}, 0x0B33 = { 7319, 3, 0}, 0x0B34 = { 7322, 3, 0}, 0x0B35 = { 7325, 3, 0}, 0x0B36 = { 7328, 3, 0}, 0x0B37 = { 7331, 3, 0}, - 0x0B38 = { 7334, 3, 0}, 0x0B39 = { 7337, 3, 0}, 0x0B3A = { 7340, 3, 0}, 0x0B3B = { 7343, 3, 0}, 0x0B3C = { 7346, 3, 0}, 0x0B3D = { 7349, 3, 0}, 0x0B3E = { 7352, 3, 0}, 0x0B3F = { 7355, 3, 0}, 0x0B40 = { 7358, 3, 0}, 0x0B41 = { 7361, 3, 0}, 0x0B42 = { 7364, 3, 0}, 0x0B43 = { 7367, 3, 0}, 0x0B44 = { 7370, 3, 0}, 0x0B45 = { 7373, 3, 0}, 0x0B46 = { 7376, 3, 0}, 0x0B47 = { 7379, 3, 0}, - 0x0B48 = { 7382, 3, 0}, 0x0B49 = { 7385, 3, 0}, 0x0B4A = { 7388, 3, 0}, 0x0B4B = { 7391, 3, 0}, 0x0B4C = { 7394, 3, 0}, 0x0B4D = { 7397, 3, 0}, 0x0B4E = { 7400, 3, 0}, 0x0B4F = { 7403, 3, 0}, 0x0B50 = { 7406, 3, 0}, 0x0B51 = { 7409, 3, 0}, 0x0B52 = { 7412, 3, 0}, 0x0B53 = { 7415, 3, 0}, 0x0B54 = { 7418, 3, 0}, 0x0B55 = { 7421, 3, 0}, 0x0B56 = { 7424, 3, 0}, 0x0B57 = { 7427, 3, 0}, - 0x0B58 = { 7430, 3, 0}, 0x0B59 = { 7433, 3, 0}, 0x0B5A = { 7436, 3, 0}, 0x0B5B = { 7439, 3, 0}, 0x0B5C = { 7442, 3, 0}, 0x0B5D = { 7445, 3, 0}, 0x0B5E = { 7448, 3, 0}, 0x0B5F = { 7451, 3, 0}, 0x0B60 = { 7454, 3, 0}, 0x0B61 = { 7457, 3, 0}, 0x0B62 = { 7460, 3, 0}, 0x0B63 = { 7463, 3, 0}, 0x0B64 = { 7466, 3, 0}, 0x0B65 = { 7469, 3, 0}, 0x0B66 = { 7472, 3, 0}, 0x0B67 = { 7475, 3, 0}, - 0x0B68 = { 7478, 3, 0}, 0x0B69 = { 7481, 3, 0}, 0x0B6A = { 7484, 3, 0}, 0x0B6B = { 7487, 3, 0}, 0x0B6C = { 7490, 3, 0}, 0x0B6D = { 7493, 3, 0}, 0x0B6E = { 7496, 3, 0}, 0x0B6F = { 7499, 3, 0}, 0x0B70 = { 7502, 3, 0}, 0x0B71 = { 7505, 3, 0}, 0x0B72 = { 7508, 3, 0}, 0x0B73 = { 7511, 3, 0}, 0x0B74 = { 7514, 3, 0}, 0x0B75 = { 7517, 3, 0}, 0x0B76 = { 7520, 3, 0}, 0x0B77 = { 7523, 3, 0}, - 0x0B78 = { 7526, 3, 0}, 0x0B79 = { 7529, 3, 0}, 0x0B7A = { 7532, 3, 0}, 0x0B7B = { 7535, 3, 0}, 0x0B7C = { 7538, 3, 0}, 0x0B7D = { 7541, 3, 0}, 0x0B7E = { 7544, 3, 0}, 0x0B7F = { 7547, 3, 0}, 0x0B80 = { 7550, 3, 0}, 0x0B81 = { 7553, 3, 0}, 0x0B82 = { 7556, 3, 0}, 0x0B83 = { 7559, 3, 0}, 0x0B84 = { 7562, 3, 0}, 0x0B85 = { 7565, 3, 0}, 0x0B86 = { 7568, 3, 0}, 0x0B87 = { 7571, 3, 0}, - 0x0B88 = { 7574, 3, 0}, 0x0B89 = { 7577, 3, 0}, 0x0B8A = { 7580, 3, 0}, 0x0B8B = { 7583, 3, 0}, 0x0B8C = { 7586, 3, 0}, 0x0B8D = { 7589, 3, 0}, 0x0B8E = { 7592, 3, 0}, 0x0B8F = { 7595, 3, 0}, 0x0B90 = { 7598, 3, 0}, 0x0B91 = { 7601, 3, 0}, 0x0B92 = { 7604, 3, 0}, 0x0B93 = { 7607, 3, 0}, 0x0B94 = { 7610, 3, 0}, 0x0B95 = { 7613, 3, 0}, 0x0B96 = { 7616, 3, 0}, 0x0B97 = { 7619, 3, 0}, - 0x0B98 = { 7622, 3, 0}, 0x0B99 = { 7625, 3, 0}, 0x0B9A = { 7628, 3, 0}, 0x0B9B = { 7631, 3, 0}, 0x0B9C = { 7634, 3, 0}, 0x0B9D = { 7637, 3, 0}, 0x0B9E = { 7640, 3, 0}, 0x0B9F = { 7643, 3, 0}, 0x0BA0 = { 7646, 3, 0}, 0x0BA1 = { 7649, 3, 0}, 0x0BA2 = { 7652, 3, 0}, 0x0BA3 = { 7655, 3, 0}, 0x0BA4 = { 7658, 3, 0}, 0x0BA5 = { 7661, 3, 0}, 0x0BA6 = { 7664, 3, 0}, 0x0BA7 = { 7667, 3, 0}, - 0x0BA8 = { 7670, 3, 0}, 0x0BA9 = { 7673, 3, 0}, 0x0BAA = { 7676, 3, 0}, 0x0BAB = { 7679, 3, 0}, 0x0BAC = { 7682, 3, 0}, 0x0BAD = { 7685, 3, 0}, 0x0BAE = { 7688, 3, 0}, 0x0BAF = { 7691, 3, 0}, 0x0BB0 = { 7694, 3, 0}, 0x0BB1 = { 7697, 3, 0}, 0x0BB2 = { 7700, 3, 0}, 0x0BB3 = { 7703, 3, 0}, 0x0BB4 = { 7706, 3, 0}, 0x0BB5 = { 7709, 3, 0}, 0x0BB6 = { 7712, 3, 0}, 0x0BB7 = { 7715, 3, 0}, - 0x0BB8 = { 7718, 3, 0}, 0x0BB9 = { 7721, 3, 0}, 0x0BBA = { 7724, 3, 0}, 0x0BBB = { 7727, 3, 0}, 0x0BBC = { 7730, 3, 0}, 0x0BBD = { 7733, 3, 0}, 0x0BBE = { 7736, 3, 0}, 0x0BBF = { 7739, 3, 0}, 0x0BC0 = { 7742, 3, 0}, 0x0BC1 = { 7745, 3, 0}, 0x0BC2 = { 7748, 3, 0}, 0x0BC3 = { 7751, 3, 0}, 0x0BC4 = { 7754, 3, 0}, 0x0BC5 = { 7757, 3, 0}, 0x0BC6 = { 7760, 3, 0}, 0x0BC7 = { 7763, 3, 0}, - 0x0BC8 = { 7766, 3, 0}, 0x0BC9 = { 7769, 3, 0}, 0x0BCA = { 7772, 3, 0}, 0x0BCB = { 7775, 3, 0}, 0x0BCC = { 7778, 3, 0}, 0x0BCD = { 7781, 3, 0}, 0x0BCE = { 7784, 3, 0}, 0x0BCF = { 7787, 3, 0}, 0x0BD0 = { 7790, 3, 0}, 0x0BD1 = { 7793, 3, 0}, 0x0BD2 = { 7796, 3, 0}, 0x0BD3 = { 7799, 3, 0}, 0x0BD4 = { 7802, 3, 0}, 0x0BD5 = { 7805, 3, 0}, 0x0BD6 = { 7808, 3, 0}, 0x0BD7 = { 7811, 3, 0}, - 0x0BD8 = { 7814, 3, 0}, 0x0BD9 = { 7817, 3, 0}, 0x0BDA = { 7820, 3, 0}, 0x0BDB = { 7823, 3, 0}, 0x0BDC = { 7826, 3, 0}, 0x0BDD = { 7829, 3, 0}, 0x0BDE = { 7832, 3, 0}, 0x0BDF = { 7835, 3, 0}, 0x0BE0 = { 7838, 3, 0}, 0x0BE1 = { 7841, 3, 0}, 0x0BE2 = { 7844, 3, 0}, 0x0BE3 = { 7847, 3, 0}, 0x0BE4 = { 7850, 3, 0}, 0x0BE5 = { 7853, 3, 0}, 0x0BE6 = { 7856, 3, 0}, 0x0BE7 = { 7859, 3, 0}, - 0x0BE8 = { 7862, 3, 0}, 0x0BE9 = { 7865, 3, 0}, 0x0BEA = { 7868, 3, 0}, 0x0BEB = { 7871, 3, 0}, 0x0BEC = { 7874, 3, 0}, 0x0BED = { 7877, 3, 0}, 0x0BEE = { 7880, 3, 0}, 0x0BEF = { 7883, 3, 0}, 0x0BF0 = { 7886, 3, 0}, 0x0BF1 = { 7889, 3, 0}, 0x0BF2 = { 7892, 3, 0}, 0x0BF3 = { 7895, 3, 0}, 0x0BF4 = { 7898, 3, 0}, 0x0BF5 = { 7901, 3, 0}, 0x0BF6 = { 7904, 3, 0}, 0x0BF7 = { 7907, 3, 0}, - 0x0BF8 = { 7910, 3, 0}, 0x0BF9 = { 7913, 3, 0}, 0x0BFA = { 7916, 3, 0}, 0x0BFB = { 7919, 3, 0}, 0x0BFC = { 7922, 3, 0}, 0x0BFD = { 7925, 3, 0}, 0x0BFE = { 7928, 3, 0}, 0x0BFF = { 7931, 3, 0}, 0x0C00 = { 7934, 3, 0}, 0x0C01 = { 7937, 1, 0}, 0x0C02 = { 7938, 1, 0}, 0x0C03 = { 7939, 1, 0}, 0x0C04 = { 7940, 1, 0}, 0x0C05 = { 7941, 1, 0}, 0x0C06 = { 7942, 1, 0}, 0x0C07 = { 7943, 1, 0}, - 0x0C08 = { 7944, 1, 0}, 0x0C09 = { 7945, 1, 0}, 0x0C0A = { 7946, 1, 0}, 0x0C0B = { 7947, 1, 0}, 0x0C0C = { 7948, 1, 0}, 0x0C0D = { 7949, 1, 0}, 0x0C0E = { 7950, 1, 0}, 0x0C0F = { 7951, 1, 0}, 0x0C10 = { 7952, 1, 0}, 0x0C11 = { 7953, 1, 0}, 0x0C12 = { 7954, 1, 0}, 0x0C13 = { 7955, 1, 0}, 0x0C14 = { 7956, 1, 0}, 0x0C15 = { 7957, 1, 0}, 0x0C16 = { 7958, 1, 0}, 0x0C17 = { 7959, 1, 0}, - 0x0C18 = { 7960, 1, 0}, 0x0C19 = { 7961, 1, 0}, 0x0C1A = { 7962, 1, 0}, 0x0C1B = { 7963, 1, 0}, 0x0C1C = { 7964, 1, 0}, 0x0C1D = { 7965, 1, 0}, 0x0C1E = { 7966, 1, 0}, 0x0C1F = { 7967, 1, 0}, 0x0C20 = { 7968, 1, 0}, 0x0C21 = { 7969, 1, 0}, 0x0C22 = { 7970, 1, 0}, 0x0C23 = { 7971, 1, 0}, 0x0C24 = { 7972, 1, 0}, 0x0C25 = { 7973, 1, 0}, 0x0C26 = { 7974, 1, 0}, 0x0C27 = { 7975, 1, 0}, - 0x0C28 = { 7976, 1, 0}, 0x0C29 = { 7977, 1, 0}, 0x0C2A = { 7978, 1, 0}, 0x0C2B = { 7979, 1, 0}, 0x0C2C = { 7980, 1, 0}, 0x0C2D = { 7981, 1, 0}, 0x0C2E = { 7982, 1, 0}, 0x0C2F = { 7983, 1, 0}, 0x0C30 = { 7984, 1, 0}, 0x0C31 = { 7985, 1, 0}, 0x0C32 = { 7986, 1, 0}, 0x0C33 = { 7987, 1, 0}, 0x0C34 = { 7988, 1, 0}, 0x0C35 = { 7989, 1, 0}, 0x0C36 = { 7990, 1, 0}, 0x0C37 = { 7991, 1, 0}, - 0x0C38 = { 7992, 1, 0}, 0x0C39 = { 7993, 1, 0}, 0x0C3A = { 7994, 1, 0}, 0x0C3B = { 7995, 1, 0}, 0x0C3C = { 7996, 1, 0}, 0x0C3D = { 7997, 1, 0}, 0x0C3E = { 7998, 1, 0}, 0x0C3F = { 7999, 1, 0}, 0x0C40 = { 8000, 1, 0}, 0x0C41 = { 8001, 1, 0}, 0x0C42 = { 8002, 1, 0}, 0x0C43 = { 8003, 1, 0}, 0x0C44 = { 8004, 1, 0}, 0x0C45 = { 8005, 1, 0}, 0x0C46 = { 8006, 1, 0}, 0x0C47 = { 8007, 1, 0}, - 0x0C48 = { 8008, 1, 0}, 0x0C49 = { 8009, 1, 0}, 0x0C4A = { 8010, 1, 0}, 0x0C4B = { 8011, 1, 0}, 0x0C4C = { 8012, 1, 0}, 0x0C4D = { 8013, 1, 0}, 0x0C4E = { 8014, 1, 0}, 0x0C4F = { 8015, 1, 0}, 0x0C50 = { 8016, 1, 0}, 0x0C51 = { 8017, 1, 0}, 0x0C52 = { 8018, 1, 0}, 0x0C53 = { 8019, 1, 0}, 0x0C54 = { 8020, 1, 0}, 0x0C55 = { 8021, 1, 0}, 0x0C56 = { 8022, 1, 0}, 0x0C57 = { 8023, 1, 0}, - 0x0C58 = { 8024, 1, 0}, 0x0C59 = { 8025, 1, 0}, 0x0C5A = { 8026, 1, 0}, 0x0C5B = { 8027, 1, 0}, 0x0C5C = { 8028, 1, 0}, 0x0C5D = { 8029, 1, 0}, 0x0C5E = { 8030, 1, 0}, 0x0C5F = { 8031, 1, 0}, 0x0C60 = { 8032, 1, 0}, 0x0C61 = { 8033, 1, 0}, 0x0C62 = { 8034, 1, 0}, 0x0C63 = { 8035, 1, 0}, 0x0C64 = { 8036, 1, 0}, 0x0C65 = { 8037, 1, 0}, 0x0C66 = { 8038, 1, 0}, 0x0C67 = { 8039, 1, 0}, - 0x0C68 = { 8040, 1, 0}, 0x0C69 = { 8041, 1, 0}, 0x0C6A = { 8042, 1, 0}, 0x0C6B = { 8043, 1, 0}, 0x0C6C = { 8044, 1, 0}, 0x0C6D = { 8045, 1, 0}, 0x0C6E = { 8046, 1, 0}, 0x0C6F = { 8047, 1, 0}, 0x0C70 = { 8048, 1, 0}, 0x0C71 = { 8049, 1, 0}, 0x0C72 = { 8050, 1, 0}, 0x0C73 = { 8051, 1, 0}, 0x0C74 = { 8052, 1, 0}, 0x0C75 = { 8053, 1, 0}, 0x0C76 = { 8054, 1, 0}, 0x0C77 = { 8055, 1, 0}, - 0x0C78 = { 8056, 1, 0}, 0x0C79 = { 8057, 1, 0}, 0x0C7A = { 8058, 1, 0}, 0x0C7B = { 8059, 1, 0}, 0x0C7C = { 8060, 1, 0}, 0x0C7D = { 8061, 1, 0}, 0x0C7E = { 8062, 1, 0}, 0x0C7F = { 8063, 1, 0}, 0x0C80 = { 8064, 1, 0}, 0x0C81 = { 8065, 1, 0}, 0x0C82 = { 8066, 1, 0}, 0x0C83 = { 8067, 1, 0}, 0x0C84 = { 8068, 1, 0}, 0x0C85 = { 8069, 1, 0}, 0x0C86 = { 8070, 1, 0}, 0x0C87 = { 8071, 1, 0}, - 0x0C88 = { 8072, 1, 0}, 0x0C89 = { 8073, 1, 0}, 0x0C8A = { 8074, 1, 0}, 0x0C8B = { 8075, 1, 0}, 0x0C8C = { 8076, 1, 0}, 0x0C8D = { 8077, 1, 0}, 0x0C8E = { 8078, 1, 0}, 0x0C8F = { 8079, 1, 0}, 0x0C90 = { 8080, 1, 0}, 0x0C91 = { 8081, 1, 0}, 0x0C92 = { 8082, 1, 0}, 0x0C93 = { 8083, 1, 0}, 0x0C94 = { 8084, 1, 0}, 0x0C95 = { 8085, 1, 0}, 0x0C96 = { 8086, 1, 0}, 0x0C97 = { 8087, 1, 0}, - 0x0C98 = { 8088, 1, 0}, 0x0C99 = { 8089, 1, 0}, 0x0C9A = { 8090, 1, 0}, 0x0C9B = { 8091, 1, 0}, 0x0C9C = { 8092, 1, 0}, 0x0C9D = { 8093, 1, 0}, 0x0C9E = { 8094, 1, 0}, 0x0C9F = { 8095, 1, 0}, 0x0CA0 = { 8096, 1, 0}, 0x0CA1 = { 8097, 1, 0}, 0x0CA2 = { 8098, 1, 0}, 0x0CA3 = { 8099, 1, 0}, 0x0CA4 = { 8100, 1, 0}, 0x0CA5 = { 8101, 1, 0}, 0x0CA6 = { 8102, 1, 0}, 0x0CA7 = { 8103, 1, 0}, - 0x0CA8 = { 8104, 1, 0}, 0x0CA9 = { 8105, 1, 0}, 0x0CAA = { 8106, 1, 0}, 0x0CAB = { 8107, 1, 0}, 0x0CAC = { 8108, 1, 0}, 0x0CAD = { 8109, 1, 0}, 0x0CAE = { 8110, 1, 0}, 0x0CAF = { 8111, 1, 0}, 0x0CB0 = { 8112, 1, 0}, 0x0CB1 = { 8113, 1, 0}, 0x0CB2 = { 8114, 1, 0}, 0x0CB3 = { 8115, 1, 0}, 0x0CB4 = { 8116, 1, 0}, 0x0CB5 = { 8117, 1, 0}, 0x0CB6 = { 8118, 1, 0}, 0x0CB7 = { 8119, 1, 0}, - 0x0CB8 = { 8120, 1, 0}, 0x0CB9 = { 8121, 1, 0}, 0x0CBA = { 8122, 1, 0}, 0x0CBB = { 8123, 1, 0}, 0x0CBC = { 8124, 1, 0}, 0x0CBD = { 8125, 1, 0}, 0x0CBE = { 8126, 1, 0}, 0x0CBF = { 8127, 1, 0}, 0x0CC0 = { 8128, 1, 0}, 0x0CC1 = { 8129, 1, 0}, 0x0CC2 = { 8130, 1, 0}, 0x0CC3 = { 8131, 1, 0}, 0x0CC4 = { 8132, 1, 0}, 0x0CC5 = { 8133, 1, 0}, 0x0CC6 = { 8134, 1, 0}, 0x0CC7 = { 8135, 1, 0}, - 0x0CC8 = { 8136, 1, 0}, 0x0CC9 = { 8137, 1, 0}, 0x0CCA = { 8138, 1, 0}, 0x0CCB = { 8139, 1, 0}, 0x0CCC = { 8140, 1, 0}, 0x0CCD = { 8141, 1, 0}, 0x0CCE = { 8142, 1, 0}, 0x0CCF = { 8143, 1, 0}, 0x0CD0 = { 8144, 1, 0}, 0x0CD1 = { 8145, 1, 0}, 0x0CD2 = { 8146, 1, 0}, 0x0CD3 = { 8147, 1, 0}, 0x0CD4 = { 8148, 1, 0}, 0x0CD5 = { 8149, 1, 0}, 0x0CD6 = { 8150, 1, 0}, 0x0CD7 = { 8151, 1, 0}, - 0x0CD8 = { 8152, 1, 0}, 0x0CD9 = { 8153, 1, 0}, 0x0CDA = { 8154, 1, 0}, 0x0CDB = { 8155, 1, 0}, 0x0CDC = { 8156, 1, 0}, 0x0CDD = { 8157, 1, 0}, 0x0CDE = { 8158, 1, 0}, 0x0CDF = { 8159, 1, 0}, 0x0CE0 = { 8160, 1, 0}, 0x0CE1 = { 8161, 1, 0}, 0x0CE2 = { 8162, 1, 0}, 0x0CE3 = { 8163, 1, 0}, 0x0CE4 = { 8164, 1, 0}, 0x0CE5 = { 8165, 1, 0}, 0x0CE6 = { 8166, 1, 0}, 0x0CE7 = { 8167, 1, 0}, - 0x0CE8 = { 8168, 1, 0}, 0x0CE9 = { 8169, 1, 0}, 0x0CEA = { 8170, 1, 0}, 0x0CEB = { 8171, 1, 0}, 0x0CEC = { 8172, 1, 0}, 0x0CED = { 8173, 1, 0}, 0x0CEE = { 8174, 1, 0}, 0x0CEF = { 8175, 1, 0}, 0x0CF0 = { 8176, 1, 0}, 0x0CF1 = { 8177, 1, 0}, 0x0CF2 = { 8178, 1, 0}, 0x0CF3 = { 8179, 1, 0}, 0x0CF4 = { 8180, 1, 0}, 0x0CF5 = { 8181, 1, 0}, 0x0CF6 = { 8182, 1, 0}, 0x0CF7 = { 8183, 1, 0}, - 0x0CF8 = { 8184, 1, 0}, 0x0CF9 = { 8185, 1, 0}, 0x0CFA = { 8186, 1, 0}, 0x0CFB = { 8187, 1, 0}, 0x0CFC = { 8188, 1, 0}, 0x0CFD = { 8189, 1, 0}, 0x0CFE = { 8190, 1, 0}, 0x0CFF = { 8191, 1, 0}, 0x0D00 = { 8192, 3, 0}, 0x0D01 = { 8195, 1, 0}, 0x0D02 = { 8196, 1, 0}, 0x0D03 = { 8197, 1, 0}, 0x0D04 = { 8198, 1, 0}, 0x0D05 = { 8199, 1, 0}, 0x0D06 = { 8200, 1, 0}, 0x0D07 = { 8201, 1, 0}, - 0x0D08 = { 8202, 1, 0}, 0x0D09 = { 8203, 1, 0}, 0x0D0A = { 8204, 1, 0}, 0x0D0B = { 8205, 1, 0}, 0x0D0C = { 8206, 1, 0}, 0x0D0D = { 8207, 1, 0}, 0x0D0E = { 8208, 1, 0}, 0x0D0F = { 8209, 1, 0}, 0x0D10 = { 8210, 1, 0}, 0x0D11 = { 8211, 1, 0}, 0x0D12 = { 8212, 1, 0}, 0x0D13 = { 8213, 1, 0}, 0x0D14 = { 8214, 1, 0}, 0x0D15 = { 8215, 1, 0}, 0x0D16 = { 8216, 1, 0}, 0x0D17 = { 8217, 1, 0}, - 0x0D18 = { 8218, 1, 0}, 0x0D19 = { 8219, 1, 0}, 0x0D1A = { 8220, 1, 0}, 0x0D1B = { 8221, 1, 0}, 0x0D1C = { 8222, 1, 0}, 0x0D1D = { 8223, 1, 0}, 0x0D1E = { 8224, 1, 0}, 0x0D1F = { 8225, 1, 0}, 0x0D20 = { 8226, 1, 0}, 0x0D21 = { 8227, 1, 0}, 0x0D22 = { 8228, 1, 0}, 0x0D23 = { 8229, 1, 0}, 0x0D24 = { 8230, 1, 0}, 0x0D25 = { 8231, 1, 0}, 0x0D26 = { 8232, 1, 0}, 0x0D27 = { 8233, 1, 0}, - 0x0D28 = { 8234, 1, 0}, 0x0D29 = { 8235, 1, 0}, 0x0D2A = { 8236, 1, 0}, 0x0D2B = { 8237, 1, 0}, 0x0D2C = { 8238, 1, 0}, 0x0D2D = { 8239, 1, 0}, 0x0D2E = { 8240, 1, 0}, 0x0D2F = { 8241, 1, 0}, 0x0D30 = { 8242, 1, 0}, 0x0D31 = { 8243, 1, 0}, 0x0D32 = { 8244, 1, 0}, 0x0D33 = { 8245, 1, 0}, 0x0D34 = { 8246, 1, 0}, 0x0D35 = { 8247, 1, 0}, 0x0D36 = { 8248, 1, 0}, 0x0D37 = { 8249, 1, 0}, - 0x0D38 = { 8250, 1, 0}, 0x0D39 = { 8251, 1, 0}, 0x0D3A = { 8252, 1, 0}, 0x0D3B = { 8253, 1, 0}, 0x0D3C = { 8254, 1, 0}, 0x0D3D = { 8255, 1, 0}, 0x0D3E = { 8256, 1, 0}, 0x0D3F = { 8257, 1, 0}, 0x0D40 = { 8258, 1, 0}, 0x0D41 = { 8259, 1, 0}, 0x0D42 = { 8260, 1, 0}, 0x0D43 = { 8261, 1, 0}, 0x0D44 = { 8262, 1, 0}, 0x0D45 = { 8263, 1, 0}, 0x0D46 = { 8264, 1, 0}, 0x0D47 = { 8265, 1, 0}, - 0x0D48 = { 8266, 1, 0}, 0x0D49 = { 8267, 1, 0}, 0x0D4A = { 8268, 1, 0}, 0x0D4B = { 8269, 1, 0}, 0x0D4C = { 8270, 1, 0}, 0x0D4D = { 8271, 1, 0}, 0x0D4E = { 8272, 1, 0}, 0x0D4F = { 8273, 1, 0}, 0x0D50 = { 8274, 1, 0}, 0x0D51 = { 8275, 1, 0}, 0x0D52 = { 8276, 1, 0}, 0x0D53 = { 8277, 1, 0}, 0x0D54 = { 8278, 1, 0}, 0x0D55 = { 8279, 1, 0}, 0x0D56 = { 8280, 1, 0}, 0x0D57 = { 8281, 1, 0}, - 0x0D58 = { 8282, 1, 0}, 0x0D59 = { 8283, 1, 0}, 0x0D5A = { 8284, 1, 0}, 0x0D5B = { 8285, 1, 0}, 0x0D5C = { 8286, 1, 0}, 0x0D5D = { 8287, 1, 0}, 0x0D5E = { 8288, 1, 0}, 0x0D5F = { 8289, 1, 0}, 0x0D60 = { 8290, 1, 0}, 0x0D61 = { 8291, 1, 0}, 0x0D62 = { 8292, 1, 0}, 0x0D63 = { 8293, 1, 0}, 0x0D64 = { 8294, 1, 0}, 0x0D65 = { 8295, 1, 0}, 0x0D66 = { 8296, 1, 0}, 0x0D67 = { 8297, 1, 0}, - 0x0D68 = { 8298, 1, 0}, 0x0D69 = { 8299, 1, 0}, 0x0D6A = { 8300, 1, 0}, 0x0D6B = { 8301, 1, 0}, 0x0D6C = { 8302, 1, 0}, 0x0D6D = { 8303, 1, 0}, 0x0D6E = { 8304, 1, 0}, 0x0D6F = { 8305, 1, 0}, 0x0D70 = { 8306, 1, 0}, 0x0D71 = { 8307, 1, 0}, 0x0D72 = { 8308, 1, 0}, 0x0D73 = { 8309, 1, 0}, 0x0D74 = { 8310, 1, 0}, 0x0D75 = { 8311, 1, 0}, 0x0D76 = { 8312, 1, 0}, 0x0D77 = { 8313, 1, 0}, - 0x0D78 = { 8314, 1, 0}, 0x0D79 = { 8315, 1, 0}, 0x0D7A = { 8316, 1, 0}, 0x0D7B = { 8317, 1, 0}, 0x0D7C = { 8318, 1, 0}, 0x0D7D = { 8319, 1, 0}, 0x0D7E = { 8320, 1, 0}, 0x0D7F = { 8321, 1, 0}, 0x0D80 = { 8322, 1, 0}, 0x0D81 = { 8323, 1, 0}, 0x0D82 = { 8324, 1, 0}, 0x0D83 = { 8325, 1, 0}, 0x0D84 = { 8326, 1, 0}, 0x0D85 = { 8327, 1, 0}, 0x0D86 = { 8328, 1, 0}, 0x0D87 = { 8329, 1, 0}, - 0x0D88 = { 8330, 1, 0}, 0x0D89 = { 8331, 1, 0}, 0x0D8A = { 8332, 1, 0}, 0x0D8B = { 8333, 1, 0}, 0x0D8C = { 8334, 1, 0}, 0x0D8D = { 8335, 1, 0}, 0x0D8E = { 8336, 1, 0}, 0x0D8F = { 8337, 1, 0}, 0x0D90 = { 8338, 1, 0}, 0x0D91 = { 8339, 1, 0}, 0x0D92 = { 8340, 1, 0}, 0x0D93 = { 8341, 1, 0}, 0x0D94 = { 8342, 1, 0}, 0x0D95 = { 8343, 1, 0}, 0x0D96 = { 8344, 1, 0}, 0x0D97 = { 8345, 1, 0}, - 0x0D98 = { 8346, 1, 0}, 0x0D99 = { 8347, 1, 0}, 0x0D9A = { 8348, 1, 0}, 0x0D9B = { 8349, 1, 0}, 0x0D9C = { 8350, 1, 0}, 0x0D9D = { 8351, 1, 0}, 0x0D9E = { 8352, 1, 0}, 0x0D9F = { 8353, 1, 0}, 0x0DA0 = { 8354, 1, 0}, 0x0DA1 = { 8355, 1, 0}, 0x0DA2 = { 8356, 1, 0}, 0x0DA3 = { 8357, 1, 0}, 0x0DA4 = { 8358, 1, 0}, 0x0DA5 = { 8359, 1, 0}, 0x0DA6 = { 8360, 1, 0}, 0x0DA7 = { 8361, 1, 0}, - 0x0DA8 = { 8362, 1, 0}, 0x0DA9 = { 8363, 1, 0}, 0x0DAA = { 8364, 1, 0}, 0x0DAB = { 8365, 1, 0}, 0x0DAC = { 8366, 1, 0}, 0x0DAD = { 8367, 1, 0}, 0x0DAE = { 8368, 1, 0}, 0x0DAF = { 8369, 1, 0}, 0x0DB0 = { 8370, 1, 0}, 0x0DB1 = { 8371, 1, 0}, 0x0DB2 = { 8372, 1, 0}, 0x0DB3 = { 8373, 1, 0}, 0x0DB4 = { 8374, 1, 0}, 0x0DB5 = { 8375, 1, 0}, 0x0DB6 = { 8376, 1, 0}, 0x0DB7 = { 8377, 1, 0}, - 0x0DB8 = { 8378, 1, 0}, 0x0DB9 = { 8379, 1, 0}, 0x0DBA = { 8380, 1, 0}, 0x0DBB = { 8381, 1, 0}, 0x0DBC = { 8382, 1, 0}, 0x0DBD = { 8383, 1, 0}, 0x0DBE = { 8384, 1, 0}, 0x0DBF = { 8385, 1, 0}, 0x0DC0 = { 8386, 1, 0}, 0x0DC1 = { 8387, 1, 0}, 0x0DC2 = { 8388, 1, 0}, 0x0DC3 = { 8389, 1, 0}, 0x0DC4 = { 8390, 1, 0}, 0x0DC5 = { 8391, 1, 0}, 0x0DC6 = { 8392, 1, 0}, 0x0DC7 = { 8393, 1, 0}, - 0x0DC8 = { 8394, 1, 0}, 0x0DC9 = { 8395, 1, 0}, 0x0DCA = { 8396, 1, 0}, 0x0DCB = { 8397, 1, 0}, 0x0DCC = { 8398, 1, 0}, 0x0DCD = { 8399, 1, 0}, 0x0DCE = { 8400, 1, 0}, 0x0DCF = { 8401, 1, 0}, 0x0DD0 = { 8402, 1, 0}, 0x0DD1 = { 8403, 1, 0}, 0x0DD2 = { 8404, 1, 0}, 0x0DD3 = { 8405, 1, 0}, 0x0DD4 = { 8406, 1, 0}, 0x0DD5 = { 8407, 1, 0}, 0x0DD6 = { 8408, 1, 0}, 0x0DD7 = { 8409, 1, 0}, - 0x0DD8 = { 8410, 1, 0}, 0x0DD9 = { 8411, 1, 0}, 0x0DDA = { 8412, 1, 0}, 0x0DDB = { 8413, 1, 0}, 0x0DDC = { 8414, 1, 0}, 0x0DDD = { 8415, 1, 0}, 0x0DDE = { 8416, 1, 0}, 0x0DDF = { 8417, 1, 0}, 0x0DE0 = { 8418, 1, 0}, 0x0DE1 = { 8419, 1, 0}, 0x0DE2 = { 8420, 1, 0}, 0x0DE3 = { 8421, 1, 0}, 0x0DE4 = { 8422, 1, 0}, 0x0DE5 = { 8423, 1, 0}, 0x0DE6 = { 8424, 1, 0}, 0x0DE7 = { 8425, 1, 0}, - 0x0DE8 = { 8426, 1, 0}, 0x0DE9 = { 8427, 1, 0}, 0x0DEA = { 8428, 1, 0}, 0x0DEB = { 8429, 1, 0}, 0x0DEC = { 8430, 1, 0}, 0x0DED = { 8431, 1, 0}, 0x0DEE = { 8432, 1, 0}, 0x0DEF = { 8433, 1, 0}, 0x0DF0 = { 8434, 1, 0}, 0x0DF1 = { 8435, 1, 0}, 0x0DF2 = { 8436, 1, 0}, 0x0DF3 = { 8437, 1, 0}, 0x0DF4 = { 8438, 1, 0}, 0x0DF5 = { 8439, 1, 0}, 0x0DF6 = { 8440, 1, 0}, 0x0DF7 = { 8441, 1, 0}, - 0x0DF8 = { 8442, 1, 0}, 0x0DF9 = { 8443, 1, 0}, 0x0DFA = { 8444, 1, 0}, 0x0DFB = { 8445, 1, 0}, 0x0DFC = { 8446, 1, 0}, 0x0DFD = { 8447, 1, 0}, 0x0DFE = { 8448, 1, 0}, 0x0DFF = { 8449, 1, 0}, 0x0E00 = { 8450, 8, 0}, 0x0E01 = { 8458, 5, 0}, 0x0E02 = { 8463, 5, 0}, 0x0E03 = { 8468, 5, 0}, 0x0E04 = { 8473, 5, 0}, 0x0E05 = { 8478, 5, 0}, 0x0E06 = { 8483, 5, 0}, 0x0E07 = { 8488, 5, 0}, - 0x0E08 = { 8493, 5, 0}, 0x0E09 = { 8498, 5, 0}, 0x0E0A = { 8503, 5, 0}, 0x0E0B = { 8508, 5, 0}, 0x0E0C = { 8513, 5, 0}, 0x0E0D = { 8518, 5, 0}, 0x0E0E = { 8523, 5, 0}, 0x0E0F = { 8528, 5, 0}, 0x0E10 = { 8533, 5, 0}, 0x0E11 = { 8538, 5, 0}, 0x0E12 = { 8543, 5, 0}, 0x0E13 = { 8548, 5, 0}, 0x0E14 = { 8553, 5, 0}, 0x0E15 = { 8558, 5, 0}, 0x0E16 = { 8563, 5, 0}, 0x0E17 = { 8568, 5, 0}, - 0x0E18 = { 8573, 5, 0}, 0x0E19 = { 8578, 5, 0}, 0x0E1A = { 8583, 5, 0}, 0x0E1B = { 8588, 5, 0}, 0x0E1C = { 8593, 5, 0}, 0x0E1D = { 8598, 5, 0}, 0x0E1E = { 8603, 5, 0}, 0x0E1F = { 8608, 5, 0}, 0x0E20 = { 8613, 5, 0}, 0x0E21 = { 8618, 5, 0}, 0x0E22 = { 8623, 5, 0}, 0x0E23 = { 8628, 5, 0}, 0x0E24 = { 8633, 5, 0}, 0x0E25 = { 8638, 5, 0}, 0x0E26 = { 8643, 5, 0}, 0x0E27 = { 8648, 5, 0}, - 0x0E28 = { 8653, 5, 0}, 0x0E29 = { 8658, 5, 0}, 0x0E2A = { 8663, 5, 0}, 0x0E2B = { 8668, 5, 0}, 0x0E2C = { 8673, 5, 0}, 0x0E2D = { 8678, 5, 0}, 0x0E2E = { 8683, 5, 0}, 0x0E2F = { 8688, 5, 0}, 0x0E30 = { 8693, 5, 0}, 0x0E31 = { 8698, 5, 0}, 0x0E32 = { 8703, 5, 0}, 0x0E33 = { 8708, 5, 0}, 0x0E34 = { 8713, 5, 0}, 0x0E35 = { 8718, 5, 0}, 0x0E36 = { 8723, 5, 0}, 0x0E37 = { 8728, 5, 0}, - 0x0E38 = { 8733, 5, 0}, 0x0E39 = { 8738, 5, 0}, 0x0E3A = { 8743, 5, 0}, 0x0E3B = { 8748, 5, 0}, 0x0E3C = { 8753, 5, 0}, 0x0E3D = { 8758, 5, 0}, 0x0E3E = { 8763, 5, 0}, 0x0E3F = { 8768, 5, 0}, 0x0E40 = { 8773, 5, 0}, 0x0E41 = { 8778, 5, 0}, 0x0E42 = { 8783, 5, 0}, 0x0E43 = { 8788, 5, 0}, 0x0E44 = { 8793, 5, 0}, 0x0E45 = { 8798, 5, 0}, 0x0E46 = { 8803, 5, 0}, 0x0E47 = { 8808, 5, 0}, - 0x0E48 = { 8813, 5, 0}, 0x0E49 = { 8818, 5, 0}, 0x0E4A = { 8823, 5, 0}, 0x0E4B = { 8828, 5, 0}, 0x0E4C = { 8833, 5, 0}, 0x0E4D = { 8838, 5, 0}, 0x0E4E = { 8843, 5, 0}, 0x0E4F = { 8848, 5, 0}, 0x0E50 = { 8853, 5, 0}, 0x0E51 = { 8858, 5, 0}, 0x0E52 = { 8863, 5, 0}, 0x0E53 = { 8868, 5, 0}, 0x0E54 = { 8873, 5, 0}, 0x0E55 = { 8878, 5, 0}, 0x0E56 = { 8883, 5, 0}, 0x0E57 = { 8888, 5, 0}, - 0x0E58 = { 8893, 5, 0}, 0x0E59 = { 8898, 5, 0}, 0x0E5A = { 8903, 5, 0}, 0x0E5B = { 8908, 5, 0}, 0x0E5C = { 8913, 5, 0}, 0x0E5D = { 8918, 5, 0}, 0x0E5E = { 8923, 5, 0}, 0x0E5F = { 8928, 5, 0}, 0x0E60 = { 8933, 5, 0}, 0x0E61 = { 8938, 5, 0}, 0x0E62 = { 8943, 5, 0}, 0x0E63 = { 8948, 5, 0}, 0x0E64 = { 8953, 5, 0}, 0x0E65 = { 8958, 5, 0}, 0x0E66 = { 8963, 5, 0}, 0x0E67 = { 8968, 5, 0}, - 0x0E68 = { 8973, 5, 0}, 0x0E69 = { 8978, 5, 0}, 0x0E6A = { 8983, 5, 0}, 0x0E6B = { 8988, 5, 0}, 0x0E6C = { 8993, 5, 0}, 0x0E6D = { 8998, 5, 0}, 0x0E6E = { 9003, 5, 0}, 0x0E6F = { 9008, 5, 0}, 0x0E70 = { 9013, 5, 0}, 0x0E71 = { 9018, 5, 0}, 0x0E72 = { 9023, 5, 0}, 0x0E73 = { 9028, 5, 0}, 0x0E74 = { 9033, 5, 0}, 0x0E75 = { 9038, 5, 0}, 0x0E76 = { 9043, 5, 0}, 0x0E77 = { 9048, 5, 0}, - 0x0E78 = { 9053, 5, 0}, 0x0E79 = { 9058, 5, 0}, 0x0E7A = { 9063, 5, 0}, 0x0E7B = { 9068, 5, 0}, 0x0E7C = { 9073, 5, 0}, 0x0E7D = { 9078, 5, 0}, 0x0E7E = { 9083, 5, 0}, 0x0E7F = { 9088, 5, 0}, 0x0E80 = { 9093, 5, 0}, 0x0E81 = { 9098, 5, 0}, 0x0E82 = { 9103, 5, 0}, 0x0E83 = { 9108, 5, 0}, 0x0E84 = { 9113, 5, 0}, 0x0E85 = { 9118, 5, 0}, 0x0E86 = { 9123, 5, 0}, 0x0E87 = { 9128, 5, 0}, - 0x0E88 = { 9133, 5, 0}, 0x0E89 = { 9138, 5, 0}, 0x0E8A = { 9143, 5, 0}, 0x0E8B = { 9148, 5, 0}, 0x0E8C = { 9153, 5, 0}, 0x0E8D = { 9158, 5, 0}, 0x0E8E = { 9163, 5, 0}, 0x0E8F = { 9168, 5, 0}, 0x0E90 = { 9173, 5, 0}, 0x0E91 = { 9178, 5, 0}, 0x0E92 = { 9183, 5, 0}, 0x0E93 = { 9188, 5, 0}, 0x0E94 = { 9193, 5, 0}, 0x0E95 = { 9198, 5, 0}, 0x0E96 = { 9203, 5, 0}, 0x0E97 = { 9208, 5, 0}, - 0x0E98 = { 9213, 5, 0}, 0x0E99 = { 9218, 5, 0}, 0x0E9A = { 9223, 5, 0}, 0x0E9B = { 9228, 5, 0}, 0x0E9C = { 9233, 5, 0}, 0x0E9D = { 9238, 5, 0}, 0x0E9E = { 9243, 5, 0}, 0x0E9F = { 9248, 5, 0}, 0x0EA0 = { 9253, 5, 0}, 0x0EA1 = { 9258, 5, 0}, 0x0EA2 = { 9263, 5, 0}, 0x0EA3 = { 9268, 5, 0}, 0x0EA4 = { 9273, 5, 0}, 0x0EA5 = { 9278, 5, 0}, 0x0EA6 = { 9283, 5, 0}, 0x0EA7 = { 9288, 5, 0}, - 0x0EA8 = { 9293, 5, 0}, 0x0EA9 = { 9298, 5, 0}, 0x0EAA = { 9303, 5, 0}, 0x0EAB = { 9308, 5, 0}, 0x0EAC = { 9313, 5, 0}, 0x0EAD = { 9318, 5, 0}, 0x0EAE = { 9323, 5, 0}, 0x0EAF = { 9328, 5, 0}, 0x0EB0 = { 9333, 5, 0}, 0x0EB1 = { 9338, 5, 0}, 0x0EB2 = { 9343, 5, 0}, 0x0EB3 = { 9348, 5, 0}, 0x0EB4 = { 9353, 5, 0}, 0x0EB5 = { 9358, 5, 0}, 0x0EB6 = { 9363, 5, 0}, 0x0EB7 = { 9368, 5, 0}, - 0x0EB8 = { 9373, 5, 0}, 0x0EB9 = { 9378, 5, 0}, 0x0EBA = { 9383, 5, 0}, 0x0EBB = { 9388, 5, 0}, 0x0EBC = { 9393, 5, 0}, 0x0EBD = { 9398, 5, 0}, 0x0EBE = { 9403, 5, 0}, 0x0EBF = { 9408, 5, 0}, 0x0EC0 = { 9413, 5, 0}, 0x0EC1 = { 9418, 5, 0}, 0x0EC2 = { 9423, 5, 0}, 0x0EC3 = { 9428, 5, 0}, 0x0EC4 = { 9433, 5, 0}, 0x0EC5 = { 9438, 5, 0}, 0x0EC6 = { 9443, 5, 0}, 0x0EC7 = { 9448, 5, 0}, - 0x0EC8 = { 9453, 5, 0}, 0x0EC9 = { 9458, 5, 0}, 0x0ECA = { 9463, 5, 0}, 0x0ECB = { 9468, 5, 0}, 0x0ECC = { 9473, 5, 0}, 0x0ECD = { 9478, 5, 0}, 0x0ECE = { 9483, 6, 0}, 0x0ECF = { 9489, 5, 0}, 0x0ED0 = { 9494, 5, 0}, 0x0ED1 = { 9499, 5, 0}, 0x0ED2 = { 9504, 5, 0}, 0x0ED3 = { 9509, 5, 0}, 0x0ED4 = { 9514, 5, 0}, 0x0ED5 = { 9519, 5, 0}, 0x0ED6 = { 9524, 5, 0}, 0x0ED7 = { 9529, 5, 0}, - 0x0ED8 = { 9534, 5, 0}, 0x0ED9 = { 9539, 5, 0}, 0x0EDA = { 9544, 5, 0}, 0x0EDB = { 9549, 5, 0}, 0x0EDC = { 9554, 5, 0}, 0x0EDD = { 9559, 5, 0}, 0x0EDE = { 9564, 5, 0}, 0x0EDF = { 9569, 5, 0}, 0x0EE0 = { 9574, 5, 0}, 0x0EE1 = { 9579, 5, 0}, 0x0EE2 = { 9584, 5, 0}, 0x0EE3 = { 9589, 5, 0}, 0x0EE4 = { 9594, 5, 0}, 0x0EE5 = { 9599, 5, 0}, 0x0EE6 = { 9604, 5, 0}, 0x0EE7 = { 9609, 5, 0}, - 0x0EE8 = { 9614, 5, 0}, 0x0EE9 = { 9619, 5, 0}, 0x0EEA = { 9624, 5, 0}, 0x0EEB = { 9629, 5, 0}, 0x0EEC = { 9634, 5, 0}, 0x0EED = { 9639, 5, 0}, 0x0EEE = { 9644, 5, 0}, 0x0EEF = { 9649, 5, 0}, 0x0EF0 = { 9654, 5, 0}, 0x0EF1 = { 9659, 5, 0}, 0x0EF2 = { 9664, 5, 0}, 0x0EF3 = { 9669, 5, 0}, 0x0EF4 = { 9674, 5, 0}, 0x0EF5 = { 9679, 5, 0}, 0x0EF6 = { 9684, 5, 0}, 0x0EF7 = { 9689, 5, 0}, - 0x0EF8 = { 9694, 5, 0}, 0x0EF9 = { 9699, 5, 0}, 0x0EFA = { 9704, 5, 0}, 0x0EFB = { 9709, 5, 0}, 0x0EFC = { 9714, 5, 0}, 0x0EFD = { 9719, 5, 0}, 0x0EFE = { 9724, 5, 0}, 0x0EFF = { 9729, 5, 0}, 0x0F00 = { 9734, 5, 0}, 0x0F01 = { 9739, 2, 0}, 0x0F02 = { 9741, 2, 0}, 0x0F03 = { 9743, 2, 0}, 0x0F04 = { 9745, 2, 0}, 0x0F05 = { 9747, 2, 0}, 0x0F06 = { 9749, 2, 0}, 0x0F07 = { 9751, 2, 0}, - 0x0F08 = { 9753, 2, 0}, 0x0F09 = { 9755, 2, 0}, 0x0F0A = { 9757, 2, 0}, 0x0F0B = { 9759, 2, 0}, 0x0F0C = { 9761, 2, 0}, 0x0F0D = { 9763, 2, 0}, 0x0F0E = { 9765, 2, 0}, 0x0F0F = { 9767, 2, 0}, 0x0F10 = { 9769, 2, 0}, 0x0F11 = { 9771, 2, 0}, 0x0F12 = { 9773, 2, 0}, 0x0F13 = { 9775, 2, 0}, 0x0F14 = { 9777, 2, 0}, 0x0F15 = { 9779, 2, 0}, 0x0F16 = { 9781, 2, 0}, 0x0F17 = { 9783, 2, 0}, - 0x0F18 = { 9785, 2, 0}, 0x0F19 = { 9787, 2, 0}, 0x0F1A = { 9789, 2, 0}, 0x0F1B = { 9791, 2, 0}, 0x0F1C = { 9793, 2, 0}, 0x0F1D = { 9795, 2, 0}, 0x0F1E = { 9797, 2, 0}, 0x0F1F = { 9799, 2, 0}, 0x0F20 = { 9801, 2, 0}, 0x0F21 = { 9803, 2, 0}, 0x0F22 = { 9805, 2, 0}, 0x0F23 = { 9807, 2, 0}, 0x0F24 = { 9809, 2, 0}, 0x0F25 = { 9811, 2, 0}, 0x0F26 = { 9813, 2, 0}, 0x0F27 = { 9815, 2, 0}, - 0x0F28 = { 9817, 2, 0}, 0x0F29 = { 9819, 2, 0}, 0x0F2A = { 9821, 2, 0}, 0x0F2B = { 9823, 2, 0}, 0x0F2C = { 9825, 2, 0}, 0x0F2D = { 9827, 2, 0}, 0x0F2E = { 9829, 2, 0}, 0x0F2F = { 9831, 2, 0}, 0x0F30 = { 9833, 2, 0}, 0x0F31 = { 9835, 2, 0}, 0x0F32 = { 9837, 2, 0}, 0x0F33 = { 9839, 2, 0}, 0x0F34 = { 9841, 2, 0}, 0x0F35 = { 9843, 2, 0}, 0x0F36 = { 9845, 2, 0}, 0x0F37 = { 9847, 2, 0}, - 0x0F38 = { 9849, 2, 0}, 0x0F39 = { 9851, 2, 0}, 0x0F3A = { 9853, 2, 0}, 0x0F3B = { 9855, 2, 0}, 0x0F3C = { 9857, 2, 0}, 0x0F3D = { 9859, 2, 0}, 0x0F3E = { 9861, 2, 0}, 0x0F3F = { 9863, 2, 0}, 0x0F40 = { 9865, 2, 0}, 0x0F41 = { 9867, 2, 0}, 0x0F42 = { 9869, 2, 0}, 0x0F43 = { 9871, 2, 0}, 0x0F44 = { 9873, 2, 0}, 0x0F45 = { 9875, 2, 0}, 0x0F46 = { 9877, 2, 0}, 0x0F47 = { 9879, 2, 0}, - 0x0F48 = { 9881, 2, 0}, 0x0F49 = { 9883, 2, 0}, 0x0F4A = { 9885, 2, 0}, 0x0F4B = { 9887, 2, 0}, 0x0F4C = { 9889, 2, 0}, 0x0F4D = { 9891, 2, 0}, 0x0F4E = { 9893, 2, 0}, 0x0F4F = { 9895, 2, 0}, 0x0F50 = { 9897, 2, 0}, 0x0F51 = { 9899, 2, 0}, 0x0F52 = { 9901, 2, 0}, 0x0F53 = { 9903, 2, 0}, 0x0F54 = { 9905, 2, 0}, 0x0F55 = { 9907, 2, 0}, 0x0F56 = { 9909, 2, 0}, 0x0F57 = { 9911, 2, 0}, - 0x0F58 = { 9913, 2, 0}, 0x0F59 = { 9915, 2, 0}, 0x0F5A = { 9917, 2, 0}, 0x0F5B = { 9919, 2, 0}, 0x0F5C = { 9921, 2, 0}, 0x0F5D = { 9923, 2, 0}, 0x0F5E = { 9925, 2, 0}, 0x0F5F = { 9927, 2, 0}, 0x0F60 = { 9929, 2, 0}, 0x0F61 = { 9931, 2, 0}, 0x0F62 = { 9933, 2, 0}, 0x0F63 = { 9935, 2, 0}, 0x0F64 = { 9937, 2, 0}, 0x0F65 = { 9939, 2, 0}, 0x0F66 = { 9941, 2, 0}, 0x0F67 = { 9943, 2, 0}, - 0x0F68 = { 9945, 2, 0}, 0x0F69 = { 9947, 2, 0}, 0x0F6A = { 9949, 2, 0}, 0x0F6B = { 9951, 2, 0}, 0x0F6C = { 9953, 2, 0}, 0x0F6D = { 9955, 2, 0}, 0x0F6E = { 9957, 2, 0}, 0x0F6F = { 9959, 2, 0}, 0x0F70 = { 9961, 2, 0}, 0x0F71 = { 9963, 2, 0}, 0x0F72 = { 9965, 2, 0}, 0x0F73 = { 9967, 2, 0}, 0x0F74 = { 9969, 2, 0}, 0x0F75 = { 9971, 2, 0}, 0x0F76 = { 9973, 2, 0}, 0x0F77 = { 9975, 2, 0}, - 0x0F78 = { 9977, 2, 0}, 0x0F79 = { 9979, 2, 0}, 0x0F7A = { 9981, 2, 0}, 0x0F7B = { 9983, 2, 0}, 0x0F7C = { 9985, 2, 0}, 0x0F7D = { 9987, 2, 0}, 0x0F7E = { 9989, 2, 0}, 0x0F7F = { 9991, 2, 0}, 0x0F80 = { 9993, 2, 0}, 0x0F81 = { 9995, 2, 0}, 0x0F82 = { 9997, 2, 0}, 0x0F83 = { 9999, 2, 0}, 0x0F84 = {10001, 2, 0}, 0x0F85 = {10003, 2, 0}, 0x0F86 = {10005, 2, 0}, 0x0F87 = {10007, 2, 0}, - 0x0F88 = {10009, 2, 0}, 0x0F89 = {10011, 2, 0}, 0x0F8A = {10013, 2, 0}, 0x0F8B = {10015, 2, 0}, 0x0F8C = {10017, 2, 0}, 0x0F8D = {10019, 2, 0}, 0x0F8E = {10021, 2, 0}, 0x0F8F = {10023, 2, 0}, 0x0F90 = {10025, 2, 0}, 0x0F91 = {10027, 2, 0}, 0x0F92 = {10029, 2, 0}, 0x0F93 = {10031, 2, 0}, 0x0F94 = {10033, 2, 0}, 0x0F95 = {10035, 2, 0}, 0x0F96 = {10037, 2, 0}, 0x0F97 = {10039, 2, 0}, - 0x0F98 = {10041, 2, 0}, 0x0F99 = {10043, 2, 0}, 0x0F9A = {10045, 2, 0}, 0x0F9B = {10047, 2, 0}, 0x0F9C = {10049, 2, 0}, 0x0F9D = {10051, 2, 0}, 0x0F9E = {10053, 2, 0}, 0x0F9F = {10055, 2, 0}, 0x0FA0 = {10057, 2, 0}, 0x0FA1 = {10059, 2, 0}, 0x0FA2 = {10061, 2, 0}, 0x0FA3 = {10063, 2, 0}, 0x0FA4 = {10065, 2, 0}, 0x0FA5 = {10067, 2, 0}, 0x0FA6 = {10069, 2, 0}, 0x0FA7 = {10071, 2, 0}, - 0x0FA8 = {10073, 2, 0}, 0x0FA9 = {10075, 2, 0}, 0x0FAA = {10077, 2, 0}, 0x0FAB = {10079, 2, 0}, 0x0FAC = {10081, 2, 0}, 0x0FAD = {10083, 2, 0}, 0x0FAE = {10085, 2, 0}, 0x0FAF = {10087, 2, 0}, 0x0FB0 = {10089, 2, 0}, 0x0FB1 = {10091, 2, 0}, 0x0FB2 = {10093, 2, 0}, 0x0FB3 = {10095, 2, 0}, 0x0FB4 = {10097, 2, 0}, 0x0FB5 = {10099, 2, 0}, 0x0FB6 = {10101, 2, 0}, 0x0FB7 = {10103, 2, 0}, - 0x0FB8 = {10105, 2, 0}, 0x0FB9 = {10107, 2, 0}, 0x0FBA = {10109, 2, 0}, 0x0FBB = {10111, 2, 0}, 0x0FBC = {10113, 2, 0}, 0x0FBD = {10115, 2, 0}, 0x0FBE = {10117, 2, 0}, 0x0FBF = {10119, 2, 0}, 0x0FC0 = {10121, 2, 0}, 0x0FC1 = {10123, 2, 0}, 0x0FC2 = {10125, 2, 0}, 0x0FC3 = {10127, 2, 0}, 0x0FC4 = {10129, 2, 0}, 0x0FC5 = {10131, 2, 0}, 0x0FC6 = {10133, 2, 0}, 0x0FC7 = {10135, 2, 0}, - 0x0FC8 = {10137, 2, 0}, 0x0FC9 = {10139, 2, 0}, 0x0FCA = {10141, 2, 0}, 0x0FCB = {10143, 2, 0}, 0x0FCC = {10145, 2, 0}, 0x0FCD = {10147, 2, 0}, 0x0FCE = {10149, 2, 0}, 0x0FCF = {10151, 2, 0}, 0x0FD0 = {10153, 2, 0}, 0x0FD1 = {10155, 2, 0}, 0x0FD2 = {10157, 2, 0}, 0x0FD3 = {10159, 2, 0}, 0x0FD4 = {10161, 2, 0}, 0x0FD5 = {10163, 2, 0}, 0x0FD6 = {10165, 2, 0}, 0x0FD7 = {10167, 2, 0}, - 0x0FD8 = {10169, 2, 0}, 0x0FD9 = {10171, 2, 0}, 0x0FDA = {10173, 2, 0}, 0x0FDB = {10175, 2, 0}, 0x0FDC = {10177, 2, 0}, 0x0FDD = {10179, 2, 0}, 0x0FDE = {10181, 2, 0}, 0x0FDF = {10183, 2, 0}, 0x0FE0 = {10185, 2, 0}, 0x0FE1 = {10187, 2, 0}, 0x0FE2 = {10189, 2, 0}, 0x0FE3 = {10191, 2, 0}, 0x0FE4 = {10193, 2, 0}, 0x0FE5 = {10195, 2, 0}, 0x0FE6 = {10197, 2, 0}, 0x0FE7 = {10199, 2, 0}, - 0x0FE8 = {10201, 2, 0}, 0x0FE9 = {10203, 2, 0}, 0x0FEA = {10205, 2, 0}, 0x0FEB = {10207, 2, 0}, 0x0FEC = {10209, 2, 0}, 0x0FED = {10211, 2, 0}, 0x0FEE = {10213, 2, 0}, 0x0FEF = {10215, 2, 0}, 0x0FF0 = {10217, 2, 0}, 0x0FF1 = {10219, 2, 0}, 0x0FF2 = {10221, 2, 0}, 0x0FF3 = {10223, 2, 0}, 0x0FF4 = {10225, 2, 0}, 0x0FF5 = {10227, 2, 0}, 0x0FF6 = {10229, 2, 0}, 0x0FF7 = {10231, 2, 0}, - 0x0FF8 = {10233, 2, 0}, 0x0FF9 = {10235, 2, 0}, 0x0FFA = {10237, 2, 0}, 0x0FFB = {10239, 2, 0}, 0x0FFC = {10241, 2, 0}, 0x0FFD = {10243, 2, 0}, 0x0FFE = {10245, 2, 0}, 0x0FFF = {10247, 2, 0}, 0x1000 = {10249, 30, 0}, 0x1001 = {10279, 2, 0}, 0x1002 = {10281, 30, 0}, 0x1003 = {10311, 2, 0}, 0x1004 = {10313, 30, 0}, 0x1005 = {10343, 2, 0}, 0x1006 = {10345, 30, 0}, 0x1007 = {10375, 2, 0}, - 0x1008 = {10377, 30, 0}, 0x1009 = {10407, 2, 0}, 0x100A = {10409, 30, 0}, 0x100B = {10439, 2, 0}, 0x100C = {10441, 30, 0}, 0x100D = {10471, 2, 0}, 0x100E = {10473, 30, 0}, 0x100F = {10503, 2, 0}, 0x1010 = {10505, 30, 0}, 0x1011 = {10535, 2, 0}, 0x1012 = {10537, 30, 0}, 0x1013 = {10567, 2, 0}, 0x1014 = {10569, 30, 0}, 0x1015 = {10599, 2, 0}, 0x1016 = {10601, 30, 0}, 0x1017 = {10631, 2, 0}, - 0x1018 = {10633, 30, 0}, 0x1019 = {10663, 2, 0}, 0x101A = {10665, 30, 0}, 0x101B = {10695, 2, 0}, 0x101C = {10697, 30, 0}, 0x101D = {10727, 2, 0}, 0x101E = {10729, 30, 0}, 0x101F = {10759, 2, 0}, 0x1020 = {10761, 30, 0}, 0x1021 = {10791, 2, 0}, 0x1022 = {10793, 30, 0}, 0x1023 = {10823, 2, 0}, 0x1024 = {10825, 30, 0}, 0x1025 = {10855, 2, 0}, 0x1026 = {10857, 30, 0}, 0x1027 = {10887, 2, 0}, - 0x1028 = {10889, 30, 0}, 0x1029 = {10919, 2, 0}, 0x102A = {10921, 30, 0}, 0x102B = {10951, 2, 0}, 0x102C = {10953, 30, 0}, 0x102D = {10983, 2, 0}, 0x102E = {10985, 30, 0}, 0x102F = {11015, 2, 0}, 0x1030 = {11017, 30, 0}, 0x1031 = {11047, 2, 0}, 0x1032 = {11049, 30, 0}, 0x1033 = {11079, 2, 0}, 0x1034 = {11081, 30, 0}, 0x1035 = {11111, 2, 0}, 0x1036 = {11113, 30, 0}, 0x1037 = {11143, 2, 0}, - 0x1038 = {11145, 30, 0}, 0x1039 = {11175, 2, 0}, 0x103A = {11177, 30, 0}, 0x103B = {11207, 2, 0}, 0x103C = {11209, 30, 0}, 0x103D = {11239, 2, 0}, 0x103E = {11241, 30, 0}, 0x103F = {11271, 2, 0}, 0x1040 = {11273, 30, 0}, 0x1041 = {11303, 2, 0}, 0x1042 = {11305, 30, 0}, 0x1043 = {11335, 2, 0}, 0x1044 = {11337, 30, 0}, 0x1045 = {11367, 2, 0}, 0x1046 = {11369, 30, 0}, 0x1047 = {11399, 2, 0}, - 0x1048 = {11401, 30, 0}, 0x1049 = {11431, 2, 0}, 0x104A = {11433, 30, 0}, 0x104B = {11463, 2, 0}, 0x104C = {11465, 30, 0}, 0x104D = {11495, 2, 0}, 0x104E = {11497, 30, 0}, 0x104F = {11527, 2, 0}, 0x1050 = {11529, 30, 0}, 0x1051 = {11559, 2, 0}, 0x1052 = {11561, 30, 0}, 0x1053 = {11591, 2, 0}, 0x1054 = {11593, 30, 0}, 0x1055 = {11623, 2, 0}, 0x1056 = {11625, 30, 0}, 0x1057 = {11655, 2, 0}, - 0x1058 = {11657, 30, 0}, 0x1059 = {11687, 2, 0}, 0x105A = {11689, 30, 0}, 0x105B = {11719, 2, 0}, 0x105C = {11721, 30, 0}, 0x105D = {11751, 2, 0}, 0x105E = {11753, 30, 0}, 0x105F = {11783, 2, 0}, 0x1060 = {11785, 30, 0}, 0x1061 = {11815, 2, 0}, 0x1062 = {11817, 30, 0}, 0x1063 = {11847, 2, 0}, 0x1064 = {11849, 30, 0}, 0x1065 = {11879, 2, 0}, 0x1066 = {11881, 30, 0}, 0x1067 = {11911, 2, 0}, - 0x1068 = {11913, 30, 0}, 0x1069 = {11943, 2, 0}, 0x106A = {11945, 30, 0}, 0x106B = {11975, 2, 0}, 0x106C = {11977, 30, 0}, 0x106D = {12007, 2, 0}, 0x106E = {12009, 30, 0}, 0x106F = {12039, 2, 0}, 0x1070 = {12041, 30, 0}, 0x1071 = {12071, 2, 0}, 0x1072 = {12073, 30, 0}, 0x1073 = {12103, 2, 0}, 0x1074 = {12105, 30, 0}, 0x1075 = {12135, 2, 0}, 0x1076 = {12137, 30, 0}, 0x1077 = {12167, 2, 0}, - 0x1078 = {12169, 30, 0}, 0x1079 = {12199, 2, 0}, 0x107A = {12201, 30, 0}, 0x107B = {12231, 2, 0}, 0x107C = {12233, 30, 0}, 0x107D = {12263, 2, 0}, 0x107E = {12265, 30, 0}, 0x107F = {12295, 2, 0}, 0x1080 = {12297, 30, 0}, 0x1081 = {12327, 2, 0}, 0x1082 = {12329, 30, 0}, 0x1083 = {12359, 2, 0}, 0x1084 = {12361, 30, 0}, 0x1085 = {12391, 2, 0}, 0x1086 = {12393, 30, 0}, 0x1087 = {12423, 2, 0}, - 0x1088 = {12425, 30, 0}, 0x1089 = {12455, 2, 0}, 0x108A = {12457, 30, 0}, 0x108B = {12487, 2, 0}, 0x108C = {12489, 30, 0}, 0x108D = {12519, 2, 0}, 0x108E = {12521, 30, 0}, 0x108F = {12551, 2, 0}, 0x1090 = {12553, 30, 0}, 0x1091 = {12583, 2, 0}, 0x1092 = {12585, 30, 0}, 0x1093 = {12615, 2, 0}, 0x1094 = {12617, 30, 0}, 0x1095 = {12647, 2, 0}, 0x1096 = {12649, 30, 0}, 0x1097 = {12679, 2, 0}, - 0x1098 = {12681, 30, 0}, 0x1099 = {12711, 2, 0}, 0x109A = {12713, 30, 0}, 0x109B = {12743, 2, 0}, 0x109C = {12745, 30, 0}, 0x109D = {12775, 2, 0}, 0x109E = {12777, 30, 0}, 0x109F = {12807, 2, 0}, 0x10A0 = {12809, 30, 0}, 0x10A1 = {12839, 2, 0}, 0x10A2 = {12841, 30, 0}, 0x10A3 = {12871, 2, 0}, 0x10A4 = {12873, 30, 0}, 0x10A5 = {12903, 2, 0}, 0x10A6 = {12905, 30, 0}, 0x10A7 = {12935, 2, 0}, - 0x10A8 = {12937, 30, 0}, 0x10A9 = {12967, 2, 0}, 0x10AA = {12969, 30, 0}, 0x10AB = {12999, 2, 0}, 0x10AC = {13001, 30, 0}, 0x10AD = {13031, 2, 0}, 0x10AE = {13033, 30, 0}, 0x10AF = {13063, 2, 0}, 0x10B0 = {13065, 30, 0}, 0x10B1 = {13095, 2, 0}, 0x10B2 = {13097, 30, 0}, 0x10B3 = {13127, 2, 0}, 0x10B4 = {13129, 30, 0}, 0x10B5 = {13159, 2, 0}, 0x10B6 = {13161, 30, 0}, 0x10B7 = {13191, 2, 0}, - 0x10B8 = {13193, 30, 0}, 0x10B9 = {13223, 2, 0}, 0x10BA = {13225, 30, 0}, 0x10BB = {13255, 2, 0}, 0x10BC = {13257, 30, 0}, 0x10BD = {13287, 2, 0}, 0x10BE = {13289, 30, 0}, 0x10BF = {13319, 2, 0}, 0x10C0 = {13321, 30, 0}, 0x10C1 = {13351, 2, 0}, 0x10C2 = {13353, 30, 0}, 0x10C3 = {13383, 2, 0}, 0x10C4 = {13385, 30, 0}, 0x10C5 = {13415, 2, 0}, 0x10C6 = {13417, 30, 0}, 0x10C7 = {13447, 2, 0}, - 0x10C8 = {13449, 30, 0}, 0x10C9 = {13479, 2, 0}, 0x10CA = {13481, 30, 0}, 0x10CB = {13511, 2, 0}, 0x10CC = {13513, 30, 0}, 0x10CD = {13543, 2, 0}, 0x10CE = {13545, 30, 0}, 0x10CF = {13575, 2, 0}, 0x10D0 = {13577, 30, 0}, 0x10D1 = {13607, 2, 0}, 0x10D2 = {13609, 30, 0}, 0x10D3 = {13639, 2, 0}, 0x10D4 = {13641, 30, 0}, 0x10D5 = {13671, 2, 0}, 0x10D6 = {13673, 30, 0}, 0x10D7 = {13703, 2, 0}, - 0x10D8 = {13705, 30, 0}, 0x10D9 = {13735, 2, 0}, 0x10DA = {13737, 30, 0}, 0x10DB = {13767, 2, 0}, 0x10DC = {13769, 30, 0}, 0x10DD = {13799, 2, 0}, 0x10DE = {13801, 30, 0}, 0x10DF = {13831, 2, 0}, 0x10E0 = {13833, 30, 0}, 0x10E1 = {13863, 2, 0}, 0x10E2 = {13865, 30, 0}, 0x10E3 = {13895, 2, 0}, 0x10E4 = {13897, 30, 0}, 0x10E5 = {13927, 2, 0}, 0x10E6 = {13929, 30, 0}, 0x10E7 = {13959, 2, 0}, - 0x10E8 = {13961, 30, 0}, 0x10E9 = {13991, 2, 0}, 0x10EA = {13993, 30, 0}, 0x10EB = {14023, 2, 0}, 0x10EC = {14025, 30, 0}, 0x10ED = {14055, 2, 0}, 0x10EE = {14057, 30, 0}, 0x10EF = {14087, 2, 0}, 0x10F0 = {14089, 30, 0}, 0x10F1 = {14119, 2, 0}, 0x10F2 = {14121, 30, 0}, 0x10F3 = {14151, 2, 0}, 0x10F4 = {14153, 30, 0}, 0x10F5 = {14183, 2, 0}, 0x10F6 = {14185, 30, 0}, 0x10F7 = {14215, 2, 0}, - 0x10F8 = {14217, 30, 0}, 0x10F9 = {14247, 2, 0}, 0x10FA = {14249, 30, 0}, 0x10FB = {14279, 2, 0}, 0x10FC = {14281, 30, 0}, 0x10FD = {14311, 2, 0}, 0x10FE = {14313, 30, 0}, 0x10FF = {14343, 2, 0}, 0x1100 = {14345, 1, 0}, 0x1101 = {14346, 1, 0}, 0x1110 = {14347, 2, 0}, 0x1111 = {14349, 1, 0}, 0x1200 = {14350, 2, 0}, 0x1201 = {14352, 2, 0}, 0x1202 = {14354, 2, 0}, 0x1203 = {14356, 2, 0}, - 0x1204 = {14358, 2, 0}, 0x1205 = {14360, 2, 0}, 0x1206 = {14362, 2, 0}, 0x1207 = {14364, 2, 0}, 0x1208 = {14366, 2, 0}, 0x1209 = {14368, 2, 0}, 0x120A = {14370, 2, 0}, 0x120B = {14372, 2, 0}, 0x120C = {14374, 2, 0}, 0x120D = {14376, 2, 0}, 0x120E = {14378, 2, 0}, 0x120F = {14380, 2, 0}, 0x1210 = {14382, 2, 0}, 0x1211 = {14384, 2, 0}, 0x1212 = {14386, 2, 0}, 0x1213 = {14388, 2, 0}, - 0x1214 = {14390, 2, 0}, 0x1215 = {14392, 2, 0}, 0x1216 = {14394, 2, 0}, 0x1217 = {14396, 2, 0}, 0x1218 = {14398, 2, 0}, 0x1219 = {14400, 2, 0}, 0x121A = {14402, 2, 0}, 0x121B = {14404, 2, 0}, 0x121C = {14406, 2, 0}, 0x121D = {14408, 2, 0}, 0x121E = {14410, 2, 0}, 0x121F = {14412, 2, 0}, 0x1220 = {14414, 2, 0}, 0x1221 = {14416, 2, 0}, 0x1222 = {14418, 2, 0}, 0x1223 = {14420, 2, 0}, - 0x1224 = {14422, 2, 0}, 0x1225 = {14424, 2, 0}, 0x1226 = {14426, 2, 0}, 0x1227 = {14428, 2, 0}, 0x1228 = {14430, 2, 0}, 0x1229 = {14432, 2, 0}, 0x122A = {14434, 2, 0}, 0x122B = {14436, 2, 0}, 0x122C = {14438, 2, 0}, 0x122D = {14440, 2, 0}, 0x122E = {14442, 2, 0}, 0x122F = {14444, 2, 0}, 0x1230 = {14446, 2, 0}, 0x1231 = {14448, 2, 0}, 0x1232 = {14450, 2, 0}, 0x1233 = {14452, 2, 0}, - 0x1234 = {14454, 2, 0}, 0x1235 = {14456, 2, 0}, 0x1236 = {14458, 2, 0}, 0x1237 = {14460, 2, 0}, 0x1238 = {14462, 2, 0}, 0x1239 = {14464, 2, 0}, 0x123A = {14466, 2, 0}, 0x123B = {14468, 2, 0}, 0x123C = {14470, 2, 0}, 0x123D = {14472, 2, 0}, 0x123E = {14474, 2, 0}, 0x123F = {14476, 2, 0}, 0x1240 = {14478, 2, 0}, 0x1241 = {14480, 2, 0}, 0x1242 = {14482, 2, 0}, 0x1243 = {14484, 2, 0}, - 0x1244 = {14486, 2, 0}, 0x1245 = {14488, 2, 0}, 0x1246 = {14490, 2, 0}, 0x1247 = {14492, 2, 0}, 0x1248 = {14494, 2, 0}, 0x1249 = {14496, 2, 0}, 0x124A = {14498, 2, 0}, 0x124B = {14500, 2, 0}, 0x124C = {14502, 2, 0}, 0x124D = {14504, 2, 0}, 0x124E = {14506, 2, 0}, 0x124F = {14508, 2, 0}, 0x1250 = {14510, 2, 0}, 0x1251 = {14512, 2, 0}, 0x1252 = {14514, 2, 0}, 0x1253 = {14516, 2, 0}, - 0x1254 = {14518, 2, 0}, 0x1255 = {14520, 2, 0}, 0x1256 = {14522, 2, 0}, 0x1257 = {14524, 2, 0}, 0x1258 = {14526, 2, 0}, 0x1259 = {14528, 2, 0}, 0x125A = {14530, 2, 0}, 0x125B = {14532, 2, 0}, 0x125C = {14534, 2, 0}, 0x125D = {14536, 2, 0}, 0x125E = {14538, 2, 0}, 0x125F = {14540, 2, 0}, 0x1260 = {14542, 2, 0}, 0x1261 = {14544, 2, 0}, 0x1262 = {14546, 2, 0}, 0x1263 = {14548, 2, 0}, - 0x1264 = {14550, 2, 0}, 0x1265 = {14552, 2, 0}, 0x1266 = {14554, 2, 0}, 0x1267 = {14556, 2, 0}, 0x1268 = {14558, 2, 0}, 0x1269 = {14560, 2, 0}, 0x126A = {14562, 2, 0}, 0x126B = {14564, 2, 0}, 0x126C = {14566, 2, 0}, 0x126D = {14568, 2, 0}, 0x126E = {14570, 2, 0}, 0x126F = {14572, 2, 0}, 0x1270 = {14574, 2, 0}, 0x1271 = {14576, 2, 0}, 0x1272 = {14578, 2, 0}, 0x1273 = {14580, 2, 0}, - 0x1274 = {14582, 2, 0}, 0x1275 = {14584, 2, 0}, 0x1276 = {14586, 2, 0}, 0x1277 = {14588, 2, 0}, 0x1278 = {14590, 2, 0}, 0x1279 = {14592, 2, 0}, 0x127A = {14594, 2, 0}, 0x127B = {14596, 2, 0}, 0x127C = {14598, 2, 0}, 0x127D = {14600, 2, 0}, 0x127E = {14602, 2, 0}, 0x127F = {14604, 2, 0}, 0x1280 = {14606, 2, 0}, 0x1281 = {14608, 2, 0}, 0x1282 = {14610, 2, 0}, 0x1283 = {14612, 2, 0}, - 0x1284 = {14614, 2, 0}, 0x1285 = {14616, 2, 0}, 0x1286 = {14618, 2, 0}, 0x1287 = {14620, 2, 0}, 0x1288 = {14622, 2, 0}, 0x1289 = {14624, 2, 0}, 0x128A = {14626, 2, 0}, 0x128B = {14628, 2, 0}, 0x128C = {14630, 2, 0}, 0x128D = {14632, 2, 0}, 0x128E = {14634, 2, 0}, 0x128F = {14636, 2, 0}, 0x1290 = {14638, 2, 0}, 0x1291 = {14640, 2, 0}, 0x1292 = {14642, 2, 0}, 0x1293 = {14644, 2, 0}, - 0x1294 = {14646, 2, 0}, 0x1295 = {14648, 2, 0}, 0x1296 = {14650, 2, 0}, 0x1297 = {14652, 2, 0}, 0x1298 = {14654, 2, 0}, 0x1299 = {14656, 2, 0}, 0x129A = {14658, 2, 0}, 0x129B = {14660, 2, 0}, 0x129C = {14662, 2, 0}, 0x129D = {14664, 2, 0}, 0x129E = {14666, 2, 0}, 0x129F = {14668, 2, 0}, 0x12A0 = {14670, 2, 0}, 0x12A1 = {14672, 2, 0}, 0x12A2 = {14674, 2, 0}, 0x12A3 = {14676, 2, 0}, - 0x12A4 = {14678, 2, 0}, 0x12A5 = {14680, 2, 0}, 0x12A6 = {14682, 2, 0}, 0x12A7 = {14684, 2, 0}, 0x12A8 = {14686, 2, 0}, 0x12A9 = {14688, 2, 0}, 0x12AA = {14690, 2, 0}, 0x12AB = {14692, 2, 0}, 0x12AC = {14694, 2, 0}, 0x12AD = {14696, 2, 0}, 0x12AE = {14698, 2, 0}, 0x12AF = {14700, 2, 0}, 0x12B0 = {14702, 2, 0}, 0x12B1 = {14704, 2, 0}, 0x12B2 = {14706, 2, 0}, 0x12B3 = {14708, 2, 0}, - 0x12B4 = {14710, 2, 0}, 0x12B5 = {14712, 2, 0}, 0x12B6 = {14714, 2, 0}, 0x12B7 = {14716, 2, 0}, 0x12B8 = {14718, 2, 0}, 0x12B9 = {14720, 2, 0}, 0x12BA = {14722, 2, 0}, 0x12BB = {14724, 2, 0}, 0x12BC = {14726, 2, 0}, 0x12BD = {14728, 2, 0}, 0x12BE = {14730, 2, 0}, 0x12BF = {14732, 2, 0}, 0x12C0 = {14734, 2, 0}, 0x12C1 = {14736, 2, 0}, 0x12C2 = {14738, 2, 0}, 0x12C3 = {14740, 2, 0}, - 0x12C4 = {14742, 2, 0}, 0x12C5 = {14744, 2, 0}, 0x12C6 = {14746, 2, 0}, 0x12C7 = {14748, 2, 0}, 0x12C8 = {14750, 2, 0}, 0x12C9 = {14752, 2, 0}, 0x12CA = {14754, 2, 0}, 0x12CB = {14756, 2, 0}, 0x12CC = {14758, 2, 0}, 0x12CD = {14760, 2, 0}, 0x12CE = {14762, 2, 0}, 0x12CF = {14764, 2, 0}, 0x12D0 = {14766, 2, 0}, 0x12D1 = {14768, 2, 0}, 0x12D2 = {14770, 2, 0}, 0x12D3 = {14772, 2, 0}, - 0x12D4 = {14774, 2, 0}, 0x12D5 = {14776, 2, 0}, 0x12D6 = {14778, 2, 0}, 0x12D7 = {14780, 2, 0}, 0x12D8 = {14782, 2, 0}, 0x12D9 = {14784, 2, 0}, 0x12DA = {14786, 2, 0}, 0x12DB = {14788, 2, 0}, 0x12DC = {14790, 2, 0}, 0x12DD = {14792, 2, 0}, 0x12DE = {14794, 2, 0}, 0x12DF = {14796, 2, 0}, 0x12E0 = {14798, 2, 0}, 0x12E1 = {14800, 2, 0}, 0x12E2 = {14802, 2, 0}, 0x12E3 = {14804, 2, 0}, - 0x12E4 = {14806, 2, 0}, 0x12E5 = {14808, 2, 0}, 0x12E6 = {14810, 2, 0}, 0x12E7 = {14812, 2, 0}, 0x12E8 = {14814, 2, 0}, 0x12E9 = {14816, 2, 0}, 0x12EA = {14818, 2, 0}, 0x12EB = {14820, 2, 0}, 0x12EC = {14822, 2, 0}, 0x12ED = {14824, 2, 0}, 0x12EE = {14826, 2, 0}, 0x12EF = {14828, 2, 0}, 0x12F0 = {14830, 2, 0}, 0x12F1 = {14832, 2, 0}, 0x12F2 = {14834, 2, 0}, 0x12F3 = {14836, 2, 0}, - 0x12F4 = {14838, 2, 0}, 0x12F5 = {14840, 2, 0}, 0x12F6 = {14842, 2, 0}, 0x12F7 = {14844, 2, 0}, 0x12F8 = {14846, 2, 0}, 0x12F9 = {14848, 2, 0}, 0x12FA = {14850, 2, 0}, 0x12FB = {14852, 2, 0}, 0x12FC = {14854, 2, 0}, 0x12FD = {14856, 2, 0}, 0x12FE = {14858, 2, 0}, 0x12FF = {14860, 2, 0}, 0x1300 = {14862, 15, 0}, 0x1301 = {14877, 1, 0}, 0x1302 = {14878, 1, 0}, 0x1310 = {14879, 36, 0}, - 0x1312 = {14915, 2, 0}, 0x1321 = {14917, 2, 0}, 0x1322 = {14919, 1, 0}, 0x1326 = {14920, 1, 0}, 0x1327 = {14921, 1, 0}, 0x1330 = {14922, 2, 0}, 0x1332 = {14924, 1, 0}, 0x1342 = {14925, 1, 0}, 0x1362 = {14926, 1, 0}, 0x1372 = {14927, 1, 0}, 0x1381 = {14928, 1, 0}, 0x1382 = {14929, 1, 0}, 0x1392 = {14930, 1, 0}, 0x1396 = {14931, 1, 0}, 0x13A1 = {14932, 1, 0}, 0x13A2 = {14933, 1, 0}, - 0x13B2 = {14934, 1, 0}, 0x13C1 = {14935, 2, 0}, 0x13C2 = {14937, 1, 0}, 0x13E1 = {14938, 1, 0}, 0x13E2 = {14939, 1, 0}, 0x1400 = {14940, 2, 0}, 0x1401 = {14942, 2, 0}, 0x1402 = {14944, 2, 0}, 0x1403 = {14946, 2, 0}, 0x1404 = {14948, 2, 0}, 0x1405 = {14950, 2, 0}, 0x1406 = {14952, 2, 0}, 0x1407 = {14954, 2, 0}, 0x1408 = {14956, 2, 0}, 0x1409 = {14958, 2, 0}, 0x140A = {14960, 2, 0}, - 0x140B = {14962, 4, 0}, 0x140C = {14966, 2, 0}, 0x140D = {14968, 2, 0}, 0x140E = {14970, 2, 0}, 0x140F = {14972, 2, 0}, 0x1410 = {14974, 2, 0}, 0x1411 = {14976, 2, 0}, 0x1412 = {14978, 2, 0}, 0x1413 = {14980, 2, 0}, 0x1414 = {14982, 2, 0}, 0x1415 = {14984, 2, 0}, 0x1416 = {14986, 2, 0}, 0x1417 = {14988, 2, 0}, 0x1418 = {14990, 2, 0}, 0x1419 = {14992, 2, 0}, 0x141A = {14994, 2, 0}, - 0x141B = {14996, 2, 0}, 0x141C = {14998, 2, 0}, 0x141D = {15000, 2, 0}, 0x141E = {15002, 2, 0}, 0x141F = {15004, 2, 0}, 0x1420 = {15006, 2, 0}, 0x1421 = {15008, 2, 0}, 0x1422 = {15010, 2, 0}, 0x1423 = {15012, 2, 0}, 0x1424 = {15014, 2, 0}, 0x1425 = {15016, 2, 0}, 0x1426 = {15018, 2, 0}, 0x1427 = {15020, 2, 0}, 0x1428 = {15022, 2, 0}, 0x1429 = {15024, 2, 0}, 0x142A = {15026, 2, 0}, - 0x142B = {15028, 2, 0}, 0x142C = {15030, 2, 0}, 0x142D = {15032, 2, 0}, 0x142E = {15034, 2, 0}, 0x142F = {15036, 2, 0}, 0x1430 = {15038, 2, 0}, 0x1431 = {15040, 2, 0}, 0x1432 = {15042, 2, 0}, 0x1433 = {15044, 2, 0}, 0x1434 = {15046, 2, 0}, 0x1435 = {15048, 2, 0}, 0x1436 = {15050, 2, 0}, 0x1437 = {15052, 2, 0}, 0x1438 = {15054, 2, 0}, 0x1439 = {15056, 2, 0}, 0x143A = {15058, 2, 0}, - 0x143B = {15060, 2, 0}, 0x143C = {15062, 2, 0}, 0x143D = {15064, 2, 0}, 0x143E = {15066, 2, 0}, 0x143F = {15068, 2, 0}, 0x1440 = {15070, 2, 0}, 0x1441 = {15072, 2, 0}, 0x1442 = {15074, 2, 0}, 0x1443 = {15076, 2, 0}, 0x1444 = {15078, 2, 0}, 0x1445 = {15080, 2, 0}, 0x1446 = {15082, 2, 0}, 0x1447 = {15084, 2, 0}, 0x1448 = {15086, 2, 0}, 0x1449 = {15088, 2, 0}, 0x144A = {15090, 2, 0}, - 0x144B = {15092, 2, 0}, 0x144C = {15094, 2, 0}, 0x144D = {15096, 2, 0}, 0x144E = {15098, 2, 0}, 0x144F = {15100, 2, 0}, 0x1450 = {15102, 2, 0}, 0x1451 = {15104, 2, 0}, 0x1452 = {15106, 2, 0}, 0x1453 = {15108, 2, 0}, 0x1454 = {15110, 2, 0}, 0x1455 = {15112, 2, 0}, 0x1456 = {15114, 2, 0}, 0x1457 = {15116, 2, 0}, 0x1458 = {15118, 2, 0}, 0x1459 = {15120, 2, 0}, 0x145A = {15122, 2, 0}, - 0x145B = {15124, 2, 0}, 0x145C = {15126, 2, 0}, 0x145D = {15128, 2, 0}, 0x145E = {15130, 2, 0}, 0x145F = {15132, 2, 0}, 0x1460 = {15134, 2, 0}, 0x1461 = {15136, 2, 0}, 0x1462 = {15138, 2, 0}, 0x1463 = {15140, 2, 0}, 0x1464 = {15142, 2, 0}, 0x1465 = {15144, 2, 0}, 0x1466 = {15146, 2, 0}, 0x1467 = {15148, 2, 0}, 0x1468 = {15150, 2, 0}, 0x1469 = {15152, 2, 0}, 0x146A = {15154, 2, 0}, - 0x146B = {15156, 2, 0}, 0x146C = {15158, 2, 0}, 0x146D = {15160, 2, 0}, 0x146E = {15162, 2, 0}, 0x146F = {15164, 2, 0}, 0x1470 = {15166, 2, 0}, 0x1471 = {15168, 2, 0}, 0x1472 = {15170, 2, 0}, 0x1473 = {15172, 2, 0}, 0x1474 = {15174, 2, 0}, 0x1475 = {15176, 2, 0}, 0x1476 = {15178, 2, 0}, 0x1477 = {15180, 2, 0}, 0x1478 = {15182, 2, 0}, 0x1479 = {15184, 2, 0}, 0x147A = {15186, 2, 0}, - 0x147B = {15188, 2, 0}, 0x147C = {15190, 2, 0}, 0x147D = {15192, 2, 0}, 0x147E = {15194, 2, 0}, 0x147F = {15196, 2, 0}, 0x1480 = {15198, 2, 0}, 0x1481 = {15200, 2, 0}, 0x1482 = {15202, 2, 0}, 0x1483 = {15204, 2, 0}, 0x1484 = {15206, 2, 0}, 0x1485 = {15208, 2, 0}, 0x1486 = {15210, 2, 0}, 0x1487 = {15212, 2, 0}, 0x1488 = {15214, 2, 0}, 0x1489 = {15216, 2, 0}, 0x148A = {15218, 2, 0}, - 0x148B = {15220, 2, 0}, 0x148C = {15222, 2, 0}, 0x148D = {15224, 2, 0}, 0x148E = {15226, 2, 0}, 0x148F = {15228, 2, 0}, 0x1490 = {15230, 2, 0}, 0x1491 = {15232, 2, 0}, 0x1492 = {15234, 2, 0}, 0x1493 = {15236, 2, 0}, 0x1494 = {15238, 2, 0}, 0x1495 = {15240, 2, 0}, 0x1496 = {15242, 2, 0}, 0x1497 = {15244, 2, 0}, 0x1498 = {15246, 2, 0}, 0x1499 = {15248, 2, 0}, 0x149A = {15250, 2, 0}, - 0x149B = {15252, 2, 0}, 0x149C = {15254, 2, 0}, 0x149D = {15256, 2, 0}, 0x149E = {15258, 2, 0}, 0x149F = {15260, 2, 0}, 0x14A0 = {15262, 2, 0}, 0x14A1 = {15264, 2, 0}, 0x14A2 = {15266, 2, 0}, 0x14A3 = {15268, 2, 0}, 0x14A4 = {15270, 2, 0}, 0x14A5 = {15272, 2, 0}, 0x14A6 = {15274, 2, 0}, 0x14A7 = {15276, 2, 0}, 0x14A8 = {15278, 2, 0}, 0x14A9 = {15280, 2, 0}, 0x14AA = {15282, 2, 0}, - 0x14AB = {15284, 2, 0}, 0x14AC = {15286, 2, 0}, 0x14AD = {15288, 2, 0}, 0x14AE = {15290, 2, 0}, 0x14AF = {15292, 2, 0}, 0x14B0 = {15294, 2, 0}, 0x14B1 = {15296, 2, 0}, 0x14B2 = {15298, 2, 0}, 0x14B3 = {15300, 2, 0}, 0x14B4 = {15302, 2, 0}, 0x14B5 = {15304, 2, 0}, 0x14B6 = {15306, 2, 0}, 0x14B7 = {15308, 2, 0}, 0x14B8 = {15310, 2, 0}, 0x14B9 = {15312, 2, 0}, 0x14BA = {15314, 2, 0}, - 0x14BB = {15316, 2, 0}, 0x14BC = {15318, 2, 0}, 0x14BD = {15320, 2, 0}, 0x14BE = {15322, 2, 0}, 0x14BF = {15324, 2, 0}, 0x14C0 = {15326, 2, 0}, 0x14C1 = {15328, 2, 0}, 0x14C2 = {15330, 2, 0}, 0x14C3 = {15332, 2, 0}, 0x14C4 = {15334, 2, 0}, 0x14C5 = {15336, 2, 0}, 0x14C6 = {15338, 2, 0}, 0x14C7 = {15340, 2, 0}, 0x14C8 = {15342, 2, 0}, 0x14C9 = {15344, 2, 0}, 0x14CA = {15346, 2, 0}, - 0x14CB = {15348, 2, 0}, 0x14CC = {15350, 2, 0}, 0x14CD = {15352, 2, 0}, 0x14CE = {15354, 2, 0}, 0x14CF = {15356, 2, 0}, 0x14D0 = {15358, 2, 0}, 0x14D1 = {15360, 2, 0}, 0x14D2 = {15362, 2, 0}, 0x14D3 = {15364, 2, 0}, 0x14D4 = {15366, 2, 0}, 0x14D5 = {15368, 2, 0}, 0x14D6 = {15370, 2, 0}, 0x14D7 = {15372, 2, 0}, 0x14D8 = {15374, 2, 0}, 0x14D9 = {15376, 2, 0}, 0x14DA = {15378, 2, 0}, - 0x14DB = {15380, 2, 0}, 0x14DC = {15382, 2, 0}, 0x14DD = {15384, 2, 0}, 0x14DE = {15386, 2, 0}, 0x14DF = {15388, 2, 0}, 0x14E0 = {15390, 2, 0}, 0x14E1 = {15392, 2, 0}, 0x14E2 = {15394, 2, 0}, 0x14E3 = {15396, 2, 0}, 0x14E4 = {15398, 2, 0}, 0x14E5 = {15400, 2, 0}, 0x14E6 = {15402, 2, 0}, 0x14E7 = {15404, 2, 0}, 0x14E8 = {15406, 2, 0}, 0x14E9 = {15408, 2, 0}, 0x14EA = {15410, 2, 0}, - 0x14EB = {15412, 2, 0}, 0x14EC = {15414, 2, 0}, 0x14ED = {15416, 2, 0}, 0x14EE = {15418, 2, 0}, 0x14EF = {15420, 2, 0}, 0x14F0 = {15422, 2, 0}, 0x14F1 = {15424, 2, 0}, 0x14F2 = {15426, 2, 0}, 0x14F3 = {15428, 2, 0}, 0x14F4 = {15430, 2, 0}, 0x14F5 = {15432, 2, 0}, 0x14F6 = {15434, 2, 0}, 0x14F7 = {15436, 2, 0}, 0x14F8 = {15438, 2, 0}, 0x14F9 = {15440, 2, 0}, 0x14FA = {15442, 2, 0}, - 0x14FB = {15444, 2, 0}, 0x14FC = {15446, 2, 0}, 0x14FD = {15448, 2, 0}, 0x14FE = {15450, 2, 0}, 0x14FF = {15452, 2, 0}, 0x1500 = {15454, 2, 0}, 0x1501 = {15456, 2, 0}, 0x1502 = {15458, 2, 0}, 0x1503 = {15460, 3, 0}, 0x1504 = {15463, 2, 0}, 0x1505 = {15465, 2, 0}, 0x1506 = {15467, 2, 0}, 0x1507 = {15469, 2, 0}, 0x1508 = {15471, 2, 0}, 0x1509 = {15473, 2, 0}, 0x150A = {15475, 2, 0}, - 0x150B = {15477, 2, 0}, 0x150C = {15479, 2, 0}, 0x150D = {15481, 2, 0}, 0x150E = {15483, 2, 0}, 0x150F = {15485, 2, 0}, 0x1510 = {15487, 2, 0}, 0x1511 = {15489, 2, 0}, 0x1512 = {15491, 2, 0}, 0x1513 = {15493, 2, 0}, 0x1514 = {15495, 2, 0}, 0x1515 = {15497, 2, 0}, 0x1516 = {15499, 2, 0}, 0x1517 = {15501, 2, 0}, 0x1518 = {15503, 2, 0}, 0x1519 = {15505, 2, 0}, 0x151A = {15507, 2, 0}, - 0x151B = {15509, 4, 0}, 0x151C = {15513, 2, 0}, 0x151D = {15515, 2, 0}, 0x151E = {15517, 2, 0}, 0x151F = {15519, 3, 0}, 0x1520 = {15522, 2, 0}, 0x1521 = {15524, 2, 0}, 0x1522 = {15526, 2, 0}, 0x1523 = {15528, 2, 0}, 0x1524 = {15530, 2, 0}, 0x1525 = {15532, 2, 0}, 0x1526 = {15534, 2, 0}, 0x1527 = {15536, 2, 0}, 0x1528 = {15538, 2, 0}, 0x1529 = {15540, 2, 0}, 0x152A = {15542, 2, 0}, - 0x152B = {15544, 2, 0}, 0x152C = {15546, 2, 0}, 0x152D = {15548, 2, 0}, 0x152E = {15550, 2, 0}, 0x152F = {15552, 2, 0}, 0x1530 = {15554, 2, 0}, 0x1531 = {15556, 2, 0}, 0x1532 = {15558, 2, 0}, 0x1533 = {15560, 2, 0}, 0x1534 = {15562, 2, 0}, 0x1535 = {15564, 2, 0}, 0x1536 = {15566, 2, 0}, 0x1537 = {15568, 2, 0}, 0x1538 = {15570, 2, 0}, 0x1539 = {15572, 2, 0}, 0x153A = {15574, 2, 0}, - 0x153B = {15576, 2, 0}, 0x153C = {15578, 2, 0}, 0x153D = {15580, 2, 0}, 0x153E = {15582, 2, 0}, 0x153F = {15584, 2, 0}, 0x1540 = {15586, 2, 0}, 0x1541 = {15588, 2, 0}, 0x1542 = {15590, 2, 0}, 0x1543 = {15592, 2, 0}, 0x1544 = {15594, 2, 0}, 0x1545 = {15596, 2, 0}, 0x1546 = {15598, 2, 0}, 0x1547 = {15600, 2, 0}, 0x1548 = {15602, 2, 0}, 0x1549 = {15604, 2, 0}, 0x154A = {15606, 2, 0}, - 0x154B = {15608, 2, 0}, 0x154C = {15610, 2, 0}, 0x154D = {15612, 2, 0}, 0x154E = {15614, 2, 0}, 0x154F = {15616, 2, 0}, 0x1550 = {15618, 2, 0}, 0x1551 = {15620, 2, 0}, 0x1552 = {15622, 2, 0}, 0x1553 = {15624, 2, 0}, 0x1554 = {15626, 2, 0}, 0x1555 = {15628, 2, 0}, 0x1556 = {15630, 2, 0}, 0x1557 = {15632, 2, 0}, 0x1558 = {15634, 2, 0}, 0x1559 = {15636, 2, 0}, 0x155A = {15638, 2, 0}, - 0x155B = {15640, 2, 0}, 0x155C = {15642, 2, 0}, 0x155D = {15644, 2, 0}, 0x155E = {15646, 2, 0}, 0x155F = {15648, 2, 0}, 0x1560 = {15650, 2, 0}, 0x1561 = {15652, 2, 0}, 0x1562 = {15654, 2, 0}, 0x1563 = {15656, 2, 0}, 0x1564 = {15658, 2, 0}, 0x1565 = {15660, 2, 0}, 0x1566 = {15662, 2, 0}, 0x1567 = {15664, 2, 0}, 0x1568 = {15666, 2, 0}, 0x1569 = {15668, 2, 0}, 0x156A = {15670, 2, 0}, - 0x156B = {15672, 2, 0}, 0x156C = {15674, 2, 0}, 0x156D = {15676, 2, 0}, 0x156E = {15678, 2, 0}, 0x156F = {15680, 2, 0}, 0x1570 = {15682, 2, 0}, 0x1571 = {15684, 2, 0}, 0x1572 = {15686, 2, 0}, 0x1573 = {15688, 2, 0}, 0x1574 = {15690, 2, 0}, 0x1575 = {15692, 2, 0}, 0x1576 = {15694, 2, 0}, 0x1577 = {15696, 2, 0}, 0x1578 = {15698, 2, 0}, 0x1579 = {15700, 2, 0}, 0x157A = {15702, 2, 0}, - 0x157B = {15704, 2, 0}, 0x157C = {15706, 2, 0}, 0x157D = {15708, 2, 0}, 0x157E = {15710, 2, 0}, 0x157F = {15712, 2, 0}, 0x1580 = {15714, 2, 0}, 0x1581 = {15716, 2, 0}, 0x1582 = {15718, 2, 0}, 0x1583 = {15720, 2, 0}, 0x1584 = {15722, 2, 0}, 0x1585 = {15724, 2, 0}, 0x1586 = {15726, 2, 0}, 0x1587 = {15728, 2, 0}, 0x1588 = {15730, 2, 0}, 0x1589 = {15732, 2, 0}, 0x158A = {15734, 2, 0}, - 0x158B = {15736, 2, 0}, 0x158C = {15738, 2, 0}, 0x158D = {15740, 2, 0}, 0x158E = {15742, 2, 0}, 0x158F = {15744, 2, 0}, 0x1590 = {15746, 2, 0}, 0x1591 = {15748, 2, 0}, 0x1592 = {15750, 2, 0}, 0x1593 = {15752, 2, 0}, 0x1594 = {15754, 2, 0}, 0x1595 = {15756, 2, 0}, 0x1596 = {15758, 2, 0}, 0x1597 = {15760, 2, 0}, 0x1598 = {15762, 2, 0}, 0x1599 = {15764, 2, 0}, 0x159A = {15766, 2, 0}, - 0x159B = {15768, 2, 0}, 0x159C = {15770, 2, 0}, 0x159D = {15772, 2, 0}, 0x159E = {15774, 2, 0}, 0x159F = {15776, 5, 0}, 0x15A0 = {15781, 2, 0}, 0x15A1 = {15783, 2, 0}, 0x15A2 = {15785, 2, 0}, 0x15A3 = {15787, 2, 0}, 0x15A4 = {15789, 2, 0}, 0x15A5 = {15791, 2, 0}, 0x15A6 = {15793, 2, 0}, 0x15A7 = {15795, 2, 0}, 0x15A8 = {15797, 2, 0}, 0x15A9 = {15799, 2, 0}, 0x15AA = {15801, 2, 0}, - 0x15AB = {15803, 2, 0}, 0x15AC = {15805, 2, 0}, 0x15AD = {15807, 2, 0}, 0x15AE = {15809, 2, 0}, 0x15AF = {15811, 2, 0}, 0x15B0 = {15813, 2, 0}, 0x15B1 = {15815, 2, 0}, 0x15B2 = {15817, 2, 0}, 0x15B3 = {15819, 2, 0}, 0x15B4 = {15821, 2, 0}, 0x15B5 = {15823, 2, 0}, 0x15B6 = {15825, 2, 0}, 0x15B7 = {15827, 2, 0}, 0x15B8 = {15829, 2, 0}, 0x15B9 = {15831, 2, 0}, 0x15BA = {15833, 2, 0}, - 0x15BB = {15835, 2, 0}, 0x15BC = {15837, 2, 0}, 0x15BD = {15839, 2, 0}, 0x15BE = {15841, 2, 0}, 0x15BF = {15843, 2, 0}, 0x15C0 = {15845, 2, 0}, 0x15C1 = {15847, 2, 0}, 0x15C2 = {15849, 2, 0}, 0x15C3 = {15851, 2, 0}, 0x15C4 = {15853, 2, 0}, 0x15C5 = {15855, 2, 0}, 0x15C6 = {15857, 2, 0}, 0x15C7 = {15859, 2, 0}, 0x15C8 = {15861, 2, 0}, 0x15C9 = {15863, 2, 0}, 0x15CA = {15865, 2, 0}, - 0x15CB = {15867, 2, 0}, 0x15CC = {15869, 2, 0}, 0x15CD = {15871, 2, 0}, 0x15CE = {15873, 2, 0}, 0x15CF = {15875, 2, 0}, 0x15D0 = {15877, 2, 0}, 0x15D1 = {15879, 2, 0}, 0x15D2 = {15881, 2, 0}, 0x15D3 = {15883, 2, 0}, 0x15D4 = {15885, 2, 0}, 0x15D5 = {15887, 2, 0}, 0x15D6 = {15889, 2, 0}, 0x15D7 = {15891, 2, 0}, 0x15D8 = {15893, 2, 0}, 0x15D9 = {15895, 2, 0}, 0x15DA = {15897, 2, 0}, - 0x15DB = {15899, 2, 0}, 0x15DC = {15901, 2, 0}, 0x15DD = {15903, 2, 0}, 0x15DE = {15905, 2, 0}, 0x15DF = {15907, 2, 0}, 0x15E0 = {15909, 2, 0}, 0x15E1 = {15911, 2, 0}, 0x15E2 = {15913, 2, 0}, 0x15E3 = {15915, 2, 0}, 0x15E4 = {15917, 2, 0}, 0x15E5 = {15919, 2, 0}, 0x15E6 = {15921, 2, 0}, 0x15E7 = {15923, 2, 0}, 0x15E8 = {15925, 2, 0}, 0x15E9 = {15927, 2, 0}, 0x15EA = {15929, 2, 0}, - 0x15EB = {15931, 2, 0}, 0x15EC = {15933, 2, 0}, 0x15ED = {15935, 2, 0}, 0x15EE = {15937, 2, 0}, 0x15EF = {15939, 2, 0}, 0x15F0 = {15941, 2, 0}, 0x15F1 = {15943, 2, 0}, 0x15F2 = {15945, 2, 0}, 0x15F3 = {15947, 2, 0}, 0x15F4 = {15949, 2, 0}, 0x15F5 = {15951, 2, 0}, 0x15F6 = {15953, 2, 0}, 0x15F7 = {15955, 2, 0}, 0x15F8 = {15957, 2, 0}, 0x15F9 = {15959, 2, 0}, 0x15FA = {15961, 2, 0}, - 0x15FB = {15963, 2, 0}, 0x15FC = {15965, 2, 0}, 0x15FD = {15967, 2, 0}, 0x15FE = {15969, 2, 0}, 0x15FF = {15971, 2, 0}, 0x1700 = {15973, 2, 0}, 0x1701 = {15975, 2, 0}, 0x1702 = {15977, 2, 0}, 0x1703 = {15979, 2, 0}, 0x1704 = {15981, 2, 0}, 0x1705 = {15983, 2, 0}, 0x1706 = {15985, 2, 0}, 0x1707 = {15987, 2, 0}, 0x1708 = {15989, 2, 0}, 0x1709 = {15991, 2, 0}, 0x170A = {15993, 2, 0}, - 0x170B = {15995, 2, 0}, 0x170C = {15997, 2, 0}, 0x170D = {15999, 2, 0}, 0x170E = {16001, 2, 0}, 0x170F = {16003, 2, 0}, 0x1710 = {16005, 2, 0}, 0x1711 = {16007, 2, 0}, 0x1712 = {16009, 2, 0}, 0x1713 = {16011, 2, 0}, 0x1714 = {16013, 2, 0}, 0x1715 = {16015, 2, 0}, 0x1716 = {16017, 2, 0}, 0x1717 = {16019, 2, 0}, 0x1718 = {16021, 2, 0}, 0x1719 = {16023, 2, 0}, 0x171A = {16025, 2, 0}, - 0x171B = {16027, 2, 0}, 0x171C = {16029, 2, 0}, 0x171D = {16031, 2, 0}, 0x171E = {16033, 2, 0}, 0x171F = {16035, 4, 0}, 0x1720 = {16039, 2, 0}, 0x1721 = {16041, 2, 0}, 0x1722 = {16043, 2, 0}, 0x1723 = {16045, 2, 0}, 0x1724 = {16047, 2, 0}, 0x1725 = {16049, 2, 0}, 0x1726 = {16051, 2, 0}, 0x1727 = {16053, 2, 0}, 0x1728 = {16055, 2, 0}, 0x1729 = {16057, 2, 0}, 0x172A = {16059, 2, 0}, - 0x172B = {16061, 2, 0}, 0x172C = {16063, 2, 0}, 0x172D = {16065, 2, 0}, 0x172E = {16067, 2, 0}, 0x172F = {16069, 2, 0}, 0x1730 = {16071, 2, 0}, 0x1731 = {16073, 2, 0}, 0x1732 = {16075, 2, 0}, 0x1733 = {16077, 2, 0}, 0x1734 = {16079, 2, 0}, 0x1735 = {16081, 2, 0}, 0x1736 = {16083, 2, 0}, 0x1737 = {16085, 2, 0}, 0x1738 = {16087, 2, 0}, 0x1739 = {16089, 2, 0}, 0x173A = {16091, 2, 0}, - 0x173B = {16093, 2, 0}, 0x173C = {16095, 2, 0}, 0x173D = {16097, 2, 0}, 0x173E = {16099, 2, 0}, 0x173F = {16101, 2, 0}, 0x1740 = {16103, 2, 0}, 0x1741 = {16105, 2, 0}, 0x1742 = {16107, 2, 0}, 0x1743 = {16109, 2, 0}, 0x1744 = {16111, 2, 0}, 0x1745 = {16113, 2, 0}, 0x1746 = {16115, 2, 0}, 0x1747 = {16117, 2, 0}, 0x1748 = {16119, 2, 0}, 0x1749 = {16121, 2, 0}, 0x174A = {16123, 2, 0}, - 0x174B = {16125, 2, 0}, 0x174C = {16127, 2, 0}, 0x174D = {16129, 2, 0}, 0x174E = {16131, 2, 0}, 0x174F = {16133, 2, 0}, 0x1750 = {16135, 2, 0}, 0x1751 = {16137, 2, 0}, 0x1752 = {16139, 2, 0}, 0x1753 = {16141, 2, 0}, 0x1754 = {16143, 2, 0}, 0x1755 = {16145, 2, 0}, 0x1756 = {16147, 2, 0}, 0x1757 = {16149, 2, 0}, 0x1758 = {16151, 2, 0}, 0x1759 = {16153, 2, 0}, 0x175A = {16155, 2, 0}, - 0x175B = {16157, 2, 0}, 0x175C = {16159, 2, 0}, 0x175D = {16161, 2, 0}, 0x175E = {16163, 2, 0}, 0x175F = {16165, 2, 0}, 0x1760 = {16167, 2, 0}, 0x1761 = {16169, 2, 0}, 0x1762 = {16171, 2, 0}, 0x1763 = {16173, 2, 0}, 0x1764 = {16175, 2, 0}, 0x1765 = {16177, 2, 0}, 0x1766 = {16179, 2, 0}, 0x1767 = {16181, 2, 0}, 0x1768 = {16183, 2, 0}, 0x1769 = {16185, 2, 0}, 0x176A = {16187, 2, 0}, - 0x176B = {16189, 2, 0}, 0x176C = {16191, 2, 0}, 0x176D = {16193, 2, 0}, 0x176E = {16195, 2, 0}, 0x176F = {16197, 2, 0}, 0x1770 = {16199, 2, 0}, 0x1771 = {16201, 2, 0}, 0x1772 = {16203, 2, 0}, 0x1773 = {16205, 2, 0}, 0x1774 = {16207, 2, 0}, 0x1775 = {16209, 2, 0}, 0x1776 = {16211, 2, 0}, 0x1777 = {16213, 2, 0}, 0x1778 = {16215, 2, 0}, 0x1779 = {16217, 2, 0}, 0x177A = {16219, 2, 0}, - 0x177B = {16221, 2, 0}, 0x177C = {16223, 2, 0}, 0x177D = {16225, 2, 0}, 0x177E = {16227, 2, 0}, 0x177F = {16229, 2, 0}, 0x1780 = {16231, 2, 0}, 0x1781 = {16233, 2, 0}, 0x1782 = {16235, 2, 0}, 0x1783 = {16237, 2, 0}, 0x1784 = {16239, 2, 0}, 0x1785 = {16241, 2, 0}, 0x1786 = {16243, 2, 0}, 0x1787 = {16245, 2, 0}, 0x1788 = {16247, 2, 0}, 0x1789 = {16249, 2, 0}, 0x178A = {16251, 2, 0}, - 0x178B = {16253, 2, 0}, 0x178C = {16255, 2, 0}, 0x178D = {16257, 2, 0}, 0x178E = {16259, 2, 0}, 0x178F = {16261, 2, 0}, 0x1790 = {16263, 2, 0}, 0x1791 = {16265, 2, 0}, 0x1792 = {16267, 2, 0}, 0x1793 = {16269, 2, 0}, 0x1794 = {16271, 2, 0}, 0x1795 = {16273, 2, 0}, 0x1796 = {16275, 2, 0}, 0x1797 = {16277, 2, 0}, 0x1798 = {16279, 2, 0}, 0x1799 = {16281, 2, 0}, 0x179A = {16283, 2, 0}, - 0x179B = {16285, 2, 0}, 0x179C = {16287, 2, 0}, 0x179D = {16289, 2, 0}, 0x179E = {16291, 2, 0}, 0x179F = {16293, 2, 0}, 0x17A0 = {16295, 2, 0}, 0x17A1 = {16297, 2, 0}, 0x17A2 = {16299, 2, 0}, 0x17A3 = {16301, 2, 0}, 0x17A4 = {16303, 2, 0}, 0x17A5 = {16305, 2, 0}, 0x17A6 = {16307, 2, 0}, 0x17A7 = {16309, 2, 0}, 0x17A8 = {16311, 2, 0}, 0x17A9 = {16313, 2, 0}, 0x17AA = {16315, 2, 0}, - 0x17AB = {16317, 2, 0}, 0x17AC = {16319, 2, 0}, 0x17AD = {16321, 2, 0}, 0x17AE = {16323, 2, 0}, 0x17AF = {16325, 2, 0}, 0x17B0 = {16327, 2, 0}, 0x17B1 = {16329, 2, 0}, 0x17B2 = {16331, 2, 0}, 0x17B3 = {16333, 2, 0}, 0x17B4 = {16335, 2, 0}, 0x17B5 = {16337, 2, 0}, 0x17B6 = {16339, 2, 0}, 0x17B7 = {16341, 2, 0}, 0x17B8 = {16343, 2, 0}, 0x17B9 = {16345, 2, 0}, 0x17BA = {16347, 2, 0}, - 0x17BB = {16349, 2, 0}, 0x17BC = {16351, 2, 0}, 0x17BD = {16353, 2, 0}, 0x17BE = {16355, 2, 0}, 0x17BF = {16357, 2, 0}, 0x17C0 = {16359, 2, 0}, 0x17C1 = {16361, 2, 0}, 0x17C2 = {16363, 2, 0}, 0x17C3 = {16365, 2, 0}, 0x17C4 = {16367, 2, 0}, 0x17C5 = {16369, 2, 0}, 0x17C6 = {16371, 2, 0}, 0x17C7 = {16373, 2, 0}, 0x17C8 = {16375, 2, 0}, 0x17C9 = {16377, 2, 0}, 0x17CA = {16379, 2, 0}, - 0x17CB = {16381, 2, 0}, 0x17CC = {16383, 2, 0}, 0x17CD = {16385, 2, 0}, 0x17CE = {16387, 2, 0}, 0x17CF = {16389, 2, 0}, 0x17D0 = {16391, 2, 0}, 0x17D1 = {16393, 2, 0}, 0x17D2 = {16395, 2, 0}, 0x17D3 = {16397, 2, 0}, 0x17D4 = {16399, 2, 0}, 0x17D5 = {16401, 2, 0}, 0x17D6 = {16403, 2, 0}, 0x17D7 = {16405, 2, 0}, 0x17D8 = {16407, 2, 0}, 0x17D9 = {16409, 2, 0}, 0x17DA = {16411, 2, 0}, - 0x17DB = {16413, 2, 0}, 0x17DC = {16415, 2, 0}, 0x17DD = {16417, 2, 0}, 0x17DE = {16419, 2, 0}, 0x17DF = {16421, 2, 0}, 0x17E0 = {16423, 2, 0}, 0x17E1 = {16425, 2, 0}, 0x17E2 = {16427, 2, 0}, 0x17E3 = {16429, 2, 0}, 0x17E4 = {16431, 2, 0}, 0x17E5 = {16433, 2, 0}, 0x17E6 = {16435, 2, 0}, 0x17E7 = {16437, 2, 0}, 0x17E8 = {16439, 2, 0}, 0x17E9 = {16441, 2, 0}, 0x17EA = {16443, 2, 0}, - 0x17EB = {16445, 2, 0}, 0x17EC = {16447, 2, 0}, 0x17ED = {16449, 2, 0}, 0x17EE = {16451, 2, 0}, 0x17EF = {16453, 2, 0}, 0x17F0 = {16455, 2, 0}, 0x17F1 = {16457, 2, 0}, 0x17F2 = {16459, 2, 0}, 0x17F3 = {16461, 2, 0}, 0x17F4 = {16463, 2, 0}, 0x17F5 = {16465, 2, 0}, 0x17F6 = {16467, 2, 0}, 0x17F7 = {16469, 2, 0}, 0x17F8 = {16471, 2, 0}, 0x17F9 = {16473, 2, 0}, 0x17FA = {16475, 2, 0}, - 0x17FB = {16477, 2, 0}, 0x17FC = {16479, 2, 0}, 0x17FD = {16481, 2, 0}, 0x17FE = {16483, 2, 0}, 0x17FF = {16485, 2, 0}, 0x1800 = {16487, 3, 0}, 0x1801 = {16490, 1, 0}, 0x1802 = {16491, 1, 0}, 0x1803 = {16492, 1, 0}, 0x1804 = {16493, 1, 0}, 0x1805 = {16494, 1, 0}, 0x1806 = {16495, 1, 0}, 0x1807 = {16496, 1, 0}, 0x1808 = {16497, 1, 0}, 0x1809 = {16498, 1, 0}, 0x180A = {16499, 1, 0}, - 0x180B = {16500, 1, 0}, 0x180C = {16501, 1, 0}, 0x180D = {16502, 1, 0}, 0x180E = {16503, 1, 0}, 0x180F = {16504, 1, 0}, 0x1810 = {16505, 1, 0}, 0x1811 = {16506, 1, 0}, 0x1812 = {16507, 1, 0}, 0x1813 = {16508, 1, 0}, 0x1814 = {16509, 1, 0}, 0x1815 = {16510, 1, 0}, 0x1816 = {16511, 1, 0}, 0x1817 = {16512, 1, 0}, 0x1818 = {16513, 1, 0}, 0x1819 = {16514, 1, 0}, 0x181A = {16515, 1, 0}, - 0x181B = {16516, 1, 0}, 0x181C = {16517, 1, 0}, 0x181D = {16518, 1, 0}, 0x181E = {16519, 1, 0}, 0x181F = {16520, 1, 0}, 0x1820 = {16521, 1, 0}, 0x1821 = {16522, 1, 0}, 0x1822 = {16523, 1, 0}, 0x1823 = {16524, 1, 0}, 0x1824 = {16525, 1, 0}, 0x1825 = {16526, 1, 0}, 0x1826 = {16527, 1, 0}, 0x1827 = {16528, 1, 0}, 0x1828 = {16529, 1, 0}, 0x1829 = {16530, 1, 0}, 0x182A = {16531, 1, 0}, - 0x182B = {16532, 1, 0}, 0x182C = {16533, 1, 0}, 0x182D = {16534, 1, 0}, 0x182E = {16535, 1, 0}, 0x182F = {16536, 1, 0}, 0x1830 = {16537, 1, 0}, 0x1831 = {16538, 1, 0}, 0x1832 = {16539, 1, 0}, 0x1833 = {16540, 1, 0}, 0x1834 = {16541, 1, 0}, 0x1835 = {16542, 1, 0}, 0x1836 = {16543, 1, 0}, 0x1837 = {16544, 1, 0}, 0x1838 = {16545, 1, 0}, 0x1839 = {16546, 1, 0}, 0x183A = {16547, 1, 0}, - 0x183B = {16548, 1, 0}, 0x183C = {16549, 1, 0}, 0x183D = {16550, 1, 0}, 0x183E = {16551, 1, 0}, 0x183F = {16552, 1, 0}, 0x1840 = {16553, 1, 0}, 0x1841 = {16554, 1, 0}, 0x1842 = {16555, 1, 0}, 0x1843 = {16556, 1, 0}, 0x1844 = {16557, 1, 0}, 0x1845 = {16558, 1, 0}, 0x1846 = {16559, 1, 0}, 0x1847 = {16560, 1, 0}, 0x1848 = {16561, 1, 0}, 0x1849 = {16562, 1, 0}, 0x184A = {16563, 1, 0}, - 0x184B = {16564, 1, 0}, 0x184C = {16565, 1, 0}, 0x184D = {16566, 1, 0}, 0x184E = {16567, 1, 0}, 0x184F = {16568, 1, 0}, 0x1850 = {16569, 1, 0}, 0x1851 = {16570, 1, 0}, 0x1852 = {16571, 1, 0}, 0x1853 = {16572, 1, 0}, 0x1854 = {16573, 1, 0}, 0x1855 = {16574, 1, 0}, 0x1856 = {16575, 1, 0}, 0x1857 = {16576, 1, 0}, 0x1858 = {16577, 1, 0}, 0x1859 = {16578, 1, 0}, 0x185A = {16579, 1, 0}, - 0x185B = {16580, 1, 0}, 0x185C = {16581, 1, 0}, 0x185D = {16582, 1, 0}, 0x185E = {16583, 1, 0}, 0x185F = {16584, 1, 0}, 0x1860 = {16585, 1, 0}, 0x1861 = {16586, 1, 0}, 0x1862 = {16587, 1, 0}, 0x1863 = {16588, 1, 0}, 0x1864 = {16589, 1, 0}, 0x1865 = {16590, 1, 0}, 0x1866 = {16591, 1, 0}, 0x1867 = {16592, 1, 0}, 0x1868 = {16593, 1, 0}, 0x1869 = {16594, 1, 0}, 0x186A = {16595, 1, 0}, - 0x186B = {16596, 1, 0}, 0x186C = {16597, 1, 0}, 0x186D = {16598, 1, 0}, 0x186E = {16599, 1, 0}, 0x186F = {16600, 1, 0}, 0x1870 = {16601, 1, 0}, 0x1871 = {16602, 1, 0}, 0x1872 = {16603, 1, 0}, 0x1873 = {16604, 1, 0}, 0x1874 = {16605, 1, 0}, 0x1875 = {16606, 1, 0}, 0x1876 = {16607, 1, 0}, 0x1877 = {16608, 1, 0}, 0x1878 = {16609, 1, 0}, 0x1879 = {16610, 1, 0}, 0x187A = {16611, 1, 0}, - 0x187B = {16612, 1, 0}, 0x187C = {16613, 1, 0}, 0x187D = {16614, 1, 0}, 0x187E = {16615, 1, 0}, 0x187F = {16616, 1, 0}, 0x1880 = {16617, 1, 0}, 0x1881 = {16618, 1, 0}, 0x1882 = {16619, 1, 0}, 0x1883 = {16620, 1, 0}, 0x1884 = {16621, 1, 0}, 0x1885 = {16622, 1, 0}, 0x1886 = {16623, 1, 0}, 0x1887 = {16624, 1, 0}, 0x1888 = {16625, 1, 0}, 0x1889 = {16626, 1, 0}, 0x188A = {16627, 1, 0}, - 0x188B = {16628, 1, 0}, 0x188C = {16629, 1, 0}, 0x188D = {16630, 1, 0}, 0x188E = {16631, 1, 0}, 0x188F = {16632, 1, 0}, 0x1890 = {16633, 1, 0}, 0x1891 = {16634, 1, 0}, 0x1892 = {16635, 1, 0}, 0x1893 = {16636, 1, 0}, 0x1894 = {16637, 1, 0}, 0x1895 = {16638, 1, 0}, 0x1896 = {16639, 1, 0}, 0x1897 = {16640, 1, 0}, 0x1898 = {16641, 1, 0}, 0x1899 = {16642, 1, 0}, 0x189A = {16643, 1, 0}, - 0x189B = {16644, 1, 0}, 0x189C = {16645, 1, 0}, 0x189D = {16646, 1, 0}, 0x189E = {16647, 1, 0}, 0x189F = {16648, 1, 0}, 0x18A0 = {16649, 1, 0}, 0x18A1 = {16650, 1, 0}, 0x18A2 = {16651, 1, 0}, 0x18A3 = {16652, 1, 0}, 0x18A4 = {16653, 1, 0}, 0x18A5 = {16654, 1, 0}, 0x18A6 = {16655, 1, 0}, 0x18A7 = {16656, 1, 0}, 0x18A8 = {16657, 1, 0}, 0x18A9 = {16658, 1, 0}, 0x18AA = {16659, 1, 0}, - 0x18AB = {16660, 1, 0}, 0x18AC = {16661, 1, 0}, 0x18AD = {16662, 1, 0}, 0x18AE = {16663, 1, 0}, 0x18AF = {16664, 1, 0}, 0x18B0 = {16665, 1, 0}, 0x18B1 = {16666, 1, 0}, 0x18B2 = {16667, 1, 0}, 0x18B3 = {16668, 1, 0}, 0x18B4 = {16669, 1, 0}, 0x18B5 = {16670, 1, 0}, 0x18B6 = {16671, 1, 0}, 0x18B7 = {16672, 1, 0}, 0x18B8 = {16673, 1, 0}, 0x18B9 = {16674, 1, 0}, 0x18BA = {16675, 1, 0}, - 0x18BB = {16676, 1, 0}, 0x18BC = {16677, 1, 0}, 0x18BD = {16678, 1, 0}, 0x18BE = {16679, 1, 0}, 0x18BF = {16680, 1, 0}, 0x18C0 = {16681, 1, 0}, 0x18C1 = {16682, 1, 0}, 0x18C2 = {16683, 1, 0}, 0x18C3 = {16684, 1, 0}, 0x18C4 = {16685, 1, 0}, 0x18C5 = {16686, 1, 0}, 0x18C6 = {16687, 1, 0}, 0x18C7 = {16688, 1, 0}, 0x18C8 = {16689, 1, 0}, 0x18C9 = {16690, 1, 0}, 0x18CA = {16691, 1, 0}, - 0x18CB = {16692, 1, 0}, 0x18CC = {16693, 1, 0}, 0x18CD = {16694, 1, 0}, 0x18CE = {16695, 1, 0}, 0x18CF = {16696, 1, 0}, 0x18D0 = {16697, 1, 0}, 0x18D1 = {16698, 1, 0}, 0x18D2 = {16699, 1, 0}, 0x18D3 = {16700, 1, 0}, 0x18D4 = {16701, 1, 0}, 0x18D5 = {16702, 1, 0}, 0x18D6 = {16703, 1, 0}, 0x18D7 = {16704, 1, 0}, 0x18D8 = {16705, 1, 0}, 0x18D9 = {16706, 1, 0}, 0x18DA = {16707, 1, 0}, - 0x18DB = {16708, 1, 0}, 0x18DC = {16709, 1, 0}, 0x18DD = {16710, 1, 0}, 0x18DE = {16711, 1, 0}, 0x18DF = {16712, 1, 0}, 0x18E0 = {16713, 1, 0}, 0x18E1 = {16714, 1, 0}, 0x18E2 = {16715, 1, 0}, 0x18E3 = {16716, 1, 0}, 0x18E4 = {16717, 1, 0}, 0x18E5 = {16718, 1, 0}, 0x18E6 = {16719, 1, 0}, 0x18E7 = {16720, 1, 0}, 0x18E8 = {16721, 1, 0}, 0x18E9 = {16722, 1, 0}, 0x18EA = {16723, 1, 0}, - 0x18EB = {16724, 1, 0}, 0x18EC = {16725, 1, 0}, 0x18ED = {16726, 1, 0}, 0x18EE = {16727, 1, 0}, 0x18EF = {16728, 1, 0}, 0x18F0 = {16729, 1, 0}, 0x18F1 = {16730, 1, 0}, 0x18F2 = {16731, 1, 0}, 0x18F3 = {16732, 1, 0}, 0x18F4 = {16733, 1, 0}, 0x18F5 = {16734, 1, 0}, 0x18F6 = {16735, 1, 0}, 0x18F7 = {16736, 1, 0}, 0x18F8 = {16737, 1, 0}, 0x18F9 = {16738, 1, 0}, 0x18FA = {16739, 1, 0}, - 0x18FB = {16740, 1, 0}, 0x18FC = {16741, 1, 0}, 0x18FD = {16742, 1, 0}, 0x18FE = {16743, 1, 0}, 0x18FF = {16744, 1, 0}, 0x1900 = {16745, 2, 0}, 0x1901 = {16747, 1, 0}, 0x1902 = {16748, 1, 0}, 0x1903 = {16749, 1, 0}, 0x1904 = {16750, 1, 0}, 0x1905 = {16751, 1, 0}, 0x1906 = {16752, 1, 0}, 0x1907 = {16753, 1, 0}, 0x1908 = {16754, 1, 0}, 0x1909 = {16755, 1, 0}, 0x190A = {16756, 1, 0}, - 0x190B = {16757, 1, 0}, 0x190C = {16758, 1, 0}, 0x190D = {16759, 1, 0}, 0x190E = {16760, 1, 0}, 0x190F = {16761, 1, 0}, 0x1910 = {16762, 1, 0}, 0x1911 = {16763, 1, 0}, 0x1912 = {16764, 1, 0}, 0x1913 = {16765, 1, 0}, 0x1914 = {16766, 1, 0}, 0x1915 = {16767, 1, 0}, 0x1916 = {16768, 1, 0}, 0x1917 = {16769, 1, 0}, 0x1918 = {16770, 1, 0}, 0x1919 = {16771, 1, 0}, 0x191A = {16772, 1, 0}, - 0x191B = {16773, 1, 0}, 0x191C = {16774, 1, 0}, 0x191D = {16775, 1, 0}, 0x191E = {16776, 1, 0}, 0x191F = {16777, 1, 0}, 0x1920 = {16778, 1, 0}, 0x1921 = {16779, 1, 0}, 0x1922 = {16780, 1, 0}, 0x1923 = {16781, 1, 0}, 0x1924 = {16782, 1, 0}, 0x1925 = {16783, 1, 0}, 0x1926 = {16784, 1, 0}, 0x1927 = {16785, 1, 0}, 0x1928 = {16786, 1, 0}, 0x1929 = {16787, 1, 0}, 0x192A = {16788, 1, 0}, - 0x192B = {16789, 1, 0}, 0x192C = {16790, 1, 0}, 0x192D = {16791, 1, 0}, 0x192E = {16792, 1, 0}, 0x192F = {16793, 1, 0}, 0x1930 = {16794, 1, 0}, 0x1931 = {16795, 1, 0}, 0x1932 = {16796, 1, 0}, 0x1933 = {16797, 1, 0}, 0x1934 = {16798, 1, 0}, 0x1935 = {16799, 1, 0}, 0x1936 = {16800, 1, 0}, 0x1937 = {16801, 1, 0}, 0x1938 = {16802, 1, 0}, 0x1939 = {16803, 1, 0}, 0x193A = {16804, 1, 0}, - 0x193B = {16805, 1, 0}, 0x193C = {16806, 1, 0}, 0x193D = {16807, 1, 0}, 0x193E = {16808, 1, 0}, 0x193F = {16809, 1, 0}, 0x1940 = {16810, 1, 0}, 0x1941 = {16811, 1, 0}, 0x1942 = {16812, 1, 0}, 0x1943 = {16813, 1, 0}, 0x1944 = {16814, 1, 0}, 0x1945 = {16815, 1, 0}, 0x1946 = {16816, 1, 0}, 0x1947 = {16817, 1, 0}, 0x1948 = {16818, 1, 0}, 0x1949 = {16819, 1, 0}, 0x194A = {16820, 1, 0}, - 0x194B = {16821, 1, 0}, 0x194C = {16822, 1, 0}, 0x194D = {16823, 1, 0}, 0x194E = {16824, 1, 0}, 0x194F = {16825, 1, 0}, 0x1950 = {16826, 1, 0}, 0x1951 = {16827, 1, 0}, 0x1952 = {16828, 1, 0}, 0x1953 = {16829, 1, 0}, 0x1954 = {16830, 1, 0}, 0x1955 = {16831, 1, 0}, 0x1956 = {16832, 1, 0}, 0x1957 = {16833, 1, 0}, 0x1958 = {16834, 1, 0}, 0x1959 = {16835, 1, 0}, 0x195A = {16836, 1, 0}, - 0x195B = {16837, 1, 0}, 0x195C = {16838, 1, 0}, 0x195D = {16839, 1, 0}, 0x195E = {16840, 1, 0}, 0x195F = {16841, 1, 0}, 0x1960 = {16842, 1, 0}, 0x1961 = {16843, 1, 0}, 0x1962 = {16844, 1, 0}, 0x1963 = {16845, 1, 0}, 0x1964 = {16846, 1, 0}, 0x1965 = {16847, 1, 0}, 0x1966 = {16848, 1, 0}, 0x1967 = {16849, 1, 0}, 0x1968 = {16850, 1, 0}, 0x1969 = {16851, 1, 0}, 0x196A = {16852, 1, 0}, - 0x196B = {16853, 1, 0}, 0x196C = {16854, 1, 0}, 0x196D = {16855, 1, 0}, 0x196E = {16856, 1, 0}, 0x196F = {16857, 1, 0}, 0x1970 = {16858, 1, 0}, 0x1971 = {16859, 1, 0}, 0x1972 = {16860, 1, 0}, 0x1973 = {16861, 1, 0}, 0x1974 = {16862, 1, 0}, 0x1975 = {16863, 1, 0}, 0x1976 = {16864, 1, 0}, 0x1977 = {16865, 1, 0}, 0x1978 = {16866, 1, 0}, 0x1979 = {16867, 1, 0}, 0x197A = {16868, 1, 0}, - 0x197B = {16869, 1, 0}, 0x197C = {16870, 1, 0}, 0x197D = {16871, 1, 0}, 0x197E = {16872, 1, 0}, 0x197F = {16873, 1, 0}, 0x1980 = {16874, 1, 0}, 0x1981 = {16875, 1, 0}, 0x1982 = {16876, 1, 0}, 0x1983 = {16877, 1, 0}, 0x1984 = {16878, 1, 0}, 0x1985 = {16879, 1, 0}, 0x1986 = {16880, 1, 0}, 0x1987 = {16881, 1, 0}, 0x1988 = {16882, 1, 0}, 0x1989 = {16883, 1, 0}, 0x198A = {16884, 1, 0}, - 0x198B = {16885, 1, 0}, 0x198C = {16886, 1, 0}, 0x198D = {16887, 1, 0}, 0x198E = {16888, 1, 0}, 0x198F = {16889, 1, 0}, 0x1990 = {16890, 1, 0}, 0x1991 = {16891, 1, 0}, 0x1992 = {16892, 1, 0}, 0x1993 = {16893, 1, 0}, 0x1994 = {16894, 1, 0}, 0x1995 = {16895, 1, 0}, 0x1996 = {16896, 1, 0}, 0x1997 = {16897, 1, 0}, 0x1998 = {16898, 1, 0}, 0x1999 = {16899, 1, 0}, 0x199A = {16900, 1, 0}, - 0x199B = {16901, 1, 0}, 0x199C = {16902, 1, 0}, 0x199D = {16903, 1, 0}, 0x199E = {16904, 1, 0}, 0x199F = {16905, 1, 0}, 0x19A0 = {16906, 1, 0}, 0x19A1 = {16907, 1, 0}, 0x19A2 = {16908, 1, 0}, 0x19A3 = {16909, 1, 0}, 0x19A4 = {16910, 1, 0}, 0x19A5 = {16911, 1, 0}, 0x19A6 = {16912, 1, 0}, 0x19A7 = {16913, 1, 0}, 0x19A8 = {16914, 1, 0}, 0x19A9 = {16915, 1, 0}, 0x19AA = {16916, 1, 0}, - 0x19AB = {16917, 1, 0}, 0x19AC = {16918, 1, 0}, 0x19AD = {16919, 1, 0}, 0x19AE = {16920, 1, 0}, 0x19AF = {16921, 1, 0}, 0x19B0 = {16922, 1, 0}, 0x19B1 = {16923, 1, 0}, 0x19B2 = {16924, 1, 0}, 0x19B3 = {16925, 1, 0}, 0x19B4 = {16926, 1, 0}, 0x19B5 = {16927, 1, 0}, 0x19B6 = {16928, 1, 0}, 0x19B7 = {16929, 1, 0}, 0x19B8 = {16930, 1, 0}, 0x19B9 = {16931, 1, 0}, 0x19BA = {16932, 1, 0}, - 0x19BB = {16933, 1, 0}, 0x19BC = {16934, 1, 0}, 0x19BD = {16935, 1, 0}, 0x19BE = {16936, 1, 0}, 0x19BF = {16937, 1, 0}, 0x19C0 = {16938, 1, 0}, 0x19C1 = {16939, 1, 0}, 0x19C2 = {16940, 1, 0}, 0x19C3 = {16941, 1, 0}, 0x19C4 = {16942, 1, 0}, 0x19C5 = {16943, 1, 0}, 0x19C6 = {16944, 1, 0}, 0x19C7 = {16945, 1, 0}, 0x19C8 = {16946, 1, 0}, 0x19C9 = {16947, 1, 0}, 0x19CA = {16948, 1, 0}, - 0x19CB = {16949, 1, 0}, 0x19CC = {16950, 1, 0}, 0x19CD = {16951, 1, 0}, 0x19CE = {16952, 1, 0}, 0x19CF = {16953, 1, 0}, 0x19D0 = {16954, 1, 0}, 0x19D1 = {16955, 1, 0}, 0x19D2 = {16956, 1, 0}, 0x19D3 = {16957, 1, 0}, 0x19D4 = {16958, 1, 0}, 0x19D5 = {16959, 1, 0}, 0x19D6 = {16960, 1, 0}, 0x19D7 = {16961, 1, 0}, 0x19D8 = {16962, 1, 0}, 0x19D9 = {16963, 1, 0}, 0x19DA = {16964, 1, 0}, - 0x19DB = {16965, 1, 0}, 0x19DC = {16966, 1, 0}, 0x19DD = {16967, 1, 0}, 0x19DE = {16968, 1, 0}, 0x19DF = {16969, 1, 0}, 0x19E0 = {16970, 1, 0}, 0x19E1 = {16971, 1, 0}, 0x19E2 = {16972, 1, 0}, 0x19E3 = {16973, 1, 0}, 0x19E4 = {16974, 1, 0}, 0x19E5 = {16975, 1, 0}, 0x19E6 = {16976, 1, 0}, 0x19E7 = {16977, 1, 0}, 0x19E8 = {16978, 1, 0}, 0x19E9 = {16979, 1, 0}, 0x19EA = {16980, 1, 0}, - 0x19EB = {16981, 1, 0}, 0x19EC = {16982, 1, 0}, 0x19ED = {16983, 1, 0}, 0x19EE = {16984, 1, 0}, 0x19EF = {16985, 1, 0}, 0x19F0 = {16986, 1, 0}, 0x19F1 = {16987, 1, 0}, 0x19F2 = {16988, 1, 0}, 0x19F3 = {16989, 1, 0}, 0x19F4 = {16990, 1, 0}, 0x19F5 = {16991, 1, 0}, 0x19F6 = {16992, 1, 0}, 0x19F7 = {16993, 1, 0}, 0x19F8 = {16994, 1, 0}, 0x19F9 = {16995, 1, 0}, 0x19FA = {16996, 1, 0}, - 0x19FB = {16997, 1, 0}, 0x19FC = {16998, 1, 0}, 0x19FD = {16999, 1, 0}, 0x19FE = {17000, 1, 0}, 0x19FF = {17001, 1, 0}, 0x1A00 = {17002, 3, 0}, 0x1A01 = {17005, 1, 0}, 0x1A02 = {17006, 1, 0}, 0x1A03 = {17007, 1, 0}, 0x1A04 = {17008, 1, 0}, 0x1A05 = {17009, 1, 0}, 0x1A06 = {17010, 1, 0}, 0x1A07 = {17011, 1, 0}, 0x1A08 = {17012, 1, 0}, 0x1A09 = {17013, 1, 0}, 0x1A0A = {17014, 1, 0}, - 0x1A0B = {17015, 1, 0}, 0x1A0C = {17016, 1, 0}, 0x1A0D = {17017, 1, 0}, 0x1A0E = {17018, 1, 0}, 0x1A0F = {17019, 1, 0}, 0x1A10 = {17020, 1, 0}, 0x1A11 = {17021, 1, 0}, 0x1A12 = {17022, 1, 0}, 0x1A13 = {17023, 1, 0}, 0x1A14 = {17024, 1, 0}, 0x1A15 = {17025, 1, 0}, 0x1A16 = {17026, 1, 0}, 0x1A17 = {17027, 1, 0}, 0x1A18 = {17028, 1, 0}, 0x1A19 = {17029, 1, 0}, 0x1A1A = {17030, 1, 0}, - 0x1A1B = {17031, 1, 0}, 0x1A1C = {17032, 1, 0}, 0x1A1D = {17033, 1, 0}, 0x1A1E = {17034, 1, 0}, 0x1A1F = {17035, 1, 0}, 0x1A20 = {17036, 1, 0}, 0x1A21 = {17037, 1, 0}, 0x1A22 = {17038, 1, 0}, 0x1A23 = {17039, 1, 0}, 0x1A24 = {17040, 1, 0}, 0x1A25 = {17041, 1, 0}, 0x1A26 = {17042, 1, 0}, 0x1A27 = {17043, 1, 0}, 0x1A28 = {17044, 1, 0}, 0x1A29 = {17045, 1, 0}, 0x1A2A = {17046, 1, 0}, - 0x1A2B = {17047, 1, 0}, 0x1A2C = {17048, 1, 0}, 0x1A2D = {17049, 1, 0}, 0x1A2E = {17050, 1, 0}, 0x1A2F = {17051, 1, 0}, 0x1A30 = {17052, 1, 0}, 0x1A31 = {17053, 1, 0}, 0x1A32 = {17054, 1, 0}, 0x1A33 = {17055, 1, 0}, 0x1A34 = {17056, 1, 0}, 0x1A35 = {17057, 1, 0}, 0x1A36 = {17058, 1, 0}, 0x1A37 = {17059, 1, 0}, 0x1A38 = {17060, 1, 0}, 0x1A39 = {17061, 1, 0}, 0x1A3A = {17062, 1, 0}, - 0x1A3B = {17063, 1, 0}, 0x1A3C = {17064, 1, 0}, 0x1A3D = {17065, 1, 0}, 0x1A3E = {17066, 1, 0}, 0x1A3F = {17067, 1, 0}, 0x1A40 = {17068, 1, 0}, 0x1A41 = {17069, 1, 0}, 0x1A42 = {17070, 1, 0}, 0x1A43 = {17071, 1, 0}, 0x1A44 = {17072, 1, 0}, 0x1A45 = {17073, 1, 0}, 0x1A46 = {17074, 1, 0}, 0x1A47 = {17075, 1, 0}, 0x1A48 = {17076, 1, 0}, 0x1A49 = {17077, 1, 0}, 0x1A4A = {17078, 1, 0}, - 0x1A4B = {17079, 1, 0}, 0x1A4C = {17080, 1, 0}, 0x1A4D = {17081, 1, 0}, 0x1A4E = {17082, 1, 0}, 0x1A4F = {17083, 1, 0}, 0x1A50 = {17084, 1, 0}, 0x1A51 = {17085, 1, 0}, 0x1A52 = {17086, 1, 0}, 0x1A53 = {17087, 1, 0}, 0x1A54 = {17088, 1, 0}, 0x1A55 = {17089, 1, 0}, 0x1A56 = {17090, 1, 0}, 0x1A57 = {17091, 1, 0}, 0x1A58 = {17092, 1, 0}, 0x1A59 = {17093, 1, 0}, 0x1A5A = {17094, 1, 0}, - 0x1A5B = {17095, 1, 0}, 0x1A5C = {17096, 1, 0}, 0x1A5D = {17097, 1, 0}, 0x1A5E = {17098, 1, 0}, 0x1A5F = {17099, 1, 0}, 0x1A60 = {17100, 1, 0}, 0x1A61 = {17101, 1, 0}, 0x1A62 = {17102, 1, 0}, 0x1A63 = {17103, 1, 0}, 0x1A64 = {17104, 1, 0}, 0x1A65 = {17105, 1, 0}, 0x1A66 = {17106, 1, 0}, 0x1A67 = {17107, 1, 0}, 0x1A68 = {17108, 1, 0}, 0x1A69 = {17109, 1, 0}, 0x1A6A = {17110, 1, 0}, - 0x1A6B = {17111, 1, 0}, 0x1A6C = {17112, 1, 0}, 0x1A6D = {17113, 1, 0}, 0x1A6E = {17114, 1, 0}, 0x1A6F = {17115, 1, 0}, 0x1A70 = {17116, 1, 0}, 0x1A71 = {17117, 1, 0}, 0x1A72 = {17118, 1, 0}, 0x1A73 = {17119, 1, 0}, 0x1A74 = {17120, 1, 0}, 0x1A75 = {17121, 1, 0}, 0x1A76 = {17122, 1, 0}, 0x1A77 = {17123, 1, 0}, 0x1A78 = {17124, 1, 0}, 0x1A79 = {17125, 1, 0}, 0x1A7A = {17126, 1, 0}, - 0x1A7B = {17127, 1, 0}, 0x1A7C = {17128, 1, 0}, 0x1A7D = {17129, 1, 0}, 0x1A7E = {17130, 1, 0}, 0x1A7F = {17131, 1, 0}, 0x1A80 = {17132, 1, 0}, 0x1A81 = {17133, 1, 0}, 0x1A82 = {17134, 1, 0}, 0x1A83 = {17135, 1, 0}, 0x1A84 = {17136, 1, 0}, 0x1A85 = {17137, 1, 0}, 0x1A86 = {17138, 1, 0}, 0x1A87 = {17139, 1, 0}, 0x1A88 = {17140, 1, 0}, 0x1A89 = {17141, 1, 0}, 0x1A8A = {17142, 1, 0}, - 0x1A8B = {17143, 1, 0}, 0x1A8C = {17144, 1, 0}, 0x1A8D = {17145, 1, 0}, 0x1A8E = {17146, 1, 0}, 0x1A8F = {17147, 1, 0}, 0x1A90 = {17148, 1, 0}, 0x1A91 = {17149, 1, 0}, 0x1A92 = {17150, 1, 0}, 0x1A93 = {17151, 1, 0}, 0x1A94 = {17152, 1, 0}, 0x1A95 = {17153, 1, 0}, 0x1A96 = {17154, 1, 0}, 0x1A97 = {17155, 1, 0}, 0x1A98 = {17156, 1, 0}, 0x1A99 = {17157, 1, 0}, 0x1A9A = {17158, 1, 0}, - 0x1A9B = {17159, 1, 0}, 0x1A9C = {17160, 1, 0}, 0x1A9D = {17161, 1, 0}, 0x1A9E = {17162, 1, 0}, 0x1A9F = {17163, 1, 0}, 0x1AA0 = {17164, 1, 0}, 0x1AA1 = {17165, 1, 0}, 0x1AA2 = {17166, 1, 0}, 0x1AA3 = {17167, 1, 0}, 0x1AA4 = {17168, 1, 0}, 0x1AA5 = {17169, 1, 0}, 0x1AA6 = {17170, 1, 0}, 0x1AA7 = {17171, 1, 0}, 0x1AA8 = {17172, 1, 0}, 0x1AA9 = {17173, 1, 0}, 0x1AAA = {17174, 1, 0}, - 0x1AAB = {17175, 1, 0}, 0x1AAC = {17176, 1, 0}, 0x1AAD = {17177, 1, 0}, 0x1AAE = {17178, 1, 0}, 0x1AAF = {17179, 1, 0}, 0x1AB0 = {17180, 1, 0}, 0x1AB1 = {17181, 1, 0}, 0x1AB2 = {17182, 1, 0}, 0x1AB3 = {17183, 1, 0}, 0x1AB4 = {17184, 1, 0}, 0x1AB5 = {17185, 1, 0}, 0x1AB6 = {17186, 1, 0}, 0x1AB7 = {17187, 1, 0}, 0x1AB8 = {17188, 1, 0}, 0x1AB9 = {17189, 1, 0}, 0x1ABA = {17190, 1, 0}, - 0x1ABB = {17191, 1, 0}, 0x1ABC = {17192, 1, 0}, 0x1ABD = {17193, 1, 0}, 0x1ABE = {17194, 1, 0}, 0x1ABF = {17195, 1, 0}, 0x1AC0 = {17196, 1, 0}, 0x1AC1 = {17197, 1, 0}, 0x1AC2 = {17198, 1, 0}, 0x1AC3 = {17199, 1, 0}, 0x1AC4 = {17200, 1, 0}, 0x1AC5 = {17201, 1, 0}, 0x1AC6 = {17202, 1, 0}, 0x1AC7 = {17203, 1, 0}, 0x1AC8 = {17204, 1, 0}, 0x1AC9 = {17205, 1, 0}, 0x1ACA = {17206, 1, 0}, - 0x1ACB = {17207, 1, 0}, 0x1ACC = {17208, 1, 0}, 0x1ACD = {17209, 1, 0}, 0x1ACE = {17210, 1, 0}, 0x1ACF = {17211, 1, 0}, 0x1AD0 = {17212, 1, 0}, 0x1AD1 = {17213, 1, 0}, 0x1AD2 = {17214, 1, 0}, 0x1AD3 = {17215, 1, 0}, 0x1AD4 = {17216, 1, 0}, 0x1AD5 = {17217, 1, 0}, 0x1AD6 = {17218, 1, 0}, 0x1AD7 = {17219, 1, 0}, 0x1AD8 = {17220, 1, 0}, 0x1AD9 = {17221, 1, 0}, 0x1ADA = {17222, 1, 0}, - 0x1ADB = {17223, 1, 0}, 0x1ADC = {17224, 1, 0}, 0x1ADD = {17225, 1, 0}, 0x1ADE = {17226, 1, 0}, 0x1ADF = {17227, 1, 0}, 0x1AE0 = {17228, 1, 0}, 0x1AE1 = {17229, 1, 0}, 0x1AE2 = {17230, 1, 0}, 0x1AE3 = {17231, 1, 0}, 0x1AE4 = {17232, 1, 0}, 0x1AE5 = {17233, 1, 0}, 0x1AE6 = {17234, 1, 0}, 0x1AE7 = {17235, 1, 0}, 0x1AE8 = {17236, 1, 0}, 0x1AE9 = {17237, 1, 0}, 0x1AEA = {17238, 1, 0}, - 0x1AEB = {17239, 1, 0}, 0x1AEC = {17240, 1, 0}, 0x1AED = {17241, 1, 0}, 0x1AEE = {17242, 1, 0}, 0x1AEF = {17243, 1, 0}, 0x1AF0 = {17244, 1, 0}, 0x1AF1 = {17245, 1, 0}, 0x1AF2 = {17246, 1, 0}, 0x1AF3 = {17247, 1, 0}, 0x1AF4 = {17248, 1, 0}, 0x1AF5 = {17249, 1, 0}, 0x1AF6 = {17250, 1, 0}, 0x1AF7 = {17251, 1, 0}, 0x1AF8 = {17252, 1, 0}, 0x1AF9 = {17253, 1, 0}, 0x1AFA = {17254, 1, 0}, - 0x1AFB = {17255, 1, 0}, 0x1AFC = {17256, 1, 0}, 0x1AFD = {17257, 1, 0}, 0x1AFE = {17258, 1, 0}, 0x1AFF = {17259, 1, 0}, 0x1B00 = {17260, 2, 0}, 0x1B01 = {17262, 1, 0}, 0x1B02 = {17263, 1, 0}, 0x1B03 = {17264, 1, 0}, 0x1B04 = {17265, 1, 0}, 0x1B05 = {17266, 1, 0}, 0x1B06 = {17267, 1, 0}, 0x1B07 = {17268, 1, 0}, 0x1B08 = {17269, 1, 0}, 0x1B09 = {17270, 1, 0}, 0x1B0A = {17271, 1, 0}, - 0x1B0B = {17272, 1, 0}, 0x1B0C = {17273, 1, 0}, 0x1B0D = {17274, 1, 0}, 0x1B0E = {17275, 1, 0}, 0x1B0F = {17276, 1, 0}, 0x1B10 = {17277, 1, 0}, 0x1B11 = {17278, 1, 0}, 0x1B12 = {17279, 1, 0}, 0x1B13 = {17280, 1, 0}, 0x1B14 = {17281, 1, 0}, 0x1B15 = {17282, 1, 0}, 0x1B16 = {17283, 1, 0}, 0x1B17 = {17284, 1, 0}, 0x1B18 = {17285, 1, 0}, 0x1B19 = {17286, 1, 0}, 0x1B1A = {17287, 1, 0}, - 0x1B1B = {17288, 1, 0}, 0x1B1C = {17289, 1, 0}, 0x1B1D = {17290, 1, 0}, 0x1B1E = {17291, 1, 0}, 0x1B1F = {17292, 1, 0}, 0x1B20 = {17293, 1, 0}, 0x1B21 = {17294, 1, 0}, 0x1B22 = {17295, 1, 0}, 0x1B23 = {17296, 1, 0}, 0x1B24 = {17297, 1, 0}, 0x1B25 = {17298, 1, 0}, 0x1B26 = {17299, 1, 0}, 0x1B27 = {17300, 1, 0}, 0x1B28 = {17301, 1, 0}, 0x1B29 = {17302, 1, 0}, 0x1B2A = {17303, 1, 0}, - 0x1B2B = {17304, 1, 0}, 0x1B2C = {17305, 1, 0}, 0x1B2D = {17306, 1, 0}, 0x1B2E = {17307, 1, 0}, 0x1B2F = {17308, 1, 0}, 0x1B30 = {17309, 1, 0}, 0x1B31 = {17310, 1, 0}, 0x1B32 = {17311, 1, 0}, 0x1B33 = {17312, 1, 0}, 0x1B34 = {17313, 1, 0}, 0x1B35 = {17314, 1, 0}, 0x1B36 = {17315, 1, 0}, 0x1B37 = {17316, 1, 0}, 0x1B38 = {17317, 1, 0}, 0x1B39 = {17318, 1, 0}, 0x1B3A = {17319, 1, 0}, - 0x1B3B = {17320, 1, 0}, 0x1B3C = {17321, 1, 0}, 0x1B3D = {17322, 1, 0}, 0x1B3E = {17323, 1, 0}, 0x1B3F = {17324, 1, 0}, 0x1B40 = {17325, 1, 0}, 0x1B41 = {17326, 1, 0}, 0x1B42 = {17327, 1, 0}, 0x1B43 = {17328, 1, 0}, 0x1B44 = {17329, 1, 0}, 0x1B45 = {17330, 1, 0}, 0x1B46 = {17331, 1, 0}, 0x1B47 = {17332, 1, 0}, 0x1B48 = {17333, 1, 0}, 0x1B49 = {17334, 1, 0}, 0x1B4A = {17335, 1, 0}, - 0x1B4B = {17336, 1, 0}, 0x1B4C = {17337, 1, 0}, 0x1B4D = {17338, 1, 0}, 0x1B4E = {17339, 1, 0}, 0x1B4F = {17340, 1, 0}, 0x1B50 = {17341, 1, 0}, 0x1B51 = {17342, 1, 0}, 0x1B52 = {17343, 1, 0}, 0x1B53 = {17344, 1, 0}, 0x1B54 = {17345, 1, 0}, 0x1B55 = {17346, 1, 0}, 0x1B56 = {17347, 1, 0}, 0x1B57 = {17348, 1, 0}, 0x1B58 = {17349, 1, 0}, 0x1B59 = {17350, 1, 0}, 0x1B5A = {17351, 1, 0}, - 0x1B5B = {17352, 1, 0}, 0x1B5C = {17353, 1, 0}, 0x1B5D = {17354, 1, 0}, 0x1B5E = {17355, 1, 0}, 0x1B5F = {17356, 1, 0}, 0x1B60 = {17357, 1, 0}, 0x1B61 = {17358, 1, 0}, 0x1B62 = {17359, 1, 0}, 0x1B63 = {17360, 1, 0}, 0x1B64 = {17361, 1, 0}, 0x1B65 = {17362, 1, 0}, 0x1B66 = {17363, 1, 0}, 0x1B67 = {17364, 1, 0}, 0x1B68 = {17365, 1, 0}, 0x1B69 = {17366, 1, 0}, 0x1B6A = {17367, 1, 0}, - 0x1B6B = {17368, 1, 0}, 0x1B6C = {17369, 1, 0}, 0x1B6D = {17370, 1, 0}, 0x1B6E = {17371, 1, 0}, 0x1B6F = {17372, 1, 0}, 0x1B70 = {17373, 1, 0}, 0x1B71 = {17374, 1, 0}, 0x1B72 = {17375, 1, 0}, 0x1B73 = {17376, 1, 0}, 0x1B74 = {17377, 1, 0}, 0x1B75 = {17378, 1, 0}, 0x1B76 = {17379, 1, 0}, 0x1B77 = {17380, 1, 0}, 0x1B78 = {17381, 1, 0}, 0x1B79 = {17382, 1, 0}, 0x1B7A = {17383, 1, 0}, - 0x1B7B = {17384, 1, 0}, 0x1B7C = {17385, 1, 0}, 0x1B7D = {17386, 1, 0}, 0x1B7E = {17387, 1, 0}, 0x1B7F = {17388, 1, 0}, 0x1B80 = {17389, 1, 0}, 0x1B81 = {17390, 1, 0}, 0x1B82 = {17391, 1, 0}, 0x1B83 = {17392, 1, 0}, 0x1B84 = {17393, 1, 0}, 0x1B85 = {17394, 1, 0}, 0x1B86 = {17395, 1, 0}, 0x1B87 = {17396, 1, 0}, 0x1B88 = {17397, 1, 0}, 0x1B89 = {17398, 1, 0}, 0x1B8A = {17399, 1, 0}, - 0x1B8B = {17400, 1, 0}, 0x1B8C = {17401, 1, 0}, 0x1B8D = {17402, 1, 0}, 0x1B8E = {17403, 1, 0}, 0x1B8F = {17404, 1, 0}, 0x1B90 = {17405, 1, 0}, 0x1B91 = {17406, 1, 0}, 0x1B92 = {17407, 1, 0}, 0x1B93 = {17408, 1, 0}, 0x1B94 = {17409, 1, 0}, 0x1B95 = {17410, 1, 0}, 0x1B96 = {17411, 1, 0}, 0x1B97 = {17412, 1, 0}, 0x1B98 = {17413, 1, 0}, 0x1B99 = {17414, 1, 0}, 0x1B9A = {17415, 1, 0}, - 0x1B9B = {17416, 1, 0}, 0x1B9C = {17417, 1, 0}, 0x1B9D = {17418, 1, 0}, 0x1B9E = {17419, 1, 0}, 0x1B9F = {17420, 1, 0}, 0x1BA0 = {17421, 1, 0}, 0x1BA1 = {17422, 1, 0}, 0x1BA2 = {17423, 1, 0}, 0x1BA3 = {17424, 1, 0}, 0x1BA4 = {17425, 1, 0}, 0x1BA5 = {17426, 1, 0}, 0x1BA6 = {17427, 1, 0}, 0x1BA7 = {17428, 1, 0}, 0x1BA8 = {17429, 1, 0}, 0x1BA9 = {17430, 1, 0}, 0x1BAA = {17431, 1, 0}, - 0x1BAB = {17432, 1, 0}, 0x1BAC = {17433, 1, 0}, 0x1BAD = {17434, 1, 0}, 0x1BAE = {17435, 1, 0}, 0x1BAF = {17436, 1, 0}, 0x1BB0 = {17437, 1, 0}, 0x1BB1 = {17438, 1, 0}, 0x1BB2 = {17439, 1, 0}, 0x1BB3 = {17440, 1, 0}, 0x1BB4 = {17441, 1, 0}, 0x1BB5 = {17442, 1, 0}, 0x1BB6 = {17443, 1, 0}, 0x1BB7 = {17444, 1, 0}, 0x1BB8 = {17445, 1, 0}, 0x1BB9 = {17446, 1, 0}, 0x1BBA = {17447, 1, 0}, - 0x1BBB = {17448, 1, 0}, 0x1BBC = {17449, 1, 0}, 0x1BBD = {17450, 1, 0}, 0x1BBE = {17451, 1, 0}, 0x1BBF = {17452, 1, 0}, 0x1BC0 = {17453, 1, 0}, 0x1BC1 = {17454, 1, 0}, 0x1BC2 = {17455, 1, 0}, 0x1BC3 = {17456, 1, 0}, 0x1BC4 = {17457, 1, 0}, 0x1BC5 = {17458, 1, 0}, 0x1BC6 = {17459, 1, 0}, 0x1BC7 = {17460, 1, 0}, 0x1BC8 = {17461, 1, 0}, 0x1BC9 = {17462, 1, 0}, 0x1BCA = {17463, 1, 0}, - 0x1BCB = {17464, 1, 0}, 0x1BCC = {17465, 1, 0}, 0x1BCD = {17466, 1, 0}, 0x1BCE = {17467, 1, 0}, 0x1BCF = {17468, 1, 0}, 0x1BD0 = {17469, 1, 0}, 0x1BD1 = {17470, 1, 0}, 0x1BD2 = {17471, 1, 0}, 0x1BD3 = {17472, 1, 0}, 0x1BD4 = {17473, 1, 0}, 0x1BD5 = {17474, 1, 0}, 0x1BD6 = {17475, 1, 0}, 0x1BD7 = {17476, 1, 0}, 0x1BD8 = {17477, 1, 0}, 0x1BD9 = {17478, 1, 0}, 0x1BDA = {17479, 1, 0}, - 0x1BDB = {17480, 1, 0}, 0x1BDC = {17481, 1, 0}, 0x1BDD = {17482, 1, 0}, 0x1BDE = {17483, 1, 0}, 0x1BDF = {17484, 1, 0}, 0x1BE0 = {17485, 1, 0}, 0x1BE1 = {17486, 1, 0}, 0x1BE2 = {17487, 1, 0}, 0x1BE3 = {17488, 1, 0}, 0x1BE4 = {17489, 1, 0}, 0x1BE5 = {17490, 1, 0}, 0x1BE6 = {17491, 1, 0}, 0x1BE7 = {17492, 1, 0}, 0x1BE8 = {17493, 1, 0}, 0x1BE9 = {17494, 1, 0}, 0x1BEA = {17495, 1, 0}, - 0x1BEB = {17496, 1, 0}, 0x1BEC = {17497, 1, 0}, 0x1BED = {17498, 1, 0}, 0x1BEE = {17499, 1, 0}, 0x1BEF = {17500, 1, 0}, 0x1BF0 = {17501, 1, 0}, 0x1BF1 = {17502, 1, 0}, 0x1BF2 = {17503, 1, 0}, 0x1BF3 = {17504, 1, 0}, 0x1BF4 = {17505, 1, 0}, 0x1BF5 = {17506, 1, 0}, 0x1BF6 = {17507, 1, 0}, 0x1BF7 = {17508, 1, 0}, 0x1BF8 = {17509, 1, 0}, 0x1BF9 = {17510, 1, 0}, 0x1BFA = {17511, 1, 0}, - 0x1BFB = {17512, 1, 0}, 0x1BFC = {17513, 1, 0}, 0x1BFD = {17514, 1, 0}, 0x1BFE = {17515, 1, 0}, 0x1BFF = {17516, 1, 0}, 0x1C00 = {17517, 2, 0}, 0x1C01 = {17519, 1, 0}, 0x1C02 = {17520, 1, 0}, 0x1C03 = {17521, 1, 0}, 0x1C04 = {17522, 1, 0}, 0x1C05 = {17523, 1, 0}, 0x1C06 = {17524, 1, 0}, 0x1C07 = {17525, 1, 0}, 0x1C08 = {17526, 1, 0}, 0x1C09 = {17527, 1, 0}, 0x1C0A = {17528, 1, 0}, - 0x1C0B = {17529, 1, 0}, 0x1C0C = {17530, 1, 0}, 0x1C0D = {17531, 1, 0}, 0x1C0E = {17532, 1, 0}, 0x1C0F = {17533, 1, 0}, 0x1C10 = {17534, 1, 0}, 0x1C11 = {17535, 1, 0}, 0x1C12 = {17536, 1, 0}, 0x1C13 = {17537, 1, 0}, 0x1C14 = {17538, 1, 0}, 0x1C15 = {17539, 1, 0}, 0x1C16 = {17540, 1, 0}, 0x1C17 = {17541, 1, 0}, 0x1C18 = {17542, 1, 0}, 0x1C19 = {17543, 1, 0}, 0x1C1A = {17544, 1, 0}, - 0x1C1B = {17545, 1, 0}, 0x1C1C = {17546, 1, 0}, 0x1C1D = {17547, 1, 0}, 0x1C1E = {17548, 1, 0}, 0x1C1F = {17549, 1, 0}, 0x1C20 = {17550, 1, 0}, 0x1C21 = {17551, 1, 0}, 0x1C22 = {17552, 1, 0}, 0x1C23 = {17553, 1, 0}, 0x1C24 = {17554, 1, 0}, 0x1C25 = {17555, 1, 0}, 0x1C26 = {17556, 1, 0}, 0x1C27 = {17557, 1, 0}, 0x1C28 = {17558, 1, 0}, 0x1C29 = {17559, 1, 0}, 0x1C2A = {17560, 1, 0}, - 0x1C2B = {17561, 1, 0}, 0x1C2C = {17562, 1, 0}, 0x1C2D = {17563, 1, 0}, 0x1C2E = {17564, 1, 0}, 0x1C2F = {17565, 1, 0}, 0x1C30 = {17566, 1, 0}, 0x1C31 = {17567, 1, 0}, 0x1C32 = {17568, 1, 0}, 0x1C33 = {17569, 1, 0}, 0x1C34 = {17570, 1, 0}, 0x1C35 = {17571, 1, 0}, 0x1C36 = {17572, 1, 0}, 0x1C37 = {17573, 1, 0}, 0x1C38 = {17574, 1, 0}, 0x1C39 = {17575, 1, 0}, 0x1C3A = {17576, 1, 0}, - 0x1C3B = {17577, 1, 0}, 0x1C3C = {17578, 1, 0}, 0x1C3D = {17579, 1, 0}, 0x1C3E = {17580, 1, 0}, 0x1C3F = {17581, 1, 0}, 0x1C40 = {17582, 1, 0}, 0x1C41 = {17583, 1, 0}, 0x1C42 = {17584, 1, 0}, 0x1C43 = {17585, 1, 0}, 0x1C44 = {17586, 1, 0}, 0x1C45 = {17587, 1, 0}, 0x1C46 = {17588, 1, 0}, 0x1C47 = {17589, 1, 0}, 0x1C48 = {17590, 1, 0}, 0x1C49 = {17591, 1, 0}, 0x1C4A = {17592, 1, 0}, - 0x1C4B = {17593, 1, 0}, 0x1C4C = {17594, 1, 0}, 0x1C4D = {17595, 1, 0}, 0x1C4E = {17596, 1, 0}, 0x1C4F = {17597, 1, 0}, 0x1C50 = {17598, 1, 0}, 0x1C51 = {17599, 1, 0}, 0x1C52 = {17600, 1, 0}, 0x1C53 = {17601, 1, 0}, 0x1C54 = {17602, 1, 0}, 0x1C55 = {17603, 1, 0}, 0x1C56 = {17604, 1, 0}, 0x1C57 = {17605, 1, 0}, 0x1C58 = {17606, 1, 0}, 0x1C59 = {17607, 1, 0}, 0x1C5A = {17608, 1, 0}, - 0x1C5B = {17609, 1, 0}, 0x1C5C = {17610, 1, 0}, 0x1C5D = {17611, 1, 0}, 0x1C5E = {17612, 1, 0}, 0x1C5F = {17613, 1, 0}, 0x1C60 = {17614, 1, 0}, 0x1C61 = {17615, 1, 0}, 0x1C62 = {17616, 1, 0}, 0x1C63 = {17617, 1, 0}, 0x1C64 = {17618, 1, 0}, 0x1C65 = {17619, 1, 0}, 0x1C66 = {17620, 1, 0}, 0x1C67 = {17621, 1, 0}, 0x1C68 = {17622, 1, 0}, 0x1C69 = {17623, 1, 0}, 0x1C6A = {17624, 1, 0}, - 0x1C6B = {17625, 1, 0}, 0x1C6C = {17626, 1, 0}, 0x1C6D = {17627, 1, 0}, 0x1C6E = {17628, 1, 0}, 0x1C6F = {17629, 1, 0}, 0x1C70 = {17630, 1, 0}, 0x1C71 = {17631, 1, 0}, 0x1C72 = {17632, 1, 0}, 0x1C73 = {17633, 1, 0}, 0x1C74 = {17634, 1, 0}, 0x1C75 = {17635, 1, 0}, 0x1C76 = {17636, 1, 0}, 0x1C77 = {17637, 1, 0}, 0x1C78 = {17638, 1, 0}, 0x1C79 = {17639, 1, 0}, 0x1C7A = {17640, 1, 0}, - 0x1C7B = {17641, 1, 0}, 0x1C7C = {17642, 1, 0}, 0x1C7D = {17643, 1, 0}, 0x1C7E = {17644, 1, 0}, 0x1C7F = {17645, 1, 0}, 0x1C80 = {17646, 1, 0}, 0x1C81 = {17647, 1, 0}, 0x1C82 = {17648, 1, 0}, 0x1C83 = {17649, 1, 0}, 0x1C84 = {17650, 1, 0}, 0x1C85 = {17651, 1, 0}, 0x1C86 = {17652, 1, 0}, 0x1C87 = {17653, 1, 0}, 0x1C88 = {17654, 1, 0}, 0x1C89 = {17655, 1, 0}, 0x1C8A = {17656, 1, 0}, - 0x1C8B = {17657, 1, 0}, 0x1C8C = {17658, 1, 0}, 0x1C8D = {17659, 1, 0}, 0x1C8E = {17660, 1, 0}, 0x1C8F = {17661, 1, 0}, 0x1C90 = {17662, 1, 0}, 0x1C91 = {17663, 1, 0}, 0x1C92 = {17664, 1, 0}, 0x1C93 = {17665, 1, 0}, 0x1C94 = {17666, 1, 0}, 0x1C95 = {17667, 1, 0}, 0x1C96 = {17668, 1, 0}, 0x1C97 = {17669, 1, 0}, 0x1C98 = {17670, 1, 0}, 0x1C99 = {17671, 1, 0}, 0x1C9A = {17672, 1, 0}, - 0x1C9B = {17673, 1, 0}, 0x1C9C = {17674, 1, 0}, 0x1C9D = {17675, 1, 0}, 0x1C9E = {17676, 1, 0}, 0x1C9F = {17677, 1, 0}, 0x1CA0 = {17678, 1, 0}, 0x1CA1 = {17679, 1, 0}, 0x1CA2 = {17680, 1, 0}, 0x1CA3 = {17681, 1, 0}, 0x1CA4 = {17682, 1, 0}, 0x1CA5 = {17683, 1, 0}, 0x1CA6 = {17684, 1, 0}, 0x1CA7 = {17685, 1, 0}, 0x1CA8 = {17686, 1, 0}, 0x1CA9 = {17687, 1, 0}, 0x1CAA = {17688, 1, 0}, - 0x1CAB = {17689, 1, 0}, 0x1CAC = {17690, 1, 0}, 0x1CAD = {17691, 1, 0}, 0x1CAE = {17692, 1, 0}, 0x1CAF = {17693, 1, 0}, 0x1CB0 = {17694, 1, 0}, 0x1CB1 = {17695, 1, 0}, 0x1CB2 = {17696, 1, 0}, 0x1CB3 = {17697, 1, 0}, 0x1CB4 = {17698, 1, 0}, 0x1CB5 = {17699, 1, 0}, 0x1CB6 = {17700, 1, 0}, 0x1CB7 = {17701, 1, 0}, 0x1CB8 = {17702, 1, 0}, 0x1CB9 = {17703, 1, 0}, 0x1CBA = {17704, 1, 0}, - 0x1CBB = {17705, 1, 0}, 0x1CBC = {17706, 1, 0}, 0x1CBD = {17707, 1, 0}, 0x1CBE = {17708, 1, 0}, 0x1CBF = {17709, 1, 0}, 0x1CC0 = {17710, 1, 0}, 0x1CC1 = {17711, 1, 0}, 0x1CC2 = {17712, 1, 0}, 0x1CC3 = {17713, 1, 0}, 0x1CC4 = {17714, 1, 0}, 0x1CC5 = {17715, 1, 0}, 0x1CC6 = {17716, 1, 0}, 0x1CC7 = {17717, 1, 0}, 0x1CC8 = {17718, 1, 0}, 0x1CC9 = {17719, 1, 0}, 0x1CCA = {17720, 1, 0}, - 0x1CCB = {17721, 1, 0}, 0x1CCC = {17722, 1, 0}, 0x1CCD = {17723, 1, 0}, 0x1CCE = {17724, 1, 0}, 0x1CCF = {17725, 1, 0}, 0x1CD0 = {17726, 1, 0}, 0x1CD1 = {17727, 1, 0}, 0x1CD2 = {17728, 1, 0}, 0x1CD3 = {17729, 1, 0}, 0x1CD4 = {17730, 1, 0}, 0x1CD5 = {17731, 1, 0}, 0x1CD6 = {17732, 1, 0}, 0x1CD7 = {17733, 1, 0}, 0x1CD8 = {17734, 1, 0}, 0x1CD9 = {17735, 1, 0}, 0x1CDA = {17736, 1, 0}, - 0x1CDB = {17737, 1, 0}, 0x1CDC = {17738, 1, 0}, 0x1CDD = {17739, 1, 0}, 0x1CDE = {17740, 1, 0}, 0x1CDF = {17741, 1, 0}, 0x1CE0 = {17742, 1, 0}, 0x1CE1 = {17743, 1, 0}, 0x1CE2 = {17744, 1, 0}, 0x1CE3 = {17745, 1, 0}, 0x1CE4 = {17746, 1, 0}, 0x1CE5 = {17747, 1, 0}, 0x1CE6 = {17748, 1, 0}, 0x1CE7 = {17749, 1, 0}, 0x1CE8 = {17750, 1, 0}, 0x1CE9 = {17751, 1, 0}, 0x1CEA = {17752, 1, 0}, - 0x1CEB = {17753, 1, 0}, 0x1CEC = {17754, 1, 0}, 0x1CED = {17755, 1, 0}, 0x1CEE = {17756, 1, 0}, 0x1CEF = {17757, 1, 0}, 0x1CF0 = {17758, 1, 0}, 0x1CF1 = {17759, 1, 0}, 0x1CF2 = {17760, 1, 0}, 0x1CF3 = {17761, 1, 0}, 0x1CF4 = {17762, 1, 0}, 0x1CF5 = {17763, 1, 0}, 0x1CF6 = {17764, 1, 0}, 0x1CF7 = {17765, 1, 0}, 0x1CF8 = {17766, 1, 0}, 0x1CF9 = {17767, 1, 0}, 0x1CFA = {17768, 1, 0}, - 0x1CFB = {17769, 1, 0}, 0x1CFC = {17770, 1, 0}, 0x1CFD = {17771, 1, 0}, 0x1CFE = {17772, 1, 0}, 0x1CFF = {17773, 1, 0}, 0x1D00 = {17774, 2, 0}, 0x1D01 = {17776, 1, 0}, 0x1D02 = {17777, 1, 0}, 0x1D03 = {17778, 1, 0}, 0x1D04 = {17779, 1, 0}, 0x1D05 = {17780, 1, 0}, 0x1D06 = {17781, 1, 0}, 0x1D07 = {17782, 1, 0}, 0x1D08 = {17783, 1, 0}, 0x1D09 = {17784, 1, 0}, 0x1D0A = {17785, 1, 0}, - 0x1D0B = {17786, 1, 0}, 0x1D0C = {17787, 1, 0}, 0x1D0D = {17788, 1, 0}, 0x1D0E = {17789, 1, 0}, 0x1D0F = {17790, 1, 0}, 0x1D10 = {17791, 1, 0}, 0x1D11 = {17792, 1, 0}, 0x1D12 = {17793, 1, 0}, 0x1D13 = {17794, 1, 0}, 0x1D14 = {17795, 1, 0}, 0x1D15 = {17796, 1, 0}, 0x1D16 = {17797, 1, 0}, 0x1D17 = {17798, 1, 0}, 0x1D18 = {17799, 1, 0}, 0x1D19 = {17800, 1, 0}, 0x1D1A = {17801, 1, 0}, - 0x1D1B = {17802, 1, 0}, 0x1D1C = {17803, 1, 0}, 0x1D1D = {17804, 1, 0}, 0x1D1E = {17805, 1, 0}, 0x1D1F = {17806, 1, 0}, 0x1D20 = {17807, 1, 0}, 0x1D21 = {17808, 1, 0}, 0x1D22 = {17809, 1, 0}, 0x1D23 = {17810, 1, 0}, 0x1D24 = {17811, 1, 0}, 0x1D25 = {17812, 1, 0}, 0x1D26 = {17813, 1, 0}, 0x1D27 = {17814, 1, 0}, 0x1D28 = {17815, 1, 0}, 0x1D29 = {17816, 1, 0}, 0x1D2A = {17817, 1, 0}, - 0x1D2B = {17818, 1, 0}, 0x1D2C = {17819, 1, 0}, 0x1D2D = {17820, 1, 0}, 0x1D2E = {17821, 1, 0}, 0x1D2F = {17822, 1, 0}, 0x1D30 = {17823, 1, 0}, 0x1D31 = {17824, 1, 0}, 0x1D32 = {17825, 1, 0}, 0x1D33 = {17826, 1, 0}, 0x1D34 = {17827, 1, 0}, 0x1D35 = {17828, 1, 0}, 0x1D36 = {17829, 1, 0}, 0x1D37 = {17830, 1, 0}, 0x1D38 = {17831, 1, 0}, 0x1D39 = {17832, 1, 0}, 0x1D3A = {17833, 1, 0}, - 0x1D3B = {17834, 1, 0}, 0x1D3C = {17835, 1, 0}, 0x1D3D = {17836, 1, 0}, 0x1D3E = {17837, 1, 0}, 0x1D3F = {17838, 1, 0}, 0x1D40 = {17839, 1, 0}, 0x1D41 = {17840, 1, 0}, 0x1D42 = {17841, 1, 0}, 0x1D43 = {17842, 1, 0}, 0x1D44 = {17843, 1, 0}, 0x1D45 = {17844, 1, 0}, 0x1D46 = {17845, 1, 0}, 0x1D47 = {17846, 1, 0}, 0x1D48 = {17847, 1, 0}, 0x1D49 = {17848, 1, 0}, 0x1D4A = {17849, 1, 0}, - 0x1D4B = {17850, 1, 0}, 0x1D4C = {17851, 1, 0}, 0x1D4D = {17852, 1, 0}, 0x1D4E = {17853, 1, 0}, 0x1D4F = {17854, 1, 0}, 0x1D50 = {17855, 1, 0}, 0x1D51 = {17856, 1, 0}, 0x1D52 = {17857, 1, 0}, 0x1D53 = {17858, 1, 0}, 0x1D54 = {17859, 1, 0}, 0x1D55 = {17860, 1, 0}, 0x1D56 = {17861, 1, 0}, 0x1D57 = {17862, 1, 0}, 0x1D58 = {17863, 1, 0}, 0x1D59 = {17864, 1, 0}, 0x1D5A = {17865, 1, 0}, - 0x1D5B = {17866, 1, 0}, 0x1D5C = {17867, 1, 0}, 0x1D5D = {17868, 1, 0}, 0x1D5E = {17869, 1, 0}, 0x1D5F = {17870, 1, 0}, 0x1D60 = {17871, 1, 0}, 0x1D61 = {17872, 1, 0}, 0x1D62 = {17873, 1, 0}, 0x1D63 = {17874, 1, 0}, 0x1D64 = {17875, 1, 0}, 0x1D65 = {17876, 1, 0}, 0x1D66 = {17877, 1, 0}, 0x1D67 = {17878, 1, 0}, 0x1D68 = {17879, 1, 0}, 0x1D69 = {17880, 1, 0}, 0x1D6A = {17881, 1, 0}, - 0x1D6B = {17882, 1, 0}, 0x1D6C = {17883, 1, 0}, 0x1D6D = {17884, 1, 0}, 0x1D6E = {17885, 1, 0}, 0x1D6F = {17886, 1, 0}, 0x1D70 = {17887, 1, 0}, 0x1D71 = {17888, 1, 0}, 0x1D72 = {17889, 1, 0}, 0x1D73 = {17890, 1, 0}, 0x1D74 = {17891, 1, 0}, 0x1D75 = {17892, 1, 0}, 0x1D76 = {17893, 1, 0}, 0x1D77 = {17894, 1, 0}, 0x1D78 = {17895, 1, 0}, 0x1D79 = {17896, 1, 0}, 0x1D7A = {17897, 1, 0}, - 0x1D7B = {17898, 1, 0}, 0x1D7C = {17899, 1, 0}, 0x1D7D = {17900, 1, 0}, 0x1D7E = {17901, 1, 0}, 0x1D7F = {17902, 1, 0}, 0x1D80 = {17903, 1, 0}, 0x1D81 = {17904, 1, 0}, 0x1D82 = {17905, 1, 0}, 0x1D83 = {17906, 1, 0}, 0x1D84 = {17907, 1, 0}, 0x1D85 = {17908, 1, 0}, 0x1D86 = {17909, 1, 0}, 0x1D87 = {17910, 1, 0}, 0x1D88 = {17911, 1, 0}, 0x1D89 = {17912, 1, 0}, 0x1D8A = {17913, 1, 0}, - 0x1D8B = {17914, 1, 0}, 0x1D8C = {17915, 1, 0}, 0x1D8D = {17916, 1, 0}, 0x1D8E = {17917, 1, 0}, 0x1D8F = {17918, 1, 0}, 0x1D90 = {17919, 1, 0}, 0x1D91 = {17920, 1, 0}, 0x1D92 = {17921, 1, 0}, 0x1D93 = {17922, 1, 0}, 0x1D94 = {17923, 1, 0}, 0x1D95 = {17924, 1, 0}, 0x1D96 = {17925, 1, 0}, 0x1D97 = {17926, 1, 0}, 0x1D98 = {17927, 1, 0}, 0x1D99 = {17928, 1, 0}, 0x1D9A = {17929, 1, 0}, - 0x1D9B = {17930, 1, 0}, 0x1D9C = {17931, 1, 0}, 0x1D9D = {17932, 1, 0}, 0x1D9E = {17933, 1, 0}, 0x1D9F = {17934, 1, 0}, 0x1DA0 = {17935, 1, 0}, 0x1DA1 = {17936, 1, 0}, 0x1DA2 = {17937, 1, 0}, 0x1DA3 = {17938, 1, 0}, 0x1DA4 = {17939, 1, 0}, 0x1DA5 = {17940, 1, 0}, 0x1DA6 = {17941, 1, 0}, 0x1DA7 = {17942, 1, 0}, 0x1DA8 = {17943, 1, 0}, 0x1DA9 = {17944, 1, 0}, 0x1DAA = {17945, 1, 0}, - 0x1DAB = {17946, 1, 0}, 0x1DAC = {17947, 1, 0}, 0x1DAD = {17948, 1, 0}, 0x1DAE = {17949, 1, 0}, 0x1DAF = {17950, 1, 0}, 0x1DB0 = {17951, 1, 0}, 0x1DB1 = {17952, 1, 0}, 0x1DB2 = {17953, 1, 0}, 0x1DB3 = {17954, 1, 0}, 0x1DB4 = {17955, 1, 0}, 0x1DB5 = {17956, 1, 0}, 0x1DB6 = {17957, 1, 0}, 0x1DB7 = {17958, 1, 0}, 0x1DB8 = {17959, 1, 0}, 0x1DB9 = {17960, 1, 0}, 0x1DBA = {17961, 1, 0}, - 0x1DBB = {17962, 1, 0}, 0x1DBC = {17963, 1, 0}, 0x1DBD = {17964, 1, 0}, 0x1DBE = {17965, 1, 0}, 0x1DBF = {17966, 1, 0}, 0x1DC0 = {17967, 1, 0}, 0x1DC1 = {17968, 1, 0}, 0x1DC2 = {17969, 1, 0}, 0x1DC3 = {17970, 1, 0}, 0x1DC4 = {17971, 1, 0}, 0x1DC5 = {17972, 1, 0}, 0x1DC6 = {17973, 1, 0}, 0x1DC7 = {17974, 1, 0}, 0x1DC8 = {17975, 1, 0}, 0x1DC9 = {17976, 1, 0}, 0x1DCA = {17977, 1, 0}, - 0x1DCB = {17978, 1, 0}, 0x1DCC = {17979, 1, 0}, 0x1DCD = {17980, 1, 0}, 0x1DCE = {17981, 1, 0}, 0x1DCF = {17982, 1, 0}, 0x1DD0 = {17983, 1, 0}, 0x1DD1 = {17984, 1, 0}, 0x1DD2 = {17985, 1, 0}, 0x1DD3 = {17986, 1, 0}, 0x1DD4 = {17987, 1, 0}, 0x1DD5 = {17988, 1, 0}, 0x1DD6 = {17989, 1, 0}, 0x1DD7 = {17990, 1, 0}, 0x1DD8 = {17991, 1, 0}, 0x1DD9 = {17992, 1, 0}, 0x1DDA = {17993, 1, 0}, - 0x1DDB = {17994, 1, 0}, 0x1DDC = {17995, 1, 0}, 0x1DDD = {17996, 1, 0}, 0x1DDE = {17997, 1, 0}, 0x1DDF = {17998, 1, 0}, 0x1DE0 = {17999, 1, 0}, 0x1DE1 = {18000, 1, 0}, 0x1DE2 = {18001, 1, 0}, 0x1DE3 = {18002, 1, 0}, 0x1DE4 = {18003, 1, 0}, 0x1DE5 = {18004, 1, 0}, 0x1DE6 = {18005, 1, 0}, 0x1DE7 = {18006, 1, 0}, 0x1DE8 = {18007, 1, 0}, 0x1DE9 = {18008, 1, 0}, 0x1DEA = {18009, 1, 0}, - 0x1DEB = {18010, 1, 0}, 0x1DEC = {18011, 1, 0}, 0x1DED = {18012, 1, 0}, 0x1DEE = {18013, 1, 0}, 0x1DEF = {18014, 1, 0}, 0x1DF0 = {18015, 1, 0}, 0x1DF1 = {18016, 1, 0}, 0x1DF2 = {18017, 1, 0}, 0x1DF3 = {18018, 1, 0}, 0x1DF4 = {18019, 1, 0}, 0x1DF5 = {18020, 1, 0}, 0x1DF6 = {18021, 1, 0}, 0x1DF7 = {18022, 1, 0}, 0x1DF8 = {18023, 1, 0}, 0x1DF9 = {18024, 1, 0}, 0x1DFA = {18025, 1, 0}, - 0x1DFB = {18026, 1, 0}, 0x1DFC = {18027, 1, 0}, 0x1DFD = {18028, 1, 0}, 0x1DFE = {18029, 1, 0}, 0x1DFF = {18030, 1, 0}, 0x1E00 = {18031, 8, 0}, 0x1E01 = {18039, 3, 0}, 0x1E02 = {18042, 5, 0}, 0x1E03 = {18047, 2, 0}, 0x1E04 = {18049, 4, 0}, 0x1E05 = {18053, 2, 0}, 0x1E06 = {18055, 4, 0}, 0x1E07 = {18059, 2, 0}, 0x1E08 = {18061, 4, 0}, 0x1E09 = {18065, 2, 0}, 0x1E10 = {18067, 2, 0}, - 0x1E11 = {18069, 2, 0}, 0x1E12 = {18071, 2, 0}, 0x1E13 = {18073, 2, 0}, 0x1E14 = {18075, 2, 0}, 0x1E15 = {18077, 2, 0}, 0x1E16 = {18079, 2, 0}, 0x1E17 = {18081, 2, 0}, 0x1E20 = {18083, 2, 0}, 0x1E21 = {18085, 2, 0}, 0x1E22 = {18087, 2, 0}, 0x1E23 = {18089, 2, 0}, 0x1E24 = {18091, 2, 0}, 0x1E25 = {18093, 2, 0}, 0x1E26 = {18095, 2, 0}, 0x1E27 = {18097, 2, 0}, 0x1E28 = {18099, 2, 0}, - 0x1E29 = {18101, 2, 0}, 0x1E30 = {18103, 2, 0}, 0x1E31 = {18105, 2, 0}, 0x1E32 = {18107, 2, 0}, 0x1E33 = {18109, 2, 0}, 0x1E34 = {18111, 2, 0}, 0x1E35 = {18113, 2, 0}, 0x1E36 = {18115, 2, 0}, 0x1E37 = {18117, 2, 0}, 0x1E40 = {18119, 2, 0}, 0x1E41 = {18121, 2, 0}, 0x1E42 = {18123, 2, 0}, 0x1E43 = {18125, 2, 0}, 0x1E44 = {18127, 2, 0}, 0x1E45 = {18129, 2, 0}, 0x1E46 = {18131, 2, 0}, - 0x1E47 = {18133, 2, 0}, 0x1E48 = {18135, 2, 0}, 0x1E49 = {18137, 2, 0}, 0x1E50 = {18139, 2, 0}, 0x1E51 = {18141, 2, 0}, 0x1E52 = {18143, 2, 0}, 0x1E53 = {18145, 2, 0}, 0x1E54 = {18147, 2, 0}, 0x1E55 = {18149, 2, 0}, 0x1E56 = {18151, 2, 0}, 0x1E57 = {18153, 2, 0}, 0x1E60 = {18155, 2, 0}, 0x1E61 = {18157, 2, 0}, 0x1E62 = {18159, 3, 0}, 0x1E63 = {18162, 2, 0}, 0x1E64 = {18164, 2, 0}, - 0x1E65 = {18166, 2, 0}, 0x1E66 = {18168, 2, 0}, 0x1E67 = {18170, 2, 0}, 0x1E68 = {18172, 2, 0}, 0x1E69 = {18174, 2, 0}, 0x1E70 = {18176, 2, 0}, 0x1E71 = {18178, 2, 0}, 0x1E72 = {18180, 4, 0}, 0x1E73 = {18184, 2, 0}, 0x1E74 = {18186, 2, 0}, 0x1E75 = {18188, 2, 0}, 0x1E76 = {18190, 2, 0}, 0x1E77 = {18192, 2, 0}, 0x1E80 = {18194, 3, 0}, 0x1E81 = {18197, 3, 0}, 0x1E82 = {18200, 2, 0}, - 0x1E83 = {18202, 2, 0}, 0x1E84 = {18204, 2, 0}, 0x1E85 = {18206, 2, 0}, 0x1E86 = {18208, 2, 0}, 0x1E87 = {18210, 2, 0}, 0x1E88 = {18212, 2, 0}, 0x1E89 = {18214, 2, 0}, 0x1E90 = {18216, 3, 0}, 0x1E91 = {18219, 2, 0}, 0x1E92 = {18221, 2, 0}, 0x1E93 = {18223, 2, 0}, 0x1E94 = {18225, 2, 0}, 0x1E95 = {18227, 2, 0}, 0x1E96 = {18229, 2, 0}, 0x1E97 = {18231, 2, 0}, 0x1EA0 = {18233, 2, 0}, - 0x1EA1 = {18235, 2, 0}, 0x1EA2 = {18237, 2, 0}, 0x1EA3 = {18239, 2, 0}, 0x1EA4 = {18241, 2, 0}, 0x1EA5 = {18243, 2, 0}, 0x1EA6 = {18245, 2, 0}, 0x1EA7 = {18247, 2, 0}, 0x1EA8 = {18249, 2, 0}, 0x1EA9 = {18251, 2, 0}, 0x1EB0 = {18253, 2, 0}, 0x1EB1 = {18255, 2, 0}, 0x1EB2 = {18257, 2, 0}, 0x1EB3 = {18259, 2, 0}, 0x1EB4 = {18261, 2, 0}, 0x1EB5 = {18263, 2, 0}, 0x1EB6 = {18265, 2, 0}, - 0x1EB7 = {18267, 2, 0}, 0x1EC0 = {18269, 2, 0}, 0x1EC1 = {18271, 2, 0}, 0x1EC2 = {18273, 2, 0}, 0x1EC3 = {18275, 2, 0}, 0x1EC4 = {18277, 2, 0}, 0x1EC5 = {18279, 2, 0}, 0x1EC6 = {18281, 2, 0}, 0x1EC7 = {18283, 2, 0}, 0x1EC8 = {18285, 2, 0}, 0x1EC9 = {18287, 2, 0}, 0x1ED0 = {18289, 2, 0}, 0x1ED1 = {18291, 2, 0}, 0x1ED2 = {18293, 2, 0}, 0x1ED3 = {18295, 2, 0}, 0x1ED4 = {18297, 2, 0}, - 0x1ED5 = {18299, 2, 0}, 0x1ED6 = {18301, 2, 0}, 0x1ED7 = {18303, 2, 0}, 0x1EE0 = {18305, 2, 0}, 0x1EE1 = {18307, 2, 0}, 0x1EE2 = {18309, 2, 0}, 0x1EE3 = {18311, 2, 0}, 0x1EE4 = {18313, 2, 0}, 0x1EE5 = {18315, 2, 0}, 0x1EE6 = {18317, 2, 0}, 0x1EE7 = {18319, 2, 0}, 0x1EE8 = {18321, 2, 0}, 0x1EE9 = {18323, 2, 0}, 0x1EF0 = {18325, 2, 0}, 0x1EF1 = {18327, 2, 0}, 0x1EF2 = {18329, 2, 0}, - 0x1EF3 = {18331, 2, 0}, 0x1EF4 = {18333, 2, 0}, 0x1EF5 = {18335, 2, 0}, 0x1EF6 = {18337, 2, 0}, 0x1EF7 = {18339, 2, 0}, 0x1F00 = {18341, 4, 0}, 0x1F02 = {18345, 1, 0}, 0x1F03 = {18346, 3, 0}, 0x1F04 = {18349, 7, 0}, 0x1F05 = {18356, 2, 0}, 0x1F06 = {18358, 4, 0}, 0x1F07 = {18362, 5, 0}, 0x1F08 = {18367, 20, 0}, 0x1F09 = {18387, 4, 0}, 0x1F0A = {18391, 19, 0}, 0x1F0B = {18410, 4, 0}, - 0x1F0C = {18414, 4, 0}, 0x1F0D = {18418, 4, 0}, 0x1F0E = {18422, 2, 0}, 0x1F0F = {18424, 1, 0}, 0x1F12 = {18425, 4, 0}, 0x1F13 = {18429, 4, 0}, 0x1F14 = {18433, 3, 0}, 0x1F15 = {18436, 6, 0}, 0x1F16 = {18442, 8, 0}, 0x1F17 = {18450, 6, 0}, 0x1F18 = {18456, 11, 0}, 0x1F19 = {18467, 2, 0}, 0x1F1A = {18469, 9, 0}, 0x1F1B = {18478, 4, 0}, 0x1F1C = {18482, 4, 0}, 0x1F1D = {18486, 5, 0}, - 0x1F1E = {18491, 2, 0}, 0x1F1F = {18493, 3, 0}, 0x1F20 = {18496, 3, 0}, 0x1F22 = {18499, 1, 0}, 0x1F23 = {18500, 3, 0}, 0x1F25 = {18503, 3, 0}, 0x1F26 = {18506, 3, 0}, 0x1F27 = {18509, 5, 0}, 0x1F28 = {18514, 12, 0}, 0x1F2C = {18526, 1, 0}, 0x1F2D = {18527, 4, 0}, 0x1F2E = {18531, 3, 0}, 0x1F2F = {18534, 1, 0}, 0x1F32 = {18535, 3, 0}, 0x1F33 = {18538, 5, 0}, 0x1F34 = {18543, 1, 0}, - 0x1F35 = {18544, 2, 0}, 0x1F36 = {18546, 5, 0}, 0x1F37 = {18551, 5, 0}, 0x1F38 = {18556, 4, 0}, 0x1F3A = {18560, 7, 0}, 0x1F3B = {18567, 4, 0}, 0x1F3C = {18571, 4, 0}, 0x1F3F = {18575, 1, 0}, 0x1F40 = {18576, 1, 0}, 0x1F42 = {18577, 1, 0}, 0x1F43 = {18578, 3, 0}, 0x1F44 = {18581, 5, 0}, 0x1F45 = {18586, 3, 0}, 0x1F46 = {18589, 3, 0}, 0x1F47 = {18592, 1, 0}, 0x1F48 = {18593, 6, 0}, - 0x1F49 = {18599, 2, 0}, 0x1F4A = {18601, 1, 0}, 0x1F4B = {18602, 6, 0}, 0x1F4C = {18608, 4, 0}, 0x1F4D = {18612, 3, 0}, 0x1F4E = {18615, 4, 0}, 0x1F4F = {18619, 1, 0}, 0x1F52 = {18620, 3, 0}, 0x1F53 = {18623, 20, 0}, 0x1F54 = {18643, 1, 0}, 0x1F55 = {18644, 4, 0}, 0x1F56 = {18648, 10, 0}, 0x1F57 = {18658, 4, 0}, 0x1F5F = {18662, 3, 0}, 0x1F61 = {18665, 1, 0}, 0x1F63 = {18666, 1, 0}, - 0x1F65 = {18667, 2, 0}, 0x1F66 = {18669, 3, 0}, 0x1F67 = {18672, 3, 0}, 0x1F68 = {18675, 10, 0}, 0x1F6B = {18685, 8, 0}, 0x1F6C = {18693, 2, 0}, 0x1F6D = {18695, 2, 0}, 0x1F6E = {18697, 3, 0}, 0x1F72 = {18700, 3, 0}, 0x1F73 = {18703, 4, 0}, 0x1F74 = {18707, 1, 0}, 0x1F75 = {18708, 2, 0}, 0x1F76 = {18710, 5, 0}, 0x1F77 = {18715, 4, 0}, 0x1F7A = {18719, 4, 0}, 0x1F7C = {18723, 4, 0}, - 0x1F80 = {18727, 2, 0}, 0x1F82 = {18729, 1, 0}, 0x1F83 = {18730, 4, 0}, 0x1F85 = {18734, 1, 0}, 0x1F86 = {18735, 5, 0}, 0x1F87 = {18740, 4, 0}, 0x1F88 = {18744, 10, 0}, 0x1F89 = {18754, 6, 0}, 0x1F8A = {18760, 10, 0}, 0x1F8B = {18770, 6, 0}, 0x1F8C = {18776, 4, 0}, 0x1F8D = {18780, 4, 0}, 0x1F8E = {18784, 4, 0}, 0x1F90 = {18788, 3, 0}, 0x1F92 = {18791, 5, 0}, 0x1F93 = {18796, 6, 0}, - 0x1F94 = {18802, 2, 0}, 0x1F95 = {18804, 4, 0}, 0x1F96 = {18808, 6, 0}, 0x1F97 = {18814, 6, 0}, 0x1F98 = {18820, 6, 0}, 0x1F99 = {18826, 6, 0}, 0x1F9A = {18832, 5, 0}, 0x1F9B = {18837, 1, 0}, 0x1F9C = {18838, 3, 0}, 0x1F9D = {18841, 1, 0}, 0x1F9F = {18842, 3, 0}, 0x1FA0 = {18845, 1, 0}, 0x1FA2 = {18846, 1, 0}, 0x1FA3 = {18847, 4, 0}, 0x1FA5 = {18851, 3, 0}, 0x1FA6 = {18854, 6, 0}, - 0x1FA7 = {18860, 4, 0}, 0x1FA9 = {18864, 6, 0}, 0x1FAA = {18870, 1, 0}, 0x1FAB = {18871, 6, 0}, 0x1FAC = {18877, 1, 0}, 0x1FAD = {18878, 4, 0}, 0x1FAE = {18882, 4, 0}, 0x1FB1 = {18886, 3, 0}, 0x1FB2 = {18889, 4, 0}, 0x1FB3 = {18893, 4, 0}, 0x1FB5 = {18897, 2, 0}, 0x1FB6 = {18899, 6, 0}, 0x1FB7 = {18905, 5, 0}, 0x1FB8 = {18910, 6, 0}, 0x1FBA = {18916, 3, 0}, 0x1FBB = {18919, 1, 0}, - 0x1FBC = {18920, 5, 0}, 0x1FC0 = {18925, 2, 0}, 0x1FC2 = {18927, 1, 0}, 0x1FC3 = {18928, 5, 0}, 0x1FC5 = {18933, 3, 0}, 0x1FC6 = {18936, 8, 0}, 0x1FC7 = {18944, 2, 0}, 0x1FC8 = {18946, 10, 0}, 0x1FC9 = {18956, 6, 0}, 0x1FCA = {18962, 10, 0}, 0x1FCB = {18972, 6, 0}, 0x1FCC = {18978, 2, 0}, 0x1FCD = {18980, 3, 0}, 0x1FCE = {18983, 2, 0}, 0x1FCF = {18985, 1, 0}, 0x1FD2 = {18986, 5, 0}, - 0x1FD3 = {18991, 23, 0}, 0x1FD4 = {19014, 1, 0}, 0x1FD5 = {19015, 3, 0}, 0x1FD6 = {19018, 4, 0}, 0x1FD7 = {19022, 3, 0}, 0x1FD8 = {19025, 4, 0}, 0x1FD9 = {19029, 4, 0}, 0x1FDA = {19033, 2, 0}, 0x1FDB = {19035, 1, 0}, 0x1FDC = {19036, 3, 0}, 0x1FDF = {19039, 4, 0}, 0x1FE0 = {19043, 2, 0}, 0x1FE3 = {19045, 2, 0}, 0x1FE5 = {19047, 2, 0}, 0x1FE6 = {19049, 6, 0}, 0x1FE7 = {19055, 4, 0}, - 0x1FE8 = {19059, 14, 0}, 0x1FE9 = {19073, 12, 0}, 0x1FEA = {19085, 10, 0}, 0x1FEB = {19095, 16, 0}, 0x1FEC = {19111, 1, 0}, 0x1FED = {19112, 2, 0}, 0x1FEE = {19114, 7, 0}, 0x1FF2 = {19121, 5, 0}, 0x1FF3 = {19126, 3, 0}, 0x1FF5 = {19129, 1, 0}, 0x1FF6 = {19130, 9, 0}, 0x1FF7 = {19139, 2, 0}, 0x1FF8 = {19141, 4, 0}, 0x1FFA = {19145, 1, 0}, 0x1FFC = {19146, 2, 0}, 0x1FFF = {19148, 1, 0}, - 0x2000 = {19149, 5, 0}, 0x2001 = {19154, 5, 0}, 0x2002 = {19159, 5, 0}, 0x2003 = {19164, 5, 0}, 0x2004 = {19169, 5, 0}, 0x2005 = {19174, 5, 0}, 0x2006 = {19179, 5, 0}, 0x2007 = {19184, 5, 0}, 0x2008 = {19189, 5, 0}, 0x2009 = {19194, 5, 0}, 0x200A = {19199, 5, 0}, 0x200B = {19204, 5, 0}, 0x200C = {19209, 5, 0}, 0x200D = {19214, 5, 0}, 0x200E = {19219, 5, 0}, 0x200F = {19224, 5, 0}, - 0x2010 = {19229, 5, 0}, 0x2011 = {19234, 5, 0}, 0x2012 = {19239, 5, 0}, 0x2013 = {19244, 5, 0}, 0x2014 = {19249, 5, 0}, 0x2015 = {19254, 5, 0}, 0x2016 = {19259, 5, 0}, 0x2017 = {19264, 5, 0}, 0x2018 = {19269, 5, 0}, 0x2019 = {19274, 5, 0}, 0x201A = {19279, 5, 0}, 0x201B = {19284, 5, 0}, 0x201C = {19289, 5, 0}, 0x201D = {19294, 5, 0}, 0x201E = {19299, 5, 0}, 0x201F = {19304, 5, 0}, - 0x2020 = {19309, 5, 0}, 0x2021 = {19314, 5, 0}, 0x2022 = {19319, 5, 0}, 0x2023 = {19324, 5, 0}, 0x2024 = {19329, 5, 0}, 0x2025 = {19334, 5, 0}, 0x2026 = {19339, 5, 0}, 0x2027 = {19344, 5, 0}, 0x2028 = {19349, 5, 0}, 0x2029 = {19354, 5, 0}, 0x202A = {19359, 5, 0}, 0x202B = {19364, 5, 0}, 0x202C = {19369, 5, 0}, 0x202D = {19374, 5, 0}, 0x202E = {19379, 5, 0}, 0x202F = {19384, 5, 0}, - 0x2030 = {19389, 5, 0}, 0x2031 = {19394, 5, 0}, 0x2032 = {19399, 5, 0}, 0x2033 = {19404, 5, 0}, 0x2034 = {19409, 5, 0}, 0x2035 = {19414, 5, 0}, 0x2036 = {19419, 5, 0}, 0x2037 = {19424, 5, 0}, 0x2038 = {19429, 5, 0}, 0x2039 = {19434, 5, 0}, 0x203A = {19439, 5, 0}, 0x203B = {19444, 5, 0}, 0x203C = {19449, 5, 0}, 0x203D = {19454, 5, 0}, 0x203E = {19459, 5, 0}, 0x203F = {19464, 5, 0}, - 0x2040 = {19469, 5, 0}, 0x2041 = {19474, 5, 0}, 0x2042 = {19479, 5, 0}, 0x2043 = {19484, 5, 0}, 0x2044 = {19489, 5, 0}, 0x2045 = {19494, 5, 0}, 0x2046 = {19499, 5, 0}, 0x2047 = {19504, 5, 0}, 0x2048 = {19509, 5, 0}, 0x2049 = {19514, 5, 0}, 0x204A = {19519, 5, 0}, 0x204B = {19524, 5, 0}, 0x204C = {19529, 5, 0}, 0x204D = {19534, 5, 0}, 0x204E = {19539, 5, 0}, 0x204F = {19544, 5, 0}, - 0x2050 = {19549, 5, 0}, 0x2051 = {19554, 5, 0}, 0x2052 = {19559, 5, 0}, 0x2053 = {19564, 5, 0}, 0x2054 = {19569, 5, 0}, 0x2055 = {19574, 5, 0}, 0x2056 = {19579, 5, 0}, 0x2057 = {19584, 5, 0}, 0x2058 = {19589, 5, 0}, 0x2059 = {19594, 5, 0}, 0x205A = {19599, 5, 0}, 0x205B = {19604, 5, 0}, 0x205C = {19609, 5, 0}, 0x205D = {19614, 5, 0}, 0x205E = {19619, 5, 0}, 0x205F = {19624, 5, 0}, - 0x2060 = {19629, 5, 0}, 0x2061 = {19634, 5, 0}, 0x2062 = {19639, 5, 0}, 0x2063 = {19644, 5, 0}, 0x2064 = {19649, 5, 0}, 0x2065 = {19654, 5, 0}, 0x2066 = {19659, 5, 0}, 0x2067 = {19664, 5, 0}, 0x2068 = {19669, 5, 0}, 0x2069 = {19674, 5, 0}, 0x206A = {19679, 5, 0}, 0x206B = {19684, 5, 0}, 0x206C = {19689, 5, 0}, 0x206D = {19694, 5, 0}, 0x206E = {19699, 5, 0}, 0x206F = {19704, 5, 0}, - 0x2070 = {19709, 5, 0}, 0x2071 = {19714, 5, 0}, 0x2072 = {19719, 5, 0}, 0x2073 = {19724, 5, 0}, 0x2074 = {19729, 5, 0}, 0x2075 = {19734, 5, 0}, 0x2076 = {19739, 5, 0}, 0x2077 = {19744, 5, 0}, 0x2078 = {19749, 5, 0}, 0x2079 = {19754, 5, 0}, 0x207A = {19759, 5, 0}, 0x207B = {19764, 5, 0}, 0x207C = {19769, 5, 0}, 0x207D = {19774, 5, 0}, 0x207E = {19779, 5, 0}, 0x207F = {19784, 5, 0}, - 0x2080 = {19789, 5, 0}, 0x2081 = {19794, 5, 0}, 0x2082 = {19799, 5, 0}, 0x2083 = {19804, 5, 0}, 0x2084 = {19809, 5, 0}, 0x2085 = {19814, 5, 0}, 0x2086 = {19819, 5, 0}, 0x2087 = {19824, 5, 0}, 0x2088 = {19829, 5, 0}, 0x2089 = {19834, 5, 0}, 0x208A = {19839, 5, 0}, 0x208B = {19844, 5, 0}, 0x208C = {19849, 5, 0}, 0x208D = {19854, 5, 0}, 0x208E = {19859, 5, 0}, 0x208F = {19864, 5, 0}, - 0x2090 = {19869, 5, 0}, 0x2091 = {19874, 5, 0}, 0x2092 = {19879, 5, 0}, 0x2093 = {19884, 5, 0}, 0x2094 = {19889, 5, 0}, 0x2095 = {19894, 5, 0}, 0x2096 = {19899, 5, 0}, 0x2097 = {19904, 5, 0}, 0x2098 = {19909, 5, 0}, 0x2099 = {19914, 5, 0}, 0x209A = {19919, 5, 0}, 0x209B = {19924, 5, 0}, 0x209C = {19929, 5, 0}, 0x209D = {19934, 5, 0}, 0x209E = {19939, 5, 0}, 0x209F = {19944, 5, 0}, - 0x20A0 = {19949, 5, 0}, 0x20A1 = {19954, 5, 0}, 0x20A2 = {19959, 5, 0}, 0x20A3 = {19964, 5, 0}, 0x20A4 = {19969, 5, 0}, 0x20A5 = {19974, 5, 0}, 0x20A6 = {19979, 5, 0}, 0x20A7 = {19984, 5, 0}, 0x20A8 = {19989, 5, 0}, 0x20A9 = {19994, 5, 0}, 0x20AA = {19999, 5, 0}, 0x20AB = {20004, 5, 0}, 0x20AC = {20009, 5, 0}, 0x20AD = {20014, 5, 0}, 0x20AE = {20019, 5, 0}, 0x20AF = {20024, 5, 0}, - 0x20B0 = {20029, 5, 0}, 0x20B1 = {20034, 5, 0}, 0x20B2 = {20039, 5, 0}, 0x20B3 = {20044, 5, 0}, 0x20B4 = {20049, 5, 0}, 0x20B5 = {20054, 5, 0}, 0x20B6 = {20059, 5, 0}, 0x20B7 = {20064, 5, 0}, 0x20B8 = {20069, 5, 0}, 0x20B9 = {20074, 5, 0}, 0x20BA = {20079, 5, 0}, 0x20BB = {20084, 5, 0}, 0x20BC = {20089, 5, 0}, 0x20BD = {20094, 5, 0}, 0x20BE = {20099, 5, 0}, 0x20BF = {20104, 5, 0}, - 0x20C0 = {20109, 5, 0}, 0x20C1 = {20114, 5, 0}, 0x20C2 = {20119, 5, 0}, 0x20C3 = {20124, 5, 0}, 0x20C4 = {20129, 5, 0}, 0x20C5 = {20134, 5, 0}, 0x20C6 = {20139, 5, 0}, 0x20C7 = {20144, 5, 0}, 0x20C8 = {20149, 5, 0}, 0x20C9 = {20154, 5, 0}, 0x20CA = {20159, 5, 0}, 0x20CB = {20164, 5, 0}, 0x20CC = {20169, 5, 0}, 0x20CD = {20174, 5, 0}, 0x20CE = {20179, 5, 0}, 0x20CF = {20184, 5, 0}, - 0x20D0 = {20189, 5, 0}, 0x20D1 = {20194, 5, 0}, 0x20D2 = {20199, 5, 0}, 0x20D3 = {20204, 5, 0}, 0x20D4 = {20209, 5, 0}, 0x20D5 = {20214, 5, 0}, 0x20D6 = {20219, 5, 0}, 0x20D7 = {20224, 5, 0}, 0x20D8 = {20229, 5, 0}, 0x20D9 = {20234, 5, 0}, 0x20DA = {20239, 5, 0}, 0x20DB = {20244, 5, 0}, 0x20DC = {20249, 5, 0}, 0x20DD = {20254, 5, 0}, 0x20DE = {20259, 5, 0}, 0x20DF = {20264, 5, 0}, - 0x20E0 = {20269, 5, 0}, 0x20E1 = {20274, 5, 0}, 0x20E2 = {20279, 5, 0}, 0x20E3 = {20284, 5, 0}, 0x20E4 = {20289, 5, 0}, 0x20E5 = {20294, 5, 0}, 0x20E6 = {20299, 5, 0}, 0x20E7 = {20304, 5, 0}, 0x20E8 = {20309, 5, 0}, 0x20E9 = {20314, 5, 0}, 0x20EA = {20319, 5, 0}, 0x20EB = {20324, 5, 0}, 0x20EC = {20329, 5, 0}, 0x20ED = {20334, 5, 0}, 0x20EE = {20339, 5, 0}, 0x20EF = {20344, 5, 0}, - 0x20F0 = {20349, 5, 0}, 0x20F1 = {20354, 5, 0}, 0x20F2 = {20359, 5, 0}, 0x20F3 = {20364, 5, 0}, 0x20F4 = {20369, 5, 0}, 0x20F5 = {20374, 5, 0}, 0x20F6 = {20379, 5, 0}, 0x20F7 = {20384, 5, 0}, 0x20F8 = {20389, 5, 0}, 0x20F9 = {20394, 5, 0}, 0x20FA = {20399, 5, 0}, 0x20FB = {20404, 5, 0}, 0x20FC = {20409, 5, 0}, 0x20FD = {20414, 5, 0}, 0x20FE = {20419, 5, 0}, 0x20FF = {20424, 5, 0}, - 0x2100 = {20429, 2, 0}, 0x2101 = {20431, 1, 0}, 0x2102 = {20432, 1, 0}, 0x2103 = {20433, 1, 0}, 0x2104 = {20434, 1, 0}, 0x2105 = {20435, 1, 0}, 0x2106 = {20436, 1, 0}, 0x2107 = {20437, 1, 0}, 0x2108 = {20438, 1, 0}, 0x2109 = {20439, 1, 0}, 0x210A = {20440, 1, 0}, 0x210B = {20441, 1, 0}, 0x210C = {20442, 1, 0}, 0x210D = {20443, 1, 0}, 0x210E = {20444, 1, 0}, 0x210F = {20445, 1, 0}, - 0x2110 = {20446, 1, 0}, 0x2111 = {20447, 1, 0}, 0x2112 = {20448, 1, 0}, 0x2113 = {20449, 1, 0}, 0x2114 = {20450, 1, 0}, 0x2115 = {20451, 1, 0}, 0x2116 = {20452, 1, 0}, 0x2117 = {20453, 1, 0}, 0x2118 = {20454, 1, 0}, 0x2119 = {20455, 1, 0}, 0x211A = {20456, 1, 0}, 0x211B = {20457, 1, 0}, 0x211C = {20458, 1, 0}, 0x211D = {20459, 1, 0}, 0x211E = {20460, 1, 0}, 0x211F = {20461, 1, 0}, - 0x2120 = {20462, 1, 0}, 0x2121 = {20463, 1, 0}, 0x2122 = {20464, 1, 0}, 0x2123 = {20465, 1, 0}, 0x2124 = {20466, 1, 0}, 0x2125 = {20467, 1, 0}, 0x2126 = {20468, 1, 0}, 0x2127 = {20469, 1, 0}, 0x2128 = {20470, 1, 0}, 0x2129 = {20471, 1, 0}, 0x212A = {20472, 1, 0}, 0x212B = {20473, 1, 0}, 0x212C = {20474, 1, 0}, 0x212D = {20475, 1, 0}, 0x212E = {20476, 1, 0}, 0x212F = {20477, 1, 0}, - 0x2130 = {20478, 1, 0}, 0x2131 = {20479, 1, 0}, 0x2132 = {20480, 1, 0}, 0x2133 = {20481, 1, 0}, 0x2134 = {20482, 1, 0}, 0x2135 = {20483, 1, 0}, 0x2136 = {20484, 1, 0}, 0x2137 = {20485, 1, 0}, 0x2138 = {20486, 1, 0}, 0x2139 = {20487, 1, 0}, 0x213A = {20488, 1, 0}, 0x213B = {20489, 1, 0}, 0x213C = {20490, 1, 0}, 0x213D = {20491, 1, 0}, 0x213E = {20492, 1, 0}, 0x213F = {20493, 1, 0}, - 0x2140 = {20494, 1, 0}, 0x2141 = {20495, 1, 0}, 0x2142 = {20496, 1, 0}, 0x2143 = {20497, 1, 0}, 0x2144 = {20498, 1, 0}, 0x2145 = {20499, 1, 0}, 0x2146 = {20500, 1, 0}, 0x2147 = {20501, 1, 0}, 0x2148 = {20502, 1, 0}, 0x2149 = {20503, 1, 0}, 0x214A = {20504, 1, 0}, 0x214B = {20505, 1, 0}, 0x214C = {20506, 1, 0}, 0x214D = {20507, 1, 0}, 0x214E = {20508, 1, 0}, 0x214F = {20509, 1, 0}, - 0x2150 = {20510, 1, 0}, 0x2151 = {20511, 1, 0}, 0x2152 = {20512, 1, 0}, 0x2153 = {20513, 1, 0}, 0x2154 = {20514, 1, 0}, 0x2155 = {20515, 1, 0}, 0x2156 = {20516, 1, 0}, 0x2157 = {20517, 1, 0}, 0x2158 = {20518, 1, 0}, 0x2159 = {20519, 1, 0}, 0x215A = {20520, 1, 0}, 0x215B = {20521, 1, 0}, 0x215C = {20522, 1, 0}, 0x215D = {20523, 1, 0}, 0x215E = {20524, 1, 0}, 0x215F = {20525, 1, 0}, - 0x2160 = {20526, 1, 0}, 0x2161 = {20527, 1, 0}, 0x2162 = {20528, 1, 0}, 0x2163 = {20529, 1, 0}, 0x2164 = {20530, 1, 0}, 0x2165 = {20531, 1, 0}, 0x2166 = {20532, 1, 0}, 0x2167 = {20533, 1, 0}, 0x2168 = {20534, 1, 0}, 0x2169 = {20535, 1, 0}, 0x216A = {20536, 1, 0}, 0x216B = {20537, 1, 0}, 0x216C = {20538, 1, 0}, 0x216D = {20539, 1, 0}, 0x216E = {20540, 1, 0}, 0x216F = {20541, 1, 0}, - 0x2170 = {20542, 1, 0}, 0x2171 = {20543, 1, 0}, 0x2172 = {20544, 1, 0}, 0x2173 = {20545, 1, 0}, 0x2174 = {20546, 1, 0}, 0x2175 = {20547, 1, 0}, 0x2176 = {20548, 1, 0}, 0x2177 = {20549, 1, 0}, 0x2178 = {20550, 1, 0}, 0x2179 = {20551, 1, 0}, 0x217A = {20552, 1, 0}, 0x217B = {20553, 1, 0}, 0x217C = {20554, 1, 0}, 0x217D = {20555, 1, 0}, 0x217E = {20556, 1, 0}, 0x217F = {20557, 1, 0}, - 0x2180 = {20558, 2, 0}, 0x2181 = {20560, 1, 0}, 0x2182 = {20561, 1, 0}, 0x2183 = {20562, 1, 0}, 0x2184 = {20563, 1, 0}, 0x2185 = {20564, 1, 0}, 0x2186 = {20565, 1, 0}, 0x2187 = {20566, 1, 0}, 0x2188 = {20567, 2, 0}, 0x2189 = {20569, 1, 0}, 0x218A = {20570, 1, 0}, 0x218B = {20571, 1, 0}, 0x218C = {20572, 1, 0}, 0x218D = {20573, 1, 0}, 0x218E = {20574, 1, 0}, 0x218F = {20575, 1, 0}, - 0x2190 = {20576, 2, 0}, 0x2191 = {20578, 1, 0}, 0x2192 = {20579, 1, 0}, 0x2193 = {20580, 1, 0}, 0x2194 = {20581, 1, 0}, 0x2195 = {20582, 1, 0}, 0x2196 = {20583, 1, 0}, 0x2197 = {20584, 1, 0}, 0x2198 = {20585, 2, 0}, 0x2199 = {20587, 1, 0}, 0x219A = {20588, 1, 0}, 0x219B = {20589, 1, 0}, 0x219C = {20590, 1, 0}, 0x219D = {20591, 1, 0}, 0x219E = {20592, 1, 0}, 0x219F = {20593, 1, 0}, - 0x21A0 = {20594, 1, 0}, 0x21A1 = {20595, 1, 0}, 0x21A2 = {20596, 1, 0}, 0x21A3 = {20597, 1, 0}, 0x21A4 = {20598, 1, 0}, 0x21A5 = {20599, 1, 0}, 0x21A6 = {20600, 1, 0}, 0x21A7 = {20601, 1, 0}, 0x21A8 = {20602, 1, 0}, 0x21A9 = {20603, 1, 0}, 0x21AA = {20604, 1, 0}, 0x21AB = {20605, 1, 0}, 0x21AC = {20606, 1, 0}, 0x21AD = {20607, 1, 0}, 0x21AE = {20608, 1, 0}, 0x21AF = {20609, 1, 0}, - 0x21B0 = {20610, 1, 0}, 0x21B1 = {20611, 1, 0}, 0x21B2 = {20612, 1, 0}, 0x21B3 = {20613, 1, 0}, 0x21B4 = {20614, 1, 0}, 0x21B5 = {20615, 1, 0}, 0x21B6 = {20616, 1, 0}, 0x21B7 = {20617, 1, 0}, 0x21B8 = {20618, 1, 0}, 0x21B9 = {20619, 1, 0}, 0x21BA = {20620, 1, 0}, 0x21BB = {20621, 1, 0}, 0x21BC = {20622, 1, 0}, 0x21BD = {20623, 1, 0}, 0x21BE = {20624, 1, 0}, 0x21BF = {20625, 1, 0}, - 0x21C0 = {20626, 1, 0}, 0x21C1 = {20627, 1, 0}, 0x21C2 = {20628, 1, 0}, 0x21C3 = {20629, 1, 0}, 0x21C4 = {20630, 1, 0}, 0x21C5 = {20631, 1, 0}, 0x21C6 = {20632, 1, 0}, 0x21C7 = {20633, 1, 0}, 0x21C8 = {20634, 1, 0}, 0x21C9 = {20635, 1, 0}, 0x21CA = {20636, 1, 0}, 0x21CB = {20637, 1, 0}, 0x21CC = {20638, 1, 0}, 0x21CD = {20639, 1, 0}, 0x21CE = {20640, 1, 0}, 0x21CF = {20641, 1, 0}, - 0x21D0 = {20642, 1, 0}, 0x21D1 = {20643, 1, 0}, 0x21D2 = {20644, 1, 0}, 0x21D3 = {20645, 1, 0}, 0x21D4 = {20646, 1, 0}, 0x21D5 = {20647, 1, 0}, 0x21D6 = {20648, 1, 0}, 0x21D7 = {20649, 1, 0}, 0x21D8 = {20650, 1, 0}, 0x21D9 = {20651, 1, 0}, 0x21DA = {20652, 1, 0}, 0x21DB = {20653, 1, 0}, 0x21DC = {20654, 1, 0}, 0x21DD = {20655, 1, 0}, 0x21DE = {20656, 1, 0}, 0x21DF = {20657, 1, 0}, - 0x21E0 = {20658, 1, 0}, 0x21E1 = {20659, 1, 0}, 0x21E2 = {20660, 1, 0}, 0x21E3 = {20661, 1, 0}, 0x21E4 = {20662, 1, 0}, 0x21E5 = {20663, 1, 0}, 0x21E6 = {20664, 1, 0}, 0x21E7 = {20665, 1, 0}, 0x21E8 = {20666, 1, 0}, 0x21E9 = {20667, 1, 0}, 0x21EA = {20668, 1, 0}, 0x21EB = {20669, 1, 0}, 0x21EC = {20670, 1, 0}, 0x21ED = {20671, 1, 0}, 0x21EE = {20672, 1, 0}, 0x21EF = {20673, 1, 0}, - 0x21F0 = {20674, 1, 0}, 0x21F1 = {20675, 1, 0}, 0x21F2 = {20676, 1, 0}, 0x21F3 = {20677, 1, 0}, 0x21F4 = {20678, 1, 0}, 0x21F5 = {20679, 1, 0}, 0x21F6 = {20680, 1, 0}, 0x21F7 = {20681, 1, 0}, 0x21F8 = {20682, 1, 0}, 0x21F9 = {20683, 1, 0}, 0x21FA = {20684, 1, 0}, 0x21FB = {20685, 1, 0}, 0x21FC = {20686, 1, 0}, 0x21FD = {20687, 1, 0}, 0x21FE = {20688, 1, 0}, 0x21FF = {20689, 1, 0}, - 0x2200 = {20690, 2, 0}, 0x2201 = {20692, 2, 0}, 0x2202 = {20694, 2, 0}, 0x2203 = {20696, 2, 0}, 0x2204 = {20698, 2, 0}, 0x2205 = {20700, 2, 0}, 0x2206 = {20702, 2, 0}, 0x2207 = {20704, 2, 0}, 0x2208 = {20706, 2, 0}, 0x2209 = {20708, 2, 0}, 0x220A = {20710, 2, 0}, 0x220B = {20712, 2, 0}, 0x220C = {20714, 2, 0}, 0x220D = {20716, 2, 0}, 0x220E = {20718, 2, 0}, 0x220F = {20720, 2, 0}, - 0x2210 = {20722, 2, 0}, 0x2211 = {20724, 2, 0}, 0x2212 = {20726, 2, 0}, 0x2213 = {20728, 2, 0}, 0x2214 = {20730, 2, 0}, 0x2215 = {20732, 2, 0}, 0x2216 = {20734, 2, 0}, 0x2217 = {20736, 2, 0}, 0x2218 = {20738, 2, 0}, 0x2219 = {20740, 2, 0}, 0x221A = {20742, 2, 0}, 0x221B = {20744, 2, 0}, 0x221C = {20746, 2, 0}, 0x221D = {20748, 2, 0}, 0x221E = {20750, 2, 0}, 0x221F = {20752, 2, 0}, - 0x2220 = {20754, 2, 0}, 0x2221 = {20756, 2, 0}, 0x2222 = {20758, 2, 0}, 0x2223 = {20760, 2, 0}, 0x2224 = {20762, 2, 0}, 0x2225 = {20764, 2, 0}, 0x2226 = {20766, 2, 0}, 0x2227 = {20768, 2, 0}, 0x2228 = {20770, 2, 0}, 0x2229 = {20772, 2, 0}, 0x222A = {20774, 2, 0}, 0x222B = {20776, 2, 0}, 0x222C = {20778, 2, 0}, 0x222D = {20780, 2, 0}, 0x222E = {20782, 2, 0}, 0x222F = {20784, 2, 0}, - 0x2230 = {20786, 2, 0}, 0x2231 = {20788, 2, 0}, 0x2232 = {20790, 2, 0}, 0x2233 = {20792, 2, 0}, 0x2234 = {20794, 2, 0}, 0x2235 = {20796, 2, 0}, 0x2236 = {20798, 2, 0}, 0x2237 = {20800, 2, 0}, 0x2238 = {20802, 2, 0}, 0x2239 = {20804, 2, 0}, 0x223A = {20806, 2, 0}, 0x223B = {20808, 2, 0}, 0x223C = {20810, 2, 0}, 0x223D = {20812, 2, 0}, 0x223E = {20814, 2, 0}, 0x223F = {20816, 2, 0}, - 0x2240 = {20818, 2, 0}, 0x2241 = {20820, 2, 0}, 0x2242 = {20822, 2, 0}, 0x2243 = {20824, 2, 0}, 0x2244 = {20826, 2, 0}, 0x2245 = {20828, 2, 0}, 0x2246 = {20830, 2, 0}, 0x2247 = {20832, 2, 0}, 0x2248 = {20834, 2, 0}, 0x2249 = {20836, 2, 0}, 0x224A = {20838, 2, 0}, 0x224B = {20840, 2, 0}, 0x224C = {20842, 2, 0}, 0x224D = {20844, 2, 0}, 0x224E = {20846, 2, 0}, 0x224F = {20848, 2, 0}, - 0x2250 = {20850, 2, 0}, 0x2251 = {20852, 2, 0}, 0x2252 = {20854, 2, 0}, 0x2253 = {20856, 2, 0}, 0x2254 = {20858, 2, 0}, 0x2255 = {20860, 2, 0}, 0x2256 = {20862, 2, 0}, 0x2257 = {20864, 2, 0}, 0x2258 = {20866, 2, 0}, 0x2259 = {20868, 2, 0}, 0x225A = {20870, 2, 0}, 0x225B = {20872, 2, 0}, 0x225C = {20874, 2, 0}, 0x225D = {20876, 2, 0}, 0x225E = {20878, 2, 0}, 0x225F = {20880, 2, 0}, - 0x2260 = {20882, 2, 0}, 0x2261 = {20884, 2, 0}, 0x2262 = {20886, 2, 0}, 0x2263 = {20888, 2, 0}, 0x2264 = {20890, 2, 0}, 0x2265 = {20892, 2, 0}, 0x2266 = {20894, 2, 0}, 0x2267 = {20896, 2, 0}, 0x2268 = {20898, 2, 0}, 0x2269 = {20900, 2, 0}, 0x226A = {20902, 2, 0}, 0x226B = {20904, 2, 0}, 0x226C = {20906, 2, 0}, 0x226D = {20908, 2, 0}, 0x226E = {20910, 2, 0}, 0x226F = {20912, 2, 0}, - 0x2270 = {20914, 2, 0}, 0x2271 = {20916, 2, 0}, 0x2272 = {20918, 2, 0}, 0x2273 = {20920, 2, 0}, 0x2274 = {20922, 2, 0}, 0x2275 = {20924, 2, 0}, 0x2276 = {20926, 2, 0}, 0x2277 = {20928, 2, 0}, 0x2278 = {20930, 2, 0}, 0x2279 = {20932, 2, 0}, 0x227A = {20934, 2, 0}, 0x227B = {20936, 2, 0}, 0x227C = {20938, 2, 0}, 0x227D = {20940, 2, 0}, 0x227E = {20942, 2, 0}, 0x227F = {20944, 2, 0}, - 0x2280 = {20946, 3, 0}, 0x2281 = {20949, 2, 0}, 0x2282 = {20951, 2, 0}, 0x2283 = {20953, 2, 0}, 0x2284 = {20955, 2, 0}, 0x2285 = {20957, 2, 0}, 0x2286 = {20959, 2, 0}, 0x2287 = {20961, 2, 0}, 0x2288 = {20963, 3, 0}, 0x2289 = {20966, 2, 0}, 0x228A = {20968, 2, 0}, 0x228B = {20970, 2, 0}, 0x228C = {20972, 2, 0}, 0x228D = {20974, 2, 0}, 0x228E = {20976, 2, 0}, 0x228F = {20978, 2, 0}, - 0x2290 = {20980, 2, 0}, 0x2291 = {20982, 2, 0}, 0x2292 = {20984, 2, 0}, 0x2293 = {20986, 2, 0}, 0x2294 = {20988, 2, 0}, 0x2295 = {20990, 2, 0}, 0x2296 = {20992, 2, 0}, 0x2297 = {20994, 2, 0}, 0x2298 = {20996, 2, 0}, 0x2299 = {20998, 2, 0}, 0x229A = {21000, 2, 0}, 0x229B = {21002, 2, 0}, 0x229C = {21004, 2, 0}, 0x229D = {21006, 2, 0}, 0x229E = {21008, 2, 0}, 0x229F = {21010, 2, 0}, - 0x22A0 = {21012, 2, 0}, 0x22A1 = {21014, 2, 0}, 0x22A2 = {21016, 2, 0}, 0x22A3 = {21018, 2, 0}, 0x22A4 = {21020, 2, 0}, 0x22A5 = {21022, 2, 0}, 0x22A6 = {21024, 2, 0}, 0x22A7 = {21026, 2, 0}, 0x22A8 = {21028, 2, 0}, 0x22A9 = {21030, 2, 0}, 0x22AA = {21032, 2, 0}, 0x22AB = {21034, 2, 0}, 0x22AC = {21036, 2, 0}, 0x22AD = {21038, 2, 0}, 0x22AE = {21040, 2, 0}, 0x22AF = {21042, 2, 0}, - 0x22B0 = {21044, 2, 0}, 0x22B1 = {21046, 2, 0}, 0x22B2 = {21048, 2, 0}, 0x22B3 = {21050, 2, 0}, 0x22B4 = {21052, 2, 0}, 0x22B5 = {21054, 2, 0}, 0x22B6 = {21056, 2, 0}, 0x22B7 = {21058, 2, 0}, 0x22B8 = {21060, 2, 0}, 0x22B9 = {21062, 2, 0}, 0x22BA = {21064, 2, 0}, 0x22BB = {21066, 2, 0}, 0x22BC = {21068, 2, 0}, 0x22BD = {21070, 2, 0}, 0x22BE = {21072, 2, 0}, 0x22BF = {21074, 2, 0}, - 0x22C0 = {21076, 2, 0}, 0x22C1 = {21078, 2, 0}, 0x22C2 = {21080, 2, 0}, 0x22C3 = {21082, 2, 0}, 0x22C4 = {21084, 2, 0}, 0x22C5 = {21086, 2, 0}, 0x22C6 = {21088, 2, 0}, 0x22C7 = {21090, 2, 0}, 0x22C8 = {21092, 2, 0}, 0x22C9 = {21094, 2, 0}, 0x22CA = {21096, 2, 0}, 0x22CB = {21098, 2, 0}, 0x22CC = {21100, 2, 0}, 0x22CD = {21102, 2, 0}, 0x22CE = {21104, 2, 0}, 0x22CF = {21106, 2, 0}, - 0x22D0 = {21108, 2, 0}, 0x22D1 = {21110, 2, 0}, 0x22D2 = {21112, 2, 0}, 0x22D3 = {21114, 2, 0}, 0x22D4 = {21116, 2, 0}, 0x22D5 = {21118, 2, 0}, 0x22D6 = {21120, 2, 0}, 0x22D7 = {21122, 2, 0}, 0x22D8 = {21124, 2, 0}, 0x22D9 = {21126, 2, 0}, 0x22DA = {21128, 2, 0}, 0x22DB = {21130, 2, 0}, 0x22DC = {21132, 2, 0}, 0x22DD = {21134, 2, 0}, 0x22DE = {21136, 2, 0}, 0x22DF = {21138, 2, 0}, - 0x22E0 = {21140, 2, 0}, 0x22E1 = {21142, 2, 0}, 0x22E2 = {21144, 2, 0}, 0x22E3 = {21146, 2, 0}, 0x22E4 = {21148, 2, 0}, 0x22E5 = {21150, 2, 0}, 0x22E6 = {21152, 2, 0}, 0x22E7 = {21154, 2, 0}, 0x22E8 = {21156, 2, 0}, 0x22E9 = {21158, 2, 0}, 0x22EA = {21160, 2, 0}, 0x22EB = {21162, 2, 0}, 0x22EC = {21164, 2, 0}, 0x22ED = {21166, 2, 0}, 0x22EE = {21168, 2, 0}, 0x22EF = {21170, 2, 0}, - 0x22F0 = {21172, 2, 0}, 0x22F1 = {21174, 2, 0}, 0x22F2 = {21176, 2, 0}, 0x22F3 = {21178, 2, 0}, 0x22F4 = {21180, 2, 0}, 0x22F5 = {21182, 2, 0}, 0x22F6 = {21184, 2, 0}, 0x22F7 = {21186, 2, 0}, 0x22F8 = {21188, 2, 0}, 0x22F9 = {21190, 2, 0}, 0x22FA = {21192, 2, 0}, 0x22FB = {21194, 2, 0}, 0x22FC = {21196, 2, 0}, 0x22FD = {21198, 2, 0}, 0x22FE = {21200, 2, 0}, 0x22FF = {21202, 2, 0}, - 0x2300 = {21204, 1, 0}, 0x2301 = {21205, 1, 0}, 0x2302 = {21206, 1, 0}, 0x2303 = {21207, 1, 0}, 0x2304 = {21208, 1, 0}, 0x2305 = {21209, 1, 0}, 0x2306 = {21210, 1, 0}, 0x2307 = {21211, 1, 0}, 0x2308 = {21212, 1, 0}, 0x2309 = {21213, 1, 0}, 0x230A = {21214, 1, 0}, 0x230B = {21215, 1, 0}, 0x230C = {21216, 1, 0}, 0x230D = {21217, 1, 0}, 0x230E = {21218, 1, 0}, 0x230F = {21219, 1, 0}, - 0x2310 = {21220, 1, 0}, 0x2311 = {21221, 1, 0}, 0x2312 = {21222, 1, 0}, 0x2313 = {21223, 1, 0}, 0x2314 = {21224, 1, 0}, 0x2315 = {21225, 1, 0}, 0x2316 = {21226, 1, 0}, 0x2317 = {21227, 1, 0}, 0x2318 = {21228, 1, 0}, 0x2319 = {21229, 1, 0}, 0x231A = {21230, 1, 0}, 0x231B = {21231, 1, 0}, 0x231C = {21232, 1, 0}, 0x231D = {21233, 1, 0}, 0x231E = {21234, 1, 0}, 0x231F = {21235, 1, 0}, - 0x2320 = {21236, 1, 0}, 0x2321 = {21237, 1, 0}, 0x2322 = {21238, 1, 0}, 0x2323 = {21239, 1, 0}, 0x2324 = {21240, 1, 0}, 0x2325 = {21241, 1, 0}, 0x2326 = {21242, 1, 0}, 0x2327 = {21243, 1, 0}, 0x2328 = {21244, 1, 0}, 0x2329 = {21245, 1, 0}, 0x232A = {21246, 1, 0}, 0x232B = {21247, 1, 0}, 0x232C = {21248, 1, 0}, 0x232D = {21249, 1, 0}, 0x232E = {21250, 1, 0}, 0x232F = {21251, 1, 0}, - 0x2330 = {21252, 1, 0}, 0x2331 = {21253, 1, 0}, 0x2332 = {21254, 1, 0}, 0x2333 = {21255, 1, 0}, 0x2334 = {21256, 1, 0}, 0x2335 = {21257, 1, 0}, 0x2336 = {21258, 1, 0}, 0x2337 = {21259, 1, 0}, 0x2338 = {21260, 1, 0}, 0x2339 = {21261, 1, 0}, 0x233A = {21262, 1, 0}, 0x233B = {21263, 1, 0}, 0x233C = {21264, 1, 0}, 0x233D = {21265, 1, 0}, 0x233E = {21266, 1, 0}, 0x233F = {21267, 1, 0}, - 0x2340 = {21268, 1, 0}, 0x2341 = {21269, 1, 0}, 0x2342 = {21270, 1, 0}, 0x2343 = {21271, 1, 0}, 0x2344 = {21272, 1, 0}, 0x2345 = {21273, 1, 0}, 0x2346 = {21274, 1, 0}, 0x2347 = {21275, 1, 0}, 0x2348 = {21276, 1, 0}, 0x2349 = {21277, 1, 0}, 0x234A = {21278, 1, 0}, 0x234B = {21279, 1, 0}, 0x234C = {21280, 1, 0}, 0x234D = {21281, 1, 0}, 0x234E = {21282, 1, 0}, 0x234F = {21283, 1, 0}, - 0x2350 = {21284, 1, 0}, 0x2351 = {21285, 1, 0}, 0x2352 = {21286, 1, 0}, 0x2353 = {21287, 1, 0}, 0x2354 = {21288, 1, 0}, 0x2355 = {21289, 1, 0}, 0x2356 = {21290, 1, 0}, 0x2357 = {21291, 1, 0}, 0x2358 = {21292, 1, 0}, 0x2359 = {21293, 1, 0}, 0x235A = {21294, 1, 0}, 0x235B = {21295, 1, 0}, 0x235C = {21296, 1, 0}, 0x235D = {21297, 1, 0}, 0x235E = {21298, 1, 0}, 0x235F = {21299, 1, 0}, - 0x2360 = {21300, 1, 0}, 0x2361 = {21301, 1, 0}, 0x2362 = {21302, 1, 0}, 0x2363 = {21303, 1, 0}, 0x2364 = {21304, 1, 0}, 0x2365 = {21305, 1, 0}, 0x2366 = {21306, 1, 0}, 0x2367 = {21307, 1, 0}, 0x2368 = {21308, 1, 0}, 0x2369 = {21309, 1, 0}, 0x236A = {21310, 1, 0}, 0x236B = {21311, 1, 0}, 0x236C = {21312, 1, 0}, 0x236D = {21313, 1, 0}, 0x236E = {21314, 1, 0}, 0x236F = {21315, 1, 0}, - 0x2370 = {21316, 1, 0}, 0x2371 = {21317, 1, 0}, 0x2372 = {21318, 1, 0}, 0x2373 = {21319, 1, 0}, 0x2374 = {21320, 1, 0}, 0x2375 = {21321, 1, 0}, 0x2376 = {21322, 1, 0}, 0x2377 = {21323, 1, 0}, 0x2378 = {21324, 1, 0}, 0x2379 = {21325, 1, 0}, 0x237A = {21326, 1, 0}, 0x237B = {21327, 1, 0}, 0x237C = {21328, 1, 0}, 0x237D = {21329, 1, 0}, 0x237E = {21330, 1, 0}, 0x237F = {21331, 1, 0}, - 0x2380 = {21332, 1, 0}, 0x2381 = {21333, 1, 0}, 0x2382 = {21334, 1, 0}, 0x2383 = {21335, 1, 0}, 0x2384 = {21336, 1, 0}, 0x2385 = {21337, 1, 0}, 0x2386 = {21338, 1, 0}, 0x2387 = {21339, 1, 0}, 0x2388 = {21340, 1, 0}, 0x2389 = {21341, 1, 0}, 0x238A = {21342, 1, 0}, 0x238B = {21343, 1, 0}, 0x238C = {21344, 1, 0}, 0x238D = {21345, 1, 0}, 0x238E = {21346, 1, 0}, 0x238F = {21347, 1, 0}, - 0x2390 = {21348, 1, 0}, 0x2391 = {21349, 1, 0}, 0x2392 = {21350, 1, 0}, 0x2393 = {21351, 1, 0}, 0x2394 = {21352, 1, 0}, 0x2395 = {21353, 1, 0}, 0x2396 = {21354, 1, 0}, 0x2397 = {21355, 1, 0}, 0x2398 = {21356, 1, 0}, 0x2399 = {21357, 1, 0}, 0x239A = {21358, 1, 0}, 0x239B = {21359, 1, 0}, 0x239C = {21360, 1, 0}, 0x239D = {21361, 1, 0}, 0x239E = {21362, 1, 0}, 0x239F = {21363, 1, 0}, - 0x23A0 = {21364, 1, 0}, 0x23A1 = {21365, 1, 0}, 0x23A2 = {21366, 1, 0}, 0x23A3 = {21367, 1, 0}, 0x23A4 = {21368, 1, 0}, 0x23A5 = {21369, 1, 0}, 0x23A6 = {21370, 1, 0}, 0x23A7 = {21371, 1, 0}, 0x23A8 = {21372, 1, 0}, 0x23A9 = {21373, 1, 0}, 0x23AA = {21374, 1, 0}, 0x23AB = {21375, 1, 0}, 0x23AC = {21376, 1, 0}, 0x23AD = {21377, 1, 0}, 0x23AE = {21378, 1, 0}, 0x23AF = {21379, 1, 0}, - 0x23B0 = {21380, 1, 0}, 0x23B1 = {21381, 1, 0}, 0x23B2 = {21382, 1, 0}, 0x23B3 = {21383, 1, 0}, 0x23B4 = {21384, 1, 0}, 0x23B5 = {21385, 1, 0}, 0x23B6 = {21386, 1, 0}, 0x23B7 = {21387, 1, 0}, 0x23B8 = {21388, 1, 0}, 0x23B9 = {21389, 1, 0}, 0x23BA = {21390, 1, 0}, 0x23BB = {21391, 1, 0}, 0x23BC = {21392, 1, 0}, 0x23BD = {21393, 1, 0}, 0x23BE = {21394, 1, 0}, 0x23BF = {21395, 1, 0}, - 0x23C0 = {21396, 1, 0}, 0x23C1 = {21397, 1, 0}, 0x23C2 = {21398, 1, 0}, 0x23C3 = {21399, 1, 0}, 0x23C4 = {21400, 1, 0}, 0x23C5 = {21401, 1, 0}, 0x23C6 = {21402, 1, 0}, 0x23C7 = {21403, 1, 0}, 0x23C8 = {21404, 1, 0}, 0x23C9 = {21405, 1, 0}, 0x23CA = {21406, 1, 0}, 0x23CB = {21407, 1, 0}, 0x23CC = {21408, 1, 0}, 0x23CD = {21409, 1, 0}, 0x23CE = {21410, 1, 0}, 0x23CF = {21411, 1, 0}, - 0x23D0 = {21412, 1, 0}, 0x23D1 = {21413, 1, 0}, 0x23D2 = {21414, 1, 0}, 0x23D3 = {21415, 1, 0}, 0x23D4 = {21416, 1, 0}, 0x23D5 = {21417, 1, 0}, 0x23D6 = {21418, 1, 0}, 0x23D7 = {21419, 1, 0}, 0x23D8 = {21420, 1, 0}, 0x23D9 = {21421, 1, 0}, 0x23DA = {21422, 1, 0}, 0x23DB = {21423, 1, 0}, 0x23DC = {21424, 1, 0}, 0x23DD = {21425, 1, 0}, 0x23DE = {21426, 1, 0}, 0x23DF = {21427, 1, 0}, - 0x23E0 = {21428, 1, 0}, 0x23E1 = {21429, 1, 0}, 0x23E2 = {21430, 1, 0}, 0x23E3 = {21431, 1, 0}, 0x23E4 = {21432, 1, 0}, 0x23E5 = {21433, 1, 0}, 0x23E6 = {21434, 1, 0}, 0x23E7 = {21435, 1, 0}, 0x23E8 = {21436, 1, 0}, 0x23E9 = {21437, 1, 0}, 0x23EA = {21438, 1, 0}, 0x23EB = {21439, 1, 0}, 0x23EC = {21440, 1, 0}, 0x23ED = {21441, 1, 0}, 0x23EE = {21442, 1, 0}, 0x23EF = {21443, 1, 0}, - 0x23F0 = {21444, 1, 0}, 0x23F1 = {21445, 1, 0}, 0x23F2 = {21446, 1, 0}, 0x23F3 = {21447, 1, 0}, 0x23F4 = {21448, 1, 0}, 0x23F5 = {21449, 1, 0}, 0x23F6 = {21450, 1, 0}, 0x23F7 = {21451, 1, 0}, 0x23F8 = {21452, 1, 0}, 0x23F9 = {21453, 1, 0}, 0x23FA = {21454, 1, 0}, 0x23FB = {21455, 1, 0}, 0x23FC = {21456, 1, 0}, 0x23FD = {21457, 1, 0}, 0x23FE = {21458, 1, 0}, 0x23FF = {21459, 1, 0}, - 0x2400 = {21460, 3, 0}, 0x2401 = {21463, 2, 0}, 0x2402 = {21465, 2, 0}, 0x2403 = {21467, 2, 0}, 0x2404 = {21469, 2, 0}, 0x2405 = {21471, 2, 0}, 0x2406 = {21473, 2, 0}, 0x2407 = {21475, 2, 0}, 0x2408 = {21477, 2, 0}, 0x2409 = {21479, 2, 0}, 0x240A = {21481, 2, 0}, 0x240B = {21483, 2, 0}, 0x240C = {21485, 2, 0}, 0x240D = {21487, 2, 0}, 0x240E = {21489, 2, 0}, 0x240F = {21491, 2, 0}, - 0x2410 = {21493, 2, 0}, 0x2411 = {21495, 2, 0}, 0x2412 = {21497, 2, 0}, 0x2413 = {21499, 2, 0}, 0x2414 = {21501, 2, 0}, 0x2415 = {21503, 2, 0}, 0x2416 = {21505, 2, 0}, 0x2417 = {21507, 2, 0}, 0x2418 = {21509, 2, 0}, 0x2419 = {21511, 2, 0}, 0x241A = {21513, 2, 0}, 0x241B = {21515, 2, 0}, 0x241C = {21517, 2, 0}, 0x241D = {21519, 2, 0}, 0x241E = {21521, 2, 0}, 0x241F = {21523, 2, 0}, - 0x2420 = {21525, 2, 0}, 0x2421 = {21527, 2, 0}, 0x2422 = {21529, 2, 0}, 0x2423 = {21531, 2, 0}, 0x2424 = {21533, 2, 0}, 0x2425 = {21535, 2, 0}, 0x2426 = {21537, 2, 0}, 0x2427 = {21539, 2, 0}, 0x2428 = {21541, 2, 0}, 0x2429 = {21543, 2, 0}, 0x242A = {21545, 2, 0}, 0x242B = {21547, 2, 0}, 0x242C = {21549, 2, 0}, 0x242D = {21551, 2, 0}, 0x242E = {21553, 2, 0}, 0x242F = {21555, 2, 0}, - 0x2430 = {21557, 2, 0}, 0x2431 = {21559, 2, 0}, 0x2432 = {21561, 2, 0}, 0x2433 = {21563, 2, 0}, 0x2434 = {21565, 2, 0}, 0x2435 = {21567, 2, 0}, 0x2436 = {21569, 2, 0}, 0x2437 = {21571, 2, 0}, 0x2438 = {21573, 2, 0}, 0x2439 = {21575, 2, 0}, 0x243A = {21577, 2, 0}, 0x243B = {21579, 2, 0}, 0x243C = {21581, 2, 0}, 0x243D = {21583, 2, 0}, 0x243E = {21585, 2, 0}, 0x243F = {21587, 2, 0}, - 0x2440 = {21589, 2, 0}, 0x2441 = {21591, 2, 0}, 0x2442 = {21593, 2, 0}, 0x2443 = {21595, 2, 0}, 0x2444 = {21597, 2, 0}, 0x2445 = {21599, 2, 0}, 0x2446 = {21601, 2, 0}, 0x2447 = {21603, 2, 0}, 0x2448 = {21605, 2, 0}, 0x2449 = {21607, 2, 0}, 0x244A = {21609, 2, 0}, 0x244B = {21611, 2, 0}, 0x244C = {21613, 2, 0}, 0x244D = {21615, 2, 0}, 0x244E = {21617, 2, 0}, 0x244F = {21619, 2, 0}, - 0x2450 = {21621, 2, 0}, 0x2451 = {21623, 2, 0}, 0x2452 = {21625, 2, 0}, 0x2453 = {21627, 2, 0}, 0x2454 = {21629, 2, 0}, 0x2455 = {21631, 2, 0}, 0x2456 = {21633, 2, 0}, 0x2457 = {21635, 2, 0}, 0x2458 = {21637, 2, 0}, 0x2459 = {21639, 2, 0}, 0x245A = {21641, 2, 0}, 0x245B = {21643, 2, 0}, 0x245C = {21645, 2, 0}, 0x245D = {21647, 2, 0}, 0x245E = {21649, 2, 0}, 0x245F = {21651, 2, 0}, - 0x2460 = {21653, 2, 0}, 0x2461 = {21655, 2, 0}, 0x2462 = {21657, 2, 0}, 0x2463 = {21659, 2, 0}, 0x2464 = {21661, 2, 0}, 0x2465 = {21663, 2, 0}, 0x2466 = {21665, 2, 0}, 0x2467 = {21667, 2, 0}, 0x2468 = {21669, 2, 0}, 0x2469 = {21671, 2, 0}, 0x246A = {21673, 2, 0}, 0x246B = {21675, 2, 0}, 0x246C = {21677, 2, 0}, 0x246D = {21679, 2, 0}, 0x246E = {21681, 2, 0}, 0x246F = {21683, 2, 0}, - 0x2470 = {21685, 2, 0}, 0x2471 = {21687, 2, 0}, 0x2472 = {21689, 2, 0}, 0x2473 = {21691, 2, 0}, 0x2474 = {21693, 2, 0}, 0x2475 = {21695, 2, 0}, 0x2476 = {21697, 2, 0}, 0x2477 = {21699, 2, 0}, 0x2478 = {21701, 2, 0}, 0x2479 = {21703, 2, 0}, 0x247A = {21705, 2, 0}, 0x247B = {21707, 2, 0}, 0x247C = {21709, 2, 0}, 0x247D = {21711, 2, 0}, 0x247E = {21713, 2, 0}, 0x247F = {21715, 2, 0}, - 0x2480 = {21717, 2, 0}, 0x2481 = {21719, 2, 0}, 0x2482 = {21721, 2, 0}, 0x2483 = {21723, 2, 0}, 0x2484 = {21725, 2, 0}, 0x2485 = {21727, 2, 0}, 0x2486 = {21729, 2, 0}, 0x2487 = {21731, 2, 0}, 0x2488 = {21733, 2, 0}, 0x2489 = {21735, 2, 0}, 0x248A = {21737, 2, 0}, 0x248B = {21739, 2, 0}, 0x248C = {21741, 2, 0}, 0x248D = {21743, 2, 0}, 0x248E = {21745, 2, 0}, 0x248F = {21747, 2, 0}, - 0x2490 = {21749, 2, 0}, 0x2491 = {21751, 2, 0}, 0x2492 = {21753, 2, 0}, 0x2493 = {21755, 2, 0}, 0x2494 = {21757, 2, 0}, 0x2495 = {21759, 2, 0}, 0x2496 = {21761, 2, 0}, 0x2497 = {21763, 2, 0}, 0x2498 = {21765, 2, 0}, 0x2499 = {21767, 2, 0}, 0x249A = {21769, 2, 0}, 0x249B = {21771, 2, 0}, 0x249C = {21773, 2, 0}, 0x249D = {21775, 2, 0}, 0x249E = {21777, 2, 0}, 0x249F = {21779, 2, 0}, - 0x24A0 = {21781, 2, 0}, 0x24A1 = {21783, 2, 0}, 0x24A2 = {21785, 2, 0}, 0x24A3 = {21787, 2, 0}, 0x24A4 = {21789, 2, 0}, 0x24A5 = {21791, 2, 0}, 0x24A6 = {21793, 2, 0}, 0x24A7 = {21795, 2, 0}, 0x24A8 = {21797, 2, 0}, 0x24A9 = {21799, 2, 0}, 0x24AA = {21801, 2, 0}, 0x24AB = {21803, 2, 0}, 0x24AC = {21805, 2, 0}, 0x24AD = {21807, 2, 0}, 0x24AE = {21809, 2, 0}, 0x24AF = {21811, 2, 0}, - 0x24B0 = {21813, 2, 0}, 0x24B1 = {21815, 2, 0}, 0x24B2 = {21817, 2, 0}, 0x24B3 = {21819, 2, 0}, 0x24B4 = {21821, 2, 0}, 0x24B5 = {21823, 2, 0}, 0x24B6 = {21825, 2, 0}, 0x24B7 = {21827, 2, 0}, 0x24B8 = {21829, 2, 0}, 0x24B9 = {21831, 2, 0}, 0x24BA = {21833, 2, 0}, 0x24BB = {21835, 2, 0}, 0x24BC = {21837, 2, 0}, 0x24BD = {21839, 2, 0}, 0x24BE = {21841, 2, 0}, 0x24BF = {21843, 2, 0}, - 0x24C0 = {21845, 2, 0}, 0x24C1 = {21847, 2, 0}, 0x24C2 = {21849, 2, 0}, 0x24C3 = {21851, 2, 0}, 0x24C4 = {21853, 2, 0}, 0x24C5 = {21855, 2, 0}, 0x24C6 = {21857, 2, 0}, 0x24C7 = {21859, 2, 0}, 0x24C8 = {21861, 2, 0}, 0x24C9 = {21863, 2, 0}, 0x24CA = {21865, 2, 0}, 0x24CB = {21867, 2, 0}, 0x24CC = {21869, 2, 0}, 0x24CD = {21871, 2, 0}, 0x24CE = {21873, 2, 0}, 0x24CF = {21875, 2, 0}, - 0x24D0 = {21877, 2, 0}, 0x24D1 = {21879, 2, 0}, 0x24D2 = {21881, 2, 0}, 0x24D3 = {21883, 2, 0}, 0x24D4 = {21885, 2, 0}, 0x24D5 = {21887, 2, 0}, 0x24D6 = {21889, 2, 0}, 0x24D7 = {21891, 2, 0}, 0x24D8 = {21893, 2, 0}, 0x24D9 = {21895, 2, 0}, 0x24DA = {21897, 2, 0}, 0x24DB = {21899, 2, 0}, 0x24DC = {21901, 2, 0}, 0x24DD = {21903, 2, 0}, 0x24DE = {21905, 2, 0}, 0x24DF = {21907, 2, 0}, - 0x24E0 = {21909, 2, 0}, 0x24E1 = {21911, 2, 0}, 0x24E2 = {21913, 2, 0}, 0x24E3 = {21915, 2, 0}, 0x24E4 = {21917, 2, 0}, 0x24E5 = {21919, 2, 0}, 0x24E6 = {21921, 2, 0}, 0x24E7 = {21923, 2, 0}, 0x24E8 = {21925, 2, 0}, 0x24E9 = {21927, 2, 0}, 0x24EA = {21929, 2, 0}, 0x24EB = {21931, 2, 0}, 0x24EC = {21933, 2, 0}, 0x24ED = {21935, 2, 0}, 0x24EE = {21937, 2, 0}, 0x24EF = {21939, 2, 0}, - 0x24F0 = {21941, 2, 0}, 0x24F1 = {21943, 2, 0}, 0x24F2 = {21945, 2, 0}, 0x24F3 = {21947, 2, 0}, 0x24F4 = {21949, 2, 0}, 0x24F5 = {21951, 2, 0}, 0x24F6 = {21953, 2, 0}, 0x24F7 = {21955, 2, 0}, 0x24F8 = {21957, 2, 0}, 0x24F9 = {21959, 2, 0}, 0x24FA = {21961, 2, 0}, 0x24FB = {21963, 2, 0}, 0x24FC = {21965, 2, 0}, 0x24FD = {21967, 2, 0}, 0x24FE = {21969, 2, 0}, 0x24FF = {21971, 2, 0}, - 0x2500 = {21973, 2, 0}, 0x2501 = {21975, 1, 0}, 0x2502 = {21976, 1, 0}, 0x2503 = {21977, 1, 0}, 0x2504 = {21978, 1, 0}, 0x2505 = {21979, 1, 0}, 0x2506 = {21980, 1, 0}, 0x2507 = {21981, 1, 0}, 0x2508 = {21982, 1, 0}, 0x2509 = {21983, 1, 0}, 0x250A = {21984, 1, 0}, 0x250B = {21985, 1, 0}, 0x250C = {21986, 1, 0}, 0x250D = {21987, 1, 0}, 0x250E = {21988, 1, 0}, 0x250F = {21989, 1, 0}, - 0x2510 = {21990, 1, 0}, 0x2511 = {21991, 1, 0}, 0x2512 = {21992, 1, 0}, 0x2513 = {21993, 1, 0}, 0x2514 = {21994, 1, 0}, 0x2515 = {21995, 1, 0}, 0x2516 = {21996, 1, 0}, 0x2517 = {21997, 1, 0}, 0x2518 = {21998, 1, 0}, 0x2519 = {21999, 1, 0}, 0x251A = {22000, 1, 0}, 0x251B = {22001, 1, 0}, 0x251C = {22002, 1, 0}, 0x251D = {22003, 1, 0}, 0x251E = {22004, 1, 0}, 0x251F = {22005, 1, 0}, - 0x2520 = {22006, 1, 0}, 0x2521 = {22007, 1, 0}, 0x2522 = {22008, 1, 0}, 0x2523 = {22009, 1, 0}, 0x2524 = {22010, 1, 0}, 0x2525 = {22011, 1, 0}, 0x2526 = {22012, 1, 0}, 0x2527 = {22013, 1, 0}, 0x2528 = {22014, 1, 0}, 0x2529 = {22015, 1, 0}, 0x252A = {22016, 1, 0}, 0x252B = {22017, 1, 0}, 0x252C = {22018, 1, 0}, 0x252D = {22019, 1, 0}, 0x252E = {22020, 1, 0}, 0x252F = {22021, 1, 0}, - 0x2530 = {22022, 1, 0}, 0x2531 = {22023, 1, 0}, 0x2532 = {22024, 1, 0}, 0x2533 = {22025, 1, 0}, 0x2534 = {22026, 1, 0}, 0x2535 = {22027, 1, 0}, 0x2536 = {22028, 1, 0}, 0x2537 = {22029, 1, 0}, 0x2538 = {22030, 1, 0}, 0x2539 = {22031, 1, 0}, 0x253A = {22032, 1, 0}, 0x253B = {22033, 1, 0}, 0x253C = {22034, 1, 0}, 0x253D = {22035, 1, 0}, 0x253E = {22036, 1, 0}, 0x253F = {22037, 1, 0}, - 0x2540 = {22038, 1, 0}, 0x2541 = {22039, 1, 0}, 0x2542 = {22040, 1, 0}, 0x2543 = {22041, 1, 0}, 0x2544 = {22042, 1, 0}, 0x2545 = {22043, 1, 0}, 0x2546 = {22044, 1, 0}, 0x2547 = {22045, 1, 0}, 0x2548 = {22046, 1, 0}, 0x2549 = {22047, 1, 0}, 0x254A = {22048, 1, 0}, 0x254B = {22049, 1, 0}, 0x254C = {22050, 1, 0}, 0x254D = {22051, 1, 0}, 0x254E = {22052, 1, 0}, 0x254F = {22053, 1, 0}, - 0x2550 = {22054, 1, 0}, 0x2551 = {22055, 1, 0}, 0x2552 = {22056, 1, 0}, 0x2553 = {22057, 1, 0}, 0x2554 = {22058, 1, 0}, 0x2555 = {22059, 1, 0}, 0x2556 = {22060, 1, 0}, 0x2557 = {22061, 1, 0}, 0x2558 = {22062, 1, 0}, 0x2559 = {22063, 1, 0}, 0x255A = {22064, 1, 0}, 0x255B = {22065, 1, 0}, 0x255C = {22066, 1, 0}, 0x255D = {22067, 1, 0}, 0x255E = {22068, 1, 0}, 0x255F = {22069, 1, 0}, - 0x2560 = {22070, 1, 0}, 0x2561 = {22071, 1, 0}, 0x2562 = {22072, 1, 0}, 0x2563 = {22073, 1, 0}, 0x2564 = {22074, 1, 0}, 0x2565 = {22075, 1, 0}, 0x2566 = {22076, 1, 0}, 0x2567 = {22077, 1, 0}, 0x2568 = {22078, 1, 0}, 0x2569 = {22079, 1, 0}, 0x256A = {22080, 1, 0}, 0x256B = {22081, 1, 0}, 0x256C = {22082, 1, 0}, 0x256D = {22083, 1, 0}, 0x256E = {22084, 1, 0}, 0x256F = {22085, 1, 0}, - 0x2570 = {22086, 1, 0}, 0x2571 = {22087, 1, 0}, 0x2572 = {22088, 1, 0}, 0x2573 = {22089, 1, 0}, 0x2574 = {22090, 1, 0}, 0x2575 = {22091, 1, 0}, 0x2576 = {22092, 1, 0}, 0x2577 = {22093, 1, 0}, 0x2578 = {22094, 1, 0}, 0x2579 = {22095, 1, 0}, 0x257A = {22096, 1, 0}, 0x257B = {22097, 1, 0}, 0x257C = {22098, 1, 0}, 0x257D = {22099, 1, 0}, 0x257E = {22100, 1, 0}, 0x257F = {22101, 1, 0}, - 0x2580 = {22102, 1, 0}, 0x2581 = {22103, 1, 0}, 0x2582 = {22104, 1, 0}, 0x2583 = {22105, 1, 0}, 0x2584 = {22106, 1, 0}, 0x2585 = {22107, 1, 0}, 0x2586 = {22108, 1, 0}, 0x2587 = {22109, 1, 0}, 0x2588 = {22110, 1, 0}, 0x2589 = {22111, 1, 0}, 0x258A = {22112, 1, 0}, 0x258B = {22113, 1, 0}, 0x258C = {22114, 1, 0}, 0x258D = {22115, 1, 0}, 0x258E = {22116, 1, 0}, 0x258F = {22117, 1, 0}, - 0x2590 = {22118, 1, 0}, 0x2591 = {22119, 1, 0}, 0x2592 = {22120, 1, 0}, 0x2593 = {22121, 1, 0}, 0x2594 = {22122, 1, 0}, 0x2595 = {22123, 1, 0}, 0x2596 = {22124, 1, 0}, 0x2597 = {22125, 1, 0}, 0x2598 = {22126, 1, 0}, 0x2599 = {22127, 1, 0}, 0x259A = {22128, 1, 0}, 0x259B = {22129, 1, 0}, 0x259C = {22130, 1, 0}, 0x259D = {22131, 1, 0}, 0x259E = {22132, 1, 0}, 0x259F = {22133, 1, 0}, - 0x25A0 = {22134, 1, 0}, 0x25A1 = {22135, 1, 0}, 0x25A2 = {22136, 1, 0}, 0x25A3 = {22137, 1, 0}, 0x25A4 = {22138, 1, 0}, 0x25A5 = {22139, 1, 0}, 0x25A6 = {22140, 1, 0}, 0x25A7 = {22141, 1, 0}, 0x25A8 = {22142, 1, 0}, 0x25A9 = {22143, 1, 0}, 0x25AA = {22144, 1, 0}, 0x25AB = {22145, 1, 0}, 0x25AC = {22146, 1, 0}, 0x25AD = {22147, 1, 0}, 0x25AE = {22148, 1, 0}, 0x25AF = {22149, 1, 0}, - 0x25B0 = {22150, 1, 0}, 0x25B1 = {22151, 1, 0}, 0x25B2 = {22152, 1, 0}, 0x25B3 = {22153, 1, 0}, 0x25B4 = {22154, 1, 0}, 0x25B5 = {22155, 1, 0}, 0x25B6 = {22156, 1, 0}, 0x25B7 = {22157, 1, 0}, 0x25B8 = {22158, 1, 0}, 0x25B9 = {22159, 1, 0}, 0x25BA = {22160, 1, 0}, 0x25BB = {22161, 1, 0}, 0x25BC = {22162, 1, 0}, 0x25BD = {22163, 1, 0}, 0x25BE = {22164, 1, 0}, 0x25BF = {22165, 1, 0}, - 0x25C0 = {22166, 1, 0}, 0x25C1 = {22167, 1, 0}, 0x25C2 = {22168, 1, 0}, 0x25C3 = {22169, 1, 0}, 0x25C4 = {22170, 1, 0}, 0x25C5 = {22171, 1, 0}, 0x25C6 = {22172, 1, 0}, 0x25C7 = {22173, 1, 0}, 0x25C8 = {22174, 1, 0}, 0x25C9 = {22175, 1, 0}, 0x25CA = {22176, 1, 0}, 0x25CB = {22177, 1, 0}, 0x25CC = {22178, 1, 0}, 0x25CD = {22179, 1, 0}, 0x25CE = {22180, 1, 0}, 0x25CF = {22181, 1, 0}, - 0x25D0 = {22182, 1, 0}, 0x25D1 = {22183, 1, 0}, 0x25D2 = {22184, 1, 0}, 0x25D3 = {22185, 1, 0}, 0x25D4 = {22186, 1, 0}, 0x25D5 = {22187, 1, 0}, 0x25D6 = {22188, 1, 0}, 0x25D7 = {22189, 1, 0}, 0x25D8 = {22190, 1, 0}, 0x25D9 = {22191, 1, 0}, 0x25DA = {22192, 1, 0}, 0x25DB = {22193, 1, 0}, 0x25DC = {22194, 1, 0}, 0x25DD = {22195, 1, 0}, 0x25DE = {22196, 1, 0}, 0x25DF = {22197, 1, 0}, - 0x25E0 = {22198, 1, 0}, 0x25E1 = {22199, 1, 0}, 0x25E2 = {22200, 1, 0}, 0x25E3 = {22201, 1, 0}, 0x25E4 = {22202, 1, 0}, 0x25E5 = {22203, 1, 0}, 0x25E6 = {22204, 1, 0}, 0x25E7 = {22205, 1, 0}, 0x25E8 = {22206, 1, 0}, 0x25E9 = {22207, 1, 0}, 0x25EA = {22208, 1, 0}, 0x25EB = {22209, 1, 0}, 0x25EC = {22210, 1, 0}, 0x25ED = {22211, 1, 0}, 0x25EE = {22212, 1, 0}, 0x25EF = {22213, 1, 0}, - 0x25F0 = {22214, 1, 0}, 0x25F1 = {22215, 1, 0}, 0x25F2 = {22216, 1, 0}, 0x25F3 = {22217, 1, 0}, 0x25F4 = {22218, 1, 0}, 0x25F5 = {22219, 1, 0}, 0x25F6 = {22220, 1, 0}, 0x25F7 = {22221, 1, 0}, 0x25F8 = {22222, 1, 0}, 0x25F9 = {22223, 1, 0}, 0x25FA = {22224, 1, 0}, 0x25FB = {22225, 1, 0}, 0x25FC = {22226, 1, 0}, 0x25FD = {22227, 1, 0}, 0x25FE = {22228, 1, 0}, 0x25FF = {22229, 1, 0}, - 0x2600 = {22230, 2, 0}, 0x2601 = {22232, 2, 0}, 0x2602 = {22234, 2, 0}, 0x2603 = {22236, 2, 0}, 0x2604 = {22238, 2, 0}, 0x2605 = {22240, 2, 0}, 0x2606 = {22242, 2, 0}, 0x2607 = {22244, 2, 0}, 0x2608 = {22246, 2, 0}, 0x2609 = {22248, 2, 0}, 0x260A = {22250, 2, 0}, 0x260B = {22252, 2, 0}, 0x260C = {22254, 2, 0}, 0x260D = {22256, 2, 0}, 0x260E = {22258, 2, 0}, 0x260F = {22260, 2, 0}, - 0x2610 = {22262, 2, 0}, 0x2611 = {22264, 2, 0}, 0x2612 = {22266, 2, 0}, 0x2613 = {22268, 2, 0}, 0x2614 = {22270, 2, 0}, 0x2615 = {22272, 2, 0}, 0x2616 = {22274, 2, 0}, 0x2617 = {22276, 2, 0}, 0x2618 = {22278, 2, 0}, 0x2619 = {22280, 2, 0}, 0x261A = {22282, 2, 0}, 0x261B = {22284, 2, 0}, 0x261C = {22286, 2, 0}, 0x261D = {22288, 2, 0}, 0x261E = {22290, 2, 0}, 0x261F = {22292, 2, 0}, - 0x2620 = {22294, 2, 0}, 0x2621 = {22296, 2, 0}, 0x2622 = {22298, 2, 0}, 0x2623 = {22300, 2, 0}, 0x2624 = {22302, 2, 0}, 0x2625 = {22304, 2, 0}, 0x2626 = {22306, 2, 0}, 0x2627 = {22308, 2, 0}, 0x2628 = {22310, 2, 0}, 0x2629 = {22312, 2, 0}, 0x262A = {22314, 2, 0}, 0x262B = {22316, 2, 0}, 0x262C = {22318, 2, 0}, 0x262D = {22320, 2, 0}, 0x262E = {22322, 2, 0}, 0x262F = {22324, 2, 0}, - 0x2630 = {22326, 2, 0}, 0x2631 = {22328, 2, 0}, 0x2632 = {22330, 2, 0}, 0x2633 = {22332, 2, 0}, 0x2634 = {22334, 2, 0}, 0x2635 = {22336, 2, 0}, 0x2636 = {22338, 2, 0}, 0x2637 = {22340, 2, 0}, 0x2638 = {22342, 2, 0}, 0x2639 = {22344, 2, 0}, 0x263A = {22346, 2, 0}, 0x263B = {22348, 2, 0}, 0x263C = {22350, 2, 0}, 0x263D = {22352, 2, 0}, 0x263E = {22354, 2, 0}, 0x263F = {22356, 2, 0}, - 0x2640 = {22358, 2, 0}, 0x2641 = {22360, 2, 0}, 0x2642 = {22362, 2, 0}, 0x2643 = {22364, 2, 0}, 0x2644 = {22366, 2, 0}, 0x2645 = {22368, 2, 0}, 0x2646 = {22370, 2, 0}, 0x2647 = {22372, 2, 0}, 0x2648 = {22374, 2, 0}, 0x2649 = {22376, 2, 0}, 0x264A = {22378, 2, 0}, 0x264B = {22380, 2, 0}, 0x264C = {22382, 2, 0}, 0x264D = {22384, 2, 0}, 0x264E = {22386, 2, 0}, 0x264F = {22388, 2, 0}, - 0x2650 = {22390, 2, 0}, 0x2651 = {22392, 2, 0}, 0x2652 = {22394, 2, 0}, 0x2653 = {22396, 2, 0}, 0x2654 = {22398, 2, 0}, 0x2655 = {22400, 2, 0}, 0x2656 = {22402, 2, 0}, 0x2657 = {22404, 2, 0}, 0x2658 = {22406, 2, 0}, 0x2659 = {22408, 2, 0}, 0x265A = {22410, 2, 0}, 0x265B = {22412, 2, 0}, 0x265C = {22414, 2, 0}, 0x265D = {22416, 2, 0}, 0x265E = {22418, 2, 0}, 0x265F = {22420, 2, 0}, - 0x2660 = {22422, 2, 0}, 0x2661 = {22424, 2, 0}, 0x2662 = {22426, 2, 0}, 0x2663 = {22428, 2, 0}, 0x2664 = {22430, 2, 0}, 0x2665 = {22432, 2, 0}, 0x2666 = {22434, 2, 0}, 0x2667 = {22436, 2, 0}, 0x2668 = {22438, 2, 0}, 0x2669 = {22440, 2, 0}, 0x266A = {22442, 2, 0}, 0x266B = {22444, 2, 0}, 0x266C = {22446, 2, 0}, 0x266D = {22448, 2, 0}, 0x266E = {22450, 2, 0}, 0x266F = {22452, 2, 0}, - 0x2670 = {22454, 2, 0}, 0x2671 = {22456, 2, 0}, 0x2672 = {22458, 2, 0}, 0x2673 = {22460, 2, 0}, 0x2674 = {22462, 2, 0}, 0x2675 = {22464, 2, 0}, 0x2676 = {22466, 2, 0}, 0x2677 = {22468, 2, 0}, 0x2678 = {22470, 2, 0}, 0x2679 = {22472, 2, 0}, 0x267A = {22474, 2, 0}, 0x267B = {22476, 2, 0}, 0x267C = {22478, 2, 0}, 0x267D = {22480, 2, 0}, 0x267E = {22482, 2, 0}, 0x267F = {22484, 2, 0}, - 0x2680 = {22486, 2, 0}, 0x2681 = {22488, 2, 0}, 0x2682 = {22490, 2, 0}, 0x2683 = {22492, 2, 0}, 0x2684 = {22494, 2, 0}, 0x2685 = {22496, 2, 0}, 0x2686 = {22498, 2, 0}, 0x2687 = {22500, 2, 0}, 0x2688 = {22502, 2, 0}, 0x2689 = {22504, 2, 0}, 0x268A = {22506, 2, 0}, 0x268B = {22508, 2, 0}, 0x268C = {22510, 2, 0}, 0x268D = {22512, 2, 0}, 0x268E = {22514, 2, 0}, 0x268F = {22516, 2, 0}, - 0x2690 = {22518, 2, 0}, 0x2691 = {22520, 2, 0}, 0x2692 = {22522, 2, 0}, 0x2693 = {22524, 2, 0}, 0x2694 = {22526, 2, 0}, 0x2695 = {22528, 2, 0}, 0x2696 = {22530, 2, 0}, 0x2697 = {22532, 2, 0}, 0x2698 = {22534, 2, 0}, 0x2699 = {22536, 2, 0}, 0x269A = {22538, 2, 0}, 0x269B = {22540, 2, 0}, 0x269C = {22542, 2, 0}, 0x269D = {22544, 2, 0}, 0x269E = {22546, 2, 0}, 0x269F = {22548, 2, 0}, - 0x26A0 = {22550, 2, 0}, 0x26A1 = {22552, 2, 0}, 0x26A2 = {22554, 2, 0}, 0x26A3 = {22556, 2, 0}, 0x26A4 = {22558, 2, 0}, 0x26A5 = {22560, 2, 0}, 0x26A6 = {22562, 2, 0}, 0x26A7 = {22564, 2, 0}, 0x26A8 = {22566, 2, 0}, 0x26A9 = {22568, 2, 0}, 0x26AA = {22570, 2, 0}, 0x26AB = {22572, 2, 0}, 0x26AC = {22574, 2, 0}, 0x26AD = {22576, 2, 0}, 0x26AE = {22578, 2, 0}, 0x26AF = {22580, 2, 0}, - 0x26B0 = {22582, 2, 0}, 0x26B1 = {22584, 2, 0}, 0x26B2 = {22586, 2, 0}, 0x26B3 = {22588, 2, 0}, 0x26B4 = {22590, 2, 0}, 0x26B5 = {22592, 2, 0}, 0x26B6 = {22594, 2, 0}, 0x26B7 = {22596, 2, 0}, 0x26B8 = {22598, 2, 0}, 0x26B9 = {22600, 2, 0}, 0x26BA = {22602, 2, 0}, 0x26BB = {22604, 2, 0}, 0x26BC = {22606, 2, 0}, 0x26BD = {22608, 2, 0}, 0x26BE = {22610, 2, 0}, 0x26BF = {22612, 2, 0}, - 0x26C0 = {22614, 2, 0}, 0x26C1 = {22616, 2, 0}, 0x26C2 = {22618, 2, 0}, 0x26C3 = {22620, 2, 0}, 0x26C4 = {22622, 2, 0}, 0x26C5 = {22624, 2, 0}, 0x26C6 = {22626, 2, 0}, 0x26C7 = {22628, 2, 0}, 0x26C8 = {22630, 2, 0}, 0x26C9 = {22632, 2, 0}, 0x26CA = {22634, 2, 0}, 0x26CB = {22636, 2, 0}, 0x26CC = {22638, 2, 0}, 0x26CD = {22640, 2, 0}, 0x26CE = {22642, 2, 0}, 0x26CF = {22644, 2, 0}, - 0x26D0 = {22646, 2, 0}, 0x26D1 = {22648, 2, 0}, 0x26D2 = {22650, 2, 0}, 0x26D3 = {22652, 2, 0}, 0x26D4 = {22654, 2, 0}, 0x26D5 = {22656, 2, 0}, 0x26D6 = {22658, 2, 0}, 0x26D7 = {22660, 2, 0}, 0x26D8 = {22662, 2, 0}, 0x26D9 = {22664, 2, 0}, 0x26DA = {22666, 2, 0}, 0x26DB = {22668, 2, 0}, 0x26DC = {22670, 2, 0}, 0x26DD = {22672, 2, 0}, 0x26DE = {22674, 2, 0}, 0x26DF = {22676, 2, 0}, - 0x26E0 = {22678, 2, 0}, 0x26E1 = {22680, 2, 0}, 0x26E2 = {22682, 2, 0}, 0x26E3 = {22684, 2, 0}, 0x26E4 = {22686, 2, 0}, 0x26E5 = {22688, 2, 0}, 0x26E6 = {22690, 2, 0}, 0x26E7 = {22692, 2, 0}, 0x26E8 = {22694, 2, 0}, 0x26E9 = {22696, 2, 0}, 0x26EA = {22698, 2, 0}, 0x26EB = {22700, 2, 0}, 0x26EC = {22702, 2, 0}, 0x26ED = {22704, 2, 0}, 0x26EE = {22706, 2, 0}, 0x26EF = {22708, 2, 0}, - 0x26F0 = {22710, 2, 0}, 0x26F1 = {22712, 2, 0}, 0x26F2 = {22714, 2, 0}, 0x26F3 = {22716, 2, 0}, 0x26F4 = {22718, 2, 0}, 0x26F5 = {22720, 2, 0}, 0x26F6 = {22722, 2, 0}, 0x26F7 = {22724, 2, 0}, 0x26F8 = {22726, 2, 0}, 0x26F9 = {22728, 2, 0}, 0x26FA = {22730, 2, 0}, 0x26FB = {22732, 2, 0}, 0x26FC = {22734, 2, 0}, 0x26FD = {22736, 2, 0}, 0x26FE = {22738, 2, 0}, 0x26FF = {22740, 2, 0}, - 0x2700 = {22742, 1, 0}, 0x2701 = {22743, 1, 0}, 0x2702 = {22744, 1, 0}, 0x2703 = {22745, 1, 0}, 0x2704 = {22746, 1, 0}, 0x2705 = {22747, 1, 0}, 0x2706 = {22748, 1, 0}, 0x2707 = {22749, 1, 0}, 0x2708 = {22750, 1, 0}, 0x2709 = {22751, 1, 0}, 0x270A = {22752, 1, 0}, 0x270B = {22753, 1, 0}, 0x270C = {22754, 1, 0}, 0x270D = {22755, 1, 0}, 0x270E = {22756, 1, 0}, 0x270F = {22757, 1, 0}, - 0x2710 = {22758, 1, 0}, 0x2711 = {22759, 1, 0}, 0x2712 = {22760, 1, 0}, 0x2713 = {22761, 1, 0}, 0x2714 = {22762, 1, 0}, 0x2715 = {22763, 1, 0}, 0x2716 = {22764, 1, 0}, 0x2717 = {22765, 1, 0}, 0x2718 = {22766, 1, 0}, 0x2719 = {22767, 1, 0}, 0x271A = {22768, 1, 0}, 0x271B = {22769, 1, 0}, 0x271C = {22770, 1, 0}, 0x271D = {22771, 1, 0}, 0x271E = {22772, 1, 0}, 0x271F = {22773, 1, 0}, - 0x2720 = {22774, 1, 0}, 0x2721 = {22775, 1, 0}, 0x2722 = {22776, 1, 0}, 0x2723 = {22777, 1, 0}, 0x2724 = {22778, 1, 0}, 0x2725 = {22779, 1, 0}, 0x2726 = {22780, 1, 0}, 0x2727 = {22781, 1, 0}, 0x2728 = {22782, 1, 0}, 0x2729 = {22783, 1, 0}, 0x272A = {22784, 1, 0}, 0x272B = {22785, 1, 0}, 0x272C = {22786, 1, 0}, 0x272D = {22787, 1, 0}, 0x272E = {22788, 1, 0}, 0x272F = {22789, 1, 0}, - 0x2730 = {22790, 1, 0}, 0x2731 = {22791, 1, 0}, 0x2732 = {22792, 1, 0}, 0x2733 = {22793, 1, 0}, 0x2734 = {22794, 1, 0}, 0x2735 = {22795, 1, 0}, 0x2736 = {22796, 1, 0}, 0x2737 = {22797, 1, 0}, 0x2738 = {22798, 1, 0}, 0x2739 = {22799, 1, 0}, 0x273A = {22800, 1, 0}, 0x273B = {22801, 1, 0}, 0x273C = {22802, 1, 0}, 0x273D = {22803, 1, 0}, 0x273E = {22804, 1, 0}, 0x273F = {22805, 1, 0}, - 0x2740 = {22806, 1, 0}, 0x2741 = {22807, 1, 0}, 0x2742 = {22808, 1, 0}, 0x2743 = {22809, 1, 0}, 0x2744 = {22810, 1, 0}, 0x2745 = {22811, 1, 0}, 0x2746 = {22812, 1, 0}, 0x2747 = {22813, 1, 0}, 0x2748 = {22814, 1, 0}, 0x2749 = {22815, 1, 0}, 0x274A = {22816, 1, 0}, 0x274B = {22817, 1, 0}, 0x274C = {22818, 1, 0}, 0x274D = {22819, 1, 0}, 0x274E = {22820, 1, 0}, 0x274F = {22821, 1, 0}, - 0x2750 = {22822, 1, 0}, 0x2751 = {22823, 1, 0}, 0x2752 = {22824, 1, 0}, 0x2753 = {22825, 1, 0}, 0x2754 = {22826, 1, 0}, 0x2755 = {22827, 1, 0}, 0x2756 = {22828, 1, 0}, 0x2757 = {22829, 1, 0}, 0x2758 = {22830, 1, 0}, 0x2759 = {22831, 1, 0}, 0x275A = {22832, 1, 0}, 0x275B = {22833, 1, 0}, 0x275C = {22834, 1, 0}, 0x275D = {22835, 1, 0}, 0x275E = {22836, 1, 0}, 0x275F = {22837, 1, 0}, - 0x2760 = {22838, 1, 0}, 0x2761 = {22839, 1, 0}, 0x2762 = {22840, 1, 0}, 0x2763 = {22841, 1, 0}, 0x2764 = {22842, 1, 0}, 0x2765 = {22843, 1, 0}, 0x2766 = {22844, 1, 0}, 0x2767 = {22845, 1, 0}, 0x2768 = {22846, 1, 0}, 0x2769 = {22847, 1, 0}, 0x276A = {22848, 1, 0}, 0x276B = {22849, 1, 0}, 0x276C = {22850, 1, 0}, 0x276D = {22851, 1, 0}, 0x276E = {22852, 1, 0}, 0x276F = {22853, 1, 0}, - 0x2770 = {22854, 1, 0}, 0x2771 = {22855, 1, 0}, 0x2772 = {22856, 1, 0}, 0x2773 = {22857, 1, 0}, 0x2774 = {22858, 1, 0}, 0x2775 = {22859, 1, 0}, 0x2776 = {22860, 1, 0}, 0x2777 = {22861, 1, 0}, 0x2778 = {22862, 1, 0}, 0x2779 = {22863, 1, 0}, 0x277A = {22864, 1, 0}, 0x277B = {22865, 1, 0}, 0x277C = {22866, 1, 0}, 0x277D = {22867, 1, 0}, 0x277E = {22868, 1, 0}, 0x277F = {22869, 1, 0}, - 0x2780 = {22870, 1, 0}, 0x2781 = {22871, 1, 0}, 0x2782 = {22872, 1, 0}, 0x2783 = {22873, 1, 0}, 0x2784 = {22874, 1, 0}, 0x2785 = {22875, 1, 0}, 0x2786 = {22876, 1, 0}, 0x2787 = {22877, 1, 0}, 0x2788 = {22878, 1, 0}, 0x2789 = {22879, 1, 0}, 0x278A = {22880, 1, 0}, 0x278B = {22881, 1, 0}, 0x278C = {22882, 1, 0}, 0x278D = {22883, 1, 0}, 0x278E = {22884, 1, 0}, 0x278F = {22885, 1, 0}, - 0x2790 = {22886, 1, 0}, 0x2791 = {22887, 1, 0}, 0x2792 = {22888, 1, 0}, 0x2793 = {22889, 1, 0}, 0x2794 = {22890, 1, 0}, 0x2795 = {22891, 1, 0}, 0x2796 = {22892, 1, 0}, 0x2797 = {22893, 1, 0}, 0x2798 = {22894, 1, 0}, 0x2799 = {22895, 1, 0}, 0x279A = {22896, 1, 0}, 0x279B = {22897, 1, 0}, 0x279C = {22898, 1, 0}, 0x279D = {22899, 1, 0}, 0x279E = {22900, 1, 0}, 0x279F = {22901, 1, 0}, - 0x27A0 = {22902, 1, 0}, 0x27A1 = {22903, 1, 0}, 0x27A2 = {22904, 1, 0}, 0x27A3 = {22905, 1, 0}, 0x27A4 = {22906, 1, 0}, 0x27A5 = {22907, 1, 0}, 0x27A6 = {22908, 1, 0}, 0x27A7 = {22909, 1, 0}, 0x27A8 = {22910, 1, 0}, 0x27A9 = {22911, 1, 0}, 0x27AA = {22912, 1, 0}, 0x27AB = {22913, 1, 0}, 0x27AC = {22914, 1, 0}, 0x27AD = {22915, 1, 0}, 0x27AE = {22916, 1, 0}, 0x27AF = {22917, 1, 0}, - 0x27B0 = {22918, 1, 0}, 0x27B1 = {22919, 1, 0}, 0x27B2 = {22920, 1, 0}, 0x27B3 = {22921, 1, 0}, 0x27B4 = {22922, 1, 0}, 0x27B5 = {22923, 1, 0}, 0x27B6 = {22924, 1, 0}, 0x27B7 = {22925, 1, 0}, 0x27B8 = {22926, 1, 0}, 0x27B9 = {22927, 1, 0}, 0x27BA = {22928, 1, 0}, 0x27BB = {22929, 1, 0}, 0x27BC = {22930, 1, 0}, 0x27BD = {22931, 1, 0}, 0x27BE = {22932, 1, 0}, 0x27BF = {22933, 1, 0}, - 0x27C0 = {22934, 1, 0}, 0x27C1 = {22935, 1, 0}, 0x27C2 = {22936, 1, 0}, 0x27C3 = {22937, 1, 0}, 0x27C4 = {22938, 1, 0}, 0x27C5 = {22939, 1, 0}, 0x27C6 = {22940, 1, 0}, 0x27C7 = {22941, 1, 0}, 0x27C8 = {22942, 1, 0}, 0x27C9 = {22943, 1, 0}, 0x27CA = {22944, 1, 0}, 0x27CB = {22945, 1, 0}, 0x27CC = {22946, 1, 0}, 0x27CD = {22947, 1, 0}, 0x27CE = {22948, 1, 0}, 0x27CF = {22949, 1, 0}, - 0x27D0 = {22950, 1, 0}, 0x27D1 = {22951, 1, 0}, 0x27D2 = {22952, 1, 0}, 0x27D3 = {22953, 1, 0}, 0x27D4 = {22954, 1, 0}, 0x27D5 = {22955, 1, 0}, 0x27D6 = {22956, 1, 0}, 0x27D7 = {22957, 1, 0}, 0x27D8 = {22958, 1, 0}, 0x27D9 = {22959, 1, 0}, 0x27DA = {22960, 1, 0}, 0x27DB = {22961, 1, 0}, 0x27DC = {22962, 1, 0}, 0x27DD = {22963, 1, 0}, 0x27DE = {22964, 1, 0}, 0x27DF = {22965, 1, 0}, - 0x27E0 = {22966, 1, 0}, 0x27E1 = {22967, 1, 0}, 0x27E2 = {22968, 1, 0}, 0x27E3 = {22969, 1, 0}, 0x27E4 = {22970, 1, 0}, 0x27E5 = {22971, 1, 0}, 0x27E6 = {22972, 1, 0}, 0x27E7 = {22973, 1, 0}, 0x27E8 = {22974, 1, 0}, 0x27E9 = {22975, 1, 0}, 0x27EA = {22976, 1, 0}, 0x27EB = {22977, 1, 0}, 0x27EC = {22978, 1, 0}, 0x27ED = {22979, 1, 0}, 0x27EE = {22980, 1, 0}, 0x27EF = {22981, 1, 0}, - 0x27F0 = {22982, 1, 0}, 0x27F1 = {22983, 1, 0}, 0x27F2 = {22984, 1, 0}, 0x27F3 = {22985, 1, 0}, 0x27F4 = {22986, 1, 0}, 0x27F5 = {22987, 1, 0}, 0x27F6 = {22988, 1, 0}, 0x27F7 = {22989, 1, 0}, 0x27F8 = {22990, 1, 0}, 0x27F9 = {22991, 1, 0}, 0x27FA = {22992, 1, 0}, 0x27FB = {22993, 1, 0}, 0x27FC = {22994, 1, 0}, 0x27FD = {22995, 1, 0}, 0x27FE = {22996, 1, 0}, 0x27FF = {22997, 1, 0}, - 0x2800 = {22998, 2, 0}, 0x2801 = {23000, 2, 0}, 0x2802 = {23002, 2, 0}, 0x2803 = {23004, 2, 0}, 0x2804 = {23006, 2, 0}, 0x2805 = {23008, 2, 0}, 0x2806 = {23010, 2, 0}, 0x2807 = {23012, 2, 0}, 0x2808 = {23014, 2, 0}, 0x2809 = {23016, 2, 0}, 0x280A = {23018, 2, 0}, 0x280B = {23020, 2, 0}, 0x280C = {23022, 2, 0}, 0x280D = {23024, 2, 0}, 0x280E = {23026, 2, 0}, 0x280F = {23028, 2, 0}, - 0x2810 = {23030, 2, 0}, 0x2811 = {23032, 2, 0}, 0x2812 = {23034, 2, 0}, 0x2813 = {23036, 2, 0}, 0x2814 = {23038, 2, 0}, 0x2815 = {23040, 2, 0}, 0x2816 = {23042, 2, 0}, 0x2817 = {23044, 2, 0}, 0x2818 = {23046, 2, 0}, 0x2819 = {23048, 2, 0}, 0x281A = {23050, 2, 0}, 0x281B = {23052, 2, 0}, 0x281C = {23054, 2, 0}, 0x281D = {23056, 2, 0}, 0x281E = {23058, 2, 0}, 0x281F = {23060, 2, 0}, - 0x2820 = {23062, 2, 0}, 0x2821 = {23064, 2, 0}, 0x2822 = {23066, 2, 0}, 0x2823 = {23068, 2, 0}, 0x2824 = {23070, 2, 0}, 0x2825 = {23072, 2, 0}, 0x2826 = {23074, 2, 0}, 0x2827 = {23076, 2, 0}, 0x2828 = {23078, 2, 0}, 0x2829 = {23080, 2, 0}, 0x282A = {23082, 2, 0}, 0x282B = {23084, 2, 0}, 0x282C = {23086, 2, 0}, 0x282D = {23088, 2, 0}, 0x282E = {23090, 2, 0}, 0x282F = {23092, 2, 0}, - 0x2830 = {23094, 2, 0}, 0x2831 = {23096, 2, 0}, 0x2832 = {23098, 2, 0}, 0x2833 = {23100, 2, 0}, 0x2834 = {23102, 2, 0}, 0x2835 = {23104, 2, 0}, 0x2836 = {23106, 2, 0}, 0x2837 = {23108, 2, 0}, 0x2838 = {23110, 2, 0}, 0x2839 = {23112, 2, 0}, 0x283A = {23114, 2, 0}, 0x283B = {23116, 2, 0}, 0x283C = {23118, 2, 0}, 0x283D = {23120, 2, 0}, 0x283E = {23122, 2, 0}, 0x283F = {23124, 2, 0}, - 0x2840 = {23126, 2, 0}, 0x2841 = {23128, 2, 0}, 0x2842 = {23130, 2, 0}, 0x2843 = {23132, 2, 0}, 0x2844 = {23134, 2, 0}, 0x2845 = {23136, 2, 0}, 0x2846 = {23138, 2, 0}, 0x2847 = {23140, 2, 0}, 0x2848 = {23142, 2, 0}, 0x2849 = {23144, 2, 0}, 0x284A = {23146, 2, 0}, 0x284B = {23148, 2, 0}, 0x284C = {23150, 2, 0}, 0x284D = {23152, 2, 0}, 0x284E = {23154, 2, 0}, 0x284F = {23156, 2, 0}, - 0x2850 = {23158, 2, 0}, 0x2851 = {23160, 2, 0}, 0x2852 = {23162, 2, 0}, 0x2853 = {23164, 2, 0}, 0x2854 = {23166, 2, 0}, 0x2855 = {23168, 2, 0}, 0x2856 = {23170, 2, 0}, 0x2857 = {23172, 2, 0}, 0x2858 = {23174, 2, 0}, 0x2859 = {23176, 2, 0}, 0x285A = {23178, 2, 0}, 0x285B = {23180, 2, 0}, 0x285C = {23182, 2, 0}, 0x285D = {23184, 2, 0}, 0x285E = {23186, 2, 0}, 0x285F = {23188, 2, 0}, - 0x2860 = {23190, 2, 0}, 0x2861 = {23192, 2, 0}, 0x2862 = {23194, 2, 0}, 0x2863 = {23196, 2, 0}, 0x2864 = {23198, 2, 0}, 0x2865 = {23200, 2, 0}, 0x2866 = {23202, 2, 0}, 0x2867 = {23204, 2, 0}, 0x2868 = {23206, 2, 0}, 0x2869 = {23208, 2, 0}, 0x286A = {23210, 2, 0}, 0x286B = {23212, 2, 0}, 0x286C = {23214, 2, 0}, 0x286D = {23216, 2, 0}, 0x286E = {23218, 2, 0}, 0x286F = {23220, 2, 0}, - 0x2870 = {23222, 2, 0}, 0x2871 = {23224, 2, 0}, 0x2872 = {23226, 2, 0}, 0x2873 = {23228, 2, 0}, 0x2874 = {23230, 2, 0}, 0x2875 = {23232, 2, 0}, 0x2876 = {23234, 2, 0}, 0x2877 = {23236, 2, 0}, 0x2878 = {23238, 2, 0}, 0x2879 = {23240, 2, 0}, 0x287A = {23242, 2, 0}, 0x287B = {23244, 2, 0}, 0x287C = {23246, 2, 0}, 0x287D = {23248, 2, 0}, 0x287E = {23250, 2, 0}, 0x287F = {23252, 2, 0}, - 0x2880 = {23254, 2, 0}, 0x2881 = {23256, 2, 0}, 0x2882 = {23258, 2, 0}, 0x2883 = {23260, 2, 0}, 0x2884 = {23262, 2, 0}, 0x2885 = {23264, 2, 0}, 0x2886 = {23266, 2, 0}, 0x2887 = {23268, 2, 0}, 0x2888 = {23270, 2, 0}, 0x2889 = {23272, 2, 0}, 0x288A = {23274, 2, 0}, 0x288B = {23276, 2, 0}, 0x288C = {23278, 2, 0}, 0x288D = {23280, 2, 0}, 0x288E = {23282, 2, 0}, 0x288F = {23284, 2, 0}, - 0x2890 = {23286, 2, 0}, 0x2891 = {23288, 2, 0}, 0x2892 = {23290, 2, 0}, 0x2893 = {23292, 2, 0}, 0x2894 = {23294, 2, 0}, 0x2895 = {23296, 2, 0}, 0x2896 = {23298, 2, 0}, 0x2897 = {23300, 2, 0}, 0x2898 = {23302, 2, 0}, 0x2899 = {23304, 2, 0}, 0x289A = {23306, 2, 0}, 0x289B = {23308, 2, 0}, 0x289C = {23310, 2, 0}, 0x289D = {23312, 2, 0}, 0x289E = {23314, 2, 0}, 0x289F = {23316, 2, 0}, - 0x28A0 = {23318, 2, 0}, 0x28A1 = {23320, 2, 0}, 0x28A2 = {23322, 2, 0}, 0x28A3 = {23324, 2, 0}, 0x28A4 = {23326, 2, 0}, 0x28A5 = {23328, 2, 0}, 0x28A6 = {23330, 2, 0}, 0x28A7 = {23332, 2, 0}, 0x28A8 = {23334, 2, 0}, 0x28A9 = {23336, 2, 0}, 0x28AA = {23338, 2, 0}, 0x28AB = {23340, 2, 0}, 0x28AC = {23342, 2, 0}, 0x28AD = {23344, 2, 0}, 0x28AE = {23346, 2, 0}, 0x28AF = {23348, 2, 0}, - 0x28B0 = {23350, 2, 0}, 0x28B1 = {23352, 2, 0}, 0x28B2 = {23354, 2, 0}, 0x28B3 = {23356, 2, 0}, 0x28B4 = {23358, 2, 0}, 0x28B5 = {23360, 2, 0}, 0x28B6 = {23362, 2, 0}, 0x28B7 = {23364, 2, 0}, 0x28B8 = {23366, 2, 0}, 0x28B9 = {23368, 2, 0}, 0x28BA = {23370, 2, 0}, 0x28BB = {23372, 2, 0}, 0x28BC = {23374, 2, 0}, 0x28BD = {23376, 2, 0}, 0x28BE = {23378, 2, 0}, 0x28BF = {23380, 2, 0}, - 0x28C0 = {23382, 2, 0}, 0x28C1 = {23384, 2, 0}, 0x28C2 = {23386, 2, 0}, 0x28C3 = {23388, 2, 0}, 0x28C4 = {23390, 2, 0}, 0x28C5 = {23392, 2, 0}, 0x28C6 = {23394, 2, 0}, 0x28C7 = {23396, 2, 0}, 0x28C8 = {23398, 2, 0}, 0x28C9 = {23400, 2, 0}, 0x28CA = {23402, 2, 0}, 0x28CB = {23404, 2, 0}, 0x28CC = {23406, 2, 0}, 0x28CD = {23408, 2, 0}, 0x28CE = {23410, 2, 0}, 0x28CF = {23412, 2, 0}, - 0x28D0 = {23414, 2, 0}, 0x28D1 = {23416, 2, 0}, 0x28D2 = {23418, 2, 0}, 0x28D3 = {23420, 2, 0}, 0x28D4 = {23422, 2, 0}, 0x28D5 = {23424, 2, 0}, 0x28D6 = {23426, 2, 0}, 0x28D7 = {23428, 2, 0}, 0x28D8 = {23430, 2, 0}, 0x28D9 = {23432, 2, 0}, 0x28DA = {23434, 2, 0}, 0x28DB = {23436, 2, 0}, 0x28DC = {23438, 2, 0}, 0x28DD = {23440, 2, 0}, 0x28DE = {23442, 2, 0}, 0x28DF = {23444, 2, 0}, - 0x28E0 = {23446, 2, 0}, 0x28E1 = {23448, 2, 0}, 0x28E2 = {23450, 2, 0}, 0x28E3 = {23452, 2, 0}, 0x28E4 = {23454, 2, 0}, 0x28E5 = {23456, 2, 0}, 0x28E6 = {23458, 2, 0}, 0x28E7 = {23460, 2, 0}, 0x28E8 = {23462, 2, 0}, 0x28E9 = {23464, 2, 0}, 0x28EA = {23466, 2, 0}, 0x28EB = {23468, 2, 0}, 0x28EC = {23470, 2, 0}, 0x28ED = {23472, 2, 0}, 0x28EE = {23474, 2, 0}, 0x28EF = {23476, 2, 0}, - 0x28F0 = {23478, 2, 0}, 0x28F1 = {23480, 2, 0}, 0x28F2 = {23482, 2, 0}, 0x28F3 = {23484, 2, 0}, 0x28F4 = {23486, 2, 0}, 0x28F5 = {23488, 2, 0}, 0x28F6 = {23490, 2, 0}, 0x28F7 = {23492, 2, 0}, 0x28F8 = {23494, 2, 0}, 0x28F9 = {23496, 2, 0}, 0x28FA = {23498, 2, 0}, 0x28FB = {23500, 2, 0}, 0x28FC = {23502, 2, 0}, 0x28FD = {23504, 2, 0}, 0x28FE = {23506, 2, 0}, 0x28FF = {23508, 2, 0}, - 0x2900 = {23510, 2, 0}, 0x2901 = {23512, 2, 0}, 0x2902 = {23514, 2, 0}, 0x2903 = {23516, 2, 0}, 0x2904 = {23518, 2, 0}, 0x2905 = {23520, 2, 0}, 0x2906 = {23522, 2, 0}, 0x2907 = {23524, 2, 0}, 0x2908 = {23526, 2, 0}, 0x2909 = {23528, 2, 0}, 0x290A = {23530, 2, 0}, 0x290B = {23532, 2, 0}, 0x290C = {23534, 2, 0}, 0x290D = {23536, 2, 0}, 0x290E = {23538, 2, 0}, 0x290F = {23540, 2, 0}, - 0x2910 = {23542, 2, 0}, 0x2911 = {23544, 2, 0}, 0x2912 = {23546, 2, 0}, 0x2913 = {23548, 2, 0}, 0x2914 = {23550, 2, 0}, 0x2915 = {23552, 2, 0}, 0x2916 = {23554, 2, 0}, 0x2917 = {23556, 2, 0}, 0x2918 = {23558, 2, 0}, 0x2919 = {23560, 2, 0}, 0x291A = {23562, 2, 0}, 0x291B = {23564, 2, 0}, 0x291C = {23566, 2, 0}, 0x291D = {23568, 2, 0}, 0x291E = {23570, 2, 0}, 0x291F = {23572, 2, 0}, - 0x2920 = {23574, 2, 0}, 0x2921 = {23576, 2, 0}, 0x2922 = {23578, 2, 0}, 0x2923 = {23580, 2, 0}, 0x2924 = {23582, 2, 0}, 0x2925 = {23584, 2, 0}, 0x2926 = {23586, 2, 0}, 0x2927 = {23588, 2, 0}, 0x2928 = {23590, 2, 0}, 0x2929 = {23592, 2, 0}, 0x292A = {23594, 2, 0}, 0x292B = {23596, 2, 0}, 0x292C = {23598, 2, 0}, 0x292D = {23600, 2, 0}, 0x292E = {23602, 2, 0}, 0x292F = {23604, 2, 0}, - 0x2930 = {23606, 2, 0}, 0x2931 = {23608, 2, 0}, 0x2932 = {23610, 2, 0}, 0x2933 = {23612, 2, 0}, 0x2934 = {23614, 2, 0}, 0x2935 = {23616, 2, 0}, 0x2936 = {23618, 2, 0}, 0x2937 = {23620, 2, 0}, 0x2938 = {23622, 2, 0}, 0x2939 = {23624, 2, 0}, 0x293A = {23626, 2, 0}, 0x293B = {23628, 2, 0}, 0x293C = {23630, 2, 0}, 0x293D = {23632, 2, 0}, 0x293E = {23634, 2, 0}, 0x293F = {23636, 2, 0}, - 0x2940 = {23638, 2, 0}, 0x2941 = {23640, 2, 0}, 0x2942 = {23642, 2, 0}, 0x2943 = {23644, 2, 0}, 0x2944 = {23646, 2, 0}, 0x2945 = {23648, 2, 0}, 0x2946 = {23650, 2, 0}, 0x2947 = {23652, 2, 0}, 0x2948 = {23654, 2, 0}, 0x2949 = {23656, 2, 0}, 0x294A = {23658, 2, 0}, 0x294B = {23660, 2, 0}, 0x294C = {23662, 2, 0}, 0x294D = {23664, 2, 0}, 0x294E = {23666, 2, 0}, 0x294F = {23668, 2, 0}, - 0x2950 = {23670, 2, 0}, 0x2951 = {23672, 2, 0}, 0x2952 = {23674, 2, 0}, 0x2953 = {23676, 2, 0}, 0x2954 = {23678, 2, 0}, 0x2955 = {23680, 2, 0}, 0x2956 = {23682, 2, 0}, 0x2957 = {23684, 2, 0}, 0x2958 = {23686, 2, 0}, 0x2959 = {23688, 2, 0}, 0x295A = {23690, 2, 0}, 0x295B = {23692, 2, 0}, 0x295C = {23694, 2, 0}, 0x295D = {23696, 2, 0}, 0x295E = {23698, 2, 0}, 0x295F = {23700, 2, 0}, - 0x2960 = {23702, 2, 0}, 0x2961 = {23704, 2, 0}, 0x2962 = {23706, 2, 0}, 0x2963 = {23708, 2, 0}, 0x2964 = {23710, 2, 0}, 0x2965 = {23712, 2, 0}, 0x2966 = {23714, 2, 0}, 0x2967 = {23716, 2, 0}, 0x2968 = {23718, 2, 0}, 0x2969 = {23720, 2, 0}, 0x296A = {23722, 2, 0}, 0x296B = {23724, 2, 0}, 0x296C = {23726, 2, 0}, 0x296D = {23728, 2, 0}, 0x296E = {23730, 2, 0}, 0x296F = {23732, 2, 0}, - 0x2970 = {23734, 2, 0}, 0x2971 = {23736, 2, 0}, 0x2972 = {23738, 2, 0}, 0x2973 = {23740, 2, 0}, 0x2974 = {23742, 2, 0}, 0x2975 = {23744, 2, 0}, 0x2976 = {23746, 2, 0}, 0x2977 = {23748, 2, 0}, 0x2978 = {23750, 2, 0}, 0x2979 = {23752, 2, 0}, 0x297A = {23754, 2, 0}, 0x297B = {23756, 2, 0}, 0x297C = {23758, 2, 0}, 0x297D = {23760, 2, 0}, 0x297E = {23762, 2, 0}, 0x297F = {23764, 2, 0}, - 0x2980 = {23766, 2, 0}, 0x2981 = {23768, 2, 0}, 0x2982 = {23770, 2, 0}, 0x2983 = {23772, 2, 0}, 0x2984 = {23774, 2, 0}, 0x2985 = {23776, 2, 0}, 0x2986 = {23778, 2, 0}, 0x2987 = {23780, 2, 0}, 0x2988 = {23782, 2, 0}, 0x2989 = {23784, 2, 0}, 0x298A = {23786, 2, 0}, 0x298B = {23788, 2, 0}, 0x298C = {23790, 2, 0}, 0x298D = {23792, 2, 0}, 0x298E = {23794, 2, 0}, 0x298F = {23796, 2, 0}, - 0x2990 = {23798, 2, 0}, 0x2991 = {23800, 2, 0}, 0x2992 = {23802, 2, 0}, 0x2993 = {23804, 2, 0}, 0x2994 = {23806, 2, 0}, 0x2995 = {23808, 2, 0}, 0x2996 = {23810, 2, 0}, 0x2997 = {23812, 2, 0}, 0x2998 = {23814, 2, 0}, 0x2999 = {23816, 2, 0}, 0x299A = {23818, 2, 0}, 0x299B = {23820, 2, 0}, 0x299C = {23822, 2, 0}, 0x299D = {23824, 2, 0}, 0x299E = {23826, 2, 0}, 0x299F = {23828, 2, 0}, - 0x29A0 = {23830, 2, 0}, 0x29A1 = {23832, 2, 0}, 0x29A2 = {23834, 2, 0}, 0x29A3 = {23836, 2, 0}, 0x29A4 = {23838, 2, 0}, 0x29A5 = {23840, 2, 0}, 0x29A6 = {23842, 2, 0}, 0x29A7 = {23844, 2, 0}, 0x29A8 = {23846, 2, 0}, 0x29A9 = {23848, 2, 0}, 0x29AA = {23850, 2, 0}, 0x29AB = {23852, 2, 0}, 0x29AC = {23854, 2, 0}, 0x29AD = {23856, 2, 0}, 0x29AE = {23858, 2, 0}, 0x29AF = {23860, 2, 0}, - 0x29B0 = {23862, 2, 0}, 0x29B1 = {23864, 2, 0}, 0x29B2 = {23866, 2, 0}, 0x29B3 = {23868, 2, 0}, 0x29B4 = {23870, 2, 0}, 0x29B5 = {23872, 2, 0}, 0x29B6 = {23874, 2, 0}, 0x29B7 = {23876, 2, 0}, 0x29B8 = {23878, 2, 0}, 0x29B9 = {23880, 2, 0}, 0x29BA = {23882, 2, 0}, 0x29BB = {23884, 2, 0}, 0x29BC = {23886, 2, 0}, 0x29BD = {23888, 2, 0}, 0x29BE = {23890, 2, 0}, 0x29BF = {23892, 2, 0}, - 0x29C0 = {23894, 2, 0}, 0x29C1 = {23896, 2, 0}, 0x29C2 = {23898, 2, 0}, 0x29C3 = {23900, 2, 0}, 0x29C4 = {23902, 2, 0}, 0x29C5 = {23904, 2, 0}, 0x29C6 = {23906, 2, 0}, 0x29C7 = {23908, 2, 0}, 0x29C8 = {23910, 2, 0}, 0x29C9 = {23912, 2, 0}, 0x29CA = {23914, 2, 0}, 0x29CB = {23916, 2, 0}, 0x29CC = {23918, 2, 0}, 0x29CD = {23920, 2, 0}, 0x29CE = {23922, 2, 0}, 0x29CF = {23924, 2, 0}, - 0x29D0 = {23926, 2, 0}, 0x29D1 = {23928, 2, 0}, 0x29D2 = {23930, 2, 0}, 0x29D3 = {23932, 2, 0}, 0x29D4 = {23934, 2, 0}, 0x29D5 = {23936, 2, 0}, 0x29D6 = {23938, 2, 0}, 0x29D7 = {23940, 2, 0}, 0x29D8 = {23942, 2, 0}, 0x29D9 = {23944, 2, 0}, 0x29DA = {23946, 2, 0}, 0x29DB = {23948, 2, 0}, 0x29DC = {23950, 2, 0}, 0x29DD = {23952, 2, 0}, 0x29DE = {23954, 2, 0}, 0x29DF = {23956, 2, 0}, - 0x29E0 = {23958, 2, 0}, 0x29E1 = {23960, 2, 0}, 0x29E2 = {23962, 2, 0}, 0x29E3 = {23964, 2, 0}, 0x29E4 = {23966, 2, 0}, 0x29E5 = {23968, 2, 0}, 0x29E6 = {23970, 2, 0}, 0x29E7 = {23972, 2, 0}, 0x29E8 = {23974, 2, 0}, 0x29E9 = {23976, 2, 0}, 0x29EA = {23978, 2, 0}, 0x29EB = {23980, 2, 0}, 0x29EC = {23982, 2, 0}, 0x29ED = {23984, 2, 0}, 0x29EE = {23986, 2, 0}, 0x29EF = {23988, 2, 0}, - 0x29F0 = {23990, 2, 0}, 0x29F1 = {23992, 2, 0}, 0x29F2 = {23994, 2, 0}, 0x29F3 = {23996, 2, 0}, 0x29F4 = {23998, 2, 0}, 0x29F5 = {24000, 2, 0}, 0x29F6 = {24002, 2, 0}, 0x29F7 = {24004, 2, 0}, 0x29F8 = {24006, 2, 0}, 0x29F9 = {24008, 2, 0}, 0x29FA = {24010, 2, 0}, 0x29FB = {24012, 2, 0}, 0x29FC = {24014, 2, 0}, 0x29FD = {24016, 2, 0}, 0x29FE = {24018, 2, 0}, 0x29FF = {24020, 2, 0}, - 0x2A00 = {24022, 3, 0}, 0x2A01 = {24025, 3, 0}, 0x2A02 = {24028, 3, 0}, 0x2A03 = {24031, 3, 0}, 0x2A04 = {24034, 3, 0}, 0x2A05 = {24037, 3, 0}, 0x2A06 = {24040, 3, 0}, 0x2A07 = {24043, 3, 0}, 0x2A08 = {24046, 3, 0}, 0x2A09 = {24049, 3, 0}, 0x2A0A = {24052, 3, 0}, 0x2A0B = {24055, 3, 0}, 0x2A0C = {24058, 3, 0}, 0x2A0D = {24061, 3, 0}, 0x2A0E = {24064, 3, 0}, 0x2A0F = {24067, 3, 0}, - 0x2A10 = {24070, 3, 0}, 0x2A11 = {24073, 3, 0}, 0x2A12 = {24076, 3, 0}, 0x2A13 = {24079, 3, 0}, 0x2A14 = {24082, 3, 0}, 0x2A15 = {24085, 3, 0}, 0x2A16 = {24088, 3, 0}, 0x2A17 = {24091, 3, 0}, 0x2A18 = {24094, 3, 0}, 0x2A19 = {24097, 3, 0}, 0x2A1A = {24100, 3, 0}, 0x2A1B = {24103, 3, 0}, 0x2A1C = {24106, 3, 0}, 0x2A1D = {24109, 3, 0}, 0x2A1E = {24112, 3, 0}, 0x2A1F = {24115, 3, 0}, - 0x2A20 = {24118, 3, 0}, 0x2A21 = {24121, 3, 0}, 0x2A22 = {24124, 3, 0}, 0x2A23 = {24127, 3, 0}, 0x2A24 = {24130, 3, 0}, 0x2A25 = {24133, 3, 0}, 0x2A26 = {24136, 3, 0}, 0x2A27 = {24139, 3, 0}, 0x2A28 = {24142, 3, 0}, 0x2A29 = {24145, 3, 0}, 0x2A2A = {24148, 3, 0}, 0x2A2B = {24151, 3, 0}, 0x2A2C = {24154, 3, 0}, 0x2A2D = {24157, 3, 0}, 0x2A2E = {24160, 3, 0}, 0x2A2F = {24163, 3, 0}, - 0x2A30 = {24166, 3, 0}, 0x2A31 = {24169, 3, 0}, 0x2A32 = {24172, 3, 0}, 0x2A33 = {24175, 3, 0}, 0x2A34 = {24178, 3, 0}, 0x2A35 = {24181, 3, 0}, 0x2A36 = {24184, 3, 0}, 0x2A37 = {24187, 3, 0}, 0x2A38 = {24190, 3, 0}, 0x2A39 = {24193, 3, 0}, 0x2A3A = {24196, 3, 0}, 0x2A3B = {24199, 3, 0}, 0x2A3C = {24202, 3, 0}, 0x2A3D = {24205, 3, 0}, 0x2A3E = {24208, 3, 0}, 0x2A3F = {24211, 3, 0}, - 0x2A40 = {24214, 3, 0}, 0x2A41 = {24217, 3, 0}, 0x2A42 = {24220, 3, 0}, 0x2A43 = {24223, 3, 0}, 0x2A44 = {24226, 3, 0}, 0x2A45 = {24229, 3, 0}, 0x2A46 = {24232, 3, 0}, 0x2A47 = {24235, 3, 0}, 0x2A48 = {24238, 3, 0}, 0x2A49 = {24241, 3, 0}, 0x2A4A = {24244, 3, 0}, 0x2A4B = {24247, 3, 0}, 0x2A4C = {24250, 3, 0}, 0x2A4D = {24253, 3, 0}, 0x2A4E = {24256, 3, 0}, 0x2A4F = {24259, 3, 0}, - 0x2A50 = {24262, 3, 0}, 0x2A51 = {24265, 3, 0}, 0x2A52 = {24268, 3, 0}, 0x2A53 = {24271, 3, 0}, 0x2A54 = {24274, 3, 0}, 0x2A55 = {24277, 3, 0}, 0x2A56 = {24280, 3, 0}, 0x2A57 = {24283, 3, 0}, 0x2A58 = {24286, 3, 0}, 0x2A59 = {24289, 3, 0}, 0x2A5A = {24292, 3, 0}, 0x2A5B = {24295, 3, 0}, 0x2A5C = {24298, 3, 0}, 0x2A5D = {24301, 3, 0}, 0x2A5E = {24304, 3, 0}, 0x2A5F = {24307, 3, 0}, - 0x2A60 = {24310, 3, 0}, 0x2A61 = {24313, 3, 0}, 0x2A62 = {24316, 3, 0}, 0x2A63 = {24319, 3, 0}, 0x2A64 = {24322, 3, 0}, 0x2A65 = {24325, 3, 0}, 0x2A66 = {24328, 3, 0}, 0x2A67 = {24331, 3, 0}, 0x2A68 = {24334, 3, 0}, 0x2A69 = {24337, 3, 0}, 0x2A6A = {24340, 3, 0}, 0x2A6B = {24343, 3, 0}, 0x2A6C = {24346, 3, 0}, 0x2A6D = {24349, 3, 0}, 0x2A6E = {24352, 3, 0}, 0x2A6F = {24355, 3, 0}, - 0x2A70 = {24358, 3, 0}, 0x2A71 = {24361, 3, 0}, 0x2A72 = {24364, 3, 0}, 0x2A73 = {24367, 3, 0}, 0x2A74 = {24370, 3, 0}, 0x2A75 = {24373, 3, 0}, 0x2A76 = {24376, 3, 0}, 0x2A77 = {24379, 3, 0}, 0x2A78 = {24382, 3, 0}, 0x2A79 = {24385, 3, 0}, 0x2A7A = {24388, 3, 0}, 0x2A7B = {24391, 3, 0}, 0x2A7C = {24394, 3, 0}, 0x2A7D = {24397, 3, 0}, 0x2A7E = {24400, 3, 0}, 0x2A7F = {24403, 3, 0}, - 0x2A80 = {24406, 3, 0}, 0x2A81 = {24409, 3, 0}, 0x2A82 = {24412, 3, 0}, 0x2A83 = {24415, 3, 0}, 0x2A84 = {24418, 3, 0}, 0x2A85 = {24421, 3, 0}, 0x2A86 = {24424, 3, 0}, 0x2A87 = {24427, 3, 0}, 0x2A88 = {24430, 3, 0}, 0x2A89 = {24433, 3, 0}, 0x2A8A = {24436, 3, 0}, 0x2A8B = {24439, 3, 0}, 0x2A8C = {24442, 3, 0}, 0x2A8D = {24445, 3, 0}, 0x2A8E = {24448, 3, 0}, 0x2A8F = {24451, 3, 0}, - 0x2A90 = {24454, 3, 0}, 0x2A91 = {24457, 3, 0}, 0x2A92 = {24460, 3, 0}, 0x2A93 = {24463, 3, 0}, 0x2A94 = {24466, 3, 0}, 0x2A95 = {24469, 3, 0}, 0x2A96 = {24472, 3, 0}, 0x2A97 = {24475, 3, 0}, 0x2A98 = {24478, 3, 0}, 0x2A99 = {24481, 3, 0}, 0x2A9A = {24484, 3, 0}, 0x2A9B = {24487, 3, 0}, 0x2A9C = {24490, 3, 0}, 0x2A9D = {24493, 3, 0}, 0x2A9E = {24496, 3, 0}, 0x2A9F = {24499, 3, 0}, - 0x2AA0 = {24502, 3, 0}, 0x2AA1 = {24505, 3, 0}, 0x2AA2 = {24508, 3, 0}, 0x2AA3 = {24511, 3, 0}, 0x2AA4 = {24514, 3, 0}, 0x2AA5 = {24517, 3, 0}, 0x2AA6 = {24520, 3, 0}, 0x2AA7 = {24523, 3, 0}, 0x2AA8 = {24526, 3, 0}, 0x2AA9 = {24529, 3, 0}, 0x2AAA = {24532, 3, 0}, 0x2AAB = {24535, 3, 0}, 0x2AAC = {24538, 3, 0}, 0x2AAD = {24541, 3, 0}, 0x2AAE = {24544, 3, 0}, 0x2AAF = {24547, 3, 0}, - 0x2AB0 = {24550, 3, 0}, 0x2AB1 = {24553, 3, 0}, 0x2AB2 = {24556, 3, 0}, 0x2AB3 = {24559, 3, 0}, 0x2AB4 = {24562, 3, 0}, 0x2AB5 = {24565, 3, 0}, 0x2AB6 = {24568, 3, 0}, 0x2AB7 = {24571, 3, 0}, 0x2AB8 = {24574, 3, 0}, 0x2AB9 = {24577, 3, 0}, 0x2ABA = {24580, 3, 0}, 0x2ABB = {24583, 3, 0}, 0x2ABC = {24586, 3, 0}, 0x2ABD = {24589, 3, 0}, 0x2ABE = {24592, 3, 0}, 0x2ABF = {24595, 3, 0}, - 0x2AC0 = {24598, 3, 0}, 0x2AC1 = {24601, 3, 0}, 0x2AC2 = {24604, 3, 0}, 0x2AC3 = {24607, 3, 0}, 0x2AC4 = {24610, 3, 0}, 0x2AC5 = {24613, 3, 0}, 0x2AC6 = {24616, 3, 0}, 0x2AC7 = {24619, 3, 0}, 0x2AC8 = {24622, 3, 0}, 0x2AC9 = {24625, 3, 0}, 0x2ACA = {24628, 3, 0}, 0x2ACB = {24631, 3, 0}, 0x2ACC = {24634, 3, 0}, 0x2ACD = {24637, 3, 0}, 0x2ACE = {24640, 3, 0}, 0x2ACF = {24643, 3, 0}, - 0x2AD0 = {24646, 3, 0}, 0x2AD1 = {24649, 3, 0}, 0x2AD2 = {24652, 3, 0}, 0x2AD3 = {24655, 3, 0}, 0x2AD4 = {24658, 3, 0}, 0x2AD5 = {24661, 3, 0}, 0x2AD6 = {24664, 3, 0}, 0x2AD7 = {24667, 3, 0}, 0x2AD8 = {24670, 3, 0}, 0x2AD9 = {24673, 3, 0}, 0x2ADA = {24676, 3, 0}, 0x2ADB = {24679, 3, 0}, 0x2ADC = {24682, 3, 0}, 0x2ADD = {24685, 3, 0}, 0x2ADE = {24688, 3, 0}, 0x2ADF = {24691, 3, 0}, - 0x2AE0 = {24694, 3, 0}, 0x2AE1 = {24697, 3, 0}, 0x2AE2 = {24700, 3, 0}, 0x2AE3 = {24703, 3, 0}, 0x2AE4 = {24706, 3, 0}, 0x2AE5 = {24709, 3, 0}, 0x2AE6 = {24712, 3, 0}, 0x2AE7 = {24715, 3, 0}, 0x2AE8 = {24718, 3, 0}, 0x2AE9 = {24721, 3, 0}, 0x2AEA = {24724, 3, 0}, 0x2AEB = {24727, 3, 0}, 0x2AEC = {24730, 3, 0}, 0x2AED = {24733, 3, 0}, 0x2AEE = {24736, 3, 0}, 0x2AEF = {24739, 3, 0}, - 0x2AF0 = {24742, 3, 0}, 0x2AF1 = {24745, 3, 0}, 0x2AF2 = {24748, 3, 0}, 0x2AF3 = {24751, 3, 0}, 0x2AF4 = {24754, 3, 0}, 0x2AF5 = {24757, 3, 0}, 0x2AF6 = {24760, 3, 0}, 0x2AF7 = {24763, 3, 0}, 0x2AF8 = {24766, 3, 0}, 0x2AF9 = {24769, 3, 0}, 0x2AFA = {24772, 3, 0}, 0x2AFB = {24775, 3, 0}, 0x2AFC = {24778, 3, 0}, 0x2AFD = {24781, 3, 0}, 0x2AFE = {24784, 3, 0}, 0x2AFF = {24787, 3, 0}, - 0x2B00 = {24790, 2, 0}, 0x2B01 = {24792, 2, 0}, 0x2B02 = {24794, 2, 0}, 0x2B03 = {24796, 2, 0}, 0x2B04 = {24798, 2, 0}, 0x2B05 = {24800, 2, 0}, 0x2B06 = {24802, 2, 0}, 0x2B07 = {24804, 2, 0}, 0x2B08 = {24806, 2, 0}, 0x2B09 = {24808, 2, 0}, 0x2B0A = {24810, 2, 0}, 0x2B0B = {24812, 2, 0}, 0x2B0C = {24814, 2, 0}, 0x2B0D = {24816, 2, 0}, 0x2B0E = {24818, 2, 0}, 0x2B0F = {24820, 2, 0}, - 0x2B10 = {24822, 2, 0}, 0x2B11 = {24824, 2, 0}, 0x2B12 = {24826, 2, 0}, 0x2B13 = {24828, 2, 0}, 0x2B14 = {24830, 2, 0}, 0x2B15 = {24832, 2, 0}, 0x2B16 = {24834, 2, 0}, 0x2B17 = {24836, 2, 0}, 0x2B18 = {24838, 2, 0}, 0x2B19 = {24840, 2, 0}, 0x2B1A = {24842, 2, 0}, 0x2B1B = {24844, 2, 0}, 0x2B1C = {24846, 2, 0}, 0x2B1D = {24848, 2, 0}, 0x2B1E = {24850, 2, 0}, 0x2B1F = {24852, 2, 0}, - 0x2B20 = {24854, 2, 0}, 0x2B21 = {24856, 2, 0}, 0x2B22 = {24858, 2, 0}, 0x2B23 = {24860, 2, 0}, 0x2B24 = {24862, 2, 0}, 0x2B25 = {24864, 2, 0}, 0x2B26 = {24866, 2, 0}, 0x2B27 = {24868, 2, 0}, 0x2B28 = {24870, 2, 0}, 0x2B29 = {24872, 2, 0}, 0x2B2A = {24874, 2, 0}, 0x2B2B = {24876, 2, 0}, 0x2B2C = {24878, 2, 0}, 0x2B2D = {24880, 2, 0}, 0x2B2E = {24882, 2, 0}, 0x2B2F = {24884, 2, 0}, - 0x2B30 = {24886, 2, 0}, 0x2B31 = {24888, 2, 0}, 0x2B32 = {24890, 2, 0}, 0x2B33 = {24892, 2, 0}, 0x2B34 = {24894, 2, 0}, 0x2B35 = {24896, 2, 0}, 0x2B36 = {24898, 2, 0}, 0x2B37 = {24900, 2, 0}, 0x2B38 = {24902, 2, 0}, 0x2B39 = {24904, 2, 0}, 0x2B3A = {24906, 2, 0}, 0x2B3B = {24908, 2, 0}, 0x2B3C = {24910, 2, 0}, 0x2B3D = {24912, 2, 0}, 0x2B3E = {24914, 2, 0}, 0x2B3F = {24916, 2, 0}, - 0x2B40 = {24918, 2, 0}, 0x2B41 = {24920, 2, 0}, 0x2B42 = {24922, 2, 0}, 0x2B43 = {24924, 2, 0}, 0x2B44 = {24926, 2, 0}, 0x2B45 = {24928, 2, 0}, 0x2B46 = {24930, 2, 0}, 0x2B47 = {24932, 2, 0}, 0x2B48 = {24934, 2, 0}, 0x2B49 = {24936, 2, 0}, 0x2B4A = {24938, 2, 0}, 0x2B4B = {24940, 2, 0}, 0x2B4C = {24942, 2, 0}, 0x2B4D = {24944, 2, 0}, 0x2B4E = {24946, 2, 0}, 0x2B4F = {24948, 2, 0}, - 0x2B50 = {24950, 2, 0}, 0x2B51 = {24952, 2, 0}, 0x2B52 = {24954, 2, 0}, 0x2B53 = {24956, 2, 0}, 0x2B54 = {24958, 2, 0}, 0x2B55 = {24960, 2, 0}, 0x2B56 = {24962, 2, 0}, 0x2B57 = {24964, 2, 0}, 0x2B58 = {24966, 2, 0}, 0x2B59 = {24968, 2, 0}, 0x2B5A = {24970, 2, 0}, 0x2B5B = {24972, 2, 0}, 0x2B5C = {24974, 2, 0}, 0x2B5D = {24976, 2, 0}, 0x2B5E = {24978, 2, 0}, 0x2B5F = {24980, 2, 0}, - 0x2B60 = {24982, 2, 0}, 0x2B61 = {24984, 2, 0}, 0x2B62 = {24986, 2, 0}, 0x2B63 = {24988, 2, 0}, 0x2B64 = {24990, 2, 0}, 0x2B65 = {24992, 2, 0}, 0x2B66 = {24994, 2, 0}, 0x2B67 = {24996, 2, 0}, 0x2B68 = {24998, 2, 0}, 0x2B69 = {25000, 2, 0}, 0x2B6A = {25002, 2, 0}, 0x2B6B = {25004, 2, 0}, 0x2B6C = {25006, 2, 0}, 0x2B6D = {25008, 2, 0}, 0x2B6E = {25010, 2, 0}, 0x2B6F = {25012, 2, 0}, - 0x2B70 = {25014, 2, 0}, 0x2B71 = {25016, 2, 0}, 0x2B72 = {25018, 2, 0}, 0x2B73 = {25020, 2, 0}, 0x2B74 = {25022, 2, 0}, 0x2B75 = {25024, 2, 0}, 0x2B76 = {25026, 2, 0}, 0x2B77 = {25028, 2, 0}, 0x2B78 = {25030, 2, 0}, 0x2B79 = {25032, 2, 0}, 0x2B7A = {25034, 2, 0}, 0x2B7B = {25036, 2, 0}, 0x2B7C = {25038, 2, 0}, 0x2B7D = {25040, 2, 0}, 0x2B7E = {25042, 2, 0}, 0x2B7F = {25044, 2, 0}, - 0x2B80 = {25046, 2, 0}, 0x2B81 = {25048, 2, 0}, 0x2B82 = {25050, 2, 0}, 0x2B83 = {25052, 2, 0}, 0x2B84 = {25054, 2, 0}, 0x2B85 = {25056, 2, 0}, 0x2B86 = {25058, 2, 0}, 0x2B87 = {25060, 2, 0}, 0x2B88 = {25062, 2, 0}, 0x2B89 = {25064, 2, 0}, 0x2B8A = {25066, 2, 0}, 0x2B8B = {25068, 2, 0}, 0x2B8C = {25070, 2, 0}, 0x2B8D = {25072, 2, 0}, 0x2B8E = {25074, 2, 0}, 0x2B8F = {25076, 2, 0}, - 0x2B90 = {25078, 2, 0}, 0x2B91 = {25080, 2, 0}, 0x2B92 = {25082, 2, 0}, 0x2B93 = {25084, 2, 0}, 0x2B94 = {25086, 2, 0}, 0x2B95 = {25088, 2, 0}, 0x2B96 = {25090, 2, 0}, 0x2B97 = {25092, 2, 0}, 0x2B98 = {25094, 2, 0}, 0x2B99 = {25096, 2, 0}, 0x2B9A = {25098, 2, 0}, 0x2B9B = {25100, 2, 0}, 0x2B9C = {25102, 2, 0}, 0x2B9D = {25104, 2, 0}, 0x2B9E = {25106, 2, 0}, 0x2B9F = {25108, 2, 0}, - 0x2BA0 = {25110, 2, 0}, 0x2BA1 = {25112, 2, 0}, 0x2BA2 = {25114, 2, 0}, 0x2BA3 = {25116, 2, 0}, 0x2BA4 = {25118, 2, 0}, 0x2BA5 = {25120, 2, 0}, 0x2BA6 = {25122, 2, 0}, 0x2BA7 = {25124, 2, 0}, 0x2BA8 = {25126, 2, 0}, 0x2BA9 = {25128, 2, 0}, 0x2BAA = {25130, 2, 0}, 0x2BAB = {25132, 2, 0}, 0x2BAC = {25134, 2, 0}, 0x2BAD = {25136, 2, 0}, 0x2BAE = {25138, 2, 0}, 0x2BAF = {25140, 2, 0}, - 0x2BB0 = {25142, 2, 0}, 0x2BB1 = {25144, 2, 0}, 0x2BB2 = {25146, 2, 0}, 0x2BB3 = {25148, 2, 0}, 0x2BB4 = {25150, 2, 0}, 0x2BB5 = {25152, 2, 0}, 0x2BB6 = {25154, 2, 0}, 0x2BB7 = {25156, 2, 0}, 0x2BB8 = {25158, 2, 0}, 0x2BB9 = {25160, 2, 0}, 0x2BBA = {25162, 2, 0}, 0x2BBB = {25164, 2, 0}, 0x2BBC = {25166, 2, 0}, 0x2BBD = {25168, 2, 0}, 0x2BBE = {25170, 2, 0}, 0x2BBF = {25172, 2, 0}, - 0x2BC0 = {25174, 2, 0}, 0x2BC1 = {25176, 2, 0}, 0x2BC2 = {25178, 2, 0}, 0x2BC3 = {25180, 2, 0}, 0x2BC4 = {25182, 2, 0}, 0x2BC5 = {25184, 2, 0}, 0x2BC6 = {25186, 2, 0}, 0x2BC7 = {25188, 2, 0}, 0x2BC8 = {25190, 2, 0}, 0x2BC9 = {25192, 2, 0}, 0x2BCA = {25194, 2, 0}, 0x2BCB = {25196, 2, 0}, 0x2BCC = {25198, 2, 0}, 0x2BCD = {25200, 2, 0}, 0x2BCE = {25202, 2, 0}, 0x2BCF = {25204, 2, 0}, - 0x2BD0 = {25206, 2, 0}, 0x2BD1 = {25208, 2, 0}, 0x2BD2 = {25210, 2, 0}, 0x2BD3 = {25212, 2, 0}, 0x2BD4 = {25214, 2, 0}, 0x2BD5 = {25216, 2, 0}, 0x2BD6 = {25218, 2, 0}, 0x2BD7 = {25220, 2, 0}, 0x2BD8 = {25222, 2, 0}, 0x2BD9 = {25224, 2, 0}, 0x2BDA = {25226, 2, 0}, 0x2BDB = {25228, 2, 0}, 0x2BDC = {25230, 2, 0}, 0x2BDD = {25232, 2, 0}, 0x2BDE = {25234, 2, 0}, 0x2BDF = {25236, 2, 0}, - 0x2BE0 = {25238, 2, 0}, 0x2BE1 = {25240, 2, 0}, 0x2BE2 = {25242, 2, 0}, 0x2BE3 = {25244, 2, 0}, 0x2BE4 = {25246, 2, 0}, 0x2BE5 = {25248, 2, 0}, 0x2BE6 = {25250, 2, 0}, 0x2BE7 = {25252, 2, 0}, 0x2BE8 = {25254, 2, 0}, 0x2BE9 = {25256, 2, 0}, 0x2BEA = {25258, 2, 0}, 0x2BEB = {25260, 2, 0}, 0x2BEC = {25262, 2, 0}, 0x2BED = {25264, 2, 0}, 0x2BEE = {25266, 2, 0}, 0x2BEF = {25268, 2, 0}, - 0x2BF0 = {25270, 2, 0}, 0x2BF1 = {25272, 2, 0}, 0x2BF2 = {25274, 2, 0}, 0x2BF3 = {25276, 2, 0}, 0x2BF4 = {25278, 2, 0}, 0x2BF5 = {25280, 2, 0}, 0x2BF6 = {25282, 2, 0}, 0x2BF7 = {25284, 2, 0}, 0x2BF8 = {25286, 2, 0}, 0x2BF9 = {25288, 2, 0}, 0x2BFA = {25290, 2, 0}, 0x2BFB = {25292, 2, 0}, 0x2BFC = {25294, 2, 0}, 0x2BFD = {25296, 2, 0}, 0x2BFE = {25298, 2, 0}, 0x2BFF = {25300, 2, 0}, - 0x2C00 = {25302, 2, 0}, 0x2C01 = {25304, 2, 0}, 0x2C02 = {25306, 2, 0}, 0x2C03 = {25308, 2, 0}, 0x2C04 = {25310, 2, 0}, 0x2C05 = {25312, 2, 0}, 0x2C06 = {25314, 2, 0}, 0x2C07 = {25316, 2, 0}, 0x2C08 = {25318, 2, 0}, 0x2C09 = {25320, 2, 0}, 0x2C0A = {25322, 2, 0}, 0x2C0B = {25324, 2, 0}, 0x2C0C = {25326, 2, 0}, 0x2C0D = {25328, 2, 0}, 0x2C0E = {25330, 2, 0}, 0x2C0F = {25332, 2, 0}, - 0x2C10 = {25334, 2, 0}, 0x2C11 = {25336, 2, 0}, 0x2C12 = {25338, 2, 0}, 0x2C13 = {25340, 2, 0}, 0x2C14 = {25342, 2, 0}, 0x2C15 = {25344, 2, 0}, 0x2C16 = {25346, 2, 0}, 0x2C17 = {25348, 2, 0}, 0x2C18 = {25350, 2, 0}, 0x2C19 = {25352, 2, 0}, 0x2C1A = {25354, 2, 0}, 0x2C1B = {25356, 2, 0}, 0x2C1C = {25358, 2, 0}, 0x2C1D = {25360, 2, 0}, 0x2C1E = {25362, 2, 0}, 0x2C1F = {25364, 2, 0}, - 0x2C20 = {25366, 2, 0}, 0x2C21 = {25368, 2, 0}, 0x2C22 = {25370, 2, 0}, 0x2C23 = {25372, 2, 0}, 0x2C24 = {25374, 2, 0}, 0x2C25 = {25376, 2, 0}, 0x2C26 = {25378, 2, 0}, 0x2C27 = {25380, 2, 0}, 0x2C28 = {25382, 2, 0}, 0x2C29 = {25384, 2, 0}, 0x2C2A = {25386, 2, 0}, 0x2C2B = {25388, 2, 0}, 0x2C2C = {25390, 2, 0}, 0x2C2D = {25392, 2, 0}, 0x2C2E = {25394, 2, 0}, 0x2C2F = {25396, 2, 0}, - 0x2C30 = {25398, 2, 0}, 0x2C31 = {25400, 2, 0}, 0x2C32 = {25402, 2, 0}, 0x2C33 = {25404, 2, 0}, 0x2C34 = {25406, 2, 0}, 0x2C35 = {25408, 2, 0}, 0x2C36 = {25410, 2, 0}, 0x2C37 = {25412, 2, 0}, 0x2C38 = {25414, 2, 0}, 0x2C39 = {25416, 2, 0}, 0x2C3A = {25418, 2, 0}, 0x2C3B = {25420, 2, 0}, 0x2C3C = {25422, 2, 0}, 0x2C3D = {25424, 2, 0}, 0x2C3E = {25426, 2, 0}, 0x2C3F = {25428, 2, 0}, - 0x2C40 = {25430, 2, 0}, 0x2C41 = {25432, 2, 0}, 0x2C42 = {25434, 2, 0}, 0x2C43 = {25436, 2, 0}, 0x2C44 = {25438, 2, 0}, 0x2C45 = {25440, 2, 0}, 0x2C46 = {25442, 2, 0}, 0x2C47 = {25444, 2, 0}, 0x2C48 = {25446, 2, 0}, 0x2C49 = {25448, 2, 0}, 0x2C4A = {25450, 2, 0}, 0x2C4B = {25452, 2, 0}, 0x2C4C = {25454, 2, 0}, 0x2C4D = {25456, 2, 0}, 0x2C4E = {25458, 2, 0}, 0x2C4F = {25460, 2, 0}, - 0x2C50 = {25462, 2, 0}, 0x2C51 = {25464, 2, 0}, 0x2C52 = {25466, 2, 0}, 0x2C53 = {25468, 2, 0}, 0x2C54 = {25470, 2, 0}, 0x2C55 = {25472, 2, 0}, 0x2C56 = {25474, 2, 0}, 0x2C57 = {25476, 2, 0}, 0x2C58 = {25478, 2, 0}, 0x2C59 = {25480, 2, 0}, 0x2C5A = {25482, 2, 0}, 0x2C5B = {25484, 2, 0}, 0x2C5C = {25486, 2, 0}, 0x2C5D = {25488, 2, 0}, 0x2C5E = {25490, 2, 0}, 0x2C5F = {25492, 2, 0}, - 0x2C60 = {25494, 2, 0}, 0x2C61 = {25496, 2, 0}, 0x2C62 = {25498, 2, 0}, 0x2C63 = {25500, 2, 0}, 0x2C64 = {25502, 2, 0}, 0x2C65 = {25504, 2, 0}, 0x2C66 = {25506, 2, 0}, 0x2C67 = {25508, 2, 0}, 0x2C68 = {25510, 2, 0}, 0x2C69 = {25512, 2, 0}, 0x2C6A = {25514, 2, 0}, 0x2C6B = {25516, 2, 0}, 0x2C6C = {25518, 2, 0}, 0x2C6D = {25520, 2, 0}, 0x2C6E = {25522, 2, 0}, 0x2C6F = {25524, 2, 0}, - 0x2C70 = {25526, 2, 0}, 0x2C71 = {25528, 2, 0}, 0x2C72 = {25530, 2, 0}, 0x2C73 = {25532, 2, 0}, 0x2C74 = {25534, 2, 0}, 0x2C75 = {25536, 2, 0}, 0x2C76 = {25538, 2, 0}, 0x2C77 = {25540, 2, 0}, 0x2C78 = {25542, 2, 0}, 0x2C79 = {25544, 2, 0}, 0x2C7A = {25546, 2, 0}, 0x2C7B = {25548, 2, 0}, 0x2C7C = {25550, 2, 0}, 0x2C7D = {25552, 2, 0}, 0x2C7E = {25554, 2, 0}, 0x2C7F = {25556, 2, 0}, - 0x2C80 = {25558, 2, 0}, 0x2C81 = {25560, 2, 0}, 0x2C82 = {25562, 2, 0}, 0x2C83 = {25564, 2, 0}, 0x2C84 = {25566, 2, 0}, 0x2C85 = {25568, 2, 0}, 0x2C86 = {25570, 2, 0}, 0x2C87 = {25572, 2, 0}, 0x2C88 = {25574, 2, 0}, 0x2C89 = {25576, 2, 0}, 0x2C8A = {25578, 2, 0}, 0x2C8B = {25580, 2, 0}, 0x2C8C = {25582, 2, 0}, 0x2C8D = {25584, 2, 0}, 0x2C8E = {25586, 2, 0}, 0x2C8F = {25588, 2, 0}, - 0x2C90 = {25590, 2, 0}, 0x2C91 = {25592, 2, 0}, 0x2C92 = {25594, 2, 0}, 0x2C93 = {25596, 2, 0}, 0x2C94 = {25598, 2, 0}, 0x2C95 = {25600, 2, 0}, 0x2C96 = {25602, 2, 0}, 0x2C97 = {25604, 2, 0}, 0x2C98 = {25606, 2, 0}, 0x2C99 = {25608, 2, 0}, 0x2C9A = {25610, 2, 0}, 0x2C9B = {25612, 2, 0}, 0x2C9C = {25614, 2, 0}, 0x2C9D = {25616, 2, 0}, 0x2C9E = {25618, 2, 0}, 0x2C9F = {25620, 2, 0}, - 0x2CA0 = {25622, 2, 0}, 0x2CA1 = {25624, 2, 0}, 0x2CA2 = {25626, 2, 0}, 0x2CA3 = {25628, 2, 0}, 0x2CA4 = {25630, 2, 0}, 0x2CA5 = {25632, 2, 0}, 0x2CA6 = {25634, 2, 0}, 0x2CA7 = {25636, 2, 0}, 0x2CA8 = {25638, 2, 0}, 0x2CA9 = {25640, 2, 0}, 0x2CAA = {25642, 2, 0}, 0x2CAB = {25644, 2, 0}, 0x2CAC = {25646, 2, 0}, 0x2CAD = {25648, 2, 0}, 0x2CAE = {25650, 2, 0}, 0x2CAF = {25652, 2, 0}, - 0x2CB0 = {25654, 2, 0}, 0x2CB1 = {25656, 2, 0}, 0x2CB2 = {25658, 2, 0}, 0x2CB3 = {25660, 2, 0}, 0x2CB4 = {25662, 2, 0}, 0x2CB5 = {25664, 2, 0}, 0x2CB6 = {25666, 2, 0}, 0x2CB7 = {25668, 2, 0}, 0x2CB8 = {25670, 2, 0}, 0x2CB9 = {25672, 2, 0}, 0x2CBA = {25674, 2, 0}, 0x2CBB = {25676, 2, 0}, 0x2CBC = {25678, 2, 0}, 0x2CBD = {25680, 2, 0}, 0x2CBE = {25682, 2, 0}, 0x2CBF = {25684, 2, 0}, - 0x2CC0 = {25686, 2, 0}, 0x2CC1 = {25688, 2, 0}, 0x2CC2 = {25690, 2, 0}, 0x2CC3 = {25692, 2, 0}, 0x2CC4 = {25694, 2, 0}, 0x2CC5 = {25696, 2, 0}, 0x2CC6 = {25698, 2, 0}, 0x2CC7 = {25700, 2, 0}, 0x2CC8 = {25702, 2, 0}, 0x2CC9 = {25704, 2, 0}, 0x2CCA = {25706, 2, 0}, 0x2CCB = {25708, 2, 0}, 0x2CCC = {25710, 2, 0}, 0x2CCD = {25712, 2, 0}, 0x2CCE = {25714, 2, 0}, 0x2CCF = {25716, 2, 0}, - 0x2CD0 = {25718, 2, 0}, 0x2CD1 = {25720, 2, 0}, 0x2CD2 = {25722, 2, 0}, 0x2CD3 = {25724, 2, 0}, 0x2CD4 = {25726, 2, 0}, 0x2CD5 = {25728, 2, 0}, 0x2CD6 = {25730, 2, 0}, 0x2CD7 = {25732, 2, 0}, 0x2CD8 = {25734, 2, 0}, 0x2CD9 = {25736, 2, 0}, 0x2CDA = {25738, 2, 0}, 0x2CDB = {25740, 2, 0}, 0x2CDC = {25742, 2, 0}, 0x2CDD = {25744, 2, 0}, 0x2CDE = {25746, 2, 0}, 0x2CDF = {25748, 2, 0}, - 0x2CE0 = {25750, 2, 0}, 0x2CE1 = {25752, 2, 0}, 0x2CE2 = {25754, 2, 0}, 0x2CE3 = {25756, 2, 0}, 0x2CE4 = {25758, 2, 0}, 0x2CE5 = {25760, 2, 0}, 0x2CE6 = {25762, 2, 0}, 0x2CE7 = {25764, 2, 0}, 0x2CE8 = {25766, 2, 0}, 0x2CE9 = {25768, 2, 0}, 0x2CEA = {25770, 2, 0}, 0x2CEB = {25772, 2, 0}, 0x2CEC = {25774, 2, 0}, 0x2CED = {25776, 2, 0}, 0x2CEE = {25778, 2, 0}, 0x2CEF = {25780, 2, 0}, - 0x2CF0 = {25782, 2, 0}, 0x2CF1 = {25784, 2, 0}, 0x2CF2 = {25786, 2, 0}, 0x2CF3 = {25788, 2, 0}, 0x2CF4 = {25790, 2, 0}, 0x2CF5 = {25792, 2, 0}, 0x2CF6 = {25794, 2, 0}, 0x2CF7 = {25796, 2, 0}, 0x2CF8 = {25798, 2, 0}, 0x2CF9 = {25800, 2, 0}, 0x2CFA = {25802, 2, 0}, 0x2CFB = {25804, 2, 0}, 0x2CFC = {25806, 2, 0}, 0x2CFD = {25808, 2, 0}, 0x2CFE = {25810, 2, 0}, 0x2CFF = {25812, 2, 0}, - 0x2D00 = {25814, 1, 0}, 0x2D01 = {25815, 1, 0}, 0x2D02 = {25816, 1, 0}, 0x2D03 = {25817, 1, 0}, 0x2D04 = {25818, 1, 0}, 0x2D05 = {25819, 1, 0}, 0x2D06 = {25820, 1, 0}, 0x2D07 = {25821, 1, 0}, 0x2D08 = {25822, 1, 0}, 0x2D09 = {25823, 1, 0}, 0x2D0A = {25824, 1, 0}, 0x2D0B = {25825, 1, 0}, 0x2D0C = {25826, 1, 0}, 0x2D0D = {25827, 1, 0}, 0x2D0E = {25828, 1, 0}, 0x2D0F = {25829, 1, 0}, - 0x2D10 = {25830, 1, 0}, 0x2D11 = {25831, 1, 0}, 0x2D12 = {25832, 1, 0}, 0x2D13 = {25833, 1, 0}, 0x2D14 = {25834, 1, 0}, 0x2D15 = {25835, 1, 0}, 0x2D16 = {25836, 1, 0}, 0x2D17 = {25837, 1, 0}, 0x2D18 = {25838, 1, 0}, 0x2D19 = {25839, 1, 0}, 0x2D1A = {25840, 1, 0}, 0x2D1B = {25841, 1, 0}, 0x2D1C = {25842, 1, 0}, 0x2D1D = {25843, 1, 0}, 0x2D1E = {25844, 1, 0}, 0x2D1F = {25845, 1, 0}, - 0x2D20 = {25846, 1, 0}, 0x2D21 = {25847, 1, 0}, 0x2D22 = {25848, 1, 0}, 0x2D23 = {25849, 1, 0}, 0x2D24 = {25850, 1, 0}, 0x2D25 = {25851, 1, 0}, 0x2D26 = {25852, 1, 0}, 0x2D27 = {25853, 1, 0}, 0x2D28 = {25854, 1, 0}, 0x2D29 = {25855, 1, 0}, 0x2D2A = {25856, 1, 0}, 0x2D2B = {25857, 1, 0}, 0x2D2C = {25858, 1, 0}, 0x2D2D = {25859, 1, 0}, 0x2D2E = {25860, 1, 0}, 0x2D2F = {25861, 1, 0}, - 0x2D30 = {25862, 1, 0}, 0x2D31 = {25863, 1, 0}, 0x2D32 = {25864, 1, 0}, 0x2D33 = {25865, 1, 0}, 0x2D34 = {25866, 1, 0}, 0x2D35 = {25867, 1, 0}, 0x2D36 = {25868, 1, 0}, 0x2D37 = {25869, 1, 0}, 0x2D38 = {25870, 1, 0}, 0x2D39 = {25871, 1, 0}, 0x2D3A = {25872, 1, 0}, 0x2D3B = {25873, 1, 0}, 0x2D3C = {25874, 1, 0}, 0x2D3D = {25875, 1, 0}, 0x2D3E = {25876, 1, 0}, 0x2D3F = {25877, 1, 0}, - 0x2D40 = {25878, 1, 0}, 0x2D41 = {25879, 1, 0}, 0x2D42 = {25880, 1, 0}, 0x2D43 = {25881, 1, 0}, 0x2D44 = {25882, 1, 0}, 0x2D45 = {25883, 1, 0}, 0x2D46 = {25884, 1, 0}, 0x2D47 = {25885, 1, 0}, 0x2D48 = {25886, 1, 0}, 0x2D49 = {25887, 1, 0}, 0x2D4A = {25888, 1, 0}, 0x2D4B = {25889, 1, 0}, 0x2D4C = {25890, 1, 0}, 0x2D4D = {25891, 1, 0}, 0x2D4E = {25892, 1, 0}, 0x2D4F = {25893, 1, 0}, - 0x2D50 = {25894, 1, 0}, 0x2D51 = {25895, 1, 0}, 0x2D52 = {25896, 1, 0}, 0x2D53 = {25897, 1, 0}, 0x2D54 = {25898, 1, 0}, 0x2D55 = {25899, 1, 0}, 0x2D56 = {25900, 1, 0}, 0x2D57 = {25901, 1, 0}, 0x2D58 = {25902, 1, 0}, 0x2D59 = {25903, 1, 0}, 0x2D5A = {25904, 1, 0}, 0x2D5B = {25905, 1, 0}, 0x2D5C = {25906, 1, 0}, 0x2D5D = {25907, 1, 0}, 0x2D5E = {25908, 1, 0}, 0x2D5F = {25909, 1, 0}, - 0x2D60 = {25910, 1, 0}, 0x2D61 = {25911, 1, 0}, 0x2D62 = {25912, 1, 0}, 0x2D63 = {25913, 1, 0}, 0x2D64 = {25914, 1, 0}, 0x2D65 = {25915, 1, 0}, 0x2D66 = {25916, 1, 0}, 0x2D67 = {25917, 1, 0}, 0x2D68 = {25918, 1, 0}, 0x2D69 = {25919, 1, 0}, 0x2D6A = {25920, 1, 0}, 0x2D6B = {25921, 1, 0}, 0x2D6C = {25922, 1, 0}, 0x2D6D = {25923, 1, 0}, 0x2D6E = {25924, 1, 0}, 0x2D6F = {25925, 1, 0}, - 0x2D70 = {25926, 1, 0}, 0x2D71 = {25927, 1, 0}, 0x2D72 = {25928, 1, 0}, 0x2D73 = {25929, 1, 0}, 0x2D74 = {25930, 1, 0}, 0x2D75 = {25931, 1, 0}, 0x2D76 = {25932, 1, 0}, 0x2D77 = {25933, 1, 0}, 0x2D78 = {25934, 1, 0}, 0x2D79 = {25935, 1, 0}, 0x2D7A = {25936, 1, 0}, 0x2D7B = {25937, 1, 0}, 0x2D7C = {25938, 1, 0}, 0x2D7D = {25939, 1, 0}, 0x2D7E = {25940, 1, 0}, 0x2D7F = {25941, 1, 0}, - 0x2D80 = {25942, 1, 0}, 0x2D81 = {25943, 1, 0}, 0x2D82 = {25944, 1, 0}, 0x2D83 = {25945, 1, 0}, 0x2D84 = {25946, 1, 0}, 0x2D85 = {25947, 1, 0}, 0x2D86 = {25948, 1, 0}, 0x2D87 = {25949, 1, 0}, 0x2D88 = {25950, 1, 0}, 0x2D89 = {25951, 1, 0}, 0x2D8A = {25952, 1, 0}, 0x2D8B = {25953, 1, 0}, 0x2D8C = {25954, 1, 0}, 0x2D8D = {25955, 1, 0}, 0x2D8E = {25956, 1, 0}, 0x2D8F = {25957, 1, 0}, - 0x2D90 = {25958, 1, 0}, 0x2D91 = {25959, 1, 0}, 0x2D92 = {25960, 1, 0}, 0x2D93 = {25961, 1, 0}, 0x2D94 = {25962, 1, 0}, 0x2D95 = {25963, 1, 0}, 0x2D96 = {25964, 1, 0}, 0x2D97 = {25965, 1, 0}, 0x2D98 = {25966, 1, 0}, 0x2D99 = {25967, 1, 0}, 0x2D9A = {25968, 1, 0}, 0x2D9B = {25969, 1, 0}, 0x2D9C = {25970, 1, 0}, 0x2D9D = {25971, 1, 0}, 0x2D9E = {25972, 1, 0}, 0x2D9F = {25973, 1, 0}, - 0x2DA0 = {25974, 1, 0}, 0x2DA1 = {25975, 1, 0}, 0x2DA2 = {25976, 1, 0}, 0x2DA3 = {25977, 1, 0}, 0x2DA4 = {25978, 1, 0}, 0x2DA5 = {25979, 1, 0}, 0x2DA6 = {25980, 1, 0}, 0x2DA7 = {25981, 1, 0}, 0x2DA8 = {25982, 1, 0}, 0x2DA9 = {25983, 1, 0}, 0x2DAA = {25984, 1, 0}, 0x2DAB = {25985, 1, 0}, 0x2DAC = {25986, 1, 0}, 0x2DAD = {25987, 1, 0}, 0x2DAE = {25988, 1, 0}, 0x2DAF = {25989, 1, 0}, - 0x2DB0 = {25990, 1, 0}, 0x2DB1 = {25991, 1, 0}, 0x2DB2 = {25992, 1, 0}, 0x2DB3 = {25993, 1, 0}, 0x2DB4 = {25994, 1, 0}, 0x2DB5 = {25995, 1, 0}, 0x2DB6 = {25996, 1, 0}, 0x2DB7 = {25997, 1, 0}, 0x2DB8 = {25998, 1, 0}, 0x2DB9 = {25999, 1, 0}, 0x2DBA = {26000, 1, 0}, 0x2DBB = {26001, 1, 0}, 0x2DBC = {26002, 1, 0}, 0x2DBD = {26003, 1, 0}, 0x2DBE = {26004, 1, 0}, 0x2DBF = {26005, 1, 0}, - 0x2DC0 = {26006, 1, 0}, 0x2DC1 = {26007, 1, 0}, 0x2DC2 = {26008, 1, 0}, 0x2DC3 = {26009, 1, 0}, 0x2DC4 = {26010, 1, 0}, 0x2DC5 = {26011, 1, 0}, 0x2DC6 = {26012, 1, 0}, 0x2DC7 = {26013, 1, 0}, 0x2DC8 = {26014, 1, 0}, 0x2DC9 = {26015, 1, 0}, 0x2DCA = {26016, 1, 0}, 0x2DCB = {26017, 1, 0}, 0x2DCC = {26018, 1, 0}, 0x2DCD = {26019, 1, 0}, 0x2DCE = {26020, 1, 0}, 0x2DCF = {26021, 1, 0}, - 0x2DD0 = {26022, 1, 0}, 0x2DD1 = {26023, 1, 0}, 0x2DD2 = {26024, 1, 0}, 0x2DD3 = {26025, 1, 0}, 0x2DD4 = {26026, 1, 0}, 0x2DD5 = {26027, 1, 0}, 0x2DD6 = {26028, 1, 0}, 0x2DD7 = {26029, 1, 0}, 0x2DD8 = {26030, 1, 0}, 0x2DD9 = {26031, 1, 0}, 0x2DDA = {26032, 1, 0}, 0x2DDB = {26033, 1, 0}, 0x2DDC = {26034, 1, 0}, 0x2DDD = {26035, 1, 0}, 0x2DDE = {26036, 1, 0}, 0x2DDF = {26037, 1, 0}, - 0x2DE0 = {26038, 1, 0}, 0x2DE1 = {26039, 1, 0}, 0x2DE2 = {26040, 1, 0}, 0x2DE3 = {26041, 1, 0}, 0x2DE4 = {26042, 1, 0}, 0x2DE5 = {26043, 1, 0}, 0x2DE6 = {26044, 1, 0}, 0x2DE7 = {26045, 1, 0}, 0x2DE8 = {26046, 1, 0}, 0x2DE9 = {26047, 1, 0}, 0x2DEA = {26048, 1, 0}, 0x2DEB = {26049, 1, 0}, 0x2DEC = {26050, 1, 0}, 0x2DED = {26051, 1, 0}, 0x2DEE = {26052, 1, 0}, 0x2DEF = {26053, 1, 0}, - 0x2DF0 = {26054, 1, 0}, 0x2DF1 = {26055, 1, 0}, 0x2DF2 = {26056, 1, 0}, 0x2DF3 = {26057, 1, 0}, 0x2DF4 = {26058, 1, 0}, 0x2DF5 = {26059, 1, 0}, 0x2DF6 = {26060, 1, 0}, 0x2DF7 = {26061, 1, 0}, 0x2DF8 = {26062, 1, 0}, 0x2DF9 = {26063, 1, 0}, 0x2DFA = {26064, 1, 0}, 0x2DFB = {26065, 1, 0}, 0x2DFC = {26066, 1, 0}, 0x2DFD = {26067, 1, 0}, 0x2DFE = {26068, 1, 0}, 0x2DFF = {26069, 1, 0}, - 0x2E00 = {26070, 3, 0}, 0x2E01 = {26073, 2, 0}, 0x2E02 = {26075, 2, 0}, 0x2E03 = {26077, 2, 0}, 0x2E04 = {26079, 2, 0}, 0x2E05 = {26081, 2, 0}, 0x2E06 = {26083, 2, 0}, 0x2E07 = {26085, 2, 0}, 0x2E08 = {26087, 2, 0}, 0x2E09 = {26089, 2, 0}, 0x2E0A = {26091, 2, 0}, 0x2E0B = {26093, 2, 0}, 0x2E0C = {26095, 2, 0}, 0x2E0D = {26097, 2, 0}, 0x2E0E = {26099, 2, 0}, 0x2E0F = {26101, 2, 0}, - 0x2E10 = {26103, 2, 0}, 0x2E11 = {26105, 2, 0}, 0x2E12 = {26107, 2, 0}, 0x2E13 = {26109, 2, 0}, 0x2E14 = {26111, 2, 0}, 0x2E15 = {26113, 2, 0}, 0x2E16 = {26115, 2, 0}, 0x2E17 = {26117, 2, 0}, 0x2E18 = {26119, 2, 0}, 0x2E19 = {26121, 2, 0}, 0x2E1A = {26123, 2, 0}, 0x2E1B = {26125, 2, 0}, 0x2E1C = {26127, 2, 0}, 0x2E1D = {26129, 2, 0}, 0x2E1E = {26131, 2, 0}, 0x2E1F = {26133, 2, 0}, - 0x2E20 = {26135, 2, 0}, 0x2E21 = {26137, 2, 0}, 0x2E22 = {26139, 2, 0}, 0x2E23 = {26141, 2, 0}, 0x2E24 = {26143, 2, 0}, 0x2E25 = {26145, 2, 0}, 0x2E26 = {26147, 2, 0}, 0x2E27 = {26149, 2, 0}, 0x2E28 = {26151, 2, 0}, 0x2E29 = {26153, 2, 0}, 0x2E2A = {26155, 2, 0}, 0x2E2B = {26157, 2, 0}, 0x2E2C = {26159, 2, 0}, 0x2E2D = {26161, 2, 0}, 0x2E2E = {26163, 2, 0}, 0x2E2F = {26165, 2, 0}, - 0x2E30 = {26167, 2, 0}, 0x2E31 = {26169, 2, 0}, 0x2E32 = {26171, 2, 0}, 0x2E33 = {26173, 2, 0}, 0x2E34 = {26175, 2, 0}, 0x2E35 = {26177, 2, 0}, 0x2E36 = {26179, 2, 0}, 0x2E37 = {26181, 2, 0}, 0x2E38 = {26183, 2, 0}, 0x2E39 = {26185, 2, 0}, 0x2E3A = {26187, 2, 0}, 0x2E3B = {26189, 2, 0}, 0x2E3C = {26191, 2, 0}, 0x2E3D = {26193, 2, 0}, 0x2E3E = {26195, 2, 0}, 0x2E3F = {26197, 2, 0}, - 0x2E40 = {26199, 2, 0}, 0x2E41 = {26201, 2, 0}, 0x2E42 = {26203, 2, 0}, 0x2E43 = {26205, 2, 0}, 0x2E44 = {26207, 2, 0}, 0x2E45 = {26209, 2, 0}, 0x2E46 = {26211, 2, 0}, 0x2E47 = {26213, 2, 0}, 0x2E48 = {26215, 2, 0}, 0x2E49 = {26217, 2, 0}, 0x2E4A = {26219, 2, 0}, 0x2E4B = {26221, 2, 0}, 0x2E4C = {26223, 2, 0}, 0x2E4D = {26225, 2, 0}, 0x2E4E = {26227, 2, 0}, 0x2E4F = {26229, 2, 0}, - 0x2E50 = {26231, 2, 0}, 0x2E51 = {26233, 2, 0}, 0x2E52 = {26235, 2, 0}, 0x2E53 = {26237, 2, 0}, 0x2E54 = {26239, 2, 0}, 0x2E55 = {26241, 2, 0}, 0x2E56 = {26243, 2, 0}, 0x2E57 = {26245, 2, 0}, 0x2E58 = {26247, 2, 0}, 0x2E59 = {26249, 2, 0}, 0x2E5A = {26251, 2, 0}, 0x2E5B = {26253, 2, 0}, 0x2E5C = {26255, 2, 0}, 0x2E5D = {26257, 2, 0}, 0x2E5E = {26259, 2, 0}, 0x2E5F = {26261, 2, 0}, - 0x2E60 = {26263, 2, 0}, 0x2E61 = {26265, 2, 0}, 0x2E62 = {26267, 2, 0}, 0x2E63 = {26269, 2, 0}, 0x2E64 = {26271, 2, 0}, 0x2E65 = {26273, 2, 0}, 0x2E66 = {26275, 2, 0}, 0x2E67 = {26277, 2, 0}, 0x2E68 = {26279, 2, 0}, 0x2E69 = {26281, 2, 0}, 0x2E6A = {26283, 2, 0}, 0x2E6B = {26285, 2, 0}, 0x2E6C = {26287, 2, 0}, 0x2E6D = {26289, 2, 0}, 0x2E6E = {26291, 2, 0}, 0x2E6F = {26293, 2, 0}, - 0x2E70 = {26295, 2, 0}, 0x2E71 = {26297, 2, 0}, 0x2E72 = {26299, 2, 0}, 0x2E73 = {26301, 2, 0}, 0x2E74 = {26303, 2, 0}, 0x2E75 = {26305, 2, 0}, 0x2E76 = {26307, 2, 0}, 0x2E77 = {26309, 2, 0}, 0x2E78 = {26311, 2, 0}, 0x2E79 = {26313, 2, 0}, 0x2E7A = {26315, 2, 0}, 0x2E7B = {26317, 2, 0}, 0x2E7C = {26319, 2, 0}, 0x2E7D = {26321, 2, 0}, 0x2E7E = {26323, 2, 0}, 0x2E7F = {26325, 2, 0}, - 0x2E80 = {26327, 2, 0}, 0x2E81 = {26329, 2, 0}, 0x2E82 = {26331, 2, 0}, 0x2E83 = {26333, 2, 0}, 0x2E84 = {26335, 2, 0}, 0x2E85 = {26337, 2, 0}, 0x2E86 = {26339, 2, 0}, 0x2E87 = {26341, 2, 0}, 0x2E88 = {26343, 2, 0}, 0x2E89 = {26345, 2, 0}, 0x2E8A = {26347, 2, 0}, 0x2E8B = {26349, 2, 0}, 0x2E8C = {26351, 2, 0}, 0x2E8D = {26353, 2, 0}, 0x2E8E = {26355, 2, 0}, 0x2E8F = {26357, 2, 0}, - 0x2E90 = {26359, 2, 0}, 0x2E91 = {26361, 2, 0}, 0x2E92 = {26363, 2, 0}, 0x2E93 = {26365, 2, 0}, 0x2E94 = {26367, 2, 0}, 0x2E95 = {26369, 2, 0}, 0x2E96 = {26371, 2, 0}, 0x2E97 = {26373, 2, 0}, 0x2E98 = {26375, 2, 0}, 0x2E99 = {26377, 2, 0}, 0x2E9A = {26379, 2, 0}, 0x2E9B = {26381, 2, 0}, 0x2E9C = {26383, 2, 0}, 0x2E9D = {26385, 2, 0}, 0x2E9E = {26387, 2, 0}, 0x2E9F = {26389, 2, 0}, - 0x2EA0 = {26391, 2, 0}, 0x2EA1 = {26393, 2, 0}, 0x2EA2 = {26395, 2, 0}, 0x2EA3 = {26397, 2, 0}, 0x2EA4 = {26399, 2, 0}, 0x2EA5 = {26401, 2, 0}, 0x2EA6 = {26403, 2, 0}, 0x2EA7 = {26405, 2, 0}, 0x2EA8 = {26407, 2, 0}, 0x2EA9 = {26409, 2, 0}, 0x2EAA = {26411, 2, 0}, 0x2EAB = {26413, 2, 0}, 0x2EAC = {26415, 2, 0}, 0x2EAD = {26417, 2, 0}, 0x2EAE = {26419, 2, 0}, 0x2EAF = {26421, 2, 0}, - 0x2EB0 = {26423, 2, 0}, 0x2EB1 = {26425, 2, 0}, 0x2EB2 = {26427, 2, 0}, 0x2EB3 = {26429, 2, 0}, 0x2EB4 = {26431, 2, 0}, 0x2EB5 = {26433, 2, 0}, 0x2EB6 = {26435, 2, 0}, 0x2EB7 = {26437, 2, 0}, 0x2EB8 = {26439, 2, 0}, 0x2EB9 = {26441, 2, 0}, 0x2EBA = {26443, 2, 0}, 0x2EBB = {26445, 2, 0}, 0x2EBC = {26447, 2, 0}, 0x2EBD = {26449, 2, 0}, 0x2EBE = {26451, 2, 0}, 0x2EBF = {26453, 2, 0}, - 0x2EC0 = {26455, 2, 0}, 0x2EC1 = {26457, 2, 0}, 0x2EC2 = {26459, 2, 0}, 0x2EC3 = {26461, 2, 0}, 0x2EC4 = {26463, 2, 0}, 0x2EC5 = {26465, 2, 0}, 0x2EC6 = {26467, 2, 0}, 0x2EC7 = {26469, 2, 0}, 0x2EC8 = {26471, 2, 0}, 0x2EC9 = {26473, 2, 0}, 0x2ECA = {26475, 2, 0}, 0x2ECB = {26477, 2, 0}, 0x2ECC = {26479, 2, 0}, 0x2ECD = {26481, 2, 0}, 0x2ECE = {26483, 2, 0}, 0x2ECF = {26485, 2, 0}, - 0x2ED0 = {26487, 2, 0}, 0x2ED1 = {26489, 2, 0}, 0x2ED2 = {26491, 2, 0}, 0x2ED3 = {26493, 2, 0}, 0x2ED4 = {26495, 2, 0}, 0x2ED5 = {26497, 2, 0}, 0x2ED6 = {26499, 2, 0}, 0x2ED7 = {26501, 2, 0}, 0x2ED8 = {26503, 2, 0}, 0x2ED9 = {26505, 2, 0}, 0x2EDA = {26507, 2, 0}, 0x2EDB = {26509, 2, 0}, 0x2EDC = {26511, 2, 0}, 0x2EDD = {26513, 2, 0}, 0x2EDE = {26515, 2, 0}, 0x2EDF = {26517, 2, 0}, - 0x2EE0 = {26519, 2, 0}, 0x2EE1 = {26521, 2, 0}, 0x2EE2 = {26523, 2, 0}, 0x2EE3 = {26525, 2, 0}, 0x2EE4 = {26527, 2, 0}, 0x2EE5 = {26529, 2, 0}, 0x2EE6 = {26531, 2, 0}, 0x2EE7 = {26533, 2, 0}, 0x2EE8 = {26535, 2, 0}, 0x2EE9 = {26537, 2, 0}, 0x2EEA = {26539, 2, 0}, 0x2EEB = {26541, 2, 0}, 0x2EEC = {26543, 2, 0}, 0x2EED = {26545, 2, 0}, 0x2EEE = {26547, 2, 0}, 0x2EEF = {26549, 2, 0}, - 0x2EF0 = {26551, 2, 0}, 0x2EF1 = {26553, 2, 0}, 0x2EF2 = {26555, 2, 0}, 0x2EF3 = {26557, 2, 0}, 0x2EF4 = {26559, 2, 0}, 0x2EF5 = {26561, 2, 0}, 0x2EF6 = {26563, 2, 0}, 0x2EF7 = {26565, 2, 0}, 0x2EF8 = {26567, 2, 0}, 0x2EF9 = {26569, 2, 0}, 0x2EFA = {26571, 2, 0}, 0x2EFB = {26573, 2, 0}, 0x2EFC = {26575, 2, 0}, 0x2EFD = {26577, 2, 0}, 0x2EFE = {26579, 2, 0}, 0x2EFF = {26581, 2, 0}, - 0x2F00 = {26583, 3, 0}, 0x2F01 = {26586, 2, 0}, 0x2F02 = {26588, 2, 0}, 0x2F03 = {26590, 2, 0}, 0x2F04 = {26592, 2, 0}, 0x2F05 = {26594, 2, 0}, 0x2F06 = {26596, 2, 0}, 0x2F07 = {26598, 2, 0}, 0x2F08 = {26600, 2, 0}, 0x2F09 = {26602, 2, 0}, 0x2F0A = {26604, 2, 0}, 0x2F0B = {26606, 2, 0}, 0x2F0C = {26608, 2, 0}, 0x2F0D = {26610, 2, 0}, 0x2F0E = {26612, 2, 0}, 0x2F0F = {26614, 2, 0}, - 0x2F10 = {26616, 2, 0}, 0x2F11 = {26618, 2, 0}, 0x2F12 = {26620, 2, 0}, 0x2F13 = {26622, 2, 0}, 0x2F14 = {26624, 2, 0}, 0x2F15 = {26626, 2, 0}, 0x2F16 = {26628, 2, 0}, 0x2F17 = {26630, 2, 0}, 0x2F18 = {26632, 2, 0}, 0x2F19 = {26634, 2, 0}, 0x2F1A = {26636, 2, 0}, 0x2F1B = {26638, 2, 0}, 0x2F1C = {26640, 2, 0}, 0x2F1D = {26642, 2, 0}, 0x2F1E = {26644, 2, 0}, 0x2F1F = {26646, 2, 0}, - 0x2F20 = {26648, 2, 0}, 0x2F21 = {26650, 2, 0}, 0x2F22 = {26652, 2, 0}, 0x2F23 = {26654, 2, 0}, 0x2F24 = {26656, 2, 0}, 0x2F25 = {26658, 2, 0}, 0x2F26 = {26660, 2, 0}, 0x2F27 = {26662, 2, 0}, 0x2F28 = {26664, 2, 0}, 0x2F29 = {26666, 2, 0}, 0x2F2A = {26668, 2, 0}, 0x2F2B = {26670, 2, 0}, 0x2F2C = {26672, 2, 0}, 0x2F2D = {26674, 2, 0}, 0x2F2E = {26676, 2, 0}, 0x2F2F = {26678, 2, 0}, - 0x2F30 = {26680, 2, 0}, 0x2F31 = {26682, 2, 0}, 0x2F32 = {26684, 2, 0}, 0x2F33 = {26686, 2, 0}, 0x2F34 = {26688, 2, 0}, 0x2F35 = {26690, 2, 0}, 0x2F36 = {26692, 2, 0}, 0x2F37 = {26694, 2, 0}, 0x2F38 = {26696, 2, 0}, 0x2F39 = {26698, 2, 0}, 0x2F3A = {26700, 2, 0}, 0x2F3B = {26702, 2, 0}, 0x2F3C = {26704, 2, 0}, 0x2F3D = {26706, 2, 0}, 0x2F3E = {26708, 2, 0}, 0x2F3F = {26710, 2, 0}, - 0x2F40 = {26712, 2, 0}, 0x2F41 = {26714, 2, 0}, 0x2F42 = {26716, 2, 0}, 0x2F43 = {26718, 2, 0}, 0x2F44 = {26720, 2, 0}, 0x2F45 = {26722, 2, 0}, 0x2F46 = {26724, 2, 0}, 0x2F47 = {26726, 2, 0}, 0x2F48 = {26728, 2, 0}, 0x2F49 = {26730, 2, 0}, 0x2F4A = {26732, 2, 0}, 0x2F4B = {26734, 2, 0}, 0x2F4C = {26736, 2, 0}, 0x2F4D = {26738, 2, 0}, 0x2F4E = {26740, 2, 0}, 0x2F4F = {26742, 2, 0}, - 0x2F50 = {26744, 2, 0}, 0x2F51 = {26746, 2, 0}, 0x2F52 = {26748, 2, 0}, 0x2F53 = {26750, 2, 0}, 0x2F54 = {26752, 2, 0}, 0x2F55 = {26754, 2, 0}, 0x2F56 = {26756, 2, 0}, 0x2F57 = {26758, 2, 0}, 0x2F58 = {26760, 2, 0}, 0x2F59 = {26762, 2, 0}, 0x2F5A = {26764, 2, 0}, 0x2F5B = {26766, 2, 0}, 0x2F5C = {26768, 2, 0}, 0x2F5D = {26770, 2, 0}, 0x2F5E = {26772, 2, 0}, 0x2F5F = {26774, 2, 0}, - 0x2F60 = {26776, 2, 0}, 0x2F61 = {26778, 2, 0}, 0x2F62 = {26780, 2, 0}, 0x2F63 = {26782, 2, 0}, 0x2F64 = {26784, 2, 0}, 0x2F65 = {26786, 2, 0}, 0x2F66 = {26788, 2, 0}, 0x2F67 = {26790, 2, 0}, 0x2F68 = {26792, 2, 0}, 0x2F69 = {26794, 2, 0}, 0x2F6A = {26796, 2, 0}, 0x2F6B = {26798, 2, 0}, 0x2F6C = {26800, 2, 0}, 0x2F6D = {26802, 2, 0}, 0x2F6E = {26804, 2, 0}, 0x2F6F = {26806, 2, 0}, - 0x2F70 = {26808, 2, 0}, 0x2F71 = {26810, 2, 0}, 0x2F72 = {26812, 2, 0}, 0x2F73 = {26814, 2, 0}, 0x2F74 = {26816, 2, 0}, 0x2F75 = {26818, 2, 0}, 0x2F76 = {26820, 2, 0}, 0x2F77 = {26822, 2, 0}, 0x2F78 = {26824, 2, 0}, 0x2F79 = {26826, 2, 0}, 0x2F7A = {26828, 2, 0}, 0x2F7B = {26830, 2, 0}, 0x2F7C = {26832, 2, 0}, 0x2F7D = {26834, 2, 0}, 0x2F7E = {26836, 2, 0}, 0x2F7F = {26838, 2, 0}, - 0x2F80 = {26840, 2, 0}, 0x2F81 = {26842, 2, 0}, 0x2F82 = {26844, 2, 0}, 0x2F83 = {26846, 2, 0}, 0x2F84 = {26848, 2, 0}, 0x2F85 = {26850, 2, 0}, 0x2F86 = {26852, 2, 0}, 0x2F87 = {26854, 2, 0}, 0x2F88 = {26856, 2, 0}, 0x2F89 = {26858, 2, 0}, 0x2F8A = {26860, 2, 0}, 0x2F8B = {26862, 2, 0}, 0x2F8C = {26864, 2, 0}, 0x2F8D = {26866, 2, 0}, 0x2F8E = {26868, 2, 0}, 0x2F8F = {26870, 2, 0}, - 0x2F90 = {26872, 2, 0}, 0x2F91 = {26874, 2, 0}, 0x2F92 = {26876, 2, 0}, 0x2F93 = {26878, 2, 0}, 0x2F94 = {26880, 2, 0}, 0x2F95 = {26882, 2, 0}, 0x2F96 = {26884, 2, 0}, 0x2F97 = {26886, 2, 0}, 0x2F98 = {26888, 2, 0}, 0x2F99 = {26890, 2, 0}, 0x2F9A = {26892, 2, 0}, 0x2F9B = {26894, 2, 0}, 0x2F9C = {26896, 2, 0}, 0x2F9D = {26898, 2, 0}, 0x2F9E = {26900, 2, 0}, 0x2F9F = {26902, 2, 0}, - 0x2FA0 = {26904, 2, 0}, 0x2FA1 = {26906, 2, 0}, 0x2FA2 = {26908, 2, 0}, 0x2FA3 = {26910, 2, 0}, 0x2FA4 = {26912, 2, 0}, 0x2FA5 = {26914, 2, 0}, 0x2FA6 = {26916, 2, 0}, 0x2FA7 = {26918, 2, 0}, 0x2FA8 = {26920, 2, 0}, 0x2FA9 = {26922, 2, 0}, 0x2FAA = {26924, 2, 0}, 0x2FAB = {26926, 2, 0}, 0x2FAC = {26928, 2, 0}, 0x2FAD = {26930, 2, 0}, 0x2FAE = {26932, 2, 0}, 0x2FAF = {26934, 2, 0}, - 0x2FB0 = {26936, 2, 0}, 0x2FB1 = {26938, 2, 0}, 0x2FB2 = {26940, 2, 0}, 0x2FB3 = {26942, 2, 0}, 0x2FB4 = {26944, 2, 0}, 0x2FB5 = {26946, 2, 0}, 0x2FB6 = {26948, 2, 0}, 0x2FB7 = {26950, 2, 0}, 0x2FB8 = {26952, 2, 0}, 0x2FB9 = {26954, 2, 0}, 0x2FBA = {26956, 2, 0}, 0x2FBB = {26958, 2, 0}, 0x2FBC = {26960, 2, 0}, 0x2FBD = {26962, 2, 0}, 0x2FBE = {26964, 2, 0}, 0x2FBF = {26966, 2, 0}, - 0x2FC0 = {26968, 2, 0}, 0x2FC1 = {26970, 2, 0}, 0x2FC2 = {26972, 2, 0}, 0x2FC3 = {26974, 2, 0}, 0x2FC4 = {26976, 2, 0}, 0x2FC5 = {26978, 2, 0}, 0x2FC6 = {26980, 2, 0}, 0x2FC7 = {26982, 2, 0}, 0x2FC8 = {26984, 2, 0}, 0x2FC9 = {26986, 2, 0}, 0x2FCA = {26988, 2, 0}, 0x2FCB = {26990, 2, 0}, 0x2FCC = {26992, 2, 0}, 0x2FCD = {26994, 2, 0}, 0x2FCE = {26996, 2, 0}, 0x2FCF = {26998, 2, 0}, - 0x2FD0 = {27000, 2, 0}, 0x2FD1 = {27002, 2, 0}, 0x2FD2 = {27004, 2, 0}, 0x2FD3 = {27006, 2, 0}, 0x2FD4 = {27008, 2, 0}, 0x2FD5 = {27010, 2, 0}, 0x2FD6 = {27012, 2, 0}, 0x2FD7 = {27014, 2, 0}, 0x2FD8 = {27016, 2, 0}, 0x2FD9 = {27018, 2, 0}, 0x2FDA = {27020, 2, 0}, 0x2FDB = {27022, 2, 0}, 0x2FDC = {27024, 2, 0}, 0x2FDD = {27026, 2, 0}, 0x2FDE = {27028, 2, 0}, 0x2FDF = {27030, 2, 0}, - 0x2FE0 = {27032, 2, 0}, 0x2FE1 = {27034, 2, 0}, 0x2FE2 = {27036, 2, 0}, 0x2FE3 = {27038, 2, 0}, 0x2FE4 = {27040, 2, 0}, 0x2FE5 = {27042, 2, 0}, 0x2FE6 = {27044, 2, 0}, 0x2FE7 = {27046, 2, 0}, 0x2FE8 = {27048, 2, 0}, 0x2FE9 = {27050, 2, 0}, 0x2FEA = {27052, 2, 0}, 0x2FEB = {27054, 2, 0}, 0x2FEC = {27056, 2, 0}, 0x2FED = {27058, 2, 0}, 0x2FEE = {27060, 2, 0}, 0x2FEF = {27062, 2, 0}, - 0x2FF0 = {27064, 2, 0}, 0x2FF1 = {27066, 2, 0}, 0x2FF2 = {27068, 2, 0}, 0x2FF3 = {27070, 2, 0}, 0x2FF4 = {27072, 2, 0}, 0x2FF5 = {27074, 2, 0}, 0x2FF6 = {27076, 2, 0}, 0x2FF7 = {27078, 2, 0}, 0x2FF8 = {27080, 2, 0}, 0x2FF9 = {27082, 2, 0}, 0x2FFA = {27084, 2, 0}, 0x2FFB = {27086, 2, 0}, 0x2FFC = {27088, 2, 0}, 0x2FFD = {27090, 2, 0}, 0x2FFE = {27092, 2, 0}, 0x2FFF = {27094, 2, 0}, - 0x3000 = {27096, 2, 0}, 0x3001 = {27098, 2, 0}, 0x3002 = {27100, 2, 0}, 0x3003 = {27102, 2, 0}, 0x3004 = {27104, 2, 0}, 0x3005 = {27106, 2, 0}, 0x3006 = {27108, 2, 0}, 0x3007 = {27110, 2, 0}, 0x3008 = {27112, 2, 0}, 0x3009 = {27114, 2, 0}, 0x300A = {27116, 2, 0}, 0x300B = {27118, 2, 0}, 0x300C = {27120, 2, 0}, 0x300D = {27122, 2, 0}, 0x300E = {27124, 2, 0}, 0x300F = {27126, 2, 0}, - 0x3010 = {27128, 2, 0}, 0x3011 = {27130, 2, 0}, 0x3012 = {27132, 2, 0}, 0x3013 = {27134, 2, 0}, 0x3014 = {27136, 2, 0}, 0x3015 = {27138, 2, 0}, 0x3016 = {27140, 2, 0}, 0x3017 = {27142, 2, 0}, 0x3018 = {27144, 2, 0}, 0x3019 = {27146, 2, 0}, 0x301A = {27148, 2, 0}, 0x301B = {27150, 2, 0}, 0x301C = {27152, 2, 0}, 0x301D = {27154, 2, 0}, 0x301E = {27156, 2, 0}, 0x301F = {27158, 2, 0}, - 0x3020 = {27160, 2, 0}, 0x3021 = {27162, 2, 0}, 0x3022 = {27164, 2, 0}, 0x3023 = {27166, 2, 0}, 0x3024 = {27168, 2, 0}, 0x3025 = {27170, 2, 0}, 0x3026 = {27172, 2, 0}, 0x3027 = {27174, 2, 0}, 0x3028 = {27176, 2, 0}, 0x3029 = {27178, 2, 0}, 0x302A = {27180, 2, 0}, 0x302B = {27182, 2, 0}, 0x302C = {27184, 2, 0}, 0x302D = {27186, 2, 0}, 0x302E = {27188, 2, 0}, 0x302F = {27190, 2, 0}, - 0x3030 = {27192, 2, 0}, 0x3031 = {27194, 2, 0}, 0x3032 = {27196, 2, 0}, 0x3033 = {27198, 2, 0}, 0x3034 = {27200, 2, 0}, 0x3035 = {27202, 2, 0}, 0x3036 = {27204, 2, 0}, 0x3037 = {27206, 2, 0}, 0x3038 = {27208, 2, 0}, 0x3039 = {27210, 2, 0}, 0x303A = {27212, 2, 0}, 0x303B = {27214, 2, 0}, 0x303C = {27216, 2, 0}, 0x303D = {27218, 2, 0}, 0x303E = {27220, 2, 0}, 0x303F = {27222, 2, 0}, - 0x3040 = {27224, 2, 0}, 0x3041 = {27226, 2, 0}, 0x3042 = {27228, 2, 0}, 0x3043 = {27230, 2, 0}, 0x3044 = {27232, 2, 0}, 0x3045 = {27234, 2, 0}, 0x3046 = {27236, 2, 0}, 0x3047 = {27238, 2, 0}, 0x3048 = {27240, 2, 0}, 0x3049 = {27242, 2, 0}, 0x304A = {27244, 2, 0}, 0x304B = {27246, 2, 0}, 0x304C = {27248, 2, 0}, 0x304D = {27250, 2, 0}, 0x304E = {27252, 2, 0}, 0x304F = {27254, 2, 0}, - 0x3050 = {27256, 2, 0}, 0x3051 = {27258, 2, 0}, 0x3052 = {27260, 2, 0}, 0x3053 = {27262, 2, 0}, 0x3054 = {27264, 2, 0}, 0x3055 = {27266, 2, 0}, 0x3056 = {27268, 2, 0}, 0x3057 = {27270, 2, 0}, 0x3058 = {27272, 2, 0}, 0x3059 = {27274, 2, 0}, 0x305A = {27276, 2, 0}, 0x305B = {27278, 2, 0}, 0x305C = {27280, 2, 0}, 0x305D = {27282, 2, 0}, 0x305E = {27284, 2, 0}, 0x305F = {27286, 2, 0}, - 0x3060 = {27288, 2, 0}, 0x3061 = {27290, 2, 0}, 0x3062 = {27292, 2, 0}, 0x3063 = {27294, 2, 0}, 0x3064 = {27296, 2, 0}, 0x3065 = {27298, 2, 0}, 0x3066 = {27300, 2, 0}, 0x3067 = {27302, 2, 0}, 0x3068 = {27304, 2, 0}, 0x3069 = {27306, 2, 0}, 0x306A = {27308, 2, 0}, 0x306B = {27310, 2, 0}, 0x306C = {27312, 2, 0}, 0x306D = {27314, 2, 0}, 0x306E = {27316, 2, 0}, 0x306F = {27318, 2, 0}, - 0x3070 = {27320, 2, 0}, 0x3071 = {27322, 2, 0}, 0x3072 = {27324, 2, 0}, 0x3073 = {27326, 2, 0}, 0x3074 = {27328, 2, 0}, 0x3075 = {27330, 2, 0}, 0x3076 = {27332, 2, 0}, 0x3077 = {27334, 2, 0}, 0x3078 = {27336, 2, 0}, 0x3079 = {27338, 2, 0}, 0x307A = {27340, 2, 0}, 0x307B = {27342, 2, 0}, 0x307C = {27344, 2, 0}, 0x307D = {27346, 2, 0}, 0x307E = {27348, 2, 0}, 0x307F = {27350, 2, 0}, - 0x3080 = {27352, 2, 0}, 0x3081 = {27354, 2, 0}, 0x3082 = {27356, 2, 0}, 0x3083 = {27358, 2, 0}, 0x3084 = {27360, 2, 0}, 0x3085 = {27362, 2, 0}, 0x3086 = {27364, 2, 0}, 0x3087 = {27366, 2, 0}, 0x3088 = {27368, 2, 0}, 0x3089 = {27370, 2, 0}, 0x308A = {27372, 2, 0}, 0x308B = {27374, 2, 0}, 0x308C = {27376, 2, 0}, 0x308D = {27378, 2, 0}, 0x308E = {27380, 2, 0}, 0x308F = {27382, 2, 0}, - 0x3090 = {27384, 2, 0}, 0x3091 = {27386, 2, 0}, 0x3092 = {27388, 2, 0}, 0x3093 = {27390, 2, 0}, 0x3094 = {27392, 2, 0}, 0x3095 = {27394, 2, 0}, 0x3096 = {27396, 2, 0}, 0x3097 = {27398, 2, 0}, 0x3098 = {27400, 2, 0}, 0x3099 = {27402, 2, 0}, 0x309A = {27404, 2, 0}, 0x309B = {27406, 2, 0}, 0x309C = {27408, 2, 0}, 0x309D = {27410, 2, 0}, 0x309E = {27412, 2, 0}, 0x309F = {27414, 2, 0}, - 0x30A0 = {27416, 2, 0}, 0x30A1 = {27418, 2, 0}, 0x30A2 = {27420, 2, 0}, 0x30A3 = {27422, 2, 0}, 0x30A4 = {27424, 2, 0}, 0x30A5 = {27426, 2, 0}, 0x30A6 = {27428, 2, 0}, 0x30A7 = {27430, 2, 0}, 0x30A8 = {27432, 2, 0}, 0x30A9 = {27434, 2, 0}, 0x30AA = {27436, 2, 0}, 0x30AB = {27438, 2, 0}, 0x30AC = {27440, 2, 0}, 0x30AD = {27442, 2, 0}, 0x30AE = {27444, 2, 0}, 0x30AF = {27446, 2, 0}, - 0x30B0 = {27448, 2, 0}, 0x30B1 = {27450, 2, 0}, 0x30B2 = {27452, 2, 0}, 0x30B3 = {27454, 2, 0}, 0x30B4 = {27456, 2, 0}, 0x30B5 = {27458, 2, 0}, 0x30B6 = {27460, 2, 0}, 0x30B7 = {27462, 2, 0}, 0x30B8 = {27464, 2, 0}, 0x30B9 = {27466, 2, 0}, 0x30BA = {27468, 2, 0}, 0x30BB = {27470, 2, 0}, 0x30BC = {27472, 2, 0}, 0x30BD = {27474, 2, 0}, 0x30BE = {27476, 2, 0}, 0x30BF = {27478, 2, 0}, - 0x30C0 = {27480, 2, 0}, 0x30C1 = {27482, 2, 0}, 0x30C2 = {27484, 2, 0}, 0x30C3 = {27486, 2, 0}, 0x30C4 = {27488, 2, 0}, 0x30C5 = {27490, 2, 0}, 0x30C6 = {27492, 2, 0}, 0x30C7 = {27494, 2, 0}, 0x30C8 = {27496, 2, 0}, 0x30C9 = {27498, 2, 0}, 0x30CA = {27500, 2, 0}, 0x30CB = {27502, 2, 0}, 0x30CC = {27504, 2, 0}, 0x30CD = {27506, 2, 0}, 0x30CE = {27508, 2, 0}, 0x30CF = {27510, 2, 0}, - 0x30D0 = {27512, 2, 0}, 0x30D1 = {27514, 2, 0}, 0x30D2 = {27516, 2, 0}, 0x30D3 = {27518, 2, 0}, 0x30D4 = {27520, 2, 0}, 0x30D5 = {27522, 2, 0}, 0x30D6 = {27524, 2, 0}, 0x30D7 = {27526, 2, 0}, 0x30D8 = {27528, 2, 0}, 0x30D9 = {27530, 2, 0}, 0x30DA = {27532, 2, 0}, 0x30DB = {27534, 2, 0}, 0x30DC = {27536, 2, 0}, 0x30DD = {27538, 2, 0}, 0x30DE = {27540, 2, 0}, 0x30DF = {27542, 2, 0}, - 0x30E0 = {27544, 2, 0}, 0x30E1 = {27546, 2, 0}, 0x30E2 = {27548, 2, 0}, 0x30E3 = {27550, 2, 0}, 0x30E4 = {27552, 2, 0}, 0x30E5 = {27554, 2, 0}, 0x30E6 = {27556, 2, 0}, 0x30E7 = {27558, 2, 0}, 0x30E8 = {27560, 2, 0}, 0x30E9 = {27562, 2, 0}, 0x30EA = {27564, 2, 0}, 0x30EB = {27566, 2, 0}, 0x30EC = {27568, 2, 0}, 0x30ED = {27570, 2, 0}, 0x30EE = {27572, 2, 0}, 0x30EF = {27574, 2, 0}, - 0x30F0 = {27576, 2, 0}, 0x30F1 = {27578, 2, 0}, 0x30F2 = {27580, 2, 0}, 0x30F3 = {27582, 2, 0}, 0x30F4 = {27584, 2, 0}, 0x30F5 = {27586, 2, 0}, 0x30F6 = {27588, 2, 0}, 0x30F7 = {27590, 2, 0}, 0x30F8 = {27592, 2, 0}, 0x30F9 = {27594, 2, 0}, 0x30FA = {27596, 2, 0}, 0x30FB = {27598, 2, 0}, 0x30FC = {27600, 2, 0}, 0x30FD = {27602, 2, 0}, 0x30FE = {27604, 2, 0}, 0x30FF = {27606, 2, 0}, - 0x3100 = {27608, 1, 0}, 0x3101 = {27609, 1, 0}, 0x3102 = {27610, 1, 0}, 0x3103 = {27611, 1, 0}, 0x3104 = {27612, 1, 0}, 0x3105 = {27613, 1, 0}, 0x3106 = {27614, 1, 0}, 0x3107 = {27615, 1, 0}, 0x3108 = {27616, 1, 0}, 0x3109 = {27617, 1, 0}, 0x310A = {27618, 1, 0}, 0x310B = {27619, 1, 0}, 0x310C = {27620, 1, 0}, 0x310D = {27621, 1, 0}, 0x310E = {27622, 1, 0}, 0x310F = {27623, 1, 0}, - 0x3110 = {27624, 1, 0}, 0x3111 = {27625, 1, 0}, 0x3112 = {27626, 1, 0}, 0x3113 = {27627, 1, 0}, 0x3114 = {27628, 1, 0}, 0x3115 = {27629, 1, 0}, 0x3116 = {27630, 1, 0}, 0x3117 = {27631, 1, 0}, 0x3118 = {27632, 1, 0}, 0x3119 = {27633, 1, 0}, 0x311A = {27634, 1, 0}, 0x311B = {27635, 1, 0}, 0x311C = {27636, 1, 0}, 0x311D = {27637, 1, 0}, 0x311E = {27638, 1, 0}, 0x311F = {27639, 1, 0}, - 0x3120 = {27640, 1, 0}, 0x3121 = {27641, 1, 0}, 0x3122 = {27642, 1, 0}, 0x3123 = {27643, 1, 0}, 0x3124 = {27644, 1, 0}, 0x3125 = {27645, 1, 0}, 0x3126 = {27646, 1, 0}, 0x3127 = {27647, 1, 0}, 0x3128 = {27648, 1, 0}, 0x3129 = {27649, 1, 0}, 0x312A = {27650, 1, 0}, 0x312B = {27651, 1, 0}, 0x312C = {27652, 1, 0}, 0x312D = {27653, 1, 0}, 0x312E = {27654, 1, 0}, 0x312F = {27655, 1, 0}, - 0x3130 = {27656, 1, 0}, 0x3131 = {27657, 1, 0}, 0x3132 = {27658, 1, 0}, 0x3133 = {27659, 1, 0}, 0x3134 = {27660, 1, 0}, 0x3135 = {27661, 1, 0}, 0x3136 = {27662, 1, 0}, 0x3137 = {27663, 1, 0}, 0x3138 = {27664, 1, 0}, 0x3139 = {27665, 1, 0}, 0x313A = {27666, 1, 0}, 0x313B = {27667, 1, 0}, 0x313C = {27668, 1, 0}, 0x313D = {27669, 1, 0}, 0x313E = {27670, 1, 0}, 0x313F = {27671, 1, 0}, - 0x3140 = {27672, 1, 0}, 0x3141 = {27673, 1, 0}, 0x3142 = {27674, 1, 0}, 0x3143 = {27675, 1, 0}, 0x3144 = {27676, 1, 0}, 0x3145 = {27677, 1, 0}, 0x3146 = {27678, 1, 0}, 0x3147 = {27679, 1, 0}, 0x3148 = {27680, 1, 0}, 0x3149 = {27681, 1, 0}, 0x314A = {27682, 1, 0}, 0x314B = {27683, 1, 0}, 0x314C = {27684, 1, 0}, 0x314D = {27685, 1, 0}, 0x314E = {27686, 1, 0}, 0x314F = {27687, 1, 0}, - 0x3150 = {27688, 1, 0}, 0x3151 = {27689, 1, 0}, 0x3152 = {27690, 1, 0}, 0x3153 = {27691, 1, 0}, 0x3154 = {27692, 1, 0}, 0x3155 = {27693, 1, 0}, 0x3156 = {27694, 1, 0}, 0x3157 = {27695, 1, 0}, 0x3158 = {27696, 1, 0}, 0x3159 = {27697, 1, 0}, 0x315A = {27698, 1, 0}, 0x315B = {27699, 1, 0}, 0x315C = {27700, 1, 0}, 0x315D = {27701, 1, 0}, 0x315E = {27702, 1, 0}, 0x315F = {27703, 1, 0}, - 0x3160 = {27704, 1, 0}, 0x3161 = {27705, 1, 0}, 0x3162 = {27706, 1, 0}, 0x3163 = {27707, 1, 0}, 0x3164 = {27708, 1, 0}, 0x3165 = {27709, 1, 0}, 0x3166 = {27710, 1, 0}, 0x3167 = {27711, 1, 0}, 0x3168 = {27712, 1, 0}, 0x3169 = {27713, 1, 0}, 0x316A = {27714, 1, 0}, 0x316B = {27715, 1, 0}, 0x316C = {27716, 1, 0}, 0x316D = {27717, 1, 0}, 0x316E = {27718, 1, 0}, 0x316F = {27719, 1, 0}, - 0x3170 = {27720, 1, 0}, 0x3171 = {27721, 1, 0}, 0x3172 = {27722, 1, 0}, 0x3173 = {27723, 1, 0}, 0x3174 = {27724, 1, 0}, 0x3175 = {27725, 1, 0}, 0x3176 = {27726, 1, 0}, 0x3177 = {27727, 1, 0}, 0x3178 = {27728, 1, 0}, 0x3179 = {27729, 1, 0}, 0x317A = {27730, 1, 0}, 0x317B = {27731, 1, 0}, 0x317C = {27732, 1, 0}, 0x317D = {27733, 1, 0}, 0x317E = {27734, 1, 0}, 0x317F = {27735, 1, 0}, - 0x3180 = {27736, 1, 0}, 0x3181 = {27737, 1, 0}, 0x3182 = {27738, 1, 0}, 0x3183 = {27739, 1, 0}, 0x3184 = {27740, 1, 0}, 0x3185 = {27741, 1, 0}, 0x3186 = {27742, 1, 0}, 0x3187 = {27743, 1, 0}, 0x3188 = {27744, 1, 0}, 0x3189 = {27745, 1, 0}, 0x318A = {27746, 1, 0}, 0x318B = {27747, 1, 0}, 0x318C = {27748, 1, 0}, 0x318D = {27749, 1, 0}, 0x318E = {27750, 1, 0}, 0x318F = {27751, 1, 0}, - 0x3190 = {27752, 1, 0}, 0x3191 = {27753, 1, 0}, 0x3192 = {27754, 1, 0}, 0x3193 = {27755, 1, 0}, 0x3194 = {27756, 1, 0}, 0x3195 = {27757, 1, 0}, 0x3196 = {27758, 1, 0}, 0x3197 = {27759, 1, 0}, 0x3198 = {27760, 1, 0}, 0x3199 = {27761, 1, 0}, 0x319A = {27762, 1, 0}, 0x319B = {27763, 1, 0}, 0x319C = {27764, 1, 0}, 0x319D = {27765, 1, 0}, 0x319E = {27766, 1, 0}, 0x319F = {27767, 1, 0}, - 0x31A0 = {27768, 1, 0}, 0x31A1 = {27769, 1, 0}, 0x31A2 = {27770, 1, 0}, 0x31A3 = {27771, 1, 0}, 0x31A4 = {27772, 1, 0}, 0x31A5 = {27773, 1, 0}, 0x31A6 = {27774, 1, 0}, 0x31A7 = {27775, 1, 0}, 0x31A8 = {27776, 1, 0}, 0x31A9 = {27777, 1, 0}, 0x31AA = {27778, 1, 0}, 0x31AB = {27779, 1, 0}, 0x31AC = {27780, 1, 0}, 0x31AD = {27781, 1, 0}, 0x31AE = {27782, 1, 0}, 0x31AF = {27783, 1, 0}, - 0x31B0 = {27784, 1, 0}, 0x31B1 = {27785, 1, 0}, 0x31B2 = {27786, 1, 0}, 0x31B3 = {27787, 1, 0}, 0x31B4 = {27788, 1, 0}, 0x31B5 = {27789, 1, 0}, 0x31B6 = {27790, 1, 0}, 0x31B7 = {27791, 1, 0}, 0x31B8 = {27792, 1, 0}, 0x31B9 = {27793, 1, 0}, 0x31BA = {27794, 1, 0}, 0x31BB = {27795, 1, 0}, 0x31BC = {27796, 1, 0}, 0x31BD = {27797, 1, 0}, 0x31BE = {27798, 1, 0}, 0x31BF = {27799, 1, 0}, - 0x31C0 = {27800, 1, 0}, 0x31C1 = {27801, 1, 0}, 0x31C2 = {27802, 1, 0}, 0x31C3 = {27803, 1, 0}, 0x31C4 = {27804, 1, 0}, 0x31C5 = {27805, 1, 0}, 0x31C6 = {27806, 1, 0}, 0x31C7 = {27807, 1, 0}, 0x31C8 = {27808, 1, 0}, 0x31C9 = {27809, 1, 0}, 0x31CA = {27810, 1, 0}, 0x31CB = {27811, 1, 0}, 0x31CC = {27812, 1, 0}, 0x31CD = {27813, 1, 0}, 0x31CE = {27814, 1, 0}, 0x31CF = {27815, 1, 0}, - 0x31D0 = {27816, 1, 0}, 0x31D1 = {27817, 1, 0}, 0x31D2 = {27818, 1, 0}, 0x31D3 = {27819, 1, 0}, 0x31D4 = {27820, 1, 0}, 0x31D5 = {27821, 1, 0}, 0x31D6 = {27822, 1, 0}, 0x31D7 = {27823, 1, 0}, 0x31D8 = {27824, 1, 0}, 0x31D9 = {27825, 1, 0}, 0x31DA = {27826, 1, 0}, 0x31DB = {27827, 1, 0}, 0x31DC = {27828, 1, 0}, 0x31DD = {27829, 1, 0}, 0x31DE = {27830, 1, 0}, 0x31DF = {27831, 1, 0}, - 0x31E0 = {27832, 1, 0}, 0x31E1 = {27833, 1, 0}, 0x31E2 = {27834, 1, 0}, 0x31E3 = {27835, 1, 0}, 0x31E4 = {27836, 1, 0}, 0x31E5 = {27837, 1, 0}, 0x31E6 = {27838, 1, 0}, 0x31E7 = {27839, 1, 0}, 0x31E8 = {27840, 1, 0}, 0x31E9 = {27841, 1, 0}, 0x31EA = {27842, 1, 0}, 0x31EB = {27843, 1, 0}, 0x31EC = {27844, 1, 0}, 0x31ED = {27845, 1, 0}, 0x31EE = {27846, 1, 0}, 0x31EF = {27847, 1, 0}, - 0x31F0 = {27848, 1, 0}, 0x31F1 = {27849, 1, 0}, 0x31F2 = {27850, 1, 0}, 0x31F3 = {27851, 1, 0}, 0x31F4 = {27852, 1, 0}, 0x31F5 = {27853, 1, 0}, 0x31F6 = {27854, 1, 0}, 0x31F7 = {27855, 1, 0}, 0x31F8 = {27856, 1, 0}, 0x31F9 = {27857, 1, 0}, 0x31FA = {27858, 1, 0}, 0x31FB = {27859, 1, 0}, 0x31FC = {27860, 1, 0}, 0x31FD = {27861, 1, 0}, 0x31FE = {27862, 1, 0}, 0x31FF = {27863, 1, 0}, - 0x3200 = {27864, 3, 0}, 0x3201 = {27867, 3, 0}, 0x3202 = {27870, 3, 0}, 0x3203 = {27873, 3, 0}, 0x3204 = {27876, 3, 0}, 0x3205 = {27879, 3, 0}, 0x3206 = {27882, 3, 0}, 0x3207 = {27885, 3, 0}, 0x3208 = {27888, 3, 0}, 0x3209 = {27891, 3, 0}, 0x320A = {27894, 3, 0}, 0x320B = {27897, 3, 0}, 0x320C = {27900, 3, 0}, 0x320D = {27903, 3, 0}, 0x320E = {27906, 3, 0}, 0x320F = {27909, 3, 0}, - 0x3210 = {27912, 3, 0}, 0x3211 = {27915, 3, 0}, 0x3212 = {27918, 3, 0}, 0x3213 = {27921, 3, 0}, 0x3214 = {27924, 3, 0}, 0x3215 = {27927, 3, 0}, 0x3216 = {27930, 3, 0}, 0x3217 = {27933, 3, 0}, 0x3218 = {27936, 3, 0}, 0x3219 = {27939, 3, 0}, 0x321A = {27942, 3, 0}, 0x321B = {27945, 3, 0}, 0x321C = {27948, 3, 0}, 0x321D = {27951, 3, 0}, 0x321E = {27954, 3, 0}, 0x321F = {27957, 3, 0}, - 0x3220 = {27960, 3, 0}, 0x3221 = {27963, 3, 0}, 0x3222 = {27966, 3, 0}, 0x3223 = {27969, 3, 0}, 0x3224 = {27972, 3, 0}, 0x3225 = {27975, 3, 0}, 0x3226 = {27978, 3, 0}, 0x3227 = {27981, 3, 0}, 0x3228 = {27984, 3, 0}, 0x3229 = {27987, 3, 0}, 0x322A = {27990, 3, 0}, 0x322B = {27993, 3, 0}, 0x322C = {27996, 3, 0}, 0x322D = {27999, 3, 0}, 0x322E = {28002, 3, 0}, 0x322F = {28005, 3, 0}, - 0x3230 = {28008, 3, 0}, 0x3231 = {28011, 3, 0}, 0x3232 = {28014, 3, 0}, 0x3233 = {28017, 3, 0}, 0x3234 = {28020, 3, 0}, 0x3235 = {28023, 3, 0}, 0x3236 = {28026, 3, 0}, 0x3237 = {28029, 3, 0}, 0x3238 = {28032, 3, 0}, 0x3239 = {28035, 3, 0}, 0x323A = {28038, 3, 0}, 0x323B = {28041, 3, 0}, 0x323C = {28044, 3, 0}, 0x323D = {28047, 3, 0}, 0x323E = {28050, 3, 0}, 0x323F = {28053, 3, 0}, - 0x3240 = {28056, 3, 0}, 0x3241 = {28059, 3, 0}, 0x3242 = {28062, 3, 0}, 0x3243 = {28065, 3, 0}, 0x3244 = {28068, 3, 0}, 0x3245 = {28071, 3, 0}, 0x3246 = {28074, 3, 0}, 0x3247 = {28077, 3, 0}, 0x3248 = {28080, 3, 0}, 0x3249 = {28083, 3, 0}, 0x324A = {28086, 3, 0}, 0x324B = {28089, 3, 0}, 0x324C = {28092, 3, 0}, 0x324D = {28095, 3, 0}, 0x324E = {28098, 3, 0}, 0x324F = {28101, 3, 0}, - 0x3250 = {28104, 3, 0}, 0x3251 = {28107, 3, 0}, 0x3252 = {28110, 3, 0}, 0x3253 = {28113, 3, 0}, 0x3254 = {28116, 3, 0}, 0x3255 = {28119, 3, 0}, 0x3256 = {28122, 3, 0}, 0x3257 = {28125, 3, 0}, 0x3258 = {28128, 3, 0}, 0x3259 = {28131, 3, 0}, 0x325A = {28134, 3, 0}, 0x325B = {28137, 3, 0}, 0x325C = {28140, 3, 0}, 0x325D = {28143, 3, 0}, 0x325E = {28146, 3, 0}, 0x325F = {28149, 3, 0}, - 0x3260 = {28152, 3, 0}, 0x3261 = {28155, 3, 0}, 0x3262 = {28158, 3, 0}, 0x3263 = {28161, 3, 0}, 0x3264 = {28164, 3, 0}, 0x3265 = {28167, 3, 0}, 0x3266 = {28170, 3, 0}, 0x3267 = {28173, 3, 0}, 0x3268 = {28176, 3, 0}, 0x3269 = {28179, 3, 0}, 0x326A = {28182, 3, 0}, 0x326B = {28185, 3, 0}, 0x326C = {28188, 3, 0}, 0x326D = {28191, 3, 0}, 0x326E = {28194, 3, 0}, 0x326F = {28197, 3, 0}, - 0x3270 = {28200, 3, 0}, 0x3271 = {28203, 3, 0}, 0x3272 = {28206, 3, 0}, 0x3273 = {28209, 3, 0}, 0x3274 = {28212, 3, 0}, 0x3275 = {28215, 3, 0}, 0x3276 = {28218, 3, 0}, 0x3277 = {28221, 3, 0}, 0x3278 = {28224, 3, 0}, 0x3279 = {28227, 3, 0}, 0x327A = {28230, 3, 0}, 0x327B = {28233, 3, 0}, 0x327C = {28236, 3, 0}, 0x327D = {28239, 3, 0}, 0x327E = {28242, 3, 0}, 0x327F = {28245, 3, 0}, - 0x3280 = {28248, 3, 0}, 0x3281 = {28251, 3, 0}, 0x3282 = {28254, 3, 0}, 0x3283 = {28257, 3, 0}, 0x3284 = {28260, 3, 0}, 0x3285 = {28263, 3, 0}, 0x3286 = {28266, 3, 0}, 0x3287 = {28269, 3, 0}, 0x3288 = {28272, 3, 0}, 0x3289 = {28275, 3, 0}, 0x328A = {28278, 3, 0}, 0x328B = {28281, 3, 0}, 0x328C = {28284, 3, 0}, 0x328D = {28287, 3, 0}, 0x328E = {28290, 3, 0}, 0x328F = {28293, 3, 0}, - 0x3290 = {28296, 3, 0}, 0x3291 = {28299, 3, 0}, 0x3292 = {28302, 3, 0}, 0x3293 = {28305, 3, 0}, 0x3294 = {28308, 3, 0}, 0x3295 = {28311, 3, 0}, 0x3296 = {28314, 3, 0}, 0x3297 = {28317, 3, 0}, 0x3298 = {28320, 3, 0}, 0x3299 = {28323, 3, 0}, 0x329A = {28326, 3, 0}, 0x329B = {28329, 3, 0}, 0x329C = {28332, 3, 0}, 0x329D = {28335, 3, 0}, 0x329E = {28338, 3, 0}, 0x329F = {28341, 3, 0}, - 0x32A0 = {28344, 3, 0}, 0x32A1 = {28347, 3, 0}, 0x32A2 = {28350, 3, 0}, 0x32A3 = {28353, 3, 0}, 0x32A4 = {28356, 3, 0}, 0x32A5 = {28359, 3, 0}, 0x32A6 = {28362, 3, 0}, 0x32A7 = {28365, 3, 0}, 0x32A8 = {28368, 3, 0}, 0x32A9 = {28371, 3, 0}, 0x32AA = {28374, 3, 0}, 0x32AB = {28377, 3, 0}, 0x32AC = {28380, 3, 0}, 0x32AD = {28383, 3, 0}, 0x32AE = {28386, 3, 0}, 0x32AF = {28389, 3, 0}, - 0x32B0 = {28392, 3, 0}, 0x32B1 = {28395, 3, 0}, 0x32B2 = {28398, 3, 0}, 0x32B3 = {28401, 3, 0}, 0x32B4 = {28404, 3, 0}, 0x32B5 = {28407, 3, 0}, 0x32B6 = {28410, 3, 0}, 0x32B7 = {28413, 3, 0}, 0x32B8 = {28416, 3, 0}, 0x32B9 = {28419, 3, 0}, 0x32BA = {28422, 3, 0}, 0x32BB = {28425, 3, 0}, 0x32BC = {28428, 3, 0}, 0x32BD = {28431, 3, 0}, 0x32BE = {28434, 3, 0}, 0x32BF = {28437, 3, 0}, - 0x32C0 = {28440, 3, 0}, 0x32C1 = {28443, 3, 0}, 0x32C2 = {28446, 3, 0}, 0x32C3 = {28449, 3, 0}, 0x32C4 = {28452, 3, 0}, 0x32C5 = {28455, 3, 0}, 0x32C6 = {28458, 3, 0}, 0x32C7 = {28461, 3, 0}, 0x32C8 = {28464, 3, 0}, 0x32C9 = {28467, 3, 0}, 0x32CA = {28470, 3, 0}, 0x32CB = {28473, 3, 0}, 0x32CC = {28476, 3, 0}, 0x32CD = {28479, 3, 0}, 0x32CE = {28482, 3, 0}, 0x32CF = {28485, 3, 0}, - 0x32D0 = {28488, 3, 0}, 0x32D1 = {28491, 3, 0}, 0x32D2 = {28494, 3, 0}, 0x32D3 = {28497, 3, 0}, 0x32D4 = {28500, 3, 0}, 0x32D5 = {28503, 3, 0}, 0x32D6 = {28506, 3, 0}, 0x32D7 = {28509, 3, 0}, 0x32D8 = {28512, 3, 0}, 0x32D9 = {28515, 3, 0}, 0x32DA = {28518, 3, 0}, 0x32DB = {28521, 3, 0}, 0x32DC = {28524, 3, 0}, 0x32DD = {28527, 3, 0}, 0x32DE = {28530, 3, 0}, 0x32DF = {28533, 3, 0}, - 0x32E0 = {28536, 3, 0}, 0x32E1 = {28539, 3, 0}, 0x32E2 = {28542, 3, 0}, 0x32E3 = {28545, 3, 0}, 0x32E4 = {28548, 3, 0}, 0x32E5 = {28551, 3, 0}, 0x32E6 = {28554, 3, 0}, 0x32E7 = {28557, 3, 0}, 0x32E8 = {28560, 3, 0}, 0x32E9 = {28563, 3, 0}, 0x32EA = {28566, 3, 0}, 0x32EB = {28569, 3, 0}, 0x32EC = {28572, 3, 0}, 0x32ED = {28575, 3, 0}, 0x32EE = {28578, 3, 0}, 0x32EF = {28581, 3, 0}, - 0x32F0 = {28584, 3, 0}, 0x32F1 = {28587, 3, 0}, 0x32F2 = {28590, 3, 0}, 0x32F3 = {28593, 3, 0}, 0x32F4 = {28596, 3, 0}, 0x32F5 = {28599, 3, 0}, 0x32F6 = {28602, 3, 0}, 0x32F7 = {28605, 3, 0}, 0x32F8 = {28608, 3, 0}, 0x32F9 = {28611, 3, 0}, 0x32FA = {28614, 3, 0}, 0x32FB = {28617, 3, 0}, 0x32FC = {28620, 3, 0}, 0x32FD = {28623, 3, 0}, 0x32FE = {28626, 3, 0}, 0x32FF = {28629, 3, 0}, - 0x3300 = {28632, 1, 0}, 0x3301 = {28633, 1, 0}, 0x3302 = {28634, 1, 0}, 0x3303 = {28635, 1, 0}, 0x3304 = {28636, 1, 0}, 0x3305 = {28637, 1, 0}, 0x3306 = {28638, 1, 0}, 0x3307 = {28639, 1, 0}, 0x3308 = {28640, 1, 0}, 0x3309 = {28641, 1, 0}, 0x330A = {28642, 1, 0}, 0x330B = {28643, 1, 0}, 0x330C = {28644, 1, 0}, 0x330D = {28645, 1, 0}, 0x330E = {28646, 1, 0}, 0x330F = {28647, 1, 0}, - 0x3310 = {28648, 1, 0}, 0x3311 = {28649, 1, 0}, 0x3312 = {28650, 1, 0}, 0x3313 = {28651, 1, 0}, 0x3314 = {28652, 1, 0}, 0x3315 = {28653, 1, 0}, 0x3316 = {28654, 1, 0}, 0x3317 = {28655, 1, 0}, 0x3318 = {28656, 1, 0}, 0x3319 = {28657, 1, 0}, 0x331A = {28658, 1, 0}, 0x331B = {28659, 1, 0}, 0x331C = {28660, 1, 0}, 0x331D = {28661, 1, 0}, 0x331E = {28662, 1, 0}, 0x331F = {28663, 1, 0}, - 0x3320 = {28664, 1, 0}, 0x3321 = {28665, 1, 0}, 0x3322 = {28666, 1, 0}, 0x3323 = {28667, 1, 0}, 0x3324 = {28668, 1, 0}, 0x3325 = {28669, 1, 0}, 0x3326 = {28670, 1, 0}, 0x3327 = {28671, 1, 0}, 0x3328 = {28672, 1, 0}, 0x3329 = {28673, 1, 0}, 0x332A = {28674, 1, 0}, 0x332B = {28675, 1, 0}, 0x332C = {28676, 1, 0}, 0x332D = {28677, 1, 0}, 0x332E = {28678, 1, 0}, 0x332F = {28679, 1, 0}, - 0x3330 = {28680, 1, 0}, 0x3331 = {28681, 1, 0}, 0x3332 = {28682, 1, 0}, 0x3333 = {28683, 1, 0}, 0x3334 = {28684, 1, 0}, 0x3335 = {28685, 1, 0}, 0x3336 = {28686, 1, 0}, 0x3337 = {28687, 1, 0}, 0x3338 = {28688, 1, 0}, 0x3339 = {28689, 1, 0}, 0x333A = {28690, 1, 0}, 0x333B = {28691, 1, 0}, 0x333C = {28692, 1, 0}, 0x333D = {28693, 1, 0}, 0x333E = {28694, 1, 0}, 0x333F = {28695, 1, 0}, - 0x3340 = {28696, 1, 0}, 0x3341 = {28697, 1, 0}, 0x3342 = {28698, 1, 0}, 0x3343 = {28699, 1, 0}, 0x3344 = {28700, 1, 0}, 0x3345 = {28701, 1, 0}, 0x3346 = {28702, 1, 0}, 0x3347 = {28703, 1, 0}, 0x3348 = {28704, 1, 0}, 0x3349 = {28705, 1, 0}, 0x334A = {28706, 1, 0}, 0x334B = {28707, 1, 0}, 0x334C = {28708, 1, 0}, 0x334D = {28709, 1, 0}, 0x334E = {28710, 1, 0}, 0x334F = {28711, 1, 0}, - 0x3350 = {28712, 1, 0}, 0x3351 = {28713, 1, 0}, 0x3352 = {28714, 1, 0}, 0x3353 = {28715, 1, 0}, 0x3354 = {28716, 1, 0}, 0x3355 = {28717, 1, 0}, 0x3356 = {28718, 1, 0}, 0x3357 = {28719, 1, 0}, 0x3358 = {28720, 1, 0}, 0x3359 = {28721, 1, 0}, 0x335A = {28722, 1, 0}, 0x335B = {28723, 1, 0}, 0x335C = {28724, 1, 0}, 0x335D = {28725, 1, 0}, 0x335E = {28726, 1, 0}, 0x335F = {28727, 1, 0}, - 0x3360 = {28728, 1, 0}, 0x3361 = {28729, 1, 0}, 0x3362 = {28730, 1, 0}, 0x3363 = {28731, 1, 0}, 0x3364 = {28732, 1, 0}, 0x3365 = {28733, 1, 0}, 0x3366 = {28734, 1, 0}, 0x3367 = {28735, 1, 0}, 0x3368 = {28736, 1, 0}, 0x3369 = {28737, 1, 0}, 0x336A = {28738, 1, 0}, 0x336B = {28739, 1, 0}, 0x336C = {28740, 1, 0}, 0x336D = {28741, 1, 0}, 0x336E = {28742, 1, 0}, 0x336F = {28743, 1, 0}, - 0x3370 = {28744, 1, 0}, 0x3371 = {28745, 1, 0}, 0x3372 = {28746, 1, 0}, 0x3373 = {28747, 1, 0}, 0x3374 = {28748, 1, 0}, 0x3375 = {28749, 1, 0}, 0x3376 = {28750, 1, 0}, 0x3377 = {28751, 1, 0}, 0x3378 = {28752, 1, 0}, 0x3379 = {28753, 1, 0}, 0x337A = {28754, 1, 0}, 0x337B = {28755, 1, 0}, 0x337C = {28756, 1, 0}, 0x337D = {28757, 1, 0}, 0x337E = {28758, 1, 0}, 0x337F = {28759, 1, 0}, - 0x3380 = {28760, 1, 0}, 0x3381 = {28761, 1, 0}, 0x3382 = {28762, 1, 0}, 0x3383 = {28763, 1, 0}, 0x3384 = {28764, 1, 0}, 0x3385 = {28765, 1, 0}, 0x3386 = {28766, 1, 0}, 0x3387 = {28767, 1, 0}, 0x3388 = {28768, 1, 0}, 0x3389 = {28769, 1, 0}, 0x338A = {28770, 1, 0}, 0x338B = {28771, 1, 0}, 0x338C = {28772, 1, 0}, 0x338D = {28773, 1, 0}, 0x338E = {28774, 1, 0}, 0x338F = {28775, 1, 0}, - 0x3390 = {28776, 1, 0}, 0x3391 = {28777, 1, 0}, 0x3392 = {28778, 1, 0}, 0x3393 = {28779, 1, 0}, 0x3394 = {28780, 1, 0}, 0x3395 = {28781, 1, 0}, 0x3396 = {28782, 1, 0}, 0x3397 = {28783, 1, 0}, 0x3398 = {28784, 1, 0}, 0x3399 = {28785, 1, 0}, 0x339A = {28786, 1, 0}, 0x339B = {28787, 1, 0}, 0x339C = {28788, 1, 0}, 0x339D = {28789, 1, 0}, 0x339E = {28790, 1, 0}, 0x339F = {28791, 1, 0}, - 0x33A0 = {28792, 1, 0}, 0x33A1 = {28793, 1, 0}, 0x33A2 = {28794, 1, 0}, 0x33A3 = {28795, 1, 0}, 0x33A4 = {28796, 1, 0}, 0x33A5 = {28797, 1, 0}, 0x33A6 = {28798, 1, 0}, 0x33A7 = {28799, 1, 0}, 0x33A8 = {28800, 1, 0}, 0x33A9 = {28801, 1, 0}, 0x33AA = {28802, 1, 0}, 0x33AB = {28803, 1, 0}, 0x33AC = {28804, 1, 0}, 0x33AD = {28805, 1, 0}, 0x33AE = {28806, 1, 0}, 0x33AF = {28807, 1, 0}, - 0x33B0 = {28808, 1, 0}, 0x33B1 = {28809, 1, 0}, 0x33B2 = {28810, 1, 0}, 0x33B3 = {28811, 1, 0}, 0x33B4 = {28812, 1, 0}, 0x33B5 = {28813, 1, 0}, 0x33B6 = {28814, 1, 0}, 0x33B7 = {28815, 1, 0}, 0x33B8 = {28816, 1, 0}, 0x33B9 = {28817, 1, 0}, 0x33BA = {28818, 1, 0}, 0x33BB = {28819, 1, 0}, 0x33BC = {28820, 1, 0}, 0x33BD = {28821, 1, 0}, 0x33BE = {28822, 1, 0}, 0x33BF = {28823, 1, 0}, - 0x33C0 = {28824, 1, 0}, 0x33C1 = {28825, 1, 0}, 0x33C2 = {28826, 1, 0}, 0x33C3 = {28827, 1, 0}, 0x33C4 = {28828, 1, 0}, 0x33C5 = {28829, 1, 0}, 0x33C6 = {28830, 1, 0}, 0x33C7 = {28831, 1, 0}, 0x33C8 = {28832, 1, 0}, 0x33C9 = {28833, 1, 0}, 0x33CA = {28834, 1, 0}, 0x33CB = {28835, 1, 0}, 0x33CC = {28836, 1, 0}, 0x33CD = {28837, 1, 0}, 0x33CE = {28838, 1, 0}, 0x33CF = {28839, 1, 0}, - 0x33D0 = {28840, 1, 0}, 0x33D1 = {28841, 1, 0}, 0x33D2 = {28842, 1, 0}, 0x33D3 = {28843, 1, 0}, 0x33D4 = {28844, 1, 0}, 0x33D5 = {28845, 1, 0}, 0x33D6 = {28846, 1, 0}, 0x33D7 = {28847, 1, 0}, 0x33D8 = {28848, 1, 0}, 0x33D9 = {28849, 1, 0}, 0x33DA = {28850, 1, 0}, 0x33DB = {28851, 1, 0}, 0x33DC = {28852, 1, 0}, 0x33DD = {28853, 1, 0}, 0x33DE = {28854, 1, 0}, 0x33DF = {28855, 1, 0}, - 0x33E0 = {28856, 1, 0}, 0x33E1 = {28857, 1, 0}, 0x33E2 = {28858, 1, 0}, 0x33E3 = {28859, 1, 0}, 0x33E4 = {28860, 1, 0}, 0x33E5 = {28861, 1, 0}, 0x33E6 = {28862, 1, 0}, 0x33E7 = {28863, 1, 0}, 0x33E8 = {28864, 1, 0}, 0x33E9 = {28865, 1, 0}, 0x33EA = {28866, 1, 0}, 0x33EB = {28867, 1, 0}, 0x33EC = {28868, 1, 0}, 0x33ED = {28869, 1, 0}, 0x33EE = {28870, 1, 0}, 0x33EF = {28871, 1, 0}, - 0x33F0 = {28872, 1, 0}, 0x33F1 = {28873, 1, 0}, 0x33F2 = {28874, 1, 0}, 0x33F3 = {28875, 1, 0}, 0x33F4 = {28876, 1, 0}, 0x33F5 = {28877, 1, 0}, 0x33F6 = {28878, 1, 0}, 0x33F7 = {28879, 1, 0}, 0x33F8 = {28880, 1, 0}, 0x33F9 = {28881, 1, 0}, 0x33FA = {28882, 1, 0}, 0x33FB = {28883, 1, 0}, 0x33FC = {28884, 1, 0}, 0x33FD = {28885, 1, 0}, 0x33FE = {28886, 1, 0}, 0x33FF = {28887, 1, 0}, - 0x3400 = {28888, 2, 0}, 0x3401 = {28890, 2, 0}, 0x3402 = {28892, 2, 0}, 0x3403 = {28894, 2, 0}, 0x3404 = {28896, 2, 0}, 0x3405 = {28898, 2, 0}, 0x3406 = {28900, 2, 0}, 0x3407 = {28902, 2, 0}, 0x3408 = {28904, 2, 0}, 0x3409 = {28906, 2, 0}, 0x340A = {28908, 2, 0}, 0x340B = {28910, 2, 0}, 0x340C = {28912, 2, 0}, 0x340D = {28914, 2, 0}, 0x340E = {28916, 2, 0}, 0x340F = {28918, 2, 0}, - 0x3410 = {28920, 2, 0}, 0x3411 = {28922, 2, 0}, 0x3412 = {28924, 2, 0}, 0x3413 = {28926, 2, 0}, 0x3414 = {28928, 2, 0}, 0x3415 = {28930, 2, 0}, 0x3416 = {28932, 2, 0}, 0x3417 = {28934, 2, 0}, 0x3418 = {28936, 2, 0}, 0x3419 = {28938, 2, 0}, 0x341A = {28940, 2, 0}, 0x341B = {28942, 2, 0}, 0x341C = {28944, 2, 0}, 0x341D = {28946, 2, 0}, 0x341E = {28948, 2, 0}, 0x341F = {28950, 2, 0}, - 0x3420 = {28952, 2, 0}, 0x3421 = {28954, 2, 0}, 0x3422 = {28956, 2, 0}, 0x3423 = {28958, 2, 0}, 0x3424 = {28960, 2, 0}, 0x3425 = {28962, 2, 0}, 0x3426 = {28964, 2, 0}, 0x3427 = {28966, 2, 0}, 0x3428 = {28968, 2, 0}, 0x3429 = {28970, 2, 0}, 0x342A = {28972, 2, 0}, 0x342B = {28974, 2, 0}, 0x342C = {28976, 2, 0}, 0x342D = {28978, 2, 0}, 0x342E = {28980, 2, 0}, 0x342F = {28982, 2, 0}, - 0x3430 = {28984, 2, 0}, 0x3431 = {28986, 2, 0}, 0x3432 = {28988, 2, 0}, 0x3433 = {28990, 2, 0}, 0x3434 = {28992, 2, 0}, 0x3435 = {28994, 2, 0}, 0x3436 = {28996, 2, 0}, 0x3437 = {28998, 2, 0}, 0x3438 = {29000, 2, 0}, 0x3439 = {29002, 2, 0}, 0x343A = {29004, 2, 0}, 0x343B = {29006, 2, 0}, 0x343C = {29008, 2, 0}, 0x343D = {29010, 2, 0}, 0x343E = {29012, 2, 0}, 0x343F = {29014, 2, 0}, - 0x3440 = {29016, 2, 0}, 0x3441 = {29018, 2, 0}, 0x3442 = {29020, 2, 0}, 0x3443 = {29022, 2, 0}, 0x3444 = {29024, 2, 0}, 0x3445 = {29026, 2, 0}, 0x3446 = {29028, 2, 0}, 0x3447 = {29030, 2, 0}, 0x3448 = {29032, 2, 0}, 0x3449 = {29034, 2, 0}, 0x344A = {29036, 2, 0}, 0x344B = {29038, 2, 0}, 0x344C = {29040, 2, 0}, 0x344D = {29042, 2, 0}, 0x344E = {29044, 2, 0}, 0x344F = {29046, 2, 0}, - 0x3450 = {29048, 2, 0}, 0x3451 = {29050, 2, 0}, 0x3452 = {29052, 2, 0}, 0x3453 = {29054, 2, 0}, 0x3454 = {29056, 2, 0}, 0x3455 = {29058, 2, 0}, 0x3456 = {29060, 2, 0}, 0x3457 = {29062, 2, 0}, 0x3458 = {29064, 2, 0}, 0x3459 = {29066, 2, 0}, 0x345A = {29068, 2, 0}, 0x345B = {29070, 2, 0}, 0x345C = {29072, 2, 0}, 0x345D = {29074, 2, 0}, 0x345E = {29076, 2, 0}, 0x345F = {29078, 2, 0}, - 0x3460 = {29080, 2, 0}, 0x3461 = {29082, 2, 0}, 0x3462 = {29084, 2, 0}, 0x3463 = {29086, 2, 0}, 0x3464 = {29088, 2, 0}, 0x3465 = {29090, 2, 0}, 0x3466 = {29092, 2, 0}, 0x3467 = {29094, 2, 0}, 0x3468 = {29096, 2, 0}, 0x3469 = {29098, 2, 0}, 0x346A = {29100, 2, 0}, 0x346B = {29102, 2, 0}, 0x346C = {29104, 2, 0}, 0x346D = {29106, 2, 0}, 0x346E = {29108, 2, 0}, 0x346F = {29110, 2, 0}, - 0x3470 = {29112, 2, 0}, 0x3471 = {29114, 2, 0}, 0x3472 = {29116, 2, 0}, 0x3473 = {29118, 2, 0}, 0x3474 = {29120, 2, 0}, 0x3475 = {29122, 2, 0}, 0x3476 = {29124, 2, 0}, 0x3477 = {29126, 2, 0}, 0x3478 = {29128, 2, 0}, 0x3479 = {29130, 2, 0}, 0x347A = {29132, 2, 0}, 0x347B = {29134, 2, 0}, 0x347C = {29136, 2, 0}, 0x347D = {29138, 2, 0}, 0x347E = {29140, 2, 0}, 0x347F = {29142, 2, 0}, - 0x3480 = {29144, 2, 0}, 0x3481 = {29146, 2, 0}, 0x3482 = {29148, 2, 0}, 0x3483 = {29150, 2, 0}, 0x3484 = {29152, 2, 0}, 0x3485 = {29154, 2, 0}, 0x3486 = {29156, 2, 0}, 0x3487 = {29158, 2, 0}, 0x3488 = {29160, 2, 0}, 0x3489 = {29162, 2, 0}, 0x348A = {29164, 2, 0}, 0x348B = {29166, 2, 0}, 0x348C = {29168, 2, 0}, 0x348D = {29170, 2, 0}, 0x348E = {29172, 2, 0}, 0x348F = {29174, 2, 0}, - 0x3490 = {29176, 2, 0}, 0x3491 = {29178, 2, 0}, 0x3492 = {29180, 2, 0}, 0x3493 = {29182, 2, 0}, 0x3494 = {29184, 2, 0}, 0x3495 = {29186, 2, 0}, 0x3496 = {29188, 2, 0}, 0x3497 = {29190, 2, 0}, 0x3498 = {29192, 2, 0}, 0x3499 = {29194, 2, 0}, 0x349A = {29196, 2, 0}, 0x349B = {29198, 2, 0}, 0x349C = {29200, 2, 0}, 0x349D = {29202, 2, 0}, 0x349E = {29204, 2, 0}, 0x349F = {29206, 2, 0}, - 0x34A0 = {29208, 2, 0}, 0x34A1 = {29210, 2, 0}, 0x34A2 = {29212, 2, 0}, 0x34A3 = {29214, 2, 0}, 0x34A4 = {29216, 2, 0}, 0x34A5 = {29218, 2, 0}, 0x34A6 = {29220, 2, 0}, 0x34A7 = {29222, 2, 0}, 0x34A8 = {29224, 2, 0}, 0x34A9 = {29226, 2, 0}, 0x34AA = {29228, 2, 0}, 0x34AB = {29230, 2, 0}, 0x34AC = {29232, 2, 0}, 0x34AD = {29234, 2, 0}, 0x34AE = {29236, 2, 0}, 0x34AF = {29238, 2, 0}, - 0x34B0 = {29240, 2, 0}, 0x34B1 = {29242, 2, 0}, 0x34B2 = {29244, 2, 0}, 0x34B3 = {29246, 2, 0}, 0x34B4 = {29248, 2, 0}, 0x34B5 = {29250, 2, 0}, 0x34B6 = {29252, 2, 0}, 0x34B7 = {29254, 2, 0}, 0x34B8 = {29256, 2, 0}, 0x34B9 = {29258, 2, 0}, 0x34BA = {29260, 2, 0}, 0x34BB = {29262, 2, 0}, 0x34BC = {29264, 2, 0}, 0x34BD = {29266, 2, 0}, 0x34BE = {29268, 2, 0}, 0x34BF = {29270, 2, 0}, - 0x34C0 = {29272, 2, 0}, 0x34C1 = {29274, 2, 0}, 0x34C2 = {29276, 2, 0}, 0x34C3 = {29278, 2, 0}, 0x34C4 = {29280, 2, 0}, 0x34C5 = {29282, 2, 0}, 0x34C6 = {29284, 2, 0}, 0x34C7 = {29286, 2, 0}, 0x34C8 = {29288, 2, 0}, 0x34C9 = {29290, 2, 0}, 0x34CA = {29292, 2, 0}, 0x34CB = {29294, 2, 0}, 0x34CC = {29296, 2, 0}, 0x34CD = {29298, 2, 0}, 0x34CE = {29300, 2, 0}, 0x34CF = {29302, 2, 0}, - 0x34D0 = {29304, 2, 0}, 0x34D1 = {29306, 2, 0}, 0x34D2 = {29308, 2, 0}, 0x34D3 = {29310, 2, 0}, 0x34D4 = {29312, 2, 0}, 0x34D5 = {29314, 2, 0}, 0x34D6 = {29316, 2, 0}, 0x34D7 = {29318, 2, 0}, 0x34D8 = {29320, 2, 0}, 0x34D9 = {29322, 2, 0}, 0x34DA = {29324, 2, 0}, 0x34DB = {29326, 2, 0}, 0x34DC = {29328, 2, 0}, 0x34DD = {29330, 2, 0}, 0x34DE = {29332, 2, 0}, 0x34DF = {29334, 2, 0}, - 0x34E0 = {29336, 2, 0}, 0x34E1 = {29338, 2, 0}, 0x34E2 = {29340, 2, 0}, 0x34E3 = {29342, 2, 0}, 0x34E4 = {29344, 2, 0}, 0x34E5 = {29346, 2, 0}, 0x34E6 = {29348, 2, 0}, 0x34E7 = {29350, 2, 0}, 0x34E8 = {29352, 2, 0}, 0x34E9 = {29354, 2, 0}, 0x34EA = {29356, 2, 0}, 0x34EB = {29358, 2, 0}, 0x34EC = {29360, 2, 0}, 0x34ED = {29362, 2, 0}, 0x34EE = {29364, 2, 0}, 0x34EF = {29366, 2, 0}, - 0x34F0 = {29368, 2, 0}, 0x34F1 = {29370, 2, 0}, 0x34F2 = {29372, 2, 0}, 0x34F3 = {29374, 2, 0}, 0x34F4 = {29376, 2, 0}, 0x34F5 = {29378, 2, 0}, 0x34F6 = {29380, 2, 0}, 0x34F7 = {29382, 2, 0}, 0x34F8 = {29384, 2, 0}, 0x34F9 = {29386, 2, 0}, 0x34FA = {29388, 2, 0}, 0x34FB = {29390, 2, 0}, 0x34FC = {29392, 2, 0}, 0x34FD = {29394, 2, 0}, 0x34FE = {29396, 2, 0}, 0x34FF = {29398, 2, 0}, - 0x3500 = {29400, 1, 0}, 0x3501 = {29401, 1, 0}, 0x3502 = {29402, 1, 0}, 0x3503 = {29403, 1, 0}, 0x3504 = {29404, 1, 0}, 0x3505 = {29405, 1, 0}, 0x3506 = {29406, 1, 0}, 0x3507 = {29407, 1, 0}, 0x3508 = {29408, 1, 0}, 0x3509 = {29409, 1, 0}, 0x350A = {29410, 1, 0}, 0x350B = {29411, 1, 0}, 0x350C = {29412, 1, 0}, 0x350D = {29413, 1, 0}, 0x350E = {29414, 1, 0}, 0x350F = {29415, 1, 0}, - 0x3510 = {29416, 1, 0}, 0x3511 = {29417, 1, 0}, 0x3512 = {29418, 1, 0}, 0x3513 = {29419, 1, 0}, 0x3514 = {29420, 1, 0}, 0x3515 = {29421, 1, 0}, 0x3516 = {29422, 1, 0}, 0x3517 = {29423, 1, 0}, 0x3518 = {29424, 1, 0}, 0x3519 = {29425, 1, 0}, 0x351A = {29426, 1, 0}, 0x351B = {29427, 1, 0}, 0x351C = {29428, 1, 0}, 0x351D = {29429, 1, 0}, 0x351E = {29430, 1, 0}, 0x351F = {29431, 1, 0}, - 0x3520 = {29432, 1, 0}, 0x3521 = {29433, 1, 0}, 0x3522 = {29434, 1, 0}, 0x3523 = {29435, 1, 0}, 0x3524 = {29436, 1, 0}, 0x3525 = {29437, 1, 0}, 0x3526 = {29438, 1, 0}, 0x3527 = {29439, 1, 0}, 0x3528 = {29440, 1, 0}, 0x3529 = {29441, 1, 0}, 0x352A = {29442, 1, 0}, 0x352B = {29443, 1, 0}, 0x352C = {29444, 1, 0}, 0x352D = {29445, 1, 0}, 0x352E = {29446, 1, 0}, 0x352F = {29447, 1, 0}, - 0x3530 = {29448, 1, 0}, 0x3531 = {29449, 1, 0}, 0x3532 = {29450, 1, 0}, 0x3533 = {29451, 1, 0}, 0x3534 = {29452, 1, 0}, 0x3535 = {29453, 1, 0}, 0x3536 = {29454, 1, 0}, 0x3537 = {29455, 1, 0}, 0x3538 = {29456, 1, 0}, 0x3539 = {29457, 1, 0}, 0x353A = {29458, 1, 0}, 0x353B = {29459, 1, 0}, 0x353C = {29460, 1, 0}, 0x353D = {29461, 1, 0}, 0x353E = {29462, 1, 0}, 0x353F = {29463, 1, 0}, - 0x3540 = {29464, 1, 0}, 0x3541 = {29465, 1, 0}, 0x3542 = {29466, 1, 0}, 0x3543 = {29467, 1, 0}, 0x3544 = {29468, 1, 0}, 0x3545 = {29469, 1, 0}, 0x3546 = {29470, 1, 0}, 0x3547 = {29471, 1, 0}, 0x3548 = {29472, 1, 0}, 0x3549 = {29473, 1, 0}, 0x354A = {29474, 1, 0}, 0x354B = {29475, 1, 0}, 0x354C = {29476, 1, 0}, 0x354D = {29477, 1, 0}, 0x354E = {29478, 1, 0}, 0x354F = {29479, 1, 0}, - 0x3550 = {29480, 1, 0}, 0x3551 = {29481, 1, 0}, 0x3552 = {29482, 1, 0}, 0x3553 = {29483, 1, 0}, 0x3554 = {29484, 1, 0}, 0x3555 = {29485, 1, 0}, 0x3556 = {29486, 1, 0}, 0x3557 = {29487, 1, 0}, 0x3558 = {29488, 1, 0}, 0x3559 = {29489, 1, 0}, 0x355A = {29490, 1, 0}, 0x355B = {29491, 1, 0}, 0x355C = {29492, 1, 0}, 0x355D = {29493, 1, 0}, 0x355E = {29494, 1, 0}, 0x355F = {29495, 1, 0}, - 0x3560 = {29496, 1, 0}, 0x3561 = {29497, 1, 0}, 0x3562 = {29498, 1, 0}, 0x3563 = {29499, 1, 0}, 0x3564 = {29500, 1, 0}, 0x3565 = {29501, 1, 0}, 0x3566 = {29502, 1, 0}, 0x3567 = {29503, 1, 0}, 0x3568 = {29504, 1, 0}, 0x3569 = {29505, 1, 0}, 0x356A = {29506, 1, 0}, 0x356B = {29507, 1, 0}, 0x356C = {29508, 1, 0}, 0x356D = {29509, 1, 0}, 0x356E = {29510, 1, 0}, 0x356F = {29511, 1, 0}, - 0x3570 = {29512, 1, 0}, 0x3571 = {29513, 1, 0}, 0x3572 = {29514, 1, 0}, 0x3573 = {29515, 1, 0}, 0x3574 = {29516, 1, 0}, 0x3575 = {29517, 1, 0}, 0x3576 = {29518, 1, 0}, 0x3577 = {29519, 1, 0}, 0x3578 = {29520, 1, 0}, 0x3579 = {29521, 1, 0}, 0x357A = {29522, 1, 0}, 0x357B = {29523, 1, 0}, 0x357C = {29524, 1, 0}, 0x357D = {29525, 1, 0}, 0x357E = {29526, 1, 0}, 0x357F = {29527, 1, 0}, - 0x3580 = {29528, 1, 0}, 0x3581 = {29529, 1, 0}, 0x3582 = {29530, 1, 0}, 0x3583 = {29531, 1, 0}, 0x3584 = {29532, 1, 0}, 0x3585 = {29533, 1, 0}, 0x3586 = {29534, 1, 0}, 0x3587 = {29535, 1, 0}, 0x3588 = {29536, 1, 0}, 0x3589 = {29537, 1, 0}, 0x358A = {29538, 1, 0}, 0x358B = {29539, 1, 0}, 0x358C = {29540, 1, 0}, 0x358D = {29541, 1, 0}, 0x358E = {29542, 1, 0}, 0x358F = {29543, 1, 0}, - 0x3590 = {29544, 1, 0}, 0x3591 = {29545, 1, 0}, 0x3592 = {29546, 1, 0}, 0x3593 = {29547, 1, 0}, 0x3594 = {29548, 1, 0}, 0x3595 = {29549, 1, 0}, 0x3596 = {29550, 1, 0}, 0x3597 = {29551, 1, 0}, 0x3598 = {29552, 1, 0}, 0x3599 = {29553, 1, 0}, 0x359A = {29554, 1, 0}, 0x359B = {29555, 1, 0}, 0x359C = {29556, 1, 0}, 0x359D = {29557, 1, 0}, 0x359E = {29558, 1, 0}, 0x359F = {29559, 1, 0}, - 0x35A0 = {29560, 1, 0}, 0x35A1 = {29561, 1, 0}, 0x35A2 = {29562, 1, 0}, 0x35A3 = {29563, 1, 0}, 0x35A4 = {29564, 1, 0}, 0x35A5 = {29565, 1, 0}, 0x35A6 = {29566, 1, 0}, 0x35A7 = {29567, 1, 0}, 0x35A8 = {29568, 1, 0}, 0x35A9 = {29569, 1, 0}, 0x35AA = {29570, 1, 0}, 0x35AB = {29571, 1, 0}, 0x35AC = {29572, 1, 0}, 0x35AD = {29573, 1, 0}, 0x35AE = {29574, 1, 0}, 0x35AF = {29575, 1, 0}, - 0x35B0 = {29576, 1, 0}, 0x35B1 = {29577, 1, 0}, 0x35B2 = {29578, 1, 0}, 0x35B3 = {29579, 1, 0}, 0x35B4 = {29580, 1, 0}, 0x35B5 = {29581, 1, 0}, 0x35B6 = {29582, 1, 0}, 0x35B7 = {29583, 1, 0}, 0x35B8 = {29584, 1, 0}, 0x35B9 = {29585, 1, 0}, 0x35BA = {29586, 1, 0}, 0x35BB = {29587, 1, 0}, 0x35BC = {29588, 1, 0}, 0x35BD = {29589, 1, 0}, 0x35BE = {29590, 1, 0}, 0x35BF = {29591, 1, 0}, - 0x35C0 = {29592, 1, 0}, 0x35C1 = {29593, 1, 0}, 0x35C2 = {29594, 1, 0}, 0x35C3 = {29595, 1, 0}, 0x35C4 = {29596, 1, 0}, 0x35C5 = {29597, 1, 0}, 0x35C6 = {29598, 1, 0}, 0x35C7 = {29599, 1, 0}, 0x35C8 = {29600, 1, 0}, 0x35C9 = {29601, 1, 0}, 0x35CA = {29602, 1, 0}, 0x35CB = {29603, 1, 0}, 0x35CC = {29604, 1, 0}, 0x35CD = {29605, 1, 0}, 0x35CE = {29606, 1, 0}, 0x35CF = {29607, 1, 0}, - 0x35D0 = {29608, 1, 0}, 0x35D1 = {29609, 1, 0}, 0x35D2 = {29610, 1, 0}, 0x35D3 = {29611, 1, 0}, 0x35D4 = {29612, 1, 0}, 0x35D5 = {29613, 1, 0}, 0x35D6 = {29614, 1, 0}, 0x35D7 = {29615, 1, 0}, 0x35D8 = {29616, 1, 0}, 0x35D9 = {29617, 1, 0}, 0x35DA = {29618, 1, 0}, 0x35DB = {29619, 1, 0}, 0x35DC = {29620, 1, 0}, 0x35DD = {29621, 1, 0}, 0x35DE = {29622, 1, 0}, 0x35DF = {29623, 1, 0}, - 0x35E0 = {29624, 1, 0}, 0x35E1 = {29625, 1, 0}, 0x35E2 = {29626, 1, 0}, 0x35E3 = {29627, 1, 0}, 0x35E4 = {29628, 1, 0}, 0x35E5 = {29629, 1, 0}, 0x35E6 = {29630, 1, 0}, 0x35E7 = {29631, 1, 0}, 0x35E8 = {29632, 1, 0}, 0x35E9 = {29633, 1, 0}, 0x35EA = {29634, 1, 0}, 0x35EB = {29635, 1, 0}, 0x35EC = {29636, 1, 0}, 0x35ED = {29637, 1, 0}, 0x35EE = {29638, 1, 0}, 0x35EF = {29639, 1, 0}, - 0x35F0 = {29640, 1, 0}, 0x35F1 = {29641, 1, 0}, 0x35F2 = {29642, 1, 0}, 0x35F3 = {29643, 1, 0}, 0x35F4 = {29644, 1, 0}, 0x35F5 = {29645, 1, 0}, 0x35F6 = {29646, 1, 0}, 0x35F7 = {29647, 1, 0}, 0x35F8 = {29648, 1, 0}, 0x35F9 = {29649, 1, 0}, 0x35FA = {29650, 1, 0}, 0x35FB = {29651, 1, 0}, 0x35FC = {29652, 1, 0}, 0x35FD = {29653, 1, 0}, 0x35FE = {29654, 1, 0}, 0x35FF = {29655, 1, 0}, - 0x3600 = {29656, 3, 0}, 0x3601 = {29659, 3, 0}, 0x3602 = {29662, 3, 0}, 0x3603 = {29665, 3, 0}, 0x3604 = {29668, 3, 0}, 0x3605 = {29671, 3, 0}, 0x3606 = {29674, 3, 0}, 0x3607 = {29677, 3, 0}, 0x3608 = {29680, 3, 0}, 0x3609 = {29683, 3, 0}, 0x360A = {29686, 3, 0}, 0x360B = {29689, 3, 0}, 0x360C = {29692, 3, 0}, 0x360D = {29695, 3, 0}, 0x360E = {29698, 3, 0}, 0x360F = {29701, 3, 0}, - 0x3610 = {29704, 3, 0}, 0x3611 = {29707, 3, 0}, 0x3612 = {29710, 3, 0}, 0x3613 = {29713, 3, 0}, 0x3614 = {29716, 3, 0}, 0x3615 = {29719, 3, 0}, 0x3616 = {29722, 3, 0}, 0x3617 = {29725, 3, 0}, 0x3618 = {29728, 3, 0}, 0x3619 = {29731, 3, 0}, 0x361A = {29734, 3, 0}, 0x361B = {29737, 3, 0}, 0x361C = {29740, 3, 0}, 0x361D = {29743, 3, 0}, 0x361E = {29746, 3, 0}, 0x361F = {29749, 3, 0}, - 0x3620 = {29752, 3, 0}, 0x3621 = {29755, 3, 0}, 0x3622 = {29758, 3, 0}, 0x3623 = {29761, 3, 0}, 0x3624 = {29764, 3, 0}, 0x3625 = {29767, 3, 0}, 0x3626 = {29770, 3, 0}, 0x3627 = {29773, 3, 0}, 0x3628 = {29776, 3, 0}, 0x3629 = {29779, 3, 0}, 0x362A = {29782, 3, 0}, 0x362B = {29785, 3, 0}, 0x362C = {29788, 3, 0}, 0x362D = {29791, 3, 0}, 0x362E = {29794, 3, 0}, 0x362F = {29797, 3, 0}, - 0x3630 = {29800, 3, 0}, 0x3631 = {29803, 3, 0}, 0x3632 = {29806, 3, 0}, 0x3633 = {29809, 3, 0}, 0x3634 = {29812, 3, 0}, 0x3635 = {29815, 3, 0}, 0x3636 = {29818, 3, 0}, 0x3637 = {29821, 3, 0}, 0x3638 = {29824, 3, 0}, 0x3639 = {29827, 3, 0}, 0x363A = {29830, 3, 0}, 0x363B = {29833, 3, 0}, 0x363C = {29836, 3, 0}, 0x363D = {29839, 3, 0}, 0x363E = {29842, 3, 0}, 0x363F = {29845, 3, 0}, - 0x3640 = {29848, 3, 0}, 0x3641 = {29851, 3, 0}, 0x3642 = {29854, 3, 0}, 0x3643 = {29857, 3, 0}, 0x3644 = {29860, 3, 0}, 0x3645 = {29863, 3, 0}, 0x3646 = {29866, 3, 0}, 0x3647 = {29869, 3, 0}, 0x3648 = {29872, 3, 0}, 0x3649 = {29875, 3, 0}, 0x364A = {29878, 3, 0}, 0x364B = {29881, 3, 0}, 0x364C = {29884, 3, 0}, 0x364D = {29887, 3, 0}, 0x364E = {29890, 3, 0}, 0x364F = {29893, 3, 0}, - 0x3650 = {29896, 3, 0}, 0x3651 = {29899, 3, 0}, 0x3652 = {29902, 3, 0}, 0x3653 = {29905, 3, 0}, 0x3654 = {29908, 3, 0}, 0x3655 = {29911, 3, 0}, 0x3656 = {29914, 3, 0}, 0x3657 = {29917, 3, 0}, 0x3658 = {29920, 3, 0}, 0x3659 = {29923, 3, 0}, 0x365A = {29926, 3, 0}, 0x365B = {29929, 3, 0}, 0x365C = {29932, 3, 0}, 0x365D = {29935, 3, 0}, 0x365E = {29938, 3, 0}, 0x365F = {29941, 3, 0}, - 0x3660 = {29944, 3, 0}, 0x3661 = {29947, 3, 0}, 0x3662 = {29950, 3, 0}, 0x3663 = {29953, 3, 0}, 0x3664 = {29956, 3, 0}, 0x3665 = {29959, 3, 0}, 0x3666 = {29962, 3, 0}, 0x3667 = {29965, 3, 0}, 0x3668 = {29968, 3, 0}, 0x3669 = {29971, 3, 0}, 0x366A = {29974, 3, 0}, 0x366B = {29977, 3, 0}, 0x366C = {29980, 3, 0}, 0x366D = {29983, 3, 0}, 0x366E = {29986, 3, 0}, 0x366F = {29989, 3, 0}, - 0x3670 = {29992, 3, 0}, 0x3671 = {29995, 3, 0}, 0x3672 = {29998, 3, 0}, 0x3673 = {30001, 3, 0}, 0x3674 = {30004, 3, 0}, 0x3675 = {30007, 3, 0}, 0x3676 = {30010, 3, 0}, 0x3677 = {30013, 3, 0}, 0x3678 = {30016, 3, 0}, 0x3679 = {30019, 3, 0}, 0x367A = {30022, 3, 0}, 0x367B = {30025, 3, 0}, 0x367C = {30028, 3, 0}, 0x367D = {30031, 3, 0}, 0x367E = {30034, 3, 0}, 0x367F = {30037, 3, 0}, - 0x3680 = {30040, 3, 0}, 0x3681 = {30043, 3, 0}, 0x3682 = {30046, 3, 0}, 0x3683 = {30049, 3, 0}, 0x3684 = {30052, 3, 0}, 0x3685 = {30055, 3, 0}, 0x3686 = {30058, 3, 0}, 0x3687 = {30061, 3, 0}, 0x3688 = {30064, 3, 0}, 0x3689 = {30067, 3, 0}, 0x368A = {30070, 3, 0}, 0x368B = {30073, 3, 0}, 0x368C = {30076, 3, 0}, 0x368D = {30079, 3, 0}, 0x368E = {30082, 3, 0}, 0x368F = {30085, 3, 0}, - 0x3690 = {30088, 3, 0}, 0x3691 = {30091, 3, 0}, 0x3692 = {30094, 3, 0}, 0x3693 = {30097, 3, 0}, 0x3694 = {30100, 3, 0}, 0x3695 = {30103, 3, 0}, 0x3696 = {30106, 3, 0}, 0x3697 = {30109, 3, 0}, 0x3698 = {30112, 3, 0}, 0x3699 = {30115, 3, 0}, 0x369A = {30118, 3, 0}, 0x369B = {30121, 3, 0}, 0x369C = {30124, 3, 0}, 0x369D = {30127, 3, 0}, 0x369E = {30130, 3, 0}, 0x369F = {30133, 3, 0}, - 0x36A0 = {30136, 3, 0}, 0x36A1 = {30139, 3, 0}, 0x36A2 = {30142, 3, 0}, 0x36A3 = {30145, 3, 0}, 0x36A4 = {30148, 3, 0}, 0x36A5 = {30151, 3, 0}, 0x36A6 = {30154, 3, 0}, 0x36A7 = {30157, 3, 0}, 0x36A8 = {30160, 3, 0}, 0x36A9 = {30163, 3, 0}, 0x36AA = {30166, 3, 0}, 0x36AB = {30169, 3, 0}, 0x36AC = {30172, 3, 0}, 0x36AD = {30175, 3, 0}, 0x36AE = {30178, 3, 0}, 0x36AF = {30181, 3, 0}, - 0x36B0 = {30184, 3, 0}, 0x36B1 = {30187, 3, 0}, 0x36B2 = {30190, 3, 0}, 0x36B3 = {30193, 3, 0}, 0x36B4 = {30196, 3, 0}, 0x36B5 = {30199, 3, 0}, 0x36B6 = {30202, 3, 0}, 0x36B7 = {30205, 3, 0}, 0x36B8 = {30208, 3, 0}, 0x36B9 = {30211, 3, 0}, 0x36BA = {30214, 3, 0}, 0x36BB = {30217, 3, 0}, 0x36BC = {30220, 3, 0}, 0x36BD = {30223, 3, 0}, 0x36BE = {30226, 3, 0}, 0x36BF = {30229, 3, 0}, - 0x36C0 = {30232, 3, 0}, 0x36C1 = {30235, 3, 0}, 0x36C2 = {30238, 3, 0}, 0x36C3 = {30241, 3, 0}, 0x36C4 = {30244, 3, 0}, 0x36C5 = {30247, 3, 0}, 0x36C6 = {30250, 3, 0}, 0x36C7 = {30253, 3, 0}, 0x36C8 = {30256, 3, 0}, 0x36C9 = {30259, 3, 0}, 0x36CA = {30262, 3, 0}, 0x36CB = {30265, 3, 0}, 0x36CC = {30268, 3, 0}, 0x36CD = {30271, 3, 0}, 0x36CE = {30274, 3, 0}, 0x36CF = {30277, 3, 0}, - 0x36D0 = {30280, 3, 0}, 0x36D1 = {30283, 3, 0}, 0x36D2 = {30286, 3, 0}, 0x36D3 = {30289, 3, 0}, 0x36D4 = {30292, 3, 0}, 0x36D5 = {30295, 3, 0}, 0x36D6 = {30298, 3, 0}, 0x36D7 = {30301, 3, 0}, 0x36D8 = {30304, 3, 0}, 0x36D9 = {30307, 3, 0}, 0x36DA = {30310, 3, 0}, 0x36DB = {30313, 3, 0}, 0x36DC = {30316, 3, 0}, 0x36DD = {30319, 3, 0}, 0x36DE = {30322, 3, 0}, 0x36DF = {30325, 3, 0}, - 0x36E0 = {30328, 3, 0}, 0x36E1 = {30331, 3, 0}, 0x36E2 = {30334, 3, 0}, 0x36E3 = {30337, 3, 0}, 0x36E4 = {30340, 3, 0}, 0x36E5 = {30343, 3, 0}, 0x36E6 = {30346, 3, 0}, 0x36E7 = {30349, 3, 0}, 0x36E8 = {30352, 3, 0}, 0x36E9 = {30355, 3, 0}, 0x36EA = {30358, 3, 0}, 0x36EB = {30361, 3, 0}, 0x36EC = {30364, 3, 0}, 0x36ED = {30367, 3, 0}, 0x36EE = {30370, 3, 0}, 0x36EF = {30373, 3, 0}, - 0x36F0 = {30376, 3, 0}, 0x36F1 = {30379, 3, 0}, 0x36F2 = {30382, 3, 0}, 0x36F3 = {30385, 3, 0}, 0x36F4 = {30388, 3, 0}, 0x36F5 = {30391, 3, 0}, 0x36F6 = {30394, 3, 0}, 0x36F7 = {30397, 3, 0}, 0x36F8 = {30400, 3, 0}, 0x36F9 = {30403, 3, 0}, 0x36FA = {30406, 3, 0}, 0x36FB = {30409, 3, 0}, 0x36FC = {30412, 3, 0}, 0x36FD = {30415, 3, 0}, 0x36FE = {30418, 3, 0}, 0x36FF = {30421, 3, 0}, - 0x3700 = {30424, 1, 0}, 0x3701 = {30425, 1, 0}, 0x3702 = {30426, 1, 0}, 0x3703 = {30427, 1, 0}, 0x3704 = {30428, 1, 0}, 0x3705 = {30429, 1, 0}, 0x3706 = {30430, 1, 0}, 0x3707 = {30431, 1, 0}, 0x3708 = {30432, 1, 0}, 0x3709 = {30433, 1, 0}, 0x370A = {30434, 1, 0}, 0x370B = {30435, 1, 0}, 0x370C = {30436, 1, 0}, 0x370D = {30437, 1, 0}, 0x370E = {30438, 1, 0}, 0x370F = {30439, 1, 0}, - 0x3710 = {30440, 1, 0}, 0x3711 = {30441, 1, 0}, 0x3712 = {30442, 1, 0}, 0x3713 = {30443, 1, 0}, 0x3714 = {30444, 1, 0}, 0x3715 = {30445, 1, 0}, 0x3716 = {30446, 1, 0}, 0x3717 = {30447, 1, 0}, 0x3718 = {30448, 1, 0}, 0x3719 = {30449, 1, 0}, 0x371A = {30450, 1, 0}, 0x371B = {30451, 1, 0}, 0x371C = {30452, 1, 0}, 0x371D = {30453, 1, 0}, 0x371E = {30454, 1, 0}, 0x371F = {30455, 1, 0}, - 0x3720 = {30456, 1, 0}, 0x3721 = {30457, 1, 0}, 0x3722 = {30458, 1, 0}, 0x3723 = {30459, 1, 0}, 0x3724 = {30460, 1, 0}, 0x3725 = {30461, 1, 0}, 0x3726 = {30462, 1, 0}, 0x3727 = {30463, 1, 0}, 0x3728 = {30464, 1, 0}, 0x3729 = {30465, 1, 0}, 0x372A = {30466, 1, 0}, 0x372B = {30467, 1, 0}, 0x372C = {30468, 1, 0}, 0x372D = {30469, 1, 0}, 0x372E = {30470, 1, 0}, 0x372F = {30471, 1, 0}, - 0x3730 = {30472, 1, 0}, 0x3731 = {30473, 1, 0}, 0x3732 = {30474, 1, 0}, 0x3733 = {30475, 1, 0}, 0x3734 = {30476, 1, 0}, 0x3735 = {30477, 1, 0}, 0x3736 = {30478, 1, 0}, 0x3737 = {30479, 1, 0}, 0x3738 = {30480, 1, 0}, 0x3739 = {30481, 1, 0}, 0x373A = {30482, 1, 0}, 0x373B = {30483, 1, 0}, 0x373C = {30484, 1, 0}, 0x373D = {30485, 1, 0}, 0x373E = {30486, 1, 0}, 0x373F = {30487, 1, 0}, - 0x3740 = {30488, 1, 0}, 0x3741 = {30489, 1, 0}, 0x3742 = {30490, 1, 0}, 0x3743 = {30491, 1, 0}, 0x3744 = {30492, 1, 0}, 0x3745 = {30493, 1, 0}, 0x3746 = {30494, 1, 0}, 0x3747 = {30495, 1, 0}, 0x3748 = {30496, 1, 0}, 0x3749 = {30497, 1, 0}, 0x374A = {30498, 1, 0}, 0x374B = {30499, 1, 0}, 0x374C = {30500, 1, 0}, 0x374D = {30501, 1, 0}, 0x374E = {30502, 1, 0}, 0x374F = {30503, 1, 0}, - 0x3750 = {30504, 1, 0}, 0x3751 = {30505, 1, 0}, 0x3752 = {30506, 1, 0}, 0x3753 = {30507, 1, 0}, 0x3754 = {30508, 1, 0}, 0x3755 = {30509, 1, 0}, 0x3756 = {30510, 1, 0}, 0x3757 = {30511, 1, 0}, 0x3758 = {30512, 1, 0}, 0x3759 = {30513, 1, 0}, 0x375A = {30514, 1, 0}, 0x375B = {30515, 1, 0}, 0x375C = {30516, 1, 0}, 0x375D = {30517, 1, 0}, 0x375E = {30518, 1, 0}, 0x375F = {30519, 1, 0}, - 0x3760 = {30520, 1, 0}, 0x3761 = {30521, 1, 0}, 0x3762 = {30522, 1, 0}, 0x3763 = {30523, 1, 0}, 0x3764 = {30524, 1, 0}, 0x3765 = {30525, 1, 0}, 0x3766 = {30526, 1, 0}, 0x3767 = {30527, 1, 0}, 0x3768 = {30528, 1, 0}, 0x3769 = {30529, 1, 0}, 0x376A = {30530, 1, 0}, 0x376B = {30531, 1, 0}, 0x376C = {30532, 1, 0}, 0x376D = {30533, 1, 0}, 0x376E = {30534, 1, 0}, 0x376F = {30535, 1, 0}, - 0x3770 = {30536, 1, 0}, 0x3771 = {30537, 1, 0}, 0x3772 = {30538, 1, 0}, 0x3773 = {30539, 1, 0}, 0x3774 = {30540, 1, 0}, 0x3775 = {30541, 1, 0}, 0x3776 = {30542, 1, 0}, 0x3777 = {30543, 1, 0}, 0x3778 = {30544, 1, 0}, 0x3779 = {30545, 1, 0}, 0x377A = {30546, 1, 0}, 0x377B = {30547, 1, 0}, 0x377C = {30548, 1, 0}, 0x377D = {30549, 1, 0}, 0x377E = {30550, 1, 0}, 0x377F = {30551, 1, 0}, - 0x3780 = {30552, 1, 0}, 0x3781 = {30553, 1, 0}, 0x3782 = {30554, 1, 0}, 0x3783 = {30555, 1, 0}, 0x3784 = {30556, 1, 0}, 0x3785 = {30557, 1, 0}, 0x3786 = {30558, 1, 0}, 0x3787 = {30559, 1, 0}, 0x3788 = {30560, 1, 0}, 0x3789 = {30561, 1, 0}, 0x378A = {30562, 1, 0}, 0x378B = {30563, 1, 0}, 0x378C = {30564, 1, 0}, 0x378D = {30565, 1, 0}, 0x378E = {30566, 1, 0}, 0x378F = {30567, 1, 0}, - 0x3790 = {30568, 1, 0}, 0x3791 = {30569, 1, 0}, 0x3792 = {30570, 1, 0}, 0x3793 = {30571, 1, 0}, 0x3794 = {30572, 1, 0}, 0x3795 = {30573, 1, 0}, 0x3796 = {30574, 1, 0}, 0x3797 = {30575, 1, 0}, 0x3798 = {30576, 1, 0}, 0x3799 = {30577, 1, 0}, 0x379A = {30578, 1, 0}, 0x379B = {30579, 1, 0}, 0x379C = {30580, 1, 0}, 0x379D = {30581, 1, 0}, 0x379E = {30582, 1, 0}, 0x379F = {30583, 1, 0}, - 0x37A0 = {30584, 1, 0}, 0x37A1 = {30585, 1, 0}, 0x37A2 = {30586, 1, 0}, 0x37A3 = {30587, 1, 0}, 0x37A4 = {30588, 1, 0}, 0x37A5 = {30589, 1, 0}, 0x37A6 = {30590, 1, 0}, 0x37A7 = {30591, 1, 0}, 0x37A8 = {30592, 1, 0}, 0x37A9 = {30593, 1, 0}, 0x37AA = {30594, 1, 0}, 0x37AB = {30595, 1, 0}, 0x37AC = {30596, 1, 0}, 0x37AD = {30597, 1, 0}, 0x37AE = {30598, 1, 0}, 0x37AF = {30599, 1, 0}, - 0x37B0 = {30600, 1, 0}, 0x37B1 = {30601, 1, 0}, 0x37B2 = {30602, 1, 0}, 0x37B3 = {30603, 1, 0}, 0x37B4 = {30604, 1, 0}, 0x37B5 = {30605, 1, 0}, 0x37B6 = {30606, 1, 0}, 0x37B7 = {30607, 1, 0}, 0x37B8 = {30608, 1, 0}, 0x37B9 = {30609, 1, 0}, 0x37BA = {30610, 1, 0}, 0x37BB = {30611, 1, 0}, 0x37BC = {30612, 1, 0}, 0x37BD = {30613, 1, 0}, 0x37BE = {30614, 1, 0}, 0x37BF = {30615, 1, 0}, - 0x37C0 = {30616, 1, 0}, 0x37C1 = {30617, 1, 0}, 0x37C2 = {30618, 1, 0}, 0x37C3 = {30619, 1, 0}, 0x37C4 = {30620, 1, 0}, 0x37C5 = {30621, 1, 0}, 0x37C6 = {30622, 1, 0}, 0x37C7 = {30623, 1, 0}, 0x37C8 = {30624, 1, 0}, 0x37C9 = {30625, 1, 0}, 0x37CA = {30626, 1, 0}, 0x37CB = {30627, 1, 0}, 0x37CC = {30628, 1, 0}, 0x37CD = {30629, 1, 0}, 0x37CE = {30630, 1, 0}, 0x37CF = {30631, 1, 0}, - 0x37D0 = {30632, 1, 0}, 0x37D1 = {30633, 1, 0}, 0x37D2 = {30634, 1, 0}, 0x37D3 = {30635, 1, 0}, 0x37D4 = {30636, 1, 0}, 0x37D5 = {30637, 1, 0}, 0x37D6 = {30638, 1, 0}, 0x37D7 = {30639, 1, 0}, 0x37D8 = {30640, 1, 0}, 0x37D9 = {30641, 1, 0}, 0x37DA = {30642, 1, 0}, 0x37DB = {30643, 1, 0}, 0x37DC = {30644, 1, 0}, 0x37DD = {30645, 1, 0}, 0x37DE = {30646, 1, 0}, 0x37DF = {30647, 1, 0}, - 0x37E0 = {30648, 1, 0}, 0x37E1 = {30649, 1, 0}, 0x37E2 = {30650, 1, 0}, 0x37E3 = {30651, 1, 0}, 0x37E4 = {30652, 1, 0}, 0x37E5 = {30653, 1, 0}, 0x37E6 = {30654, 1, 0}, 0x37E7 = {30655, 1, 0}, 0x37E8 = {30656, 1, 0}, 0x37E9 = {30657, 1, 0}, 0x37EA = {30658, 1, 0}, 0x37EB = {30659, 1, 0}, 0x37EC = {30660, 1, 0}, 0x37ED = {30661, 1, 0}, 0x37EE = {30662, 1, 0}, 0x37EF = {30663, 1, 0}, - 0x37F0 = {30664, 1, 0}, 0x37F1 = {30665, 1, 0}, 0x37F2 = {30666, 1, 0}, 0x37F3 = {30667, 1, 0}, 0x37F4 = {30668, 1, 0}, 0x37F5 = {30669, 1, 0}, 0x37F6 = {30670, 1, 0}, 0x37F7 = {30671, 1, 0}, 0x37F8 = {30672, 1, 0}, 0x37F9 = {30673, 1, 0}, 0x37FA = {30674, 1, 0}, 0x37FB = {30675, 1, 0}, 0x37FC = {30676, 1, 0}, 0x37FD = {30677, 1, 0}, 0x37FE = {30678, 1, 0}, 0x37FF = {30679, 1, 0}, - 0x3800 = {30680, 3, 0}, 0x3801 = {30683, 1, 0}, 0x3802 = {30684, 1, 0}, 0x3803 = {30685, 1, 0}, 0x3804 = {30686, 1, 0}, 0x3805 = {30687, 1, 0}, 0x3806 = {30688, 1, 0}, 0x3807 = {30689, 1, 0}, 0x3808 = {30690, 2, 0}, 0x3809 = {30692, 1, 0}, 0x380A = {30693, 1, 0}, 0x380B = {30694, 1, 0}, 0x380C = {30695, 1, 0}, 0x380D = {30696, 1, 0}, 0x380E = {30697, 1, 0}, 0x380F = {30698, 1, 0}, - 0x3810 = {30699, 2, 0}, 0x3811 = {30701, 1, 0}, 0x3812 = {30702, 1, 0}, 0x3813 = {30703, 1, 0}, 0x3814 = {30704, 1, 0}, 0x3815 = {30705, 1, 0}, 0x3816 = {30706, 1, 0}, 0x3817 = {30707, 1, 0}, 0x3818 = {30708, 2, 0}, 0x3819 = {30710, 1, 0}, 0x381A = {30711, 1, 0}, 0x381B = {30712, 1, 0}, 0x381C = {30713, 1, 0}, 0x381D = {30714, 1, 0}, 0x381E = {30715, 1, 0}, 0x381F = {30716, 1, 0}, - 0x3820 = {30717, 2, 0}, 0x3821 = {30719, 1, 0}, 0x3822 = {30720, 1, 0}, 0x3823 = {30721, 1, 0}, 0x3824 = {30722, 1, 0}, 0x3825 = {30723, 1, 0}, 0x3826 = {30724, 1, 0}, 0x3827 = {30725, 1, 0}, 0x3828 = {30726, 2, 0}, 0x3829 = {30728, 1, 0}, 0x382A = {30729, 1, 0}, 0x382B = {30730, 1, 0}, 0x382C = {30731, 1, 0}, 0x382D = {30732, 1, 0}, 0x382E = {30733, 1, 0}, 0x382F = {30734, 1, 0}, - 0x3830 = {30735, 2, 0}, 0x3831 = {30737, 1, 0}, 0x3832 = {30738, 1, 0}, 0x3833 = {30739, 1, 0}, 0x3834 = {30740, 1, 0}, 0x3835 = {30741, 1, 0}, 0x3836 = {30742, 1, 0}, 0x3837 = {30743, 1, 0}, 0x3838 = {30744, 2, 0}, 0x3839 = {30746, 1, 0}, 0x383A = {30747, 1, 0}, 0x383B = {30748, 1, 0}, 0x383C = {30749, 1, 0}, 0x383D = {30750, 1, 0}, 0x383E = {30751, 1, 0}, 0x383F = {30752, 1, 0}, - 0x3840 = {30753, 2, 0}, 0x3841 = {30755, 1, 0}, 0x3842 = {30756, 1, 0}, 0x3843 = {30757, 1, 0}, 0x3844 = {30758, 1, 0}, 0x3845 = {30759, 1, 0}, 0x3846 = {30760, 1, 0}, 0x3847 = {30761, 1, 0}, 0x3848 = {30762, 2, 0}, 0x3849 = {30764, 1, 0}, 0x384A = {30765, 1, 0}, 0x384B = {30766, 1, 0}, 0x384C = {30767, 1, 0}, 0x384D = {30768, 1, 0}, 0x384E = {30769, 1, 0}, 0x384F = {30770, 1, 0}, - 0x3850 = {30771, 2, 0}, 0x3851 = {30773, 1, 0}, 0x3852 = {30774, 1, 0}, 0x3853 = {30775, 1, 0}, 0x3854 = {30776, 1, 0}, 0x3855 = {30777, 1, 0}, 0x3856 = {30778, 1, 0}, 0x3857 = {30779, 1, 0}, 0x3858 = {30780, 2, 0}, 0x3859 = {30782, 1, 0}, 0x385A = {30783, 1, 0}, 0x385B = {30784, 1, 0}, 0x385C = {30785, 1, 0}, 0x385D = {30786, 1, 0}, 0x385E = {30787, 1, 0}, 0x385F = {30788, 1, 0}, - 0x3860 = {30789, 2, 0}, 0x3861 = {30791, 1, 0}, 0x3862 = {30792, 1, 0}, 0x3863 = {30793, 1, 0}, 0x3864 = {30794, 1, 0}, 0x3865 = {30795, 1, 0}, 0x3866 = {30796, 1, 0}, 0x3867 = {30797, 1, 0}, 0x3868 = {30798, 2, 0}, 0x3869 = {30800, 1, 0}, 0x386A = {30801, 1, 0}, 0x386B = {30802, 1, 0}, 0x386C = {30803, 1, 0}, 0x386D = {30804, 1, 0}, 0x386E = {30805, 1, 0}, 0x386F = {30806, 1, 0}, - 0x3870 = {30807, 2, 0}, 0x3871 = {30809, 1, 0}, 0x3872 = {30810, 1, 0}, 0x3873 = {30811, 1, 0}, 0x3874 = {30812, 1, 0}, 0x3875 = {30813, 1, 0}, 0x3876 = {30814, 1, 0}, 0x3877 = {30815, 1, 0}, 0x3878 = {30816, 2, 0}, 0x3879 = {30818, 1, 0}, 0x387A = {30819, 1, 0}, 0x387B = {30820, 1, 0}, 0x387C = {30821, 1, 0}, 0x387D = {30822, 1, 0}, 0x387E = {30823, 1, 0}, 0x387F = {30824, 1, 0}, - 0x3880 = {30825, 2, 0}, 0x3881 = {30827, 1, 0}, 0x3882 = {30828, 1, 0}, 0x3883 = {30829, 1, 0}, 0x3884 = {30830, 1, 0}, 0x3885 = {30831, 1, 0}, 0x3886 = {30832, 1, 0}, 0x3887 = {30833, 1, 0}, 0x3888 = {30834, 2, 0}, 0x3889 = {30836, 1, 0}, 0x388A = {30837, 1, 0}, 0x388B = {30838, 1, 0}, 0x388C = {30839, 1, 0}, 0x388D = {30840, 1, 0}, 0x388E = {30841, 1, 0}, 0x388F = {30842, 1, 0}, - 0x3890 = {30843, 2, 0}, 0x3891 = {30845, 1, 0}, 0x3892 = {30846, 1, 0}, 0x3893 = {30847, 1, 0}, 0x3894 = {30848, 1, 0}, 0x3895 = {30849, 1, 0}, 0x3896 = {30850, 1, 0}, 0x3897 = {30851, 1, 0}, 0x3898 = {30852, 2, 0}, 0x3899 = {30854, 1, 0}, 0x389A = {30855, 1, 0}, 0x389B = {30856, 1, 0}, 0x389C = {30857, 1, 0}, 0x389D = {30858, 1, 0}, 0x389E = {30859, 1, 0}, 0x389F = {30860, 1, 0}, - 0x38A0 = {30861, 2, 0}, 0x38A1 = {30863, 1, 0}, 0x38A2 = {30864, 1, 0}, 0x38A3 = {30865, 1, 0}, 0x38A4 = {30866, 1, 0}, 0x38A5 = {30867, 1, 0}, 0x38A6 = {30868, 1, 0}, 0x38A7 = {30869, 1, 0}, 0x38A8 = {30870, 2, 0}, 0x38A9 = {30872, 1, 0}, 0x38AA = {30873, 1, 0}, 0x38AB = {30874, 1, 0}, 0x38AC = {30875, 1, 0}, 0x38AD = {30876, 1, 0}, 0x38AE = {30877, 1, 0}, 0x38AF = {30878, 1, 0}, - 0x38B0 = {30879, 2, 0}, 0x38B1 = {30881, 1, 0}, 0x38B2 = {30882, 1, 0}, 0x38B3 = {30883, 1, 0}, 0x38B4 = {30884, 1, 0}, 0x38B5 = {30885, 1, 0}, 0x38B6 = {30886, 1, 0}, 0x38B7 = {30887, 1, 0}, 0x38B8 = {30888, 2, 0}, 0x38B9 = {30890, 1, 0}, 0x38BA = {30891, 1, 0}, 0x38BB = {30892, 1, 0}, 0x38BC = {30893, 1, 0}, 0x38BD = {30894, 1, 0}, 0x38BE = {30895, 1, 0}, 0x38BF = {30896, 1, 0}, - 0x38C0 = {30897, 2, 0}, 0x38C1 = {30899, 1, 0}, 0x38C2 = {30900, 1, 0}, 0x38C3 = {30901, 1, 0}, 0x38C4 = {30902, 1, 0}, 0x38C5 = {30903, 1, 0}, 0x38C6 = {30904, 1, 0}, 0x38C7 = {30905, 1, 0}, 0x38C8 = {30906, 2, 0}, 0x38C9 = {30908, 1, 0}, 0x38CA = {30909, 1, 0}, 0x38CB = {30910, 1, 0}, 0x38CC = {30911, 1, 0}, 0x38CD = {30912, 1, 0}, 0x38CE = {30913, 1, 0}, 0x38CF = {30914, 1, 0}, - 0x38D0 = {30915, 2, 0}, 0x38D1 = {30917, 1, 0}, 0x38D2 = {30918, 1, 0}, 0x38D3 = {30919, 1, 0}, 0x38D4 = {30920, 1, 0}, 0x38D5 = {30921, 1, 0}, 0x38D6 = {30922, 1, 0}, 0x38D7 = {30923, 1, 0}, 0x38D8 = {30924, 2, 0}, 0x38D9 = {30926, 1, 0}, 0x38DA = {30927, 1, 0}, 0x38DB = {30928, 1, 0}, 0x38DC = {30929, 1, 0}, 0x38DD = {30930, 1, 0}, 0x38DE = {30931, 1, 0}, 0x38DF = {30932, 1, 0}, - 0x38E0 = {30933, 2, 0}, 0x38E1 = {30935, 1, 0}, 0x38E2 = {30936, 1, 0}, 0x38E3 = {30937, 1, 0}, 0x38E4 = {30938, 1, 0}, 0x38E5 = {30939, 1, 0}, 0x38E6 = {30940, 1, 0}, 0x38E7 = {30941, 1, 0}, 0x38E8 = {30942, 2, 0}, 0x38E9 = {30944, 1, 0}, 0x38EA = {30945, 1, 0}, 0x38EB = {30946, 1, 0}, 0x38EC = {30947, 1, 0}, 0x38ED = {30948, 1, 0}, 0x38EE = {30949, 1, 0}, 0x38EF = {30950, 1, 0}, - 0x38F0 = {30951, 2, 0}, 0x38F1 = {30953, 1, 0}, 0x38F2 = {30954, 1, 0}, 0x38F3 = {30955, 1, 0}, 0x38F4 = {30956, 1, 0}, 0x38F5 = {30957, 1, 0}, 0x38F6 = {30958, 1, 0}, 0x38F7 = {30959, 1, 0}, 0x38F8 = {30960, 2, 0}, 0x38F9 = {30962, 1, 0}, 0x38FA = {30963, 1, 0}, 0x38FB = {30964, 1, 0}, 0x38FC = {30965, 1, 0}, 0x38FD = {30966, 1, 0}, 0x38FE = {30967, 1, 0}, 0x38FF = {30968, 1, 0}, - 0x3900 = {30969, 4, 0}, 0x3901 = {30973, 4, 0}, 0x3902 = {30977, 3, 0}, 0x3903 = {30980, 4, 0}, 0x3904 = {30984, 3, 0}, 0x3905 = {30987, 4, 0}, 0x3906 = {30991, 3, 0}, 0x3907 = {30994, 4, 0}, 0x3908 = {30998, 3, 0}, 0x3909 = {31001, 4, 0}, 0x390A = {31005, 3, 0}, 0x390B = {31008, 4, 0}, 0x390C = {31012, 3, 0}, 0x390D = {31015, 4, 0}, 0x390E = {31019, 3, 0}, 0x390F = {31022, 4, 0}, - 0x3910 = {31026, 3, 0}, 0x3911 = {31029, 4, 0}, 0x3912 = {31033, 3, 0}, 0x3913 = {31036, 4, 0}, 0x3914 = {31040, 3, 0}, 0x3915 = {31043, 4, 0}, 0x3916 = {31047, 3, 0}, 0x3917 = {31050, 4, 0}, 0x3918 = {31054, 3, 0}, 0x3919 = {31057, 4, 0}, 0x391A = {31061, 3, 0}, 0x391B = {31064, 4, 0}, 0x391C = {31068, 3, 0}, 0x391D = {31071, 4, 0}, 0x391E = {31075, 3, 0}, 0x391F = {31078, 4, 0}, - 0x3920 = {31082, 3, 0}, 0x3921 = {31085, 4, 0}, 0x3922 = {31089, 3, 0}, 0x3923 = {31092, 4, 0}, 0x3924 = {31096, 3, 0}, 0x3925 = {31099, 4, 0}, 0x3926 = {31103, 3, 0}, 0x3927 = {31106, 4, 0}, 0x3928 = {31110, 3, 0}, 0x3929 = {31113, 4, 0}, 0x392A = {31117, 3, 0}, 0x392B = {31120, 4, 0}, 0x392C = {31124, 3, 0}, 0x392D = {31127, 4, 0}, 0x392E = {31131, 3, 0}, 0x392F = {31134, 4, 0}, - 0x3930 = {31138, 3, 0}, 0x3931 = {31141, 4, 0}, 0x3932 = {31145, 3, 0}, 0x3933 = {31148, 4, 0}, 0x3934 = {31152, 3, 0}, 0x3935 = {31155, 4, 0}, 0x3936 = {31159, 3, 0}, 0x3937 = {31162, 4, 0}, 0x3938 = {31166, 3, 0}, 0x3939 = {31169, 4, 0}, 0x393A = {31173, 3, 0}, 0x393B = {31176, 4, 0}, 0x393C = {31180, 3, 0}, 0x393D = {31183, 4, 0}, 0x393E = {31187, 3, 0}, 0x393F = {31190, 4, 0}, - 0x3940 = {31194, 3, 0}, 0x3941 = {31197, 4, 0}, 0x3942 = {31201, 3, 0}, 0x3943 = {31204, 4, 0}, 0x3944 = {31208, 3, 0}, 0x3945 = {31211, 4, 0}, 0x3946 = {31215, 3, 0}, 0x3947 = {31218, 4, 0}, 0x3948 = {31222, 3, 0}, 0x3949 = {31225, 4, 0}, 0x394A = {31229, 3, 0}, 0x394B = {31232, 4, 0}, 0x394C = {31236, 3, 0}, 0x394D = {31239, 4, 0}, 0x394E = {31243, 3, 0}, 0x394F = {31246, 4, 0}, - 0x3950 = {31250, 3, 0}, 0x3951 = {31253, 4, 0}, 0x3952 = {31257, 3, 0}, 0x3953 = {31260, 4, 0}, 0x3954 = {31264, 3, 0}, 0x3955 = {31267, 4, 0}, 0x3956 = {31271, 3, 0}, 0x3957 = {31274, 4, 0}, 0x3958 = {31278, 3, 0}, 0x3959 = {31281, 4, 0}, 0x395A = {31285, 3, 0}, 0x395B = {31288, 4, 0}, 0x395C = {31292, 3, 0}, 0x395D = {31295, 4, 0}, 0x395E = {31299, 3, 0}, 0x395F = {31302, 4, 0}, - 0x3960 = {31306, 3, 0}, 0x3961 = {31309, 4, 0}, 0x3962 = {31313, 3, 0}, 0x3963 = {31316, 4, 0}, 0x3964 = {31320, 3, 0}, 0x3965 = {31323, 4, 0}, 0x3966 = {31327, 3, 0}, 0x3967 = {31330, 4, 0}, 0x3968 = {31334, 3, 0}, 0x3969 = {31337, 4, 0}, 0x396A = {31341, 3, 0}, 0x396B = {31344, 4, 0}, 0x396C = {31348, 3, 0}, 0x396D = {31351, 4, 0}, 0x396E = {31355, 3, 0}, 0x396F = {31358, 4, 0}, - 0x3970 = {31362, 3, 0}, 0x3971 = {31365, 4, 0}, 0x3972 = {31369, 3, 0}, 0x3973 = {31372, 4, 0}, 0x3974 = {31376, 3, 0}, 0x3975 = {31379, 4, 0}, 0x3976 = {31383, 3, 0}, 0x3977 = {31386, 4, 0}, 0x3978 = {31390, 3, 0}, 0x3979 = {31393, 4, 0}, 0x397A = {31397, 3, 0}, 0x397B = {31400, 4, 0}, 0x397C = {31404, 3, 0}, 0x397D = {31407, 4, 0}, 0x397E = {31411, 3, 0}, 0x397F = {31414, 4, 0}, - 0x3980 = {31418, 3, 0}, 0x3981 = {31421, 4, 0}, 0x3982 = {31425, 3, 0}, 0x3983 = {31428, 4, 0}, 0x3984 = {31432, 3, 0}, 0x3985 = {31435, 4, 0}, 0x3986 = {31439, 3, 0}, 0x3987 = {31442, 4, 0}, 0x3988 = {31446, 3, 0}, 0x3989 = {31449, 4, 0}, 0x398A = {31453, 3, 0}, 0x398B = {31456, 4, 0}, 0x398C = {31460, 3, 0}, 0x398D = {31463, 4, 0}, 0x398E = {31467, 3, 0}, 0x398F = {31470, 4, 0}, - 0x3990 = {31474, 3, 0}, 0x3991 = {31477, 4, 0}, 0x3992 = {31481, 3, 0}, 0x3993 = {31484, 4, 0}, 0x3994 = {31488, 3, 0}, 0x3995 = {31491, 4, 0}, 0x3996 = {31495, 3, 0}, 0x3997 = {31498, 4, 0}, 0x3998 = {31502, 3, 0}, 0x3999 = {31505, 4, 0}, 0x399A = {31509, 3, 0}, 0x399B = {31512, 4, 0}, 0x399C = {31516, 3, 0}, 0x399D = {31519, 4, 0}, 0x399E = {31523, 3, 0}, 0x399F = {31526, 4, 0}, - 0x39A0 = {31530, 3, 0}, 0x39A1 = {31533, 4, 0}, 0x39A2 = {31537, 3, 0}, 0x39A3 = {31540, 4, 0}, 0x39A4 = {31544, 3, 0}, 0x39A5 = {31547, 4, 0}, 0x39A6 = {31551, 3, 0}, 0x39A7 = {31554, 4, 0}, 0x39A8 = {31558, 3, 0}, 0x39A9 = {31561, 4, 0}, 0x39AA = {31565, 3, 0}, 0x39AB = {31568, 4, 0}, 0x39AC = {31572, 3, 0}, 0x39AD = {31575, 4, 0}, 0x39AE = {31579, 3, 0}, 0x39AF = {31582, 4, 0}, - 0x39B0 = {31586, 3, 0}, 0x39B1 = {31589, 4, 0}, 0x39B2 = {31593, 3, 0}, 0x39B3 = {31596, 4, 0}, 0x39B4 = {31600, 3, 0}, 0x39B5 = {31603, 4, 0}, 0x39B6 = {31607, 3, 0}, 0x39B7 = {31610, 4, 0}, 0x39B8 = {31614, 3, 0}, 0x39B9 = {31617, 4, 0}, 0x39BA = {31621, 3, 0}, 0x39BB = {31624, 4, 0}, 0x39BC = {31628, 3, 0}, 0x39BD = {31631, 4, 0}, 0x39BE = {31635, 3, 0}, 0x39BF = {31638, 4, 0}, - 0x39C0 = {31642, 3, 0}, 0x39C1 = {31645, 4, 0}, 0x39C2 = {31649, 3, 0}, 0x39C3 = {31652, 4, 0}, 0x39C4 = {31656, 3, 0}, 0x39C5 = {31659, 4, 0}, 0x39C6 = {31663, 3, 0}, 0x39C7 = {31666, 4, 0}, 0x39C8 = {31670, 3, 0}, 0x39C9 = {31673, 4, 0}, 0x39CA = {31677, 3, 0}, 0x39CB = {31680, 4, 0}, 0x39CC = {31684, 3, 0}, 0x39CD = {31687, 4, 0}, 0x39CE = {31691, 3, 0}, 0x39CF = {31694, 4, 0}, - 0x39D0 = {31698, 3, 0}, 0x39D1 = {31701, 4, 0}, 0x39D2 = {31705, 3, 0}, 0x39D3 = {31708, 4, 0}, 0x39D4 = {31712, 3, 0}, 0x39D5 = {31715, 4, 0}, 0x39D6 = {31719, 3, 0}, 0x39D7 = {31722, 4, 0}, 0x39D8 = {31726, 3, 0}, 0x39D9 = {31729, 4, 0}, 0x39DA = {31733, 3, 0}, 0x39DB = {31736, 4, 0}, 0x39DC = {31740, 3, 0}, 0x39DD = {31743, 4, 0}, 0x39DE = {31747, 3, 0}, 0x39DF = {31750, 4, 0}, - 0x39E0 = {31754, 3, 0}, 0x39E1 = {31757, 4, 0}, 0x39E2 = {31761, 3, 0}, 0x39E3 = {31764, 4, 0}, 0x39E4 = {31768, 3, 0}, 0x39E5 = {31771, 4, 0}, 0x39E6 = {31775, 3, 0}, 0x39E7 = {31778, 4, 0}, 0x39E8 = {31782, 3, 0}, 0x39E9 = {31785, 4, 0}, 0x39EA = {31789, 3, 0}, 0x39EB = {31792, 4, 0}, 0x39EC = {31796, 3, 0}, 0x39ED = {31799, 4, 0}, 0x39EE = {31803, 3, 0}, 0x39EF = {31806, 4, 0}, - 0x39F0 = {31810, 3, 0}, 0x39F1 = {31813, 4, 0}, 0x39F2 = {31817, 3, 0}, 0x39F3 = {31820, 4, 0}, 0x39F4 = {31824, 3, 0}, 0x39F5 = {31827, 4, 0}, 0x39F6 = {31831, 3, 0}, 0x39F7 = {31834, 4, 0}, 0x39F8 = {31838, 3, 0}, 0x39F9 = {31841, 4, 0}, 0x39FA = {31845, 3, 0}, 0x39FB = {31848, 4, 0}, 0x39FC = {31852, 3, 0}, 0x39FD = {31855, 4, 0}, 0x39FE = {31859, 3, 0}, 0x39FF = {31862, 4, 0}, - 0x3A00 = {31866, 2, 0}, 0x3A01 = {31868, 1, 0}, 0x3A02 = {31869, 2, 0}, 0x3A03 = {31871, 1, 0}, 0x3A04 = {31872, 2, 0}, 0x3A05 = {31874, 1, 0}, 0x3A06 = {31875, 2, 0}, 0x3A07 = {31877, 1, 0}, 0x3A08 = {31878, 2, 0}, 0x3A09 = {31880, 1, 0}, 0x3A0A = {31881, 2, 0}, 0x3A0B = {31883, 1, 0}, 0x3A0C = {31884, 2, 0}, 0x3A0D = {31886, 1, 0}, 0x3A0E = {31887, 2, 0}, 0x3A0F = {31889, 1, 0}, - 0x3A10 = {31890, 2, 0}, 0x3A11 = {31892, 1, 0}, 0x3A12 = {31893, 2, 0}, 0x3A13 = {31895, 1, 0}, 0x3A14 = {31896, 2, 0}, 0x3A15 = {31898, 1, 0}, 0x3A16 = {31899, 2, 0}, 0x3A17 = {31901, 1, 0}, 0x3A18 = {31902, 2, 0}, 0x3A19 = {31904, 1, 0}, 0x3A1A = {31905, 2, 0}, 0x3A1B = {31907, 1, 0}, 0x3A1C = {31908, 2, 0}, 0x3A1D = {31910, 1, 0}, 0x3A1E = {31911, 2, 0}, 0x3A1F = {31913, 1, 0}, - 0x3A20 = {31914, 2, 0}, 0x3A21 = {31916, 1, 0}, 0x3A22 = {31917, 2, 0}, 0x3A23 = {31919, 1, 0}, 0x3A24 = {31920, 2, 0}, 0x3A25 = {31922, 1, 0}, 0x3A26 = {31923, 2, 0}, 0x3A27 = {31925, 1, 0}, 0x3A28 = {31926, 2, 0}, 0x3A29 = {31928, 1, 0}, 0x3A2A = {31929, 2, 0}, 0x3A2B = {31931, 1, 0}, 0x3A2C = {31932, 2, 0}, 0x3A2D = {31934, 1, 0}, 0x3A2E = {31935, 2, 0}, 0x3A2F = {31937, 1, 0}, - 0x3A30 = {31938, 2, 0}, 0x3A31 = {31940, 1, 0}, 0x3A32 = {31941, 2, 0}, 0x3A33 = {31943, 1, 0}, 0x3A34 = {31944, 2, 0}, 0x3A35 = {31946, 1, 0}, 0x3A36 = {31947, 2, 0}, 0x3A37 = {31949, 1, 0}, 0x3A38 = {31950, 2, 0}, 0x3A39 = {31952, 1, 0}, 0x3A3A = {31953, 2, 0}, 0x3A3B = {31955, 1, 0}, 0x3A3C = {31956, 2, 0}, 0x3A3D = {31958, 1, 0}, 0x3A3E = {31959, 2, 0}, 0x3A3F = {31961, 1, 0}, - 0x3A40 = {31962, 2, 0}, 0x3A41 = {31964, 1, 0}, 0x3A42 = {31965, 2, 0}, 0x3A43 = {31967, 1, 0}, 0x3A44 = {31968, 2, 0}, 0x3A45 = {31970, 1, 0}, 0x3A46 = {31971, 2, 0}, 0x3A47 = {31973, 1, 0}, 0x3A48 = {31974, 2, 0}, 0x3A49 = {31976, 1, 0}, 0x3A4A = {31977, 2, 0}, 0x3A4B = {31979, 1, 0}, 0x3A4C = {31980, 2, 0}, 0x3A4D = {31982, 1, 0}, 0x3A4E = {31983, 2, 0}, 0x3A4F = {31985, 1, 0}, - 0x3A50 = {31986, 2, 0}, 0x3A51 = {31988, 1, 0}, 0x3A52 = {31989, 2, 0}, 0x3A53 = {31991, 1, 0}, 0x3A54 = {31992, 2, 0}, 0x3A55 = {31994, 1, 0}, 0x3A56 = {31995, 2, 0}, 0x3A57 = {31997, 1, 0}, 0x3A58 = {31998, 2, 0}, 0x3A59 = {32000, 1, 0}, 0x3A5A = {32001, 2, 0}, 0x3A5B = {32003, 1, 0}, 0x3A5C = {32004, 2, 0}, 0x3A5D = {32006, 1, 0}, 0x3A5E = {32007, 2, 0}, 0x3A5F = {32009, 1, 0}, - 0x3A60 = {32010, 2, 0}, 0x3A61 = {32012, 1, 0}, 0x3A62 = {32013, 2, 0}, 0x3A63 = {32015, 1, 0}, 0x3A64 = {32016, 2, 0}, 0x3A65 = {32018, 1, 0}, 0x3A66 = {32019, 2, 0}, 0x3A67 = {32021, 1, 0}, 0x3A68 = {32022, 2, 0}, 0x3A69 = {32024, 1, 0}, 0x3A6A = {32025, 2, 0}, 0x3A6B = {32027, 1, 0}, 0x3A6C = {32028, 2, 0}, 0x3A6D = {32030, 1, 0}, 0x3A6E = {32031, 2, 0}, 0x3A6F = {32033, 1, 0}, - 0x3A70 = {32034, 2, 0}, 0x3A71 = {32036, 1, 0}, 0x3A72 = {32037, 2, 0}, 0x3A73 = {32039, 1, 0}, 0x3A74 = {32040, 2, 0}, 0x3A75 = {32042, 1, 0}, 0x3A76 = {32043, 2, 0}, 0x3A77 = {32045, 1, 0}, 0x3A78 = {32046, 2, 0}, 0x3A79 = {32048, 1, 0}, 0x3A7A = {32049, 2, 0}, 0x3A7B = {32051, 1, 0}, 0x3A7C = {32052, 2, 0}, 0x3A7D = {32054, 1, 0}, 0x3A7E = {32055, 2, 0}, 0x3A7F = {32057, 1, 0}, - 0x3A80 = {32058, 2, 0}, 0x3A81 = {32060, 1, 0}, 0x3A82 = {32061, 2, 0}, 0x3A83 = {32063, 1, 0}, 0x3A84 = {32064, 2, 0}, 0x3A85 = {32066, 1, 0}, 0x3A86 = {32067, 2, 0}, 0x3A87 = {32069, 1, 0}, 0x3A88 = {32070, 2, 0}, 0x3A89 = {32072, 1, 0}, 0x3A8A = {32073, 2, 0}, 0x3A8B = {32075, 1, 0}, 0x3A8C = {32076, 2, 0}, 0x3A8D = {32078, 1, 0}, 0x3A8E = {32079, 2, 0}, 0x3A8F = {32081, 1, 0}, - 0x3A90 = {32082, 2, 0}, 0x3A91 = {32084, 1, 0}, 0x3A92 = {32085, 2, 0}, 0x3A93 = {32087, 1, 0}, 0x3A94 = {32088, 2, 0}, 0x3A95 = {32090, 1, 0}, 0x3A96 = {32091, 2, 0}, 0x3A97 = {32093, 1, 0}, 0x3A98 = {32094, 2, 0}, 0x3A99 = {32096, 1, 0}, 0x3A9A = {32097, 2, 0}, 0x3A9B = {32099, 1, 0}, 0x3A9C = {32100, 2, 0}, 0x3A9D = {32102, 1, 0}, 0x3A9E = {32103, 2, 0}, 0x3A9F = {32105, 1, 0}, - 0x3AA0 = {32106, 2, 0}, 0x3AA1 = {32108, 1, 0}, 0x3AA2 = {32109, 2, 0}, 0x3AA3 = {32111, 1, 0}, 0x3AA4 = {32112, 2, 0}, 0x3AA5 = {32114, 1, 0}, 0x3AA6 = {32115, 2, 0}, 0x3AA7 = {32117, 1, 0}, 0x3AA8 = {32118, 2, 0}, 0x3AA9 = {32120, 1, 0}, 0x3AAA = {32121, 2, 0}, 0x3AAB = {32123, 1, 0}, 0x3AAC = {32124, 2, 0}, 0x3AAD = {32126, 1, 0}, 0x3AAE = {32127, 2, 0}, 0x3AAF = {32129, 1, 0}, - 0x3AB0 = {32130, 2, 0}, 0x3AB1 = {32132, 1, 0}, 0x3AB2 = {32133, 2, 0}, 0x3AB3 = {32135, 1, 0}, 0x3AB4 = {32136, 2, 0}, 0x3AB5 = {32138, 1, 0}, 0x3AB6 = {32139, 2, 0}, 0x3AB7 = {32141, 1, 0}, 0x3AB8 = {32142, 2, 0}, 0x3AB9 = {32144, 1, 0}, 0x3ABA = {32145, 2, 0}, 0x3ABB = {32147, 1, 0}, 0x3ABC = {32148, 2, 0}, 0x3ABD = {32150, 1, 0}, 0x3ABE = {32151, 2, 0}, 0x3ABF = {32153, 1, 0}, - 0x3AC0 = {32154, 2, 0}, 0x3AC1 = {32156, 1, 0}, 0x3AC2 = {32157, 2, 0}, 0x3AC3 = {32159, 1, 0}, 0x3AC4 = {32160, 2, 0}, 0x3AC5 = {32162, 1, 0}, 0x3AC6 = {32163, 2, 0}, 0x3AC7 = {32165, 1, 0}, 0x3AC8 = {32166, 2, 0}, 0x3AC9 = {32168, 1, 0}, 0x3ACA = {32169, 2, 0}, 0x3ACB = {32171, 1, 0}, 0x3ACC = {32172, 2, 0}, 0x3ACD = {32174, 1, 0}, 0x3ACE = {32175, 2, 0}, 0x3ACF = {32177, 1, 0}, - 0x3AD0 = {32178, 2, 0}, 0x3AD1 = {32180, 1, 0}, 0x3AD2 = {32181, 2, 0}, 0x3AD3 = {32183, 1, 0}, 0x3AD4 = {32184, 2, 0}, 0x3AD5 = {32186, 1, 0}, 0x3AD6 = {32187, 2, 0}, 0x3AD7 = {32189, 1, 0}, 0x3AD8 = {32190, 2, 0}, 0x3AD9 = {32192, 1, 0}, 0x3ADA = {32193, 2, 0}, 0x3ADB = {32195, 1, 0}, 0x3ADC = {32196, 2, 0}, 0x3ADD = {32198, 1, 0}, 0x3ADE = {32199, 2, 0}, 0x3ADF = {32201, 1, 0}, - 0x3AE0 = {32202, 2, 0}, 0x3AE1 = {32204, 1, 0}, 0x3AE2 = {32205, 2, 0}, 0x3AE3 = {32207, 1, 0}, 0x3AE4 = {32208, 2, 0}, 0x3AE5 = {32210, 1, 0}, 0x3AE6 = {32211, 2, 0}, 0x3AE7 = {32213, 1, 0}, 0x3AE8 = {32214, 2, 0}, 0x3AE9 = {32216, 1, 0}, 0x3AEA = {32217, 2, 0}, 0x3AEB = {32219, 1, 0}, 0x3AEC = {32220, 2, 0}, 0x3AED = {32222, 1, 0}, 0x3AEE = {32223, 2, 0}, 0x3AEF = {32225, 1, 0}, - 0x3AF0 = {32226, 2, 0}, 0x3AF1 = {32228, 1, 0}, 0x3AF2 = {32229, 2, 0}, 0x3AF3 = {32231, 1, 0}, 0x3AF4 = {32232, 2, 0}, 0x3AF5 = {32234, 1, 0}, 0x3AF6 = {32235, 2, 0}, 0x3AF7 = {32237, 1, 0}, 0x3AF8 = {32238, 2, 0}, 0x3AF9 = {32240, 1, 0}, 0x3AFA = {32241, 2, 0}, 0x3AFB = {32243, 1, 0}, 0x3AFC = {32244, 2, 0}, 0x3AFD = {32246, 1, 0}, 0x3AFE = {32247, 2, 0}, 0x3AFF = {32249, 1, 0}, - 0x3B02 = {32250, 8, 0}, 0x3B03 = {32258, 2, 0}, 0x3B0B = {32260, 2, 0}, 0x3B0F = {32262, 2, 0}, 0x3B12 = {32264, 2, 0}, 0x3B14 = {32266, 2, 0}, 0x3B15 = {32268, 2, 0}, 0x3B16 = {32270, 2, 0}, 0x3B18 = {32272, 2, 0}, 0x3B19 = {32274, 2, 0}, 0x3B1A = {32276, 2, 0}, 0x3B1C = {32278, 2, 0}, 0x3B1D = {32280, 2, 0}, 0x3B1E = {32282, 2, 0}, 0x3B1F = {32284, 2, 0}, 0x3B22 = {32286, 8, 0}, - 0x3B23 = {32294, 2, 0}, 0x3B2F = {32296, 2, 0}, 0x3B39 = {32298, 2, 0}, 0x3B3C = {32300, 2, 0}, 0x3B3D = {32302, 2, 0}, 0x3B3E = {32304, 2, 0}, 0x3B3F = {32306, 2, 0}, 0x3B42 = {32308, 6, 0}, 0x3B43 = {32314, 2, 0}, 0x3B4B = {32316, 8, 0}, 0x3B4E = {32324, 2, 0}, 0x3B4F = {32326, 2, 0}, 0x3B59 = {32328, 2, 0}, 0x3B5C = {32330, 2, 0}, 0x3B5D = {32332, 2, 0}, 0x3B5E = {32334, 2, 0}, - 0x3B5F = {32336, 2, 0}, 0x3B62 = {32338, 6, 0}, 0x3B63 = {32344, 2, 0}, 0x3B6B = {32346, 8, 0}, 0x3B6F = {32354, 2, 0}, 0x3B79 = {32356, 2, 0}, 0x3B7C = {32358, 2, 0}, 0x3B7D = {32360, 2, 0}, 0x3B7E = {32362, 2, 0}, 0x3B7F = {32364, 2, 0}, 0x3B82 = {32366, 2, 0}, 0x3B8B = {32368, 2, 0}, 0x3B8F = {32370, 4, 0}, 0x3B99 = {32374, 2, 0}, 0x3B9C = {32376, 2, 0}, 0x3B9D = {32378, 2, 0}, - 0x3B9E = {32380, 2, 0}, 0x3B9F = {32382, 2, 0}, 0x3BA2 = {32384, 2, 0}, 0x3BAB = {32386, 2, 0}, 0x3BAF = {32388, 4, 0}, 0x3BB9 = {32392, 2, 0}, 0x3BBC = {32394, 2, 0}, 0x3BBD = {32396, 2, 0}, 0x3BBE = {32398, 2, 0}, 0x3BBF = {32400, 2, 0}, 0x3BC2 = {32402, 1, 0}, 0x3BCB = {32403, 8, 0}, 0x3BCE = {32411, 2, 0}, 0x3BCF = {32413, 2, 0}, 0x3BD9 = {32415, 2, 0}, 0x3BDC = {32417, 2, 0}, - 0x3BDD = {32419, 2, 0}, 0x3BDE = {32421, 2, 0}, 0x3BDF = {32423, 2, 0}, 0x3BE2 = {32425, 1, 0}, 0x3BE3 = {32426, 2, 0}, 0x3BEB = {32428, 8, 0}, 0x3BEF = {32436, 2, 0}, 0x3BF9 = {32438, 2, 0}, 0x3BFC = {32440, 2, 0}, 0x3BFD = {32442, 2, 0}, 0x3BFE = {32444, 2, 0}, 0x3BFF = {32446, 2, 0}, 0x3C00 = {32448, 6, 0}, 0x3C01 = {32454, 5, 0}, 0x3C02 = {32459, 5, 0}, 0x3C03 = {32464, 5, 0}, - 0x3C04 = {32469, 5, 0}, 0x3C05 = {32474, 5, 0}, 0x3C06 = {32479, 5, 0}, 0x3C07 = {32484, 5, 0}, 0x3C08 = {32489, 3, 0}, 0x3C09 = {32492, 3, 0}, 0x3C0A = {32495, 3, 0}, 0x3C0B = {32498, 3, 0}, 0x3C0C = {32501, 4, 0}, 0x3C0D = {32505, 4, 0}, 0x3C0E = {32509, 4, 0}, 0x3C0F = {32513, 4, 0}, 0x3C10 = {32517, 3, 0}, 0x3C11 = {32520, 3, 0}, 0x3C12 = {32523, 4, 0}, 0x3C13 = {32527, 4, 0}, - 0x3C14 = {32531, 3, 0}, 0x3C15 = {32534, 3, 0}, 0x3C16 = {32537, 4, 0}, 0x3C17 = {32541, 4, 0}, 0x3C18 = {32545, 2, 0}, 0x3C19 = {32547, 2, 0}, 0x3C1A = {32549, 2, 0}, 0x3C1B = {32551, 2, 0}, 0x3C1C = {32553, 2, 0}, 0x3C1D = {32555, 2, 0}, 0x3C1E = {32557, 2, 0}, 0x3C1F = {32559, 2, 0}, 0x3C20 = {32561, 5, 0}, 0x3C21 = {32566, 5, 0}, 0x3C22 = {32571, 5, 0}, 0x3C23 = {32576, 5, 0}, - 0x3C24 = {32581, 5, 0}, 0x3C25 = {32586, 5, 0}, 0x3C26 = {32591, 5, 0}, 0x3C27 = {32596, 5, 0}, 0x3C28 = {32601, 3, 0}, 0x3C29 = {32604, 3, 0}, 0x3C2A = {32607, 3, 0}, 0x3C2B = {32610, 3, 0}, 0x3C2C = {32613, 4, 0}, 0x3C2D = {32617, 4, 0}, 0x3C2E = {32621, 4, 0}, 0x3C2F = {32625, 4, 0}, 0x3C30 = {32629, 3, 0}, 0x3C31 = {32632, 3, 0}, 0x3C32 = {32635, 4, 0}, 0x3C33 = {32639, 4, 0}, - 0x3C34 = {32643, 3, 0}, 0x3C35 = {32646, 3, 0}, 0x3C36 = {32649, 1, 0}, 0x3C37 = {32650, 1, 0}, 0x3C38 = {32651, 2, 0}, 0x3C39 = {32653, 2, 0}, 0x3C3A = {32655, 2, 0}, 0x3C3B = {32657, 2, 0}, 0x3C3C = {32659, 2, 0}, 0x3C3D = {32661, 2, 0}, 0x3C3E = {32663, 2, 0}, 0x3C3F = {32665, 2, 0}, 0x3C40 = {32667, 5, 0}, 0x3C41 = {32672, 5, 0}, 0x3C42 = {32677, 5, 0}, 0x3C43 = {32682, 5, 0}, - 0x3C44 = {32687, 5, 0}, 0x3C45 = {32692, 5, 0}, 0x3C46 = {32697, 5, 0}, 0x3C47 = {32702, 5, 0}, 0x3C48 = {32707, 4, 0}, 0x3C49 = {32711, 4, 0}, 0x3C4A = {32715, 4, 0}, 0x3C4B = {32719, 4, 0}, 0x3C4C = {32723, 4, 0}, 0x3C4D = {32727, 4, 0}, 0x3C4E = {32731, 4, 0}, 0x3C4F = {32735, 4, 0}, 0x3C50 = {32739, 4, 0}, 0x3C51 = {32743, 3, 0}, 0x3C52 = {32746, 3, 0}, 0x3C53 = {32749, 3, 0}, - 0x3C54 = {32752, 4, 0}, 0x3C55 = {32756, 1, 0}, 0x3C56 = {32757, 2, 0}, 0x3C57 = {32759, 2, 0}, 0x3C58 = {32761, 2, 0}, 0x3C59 = {32763, 2, 0}, 0x3C5A = {32765, 2, 0}, 0x3C5B = {32767, 2, 0}, 0x3C5C = {32769, 2, 0}, 0x3C5D = {32771, 2, 0}, 0x3C5E = {32773, 2, 0}, 0x3C5F = {32775, 2, 0}, 0x3C60 = {32777, 5, 0}, 0x3C61 = {32782, 4, 0}, 0x3C62 = {32786, 4, 0}, 0x3C63 = {32790, 4, 0}, - 0x3C64 = {32794, 5, 0}, 0x3C65 = {32799, 5, 0}, 0x3C66 = {32804, 5, 0}, 0x3C67 = {32809, 5, 0}, 0x3C68 = {32814, 5, 0}, 0x3C69 = {32819, 4, 0}, 0x3C6A = {32823, 4, 0}, 0x3C6B = {32827, 4, 0}, 0x3C6C = {32831, 1, 0}, 0x3C6D = {32832, 1, 0}, 0x3C6E = {32833, 1, 0}, 0x3C6F = {32834, 1, 0}, 0x3C70 = {32835, 4, 0}, 0x3C71 = {32839, 3, 0}, 0x3C72 = {32842, 3, 0}, 0x3C73 = {32845, 3, 0}, - 0x3C74 = {32848, 2, 0}, 0x3C75 = {32850, 1, 0}, 0x3C76 = {32851, 1, 0}, 0x3C77 = {32852, 1, 0}, 0x3C78 = {32853, 2, 0}, 0x3C79 = {32855, 2, 0}, 0x3C7A = {32857, 2, 0}, 0x3C7B = {32859, 2, 0}, 0x3C7C = {32861, 2, 0}, 0x3C7D = {32863, 2, 0}, 0x3C7E = {32865, 2, 0}, 0x3C7F = {32867, 2, 0}, 0x3C80 = {32869, 5, 0}, 0x3C81 = {32874, 5, 0}, 0x3C82 = {32879, 5, 0}, 0x3C83 = {32884, 5, 0}, - 0x3C84 = {32889, 5, 0}, 0x3C85 = {32894, 5, 0}, 0x3C86 = {32899, 5, 0}, 0x3C87 = {32904, 5, 0}, 0x3C88 = {32909, 2, 0}, 0x3C89 = {32911, 2, 0}, 0x3C8A = {32913, 2, 0}, 0x3C8B = {32915, 2, 0}, 0x3C8C = {32917, 4, 0}, 0x3C8D = {32921, 4, 0}, 0x3C8E = {32925, 3, 0}, 0x3C8F = {32928, 3, 0}, 0x3C90 = {32931, 5, 0}, 0x3C91 = {32936, 5, 0}, 0x3C92 = {32941, 5, 0}, 0x3C93 = {32946, 5, 0}, - 0x3C94 = {32951, 4, 0}, 0x3C95 = {32955, 4, 0}, 0x3C96 = {32959, 5, 0}, 0x3C97 = {32964, 4, 0}, 0x3C98 = {32968, 2, 0}, 0x3C99 = {32970, 2, 0}, 0x3C9A = {32972, 2, 0}, 0x3C9B = {32974, 2, 0}, 0x3C9C = {32976, 2, 0}, 0x3C9D = {32978, 2, 0}, 0x3C9E = {32980, 2, 0}, 0x3C9F = {32982, 2, 0}, 0x3CA0 = {32984, 5, 0}, 0x3CA1 = {32989, 5, 0}, 0x3CA2 = {32994, 5, 0}, 0x3CA3 = {32999, 5, 0}, - 0x3CA4 = {33004, 5, 0}, 0x3CA5 = {33009, 5, 0}, 0x3CA6 = {33014, 5, 0}, 0x3CA7 = {33019, 5, 0}, 0x3CA8 = {33024, 2, 0}, 0x3CA9 = {33026, 2, 0}, 0x3CAA = {33028, 2, 0}, 0x3CAB = {33030, 2, 0}, 0x3CAC = {33032, 4, 0}, 0x3CAD = {33036, 4, 0}, 0x3CAE = {33040, 3, 0}, 0x3CAF = {33043, 3, 0}, 0x3CB0 = {33046, 5, 0}, 0x3CB1 = {33051, 5, 0}, 0x3CB2 = {33056, 5, 0}, 0x3CB3 = {33061, 5, 0}, - 0x3CB4 = {33066, 4, 0}, 0x3CB5 = {33070, 4, 0}, 0x3CB6 = {33074, 18, 0}, 0x3CB7 = {33092, 1, 0}, 0x3CB8 = {33093, 2, 0}, 0x3CB9 = {33095, 2, 0}, 0x3CBA = {33097, 2, 0}, 0x3CBB = {33099, 2, 0}, 0x3CBC = {33101, 2, 0}, 0x3CBD = {33103, 2, 0}, 0x3CBE = {33105, 2, 0}, 0x3CBF = {33107, 2, 0}, 0x3CC0 = {33109, 5, 0}, 0x3CC1 = {33114, 5, 0}, 0x3CC2 = {33119, 5, 0}, 0x3CC3 = {33124, 5, 0}, - 0x3CC4 = {33129, 5, 0}, 0x3CC5 = {33134, 5, 0}, 0x3CC6 = {33139, 5, 0}, 0x3CC7 = {33144, 5, 0}, 0x3CC8 = {33149, 3, 0}, 0x3CC9 = {33152, 3, 0}, 0x3CCA = {33155, 3, 0}, 0x3CCB = {33158, 3, 0}, 0x3CCC = {33161, 3, 0}, 0x3CCD = {33164, 3, 0}, 0x3CCE = {33167, 3, 0}, 0x3CCF = {33170, 3, 0}, 0x3CD0 = {33173, 4, 0}, 0x3CD1 = {33177, 4, 0}, 0x3CD2 = {33181, 5, 0}, 0x3CD3 = {33186, 5, 0}, - 0x3CD4 = {33191, 5, 0}, 0x3CD5 = {33196, 1, 0}, 0x3CD6 = {33197, 3, 0}, 0x3CD7 = {33200, 3, 0}, 0x3CD8 = {33203, 2, 0}, 0x3CD9 = {33205, 2, 0}, 0x3CDA = {33207, 2, 0}, 0x3CDB = {33209, 2, 0}, 0x3CDC = {33211, 2, 0}, 0x3CDD = {33213, 2, 0}, 0x3CDE = {33215, 2, 0}, 0x3CDF = {33217, 2, 0}, 0x3CE0 = {33219, 4, 0}, 0x3CE1 = {33223, 3, 0}, 0x3CE2 = {33226, 3, 0}, 0x3CE3 = {33229, 3, 0}, - 0x3CE4 = {33232, 5, 0}, 0x3CE5 = {33237, 5, 0}, 0x3CE6 = {33242, 5, 0}, 0x3CE7 = {33247, 5, 0}, 0x3CE8 = {33252, 3, 0}, 0x3CE9 = {33255, 2, 0}, 0x3CEA = {33257, 2, 0}, 0x3CEB = {33259, 2, 0}, 0x3CEC = {33261, 1, 0}, 0x3CED = {33262, 1, 0}, 0x3CEE = {33263, 1, 0}, 0x3CEF = {33264, 1, 0}, 0x3CF0 = {33265, 4, 0}, 0x3CF1 = {33269, 4, 0}, 0x3CF2 = {33273, 5, 0}, 0x3CF3 = {33278, 5, 0}, - 0x3CF4 = {33283, 3, 0}, 0x3CF5 = {33286, 1, 0}, 0x3CF6 = {33287, 1, 0}, 0x3CF7 = {33288, 1, 0}, 0x3CF8 = {33289, 2, 0}, 0x3CF9 = {33291, 2, 0}, 0x3CFA = {33293, 2, 0}, 0x3CFB = {33295, 2, 0}, 0x3CFC = {33297, 2, 0}, 0x3CFD = {33299, 2, 0}, 0x3CFE = {33301, 2, 0}, 0x3CFF = {33303, 2, 0}, 0x3D00 = {33305, 5, 0}, 0x3D01 = {33310, 4, 0}, 0x3D02 = {33314, 4, 0}, 0x3D03 = {33318, 4, 0}, - 0x3D04 = {33322, 4, 0}, 0x3D05 = {33326, 4, 0}, 0x3D06 = {33330, 4, 0}, 0x3D07 = {33334, 4, 0}, 0x3D08 = {33338, 4, 0}, 0x3D09 = {33342, 4, 0}, 0x3D0A = {33346, 4, 0}, 0x3D0B = {33350, 4, 0}, 0x3D0C = {33354, 4, 0}, 0x3D0D = {33358, 4, 0}, 0x3D0E = {33362, 4, 0}, 0x3D0F = {33366, 4, 0}, 0x3D10 = {33370, 4, 0}, 0x3D11 = {33374, 4, 0}, 0x3D12 = {33378, 4, 0}, 0x3D13 = {33382, 4, 0}, - 0x3D14 = {33386, 4, 0}, 0x3D15 = {33390, 4, 0}, 0x3D16 = {33394, 4, 0}, 0x3D17 = {33398, 4, 0}, 0x3D18 = {33402, 4, 0}, 0x3D19 = {33406, 4, 0}, 0x3D1A = {33410, 4, 0}, 0x3D1B = {33414, 4, 0}, 0x3D1C = {33418, 4, 0}, 0x3D1D = {33422, 4, 0}, 0x3D1E = {33426, 4, 0}, 0x3D1F = {33430, 4, 0}, 0x3D20 = {33434, 4, 0}, 0x3D21 = {33438, 4, 0}, 0x3D22 = {33442, 4, 0}, 0x3D23 = {33446, 4, 0}, - 0x3D24 = {33450, 4, 0}, 0x3D25 = {33454, 4, 0}, 0x3D26 = {33458, 4, 0}, 0x3D27 = {33462, 4, 0}, 0x3D28 = {33466, 4, 0}, 0x3D29 = {33470, 4, 0}, 0x3D2A = {33474, 4, 0}, 0x3D2B = {33478, 4, 0}, 0x3D2C = {33482, 4, 0}, 0x3D2D = {33486, 4, 0}, 0x3D2E = {33490, 4, 0}, 0x3D2F = {33494, 4, 0}, 0x3D30 = {33498, 4, 0}, 0x3D31 = {33502, 4, 0}, 0x3D32 = {33506, 4, 0}, 0x3D33 = {33510, 4, 0}, - 0x3D34 = {33514, 4, 0}, 0x3D35 = {33518, 4, 0}, 0x3D36 = {33522, 4, 0}, 0x3D37 = {33526, 4, 0}, 0x3D38 = {33530, 4, 0}, 0x3D39 = {33534, 4, 0}, 0x3D3A = {33538, 4, 0}, 0x3D3B = {33542, 4, 0}, 0x3D3C = {33546, 4, 0}, 0x3D3D = {33550, 4, 0}, 0x3D3E = {33554, 4, 0}, 0x3D3F = {33558, 4, 0}, 0x3D40 = {33562, 4, 0}, 0x3D41 = {33566, 4, 0}, 0x3D42 = {33570, 4, 0}, 0x3D43 = {33574, 4, 0}, - 0x3D44 = {33578, 4, 0}, 0x3D45 = {33582, 4, 0}, 0x3D46 = {33586, 4, 0}, 0x3D47 = {33590, 4, 0}, 0x3D48 = {33594, 4, 0}, 0x3D49 = {33598, 4, 0}, 0x3D4A = {33602, 4, 0}, 0x3D4B = {33606, 4, 0}, 0x3D4C = {33610, 4, 0}, 0x3D4D = {33614, 4, 0}, 0x3D4E = {33618, 4, 0}, 0x3D4F = {33622, 4, 0}, 0x3D50 = {33626, 4, 0}, 0x3D51 = {33630, 4, 0}, 0x3D52 = {33634, 4, 0}, 0x3D53 = {33638, 4, 0}, - 0x3D54 = {33642, 4, 0}, 0x3D55 = {33646, 4, 0}, 0x3D56 = {33650, 4, 0}, 0x3D57 = {33654, 4, 0}, 0x3D58 = {33658, 4, 0}, 0x3D59 = {33662, 4, 0}, 0x3D5A = {33666, 4, 0}, 0x3D5B = {33670, 4, 0}, 0x3D5C = {33674, 4, 0}, 0x3D5D = {33678, 4, 0}, 0x3D5E = {33682, 4, 0}, 0x3D5F = {33686, 4, 0}, 0x3D60 = {33690, 4, 0}, 0x3D61 = {33694, 4, 0}, 0x3D62 = {33698, 4, 0}, 0x3D63 = {33702, 4, 0}, - 0x3D64 = {33706, 4, 0}, 0x3D65 = {33710, 4, 0}, 0x3D66 = {33714, 4, 0}, 0x3D67 = {33718, 4, 0}, 0x3D68 = {33722, 4, 0}, 0x3D69 = {33726, 4, 0}, 0x3D6A = {33730, 4, 0}, 0x3D6B = {33734, 4, 0}, 0x3D6C = {33738, 4, 0}, 0x3D6D = {33742, 4, 0}, 0x3D6E = {33746, 4, 0}, 0x3D6F = {33750, 4, 0}, 0x3D70 = {33754, 4, 0}, 0x3D71 = {33758, 4, 0}, 0x3D72 = {33762, 4, 0}, 0x3D73 = {33766, 4, 0}, - 0x3D74 = {33770, 4, 0}, 0x3D75 = {33774, 4, 0}, 0x3D76 = {33778, 4, 0}, 0x3D77 = {33782, 4, 0}, 0x3D78 = {33786, 4, 0}, 0x3D79 = {33790, 4, 0}, 0x3D7A = {33794, 4, 0}, 0x3D7B = {33798, 4, 0}, 0x3D7C = {33802, 4, 0}, 0x3D7D = {33806, 4, 0}, 0x3D7E = {33810, 4, 0}, 0x3D7F = {33814, 4, 0}, 0x3D80 = {33818, 4, 0}, 0x3D81 = {33822, 4, 0}, 0x3D82 = {33826, 4, 0}, 0x3D83 = {33830, 4, 0}, - 0x3D84 = {33834, 4, 0}, 0x3D85 = {33838, 4, 0}, 0x3D86 = {33842, 4, 0}, 0x3D87 = {33846, 4, 0}, 0x3D88 = {33850, 4, 0}, 0x3D89 = {33854, 4, 0}, 0x3D8A = {33858, 4, 0}, 0x3D8B = {33862, 4, 0}, 0x3D8C = {33866, 4, 0}, 0x3D8D = {33870, 4, 0}, 0x3D8E = {33874, 4, 0}, 0x3D8F = {33878, 4, 0}, 0x3D90 = {33882, 4, 0}, 0x3D91 = {33886, 4, 0}, 0x3D92 = {33890, 4, 0}, 0x3D93 = {33894, 4, 0}, - 0x3D94 = {33898, 4, 0}, 0x3D95 = {33902, 4, 0}, 0x3D96 = {33906, 4, 0}, 0x3D97 = {33910, 4, 0}, 0x3D98 = {33914, 4, 0}, 0x3D99 = {33918, 4, 0}, 0x3D9A = {33922, 4, 0}, 0x3D9B = {33926, 4, 0}, 0x3D9C = {33930, 4, 0}, 0x3D9D = {33934, 4, 0}, 0x3D9E = {33938, 4, 0}, 0x3D9F = {33942, 4, 0}, 0x3DA0 = {33946, 4, 0}, 0x3DA1 = {33950, 4, 0}, 0x3DA2 = {33954, 4, 0}, 0x3DA3 = {33958, 4, 0}, - 0x3DA4 = {33962, 4, 0}, 0x3DA5 = {33966, 4, 0}, 0x3DA6 = {33970, 4, 0}, 0x3DA7 = {33974, 4, 0}, 0x3DA8 = {33978, 4, 0}, 0x3DA9 = {33982, 4, 0}, 0x3DAA = {33986, 4, 0}, 0x3DAB = {33990, 4, 0}, 0x3DAC = {33994, 4, 0}, 0x3DAD = {33998, 4, 0}, 0x3DAE = {34002, 4, 0}, 0x3DAF = {34006, 4, 0}, 0x3DB0 = {34010, 4, 0}, 0x3DB1 = {34014, 4, 0}, 0x3DB2 = {34018, 4, 0}, 0x3DB3 = {34022, 4, 0}, - 0x3DB4 = {34026, 4, 0}, 0x3DB5 = {34030, 4, 0}, 0x3DB6 = {34034, 4, 0}, 0x3DB7 = {34038, 4, 0}, 0x3DB8 = {34042, 4, 0}, 0x3DB9 = {34046, 4, 0}, 0x3DBA = {34050, 4, 0}, 0x3DBB = {34054, 4, 0}, 0x3DBC = {34058, 4, 0}, 0x3DBD = {34062, 4, 0}, 0x3DBE = {34066, 4, 0}, 0x3DBF = {34070, 4, 0}, 0x3DC0 = {34074, 4, 0}, 0x3DC1 = {34078, 4, 0}, 0x3DC2 = {34082, 4, 0}, 0x3DC3 = {34086, 4, 0}, - 0x3DC4 = {34090, 4, 0}, 0x3DC5 = {34094, 4, 0}, 0x3DC6 = {34098, 4, 0}, 0x3DC7 = {34102, 4, 0}, 0x3DC8 = {34106, 4, 0}, 0x3DC9 = {34110, 4, 0}, 0x3DCA = {34114, 4, 0}, 0x3DCB = {34118, 4, 0}, 0x3DCC = {34122, 4, 0}, 0x3DCD = {34126, 4, 0}, 0x3DCE = {34130, 4, 0}, 0x3DCF = {34134, 4, 0}, 0x3DD0 = {34138, 4, 0}, 0x3DD1 = {34142, 4, 0}, 0x3DD2 = {34146, 4, 0}, 0x3DD3 = {34150, 4, 0}, - 0x3DD4 = {34154, 4, 0}, 0x3DD5 = {34158, 4, 0}, 0x3DD6 = {34162, 4, 0}, 0x3DD7 = {34166, 4, 0}, 0x3DD8 = {34170, 4, 0}, 0x3DD9 = {34174, 4, 0}, 0x3DDA = {34178, 4, 0}, 0x3DDB = {34182, 4, 0}, 0x3DDC = {34186, 4, 0}, 0x3DDD = {34190, 4, 0}, 0x3DDE = {34194, 4, 0}, 0x3DDF = {34198, 4, 0}, 0x3DE0 = {34202, 4, 0}, 0x3DE1 = {34206, 4, 0}, 0x3DE2 = {34210, 4, 0}, 0x3DE3 = {34214, 4, 0}, - 0x3DE4 = {34218, 4, 0}, 0x3DE5 = {34222, 4, 0}, 0x3DE6 = {34226, 4, 0}, 0x3DE7 = {34230, 4, 0}, 0x3DE8 = {34234, 4, 0}, 0x3DE9 = {34238, 4, 0}, 0x3DEA = {34242, 4, 0}, 0x3DEB = {34246, 4, 0}, 0x3DEC = {34250, 4, 0}, 0x3DED = {34254, 4, 0}, 0x3DEE = {34258, 4, 0}, 0x3DEF = {34262, 4, 0}, 0x3DF0 = {34266, 4, 0}, 0x3DF1 = {34270, 4, 0}, 0x3DF2 = {34274, 4, 0}, 0x3DF3 = {34278, 4, 0}, - 0x3DF4 = {34282, 4, 0}, 0x3DF5 = {34286, 4, 0}, 0x3DF6 = {34290, 4, 0}, 0x3DF7 = {34294, 4, 0}, 0x3DF8 = {34298, 4, 0}, 0x3DF9 = {34302, 4, 0}, 0x3DFA = {34306, 4, 0}, 0x3DFB = {34310, 4, 0}, 0x3DFC = {34314, 4, 0}, 0x3DFD = {34318, 4, 0}, 0x3DFE = {34322, 4, 0}, 0x3DFF = {34326, 4, 0}, 0x3E00 = {34330, 2, 0}, 0x3E01 = {34332, 1, 0}, 0x3E02 = {34333, 2, 0}, 0x3E03 = {34335, 1, 0}, - 0x3E04 = {34336, 2, 0}, 0x3E05 = {34338, 1, 0}, 0x3E06 = {34339, 2, 0}, 0x3E07 = {34341, 1, 0}, 0x3E08 = {34342, 2, 0}, 0x3E09 = {34344, 1, 0}, 0x3E0A = {34345, 2, 0}, 0x3E0B = {34347, 1, 0}, 0x3E0C = {34348, 2, 0}, 0x3E0D = {34350, 1, 0}, 0x3E0E = {34351, 2, 0}, 0x3E0F = {34353, 1, 0}, 0x3E10 = {34354, 2, 0}, 0x3E11 = {34356, 1, 0}, 0x3E12 = {34357, 2, 0}, 0x3E13 = {34359, 1, 0}, - 0x3E14 = {34360, 2, 0}, 0x3E15 = {34362, 1, 0}, 0x3E16 = {34363, 2, 0}, 0x3E17 = {34365, 1, 0}, 0x3E18 = {34366, 2, 0}, 0x3E19 = {34368, 1, 0}, 0x3E1A = {34369, 2, 0}, 0x3E1B = {34371, 1, 0}, 0x3E1C = {34372, 2, 0}, 0x3E1D = {34374, 1, 0}, 0x3E1E = {34375, 2, 0}, 0x3E1F = {34377, 1, 0}, 0x3E20 = {34378, 2, 0}, 0x3E21 = {34380, 1, 0}, 0x3E22 = {34381, 2, 0}, 0x3E23 = {34383, 1, 0}, - 0x3E24 = {34384, 2, 0}, 0x3E25 = {34386, 1, 0}, 0x3E26 = {34387, 2, 0}, 0x3E27 = {34389, 1, 0}, 0x3E28 = {34390, 2, 0}, 0x3E29 = {34392, 1, 0}, 0x3E2A = {34393, 2, 0}, 0x3E2B = {34395, 1, 0}, 0x3E2C = {34396, 2, 0}, 0x3E2D = {34398, 1, 0}, 0x3E2E = {34399, 2, 0}, 0x3E2F = {34401, 1, 0}, 0x3E30 = {34402, 2, 0}, 0x3E31 = {34404, 1, 0}, 0x3E32 = {34405, 2, 0}, 0x3E33 = {34407, 1, 0}, - 0x3E34 = {34408, 2, 0}, 0x3E35 = {34410, 1, 0}, 0x3E36 = {34411, 2, 0}, 0x3E37 = {34413, 1, 0}, 0x3E38 = {34414, 2, 0}, 0x3E39 = {34416, 1, 0}, 0x3E3A = {34417, 2, 0}, 0x3E3B = {34419, 1, 0}, 0x3E3C = {34420, 2, 0}, 0x3E3D = {34422, 1, 0}, 0x3E3E = {34423, 2, 0}, 0x3E3F = {34425, 1, 0}, 0x3E40 = {34426, 2, 0}, 0x3E41 = {34428, 1, 0}, 0x3E42 = {34429, 2, 0}, 0x3E43 = {34431, 1, 0}, - 0x3E44 = {34432, 2, 0}, 0x3E45 = {34434, 1, 0}, 0x3E46 = {34435, 2, 0}, 0x3E47 = {34437, 1, 0}, 0x3E48 = {34438, 2, 0}, 0x3E49 = {34440, 1, 0}, 0x3E4A = {34441, 2, 0}, 0x3E4B = {34443, 1, 0}, 0x3E4C = {34444, 2, 0}, 0x3E4D = {34446, 1, 0}, 0x3E4E = {34447, 2, 0}, 0x3E4F = {34449, 1, 0}, 0x3E50 = {34450, 2, 0}, 0x3E51 = {34452, 1, 0}, 0x3E52 = {34453, 2, 0}, 0x3E53 = {34455, 1, 0}, - 0x3E54 = {34456, 2, 0}, 0x3E55 = {34458, 1, 0}, 0x3E56 = {34459, 2, 0}, 0x3E57 = {34461, 1, 0}, 0x3E58 = {34462, 2, 0}, 0x3E59 = {34464, 1, 0}, 0x3E5A = {34465, 2, 0}, 0x3E5B = {34467, 1, 0}, 0x3E5C = {34468, 2, 0}, 0x3E5D = {34470, 1, 0}, 0x3E5E = {34471, 2, 0}, 0x3E5F = {34473, 1, 0}, 0x3E60 = {34474, 2, 0}, 0x3E61 = {34476, 1, 0}, 0x3E62 = {34477, 2, 0}, 0x3E63 = {34479, 1, 0}, - 0x3E64 = {34480, 2, 0}, 0x3E65 = {34482, 1, 0}, 0x3E66 = {34483, 2, 0}, 0x3E67 = {34485, 1, 0}, 0x3E68 = {34486, 2, 0}, 0x3E69 = {34488, 1, 0}, 0x3E6A = {34489, 2, 0}, 0x3E6B = {34491, 1, 0}, 0x3E6C = {34492, 2, 0}, 0x3E6D = {34494, 1, 0}, 0x3E6E = {34495, 2, 0}, 0x3E6F = {34497, 1, 0}, 0x3E70 = {34498, 2, 0}, 0x3E71 = {34500, 1, 0}, 0x3E72 = {34501, 2, 0}, 0x3E73 = {34503, 1, 0}, - 0x3E74 = {34504, 2, 0}, 0x3E75 = {34506, 1, 0}, 0x3E76 = {34507, 2, 0}, 0x3E77 = {34509, 1, 0}, 0x3E78 = {34510, 2, 0}, 0x3E79 = {34512, 1, 0}, 0x3E7A = {34513, 2, 0}, 0x3E7B = {34515, 1, 0}, 0x3E7C = {34516, 2, 0}, 0x3E7D = {34518, 1, 0}, 0x3E7E = {34519, 2, 0}, 0x3E7F = {34521, 1, 0}, 0x3E80 = {34522, 2, 0}, 0x3E81 = {34524, 1, 0}, 0x3E82 = {34525, 2, 0}, 0x3E83 = {34527, 1, 0}, - 0x3E84 = {34528, 2, 0}, 0x3E85 = {34530, 1, 0}, 0x3E86 = {34531, 2, 0}, 0x3E87 = {34533, 1, 0}, 0x3E88 = {34534, 2, 0}, 0x3E89 = {34536, 1, 0}, 0x3E8A = {34537, 2, 0}, 0x3E8B = {34539, 1, 0}, 0x3E8C = {34540, 2, 0}, 0x3E8D = {34542, 1, 0}, 0x3E8E = {34543, 2, 0}, 0x3E8F = {34545, 1, 0}, 0x3E90 = {34546, 2, 0}, 0x3E91 = {34548, 1, 0}, 0x3E92 = {34549, 2, 0}, 0x3E93 = {34551, 1, 0}, - 0x3E94 = {34552, 2, 0}, 0x3E95 = {34554, 1, 0}, 0x3E96 = {34555, 2, 0}, 0x3E97 = {34557, 1, 0}, 0x3E98 = {34558, 2, 0}, 0x3E99 = {34560, 1, 0}, 0x3E9A = {34561, 2, 0}, 0x3E9B = {34563, 1, 0}, 0x3E9C = {34564, 2, 0}, 0x3E9D = {34566, 1, 0}, 0x3E9E = {34567, 2, 0}, 0x3E9F = {34569, 1, 0}, 0x3EA0 = {34570, 2, 0}, 0x3EA1 = {34572, 1, 0}, 0x3EA2 = {34573, 2, 0}, 0x3EA3 = {34575, 1, 0}, - 0x3EA4 = {34576, 2, 0}, 0x3EA5 = {34578, 1, 0}, 0x3EA6 = {34579, 2, 0}, 0x3EA7 = {34581, 1, 0}, 0x3EA8 = {34582, 2, 0}, 0x3EA9 = {34584, 1, 0}, 0x3EAA = {34585, 2, 0}, 0x3EAB = {34587, 1, 0}, 0x3EAC = {34588, 2, 0}, 0x3EAD = {34590, 1, 0}, 0x3EAE = {34591, 2, 0}, 0x3EAF = {34593, 1, 0}, 0x3EB0 = {34594, 2, 0}, 0x3EB1 = {34596, 1, 0}, 0x3EB2 = {34597, 2, 0}, 0x3EB3 = {34599, 1, 0}, - 0x3EB4 = {34600, 2, 0}, 0x3EB5 = {34602, 1, 0}, 0x3EB6 = {34603, 2, 0}, 0x3EB7 = {34605, 1, 0}, 0x3EB8 = {34606, 2, 0}, 0x3EB9 = {34608, 1, 0}, 0x3EBA = {34609, 2, 0}, 0x3EBB = {34611, 1, 0}, 0x3EBC = {34612, 2, 0}, 0x3EBD = {34614, 1, 0}, 0x3EBE = {34615, 2, 0}, 0x3EBF = {34617, 1, 0}, 0x3EC0 = {34618, 2, 0}, 0x3EC1 = {34620, 1, 0}, 0x3EC2 = {34621, 2, 0}, 0x3EC3 = {34623, 1, 0}, - 0x3EC4 = {34624, 2, 0}, 0x3EC5 = {34626, 1, 0}, 0x3EC6 = {34627, 2, 0}, 0x3EC7 = {34629, 1, 0}, 0x3EC8 = {34630, 2, 0}, 0x3EC9 = {34632, 1, 0}, 0x3ECA = {34633, 2, 0}, 0x3ECB = {34635, 1, 0}, 0x3ECC = {34636, 2, 0}, 0x3ECD = {34638, 1, 0}, 0x3ECE = {34639, 2, 0}, 0x3ECF = {34641, 1, 0}, 0x3ED0 = {34642, 2, 0}, 0x3ED1 = {34644, 1, 0}, 0x3ED2 = {34645, 2, 0}, 0x3ED3 = {34647, 1, 0}, - 0x3ED4 = {34648, 2, 0}, 0x3ED5 = {34650, 1, 0}, 0x3ED6 = {34651, 2, 0}, 0x3ED7 = {34653, 1, 0}, 0x3ED8 = {34654, 2, 0}, 0x3ED9 = {34656, 1, 0}, 0x3EDA = {34657, 2, 0}, 0x3EDB = {34659, 1, 0}, 0x3EDC = {34660, 2, 0}, 0x3EDD = {34662, 1, 0}, 0x3EDE = {34663, 2, 0}, 0x3EDF = {34665, 1, 0}, 0x3EE0 = {34666, 2, 0}, 0x3EE1 = {34668, 1, 0}, 0x3EE2 = {34669, 2, 0}, 0x3EE3 = {34671, 1, 0}, - 0x3EE4 = {34672, 2, 0}, 0x3EE5 = {34674, 1, 0}, 0x3EE6 = {34675, 2, 0}, 0x3EE7 = {34677, 1, 0}, 0x3EE8 = {34678, 2, 0}, 0x3EE9 = {34680, 1, 0}, 0x3EEA = {34681, 2, 0}, 0x3EEB = {34683, 1, 0}, 0x3EEC = {34684, 2, 0}, 0x3EED = {34686, 1, 0}, 0x3EEE = {34687, 2, 0}, 0x3EEF = {34689, 1, 0}, 0x3EF0 = {34690, 2, 0}, 0x3EF1 = {34692, 1, 0}, 0x3EF2 = {34693, 2, 0}, 0x3EF3 = {34695, 1, 0}, - 0x3EF4 = {34696, 2, 0}, 0x3EF5 = {34698, 1, 0}, 0x3EF6 = {34699, 2, 0}, 0x3EF7 = {34701, 1, 0}, 0x3EF8 = {34702, 2, 0}, 0x3EF9 = {34704, 1, 0}, 0x3EFA = {34705, 2, 0}, 0x3EFB = {34707, 1, 0}, 0x3EFC = {34708, 2, 0}, 0x3EFD = {34710, 1, 0}, 0x3EFE = {34711, 2, 0}, 0x3EFF = {34713, 1, 0}, 0x3F00 = {34714, 26, 0}, 0x3F02 = {34740, 4, 0}, 0x3F04 = {34744, 4, 0}, 0x3F05 = {34748, 2, 0}, - 0x3F08 = {34750, 4, 0}, 0x3F0C = {34754, 2, 0}, 0x3F0E = {34756, 2, 0}, 0x3F0F = {34758, 2, 0}, 0x3F12 = {34760, 2, 0}, 0x3F14 = {34762, 2, 0}, 0x3F15 = {34764, 2, 0}, 0x3F16 = {34766, 2, 0}, 0x3F17 = {34768, 2, 0}, 0x3F18 = {34770, 2, 0}, 0x3F19 = {34772, 2, 0}, 0x3F1A = {34774, 2, 0}, 0x3F1C = {34776, 2, 0}, 0x3F1D = {34778, 2, 0}, 0x3F1E = {34780, 2, 0}, 0x3F1F = {34782, 2, 0}, - 0x3F20 = {34784, 1, 0}, 0x3F22 = {34785, 6, 0}, 0x3F24 = {34791, 11, 0}, 0x3F25 = {34802, 1, 0}, 0x3F26 = {34803, 2, 0}, 0x3F28 = {34805, 2, 0}, 0x3F2E = {34807, 2, 0}, 0x3F2F = {34809, 2, 0}, 0x3F37 = {34811, 2, 0}, 0x3F39 = {34813, 2, 0}, 0x3F3C = {34815, 2, 0}, 0x3F3D = {34817, 2, 0}, 0x3F3E = {34819, 2, 0}, 0x3F3F = {34821, 2, 0}, 0x3F40 = {34823, 1, 0}, 0x3F44 = {34824, 10, 0}, - 0x3F46 = {34834, 3, 0}, 0x3F47 = {34837, 8, 0}, 0x3F48 = {34845, 2, 0}, 0x3F4E = {34847, 2, 0}, 0x3F57 = {34849, 2, 0}, 0x3F59 = {34851, 2, 0}, 0x3F5C = {34853, 2, 0}, 0x3F5D = {34855, 2, 0}, 0x3F5E = {34857, 2, 0}, 0x3F5F = {34859, 2, 0}, 0x3F64 = {34861, 2, 0}, 0x3F77 = {34863, 2, 0}, 0x3F79 = {34865, 2, 0}, 0x3F7C = {34867, 2, 0}, 0x3F7D = {34869, 2, 0}, 0x3F7E = {34871, 2, 0}, - 0x3F7F = {34873, 2, 0}, 0x3F80 = {34875, 1, 0}, 0x3F82 = {34876, 2, 0}, 0x3F84 = {34878, 4, 0}, 0x3F86 = {34882, 2, 0}, 0x3F88 = {34884, 4, 0}, 0x3F8E = {34888, 2, 0}, 0x3F8F = {34890, 2, 0}, 0x3F97 = {34892, 2, 0}, 0x3F99 = {34894, 2, 0}, 0x3F9C = {34896, 2, 0}, 0x3F9D = {34898, 2, 0}, 0x3F9E = {34900, 2, 0}, 0x3F9F = {34902, 2, 0}, 0x3FA0 = {34904, 1, 0}, 0x3FA4 = {34905, 3, 0}, - 0x3FA8 = {34908, 2, 0}, 0x3FAE = {34910, 2, 0}, 0x3FAF = {34912, 2, 0}, 0x3FB7 = {34914, 2, 0}, 0x3FB9 = {34916, 2, 0}, 0x3FBC = {34918, 2, 0}, 0x3FBD = {34920, 2, 0}, 0x3FBE = {34922, 2, 0}, 0x3FBF = {34924, 2, 0}, 0x3FC4 = {34926, 4, 0}, 0x3FC6 = {34930, 1, 0}, 0x3FC7 = {34931, 2, 0}, 0x3FC8 = {34933, 2, 0}, 0x3FCE = {34935, 2, 0}, 0x3FD7 = {34937, 2, 0}, 0x3FD9 = {34939, 2, 0}, - 0x3FDC = {34941, 2, 0}, 0x3FDD = {34943, 2, 0}, 0x3FDE = {34945, 2, 0}, 0x3FDF = {34947, 2, 0}, 0x3FE4 = {34949, 4, 0}, 0x3FE8 = {34953, 2, 0}, 0x3FF7 = {34955, 2, 0}, 0x3FF9 = {34957, 2, 0}, 0x3FFC = {34959, 2, 0}, 0x3FFD = {34961, 2, 0}, 0x3FFE = {34963, 2, 0}, 0x3FFF = {34965, 2, 0}, -} - diff --git a/core/rexcode/ppc/encoder.odin b/core/rexcode/ppc/encoder.odin index 5db223a8b..583e89dd9 100644 --- a/core/rexcode/ppc/encoder.odin +++ b/core/rexcode/ppc/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= @@ -101,7 +103,7 @@ encode_one_inline :: #force_inline proc( relocs: ^[dynamic]Relocation, errors: ^[dynamic]Error, ) -> bool { - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return false @@ -142,7 +144,7 @@ encode_one_inline :: #force_inline proc( // Emit bytes. PowerPC is big-endian on the wire. if form.flags.prefixed { - prefix := PREFIX_BITS_TABLE[inst.mnemonic] + prefix := PREFIX_BITS_TABLE[u16(inst.mnemonic)] write_u32_be(code, pc, prefix) write_u32_be(code, pc + 4, word) inst.length = 8 diff --git a/core/rexcode/ppc/encoding_types.odin b/core/rexcode/ppc/encoding_types.odin index 143a89765..a654dd10a 100644 --- a/core/rexcode/ppc/encoding_types.odin +++ b/core/rexcode/ppc/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc import "../isa" diff --git a/core/rexcode/ppc/instructions.odin b/core/rexcode/ppc/instructions.odin index decd8fffc..4c9badd85 100644 --- a/core/rexcode/ppc/instructions.odin +++ b/core/rexcode/ppc/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= diff --git a/core/rexcode/ppc/mnemonics.odin b/core/rexcode/ppc/mnemonics.odin index 767847d32..2168409f5 100644 --- a/core/rexcode/ppc/mnemonics.odin +++ b/core/rexcode/ppc/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= diff --git a/core/rexcode/ppc/operands.odin b/core/rexcode/ppc/operands.odin index e9c91f4df..02d09dc5a 100644 --- a/core/rexcode/ppc/operands.odin +++ b/core/rexcode/ppc/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= diff --git a/core/rexcode/ppc/printer.odin b/core/rexcode/ppc/printer.odin index 9819a7d59..5018d9cde 100644 --- a/core/rexcode/ppc/printer.odin +++ b/core/rexcode/ppc/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc import "core:strings" diff --git a/core/rexcode/ppc/registers.odin b/core/rexcode/ppc/registers.odin index 3cbe3b202..691286736 100644 --- a/core/rexcode/ppc/registers.odin +++ b/core/rexcode/ppc/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= diff --git a/core/rexcode/ppc/reloc.odin b/core/rexcode/ppc/reloc.odin index 9bef135d1..9eee1299b 100644 --- a/core/rexcode/ppc/reloc.odin +++ b/core/rexcode/ppc/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc // ============================================================================= diff --git a/core/rexcode/ppc/encoding_table.odin b/core/rexcode/ppc/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/ppc/encoding_table.odin rename to core/rexcode/ppc/tablegen/encoding_table.odin index 76ae34f53..2888f4d06 100644 --- a/core/rexcode/ppc/encoding_table.odin +++ b/core/rexcode/ppc/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_ppc +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc_tablegen // ============================================================================= // PowerPC ENCODING_TABLE diff --git a/core/rexcode/ppc/tablegen/gen.odin b/core/rexcode/ppc/tablegen/gen.odin new file mode 100644 index 000000000..37b28c460 --- /dev/null +++ b/core/rexcode/ppc/tablegen/gen.odin @@ -0,0 +1,447 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc_tablegen + +// ============================================================================= +// POWERPC TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS + PREFIX_BITS_TABLE +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_FORM_IDX + +// DECODE_BUCKET_LIST + primary/sub index tables +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run ppc/tablegen # Stage A +// odin run ppc/tablegen/generated # Stage B +// +// PowerPC dispatch is two-level (one DECODE_ENTRIES array, two index tables): +// Primary (64 buckets): key = bits[26:31] (6-bit primary opcode). +// Secondary (16384): key = primary*256 + bits[1:8] (low XO bits, skip Rc). +// Each bucket points to a contiguous run in DECODE_BUCKET_LIST of entry indices, +// sorted by mask popcount descending so the most-specific match wins first. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "ppc.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "ppc.encode_runs.bin", "Encode_Run"}, + {"PREFIX_BITS_TABLE", "ppc.prefix_bits.bin", "u32"}, + {"DECODE_ENTRIES", "ppc.entries.bin", "Decode_Entry"}, + {"DECODE_FORM_IDX", "ppc.form_idx.bin", "u16"}, + {"DECODE_BUCKET_LIST", "ppc.bucket_list.bin", "u16"}, + {"DECODE_INDEX_PRIMARY", "ppc.idx_primary.bin", "Decode_Index"}, + {"DECODE_INDEX_SUB", "ppc.idx_sub.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +PRIMARY_BUCKETS :: 64 // bits[26:31] of word +SUB_BITS :: 8 // bits[1:8] of word (low XO bits, skipping Rc) +SUB_BUCKETS :: PRIMARY_BUCKETS * (1 << SUB_BITS) // 64 * 256 = 16384 + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + mode: lib.Mode, + flags: lib.Encoding_Flags, + form_idx: u16, +} + +Range :: struct { start: u32, count: u16 } + +Pair :: struct { bucket: u32, entry_idx: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("ppc tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index + prefix words (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for mn in Mnemonic { + for f, fi in ENCODING_TABLE[mn] { + append(&all, Entry{ + mnemonic = mn, + ops = f.ops, + enc = f.enc, + bits = f.bits, + mask = f.mask, + feature = f.feature, + mode = f.mode, + flags = f.flags, + form_idx = u16(fi), + }) + } + } + + // Sort the global entries array: by primary opcode, then mask popcount + // descending so within-bucket scan picks the most specific first. + slice.sort_by(all[:], proc(x, y: Entry) -> bool { + px := (x.bits >> 26) & 0x3F + py := (y.bits >> 26) & 0x3F + if px != py { return px < py } + xc := bits.count_ones(x.mask) + yc := bits.count_ones(y.mask) + if xc != yc { return xc > yc } + return u16(x.mnemonic) < u16(y.mnemonic) + }) + + // For each entry, enumerate the (primary, sub-key) pairs it can match. + primary_pairs: [dynamic]Pair + sub_pairs: [dynamic]Pair + defer delete(primary_pairs); defer delete(sub_pairs) + + keys: [dynamic]u32 + defer delete(keys) + + for e, i in all { + // Primary key + enumerate_keys(e.bits, e.mask, 26, 6, &keys) + for k in keys { + append(&primary_pairs, Pair{bucket = k, entry_idx = u16(i)}) + } + + // Sub key: primary << SUB_BITS | bits[1..SUB_BITS+1) + prim_keys: [dynamic]u32 + sub_only: [dynamic]u32 + defer delete(prim_keys); defer delete(sub_only) + enumerate_keys(e.bits, e.mask, 26, 6, &prim_keys) + enumerate_keys(e.bits, e.mask, 1, SUB_BITS, &sub_only) + for pk in prim_keys { + for sk in sub_only { + key := pk * (1 << SUB_BITS) + sk + append(&sub_pairs, Pair{bucket = key, entry_idx = u16(i)}) + } + } + } + + // Re-sort pair lists: primary order, then mask popcount descending. + rebuild :: proc(pairs: ^[dynamic]Pair, all: []Entry) { + Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u32 } + sortable := make([dynamic]Sort_Pair, 0, len(pairs), context.temp_allocator) + for pp in pairs^ { + e := all[pp.entry_idx] + pop := u64(bits.count_ones(e.mask)) + // (bucket << 40) | ((63 - pop) << 32) | mnemonic + key := (u64(pp.bucket) << 40) | ((63 - pop) << 32) | u64(e.mnemonic) + append(&sortable, Sort_Pair{sort_key = key, entry_idx = pp.entry_idx, bucket = pp.bucket}) + } + slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) + clear(pairs) + for s in sortable { append(pairs, Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } + } + rebuild(&primary_pairs, all[:]) + rebuild(&sub_pairs, all[:]) + + // Build flat u16 dispatch list. Each bucket points to a contiguous run. + primary_idx: [PRIMARY_BUCKETS]Range + sub_idx: [SUB_BUCKETS]Range + bucket_list: [dynamic]u16 + defer delete(bucket_list) + + emit_pairs :: proc(pairs: []Pair, idx: []Range, list: ^[dynamic]u16) { + prev_bucket: i64 = -1 + for pp in pairs { + cur := i64(pp.bucket) + if cur != prev_bucket { + idx[cur].start = u32(len(list)) + idx[cur].count = 0 + prev_bucket = cur + } + append(list, pp.entry_idx) + idx[cur].count += 1 + } + } + emit_pairs(primary_pairs[:], primary_idx[:], &bucket_list) + emit_pairs(sub_pairs[:], sub_idx[:], &bucket_list) + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), two-level primary+sub dispatch.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_form_idx(&sb, all[:]) + emit_bucket_list(&sb, bucket_list[:]) + emit_range_table(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) + emit_range_table(&sb, "DECODE_INDEX_SUB", sub_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +enumerate_keys :: proc(b, mask: u32, key_shift: u32, key_bits: u32, out: ^[dynamic]u32) { + clear(out) + key_mask := (u32(1) << key_bits) - 1 + fixed_key := ((b & mask) >> key_shift) & key_mask + var_bits := (~mask >> key_shift) & key_mask + sub: u32 = 0 + for { + append(out, fixed_key | sub) + if var_bits == 0 { break } + if sub == var_bits { break } + sub = (sub - var_bits) & var_bits + } +} + +emit_form_idx :: proc(sb: ^strings.Builder, entries: []Entry) { + all_zero := true + for e in entries { + if e.form_idx != 0 { all_zero = false; break } + } + if all_zero { + fmt.sbprintf(sb, "DECODE_FORM_IDX: [%d]u16\n\n", len(entries)) + } else { + fmt.sbprintf(sb, "DECODE_FORM_IDX := [%d]u16{{", len(entries)) + for e, i in entries { + if i % 64 == 0 { strings.write_string(sb, "\n\t") } + fmt.sbprintf(sb, "%d, ", e.form_idx) + } + strings.write_string(sb, "\n}\n\n") + } +} + +emit_bucket_list :: proc(sb: ^strings.Builder, items: []u16) { + fmt.sbprintf(sb, "DECODE_BUCKET_LIST := [%d]u16{{", len(items)) + for v, i in items { + if i % 64 == 0 { strings.write_string(sb, "\n\t") } + fmt.sbprintf(sb, "% 4d, ", v) + } + strings.write_string(sb, "\n}\n\n") +} + +emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintf(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + amount_set := 0 + for r, i in ranges { + if r.count != 0 { + if amount_set % 16 == 0 { strings.write_string(sb, "\n\t") } + fmt.sbprintf(sb, "0x%04X = {{% 5d, % 4d, 0}}, ", i, r.start, r.count) + amount_set += 1 + } + } + strings.write_string(sb, "\n}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, + mode: lib.Mode, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, mode, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.branch { append(&parts, "branch=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + if f.writes_lr { append(&parts, "writes_lr=true") } + if f.sets_cr0 { append(&parts, "sets_cr0=true") } + if f.sets_cr1 { append(&parts, "sets_cr1=true") } + if f.abs_branch { append(&parts, "abs_branch=true") } + if f.has_oe { append(&parts, "has_oe=true") } + if f.prefixed { append(&parts, "prefixed=true") } + if f.vle { append(&parts, "vle=true") } + if f.vle_short { append(&parts, "vle_short=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 2 +} +#assert(size_of(Decode_Entry) == 22) + +Decode_Index :: struct #packed { + start: u32, + count: u16, + _: u16, +} +#assert(size_of(Decode_Index) == 8) + +DECODE_SUB_BUCKETS :: 256 // per primary +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "ppc.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "ppc.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "ppc.prefix_bits.bin", raw(&PREFIX_BITS_TABLE, size_of(PREFIX_BITS_TABLE))) + w(TABLES + "ppc.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "ppc.form_idx.bin", raw(&DECODE_FORM_IDX, size_of(DECODE_FORM_IDX))) + w(TABLES + "ppc.bucket_list.bin", raw(&DECODE_BUCKET_LIST, size_of(DECODE_BUCKET_LIST))) + w(TABLES + "ppc.idx_primary.bin", raw(&DECODE_INDEX_PRIMARY, size_of(DECODE_INDEX_PRIMARY))) + w(TABLES + "ppc.idx_sub.bin", raw(&DECODE_INDEX_SUB, size_of(DECODE_INDEX_SUB))) +} diff --git a/core/rexcode/ppc/tables.odin b/core/rexcode/ppc/tables.odin new file mode 100644 index 000000000..3078f7b7c --- /dev/null +++ b/core/rexcode/ppc/tables.odin @@ -0,0 +1,70 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 2 +} +#assert(size_of(Decode_Entry) == 22) + +Decode_Index :: struct #packed { + start: u32, + count: u16, + _: u16, +} +#assert(size_of(Decode_Index) == 8) + +DECODE_SUB_BUCKETS :: 256 // per primary + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/ppc.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/ppc.encode_runs.bin", []Encode_Run) +@(rodata) PREFIX_BITS_TABLE := #load("tables/ppc.prefix_bits.bin", []u32) +@(rodata) DECODE_ENTRIES := #load("tables/ppc.entries.bin", []Decode_Entry) +@(rodata) DECODE_FORM_IDX := #load("tables/ppc.form_idx.bin", []u16) +@(rodata) DECODE_BUCKET_LIST := #load("tables/ppc.bucket_list.bin", []u16) +@(rodata) DECODE_INDEX_PRIMARY := #load("tables/ppc.idx_primary.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SUB := #load("tables/ppc.idx_sub.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/ppc/tables/ppc.bucket_list.bin b/core/rexcode/ppc/tables/ppc.bucket_list.bin new file mode 100644 index 0000000000000000000000000000000000000000..11315de5372f3a23aceb6c8d6acb24a62beea28f GIT binary patch literal 69934 zcmZQzU}RuoU}j)pU}a!qU}xZ9;AG%p;AY@q;AP-r;AaqE5M&Ty5M~fz5M>Z!5ND8J zkYtczkYOC}k*PC}*f(sAQ;OsAi~PsAZ^QsAp(k zXk=(&Xl7_(Xk}<)XlLkP=w#?(=w|3)=w;|*=x3O~Fp*&r!(@gj3{x4VF-&Ke!7!6y z7Q<|YISg|d<}u7?SirE5VG+Y(h9wM38J00DXIR0ol3^9YYKAooYZ=xttY_H3u#sUC z!)Asp3|kqtF>Ghp!LXBI7sGCbJq&vp_A%^dIKXg_;Sj@Nh9e9|8ICa=XE?!dlHnA? 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z-v{OIhw=|X`G=tVBT)WPDE~N=e*(%s1?8WH^3Ou~=b-!xQ2s?I|1y++1f{#_{lK9v6e%6|mqKZf$3Lix|2{1;IEODO*}l>Y|Ge+T8ihw?u{`JbTt zFHrthDE~W@{{zbZ1?B&S^8Z5l|Db$^c1Zcf*bXVrn4x?YD4z|=XNU4Rp?oeVp9jk4 zh4T5Kd;ut52+9|R@%1?yy zlcD?+C_fF#Plxg|q5Lc;KL^Ush4S;E`~oPy2+A*p@=KxoGAO?S%CCg-tD*cFD8CNM zuZQv*q5LK&zXi%~h4R~>{0=C;3(D_?@_V8DJ}7?zls^&5pA6+sf%2z8`O~5NnNa?$ zb_ND1*dzi21H+bfNc#aMv;)fD1Jwr;htd0>@-RL+eF#n85h(u{ltx#70!{oBlz#?F zpM%mDp!6jueFaKigVHc_Z$SCCp!6LmeGf`MfQAE1{lj+1{5OpMyq$r8n}LDh6I9)2 zs6LqdS2R9M92fl^s{SXG#-)ys_-{1*f6@3b{r{ojj2+N&5lXW{Y4#3Cxd~H`PIGiH zFmNFW3UxrnqeMF(>m+2M<{&A-%akWkJubr((acds z)#1`lD{*}^cNwDbVfGqB#Z95KIh3}9($;A4Zvz#F>9^}ZEf1W~*D)EsniT>Lnw`UEJA zOC2HcBsBdgXndIdG^lt6l+J?EIZzs=4i}w=7QaQ%@G6GtFNM;$^rMTHlc*kDKa5|A zW==I4AEvGrDqatz8=-VFl!mFpMYp2)A6;E1k>;T5qm> 24); buf[1] = u8(pfx >> 16); buf[2] = u8(pfx >> 8); buf[3] = u8(pfx) buf[4] = u8(word >> 24); buf[5] = u8(word >> 16); buf[6] = u8(word >> 8); buf[7] = u8(word) ilen = 8 diff --git a/core/rexcode/ppc/tests/full_sweep.odin b/core/rexcode/ppc/tests/full_sweep.odin index d91b0d7bc..455149e92 100644 --- a/core/rexcode/ppc/tests/full_sweep.odin +++ b/core/rexcode/ppc/tests/full_sweep.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_tests // Full encode→decode→re-encode sweep across the entire ENCODING_TABLE. @@ -30,7 +32,8 @@ run_full_sweep :: proc() { defer delete(fail_samples) for mn in p.Mnemonic { - forms := p.ENCODING_TABLE[mn] + _run := p.ENCODE_RUNS[u16(mn)] + forms := p.ENCODE_FORMS[_run.start:][:_run.count] for &f, fi in forms { test_form(mn, fi, &f, &fail_samples) } diff --git a/core/rexcode/ppc/tests/printer.odin b/core/rexcode/ppc/tests/printer.odin index 3803d89eb..cdab622ff 100644 --- a/core/rexcode/ppc/tests/printer.odin +++ b/core/rexcode/ppc/tests/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_tests import "core:fmt" diff --git a/core/rexcode/ppc/tests/roundtrip.odin b/core/rexcode/ppc/tests/roundtrip.odin index b3c5cc435..042f353f9 100644 --- a/core/rexcode/ppc/tests/roundtrip.odin +++ b/core/rexcode/ppc/tests/roundtrip.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_tests import "core:fmt" diff --git a/core/rexcode/ppc/tests/smoke.odin b/core/rexcode/ppc/tests/smoke.odin index 5ce918781..9012b7d06 100644 --- a/core/rexcode/ppc/tests/smoke.odin +++ b/core/rexcode/ppc/tests/smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_tests import "core:fmt" @@ -8,7 +10,8 @@ ok_count, fail_count: int @(private="file") check :: proc(name: string, mn: p.Mnemonic, idx: int, want_bits, want_mask: u32) { - enc := p.ENCODING_TABLE[mn] + _run := p.ENCODE_RUNS[u16(mn)] + enc := p.ENCODE_FORMS[_run.start:][:_run.count] if idx >= len(enc) { fmt.printf(" [FAIL] %s: entry %d not present (have %d)\n", name, idx, len(enc)) fail_count += 1 diff --git a/core/rexcode/ppc/tools/dump_verify_input.odin b/core/rexcode/ppc/tools/dump_verify_input.odin index 26dee0648..aae1b9a35 100644 --- a/core/rexcode/ppc/tools/dump_verify_input.odin +++ b/core/rexcode/ppc/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -38,7 +40,8 @@ main :: proc() { n_main, n_spe: int for mn in p.Mnemonic { - for &f in p.ENCODING_TABLE[mn] { + _run := p.ENCODE_RUNS[u16(mn)] + for &f in p.ENCODE_FORMS[_run.start:][:_run.count] { bits := fill_safe_operands(&f) hex_buf := &main_hex meta_buf := &main_meta @@ -53,7 +56,7 @@ main :: proc() { // For prefixed (POWER10 8-byte) instructions, emit the PREFIX // word first, then the SUFFIX word, both BE. if f.flags.prefixed { - pfx := p.PREFIX_BITS_TABLE[mn] | prefix_safe_fill(&f) + pfx := p.PREFIX_BITS_TABLE[u16(mn)] | prefix_safe_fill(&f) fmt.sbprintf(hex_buf, "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", (pfx >> 24) & 0xFF, (pfx >> 16) & 0xFF, (pfx >> 8) & 0xFF, pfx & 0xFF, (bits >> 24) & 0xFF, (bits >> 16) & 0xFF, (bits >> 8) & 0xFF, bits & 0xFF) diff --git a/core/rexcode/ppc/tools/gen_decode_tables.odin b/core/rexcode/ppc/tools/gen_decode_tables.odin deleted file mode 100644 index 11fefdb81..000000000 --- a/core/rexcode/ppc/tools/gen_decode_tables.odin +++ /dev/null @@ -1,378 +0,0 @@ -package main - -// ============================================================================= -// PowerPC DECODE-TABLE GENERATOR -// ============================================================================= -// -// Two-level dispatch (one DECODE_ENTRIES array, two index tables): -// -// Primary (64 buckets): -// key = bits[26:31] of the instruction word (6 bits = primary opcode). -// Covers all PowerPC instructions including 8-byte prefixed (whose SUFFIX -// word's primary opcode is also used here — the suffix's primary is -// distinct from the prefix's primary=1). -// -// Secondary (64 * 256 = 16384 buckets): -// key = primary * 256 + bits[1:8] (low 8 bits of the XO field, skipping -// the Rc bit at position 0). Most PPC entries have XO covered by the -// mask in bits 1..10, so secondary buckets are sparsely populated and -// scan length is small. -// -// At decode time: -// 1. Compute primary key. If primary == 1 (prefixed-instruction prefix), -// the next 4 bytes are the SUFFIX word and we redo dispatch on the -// suffix's primary. -// 2. Compute secondary key. If DECODE_INDEX_SUB[sub_key].count > 0, scan -// that bucket. Else fall back to DECODE_INDEX_PRIMARY[primary]. -// 3. Within a bucket, entries are sorted by mask popcount descending so -// the most-specific match wins on first hit. -// -// Run with: cd ppc && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:reflect" -import "core:math/bits" - -import p ".." - -Entry :: struct { - mnemonic: p.Mnemonic, - ops: [4]p.Operand_Type, - enc: [4]p.Operand_Encoding, - bits: u32, - mask: u32, - feature: p.Feature, - mode: p.Mode, - flags: p.Encoding_Flags, - form_idx: u16, -} - -Range :: struct { - start: u32, - count: u16, - _: u16, -} - -PRIMARY_BUCKETS :: 64 // bits[26:31] of word -SUB_BITS :: 8 // bits[1:8] of word (low XO bits, skipping Rc) -SUB_BUCKETS :: PRIMARY_BUCKETS * (1 << SUB_BITS) // 64 * 256 = 16384 - -Pair :: struct { bucket: u32, entry_idx: u16 } - -main :: proc() { - fmt.println("Generating PowerPC decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mn in p.Mnemonic { - for f, fi in p.ENCODING_TABLE[mn] { - e := Entry{ - mnemonic = mn, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - mode = f.mode, - flags = f.flags, - form_idx = u16(fi), - } - append(&all, e) - } - } - - // Sort the global entries array: by primary opcode, then mask popcount - // descending so within-bucket scan picks the most specific first. - slice.sort_by(all[:], proc(x, y: Entry) -> bool { - px := (x.bits >> 26) & 0x3F - py := (y.bits >> 26) & 0x3F - if px != py { return px < py } - xc := bits.count_ones(x.mask) - yc := bits.count_ones(y.mask) - if xc != yc { return xc > yc } - return u16(x.mnemonic) < u16(y.mnemonic) - }) - - // For each entry, enumerate the (primary, sub-key) pairs it can match. - // enumerate_keys handles variable bits in the bucket-key field. - primary_pairs: [dynamic]Pair - sub_pairs: [dynamic]Pair - defer delete(primary_pairs); defer delete(sub_pairs) - - keys: [dynamic]u32 - defer delete(keys) - - for e, i in all { - // Primary key - enumerate_keys(e.bits, e.mask, 26, 6, &keys) - for k in keys { - append(&primary_pairs, Pair{bucket = k, entry_idx = u16(i)}) - } - - // Sub key: primary << SUB_BITS | bits[1..SUB_BITS+1) - // (enumerate_keys handles variable bits in both ranges; we combine - // primary and XO low bits into a single 14-bit key.) - prim_keys: [dynamic]u32 - sub_only: [dynamic]u32 - defer delete(prim_keys); defer delete(sub_only) - enumerate_keys(e.bits, e.mask, 26, 6, &prim_keys) - enumerate_keys(e.bits, e.mask, 1, SUB_BITS, &sub_only) - for pk in prim_keys { - for sk in sub_only { - key := pk * (1 << SUB_BITS) + sk - append(&sub_pairs, Pair{bucket = key, entry_idx = u16(i)}) - } - } - } - - // Re-sort pair lists: primary order, then mask popcount descending - rebuild :: proc(pairs: ^[dynamic]Pair, all: []Entry) { - Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u32 } - sortable := make([dynamic]Sort_Pair, 0, len(pairs), context.temp_allocator) - for pp in pairs^ { - e := all[pp.entry_idx] - pop := u64(bits.count_ones(e.mask)) - // (bucket << 40) | ((63 - pop) << 32) | mnemonic - key := (u64(pp.bucket) << 40) | ((63 - pop) << 32) | u64(e.mnemonic) - append(&sortable, Sort_Pair{sort_key = key, entry_idx = pp.entry_idx, bucket = pp.bucket}) - } - slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) - clear(pairs) - for s in sortable { append(pairs, Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } - } - rebuild(&primary_pairs, all[:]) - rebuild(&sub_pairs, all[:]) - - // Build flat u16 dispatch list. Each bucket points to a contiguous run. - primary_idx: [PRIMARY_BUCKETS]Range - sub_idx: [SUB_BUCKETS]Range - bucket_list: [dynamic]u16 - defer delete(bucket_list) - - emit_pairs :: proc(pairs: []Pair, idx: []Range, list: ^[dynamic]u16) { - prev_bucket: i64 = -1 - for pp in pairs { - cur := i64(pp.bucket) - if cur != prev_bucket { - idx[cur].start = u32(len(list)) - idx[cur].count = 0 - prev_bucket = cur - } - append(list, pp.entry_idx) - idx[cur].count += 1 - } - } - emit_pairs(primary_pairs[:], primary_idx[:], &bucket_list) - emit_pairs(sub_pairs[:], sub_idx[:], &bucket_list) - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_form_idx(&sb, all[:]) - emit_bucket_list(&sb, bucket_list[:]) - emit_range_table(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SUB", sub_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - // Stats - max_primary, max_sub: u16 - pop_primary, pop_sub: int - for r in primary_idx { if r.count > max_primary { max_primary = r.count }; if r.count > 0 { pop_primary += 1 } } - for r in sub_idx { if r.count > max_sub { max_sub = r.count }; if r.count > 0 { pop_sub += 1 } } - fmt.printfln("OK — %d entries: PRIMARY %d/%d buckets (max=%d); SUB %d/%d buckets (max=%d); bucket_list %d entries", - len(all), pop_primary, PRIMARY_BUCKETS, max_primary, - pop_sub, SUB_BUCKETS, max_sub, len(bucket_list)) -} - -enumerate_keys :: proc(b, mask: u32, key_shift: u32, key_bits: u32, out: ^[dynamic]u32) { - clear(out) - key_mask := (u32(1) << key_bits) - 1 - fixed_key := ((b & mask) >> key_shift) & key_mask - var_bits := (~mask >> key_shift) & key_mask - sub: u32 = 0 - for { - append(out, fixed_key | sub) - if var_bits == 0 { break } - if sub == var_bits { break } - sub = (sub - var_bits) & var_bits - } -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_ppc - -// ============================================================================= -// GENERATED FILE — DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd ppc && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - mode: Mode, - flags: Encoding_Flags, -} - -Decode_Index :: struct #packed { - start: u32, - count: u16, - _: u16, -} - -DECODE_SUB_BUCKETS :: 256 // per primary - -`) -} - - -print_enum_buffered :: proc(sb: ^strings.Builder, x: $T, max_name: int, comma: bool) { - fmt.sbprintf(sb, ".%v", x) - if comma { - strings.write_string(sb, ", ") - } else { - return - } - for n := max_name-len(reflect.enum_string(x)); n > 0; n -= 1 { - strings.write_byte(sb, ' ') - } -} - -print_enum_space :: proc(sb: ^strings.Builder, x: $T, max_name: int) { - for n := max_name-len(reflect.enum_string(x)); n > 0; n -= 1 { - strings.write_byte(sb, ' ') - } -} - - -max_enum_name_len :: proc($T: typeid) -> int { - max_len := 0 - for name in reflect.enum_field_names(T) { - max_len = max(max_len, len(name)) - } - return max_len -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - - max_mnemonic_len := max_enum_name_len(p.Mnemonic) - max_op_len := max_enum_name_len(p.Operand_Type) - max_enc_len := max_enum_name_len(p.Operand_Encoding) - max_feature_len := max_enum_name_len(p.Feature) - max_mode_len := max_enum_name_len(p.Mode) - - for e in entries { - strings.write_string(sb, "\t{") - defer strings.write_string(sb, "},\n") - - print_enum_buffered(sb, e.mnemonic, max_mnemonic_len, true) - - flags_str := encode_flags_literal(e.flags) - - strings.write_string(sb, "{") - for op_type, i in e.ops { - print_enum_buffered(sb, op_type, max_op_len, i+1 < len(e.ops)) - } - strings.write_string(sb, "}, ") - print_enum_space(sb, e.ops[len(e.ops)-1], max_op_len) - - strings.write_string(sb, "{") - for enc_type, i in e.enc { - print_enum_buffered(sb, enc_type, max_enc_len, i+1 < len(e.enc)) - } - strings.write_string(sb, "}, ") - print_enum_space(sb, e.enc[len(e.enc)-1], max_enc_len) - - fmt.sbprintf(sb, "0x%08X, 0x%08X, ", e.bits, e.mask) - print_enum_buffered(sb, e.feature, max_feature_len, true) - print_enum_buffered(sb, e.mode, max_mode_len, true) - fmt.sbprintf(sb, "{{%s}}", flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: p.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - w :: proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.branch { w(&sb, &first, "branch=true") } - if f.cond_branch { w(&sb, &first, "cond_branch=true") } - if f.writes_lr { w(&sb, &first, "writes_lr=true") } - if f.sets_cr0 { w(&sb, &first, "sets_cr0=true") } - if f.sets_cr1 { w(&sb, &first, "sets_cr1=true") } - if f.abs_branch { w(&sb, &first, "abs_branch=true") } - if f.has_oe { w(&sb, &first, "has_oe=true") } - if f.prefixed { w(&sb, &first, "prefixed=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintf(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - amount_set := 0 - for r, i in ranges { - if r.count != 0 { - if amount_set % 16 == 0 { strings.write_string(sb, "\n\t") } - fmt.sbprintf(sb, "0x%04X = {{% 5d, % 4d, 0}}, ", i, r.start, r.count) - amount_set += 1 - } - } - strings.write_string(sb, "\n}\n\n") -} - -emit_form_idx :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "@(rodata)") - all_zero := true - for e in entries { - if e.form_idx != 0 { - all_zero = false - break - } - } - if all_zero { - fmt.sbprintf(sb, "DECODE_FORM_IDX: [%d]u16\n\n", len(entries)) - } else { - fmt.sbprintf(sb, "DECODE_FORM_IDX := [%d]u16{{", len(entries)) - for e, i in entries { - if i % 64 == 0 { strings.write_string(sb, "\n\t") } - fmt.sbprintf(sb, "%d, ", e.form_idx) - } - strings.write_string(sb, "\n}\n\n") - } -} - -emit_bucket_list :: proc(sb: ^strings.Builder, items: []u16) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintf(sb, "DECODE_BUCKET_LIST := [%d]u16{{", len(items)) - for v, i in items { - if i % 64 == 0 { strings.write_string(sb, "\n\t") } - fmt.sbprintf(sb, "% 4d, ", v) - } - strings.write_string(sb, "\n}\n\n") -} diff --git a/core/rexcode/ppc/tools/llvm_per_line.sh b/core/rexcode/ppc/tools/llvm_per_line.sh index 74b32c287..fb508c843 100644 --- a/core/rexcode/ppc/tools/llvm_per_line.sh +++ b/core/rexcode/ppc/tools/llvm_per_line.sh @@ -1,4 +1,6 @@ #!/bin/bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # Per-line llvm-mc disassembly wrapper. Reads a .hex manifest, runs each line # through llvm-mc independently so output lines align 1:1 with input lines. # (llvm-mc's stream mode is greedy: it consumes prefix bytes when a line looks diff --git a/core/rexcode/ppc/tools/verify_against_llvm.odin b/core/rexcode/ppc/tools/verify_against_llvm.odin index 211b6cd98..0c6d488bc 100644 --- a/core/rexcode/ppc/tools/verify_against_llvm.odin +++ b/core/rexcode/ppc/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= diff --git a/core/rexcode/ppc_vle/decoder.odin b/core/rexcode/ppc_vle/decoder.odin index e7a306035..4ea248ef0 100644 --- a/core/rexcode/ppc_vle/decoder.odin +++ b/core/rexcode/ppc_vle/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle import "../isa" diff --git a/core/rexcode/ppc_vle/encoder.odin b/core/rexcode/ppc_vle/encoder.odin index 158761815..2869e078a 100644 --- a/core/rexcode/ppc_vle/encoder.odin +++ b/core/rexcode/ppc_vle/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= @@ -82,7 +84,7 @@ encode_one_inline :: #force_inline proc( relocs: ^[dynamic]Relocation, errors: ^[dynamic]Error, ) -> bool { - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return false diff --git a/core/rexcode/ppc_vle/encoding_types.odin b/core/rexcode/ppc_vle/encoding_types.odin index 5f5145609..53296012d 100644 --- a/core/rexcode/ppc_vle/encoding_types.odin +++ b/core/rexcode/ppc_vle/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle import "../isa" diff --git a/core/rexcode/ppc_vle/instructions.odin b/core/rexcode/ppc_vle/instructions.odin index db0a4049a..1e2b545ab 100644 --- a/core/rexcode/ppc_vle/instructions.odin +++ b/core/rexcode/ppc_vle/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= diff --git a/core/rexcode/ppc_vle/mnemonics.odin b/core/rexcode/ppc_vle/mnemonics.odin index 0f160c144..a5aa74a80 100644 --- a/core/rexcode/ppc_vle/mnemonics.odin +++ b/core/rexcode/ppc_vle/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= diff --git a/core/rexcode/ppc_vle/operands.odin b/core/rexcode/ppc_vle/operands.odin index a130c6c47..3e81c0f9a 100644 --- a/core/rexcode/ppc_vle/operands.odin +++ b/core/rexcode/ppc_vle/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= diff --git a/core/rexcode/ppc_vle/printer.odin b/core/rexcode/ppc_vle/printer.odin index a8cb18f97..52a06b3ef 100644 --- a/core/rexcode/ppc_vle/printer.odin +++ b/core/rexcode/ppc_vle/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle import "core:strings" diff --git a/core/rexcode/ppc_vle/registers.odin b/core/rexcode/ppc_vle/registers.odin index 07401bf4d..6b02c7032 100644 --- a/core/rexcode/ppc_vle/registers.odin +++ b/core/rexcode/ppc_vle/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= diff --git a/core/rexcode/ppc_vle/reloc.odin b/core/rexcode/ppc_vle/reloc.odin index f674528a5..de17f60d1 100644 --- a/core/rexcode/ppc_vle/reloc.odin +++ b/core/rexcode/ppc_vle/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_ppc_vle // ============================================================================= diff --git a/core/rexcode/ppc_vle/encoding_table.odin b/core/rexcode/ppc_vle/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/ppc_vle/encoding_table.odin rename to core/rexcode/ppc_vle/tablegen/encoding_table.odin index 666d25a6a..683e3d926 100644 --- a/core/rexcode/ppc_vle/encoding_table.odin +++ b/core/rexcode/ppc_vle/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_ppc_vle +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc_vle_tablegen // ============================================================================= // PowerPC VLE Encoding Table diff --git a/core/rexcode/ppc_vle/tablegen/gen.odin b/core/rexcode/ppc_vle/tablegen/gen.odin new file mode 100644 index 000000000..cb847d0b4 --- /dev/null +++ b/core/rexcode/ppc_vle/tablegen/gen.odin @@ -0,0 +1,379 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc_vle_tablegen + +// ============================================================================= +// PowerPC VLE TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + DECODE_FORM_IDX + +// DECODE_BUCKET_LIST + DECODE_INDEX_SHORT/LONG +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run ppc_vle/tablegen # Stage A +// odin run ppc_vle/tablegen/generated # Stage B +// +// VLE dispatch has two namespaces: +// - 16-bit (flags.short=true) — primary key = bits 10..15 of halfword (6 bits) +// - 32-bit — primary key = bits 26..31 of word (6 bits) +// Each fits a 64-bucket primary table. Within a bucket, entries are sorted by +// mask popcount descending so the most-specific form matches first. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "ppc_vle.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "ppc_vle.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "ppc_vle.entries.bin", "Decode_Entry"}, + {"DECODE_FORM_IDX", "ppc_vle.form_idx.bin", "u16"}, + {"DECODE_BUCKET_LIST", "ppc_vle.bucket_list.bin", "u16"}, + {"DECODE_INDEX_SHORT", "ppc_vle.idx_short.bin", "Decode_Index"}, + {"DECODE_INDEX_LONG", "ppc_vle.idx_long.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +PRIMARY_BUCKETS :: 64 + +Entry :: struct { + mn: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + mode: lib.Mode, + flags: lib.Encoding_Flags, + form_idx: u16, +} + +// Decode index range: {start into bucket_list, count}. Mirrors the loader's +// 8-byte Decode_Index ({u32,u16,u16}); the writer dumps the matching shape. +Range :: struct { start: u32, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("ppc_vle tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_vle_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f, fi in ENCODING_TABLE[m] { + append(&all, Entry{ + mn = m, ops = f.ops, enc = f.enc, + bits = f.bits, mask = f.mask, + feature = f.feature, mode = f.mode, flags = f.flags, + form_idx = u16(fi), + }) + } + } + + slice.sort_by(all[:], proc(x, y: Entry) -> bool { + px := primary_key(x) + py := primary_key(y) + if px != py { return px < py } + if x.flags.short != y.flags.short { return x.flags.short } + xc := bits.count_ones(x.mask) + yc := bits.count_ones(y.mask) + if xc != yc { return xc > yc } + return u16(x.mn) < u16(y.mn) + }) + + Pair :: struct { bucket: u16, entry_idx: u16 } + short_pairs: [dynamic]Pair + long_pairs: [dynamic]Pair + defer delete(short_pairs); defer delete(long_pairs) + + for e, i in all { + key := primary_key(e) + p := Pair{bucket = key, entry_idx = u16(i)} + if e.flags.short { + append(&short_pairs, p) + } else { + append(&long_pairs, p) + } + } + + rebuild :: proc(pairs: ^[dynamic]Pair, all: []Entry) { + Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u16 } + sortable := make([dynamic]Sort_Pair, 0, len(pairs), context.temp_allocator) + for p in pairs^ { + e := all[p.entry_idx] + pop := u64(bits.count_ones(e.mask)) + key := (u64(p.bucket) << 40) | ((63 - pop) << 32) | u64(e.mn) + append(&sortable, Sort_Pair{sort_key = key, entry_idx = p.entry_idx, bucket = p.bucket}) + } + slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) + clear(pairs) + for s in sortable { append(pairs, Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } + } + rebuild(&short_pairs, all[:]) + rebuild(&long_pairs, all[:]) + + short_idx: [PRIMARY_BUCKETS]Range + long_idx: [PRIMARY_BUCKETS]Range + bucket_list: [dynamic]u16 + defer delete(bucket_list) + + emit_pairs :: proc(pairs: []Pair, idx: []Range, list: ^[dynamic]u16) { + prev: i32 = -1 + for p in pairs { + cur := i32(p.bucket) + if cur != prev { + idx[cur].start = u32(len(list)) + idx[cur].count = 0 + prev = cur + } + append(list, p.entry_idx) + idx[cur].count += 1 + } + } + emit_pairs(short_pairs[:], short_idx[:], &bucket_list) + emit_pairs(long_pairs[:], long_idx[:], &bucket_list) + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_vle_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by primary opcode.\n") + strings.write_string(&sb, "// Two dispatch namespaces: 16-bit (SHORT) and 32-bit (LONG).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mn, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags) + } + strings.write_string(&sb, "}\n\n") + + fmt.sbprintf(&sb, "DECODE_FORM_IDX := [%d]u16{{", len(all)) + for e, i in all { + if i % 16 == 0 { strings.write_string(&sb, "\n\t") } + fmt.sbprintf(&sb, "%d, ", e.form_idx) + } + strings.write_string(&sb, "\n}\n\n") + + fmt.sbprintf(&sb, "DECODE_BUCKET_LIST := [%d]u16{{", len(bucket_list)) + for v, i in bucket_list { + if i % 16 == 0 { strings.write_string(&sb, "\n\t") } + fmt.sbprintf(&sb, "% 3d, ", v) + } + strings.write_string(&sb, "\n}\n\n") + + emit_range(&sb, "DECODE_INDEX_SHORT", short_idx[:]) + emit_range(&sb, "DECODE_INDEX_LONG", long_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +primary_key :: proc(e: Entry) -> u16 { + if e.flags.short { + return u16((e.bits >> 10) & 0x3F) + } + return u16((e.bits >> 26) & 0x3F) +} + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d, 0}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting (matches ppc_vle's original generator) +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, + feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v, .%v, .%v, .%v}}, {{.%v, .%v, .%v, .%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], + bits, mask, feature, mode, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.short { append(&parts, "short=true") } + if f.cond_branch { append(&parts, "cond_branch=true") } + if f.writes_lr { append(&parts, "writes_lr=true") } + if f.sets_cr0 { append(&parts, "sets_cr0=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_vle_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 21) + +Decode_Index :: struct #packed { + start: u32, + count: u16, + _: u16, +} +#assert(size_of(Decode_Index) == 8) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_ppc_vle\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "ppc_vle.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "ppc_vle.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "ppc_vle.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "ppc_vle.form_idx.bin", raw(&DECODE_FORM_IDX, size_of(DECODE_FORM_IDX))) + w(TABLES + "ppc_vle.bucket_list.bin", raw(&DECODE_BUCKET_LIST, size_of(DECODE_BUCKET_LIST))) + w(TABLES + "ppc_vle.idx_short.bin", raw(&DECODE_INDEX_SHORT, size_of(DECODE_INDEX_SHORT))) + w(TABLES + "ppc_vle.idx_long.bin", raw(&DECODE_INDEX_LONG, size_of(DECODE_INDEX_LONG))) +} diff --git a/core/rexcode/ppc_vle/tables.odin b/core/rexcode/ppc_vle/tables.odin new file mode 100644 index 000000000..f68aa3644 --- /dev/null +++ b/core/rexcode/ppc_vle/tables.odin @@ -0,0 +1,67 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_ppc_vle + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + mode: Mode, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 21) + +Decode_Index :: struct #packed { + start: u32, + count: u16, + _: u16, +} +#assert(size_of(Decode_Index) == 8) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/ppc_vle.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/ppc_vle.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/ppc_vle.entries.bin", []Decode_Entry) +@(rodata) DECODE_FORM_IDX := #load("tables/ppc_vle.form_idx.bin", []u16) +@(rodata) DECODE_BUCKET_LIST := #load("tables/ppc_vle.bucket_list.bin", []u16) +@(rodata) DECODE_INDEX_SHORT := #load("tables/ppc_vle.idx_short.bin", []Decode_Index) +@(rodata) DECODE_INDEX_LONG := #load("tables/ppc_vle.idx_long.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/ppc_vle/tables/ppc_vle.bucket_list.bin b/core/rexcode/ppc_vle/tables/ppc_vle.bucket_list.bin new file mode 100644 index 0000000000000000000000000000000000000000..650cd99ad0d6d937616e136a6cc24b87b48bc0fe GIT binary patch literal 444 zcmZQzU}RuoU}j)pU}a!qU}xZ9;AG%p;AY@q;AP-r;AaqE5M&Ty5M~fz5M>Z!5ND8J zkYtczkYxXy5c;U>c^ zhT9Bx816DCGAJ=9GpI1AGN>`AGiWeqGH5YqGw3krGUzerGZ-)!G8i!!Gng=#GMF)# zGgvTKGFUNKGuSZLGT1TLGdM6fGB`0fGq^CgGPp6gGk7p~GI%j~Gx#w0GWaq0GXyXM zG6XS1F+?-OFr+c0Gh{GiG88ftF%&bDFqATsF_be@FjO*BF;p|uFw`>CG1N0OFf=kW zF*Gx@FtjqXF|;#uFmy6>F?2KZF!VC?G4wM`V3^1-iD5Fs6o#n`(-@{R%wU+wFpFU} z!yJaW4D%S~Gb~_O$gqfEF~bsur3}j$mNTqiSjn)8VKu`VhP4dq7}hgvVA#m8iD5It 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%d passed, %d failed\n", ok_count, fail_count) if fail_count > 0 { os.exit(1) } diff --git a/core/rexcode/ppc_vle/tools/dump_verify_input.odin b/core/rexcode/ppc_vle/tools/dump_verify_input.odin index 032f34745..f6521da74 100644 --- a/core/rexcode/ppc_vle/tools/dump_verify_input.odin +++ b/core/rexcode/ppc_vle/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -42,7 +44,8 @@ main :: proc() { n: int for mn in v.Mnemonic { - for &f in v.ENCODING_TABLE[mn] { + _run := v.ENCODE_RUNS[u16(mn)] + for &f in v.ENCODE_FORMS[_run.start:][:_run.count] { word := f.bits if f.flags.short { fmt.sbprintf(&hex_buf, "0x%02x,0x%02x\n", diff --git a/core/rexcode/ppc_vle/tools/gen_decode_tables.odin b/core/rexcode/ppc_vle/tools/gen_decode_tables.odin deleted file mode 100644 index 7a2d80213..000000000 --- a/core/rexcode/ppc_vle/tools/gen_decode_tables.odin +++ /dev/null @@ -1,230 +0,0 @@ -package main - -// ============================================================================= -// PowerPC VLE Decode-Table Generator -// ============================================================================= -// -// VLE has two dispatch namespaces: -// - 16-bit (flags.short=true) — primary key = bits 10..15 of halfword (6 bits) -// - 32-bit — primary key = bits 26..31 of word (6 bits) -// -// Both fit in 64-bucket primary tables. Within a bucket, entries are sorted -// by mask popcount descending so the most-specific form matches first. - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import v ".." - -Range :: struct #packed { - start: u32, - count: u16, - _: u16, -} - -Entry :: struct { - mn: v.Mnemonic, - ops: [4]v.Operand_Type, - enc: [4]v.Operand_Encoding, - bits: u32, - mask: u32, - feature: v.Feature, - mode: v.Mode, - flags: v.Encoding_Flags, - form_idx: u16, -} - -PRIMARY_BUCKETS :: 64 - -Pair :: struct { bucket: u16, entry_idx: u16 } - -main :: proc() { - fmt.println("Generating PowerPC VLE decoder tables...") - - all: [dynamic]Entry - defer delete(all) - - for mn in v.Mnemonic { - for f, fi in v.ENCODING_TABLE[mn] { - append(&all, Entry{ - mn = mn, ops = f.ops, enc = f.enc, - bits = f.bits, mask = f.mask, - feature = f.feature, mode = f.mode, flags = f.flags, - form_idx = u16(fi), - }) - } - } - - slice.sort_by(all[:], proc(x, y: Entry) -> bool { - px := primary_key(x) - py := primary_key(y) - if px != py { return px < py } - if x.flags.short != y.flags.short { return x.flags.short } - xc := bits.count_ones(x.mask) - yc := bits.count_ones(y.mask) - if xc != yc { return xc > yc } - return u16(x.mn) < u16(y.mn) - }) - - short_pairs: [dynamic]Pair - long_pairs: [dynamic]Pair - defer delete(short_pairs); defer delete(long_pairs) - - for e, i in all { - key := primary_key(e) - p := Pair{bucket = key, entry_idx = u16(i)} - if e.flags.short { - append(&short_pairs, p) - } else { - append(&long_pairs, p) - } - } - - rebuild :: proc(pairs: ^[dynamic]Pair, all: []Entry) { - Sort_Pair :: struct { sort_key: u64, entry_idx: u16, bucket: u16 } - sortable := make([dynamic]Sort_Pair, 0, len(pairs), context.temp_allocator) - for p in pairs^ { - e := all[p.entry_idx] - pop := u64(bits.count_ones(e.mask)) - key := (u64(p.bucket) << 40) | ((63 - pop) << 32) | u64(e.mn) - append(&sortable, Sort_Pair{sort_key = key, entry_idx = p.entry_idx, bucket = p.bucket}) - } - slice.sort_by_key(sortable[:], proc(s: Sort_Pair) -> u64 { return s.sort_key }) - clear(pairs) - for s in sortable { append(pairs, Pair{bucket = s.bucket, entry_idx = s.entry_idx}) } - } - rebuild(&short_pairs, all[:]) - rebuild(&long_pairs, all[:]) - - short_idx: [PRIMARY_BUCKETS]Range - long_idx: [PRIMARY_BUCKETS]Range - bucket_list: [dynamic]u16 - defer delete(bucket_list) - - emit_pairs :: proc(pairs: []Pair, idx: []Range, list: ^[dynamic]u16) { - prev: i32 = -1 - for p in pairs { - cur := i32(p.bucket) - if cur != prev { - idx[cur].start = u32(len(list)) - idx[cur].count = 0 - prev = cur - } - append(list, p.entry_idx) - idx[cur].count += 1 - } - } - emit_pairs(short_pairs[:], short_idx[:], &bucket_list) - emit_pairs(long_pairs[:], long_idx[:], &bucket_list) - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - strings.write_string(&sb, `package rexcode_ppc_vle - -// ============================================================================= -// GENERATED FILE — DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd ppc_vle && odin run tools/gen_decode_tables.odin -file - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - mode: Mode, - flags: Encoding_Flags, -} - -Decode_Index :: struct #packed { - start: u32, - count: u16, - _: u16, -} - -`) - - fmt.sbprintfln(&sb, "@(rodata)") - fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(all)) - for e in all { - flags_str := flags_literal(e.flags) - fmt.sbprintfln(&sb, - "\t{{ .%v, {{.%v, .%v, .%v, .%v}}, {{.%v, .%v, .%v, .%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},", - e.mn, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, e.mode, flags_str) - } - strings.write_string(&sb, "}\n\n") - - fmt.sbprintf(&sb, "DECODE_FORM_IDX := [%d]u16{{", len(all)) - for e, i in all { - if i % 16 == 0 { strings.write_string(&sb, "\n\t") } - fmt.sbprintf(&sb, "%d, ", e.form_idx) - } - strings.write_string(&sb, "\n}\n\n") - - fmt.sbprintf(&sb, "DECODE_BUCKET_LIST := [%d]u16{{", len(bucket_list)) - for v, i in bucket_list { - if i % 16 == 0 { strings.write_string(&sb, "\n\t") } - fmt.sbprintf(&sb, "% 3d, ", v) - } - strings.write_string(&sb, "\n}\n\n") - - emit_range_table(&sb, "DECODE_INDEX_SHORT", short_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_LONG", long_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED: %v", err); os.exit(1) - } - - max_s, max_l: u16 - pop_s, pop_l: int - for r in short_idx { if r.count > max_s { max_s = r.count }; if r.count > 0 { pop_s += 1 } } - for r in long_idx { if r.count > max_l { max_l = r.count }; if r.count > 0 { pop_l += 1 } } - fmt.printfln("OK — %d entries: SHORT %d/64 buckets (max=%d); LONG %d/64 buckets (max=%d); bucket_list %d", - len(all), pop_s, max_s, pop_l, max_l, len(bucket_list)) -} - -primary_key :: proc(e: Entry) -> u16 { - if e.flags.short { - return u16((e.bits >> 10) & 0x3F) - } - return u16((e.bits >> 26) & 0x3F) -} - -flags_literal :: proc(f: v.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - w :: proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.short { w(&sb, &first, "short=true") } - if f.cond_branch { w(&sb, &first, "cond_branch=true") } - if f.writes_lr { w(&sb, &first, "writes_lr=true") } - if f.sets_cr0 { w(&sb, &first, "sets_cr0=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d,%d,0}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/ppc_vle/tools/verify_against_vle_as.sh b/core/rexcode/ppc_vle/tools/verify_against_vle_as.sh index f95041421..e93e24a6f 100644 --- a/core/rexcode/ppc_vle/tools/verify_against_vle_as.sh +++ b/core/rexcode/ppc_vle/tools/verify_against_vle_as.sh @@ -1,4 +1,6 @@ #!/usr/bin/env bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # ============================================================================= # PowerPC VLE verification harness — assemble + objdump (binutils VLE) # ============================================================================= diff --git a/core/rexcode/riscv/decoder.odin b/core/rexcode/riscv/decoder.odin index 467cbc146..27e6ab4ae 100644 --- a/core/rexcode/riscv/decoder.odin +++ b/core/rexcode/riscv/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv import "../isa" diff --git a/core/rexcode/riscv/decoding_tables.odin b/core/rexcode/riscv/decoding_tables.odin deleted file mode 100644 index 6fd184473..000000000 --- a/core/rexcode/riscv/decoding_tables.odin +++ /dev/null @@ -1,307 +0,0 @@ -package rexcode_riscv - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd riscv && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -@(rodata) -DECODE_ENTRIES := [194]Decode_Entry{ - {.LB, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00000003, 0x0000707F, .I, {}}, - {.LH, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00001003, 0x0000707F, .I, {}}, - {.LW, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00002003, 0x0000707F, .I, {}}, - {.LBU, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00004003, 0x0000707F, .I, {}}, - {.LHU, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00005003, 0x0000707F, .I, {}}, - {.LWU, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00006003, 0x0000707F, .I, {rv64_only=true}}, - {.LD, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00003003, 0x0000707F, .I, {rv64_only=true}}, - {.FLW, {.FPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00002007, 0x0000707F, .F, {}}, - {.FLD, {.FPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_I, .NONE, .NONE}, 0x00003007, 0x0000707F, .D, {}}, - {.FENCE_I, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000100F, 0xFFFFFFFF, .ZIFENCEI, {}}, - {.FENCE, {.FENCE_FLAGS, .FENCE_FLAGS, .NONE, .NONE}, {.FENCE_PRED, .FENCE_SUCC, .NONE, .NONE}, 0x0000000F, 0x0000707F, .I, {}}, - {.SLLI, {.GPR, .GPR, .IMM6, .NONE}, {.RD, .RS1, .SHAMT6, .NONE}, 0x00001013, 0xFC00707F, .I, {}}, - {.SRLI, {.GPR, .GPR, .IMM6, .NONE}, {.RD, .RS1, .SHAMT6, .NONE}, 0x00005013, 0xFC00707F, .I, {}}, - {.SRAI, {.GPR, .GPR, .IMM6, .NONE}, {.RD, .RS1, .SHAMT6, .NONE}, 0x40005013, 0xFC00707F, .I, {}}, - {.ADDI, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00000013, 0x0000707F, .I, {}}, - {.SLTI, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00002013, 0x0000707F, .I, {}}, - {.SLTIU, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00003013, 0x0000707F, .I, {}}, - {.XORI, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00004013, 0x0000707F, .I, {}}, - {.ORI, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00006013, 0x0000707F, .I, {}}, - {.ANDI, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00007013, 0x0000707F, .I, {}}, - {.AUIPC, {.GPR, .IMM20, .NONE, .NONE}, {.RD, .IMM_U, .NONE, .NONE}, 0x00000017, 0x0000007F, .I, {}}, - {.SLLIW, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RS1, .SHAMT5, .NONE}, 0x0000101B, 0xFE00707F, .I, {rv64_only=true}}, - {.SRLIW, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RS1, .SHAMT5, .NONE}, 0x0000501B, 0xFE00707F, .I, {rv64_only=true}}, - {.SRAIW, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RS1, .SHAMT5, .NONE}, 0x4000501B, 0xFE00707F, .I, {rv64_only=true}}, - {.ADDIW, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x0000001B, 0x0000707F, .I, {rv64_only=true}}, - {.SB, {.GPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00000023, 0x0000707F, .I, {}}, - {.SH, {.GPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00001023, 0x0000707F, .I, {}}, - {.SW, {.GPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00002023, 0x0000707F, .I, {}}, - {.SD, {.GPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00003023, 0x0000707F, .I, {rv64_only=true}}, - {.FSW, {.FPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00002027, 0x0000707F, .F, {}}, - {.FSD, {.FPR, .MEM, .NONE, .NONE}, {.RS2, .OFFSET_BASE_S, .NONE, .NONE}, 0x00003027, 0x0000707F, .D, {}}, - {.LR_W, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_A, .NONE, .NONE}, 0x1000202F, 0xF9F0707F, .A, {}}, - {.LR_D, {.GPR, .MEM, .NONE, .NONE}, {.RD, .OFFSET_BASE_A, .NONE, .NONE}, 0x1000302F, 0xF9F0707F, .A, {rv64_only=true}}, - {.SC_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x1800202F, 0xF800707F, .A, {}}, - {.AMOSWAP_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x0800202F, 0xF800707F, .A, {}}, - {.AMOADD_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x0000202F, 0xF800707F, .A, {}}, - {.AMOXOR_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x2000202F, 0xF800707F, .A, {}}, - {.AMOAND_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x6000202F, 0xF800707F, .A, {}}, - {.AMOOR_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x4000202F, 0xF800707F, .A, {}}, - {.AMOMIN_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x8000202F, 0xF800707F, .A, {}}, - {.AMOMAX_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xA000202F, 0xF800707F, .A, {}}, - {.AMOMINU_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xC000202F, 0xF800707F, .A, {}}, - {.AMOMAXU_W, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xE000202F, 0xF800707F, .A, {}}, - {.SC_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x1800302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOSWAP_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x0800302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOADD_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x0000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOXOR_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x2000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOAND_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x6000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOOR_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x4000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOMIN_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0x8000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOMAX_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xA000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOMINU_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xC000302F, 0xF800707F, .A, {rv64_only=true}}, - {.AMOMAXU_D, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RS2, .OFFSET_BASE_A, .NONE}, 0xE000302F, 0xF800707F, .A, {rv64_only=true}}, - {.ADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00000033, 0xFE00707F, .I, {}}, - {.SUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x40000033, 0xFE00707F, .I, {}}, - {.SLL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00001033, 0xFE00707F, .I, {}}, - {.SLT, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00002033, 0xFE00707F, .I, {}}, - {.SLTU, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00003033, 0xFE00707F, .I, {}}, - {.XOR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00004033, 0xFE00707F, .I, {}}, - {.SRL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00005033, 0xFE00707F, .I, {}}, - {.SRA, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x40005033, 0xFE00707F, .I, {}}, - {.OR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00006033, 0xFE00707F, .I, {}}, - {.AND, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00007033, 0xFE00707F, .I, {}}, - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02000033, 0xFE00707F, .M, {}}, - {.MULH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02001033, 0xFE00707F, .M, {}}, - {.MULHSU, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02002033, 0xFE00707F, .M, {}}, - {.MULHU, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02003033, 0xFE00707F, .M, {}}, - {.DIV, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02004033, 0xFE00707F, .M, {}}, - {.DIVU, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02005033, 0xFE00707F, .M, {}}, - {.REM, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02006033, 0xFE00707F, .M, {}}, - {.REMU, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02007033, 0xFE00707F, .M, {}}, - {.LUI, {.GPR, .IMM20, .NONE, .NONE}, {.RD, .IMM_U, .NONE, .NONE}, 0x00000037, 0x0000007F, .I, {}}, - {.ADDW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0000003B, 0xFE00707F, .I, {rv64_only=true}}, - {.SUBW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x4000003B, 0xFE00707F, .I, {rv64_only=true}}, - {.SLLW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0000103B, 0xFE00707F, .I, {rv64_only=true}}, - {.SRLW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0000503B, 0xFE00707F, .I, {rv64_only=true}}, - {.SRAW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x4000503B, 0xFE00707F, .I, {rv64_only=true}}, - {.MULW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0200003B, 0xFE00707F, .M, {rv64_only=true}}, - {.DIVW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0200403B, 0xFE00707F, .M, {rv64_only=true}}, - {.DIVUW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0200503B, 0xFE00707F, .M, {rv64_only=true}}, - {.REMW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0200603B, 0xFE00707F, .M, {rv64_only=true}}, - {.REMUW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0200703B, 0xFE00707F, .M, {rv64_only=true}}, - {.FMADD_S, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x00000043, 0x0600007F, .F, {fp_round=true}}, - {.FMADD_D, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x02000043, 0x0600007F, .D, {fp_round=true}}, - {.FMSUB_S, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x00000047, 0x0600007F, .F, {fp_round=true}}, - {.FMSUB_D, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x02000047, 0x0600007F, .D, {fp_round=true}}, - {.FNMSUB_S, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x0000004B, 0x0600007F, .F, {fp_round=true}}, - {.FNMSUB_D, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x0200004B, 0x0600007F, .D, {fp_round=true}}, - {.FNMADD_S, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x0000004F, 0x0600007F, .F, {fp_round=true}}, - {.FNMADD_D, {.FPR, .FPR, .FPR, .FPR}, {.RD, .RS1, .RS2, .RS3}, 0x0200004F, 0x0600007F, .D, {fp_round=true}}, - {.FADD_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x00000053, 0xFE00007F, .F, {fp_round=true}}, - {.FADD_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x02000053, 0xFE00007F, .D, {fp_round=true}}, - {.FSUB_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x08000053, 0xFE00007F, .F, {fp_round=true}}, - {.FSUB_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x0A000053, 0xFE00007F, .D, {fp_round=true}}, - {.FMUL_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x10000053, 0xFE00007F, .F, {fp_round=true}}, - {.FMUL_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x12000053, 0xFE00007F, .D, {fp_round=true}}, - {.FDIV_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x18000053, 0xFE00007F, .F, {fp_round=true}}, - {.FDIV_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x1A000053, 0xFE00007F, .D, {fp_round=true}}, - {.FSGNJ_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x20000053, 0xFE00707F, .F, {}}, - {.FSGNJN_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x20001053, 0xFE00707F, .F, {}}, - {.FSGNJX_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x20002053, 0xFE00707F, .F, {}}, - {.FSGNJ_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x22000053, 0xFE00707F, .D, {}}, - {.FSGNJN_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x22001053, 0xFE00707F, .D, {}}, - {.FSGNJX_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x22002053, 0xFE00707F, .D, {}}, - {.FMIN_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x28000053, 0xFE00707F, .F, {}}, - {.FMAX_S, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x28001053, 0xFE00707F, .F, {}}, - {.FMIN_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x2A000053, 0xFE00707F, .D, {}}, - {.FMAX_D, {.FPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0x2A001053, 0xFE00707F, .D, {}}, - {.FCVT_S_D, {.FPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0x40100053, 0xFFF0007F, .D, {fp_round=true}}, - {.FCVT_D_S, {.FPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0x42000053, 0xFFF0007F, .D, {fp_round=true}}, - {.FSQRT_S, {.FPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0x58000053, 0xFFF0007F, .F, {fp_round=true}}, - {.FSQRT_D, {.FPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0x5A000053, 0xFFF0007F, .D, {fp_round=true}}, - {.FEQ_S, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA0002053, 0xFE00707F, .F, {}}, - {.FLT_S, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA0001053, 0xFE00707F, .F, {}}, - {.FLE_S, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA0000053, 0xFE00707F, .F, {}}, - {.FEQ_D, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA2002053, 0xFE00707F, .D, {}}, - {.FLT_D, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA2001053, 0xFE00707F, .D, {}}, - {.FLE_D, {.GPR, .FPR, .FPR, .NONE}, {.RD, .RS1, .RS2, .NONE}, 0xA2000053, 0xFE00707F, .D, {}}, - {.FCVT_W_S, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC0000053, 0xFFF0007F, .F, {fp_round=true}}, - {.FCVT_WU_S, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC0100053, 0xFFF0007F, .F, {fp_round=true}}, - {.FCVT_L_S, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true}}, - {.FCVT_LU_S, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true}}, - {.FCVT_W_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC2000053, 0xFFF0007F, .D, {fp_round=true}}, - {.FCVT_WU_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC2100053, 0xFFF0007F, .D, {fp_round=true}}, - {.FCVT_L_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true}}, - {.FCVT_LU_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xC2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true}}, - {.FCVT_S_W, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD0000053, 0xFFF0007F, .F, {fp_round=true}}, - {.FCVT_S_WU, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD0100053, 0xFFF0007F, .F, {fp_round=true}}, - {.FCVT_S_L, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true}}, - {.FCVT_S_LU, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true}}, - {.FCVT_D_W, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD2000053, 0xFFF0007F, .D, {fp_round=true}}, - {.FCVT_D_WU, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD2100053, 0xFFF0007F, .D, {fp_round=true}}, - {.FCVT_D_L, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true}}, - {.FCVT_D_LU, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xD2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true}}, - {.FMV_X_W, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xE0000053, 0xFFF0707F, .F, {}}, - {.FCLASS_S, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xE0001053, 0xFFF0707F, .F, {}}, - {.FCLASS_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xE2001053, 0xFFF0707F, .D, {}}, - {.FMV_X_D, {.GPR, .FPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xE2000053, 0xFFF0707F, .D, {rv64_only=true}}, - {.FMV_W_X, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xF0000053, 0xFFF0707F, .F, {}}, - {.FMV_D_X, {.FPR, .GPR, .NONE, .NONE}, {.RD, .RS1, .NONE, .NONE}, 0xF2000053, 0xFFF0707F, .D, {rv64_only=true}}, - {.BEQ, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00000063, 0x0000707F, .I, {branch=true}}, - {.BNE, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00001063, 0x0000707F, .I, {branch=true}}, - {.BLT, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00004063, 0x0000707F, .I, {branch=true}}, - {.BGE, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00005063, 0x0000707F, .I, {branch=true}}, - {.BLTU, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00006063, 0x0000707F, .I, {branch=true}}, - {.BGEU, {.GPR, .GPR, .REL13, .NONE}, {.RS1, .RS2, .IMM_B, .NONE}, 0x00007063, 0x0000707F, .I, {branch=true}}, - {.JALR, {.GPR, .GPR, .IMM12, .NONE}, {.RD, .RS1, .IMM_I, .NONE}, 0x00000067, 0x0000707F, .I, {branch=true}}, - {.JAL, {.GPR, .REL21, .NONE, .NONE}, {.RD, .IMM_J, .NONE, .NONE}, 0x0000006F, 0x0000007F, .I, {branch=true}}, - {.ECALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00000073, 0xFFFFFFFF, .I, {branch=true}}, - {.EBREAK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00100073, 0xFFFFFFFF, .I, {branch=true}}, - {.CSRRW, {.GPR, .CSR, .GPR, .NONE}, {.RD, .CSR_FIELD, .RS1, .NONE}, 0x00001073, 0x0000707F, .ZICSR, {}}, - {.CSRRS, {.GPR, .CSR, .GPR, .NONE}, {.RD, .CSR_FIELD, .RS1, .NONE}, 0x00002073, 0x0000707F, .ZICSR, {}}, - {.CSRRC, {.GPR, .CSR, .GPR, .NONE}, {.RD, .CSR_FIELD, .RS1, .NONE}, 0x00003073, 0x0000707F, .ZICSR, {}}, - {.CSRRWI, {.GPR, .CSR, .ZIMM5, .NONE}, {.RD, .CSR_FIELD, .ZIMM_FIELD, .NONE}, 0x00005073, 0x0000707F, .ZICSR, {}}, - {.CSRRSI, {.GPR, .CSR, .ZIMM5, .NONE}, {.RD, .CSR_FIELD, .ZIMM_FIELD, .NONE}, 0x00006073, 0x0000707F, .ZICSR, {}}, - {.CSRRCI, {.GPR, .CSR, .ZIMM5, .NONE}, {.RD, .CSR_FIELD, .ZIMM_FIELD, .NONE}, 0x00007073, 0x0000707F, .ZICSR, {}}, - {.C_ADDI4SPN, {.GPR_C, .GPR_SP, .IMM_C8U, .NONE}, {.C_RD_PRIMED, .NONE, .C_IMM_CIW, .NONE}, 0x00000000, 0x0000E003, .C, {}}, - {.C_NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00000001, 0x0000FFFF, .C, {}}, - {.C_ADDI, {.GPR_NONZERO, .IMM_C6S, .NONE, .NONE}, {.C_RD_RS1, .C_IMM_CI_S, .NONE, .NONE}, 0x00000001, 0x0000E003, .C, {}}, - {.C_SLLI, {.GPR_NONZERO, .IMM_C6U, .NONE, .NONE}, {.C_RD_RS1, .C_IMM_CI_U, .NONE, .NONE}, 0x00000002, 0x0000E003, .C, {}}, - {.C_FLD, {.FPR_C, .MEM_C_D, .NONE, .NONE}, {.C_RD_PRIMED, .C_OFFSET_BASE_D, .NONE, .NONE}, 0x00002000, 0x0000E003, .D, {}}, - {.C_ADDIW, {.GPR_NONZERO, .IMM_C6S, .NONE, .NONE}, {.C_RD_RS1, .C_IMM_CI_S, .NONE, .NONE}, 0x00002001, 0x0000E003, .C, {rv64_only=true}}, - {.C_JAL, {.REL12, .NONE, .NONE, .NONE}, {.C_BRANCH12, .NONE, .NONE, .NONE}, 0x00002001, 0x0000E003, .C, {rv32_only=true, branch=true}}, - {.C_FLDSP, {.FPR, .MEM_C_SP_D, .NONE, .NONE}, {.C_RD_RS1, .C_SP_OFFSET_D, .NONE, .NONE}, 0x00002002, 0x0000E003, .D, {}}, - {.C_LW, {.GPR_C, .MEM_C_W, .NONE, .NONE}, {.C_RD_PRIMED, .C_OFFSET_BASE_W, .NONE, .NONE}, 0x00004000, 0x0000E003, .C, {}}, - {.C_LI, {.GPR_NONZERO, .IMM_C6S, .NONE, .NONE}, {.C_RD_RS1, .C_IMM_CI_S, .NONE, .NONE}, 0x00004001, 0x0000E003, .C, {}}, - {.C_LWSP, {.GPR_NONZERO, .MEM_C_SP_W, .NONE, .NONE}, {.C_RD_RS1, .C_SP_OFFSET_W, .NONE, .NONE}, 0x00004002, 0x0000E003, .C, {}}, - {.C_LD, {.GPR_C, .MEM_C_D, .NONE, .NONE}, {.C_RD_PRIMED, .C_OFFSET_BASE_D, .NONE, .NONE}, 0x00006000, 0x0000E003, .C, {rv64_only=true}}, - {.C_ADDI16SP, {.GPR_SP, .IMM_C10S, .NONE, .NONE}, {.NONE, .C_IMM_ADDI16SP, .NONE, .NONE}, 0x00006101, 0x0000EF83, .C, {}}, - {.C_LUI, {.GPR_NONZERO, .IMM_C18S, .NONE, .NONE}, {.C_RD_RS1, .C_IMM_LUI, .NONE, .NONE}, 0x00006001, 0x0000E003, .C, {}}, - {.C_LDSP, {.GPR_NONZERO, .MEM_C_SP_D, .NONE, .NONE}, {.C_RD_RS1, .C_SP_OFFSET_D, .NONE, .NONE}, 0x00006002, 0x0000E003, .C, {rv64_only=true}}, - {.C_SUB, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00008C01, 0x0000FC63, .C, {}}, - {.C_XOR, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00008C21, 0x0000FC63, .C, {}}, - {.C_OR, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00008C41, 0x0000FC63, .C, {}}, - {.C_AND, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00008C61, 0x0000FC63, .C, {}}, - {.C_SUBW, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00009C01, 0x0000FC63, .C, {rv64_only=true}}, - {.C_ADDW, {.GPR_C, .GPR_C, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_RS2_PRIMED, .NONE, .NONE}, 0x00009C21, 0x0000FC63, .C, {rv64_only=true}}, - {.C_SRLI, {.GPR_C, .IMM_C6U, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_IMM_CI_U, .NONE, .NONE}, 0x00008001, 0x0000EC03, .C, {}}, - {.C_SRAI, {.GPR_C, .IMM_C6U, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_IMM_CI_U, .NONE, .NONE}, 0x00008401, 0x0000EC03, .C, {}}, - {.C_ANDI, {.GPR_C, .IMM_C6S, .NONE, .NONE}, {.C_RD_RS1_PRIMED, .C_IMM_CI_S, .NONE, .NONE}, 0x00008801, 0x0000EC03, .C, {}}, - {.C_EBREAK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00009002, 0x0000FFFF, .C, {}}, - {.C_JR, {.GPR_NONZERO, .NONE, .NONE, .NONE}, {.C_RD_RS1, .NONE, .NONE, .NONE}, 0x00008002, 0x0000F07F, .C, {branch=true}}, - {.C_JALR, {.GPR_NONZERO, .NONE, .NONE, .NONE}, {.C_RD_RS1, .NONE, .NONE, .NONE}, 0x00009002, 0x0000F07F, .C, {branch=true}}, - {.C_MV, {.GPR_NONZERO, .GPR_NONZERO, .NONE, .NONE}, {.C_RD_RS1, .C_RS2, .NONE, .NONE}, 0x00008002, 0x0000F003, .C, {}}, - {.C_ADD, {.GPR_NONZERO, .GPR_NONZERO, .NONE, .NONE}, {.C_RD_RS1, .C_RS2, .NONE, .NONE}, 0x00009002, 0x0000F003, .C, {}}, - {.C_FSD, {.FPR_C, .MEM_C_D, .NONE, .NONE}, {.C_RS2_PRIMED, .C_OFFSET_BASE_D, .NONE, .NONE}, 0x0000A000, 0x0000E003, .D, {}}, - {.C_J, {.REL12, .NONE, .NONE, .NONE}, {.C_BRANCH12, .NONE, .NONE, .NONE}, 0x0000A001, 0x0000E003, .C, {branch=true}}, - {.C_FSDSP, {.FPR, .MEM_C_SP_D, .NONE, .NONE}, {.C_RS2, .C_IMM_CSS_D, .NONE, .NONE}, 0x0000A002, 0x0000E003, .D, {}}, - {.C_SW, {.GPR_C, .MEM_C_W, .NONE, .NONE}, {.C_RS2_PRIMED, .C_OFFSET_BASE_W, .NONE, .NONE}, 0x0000C000, 0x0000E003, .C, {}}, - {.C_BEQZ, {.GPR_C, .REL9, .NONE, .NONE}, {.C_RS1_PRIMED, .C_BRANCH9, .NONE, .NONE}, 0x0000C001, 0x0000E003, .C, {branch=true}}, - {.C_SWSP, {.GPR, .MEM_C_SP_W, .NONE, .NONE}, {.C_RS2, .C_IMM_CSS_W, .NONE, .NONE}, 0x0000C002, 0x0000E003, .C, {}}, - {.C_SD, {.GPR_C, .MEM_C_D, .NONE, .NONE}, {.C_RS2_PRIMED, .C_OFFSET_BASE_D, .NONE, .NONE}, 0x0000E000, 0x0000E003, .C, {rv64_only=true}}, - {.C_BNEZ, {.GPR_C, .REL9, .NONE, .NONE}, {.C_RS1_PRIMED, .C_BRANCH9, .NONE, .NONE}, 0x0000E001, 0x0000E003, .C, {branch=true}}, - {.C_SDSP, {.GPR, .MEM_C_SP_D, .NONE, .NONE}, {.C_RS2, .C_IMM_CSS_D, .NONE, .NONE}, 0x0000E002, 0x0000E003, .C, {rv64_only=true}}, -} - -@(rodata) -DECODE_INDEX_OPCODE := [128]Decode_Index{ - 0x03 = {0, 7}, - 0x07 = {7, 2}, - 0x0F = {9, 2}, - 0x13 = {11, 9}, - 0x17 = {20, 1}, - 0x1B = {21, 4}, - 0x23 = {25, 4}, - 0x27 = {29, 2}, - 0x2F = {31, 22}, - 0x33 = {53, 18}, - 0x37 = {71, 1}, - 0x3B = {72, 10}, - 0x43 = {82, 2}, - 0x47 = {84, 2}, - 0x4B = {86, 2}, - 0x4F = {88, 2}, - 0x53 = {90, 50}, - 0x63 = {140, 6}, - 0x67 = {146, 1}, - 0x6F = {147, 1}, - 0x73 = {148, 8}, -} - -@(rodata) -DECODE_INDEX_OP_FP := [128]Decode_Index{ - 0x00 = {90, 1}, - 0x01 = {91, 1}, - 0x04 = {92, 1}, - 0x05 = {93, 1}, - 0x08 = {94, 1}, - 0x09 = {95, 1}, - 0x0C = {96, 1}, - 0x0D = {97, 1}, - 0x10 = {98, 3}, - 0x11 = {101, 3}, - 0x14 = {104, 2}, - 0x15 = {106, 2}, - 0x20 = {108, 1}, - 0x21 = {109, 1}, - 0x2C = {110, 1}, - 0x2D = {111, 1}, - 0x50 = {112, 3}, - 0x51 = {115, 3}, - 0x60 = {118, 4}, - 0x61 = {122, 4}, - 0x68 = {126, 4}, - 0x69 = {130, 4}, - 0x70 = {134, 2}, - 0x71 = {136, 2}, - 0x78 = {138, 1}, - 0x79 = {139, 1}, -} - -@(rodata) -DECODE_INDEX_RVC := [32]Decode_Index{ - 0x00 = {156, 1}, - 0x01 = {157, 2}, - 0x02 = {159, 1}, - 0x04 = {160, 1}, - 0x05 = {161, 2}, - 0x06 = {163, 1}, - 0x08 = {164, 1}, - 0x09 = {165, 1}, - 0x0A = {166, 1}, - 0x0C = {167, 1}, - 0x0D = {168, 2}, - 0x0E = {170, 1}, - 0x11 = {171, 9}, - 0x12 = {180, 5}, - 0x14 = {185, 1}, - 0x15 = {186, 1}, - 0x16 = {187, 1}, - 0x18 = {188, 1}, - 0x19 = {189, 1}, - 0x1A = {190, 1}, - 0x1C = {191, 1}, - 0x1D = {192, 1}, - 0x1E = {193, 1}, -} - diff --git a/core/rexcode/riscv/encoder.odin b/core/rexcode/riscv/encoder.odin index 461d47ef5..f0424d0ce 100644 --- a/core/rexcode/riscv/encoder.odin +++ b/core/rexcode/riscv/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= @@ -118,7 +120,7 @@ encode_one_inline :: #force_inline proc( return 0, 0, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, 0, false diff --git a/core/rexcode/riscv/encoding_types.odin b/core/rexcode/riscv/encoding_types.odin index e17a231b7..bc8f04d24 100644 --- a/core/rexcode/riscv/encoding_types.odin +++ b/core/rexcode/riscv/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv import "../isa" diff --git a/core/rexcode/riscv/instructions.odin b/core/rexcode/riscv/instructions.odin index ec73b59e0..ccc5e8123 100644 --- a/core/rexcode/riscv/instructions.odin +++ b/core/rexcode/riscv/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= diff --git a/core/rexcode/riscv/mnemonics.odin b/core/rexcode/riscv/mnemonics.odin index a2d2b868d..adf5effb4 100644 --- a/core/rexcode/riscv/mnemonics.odin +++ b/core/rexcode/riscv/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= diff --git a/core/rexcode/riscv/operands.odin b/core/rexcode/riscv/operands.odin index 7959540f1..2a244a5f1 100644 --- a/core/rexcode/riscv/operands.odin +++ b/core/rexcode/riscv/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= diff --git a/core/rexcode/riscv/printer.odin b/core/rexcode/riscv/printer.odin index 15a122224..9a8f1cb1f 100644 --- a/core/rexcode/riscv/printer.odin +++ b/core/rexcode/riscv/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv import "core:strings" diff --git a/core/rexcode/riscv/registers.odin b/core/rexcode/riscv/registers.odin index fb62e191d..485eebcd9 100644 --- a/core/rexcode/riscv/registers.odin +++ b/core/rexcode/riscv/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= diff --git a/core/rexcode/riscv/reloc.odin b/core/rexcode/riscv/reloc.odin index 774349d8e..ccac4989a 100644 --- a/core/rexcode/riscv/reloc.odin +++ b/core/rexcode/riscv/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv // ============================================================================= diff --git a/core/rexcode/riscv/encoding_table.odin b/core/rexcode/riscv/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/riscv/encoding_table.odin rename to core/rexcode/riscv/tablegen/encoding_table.odin index 90423a28f..0b9eb9d41 100644 --- a/core/rexcode/riscv/encoding_table.odin +++ b/core/rexcode/riscv/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_riscv +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_riscv_tablegen // ============================================================================= // RISC-V ENCODING_TABLE diff --git a/core/rexcode/riscv/tablegen/gen.odin b/core/rexcode/riscv/tablegen/gen.odin new file mode 100644 index 000000000..76e8270d0 --- /dev/null +++ b/core/rexcode/riscv/tablegen/gen.odin @@ -0,0 +1,348 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_riscv_tablegen + +// ============================================================================= +// RISC-V TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + OPCODE / OP_FP / RVC index tables +// generated/writer.odin Stage B: serialize those globals to ../../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run riscv/tablegen # Stage A +// odin run riscv/tablegen/generated # Stage B +// +// Decode dispatch (ported from the old tools/gen_decode_tables.odin): +// primary opcode (bits 6-0) -> DECODE_INDEX_OPCODE [128] +// opcode 0x53 OP-FP -> by funct7 -> DECODE_INDEX_OP_FP [128] +// compressed (RVC, 2-byte) words -> DECODE_INDEX_RVC [32] +// keyed by (op[1:0] | funct3[15:13]<<2) + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +// The SoT's bit/mask literals reference these field-mask constants. +MASK_OPCODE :: lib.MASK_OPCODE +MASK_RD :: lib.MASK_RD +MASK_FUNCT3 :: lib.MASK_FUNCT3 +MASK_RS1 :: lib.MASK_RS1 +MASK_RS2 :: lib.MASK_RS2 +MASK_FUNCT7 :: lib.MASK_FUNCT7 +MASK_IMM_I :: lib.MASK_IMM_I +MASK_SHAMT5 :: lib.MASK_SHAMT5 +MASK_SHAMT6 :: lib.MASK_SHAMT6 +MASK_R :: lib.MASK_R +MASK_I :: lib.MASK_I +MASK_I_SHIFT :: lib.MASK_I_SHIFT +MASK_S :: lib.MASK_S +MASK_B :: lib.MASK_B +MASK_U :: lib.MASK_U +MASK_J :: lib.MASK_J + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "riscv.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "riscv.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "riscv.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_OPCODE", "riscv.idx_opcode.bin", "Decode_Index"}, + {"DECODE_INDEX_OP_FP", "riscv.idx_op_fp.bin", "Decode_Index"}, + {"DECODE_INDEX_RVC", "riscv.idx_rvc.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + flags: lib.Encoding_Flags, + primary_op: u8, + sub_key: u8, // funct7 for opcode 0x53 + is_rvc: bool, // 2-byte compressed instruction + rvc_key: u8, // RVC dispatch key: (op[1:0] | funct3[15:13]<<2), 5 bits +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("riscv tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_riscv_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f in ENCODING_TABLE[m] { + e := Entry{ + mnemonic = f.mnemonic, + ops = f.ops, + enc = f.enc, + bits = f.bits, + mask = f.mask, + feature = f.feature, + flags = f.flags, + is_rvc = lib.inst_size_from_bits(f.bits) == 2, + } + if e.is_rvc { + // RVC: 5-bit dispatch (op[1:0] + funct3[15:13]<<2). + e.rvc_key = u8((f.bits & 0x3) | ((f.bits >> 13) & 0x7) << 2) + } else { + e.primary_op = u8(f.bits & 0x7F) + if e.primary_op == 0x53 { + e.sub_key = u8((f.bits >> 25) & 0x7F) + } + } + append(&all, e) + } + } + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.is_rvc != b.is_rvc { return !a.is_rvc } // non-RVC first + if a.is_rvc { + if a.rvc_key != b.rvc_key { return a.rvc_key < b.rvc_key } + } else { + if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } + if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } + } + ac := bits.count_ones(a.mask) + bc := bits.count_ones(b.mask) + if ac != bc { return ac > bc } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + primary_idx: [128]Range + op_fp_idx: [128]Range + rvc_idx: [32]Range + for e, i in all { + if e.is_rvc { + push(&rvc_idx[e.rvc_key], u16(i)) + } else { + push(&primary_idx[e.primary_op], u16(i)) + if e.primary_op == 0x53 { + push(&op_fp_idx[e.sub_key], u16(i)) + } + } + } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_riscv_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by primary opcode / funct7 / RVC key.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_OPCODE", primary_idx[:]) + emit_range(&sb, "DECODE_INDEX_OP_FP", op_fp_idx[:]) + emit_range(&sb, "DECODE_INDEX_RVC", rvc_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting (compact, matching riscv's original generator) +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.rv32_only { append(&parts, "rv32_only=true") } + if f.rv64_only { append(&parts, "rv64_only=true") } + if f.branch { append(&parts, "branch=true") } + if f.fp_round { append(&parts, "fp_round=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_riscv_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_riscv\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "riscv.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "riscv.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "riscv.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "riscv.idx_opcode.bin", raw(&DECODE_INDEX_OPCODE, size_of(DECODE_INDEX_OPCODE))) + w(TABLES + "riscv.idx_op_fp.bin", raw(&DECODE_INDEX_OP_FP, size_of(DECODE_INDEX_OP_FP))) + w(TABLES + "riscv.idx_rvc.bin", raw(&DECODE_INDEX_RVC, size_of(DECODE_INDEX_RVC))) +} diff --git a/core/rexcode/riscv/tables.odin b/core/rexcode/riscv/tables.odin new file mode 100644 index 000000000..de5093efc --- /dev/null +++ b/core/rexcode/riscv/tables.odin @@ -0,0 +1,64 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_riscv + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/riscv.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/riscv.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/riscv.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_OPCODE := #load("tables/riscv.idx_opcode.bin", []Decode_Index) +@(rodata) DECODE_INDEX_OP_FP := #load("tables/riscv.idx_op_fp.bin", []Decode_Index) +@(rodata) DECODE_INDEX_RVC := #load("tables/riscv.idx_rvc.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/riscv/tables/riscv.encode_forms.bin b/core/rexcode/riscv/tables/riscv.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..d943520d4daff806c95494515875384ba8068eb0 GIT binary patch literal 3880 zcmZQ%U}R@tVB}(8FlS(3sAm8HCb*b5T#T84k&}Uek(+@bA121a!obML%)rRR&X5ig zD_~$?U}0roWaMCAV&-H>hKsQw!~_@^>cQ&R5n>K7F%E=S08ES%A(j9W<3flPz{I%0 zeqiKbU|@#X%fN#WgW1c#ix5+Q>Sf?Vh{4>#z>g4vxrIRhEXK^sz@QAbLl7Ybw?haa z2Dd{PECzNT%pXi52r&bwTbM+_VqiPqVq)-c7KYm^ju3;}A%PHs>1B{ah{63Pg%E?e zg+Ur21`AUL83sm1HU>r}HU?pc-~KQ#$Rflb;qr%pK@M5Wp}v6O4+Dcd+&pQRo0$|C z7#Ud^7@1fZq#@@0V_;H5h(XNz$H1h7ECw>~9|Myz10y3N10xeNgE7Rse+&#N$YKz6 z45|n*m>mpi2r)=l{bOKIM~Fef>K_Ax20{!HR{t0nG!bGj_c3T8i$U$xMu6!TiBwfDnVZg~BryT7ItCUq21ag121b4+hGK|Y z7+4w15n_-qWng8nK!`!Yl!2AOl7W$%kAab2fT0-TW(HOUD})#%tQc4stPx_6uwr0k zuz~x{n1O+*zJTE$BZDnMOaLZkhY(YMiP3}9jo2r&nkm?J_g04C;y5KDlGIU~dh zU}7$CF>9Fnm|PKJFguvs5MnSpnA{O!Fgut$5MnSpm^{Jd0V5v+gT4ZTKz+f7pG*v1 z42+Ci42;ZtATf#h0)`(<4Bp6M91t-dWHC^=`-6$W7gCzNSq$PgrYK}Fh~Jo^k;Nc>V~Rl*gZPap7Fi79H>NmbF^J!o;u)B@7#Kk1 zJv%giFf$~8#Xx1dI$SJ~fr*KUiIIt!#Tk@W85r1@Ig;RF?r^bWxR^IwECnv+4;M=X ziGj<>V2Id1W{xyuF^+l$hJVZ)>BwRN5U~toF$suRCIb@_0|O%y14A$aLqt8phyTnR zS;*=@;rx%8AsZnkzyKA?L5L~9#Bvd03=A5eJk89IhY%BhiRFXsgxY%mVs8PGm;h9) z5J`;TL4Co8|I7?U42(=nkT6hS0L9xsW`<&fm;g+y1R=%%6DviSCjc|AjDd*}9tIa6 zZYf6+6M%|UAc--2fVia+VIG45#LZk)NMZ(1v1%l}3J~+SYLLVXpklS)Gz3mp&@z^V zp$;qtPFHZTdQh0c(iKxZ0|OfiM+02U9aLU{#Twya-f*!dxR^g&tQjN*2~&vJKNgM_ zWHByKdST&cMHUl+h_xY$NkPQgk<(QaC`?&6I*`>Vfzk#GLnlH^fB`Djg%DGKiFG5y z7#Or5dV3IJ0x+>&BzpxMAolhli7_}q#QG6wLxEut#JmXzF#(v^M1&XvOl%S&egzmF zfzkmB!(@aQ1H&PR9aE6R1fXJ5k>Z@;5=7lJBryS~*mNYl3J|?qGmyj#pkgzT^eRB~ za?L^#Gk}WCM$!v)Gt(R-bqt@t{$QF5Zyzv%+YAg0>GOTl7bbqio(%NPWO85l&R85lrrhS<9tAqLgU&a?s{26x{| z20?KK22nW%21c0s7*;U|h%tbgxD1Sm3=GZhL4I4!z%RnUASJ`Vz}UdR!2AXzwgw^A z0ux)yz%R_eAO&(u2TW`o13y0lgOnr#17i;ZL-HSx-t}-XMYz}oxR@hcY$IGO5iYg~ zF2*#5>1PfE9-3*K} z3=Col3=B*#I~evbFv>D8h$%8KFv09#+RMNM(+hPU3&TFJ7+4+DA1n;}83Y*^7(^Ku s7?>Iu80tSTFtD>6K!{C%i5+AR6l7o!6@#c_2B~8>gbt(wtD53rcfCX&xxe3#Iv>G(VIUfYO3c zS_n!DLunBxEefT@ptLxYmVnZdP+AH~OG9ZHC@l-6<)E}YlvaS!icne!N-INY6)3F= zrPZLcI+WIc(wb0O3rcH4X&or73#Ij-v_6zJfYOFg+6YP;LunHzZ3?B$ptL!Zwt&)> zP}&MgTSI9ZC~XU+?Vz+hly-p9j!@bON;^Yo7bxutrQM*kJCyc-(witC>;x>!5T!lx~31jZnG?N;gC47AV~crQ4u%JCyE# z(w$Jc3rcrG=^iNE3#I#@bU&1y0Hr5F=}Ay}GL)VIrKdvaX;6APl%4^lXF};&PdOnn10Hqf~=|xa_F_c~crI$kKWl(xKlwJX)S3>DkPcQcS7l1PNcoAX>Ffl%am;+3VA0ZY16B9;=B|ycP zL=a*IFtK{Ac)FQ;7>R1?zL5>7tegOuC|NsC0XJas8;Nf9l5ENoy;D`G| zhJlfhje(JgjX@aVk3S3yvIsGV`~EO6$RUe4)E6-PVPFtrU}R)wU}R!v5Qdv4ju3;o zkAXn~AqI6H1A`<&3?4302r*a~Fi0cB3ZP-Yz{J4F&HxS@age=WUn(##GO{u-GO;p9 zL;UfNfk_b|2Jy!~1|}tBF_1t0F)+!)?T`kU2Z~=N0kHYZybKJ=Ffj%}gc!sQ1_lNp zgc#hvq6jgVf0+`%aRf3?9jcC*p$;JiRmZ~M3D(QV$H1Vkz#vdx@Zl#DLkL3504m1h z#lXnO#lXnS2T~_dU%>E#iNPCLi~}O(gDeJ0yFZv1e38WzAnN>(#S$Q5{>WmWu=>Ho z5P&S!08tl+EVck57KAKz03sHQEcO5*7K#uvV1W38DGXT*;t!^9WHE?8m?DtHApT&A zL>7bigDDDG4B`)_Xk;;nKbT^W#UTD*ibWQK_=719Sq$P2CS?XjMn(okCT4KXt1n>q z$H1V1EC#ao9|MCbLJX3I{xLA9A;chQ;~xWqIzkMRHvTa%XduKOdFCGjgC;@@mc|*h zkj0?(Y9quTdFvkogAPIrlDGabFxVi(7#Ns9{$OOVMTiN&#Ox4a3NSHygqQ(L%mE?h z026aWhy}pJoDgCOFfnI@SOH9o5uW$WLHQD#_jTdwtU+R+uxHXk7K4NVlRiQW7WPaA z2r*drF&QF@LG`*I#9-mVB*wy#jw~hs5@Y6QMHUkRiLr2G zAd5+W#F#nSkj11xVk{h4$YP-K;2$$XHbP8*0Vq3Yrz{GM9Vhju#Aic~Cc?dB9m{>PLjDbN5q>hE52O%Z^6YFJQVq#!mWMW_lW)N_w zXZY}+g`*EijKK*amWeDD0TN^8Xh#-{0*SG36frO|F+t)@fdN#m{bOb*Mu-W(#7Yoi z3^1{NgqQ-uB8ZzOAjAYj$YPH`>R1?NBg7aOAYx1vNOmxM0I6eUn1d|#2_(kC#LB?P$icwG%*l`p%IBc= z5DObZ3{rM7FtD&A#31z%0|N^OLJU%#GBB`kBE%qd4+8@W7eWkD_b@Q9u)y14>2Q0Q z85lVk7#O)381g}4pz@x@1Vn;yF$1J+%fMm^=7Wf01_5w;mx0BMfsvb$fsvnyp&06B zRt9r~7^JRcU}dmCh(YRF237`321af^21b4XhGM8cSQ)GkVo-muGFT(Tp#ETGn9sm3 zAj%-lAPaI11M>q026l$IU^a+g1iKj|wv0hgn1Ml5nt=f%22rxH#5>1Qlap zSirz9#lRr0#=yYf05Ol9VFkiGxY$kxK^X=HQ4IzLCb-x_27Z`Z5}OF)%R5 zGcYhFGB7m12l;I!gP=GAgQy$>10zfw!!8Cvm|I|COzRl<`573bBpDbOdl(p!|A6$a zhl?q~#Wujj9N}Uc;bMt!u}yF>#yL>)m^Q=36yaj48TdsQ7^Gwv7#JHE7?|IH>|KKp zYk`TaW#AWPV2}dEQ3p(H9w-{Ym}vqi{ekrEXAopyU=U?sU|?!sV5tAVz`)LO03kL3 zCU%fPP>_K^R1Bhy8KjQk5JGGM0|P{CDLBq0L2|pFyNiL5p&L(l0RX*d3uFKQ literal 0 HcmV?d00001 diff --git a/core/rexcode/riscv/tables/riscv.idx_opcode.bin b/core/rexcode/riscv/tables/riscv.idx_opcode.bin new file mode 100644 index 0000000000000000000000000000000000000000..ed0bf4dd258af91bcfa4f25d746f8d57cd17fd27 GIT binary patch literal 512 zcmZQT0qkfzCKNt8hm!$So|}OaMTrOlBMM)Xfdz$+&XGiumqjxlUA;Vm7>bZ7gAfYe z9nF3Z1}+qNbWRYOeIaQ4Ff@Jy8b6A`2;E4M_&p44DC#GnxgSN6fq`K%n*0<74s<01 F`2dF01?>O; literal 0 HcmV?d00001 diff --git a/core/rexcode/riscv/tables/riscv.idx_rvc.bin b/core/rexcode/riscv/tables/riscv.idx_rvc.bin new file mode 100644 index 0000000000000000000000000000000000000000..eb8429c0a24b6efc7125d108e9e3948b6dc7865b GIT binary patch literal 128 zcmbQkz{oI{fr(*010w?nEMQ<{SjfP{uo%i;!obL|l!1|98I-@AfstVa0~5n4C?BL} vH3KKZ76w)jlVK+VBf~BRMuy!``8^Db40{`xzJ+4lpn>9E9=#3qTLg literal 0 HcmV?d00001 diff --git a/core/rexcode/riscv/tests/pipeline_smoke.odin b/core/rexcode/riscv/tests/pipeline_smoke.odin index aeba4f8a3..18434bc58 100644 --- a/core/rexcode/riscv/tests/pipeline_smoke.odin +++ b/core/rexcode/riscv/tests/pipeline_smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv_tests // End-to-end RISC-V pipeline tests: encode -> decode -> print across diff --git a/core/rexcode/riscv/tests/smoke.odin b/core/rexcode/riscv/tests/smoke.odin index bea566a53..ee15de0ac 100644 --- a/core/rexcode/riscv/tests/smoke.odin +++ b/core/rexcode/riscv/tests/smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_riscv_tests // Spot-check ENCODING_TABLE entries against the canonical bit/mask @@ -15,7 +17,8 @@ import rv "../" @(private="file") check :: proc(name: string, m: rv.Mnemonic, want_bits, want_mask: u32) { - encs := rv.ENCODING_TABLE[m] + _run := rv.ENCODE_RUNS[u16(m)] + encs := rv.ENCODE_FORMS[_run.start:][:_run.count] if len(encs) == 0 { fmt.printfln(" [FAIL] %s: no encoding", name) failures += 1 diff --git a/core/rexcode/riscv/tools/dump_verify_input.odin b/core/rexcode/riscv/tools/dump_verify_input.odin index e8c871b95..9b197feb5 100644 --- a/core/rexcode/riscv/tools/dump_verify_input.odin +++ b/core/rexcode/riscv/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -29,7 +31,8 @@ main :: proc() { count := 0 for mn in r.Mnemonic { - for f in r.ENCODING_TABLE[mn] { + _run := r.ENCODE_RUNS[u16(mn)] + for f in r.ENCODE_FORMS[_run.start:][:_run.count] { size := r.inst_size_from_bits(f.bits) b0 := u8( f.bits & 0xFF) b1 := u8((f.bits >> 8) & 0xFF) @@ -41,7 +44,7 @@ main :: proc() { fmt.sbprintf(&hex_buf, "0x%02x,0x%02x,0x%02x,0x%02x\n", b0, b1, b2, b3) } fmt.sbprintf(&meta_buf, "%v\t%08x\t%08x\t%v\t%d\n", - mn, f.bits, f.mask, f.ext, size) + mn, f.bits, f.mask, f.feature, size) count += 1 } } diff --git a/core/rexcode/riscv/tools/gen_decode_tables.odin b/core/rexcode/riscv/tools/gen_decode_tables.odin deleted file mode 100644 index b21842b7c..000000000 --- a/core/rexcode/riscv/tools/gen_decode_tables.odin +++ /dev/null @@ -1,220 +0,0 @@ -package main - -// ============================================================================= -// RISC-V DECODE-TABLE GENERATOR -// ============================================================================= -// -// Two-level dispatch: -// -// primary opcode (bits 6-0) -> DECODE_INDEX_OPCODE [128] -// opcode 0x53 OP-FP -> by funct7 -> DECODE_INDEX_OP_FP [128] -// -// 0x53 is the densest bucket (~40 entries: every F + D arithmetic / -// conversion / FMV / FCLASS / FEQ-FLT-FLE). Sub-bucketing by funct7 -// brings the inner linear scan down to <= 3 candidates. -// -// All other primary opcodes have <= 22 entries; linear scan within the -// primary bucket is fine. Entries within a bucket are sorted by mask- -// popcount descending so the most-specific encoding form is matched first. -// -// Run with: cd riscv && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import rv "../" - -Entry :: struct { - mnemonic: rv.Mnemonic, - ops: [4]rv.Operand_Type, - enc: [4]rv.Operand_Encoding, - bits: u32, - mask: u32, - feature: rv.Feature, - flags: rv.Encoding_Flags, - primary_op: u8, - sub_key: u8, // funct7 for opcode 0x53 - is_rvc: bool, // 2-byte compressed instruction - rvc_key: u8, // RVC dispatch key: (op[1:0] | funct3[15:13]<<2), 5 bits -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating RISC-V decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mn in rv.Mnemonic { - for f in rv.ENCODING_TABLE[mn] { - ilen := rv.inst_size_from_bits(f.bits) - e := Entry{ - mnemonic = mn, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - flags = f.flags, - is_rvc = ilen == 2, - } - if e.is_rvc { - // RVC: 5-bit dispatch (op[1:0] + funct3[15:13]<<2). - e.rvc_key = u8((f.bits & 0x3) | ((f.bits >> 13) & 0x7) << 2) - } else { - e.primary_op = u8(f.bits & 0x7F) - if e.primary_op == 0x53 { - e.sub_key = u8((f.bits >> 25) & 0x7F) - } - } - append(&all, e) - } - } - - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.is_rvc != b.is_rvc { return !a.is_rvc } // non-RVC first - if a.is_rvc { - if a.rvc_key != b.rvc_key { return a.rvc_key < b.rvc_key } - } else { - if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } - if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } - } - ac := bits.count_ones(a.mask) - bc := bits.count_ones(b.mask) - if ac != bc { return ac > bc } - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - primary_idx: [128]Range - op_fp_idx: [128]Range - rvc_idx: [32]Range - - for e, i in all { - if e.is_rvc { - push_range(&rvc_idx[e.rvc_key], u16(i)) - } else { - push_range(&primary_idx[e.primary_op], u16(i)) - if e.primary_op == 0x53 { - push_range(&op_fp_idx[e.sub_key], u16(i)) - } - } - } - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_range_table(&sb, "DECODE_INDEX_OPCODE", primary_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_OP_FP", op_fp_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_RVC", rvc_idx[:]) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)strings.to_string(sb)) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - max_primary, max_opfp, max_rvc: u16 - populated_primary, populated_rvc: int - for r in primary_idx { - if r.count > max_primary { max_primary = r.count } - if r.count > 0 { populated_primary += 1 } - } - for r in op_fp_idx { - if r.count > max_opfp { max_opfp = r.count } - } - for r in rvc_idx { - if r.count > max_rvc { max_rvc = r.count } - if r.count > 0 { populated_rvc += 1 } - } - fmt.printfln("OK -- %d entries; primary=%d buckets (max=%d); OP-FP max=%d; RVC=%d buckets (max=%d)", - len(all), populated_primary, max_primary, max_opfp, populated_rvc, max_rvc) -} - -push_range :: proc(r: ^Range, i: u16) { - if r.count == 0 { r.start = i } - r.count += 1 -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_riscv - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd riscv && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{.%v, {{.%v, .%v, .%v, .%v}}, {{.%v, .%v, .%v, .%v}}, 0x%08X, 0x%08X, .%v, {{%s}}}},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: rv.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.rv32_only { write(&sb, &first, "rv32_only=true") } - if f.rv64_only { write(&sb, &first, "rv64_only=true") } - if f.branch { write(&sb, &first, "branch=true") } - if f.fp_round { write(&sb, &first, "fp_round=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/riscv/tools/llvm_per_line.sh b/core/rexcode/riscv/tools/llvm_per_line.sh index 57b22e607..b6d959fa4 100644 --- a/core/rexcode/riscv/tools/llvm_per_line.sh +++ b/core/rexcode/riscv/tools/llvm_per_line.sh @@ -1,4 +1,6 @@ #!/bin/bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # Per-line llvm-mc disassembly wrapper. # # llvm-mc reads the entire stdin as a stream and decodes greedily, so a diff --git a/core/rexcode/riscv/tools/verify_against_llvm.odin b/core/rexcode/riscv/tools/verify_against_llvm.odin index 5fbaaf17c..5aeadfbe3 100644 --- a/core/rexcode/riscv/tools/verify_against_llvm.odin +++ b/core/rexcode/riscv/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main import "core:fmt" diff --git a/core/rexcode/rsp/decoder.odin b/core/rexcode/rsp/decoder.odin index d8b7c9eda..150717460 100644 --- a/core/rexcode/rsp/decoder.odin +++ b/core/rexcode/rsp/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp import "../isa" diff --git a/core/rexcode/rsp/encoder.odin b/core/rexcode/rsp/encoder.odin index 93871574a..e0a0cb900 100644 --- a/core/rexcode/rsp/encoder.odin +++ b/core/rexcode/rsp/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= @@ -105,7 +107,7 @@ encode_one_inline :: #force_inline proc( return 0, false } - forms := ENCODING_TABLE[inst.mnemonic] + forms := encoding_forms(inst.mnemonic) if len(forms) == 0 { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) return 0, false diff --git a/core/rexcode/rsp/encoding_types.odin b/core/rexcode/rsp/encoding_types.odin index 5273551c6..fd4182dc8 100644 --- a/core/rexcode/rsp/encoding_types.odin +++ b/core/rexcode/rsp/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp import "../isa" diff --git a/core/rexcode/rsp/instructions.odin b/core/rexcode/rsp/instructions.odin index d1acb4fb2..c37fd472c 100644 --- a/core/rexcode/rsp/instructions.odin +++ b/core/rexcode/rsp/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= diff --git a/core/rexcode/rsp/mnemonics.odin b/core/rexcode/rsp/mnemonics.odin index 9c1c9ae75..1fe377de9 100644 --- a/core/rexcode/rsp/mnemonics.odin +++ b/core/rexcode/rsp/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= diff --git a/core/rexcode/rsp/operands.odin b/core/rexcode/rsp/operands.odin index 59e693eb0..f291c3e9c 100644 --- a/core/rexcode/rsp/operands.odin +++ b/core/rexcode/rsp/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= diff --git a/core/rexcode/rsp/printer.odin b/core/rexcode/rsp/printer.odin index 97c9b5896..15aab8cf9 100644 --- a/core/rexcode/rsp/printer.odin +++ b/core/rexcode/rsp/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp import "core:strings" diff --git a/core/rexcode/rsp/registers.odin b/core/rexcode/rsp/registers.odin index 10781668f..c0854035d 100644 --- a/core/rexcode/rsp/registers.odin +++ b/core/rexcode/rsp/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= diff --git a/core/rexcode/rsp/reloc.odin b/core/rexcode/rsp/reloc.odin index b39e07676..7dbc601be 100644 --- a/core/rexcode/rsp/reloc.odin +++ b/core/rexcode/rsp/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp // ============================================================================= diff --git a/core/rexcode/rsp/encoding_table.odin b/core/rexcode/rsp/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/rsp/encoding_table.odin rename to core/rexcode/rsp/tablegen/encoding_table.odin index a96791005..8d439c6b1 100644 --- a/core/rexcode/rsp/encoding_table.odin +++ b/core/rexcode/rsp/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_rsp +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_rsp_tablegen // ============================================================================= // N64 RSP ENCODING_TABLE diff --git a/core/rexcode/rsp/tablegen/gen.odin b/core/rexcode/rsp/tablegen/gen.odin new file mode 100644 index 000000000..a22b18917 --- /dev/null +++ b/core/rexcode/rsp/tablegen/gen.odin @@ -0,0 +1,312 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_rsp_tablegen + +// ============================================================================= +// N64 RSP TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, this +// package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin DECODE_ENTRIES + primary/SPECIAL/REGIMM/COP2/ +// LWC2/SWC2 index tables +// generated/writer.odin Stage B: serialize those globals to ../tables/*.bin +// +// It also re-emits the library loader ../tables.odin. Run: +// odin run rsp/tablegen # Stage A +// odin run rsp/tablegen/generated # Stage B + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import "core:math/bits" +import lib "../" + +// Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic + +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "rsp.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "rsp.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "rsp.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_PRIMARY", "rsp.idx_primary.bin", "Decode_Index"}, + {"DECODE_INDEX_SPECIAL", "rsp.idx_special.bin", "Decode_Index"}, + {"DECODE_INDEX_REGIMM", "rsp.idx_regimm.bin", "Decode_Index"}, + {"DECODE_INDEX_COP2", "rsp.idx_cop2.bin", "Decode_Index"}, + {"DECODE_INDEX_LWC2", "rsp.idx_lwc2.bin", "Decode_Index"}, + {"DECODE_INDEX_SWC2", "rsp.idx_swc2.bin", "Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +Entry :: struct { + mnemonic: lib.Mnemonic, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + bits: u32, + mask: u32, + feature: lib.Feature, + flags: lib.Encoding_Flags, + primary_op: u8, + sub_key: u8, +} + +Range :: struct { start: u16, count: u16 } + +main :: proc() { + n := emit_encode_tables() + ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("rsp tablegen: %d encode forms, %d decode entries", n, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side +// ----------------------------------------------------------------------------- + +emit_encode_tables :: proc() -> (total: int) { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_rsp_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags) + } + } + strings.write_string(&sb, "}\n\n") + + run_w := 0 + for m in Mnemonic { run_w = max(run_w, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + c := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (total: int) { + all: [dynamic]Entry + defer delete(all) + for m in Mnemonic { + for f in ENCODING_TABLE[m] { + primary := u8((f.bits >> 26) & 0x3F) + sub: u8 + switch primary { + case 0x00, 0x12: sub = u8(f.bits & 0x3F) // funct + case 0x01: sub = u8((f.bits >> 16) & 0x1F) // rt + case 0x32, 0x3A: sub = u8((f.bits >> 11) & 0x1F) // op2 + } + append(&all, Entry{f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags, primary, sub}) + } + } + slice.sort_by(all[:], proc(a, b: Entry) -> bool { + if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } + if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } + ac := bits.count_ones(a.mask); bc := bits.count_ones(b.mask) + if ac != bc { return ac > bc } + return u16(a.mnemonic) < u16(b.mnemonic) + }) + + primary_idx: [64]Range + special_idx: [64]Range + regimm_idx: [32]Range + cop2_idx: [64]Range + lwc2_idx: [32]Range + swc2_idx: [32]Range + for e, i in all { + push(&primary_idx[e.primary_op], u16(i)) + switch e.primary_op { + case 0x00: push(&special_idx[e.sub_key], u16(i)) + case 0x01: push(®imm_idx [e.sub_key], u16(i)) + case 0x12: push(&cop2_idx [e.sub_key], u16(i)) + case 0x32: push(&lwc2_idx [e.sub_key], u16(i)) + case 0x3A: push(&swc2_idx [e.sub_key], u16(i)) + } + } + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_rsp_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed by primary opcode + sub-field.\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) + for e in all { + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags) + } + strings.write_string(&sb, "}\n\n") + + emit_range(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) + emit_range(&sb, "DECODE_INDEX_SPECIAL", special_idx[:]) + emit_range(&sb, "DECODE_INDEX_REGIMM", regimm_idx[:]) + emit_range(&sb, "DECODE_INDEX_COP2", cop2_idx[:]) + emit_range(&sb, "DECODE_INDEX_LWC2", lwc2_idx[:]) + emit_range(&sb, "DECODE_INDEX_SWC2", swc2_idx[:]) + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(all) +} + +push :: proc(r: ^Range, i: u16) { if r.count == 0 { r.start = i }; r.count += 1 } + +emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { + fmt.sbprintfln(sb, "%s := [%d]lib.Decode_Index{{", name, len(ranges)) + for r, i in ranges { + if r.count != 0 { + fmt.sbprintfln(sb, "\t0x%02X = {{% 4d, % 3d}},", i, r.start, r.count) + } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared row + flags formatting (compact, matching rsp's original generator) +// ----------------------------------------------------------------------------- + +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags)) +} + +flags_lit :: proc(f: lib.Encoding_Flags) -> string { + parts: [dynamic]string + defer delete(parts) + if f.delay_slot { append(&parts, "delay_slot=true") } + if f.likely { append(&parts, "likely=true") } + return strings.join(parts[:], ", ", context.temp_allocator) +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_rsp_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_rsp\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { gmax = max(gmax, len(b.global)); fmax = max(fmax, len(b.file)) } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "rsp.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "rsp.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "rsp.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) + w(TABLES + "rsp.idx_primary.bin", raw(&DECODE_INDEX_PRIMARY, size_of(DECODE_INDEX_PRIMARY))) + w(TABLES + "rsp.idx_special.bin", raw(&DECODE_INDEX_SPECIAL, size_of(DECODE_INDEX_SPECIAL))) + w(TABLES + "rsp.idx_regimm.bin", raw(&DECODE_INDEX_REGIMM, size_of(DECODE_INDEX_REGIMM))) + w(TABLES + "rsp.idx_cop2.bin", raw(&DECODE_INDEX_COP2, size_of(DECODE_INDEX_COP2))) + w(TABLES + "rsp.idx_lwc2.bin", raw(&DECODE_INDEX_LWC2, size_of(DECODE_INDEX_LWC2))) + w(TABLES + "rsp.idx_swc2.bin", raw(&DECODE_INDEX_SWC2, size_of(DECODE_INDEX_SWC2))) +} diff --git a/core/rexcode/rsp/tables.odin b/core/rexcode/rsp/tables.odin new file mode 100644 index 000000000..6b236a748 --- /dev/null +++ b/core/rexcode/rsp/tables.odin @@ -0,0 +1,67 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_rsp + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata). Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, + count: u32, +} + +Decode_Entry :: struct #packed { + mnemonic: Mnemonic, // 2 + ops: [4]Operand_Type, // 4 + enc: [4]Operand_Encoding, // 4 + bits: u32, // 4 + mask: u32, // 4 + feature: Feature, // 1 + flags: Encoding_Flags, // 1 +} +#assert(size_of(Decode_Entry) == 20) + +Decode_Index :: struct #packed { + start: u16, + count: u16, +} +#assert(size_of(Decode_Index) == 4) + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/rsp.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/rsp.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/rsp.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_PRIMARY := #load("tables/rsp.idx_primary.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SPECIAL := #load("tables/rsp.idx_special.bin", []Decode_Index) +@(rodata) DECODE_INDEX_REGIMM := #load("tables/rsp.idx_regimm.bin", []Decode_Index) +@(rodata) DECODE_INDEX_COP2 := #load("tables/rsp.idx_cop2.bin", []Decode_Index) +@(rodata) DECODE_INDEX_LWC2 := #load("tables/rsp.idx_lwc2.bin", []Decode_Index) +@(rodata) DECODE_INDEX_SWC2 := #load("tables/rsp.idx_swc2.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} diff --git a/core/rexcode/rsp/tables/rsp.encode_forms.bin b/core/rexcode/rsp/tables/rsp.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..1d97c8e8420d0dffc489bafa3f22dedd5c2fbd9d GIT binary patch literal 2320 zcmZQ%U}R)uU}j`uP+(wS_|MMphk=0!E~W?(%>ToemxR@4Pj0-NN4Hx5PU}R)tU}j=t00Dc32mcuuc;I483=9kqFI4}W8QB?_7+FEqf`af51A`E<7$_M2Ffa%s zi)k=0fWlb>Sxg5aCd$Cb$N@9Y03s%aEM@``6Gs-afQU&jFmf<3FoB)IV8Z|o14#x( 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b/core/rexcode/rsp/tables/rsp.idx_special.bin new file mode 100644 index 0000000000000000000000000000000000000000..617249ad478278d4a1df39847b089104545f15f4 GIT binary patch literal 256 zcmZQzU}69PCI&_ZW(GzE76wKTmw}amk%5hYk%66ok%0p$29{u8VBkdK!^Fv decode -> print round-trips diff --git a/core/rexcode/rsp/tests/smoke.odin b/core/rexcode/rsp/tests/smoke.odin index 1cd56bced..664f69d4f 100644 --- a/core/rexcode/rsp/tests/smoke.odin +++ b/core/rexcode/rsp/tests/smoke.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_rsp_tests // Spot-check N64 RSP encodings across scalar core, vector ALU, and @@ -13,7 +15,8 @@ import rsp "../" @(private="file") failures := 0 check :: proc(name: string, m: rsp.Mnemonic, want_bits, want_mask: u32) { - encs := rsp.ENCODING_TABLE[m] + _run := rsp.ENCODE_RUNS[u16(m)] + encs := rsp.ENCODE_FORMS[_run.start:][:_run.count] if len(encs) == 0 { fmt.printfln(" [FAIL] %s: no encoding", name) failures += 1 diff --git a/core/rexcode/rsp/tools/armips_lwv_patch.sh b/core/rexcode/rsp/tools/armips_lwv_patch.sh index dc3af64a9..dd31be86d 100644 --- a/core/rexcode/rsp/tools/armips_lwv_patch.sh +++ b/core/rexcode/rsp/tools/armips_lwv_patch.sh @@ -1,4 +1,6 @@ #!/usr/bin/env bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # ============================================================================= # Build a patched armips with LWV restored # ============================================================================= diff --git a/core/rexcode/rsp/tools/dump_verify_input.odin b/core/rexcode/rsp/tools/dump_verify_input.odin index d21e907f4..5ba1b1cf2 100644 --- a/core/rexcode/rsp/tools/dump_verify_input.odin +++ b/core/rexcode/rsp/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -90,7 +92,8 @@ main :: proc() { n: int for mn in r.Mnemonic { - for &f in r.ENCODING_TABLE[mn] { + _run := r.ENCODE_RUNS[u16(mn)] + for &f in r.ENCODE_FORMS[_run.start:][:_run.count] { word := f.bits // Compute "armips-effective" expected bytes: // For single-source ops, armips's [0] yields element=8 in two fields. diff --git a/core/rexcode/rsp/tools/gen_decode_tables.odin b/core/rexcode/rsp/tools/gen_decode_tables.odin deleted file mode 100644 index 161a4522b..000000000 --- a/core/rexcode/rsp/tools/gen_decode_tables.odin +++ /dev/null @@ -1,219 +0,0 @@ -package main - -// ============================================================================= -// N64 RSP DECODE-TABLE GENERATOR -// ============================================================================= -// -// Walks rsp.ENCODING_TABLE and emits `decoding_tables.odin`. Same shape as -// mips/tools/gen_decode_tables.odin, with an RSP-specific dispatch tree: -// -// primary opcode -> DECODE_INDEX_PRIMARY [64] -// 0x00 SPECIAL -> by funct -> DECODE_INDEX_SPECIAL [64] -// 0x01 REGIMM -> by rt -> DECODE_INDEX_REGIMM [32] -// 0x12 COP2 -> by funct -> DECODE_INDEX_COP2 [64] -// (handles both MFC2/MTC2/CFC2/CTC2 with CO=0 and -// all VU ops with CO=1; funct=0 has 5 candidates -// which we linearly scan -- the CO bit lives in -// the static mask so they disambiguate cleanly.) -// 0x32 LWC2 -> by op2 -> DECODE_INDEX_LWC2 [32] -// 0x3A SWC2 -> by op2 -> DECODE_INDEX_SWC2 [32] -// -// Within each Decode_Index range, entries are sorted by mask-popcount -// descending so the most-specific encoding form is matched first. -// -// Run with: cd rsp && odin run tools/gen_decode_tables.odin -file -// Output: ./decoding_tables.odin - -import "core:fmt" -import "core:os" -import "core:slice" -import "core:strings" -import "core:math/bits" - -import rsp "../" - -Entry :: struct { - mnemonic: rsp.Mnemonic, - ops: [4]rsp.Operand_Type, - enc: [4]rsp.Operand_Encoding, - bits: u32, - mask: u32, - feature: rsp.Feature, - flags: rsp.Encoding_Flags, - primary_op: u8, - sub_key: u8, -} - -Range :: struct { - start: u16, - count: u16, -} - -main :: proc() { - fmt.println("Generating RSP decoder tables from ENCODING_TABLE...") - - all: [dynamic]Entry - defer delete(all) - - for mnem in rsp.Mnemonic { - forms := rsp.ENCODING_TABLE[mnem] - for f in forms { - primary := u8((f.bits >> 26) & 0x3F) - sub: u8 - switch primary { - case 0x00, 0x12: - sub = u8(f.bits & 0x3F) // funct - case 0x01: - sub = u8((f.bits >> 16) & 0x1F) // rt - case 0x32, 0x3A: - sub = u8((f.bits >> 11) & 0x1F) // op2 - } - append(&all, Entry{ - mnemonic = mnem, - ops = f.ops, - enc = f.enc, - bits = f.bits, - mask = f.mask, - feature = f.feature, - flags = f.flags, - primary_op = primary, - sub_key = sub, - }) - } - } - - slice.sort_by(all[:], proc(a, b: Entry) -> bool { - if a.primary_op != b.primary_op { return a.primary_op < b.primary_op } - if a.sub_key != b.sub_key { return a.sub_key < b.sub_key } - ac := bits.count_ones(a.mask) - bc := bits.count_ones(b.mask) - if ac != bc { return ac > bc } - return u16(a.mnemonic) < u16(b.mnemonic) - }) - - primary_idx: [64]Range - special_idx: [64]Range - regimm_idx: [32]Range - cop2_idx: [64]Range - lwc2_idx: [32]Range - swc2_idx: [32]Range - - for e, i in all { - push_range(&primary_idx[e.primary_op], u16(i)) - switch e.primary_op { - case 0x00: push_range(&special_idx[e.sub_key], u16(i)) - case 0x01: push_range(®imm_idx [e.sub_key], u16(i)) - case 0x12: push_range(&cop2_idx [e.sub_key], u16(i)) - case 0x32: push_range(&lwc2_idx [e.sub_key], u16(i)) - case 0x3A: push_range(&swc2_idx [e.sub_key], u16(i)) - } - } - - sb: strings.Builder - strings.builder_init(&sb) - defer strings.builder_destroy(&sb) - - emit_header(&sb) - emit_entries(&sb, all[:]) - emit_range_table(&sb, "DECODE_INDEX_PRIMARY", primary_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SPECIAL", special_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_REGIMM", regimm_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_COP2", cop2_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_LWC2", lwc2_idx[:]) - emit_range_table(&sb, "DECODE_INDEX_SWC2", swc2_idx[:]) - - output := strings.to_string(sb) - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)output) - if err != nil { - fmt.eprintfln("FAILED to write decoding_tables.odin: %v", err) - os.exit(1) - } - - max_primary, max_special, max_regimm, max_cop2, max_lwc2, max_swc2: u16 - for r in primary_idx { if r.count > max_primary { max_primary = r.count } } - for r in special_idx { if r.count > max_special { max_special = r.count } } - for r in regimm_idx { if r.count > max_regimm { max_regimm = r.count } } - for r in cop2_idx { if r.count > max_cop2 { max_cop2 = r.count } } - for r in lwc2_idx { if r.count > max_lwc2 { max_lwc2 = r.count } } - for r in swc2_idx { if r.count > max_swc2 { max_swc2 = r.count } } - - fmt.printfln("OK -- %d entries", len(all)) - fmt.printfln(" max bucket sizes: primary=%d special=%d regimm=%d cop2=%d lwc2=%d swc2=%d", - max_primary, max_special, max_regimm, max_cop2, max_lwc2, max_swc2) -} - -push_range :: proc(r: ^Range, i: u16) { - if r.count == 0 { r.start = i } - r.count += 1 -} - -emit_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_rsp - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by tools/gen_decode_tables.odin from ENCODING_TABLE. -// Regenerate with: cd rsp && odin run tools/gen_decode_tables.odin -file -// - -Decode_Entry :: struct #packed { - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - bits: u32, - mask: u32, - feature: Feature, - flags: Encoding_Flags, -} -#assert(size_of(Decode_Entry) == 20) - -Decode_Index :: struct #packed { - start: u16, - count: u16, -} -#assert(size_of(Decode_Index) == 4) - -`) -} - -emit_entries :: proc(sb: ^strings.Builder, entries: []Entry) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "DECODE_ENTRIES := [%d]Decode_Entry{{", len(entries)) - for e in entries { - flags_str := encode_flags_literal(e.flags) - fmt.sbprintfln(sb, - "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},", - e.mnemonic, - e.ops[0], e.ops[1], e.ops[2], e.ops[3], - e.enc[0], e.enc[1], e.enc[2], e.enc[3], - e.bits, e.mask, e.feature, flags_str) - } - strings.write_string(sb, "}\n\n") -} - -encode_flags_literal :: proc(f: rsp.Encoding_Flags) -> string { - sb: strings.Builder - strings.builder_init(&sb) - first := true - write := proc(sb: ^strings.Builder, first: ^bool, s: string) { - if !first^ { strings.write_string(sb, ", ") } - strings.write_string(sb, s) - first^ = false - } - if f.delay_slot { write(&sb, &first, "delay_slot=true") } - if f.likely { write(&sb, &first, "likely=true") } - return strings.to_string(sb) -} - -emit_range_table :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { - fmt.sbprintfln(sb, "@(rodata)") - fmt.sbprintfln(sb, "%s := [%d]Decode_Index{{", name, len(ranges)) - for r, i in ranges { - if r.count != 0 { - fmt.sbprintfln(sb, "\t0x%02X = {{%d, %d}},", i, r.start, r.count) - } - } - strings.write_string(sb, "}\n\n") -} diff --git a/core/rexcode/rsp/tools/verify_against_armips.sh b/core/rexcode/rsp/tools/verify_against_armips.sh index 89ccc292a..d7afa9c62 100644 --- a/core/rexcode/rsp/tools/verify_against_armips.sh +++ b/core/rexcode/rsp/tools/verify_against_armips.sh @@ -1,4 +1,6 @@ #!/usr/bin/env bash +# rexcode · Brendan Punsky (dotbmp@github), original author + # ============================================================================= # N64 RSP verification harness — assembles via `armips`, compares bytes # ============================================================================= diff --git a/core/rexcode/x86/decoder.odin b/core/rexcode/x86/decoder.odin index c0c7749dc..fc797898f 100644 --- a/core/rexcode/x86/decoder.odin +++ b/core/rexcode/x86/decoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 import "core:fmt" @@ -317,29 +319,29 @@ decode_opcode :: proc(state: ^Decoder_State) -> (entry: ^Decode_Entry, vex_entry switch esc { case .NONE: // For legacy instructions, 0x66 is operand size override, use prefix=0 - idx = DECODE_INDEX_LEGACY[0][opcode] + idx = didx(DECODE_INDEX_LEGACY, 0, opcode) case ._0F: - idx = DECODE_INDEX_ESC_0F[prefix][opcode] + idx = didx(DECODE_INDEX_ESC_0F, prefix, opcode) // If not found with 66 prefix, try without (66 is operand size override) if idx.count == 0 && prefix == 1 { - idx = DECODE_INDEX_ESC_0F[0][opcode] + idx = didx(DECODE_INDEX_ESC_0F, 0, opcode) } case ._0F38: - idx = DECODE_INDEX_ESC_0F38[prefix][opcode] + idx = didx(DECODE_INDEX_ESC_0F38, prefix, opcode) if idx.count == 0 && prefix == 1 { - idx = DECODE_INDEX_ESC_0F38[0][opcode] + idx = didx(DECODE_INDEX_ESC_0F38, 0, opcode) } case ._0F3A: - idx = DECODE_INDEX_ESC_0F3A[prefix][opcode] + idx = didx(DECODE_INDEX_ESC_0F3A, prefix, opcode) if idx.count == 0 && prefix == 1 { - idx = DECODE_INDEX_ESC_0F3A[0][opcode] + idx = didx(DECODE_INDEX_ESC_0F3A, 0, opcode) } } // If not found, try +r encoding (opcode with register in low 3 bits) if idx.count == 0 && esc == .NONE { base_opcode := opcode & 0xF8 // Mask off low 3 bits - idx = DECODE_INDEX_LEGACY[prefix][base_opcode] + idx = didx(DECODE_INDEX_LEGACY, prefix, base_opcode) // Check if this is actually an Op_R encoding if idx.count > 0 { @@ -523,16 +525,16 @@ decode_opcode_vex :: #force_inline proc(state: ^Decoder_State) -> (entry: ^Decod if state.vex_type == .EVEX { switch esc_idx { - case 0: idx = EVEX_INDEX_0F[prefix][opcode] - case 1: idx = EVEX_INDEX_0F38[prefix][opcode] - case 2: idx = EVEX_INDEX_0F3A[prefix][opcode] + case 0: idx = didx(EVEX_INDEX_0F, prefix, opcode) + case 1: idx = didx(EVEX_INDEX_0F38, prefix, opcode) + case 2: idx = didx(EVEX_INDEX_0F3A, prefix, opcode) } entries = EVEX_DECODE_ENTRIES[:] } else { switch esc_idx { - case 0: idx = VEX_INDEX_0F[prefix][opcode] - case 1: idx = VEX_INDEX_0F38[prefix][opcode] - case 2: idx = VEX_INDEX_0F3A[prefix][opcode] + case 0: idx = didx(VEX_INDEX_0F, prefix, opcode) + case 1: idx = didx(VEX_INDEX_0F38, prefix, opcode) + case 2: idx = didx(VEX_INDEX_0F3A, prefix, opcode) } entries = VEX_DECODE_ENTRIES[:] } diff --git a/core/rexcode/x86/encoder.odin b/core/rexcode/x86/encoder.odin index 0e51bdf26..7bfa6548b 100644 --- a/core/rexcode/x86/encoder.odin +++ b/core/rexcode/x86/encoder.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= @@ -140,7 +142,7 @@ encode :: proc( } // Find matching encoding from table (O(1) mnemonic lookup) - encodings := ENCODING_TABLE[inst.mnemonic] + encodings := encoding_forms(inst.mnemonic) if len(encodings) == 0 { append(errors, Error{u32(instruction_index), .INVALID_MNEMONIC, {}}) has_errors = true diff --git a/core/rexcode/x86/encoding_types.odin b/core/rexcode/x86/encoding_types.odin index ea6fa4bcb..62b1393df 100644 --- a/core/rexcode/x86/encoding_types.odin +++ b/core/rexcode/x86/encoding_types.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/instructions.odin b/core/rexcode/x86/instructions.odin index 6a2fcfe3b..3ad64f237 100644 --- a/core/rexcode/x86/instructions.odin +++ b/core/rexcode/x86/instructions.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/labels.odin b/core/rexcode/x86/labels.odin index 7f74474e1..4fc56b599 100644 --- a/core/rexcode/x86/labels.odin +++ b/core/rexcode/x86/labels.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/mnemonic_builders.odin b/core/rexcode/x86/mnemonic_builders.odin index 6ab6befd8..e5e1b5f4d 100644 --- a/core/rexcode/x86/mnemonic_builders.odin +++ b/core/rexcode/x86/mnemonic_builders.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/mnemonics.odin b/core/rexcode/x86/mnemonics.odin index 49eef99f5..0ed1b142c 100644 --- a/core/rexcode/x86/mnemonics.odin +++ b/core/rexcode/x86/mnemonics.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/operands.odin b/core/rexcode/x86/operands.odin index 85e8e60f4..d0634abe2 100644 --- a/core/rexcode/x86/operands.odin +++ b/core/rexcode/x86/operands.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/printer.odin b/core/rexcode/x86/printer.odin index 6d391c6bf..792c01afb 100644 --- a/core/rexcode/x86/printer.odin +++ b/core/rexcode/x86/printer.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= @@ -306,7 +308,9 @@ sbprint :: proc( if label_def != LABEL_UNDEFINED && u32(label_def) == info.offset { // Print label definition start := strings.builder_len(sb^) - if name, ok := label_names^[u32(label_id)]; ok { + name: string; ok: bool + if label_names != nil { name, ok = label_names^[u32(label_id)] } + if ok { strings.write_string(sb, name) } else { strings.write_string(sb, options.label_prefix) @@ -397,7 +401,9 @@ sbprint :: proc( if found_label_valid { start := strings.builder_len(sb^) - if name, ok := label_names^[found_label]; ok { + name: string; ok: bool + if label_names != nil { name, ok = label_names^[found_label] } + if ok { strings.write_string(sb, name) } else { strings.write_string(sb, options.label_prefix) diff --git a/core/rexcode/x86/registers.odin b/core/rexcode/x86/registers.odin index 32dafd041..b9f6eaa44 100644 --- a/core/rexcode/x86/registers.odin +++ b/core/rexcode/x86/registers.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/reloc.odin b/core/rexcode/x86/reloc.odin index 39944d2ac..454a3e48a 100644 --- a/core/rexcode/x86/reloc.odin +++ b/core/rexcode/x86/reloc.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86 // ============================================================================= diff --git a/core/rexcode/x86/encoding_table.odin b/core/rexcode/x86/tablegen/encoding_table.odin similarity index 99% rename from core/rexcode/x86/encoding_table.odin rename to core/rexcode/x86/tablegen/encoding_table.odin index 80134cf6d..24f96a0f6 100644 --- a/core/rexcode/x86/encoding_table.odin +++ b/core/rexcode/x86/tablegen/encoding_table.odin @@ -1,4 +1,6 @@ -package rexcode_x86 +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_x86_tablegen // ============================================================================= // x86 ENCODING_TABLE diff --git a/core/rexcode/x86/tablegen/gen.odin b/core/rexcode/x86/tablegen/gen.odin new file mode 100644 index 000000000..8ae9bd767 --- /dev/null +++ b/core/rexcode/x86/tablegen/gen.odin @@ -0,0 +1,530 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_x86_tablegen + +// ============================================================================= +// x86 TABLE GENERATOR (Stage A) +// ============================================================================= +// +// Reads the single-source-of-truth ENCODING_TABLE (encoding_table.odin, in this +// same package) and emits human-readable, type-checked Odin into ./generated/: +// +// generated/encode_tables.odin ENCODE_FORMS + ENCODE_RUNS (flattened encode) +// generated/decode_tables.odin modrm/sib + decode entries + opcode indices +// generated/writer.odin Stage B: serializes those globals to ../tables/*.bin +// +// It also (re)emits the library loader ../tables.odin (subsidiary types + #load). +// +// Run from anywhere: +// odin run core/rexcode/x86/tablegen # Stage A (this program) +// odin run core/rexcode/x86/tablegen/generated # Stage B (writes the blobs) +// +// The generated Odin is the auditable intermediate: the compiler validates it +// before Stage B dumps it to raw bytes, so the blobs can never drift from a +// well-typed table. + +import "core:fmt" +import "core:os" +import "core:strings" +import "core:slice" +import "core:reflect" +import lib "../" + +// Package-scope aliases so the moved SoT (encoding_table.odin) resolves +// `Mnemonic`/`Encoding` unqualified — its body stays byte-for-byte unedited. +Encoding :: lib.Encoding +Mnemonic :: lib.Mnemonic +PREFIX_66 :: lib.PREFIX_66 +PREFIX_F3 :: lib.PREFIX_F3 +PREFIX_F2 :: lib.PREFIX_F2 + +// One row of the blob manifest. Drives BOTH the loader's #load lines and the +// writer's dump calls, so the two can never disagree on names/files. +Blob :: struct { global, file, typ: string } +BLOBS := [?]Blob{ + {"ENCODE_FORMS", "x86.encode_forms.bin", "Encoding"}, + {"ENCODE_RUNS", "x86.encode_runs.bin", "Encode_Run"}, + {"MODRM_TABLE", "x86.modrm.bin", "ModRM_Info"}, + {"SIB_TABLE", "x86.sib.bin", "SIB_Info"}, + {"LEGACY_DECODE_ENTRIES", "x86.legacy.bin", "Decode_Entry"}, + {"VEX_DECODE_ENTRIES", "x86.vex.bin", "VEX_Decode_Entry"}, + {"EVEX_DECODE_ENTRIES", "x86.evex.bin", "VEX_Decode_Entry"}, + {"DECODE_INDEX_LEGACY", "x86.idx_legacy.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F", "x86.idx_0f.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F38", "x86.idx_0f38.bin", "Decode_Index"}, + {"DECODE_INDEX_ESC_0F3A", "x86.idx_0f3a.bin", "Decode_Index"}, + {"VEX_INDEX_0F", "x86.vex_idx_0f.bin", "Decode_Index"}, + {"VEX_INDEX_0F38", "x86.vex_idx_0f38.bin", "Decode_Index"}, + {"VEX_INDEX_0F3A", "x86.vex_idx_0f3a.bin", "Decode_Index"}, + {"EVEX_INDEX_0F", "x86.evex_idx_0f.bin", "Decode_Index"}, + {"EVEX_INDEX_0F38", "x86.evex_idx_0f38.bin","Decode_Index"}, + {"EVEX_INDEX_0F3A", "x86.evex_idx_0f3a.bin","Decode_Index"}, +} + +DIR_GEN :: #directory + "/generated/" +PATH_LOADER :: #directory + "/../tables.odin" + +main :: proc() { + emit_encode_tables() + nl, nv, ne := emit_decode_tables() + emit_writer() + emit_loader() + fmt.printfln("x86 tablegen: %d encode forms, %d legacy / %d vex / %d evex decode entries", + total_forms(), nl, nv, ne) +} + +// ----------------------------------------------------------------------------- +// Encode side: ENCODE_FORMS (flat) + ENCODE_RUNS (per-mnemonic index) +// ----------------------------------------------------------------------------- + +total_forms :: proc() -> (n: int) { + for m in Mnemonic { n += len(ENCODING_TABLE[m]) } + return +} + +emit_encode_tables :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_x86_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + max_name := 0 + for m in Mnemonic { + if len(ENCODING_TABLE[m]) > 0 { + max_name = max(max_name, len(reflect.enum_string(m))) + } + } + + fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total_forms()) + for m in Mnemonic { + forms := ENCODING_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { write_encoding(&sb, f, max_name) } + } + strings.write_string(&sb, "}\n\n") + + // Run index, one entry per mnemonic (dense, enum-ordinal order). + run_name := 0 + for m in Mnemonic { run_name = max(run_name, len(reflect.enum_string(m))) } + strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") + start := 0 + for m in Mnemonic { + n := len(ENCODING_TABLE[m]) + name := reflect.enum_string(m) + fmt.sbprintf(&sb, "\t.%s", name) + for _ in 0.. (n_legacy, n_vex, n_evex: int) { + legacy, vex, evex: [dynamic]Collected_Entry + for m in Mnemonic { + for enc in ENCODING_TABLE[m] { + e := Collected_Entry{ + esc = enc.flags.esc, + prefix = enc.flags.prefix, + opcode = enc.opcode, + ext = enc.flags.modrm_reg_ext ? enc.ext : 0xFF, + mnemonic = enc.mnemonic, + ops = enc.ops, + enc = enc.enc, + flags = enc.flags, + vex_w = enc.flags.vex_w, + vex_l = enc.flags.vex_l, + } + switch enc.flags.vex_type { + case .VEX: append(&vex, e) + case .EVEX: append(&evex, e) + case .NONE, .XOP: append(&legacy, e) + } + } + } + slice.sort_by(legacy[:], entry_less) + slice.sort_by(vex[:], entry_less) + slice.sort_by(evex[:], entry_less) + + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_x86_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Reverse decode tables (source: ENCODING_TABLE), keyed (esc, prefix, opcode, ext).\n\n") + strings.write_string(&sb, "import lib \"../..\"\n\n") + + gen_modrm(&sb) + gen_sib(&sb) + gen_entries(&sb, "LEGACY_DECODE_ENTRIES", "lib.Decode_Entry", legacy[:], false) + gen_entries(&sb, "VEX_DECODE_ENTRIES", "lib.VEX_Decode_Entry", vex[:], true) + gen_entries(&sb, "EVEX_DECODE_ENTRIES", "lib.VEX_Decode_Entry", evex[:], true) + gen_legacy_index(&sb, legacy[:]) + gen_vex_index(&sb, vex[:], "VEX") + gen_vex_index(&sb, evex[:], "EVEX") + + emit_file(DIR_GEN + "decode_tables.odin", &sb) + return len(legacy), len(vex), len(evex) +} + +entry_less :: proc(a, b: Collected_Entry) -> bool { + if a.esc != b.esc { return int(a.esc) < int(b.esc) } + if a.prefix != b.prefix { return a.prefix < b.prefix } + if a.opcode != b.opcode { return a.opcode < b.opcode } + return a.ext < b.ext +} + +gen_entries :: proc(sb: ^strings.Builder, name, typ: string, entries: []Collected_Entry, is_vex: bool) { + max_name := 0 + for e in entries { max_name = max(max_name, len(reflect.enum_string(e.mnemonic))) } + fmt.sbprintfln(sb, "%s := [%d]%s{{", name, len(entries), typ) + for e in entries { + strings.write_string(sb, "\t{") + print_enum_buffered(sb, e.esc, 5, true) + fmt.sbprintf(sb, "%d, 0x%02X, 0x%02X, ", e.prefix, e.opcode, e.ext) + if is_vex { + print_enum_buffered(sb, e.vex_w, 4, true) + print_enum_buffered(sb, e.vex_l, 4, true) + } + print_enum_buffered(sb, e.mnemonic, max_name, true) + strings.write_string(sb, "{") + for op, i in e.ops { print_enum_buffered(sb, op, 9, i+1 < len(e.ops)) } + strings.write_string(sb, "}, {") + for en, i in e.enc { print_enum_buffered(sb, en, 4, i+1 < len(e.enc)) } + strings.write_string(sb, "}, ") + write_flags(sb, e.flags) + strings.write_string(sb, "},\n") + } + strings.write_string(sb, "}\n\n") +} + +find_run :: proc(entries: []Collected_Entry, esc: lib.Escape, prefix, opcode: u8) -> (start, count: int) { + found := false + for e, idx in entries { + if e.esc == esc && e.prefix == prefix && e.opcode == opcode { + if !found { start = idx; found = true } + count += 1 + } else if found { + break + } + } + return +} + +prefix_name :: proc(p: int) -> string { + switch p { + case 0: return "none" + case 1: return "66" + case 2: return "F3" + case 3: return "F2" + } + return "?" +} + +gen_legacy_index :: proc(sb: ^strings.Builder, entries: []Collected_Entry) { + for esc in lib.Escape { + name: string + switch esc { + case .NONE: name = "DECODE_INDEX_LEGACY" + case ._0F: name = "DECODE_INDEX_ESC_0F" + case ._0F38: name = "DECODE_INDEX_ESC_0F38" + case ._0F3A: name = "DECODE_INDEX_ESC_0F3A" + } + fmt.sbprintfln(sb, "%s := [4][256]lib.Decode_Index{{", name) + for prefix in 0..<4 { + fmt.sbprintfln(sb, "\t{{ // prefix = %s", prefix_name(prefix)) + for opcode in 0..<256 { + start, count := find_run(entries, esc, u8(prefix), u8(opcode)) + if count > 0 { + fmt.sbprintfln(sb, "\t\t0x%02X = {{% 4d, % 2d}},", opcode, start, count) + } + } + strings.write_string(sb, "\t},\n") + } + strings.write_string(sb, "}\n\n") + } +} + +gen_vex_index :: proc(sb: ^strings.Builder, entries: []Collected_Entry, kind: string) { + for esc_idx in 0..<3 { + esc: lib.Escape + esc_name: string + switch esc_idx { + case 0: esc = ._0F; esc_name = "0F" + case 1: esc = ._0F38; esc_name = "0F38" + case 2: esc = ._0F3A; esc_name = "0F3A" + } + fmt.sbprintfln(sb, "%s_INDEX_%s := [4][256]lib.Decode_Index{{", kind, esc_name) + for prefix in 0..<4 { + any := false + for opcode in 0..<256 { + _, count := find_run(entries, esc, u8(prefix), u8(opcode)) + if count > 0 { any = true; break } + } + fmt.sbprintf(sb, "\t%d = {{ /* prefix = %s */", prefix, prefix_name(prefix)) + if !any { + strings.write_string(sb, " },\n") + continue + } + strings.write_string(sb, "\n") + for opcode in 0..<256 { + start, count := find_run(entries, esc, u8(prefix), u8(opcode)) + if count > 0 { + fmt.sbprintfln(sb, "\t\t0x%02X = {{% 3d, % 2d}},", opcode, start, count) + } + } + strings.write_string(sb, "\t},\n") + } + strings.write_string(sb, "}\n\n") + } +} + +gen_modrm :: proc(sb: ^strings.Builder) { + strings.write_string(sb, "MODRM_TABLE := [256]lib.ModRM_Info{\n") + for i in 0..<256 { + modrm := u8(i) + mod := (modrm >> 6) & 0x3 + reg := (modrm >> 3) & 0x7 + rm := modrm & 0x7 + has_sib := (rm == 4) && (mod != 3) + disp_size: u8 = 0 + if mod == 0 && rm == 5 { disp_size = 4 } + else if mod == 1 { disp_size = 1 } + else if mod == 2 { disp_size = 4 } + if i % 4 == 0 { strings.write_string(sb, "\t") } + fmt.sbprintf(sb, "{{%d, %d, %d, %s, %d}}, ", mod, reg, rm, has_sib ? " true" : "false", disp_size) + if (i + 1) % 4 == 0 { strings.write_string(sb, "\n") } + } + strings.write_string(sb, "}\n\n") +} + +gen_sib :: proc(sb: ^strings.Builder) { + strings.write_string(sb, "SIB_TABLE := [256]lib.SIB_Info{\n") + for i in 0..<256 { + sib := u8(i) + scale: u8 = 1 << ((sib >> 6) & 0x3) + index := (sib >> 3) & 0x7 + base := sib & 0x7 + index_out := index == 4 ? u8(0xFF) : index + fmt.sbprintf(sb, "\t{{%d, % 3d, %d}},", scale, index_out, base) + if (i + 1) % 4 == 0 { strings.write_string(sb, "\n") } + } + strings.write_string(sb, "}\n\n") +} + +// ----------------------------------------------------------------------------- +// Shared formatting helpers (ported from the original decode generator) +// ----------------------------------------------------------------------------- + +print_enum_buffered :: proc(sb: ^strings.Builder, x: $T, max_name: int, comma: bool) { + fmt.sbprintf(sb, ".%v", x) + if comma { strings.write_string(sb, ", ") } else { return } + for n := max_name - len(reflect.enum_string(x)); n > 0; n -= 1 { + strings.write_byte(sb, ' ') + } +} + +// Complete Encoding_Flags emitter -- every field, so ENCODE_FORMS round-trips +// the SoT exactly (mode_32_only is read by the encoder). +write_flags :: proc(sb: ^strings.Builder, flags: lib.Encoding_Flags) { + parts: [dynamic]string + defer delete(parts) + if flags.esc != .NONE { append(&parts, fmt.tprintf("esc=.%v", flags.esc)) } + if flags.prefix != 0 { append(&parts, fmt.tprintf("prefix=%d", flags.prefix)) } + if flags.vex_type != .NONE { append(&parts, fmt.tprintf("vex_type=.%v", flags.vex_type)) } + if flags.vex_w != .WIG { append(&parts, fmt.tprintf("vex_w=.%v", flags.vex_w)) } + if flags.vex_l != .LIG { append(&parts, fmt.tprintf("vex_l=.%v", flags.vex_l)) } + if flags.default_64 { append(&parts, "default_64=true") } + if flags.force_rex_w { append(&parts, "force_rex_w=true") } + if flags.no_rex { append(&parts, "no_rex=true") } + if flags.lock_ok { append(&parts, "lock_ok=true") } + if flags.rep_ok { append(&parts, "rep_ok=true") } + if flags.modrm_reg_ext { append(&parts, "modrm_reg_ext=true") } + if flags.mode_32_only { append(&parts, "mode_32_only=true") } + strings.write_string(sb, "{") + for part, i in parts { + if i > 0 { strings.write_string(sb, ", ") } + strings.write_string(sb, part) + } + strings.write_string(sb, "}") +} + +// ----------------------------------------------------------------------------- +// Stage B writer + the library loader +// ----------------------------------------------------------------------------- + +emit_writer :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_x86_generated\n\n") + strings.write_string(&sb, "// GENERATED by ../gen.odin -- DO NOT EDIT.\n") + strings.write_string(&sb, "// Stage B: serialize the typed tables above to raw blobs under ../../tables/.\n\n") + strings.write_string(&sb, "import \"core:os\"\nimport \"core:fmt\"\n\n") + strings.write_string(&sb, "TABLES :: #directory + \"/../../tables/\"\n\n") + strings.write_string(&sb, "raw :: #force_inline proc \"contextless\" (p: rawptr, n: int) -> []u8 {\n") + strings.write_string(&sb, "\treturn (cast([^]u8)p)[:n]\n}\n\n") + strings.write_string(&sb, "w :: proc(file: string, data: []u8) {\n") + strings.write_string(&sb, "\tif err := os.write_entire_file(file, data); err != nil {\n") + strings.write_string(&sb, "\t\tfmt.eprintfln(\"rexcode tablegen: failed to write %s: %v\", file, err)\n") + strings.write_string(&sb, "\t\tos.exit(1)\n\t}\n}\n\n") + strings.write_string(&sb, "main :: proc() {\n") + for b in BLOBS { + fmt.sbprintfln(&sb, "\tw(TABLES + \"%s\", raw(&%s, size_of(%s)))", b.file, b.global, b.global) + } + strings.write_string(&sb, "}\n") + emit_file(DIR_GEN + "writer.odin", &sb) +} + +LOADER_TYPES :: `// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, // start index in ENCODE_FORMS + count: u32, // number of forms for this mnemonic +} + +// Precomputed extraction of mod, reg, rm fields from a ModR/M byte. +ModRM_Info :: struct #packed { + mod: u8, + reg: u8, + rm: u8, + has_sib: bool, + disp_size: u8, +} + +// Precomputed extraction of scale, index, base fields from a SIB byte. +SIB_Info :: struct #packed { + scale: u8, + index: u8, + base: u8, +} + +// Information needed to decode an instruction given its opcode bytes. +Decode_Entry :: struct { + esc: Escape, + prefix: u8, + opcode: u8, + ext: u8, + mnemonic: Mnemonic, + ops: [4]Operand_Type, + enc: [4]Operand_Encoding, + flags: Encoding_Flags, +} + +VEX_Decode_Entry :: struct { + esc: Escape, + prefix: u8, + opcode: u8, + ext: u8, + vex_w: VEX_W, + vex_l: VEX_L, + mnemonic: Mnemonic, + ops: [4]Operand_Type, + enc: [4]Operand_Encoding, + flags: Encoding_Flags, +} + +// (start, count) into a *_DECODE_ENTRIES array. Index tables are stored flat: +// a logical [4][256] is loaded as [1024]; address with ` + "`didx`" + `. +Decode_Index :: struct { + start: u16, + count: u8, +} +` + +LOADER_ACCESSORS :: `// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to ` + "`m`" + `. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} + +// Flat [prefix][opcode] lookup into a logical [4][256] index table. +@(private, require_results) +didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { + return t[(int(prefix) << 8) | int(opcode)] +} +` + +emit_loader :: proc() { + sb := strings.builder_make() + strings.write_string(&sb, "package rexcode_x86\n\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "// GENERATED FILE - DO NOT EDIT\n") + strings.write_string(&sb, "// =============================================================================\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// Loads the flat binary encode/decode tables into @(rodata) and exposes the\n") + strings.write_string(&sb, "// accessors the encoder/decoder drive. Produced by tablegen:\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file\n") + strings.write_string(&sb, "// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin\n") + strings.write_string(&sb, "//\n") + strings.write_string(&sb, "// The .bin blobs are raw, host-endian, packed struct images.\n\n") + strings.write_string(&sb, LOADER_TYPES) + strings.write_string(&sb, "\n// -----------------------------------------------------------------------------\n") + strings.write_string(&sb, "// Loaded tables (rodata, embedded from tables/*.bin at compile time)\n") + strings.write_string(&sb, "// -----------------------------------------------------------------------------\n\n") + + gmax, fmax := 0, 0 + for b in BLOBS { + gmax = max(gmax, len(b.global)) + fmax = max(fmax, len(b.file)) + } + for b in BLOBS { + fmt.sbprintf(&sb, "@(rodata) %s", b.global) + for _ in 0.. []u8 { + return (cast([^]u8)p)[:n] +} + +w :: proc(file: string, data: []u8) { + if err := os.write_entire_file(file, data); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", file, err) + os.exit(1) + } +} + +main :: proc() { + w(TABLES + "x86.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "x86.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) + w(TABLES + "x86.modrm.bin", raw(&MODRM_TABLE, size_of(MODRM_TABLE))) + w(TABLES + "x86.sib.bin", raw(&SIB_TABLE, size_of(SIB_TABLE))) + w(TABLES + "x86.legacy.bin", raw(&LEGACY_DECODE_ENTRIES, size_of(LEGACY_DECODE_ENTRIES))) + w(TABLES + "x86.vex.bin", raw(&VEX_DECODE_ENTRIES, size_of(VEX_DECODE_ENTRIES))) + w(TABLES + "x86.evex.bin", raw(&EVEX_DECODE_ENTRIES, size_of(EVEX_DECODE_ENTRIES))) + w(TABLES + "x86.idx_legacy.bin", raw(&DECODE_INDEX_LEGACY, size_of(DECODE_INDEX_LEGACY))) + w(TABLES + "x86.idx_0f.bin", raw(&DECODE_INDEX_ESC_0F, size_of(DECODE_INDEX_ESC_0F))) + w(TABLES + "x86.idx_0f38.bin", raw(&DECODE_INDEX_ESC_0F38, size_of(DECODE_INDEX_ESC_0F38))) + w(TABLES + "x86.idx_0f3a.bin", raw(&DECODE_INDEX_ESC_0F3A, size_of(DECODE_INDEX_ESC_0F3A))) + w(TABLES + "x86.vex_idx_0f.bin", raw(&VEX_INDEX_0F, size_of(VEX_INDEX_0F))) + w(TABLES + "x86.vex_idx_0f38.bin", raw(&VEX_INDEX_0F38, size_of(VEX_INDEX_0F38))) + w(TABLES + "x86.vex_idx_0f3a.bin", raw(&VEX_INDEX_0F3A, size_of(VEX_INDEX_0F3A))) + w(TABLES + "x86.evex_idx_0f.bin", raw(&EVEX_INDEX_0F, size_of(EVEX_INDEX_0F))) + w(TABLES + "x86.evex_idx_0f38.bin", raw(&EVEX_INDEX_0F38, size_of(EVEX_INDEX_0F38))) + w(TABLES + "x86.evex_idx_0f3a.bin", raw(&EVEX_INDEX_0F3A, size_of(EVEX_INDEX_0F3A))) +} diff --git a/core/rexcode/x86/tables.odin b/core/rexcode/x86/tables.odin new file mode 100644 index 000000000..06aae9829 --- /dev/null +++ b/core/rexcode/x86/tables.odin @@ -0,0 +1,113 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_x86 + +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Loads the flat binary encode/decode tables into @(rodata) and exposes the +// accessors the encoder/decoder drive. Produced by tablegen: +// +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// +// The .bin blobs are raw, host-endian, packed struct images. + +// ----------------------------------------------------------------------------- +// Subsidiary table types (generated scaffolding) +// ----------------------------------------------------------------------------- + +// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. +Encode_Run :: struct { + start: u32, // start index in ENCODE_FORMS + count: u32, // number of forms for this mnemonic +} + +// Precomputed extraction of mod, reg, rm fields from a ModR/M byte. +ModRM_Info :: struct #packed { + mod: u8, + reg: u8, + rm: u8, + has_sib: bool, + disp_size: u8, +} + +// Precomputed extraction of scale, index, base fields from a SIB byte. +SIB_Info :: struct #packed { + scale: u8, + index: u8, + base: u8, +} + +// Information needed to decode an instruction given its opcode bytes. +Decode_Entry :: struct { + esc: Escape, + prefix: u8, + opcode: u8, + ext: u8, + mnemonic: Mnemonic, + ops: [4]Operand_Type, + enc: [4]Operand_Encoding, + flags: Encoding_Flags, +} + +VEX_Decode_Entry :: struct { + esc: Escape, + prefix: u8, + opcode: u8, + ext: u8, + vex_w: VEX_W, + vex_l: VEX_L, + mnemonic: Mnemonic, + ops: [4]Operand_Type, + enc: [4]Operand_Encoding, + flags: Encoding_Flags, +} + +// (start, count) into a *_DECODE_ENTRIES array. Index tables are stored flat: +// a logical [4][256] is loaded as [1024]; address with `didx`. +Decode_Index :: struct { + start: u16, + count: u8, +} + +// ----------------------------------------------------------------------------- +// Loaded tables (rodata, embedded from tables/*.bin at compile time) +// ----------------------------------------------------------------------------- + +@(rodata) ENCODE_FORMS := #load("tables/x86.encode_forms.bin", []Encoding) +@(rodata) ENCODE_RUNS := #load("tables/x86.encode_runs.bin", []Encode_Run) +@(rodata) MODRM_TABLE := #load("tables/x86.modrm.bin", []ModRM_Info) +@(rodata) SIB_TABLE := #load("tables/x86.sib.bin", []SIB_Info) +@(rodata) LEGACY_DECODE_ENTRIES := #load("tables/x86.legacy.bin", []Decode_Entry) +@(rodata) VEX_DECODE_ENTRIES := #load("tables/x86.vex.bin", []VEX_Decode_Entry) +@(rodata) EVEX_DECODE_ENTRIES := #load("tables/x86.evex.bin", []VEX_Decode_Entry) +@(rodata) DECODE_INDEX_LEGACY := #load("tables/x86.idx_legacy.bin", []Decode_Index) +@(rodata) DECODE_INDEX_ESC_0F := #load("tables/x86.idx_0f.bin", []Decode_Index) +@(rodata) DECODE_INDEX_ESC_0F38 := #load("tables/x86.idx_0f38.bin", []Decode_Index) +@(rodata) DECODE_INDEX_ESC_0F3A := #load("tables/x86.idx_0f3a.bin", []Decode_Index) +@(rodata) VEX_INDEX_0F := #load("tables/x86.vex_idx_0f.bin", []Decode_Index) +@(rodata) VEX_INDEX_0F38 := #load("tables/x86.vex_idx_0f38.bin", []Decode_Index) +@(rodata) VEX_INDEX_0F3A := #load("tables/x86.vex_idx_0f3a.bin", []Decode_Index) +@(rodata) EVEX_INDEX_0F := #load("tables/x86.evex_idx_0f.bin", []Decode_Index) +@(rodata) EVEX_INDEX_0F38 := #load("tables/x86.evex_idx_0f38.bin", []Decode_Index) +@(rodata) EVEX_INDEX_0F3A := #load("tables/x86.evex_idx_0f3a.bin", []Decode_Index) + +// ----------------------------------------------------------------------------- +// Accessors +// ----------------------------------------------------------------------------- + +// Per-mnemonic encode forms: the run of ENCODE_FORMS belonging to `m`. +// Replaces the old ENCODING_TABLE[m] slice; the returned view is into rodata. +@(private, require_results) +encoding_forms :: #force_inline proc "contextless" (m: Mnemonic) -> []Encoding { + r := ENCODE_RUNS[u16(m)] + return ENCODE_FORMS[r.start:][:r.count] +} + +// Flat [prefix][opcode] lookup into a logical [4][256] index table. +@(private, require_results) +didx :: #force_inline proc "contextless" (t: []Decode_Index, prefix, opcode: u8) -> Decode_Index { + return t[(int(prefix) << 8) | int(opcode)] +} diff --git a/core/rexcode/x86/tables/x86.encode_forms.bin b/core/rexcode/x86/tables/x86.encode_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..f5d461a38f200d4946796911b1b56519cdbe1f1a GIT binary patch literal 37680 zcmZQ%U}a=rU}R!o=wJW=Mg}$}2)`4=Wng4rXGZ07u)z5o3=E76jI0a{OpFW+T~PH* zY!H4ol+VnL%4gw#^C9|$7#LVs85lM|)iVh*FtD&OFzkTxnMD{FSlAJK7EuNUkQqA| z7{K~jg&4qYIL5%x0CEqTFarZ48w0~}D4$(~fq{`7!RJ8mJ3#6sO&J(CIT#ogK<$$< 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a/core/rexcode/x86/tests32/test_32bit.odin +++ b/core/rexcode/x86/tests32/test_32bit.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package rexcode_x86_tests32 // Focused smoke tests for the i386 (Mode._32) encode/decode paths. diff --git a/core/rexcode/x86/tools/dump_verify_input.odin b/core/rexcode/x86/tools/dump_verify_input.odin index 1b1a97aa0..b375d6ab8 100644 --- a/core/rexcode/x86/tools/dump_verify_input.odin +++ b/core/rexcode/x86/tools/dump_verify_input.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -113,7 +115,8 @@ main :: proc() { total, dumped, skipped := 0, 0, 0 for mn in x.Mnemonic { - for entry, ei in x.ENCODING_TABLE[mn] { + _run := x.ENCODE_RUNS[u16(mn)] + for entry, ei in x.ENCODE_FORMS[_run.start:][:_run.count] { total += 1 // Skip entries that need REL/MOFFS or other forms we can't easily diff --git a/core/rexcode/x86/tools/gen_decode_tables.odin b/core/rexcode/x86/tools/gen_decode_tables.odin deleted file mode 100644 index a5537740a..000000000 --- a/core/rexcode/x86/tools/gen_decode_tables.odin +++ /dev/null @@ -1,568 +0,0 @@ -package main - -// ============================================================================= -// Decoder Table Generator -// ============================================================================= -// -// This script generates decoding_tables.odin by iterating the encoder's ENC_TABLE -// and building reverse lookup tables (opcode -> encoding info). -// -// Run with: odin run gen_decode_tables.odin -file -// -// Output: decoding_tables.odin (written to current directory) - -import "core:fmt" -import "core:reflect" -import "core:os" -import "core:strings" -import "core:slice" -import x86 "../" - -main :: proc() { - fmt.println("Generating decoder tables from ENC_TABLE...") - - sb := strings.builder_make() - - generate_header(&sb) - generate_modrm_table(&sb) - generate_sib_table(&sb) - generate_opcode_tables(&sb) - - output := strings.to_string(sb) - - err := os.write_entire_file("decoding_tables.odin", transmute([]u8)output) - if err == nil { - fmt.println("Generated decoding_tables.odin successfully!") - } else { - fmt.eprintln("Failed to write decoding_tables.odin") - } -} - -generate_header :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `package rexcode_x86 - -// ============================================================================= -// GENERATED FILE - DO NOT EDIT -// ============================================================================= -// -// Generated by gen_decode_tables.odin from ENC_TABLE -// Regenerate with: odin run tools/gen_decode_tables.odin -file && mv decoding_tables.odin -// - -// ============================================================================= -// ModR/M Lookup Table -// ============================================================================= - -// Precomputed extraction of mod, reg, rm fields from ModR/M byte -ModRM_Info :: struct #packed { - mod: u8, // bits [7:6] - addressing mode - reg: u8, // bits [5:3] - register or opcode extension - rm: u8, // bits [2:0] - register or memory - has_sib: bool, // rm==4 && mod!=3 (SIB byte follows) - disp_size: u8, // displacement size: 0, 1, or 4 bytes -} - -`) -} - -generate_modrm_table :: proc(sb: ^strings.Builder) { - strings.write_string(sb, "@(rodata)\n") - strings.write_string(sb, "MODRM_TABLE := [256]ModRM_Info{\n") - - for i in 0..<256 { - modrm := u8(i) - mod := (modrm >> 6) & 0x3 - reg := (modrm >> 3) & 0x7 - rm := modrm & 0x7 - - has_sib := (rm == 4) && (mod != 3) - - disp_size: u8 = 0 - if mod == 0 && rm == 5 { - disp_size = 4 // RIP-relative or disp32 - } else if mod == 1 { - disp_size = 1 - } else if mod == 2 { - disp_size = 4 - } - - if i % 4 == 0 { - strings.write_string(sb, "\t") - } - has_sib_str := has_sib ? " true" : "false" - fmt.sbprintf(sb, "{{%d, %d, %d, %s, %d}}, ", mod, reg, rm, has_sib_str, disp_size) - if (i + 1) % 4 == 0 { - strings.write_string(sb, "\n") - } - } - - strings.write_string(sb, "}\n\n") -} - -generate_sib_table :: proc(sb: ^strings.Builder) { - strings.write_string(sb, `// ============================================================================= -// SIB Lookup Table -// ============================================================================= - -// Precomputed extraction of scale, index, base fields from SIB byte -SIB_Info :: struct #packed { - scale: u8, // 1, 2, 4, or 8 - index: u8, // index register (0-7, or 0xFF if none when index==4) - base: u8, // base register (0-7, or 0xFF for special cases) -} - -`) - strings.write_string(sb, "@(rodata)\n") - strings.write_string(sb, "SIB_TABLE := [256]SIB_Info{\n") - - for i in 0..<256 { - sib := u8(i) - scale_bits := (sib >> 6) & 0x3 - index := (sib >> 3) & 0x7 - base := sib & 0x7 - - scale: u8 = 1 << scale_bits // 0->1, 1->2, 2->4, 3->8 - - // index == 4 means no index register - index_out := index - if index == 4 { - index_out = 0xFF - } - - fmt.sbprintf(sb, "\t{{%d, % 3d, %d}},", scale, index_out, base) - if (i + 1) % 4 == 0 { - strings.write_string(sb, "\n") - } - } - - strings.write_string(sb, "}\n\n") -} - -// Collected entry for sorting and output -Collected_Entry :: struct { - esc: x86.Escape, - prefix: u8, - opcode: u8, - ext: u8, // 0xFF if not using modrm_reg_ext - mnemonic: x86.Mnemonic, - ops: [4]x86.Operand_Type, - enc: [4]x86.Operand_Encoding, - flags: x86.Encoding_Flags, - vex_w: x86.VEX_W, - vex_l: x86.VEX_L, -} - -generate_opcode_tables :: proc(sb: ^strings.Builder) { - // Collect all entries from ENC_TABLE - legacy_entries: [dynamic]Collected_Entry - vex_entries: [dynamic]Collected_Entry - evex_entries: [dynamic]Collected_Entry - - for mnemonic in x86.Mnemonic { - encodings := x86.ENCODING_TABLE[mnemonic] - for enc in encodings { - entry := Collected_Entry{ - esc = enc.flags.esc, - prefix = enc.flags.prefix, - opcode = enc.opcode, - ext = enc.flags.modrm_reg_ext ? enc.ext : 0xFF, - mnemonic = enc.mnemonic, - ops = enc.ops, - enc = enc.enc, - flags = enc.flags, - vex_w = enc.flags.vex_w, - vex_l = enc.flags.vex_l, - } - - if enc.flags.vex_type == .VEX { - append(&vex_entries, entry) - } else if enc.flags.vex_type == .EVEX { - append(&evex_entries, entry) - } else { - append(&legacy_entries, entry) - } - } - } - - // Sort entries by (esc, prefix, opcode, ext) for efficient lookup - entry_less :: proc(a, b: Collected_Entry) -> bool { - if a.esc != b.esc { return int(a.esc) < int(b.esc) } - if a.prefix != b.prefix { return a.prefix < b.prefix } - if a.opcode != b.opcode { return a.opcode < b.opcode } - return a.ext < b.ext - } - - slice.sort_by(legacy_entries[:], entry_less) - slice.sort_by(vex_entries[:], entry_less) - slice.sort_by(evex_entries[:], entry_less) - - fmt.printf("Legacy entries: %d\n", len(legacy_entries)) - fmt.printf("VEX entries: %d\n", len(vex_entries)) - fmt.printf("EVEX entries: %d\n", len(evex_entries)) - - // Generate decode entry type - strings.write_string(sb, `// ============================================================================= -// Decode Entry -// ============================================================================= - -// Information needed to decode an instruction given its opcode bytes -Decode_Entry :: struct { - esc: Escape, // escape sequence used to find this entry - prefix: u8, // mandatory prefix (0=none, 1=66, 2=F3, 3=F2) - opcode: u8, // primary opcode byte - ext: u8, // ModR/M reg extension (0-7) or 0xFF if not used - mnemonic: Mnemonic, - ops: [4]Operand_Type, // operand types - enc: [4]Operand_Encoding, // operand encodings - flags: Encoding_Flags, -} - -`) - - // Generate legacy table - fmt.sbprintfln(sb, "// Legacy decode entries: %d", len(legacy_entries)) - strings.write_string(sb, "@(rodata)\n") - fmt.sbprintfln(sb, "LEGACY_DECODE_ENTRIES := [%d]Decode_Entry{{", len(legacy_entries)) - max_legacy_decode_entries_name := 0 - for entry in legacy_entries { - max_legacy_decode_entries_name = max(max_legacy_decode_entries_name, len(reflect.enum_string(entry.mnemonic))) - } - for entry in legacy_entries { - write_decode_entry(sb, entry, max_legacy_decode_entries_name) - } - strings.write_string(sb, "}\n\n") - - // Generate VEX table with additional vex_w, vex_l fields - strings.write_string(sb, `// ============================================================================= -// VEX Decode Entry -// ============================================================================= - -VEX_Decode_Entry :: struct { - esc: Escape, - prefix: u8, - opcode: u8, - ext: u8, - vex_w: VEX_W, - vex_l: VEX_L, - mnemonic: Mnemonic, - ops: [4]Operand_Type, - enc: [4]Operand_Encoding, - flags: Encoding_Flags, -} - -`) - - fmt.sbprintfln(sb, "// VEX decode entries: %d", len(vex_entries)) - strings.write_string(sb, "@(rodata)\n") - fmt.sbprintfln(sb, "VEX_DECODE_ENTRIES := [%d]VEX_Decode_Entry{{", len(vex_entries)) - max_vex_decode_entries_name := 0 - for entry in vex_entries { - max_vex_decode_entries_name = max(max_vex_decode_entries_name, len(reflect.enum_string(entry.mnemonic))) - } - for entry in vex_entries { - write_vex_decode_entry(sb, entry, max_vex_decode_entries_name) - } - strings.write_string(sb, "}\n\n") - - // Generate EVEX table - fmt.sbprintfln(sb, "// EVEX decode entries: %d", len(evex_entries)) - strings.write_string(sb, "@(rodata)\n") - fmt.sbprintfln(sb, "EVEX_DECODE_ENTRIES := [%d]VEX_Decode_Entry{{", len(evex_entries)) - max_evex_decode_entries_name := 0 - for entry in vex_entries { - max_evex_decode_entries_name = max(max_evex_decode_entries_name, len(reflect.enum_string(entry.mnemonic))) - } - for entry in evex_entries { - write_vex_decode_entry(sb, entry, max_evex_decode_entries_name) - } - strings.write_string(sb, "}\n\n") - - // Generate index tables for O(1) lookup by opcode - generate_index_tables(sb, legacy_entries[:]) - - // Generate VEX/EVEX index tables - generate_vex_index_tables(sb, vex_entries[:], "VEX") - generate_vex_index_tables(sb, evex_entries[:], "EVEX") -} - -print_enum_buffered :: proc(sb: ^strings.Builder, x: $T, max_name: int, comma: bool) { - fmt.sbprintf(sb, ".%v", x) - if comma { - strings.write_string(sb, ", ") - } else { - return - } - for n := max_name-len(reflect.enum_string(x)); n > 0; n -= 1 { - strings.write_byte(sb, ' ') - } -} -write_decode_entry :: proc(sb: ^strings.Builder, entry: Collected_Entry, max_entries_name: int) { - strings.write_string(sb, "\t{") - print_enum_buffered(sb, entry.esc, 5, true) - fmt.sbprintf(sb, "%d, ", entry.prefix) - fmt.sbprintf(sb, "0x%02X, ", entry.opcode) - fmt.sbprintf(sb, "0x%02X, ", entry.ext) - print_enum_buffered(sb, entry.mnemonic, max_entries_name, true) - - // ops - strings.write_string(sb, "{") - for op, i in entry.ops { - print_enum_buffered(sb, op, 9, i+1 < len(entry.ops)) - } - strings.write_string(sb, "}, ") - - // enc - strings.write_string(sb, "{") - for enc, i in entry.enc { - print_enum_buffered(sb, enc, 4, i+1 < len(entry.enc)) - } - strings.write_string(sb, "}, ") - - // flags - write_enc_flags(sb, entry.flags) - - strings.write_string(sb, "},\n") -} - -write_vex_decode_entry :: proc(sb: ^strings.Builder, entry: Collected_Entry, max_entries_name: int) { - strings.write_string(sb, "\t{") - print_enum_buffered(sb, entry.esc, 5, true) - fmt.sbprintf(sb, "%d, ", entry.prefix) - fmt.sbprintf(sb, "0x%02X, ", entry.opcode) - fmt.sbprintf(sb, "0x%02X, ", entry.ext) - print_enum_buffered(sb, entry.vex_w, 4, true) - print_enum_buffered(sb, entry.vex_l, 4, true) - print_enum_buffered(sb, entry.mnemonic, max_entries_name, true) - - // ops - strings.write_string(sb, "{") - for op, i in entry.ops { - print_enum_buffered(sb, op, 8, i+1 < len(entry.enc)) - } - strings.write_string(sb, "}, ") - - // enc - strings.write_string(sb, "{") - for enc, i in entry.enc { - print_enum_buffered(sb, enc, 4, i+1 < len(entry.enc)) - } - strings.write_string(sb, "}, ") - - // flags - write_enc_flags(sb, entry.flags) - - strings.write_string(sb, "},\n") -} - -write_enc_flags :: proc(sb: ^strings.Builder, flags: x86.Encoding_Flags) { - parts: [dynamic]string - defer delete(parts) - - if flags.esc != .NONE { - append(&parts, fmt.tprintf("esc=.%v", flags.esc)) - } - if flags.prefix != 0 { - append(&parts, fmt.tprintf("prefix=%d", flags.prefix)) - } - if flags.vex_type != .NONE { - append(&parts, fmt.tprintf("vex_type=.%v", flags.vex_type)) - } - if flags.vex_w != .WIG { - append(&parts, fmt.tprintf("vex_w=.%v", flags.vex_w)) - } - if flags.vex_l != .LIG { - append(&parts, fmt.tprintf("vex_l=.%v", flags.vex_l)) - } - if flags.default_64 { - append(&parts, "default_64=true") - } - if flags.force_rex_w { - append(&parts, "force_rex_w=true") - } - if flags.no_rex { - append(&parts, "no_rex=true") - } - if flags.lock_ok { - append(&parts, "lock_ok=true") - } - if flags.rep_ok { - append(&parts, "rep_ok=true") - } - if flags.modrm_reg_ext { - append(&parts, "modrm_reg_ext=true") - } - - if len(parts) == 0 { - strings.write_string(sb, "{}") - } else { - strings.write_string(sb, "{") - for part, i in parts { - if i > 0 { strings.write_string(sb, ", ") } - strings.write_string(sb, part) - } - strings.write_string(sb, "}") - } -} - -generate_vex_index_tables :: proc(sb: ^strings.Builder, entries: []Collected_Entry, name: string) { - // Build index ranges for each (esc, prefix, opcode) combination for VEX/EVEX - // Escape 0=0F, 1=0F38, 2=0F3A (VEX only uses these) - // Prefix 0-3 as usual - - strings.write_string(sb, fmt.tprintf(`// ============================================================================= -// %s Index Tables for O(1) Opcode Lookup -// ============================================================================= - -// Indexed by [esc_idx][prefix][opcode] where esc_idx: 0=0F, 1=0F38, 2=0F3A -`, name)) - - for esc_idx in 0..<3 { - esc: x86.Escape - esc_name: string - switch esc_idx { - case 0: esc = ._0F; esc_name = "0F" - case 1: esc = ._0F38; esc_name = "0F38" - case 2: esc = ._0F3A; esc_name = "0F3A" - } - - strings.write_string(sb, "@(rodata)\n") - fmt.sbprintfln(sb, "%s_INDEX_%s := [4][256]Decode_Index{{", name, esc_name) - - for prefix in 0..<4 { - is_empty := true - for opcode in 0..<256 { - start: u16 = 0 - count: u8 = 0 - found_start := false - - for entry, idx in entries { - if entry.esc == esc && entry.prefix == u8(prefix) && entry.opcode == u8(opcode) { - if !found_start { - start = u16(idx) - found_start = true - } - count += 1 - } else if found_start { - break - } - } - - if count > 0 { - is_empty = false - break - } - } - - - fmt.sbprintf(sb, "\t%d = {{ /* prefix = ", prefix) - switch prefix { - case 0: strings.write_string(sb, "none") - case 1: strings.write_string(sb, "66") - case 2: strings.write_string(sb, "F3") - case 3: strings.write_string(sb, "F2") - } - - strings.write_string(sb, " */") - if is_empty { - strings.write_string(sb, " },\n") - } else { - strings.write_string(sb, "\n") - for opcode in 0..<256 { - start: u16 = 0 - count: u8 = 0 - found_start := false - - for entry, idx in entries { - if entry.esc == esc && entry.prefix == u8(prefix) && entry.opcode == u8(opcode) { - if !found_start { - start = u16(idx) - found_start = true - } - count += 1 - } else if found_start { - break - } - } - - if count > 0 { - fmt.sbprintfln(sb, "\t\t0x%02X = {{% 3d, % 2d}},", opcode, start, count) - } - } - - strings.write_string(sb, "\t},\n") - } - } - - strings.write_string(sb, "}\n\n") - } -} - -generate_index_tables :: proc(sb: ^strings.Builder, entries: []Collected_Entry) { - // Build index ranges for each (esc, prefix, opcode) combination - // This allows O(1) lookup to find the start/end indices in LEGACY_DECODE_ENTRIES - - strings.write_string(sb, `// ============================================================================= -// Index Tables for O(1) Opcode Lookup -// ============================================================================= - -// Each entry contains (start_index, count) into LEGACY_DECODE_ENTRIES -// Indexed by [esc][prefix][opcode] -Decode_Index :: struct { - start: u16, // start index in LEGACY_DECODE_ENTRIES - count: u8, // number of entries -} - -`) - - // Generate for each escape sequence - for esc in x86.Escape { - esc_name: string - switch esc { - case .NONE: esc_name = "LEGACY" - case ._0F: esc_name = "ESC_0F" - case ._0F38: esc_name = "ESC_0F38" - case ._0F3A: esc_name = "ESC_0F3A" - } - - strings.write_string(sb, "@(rodata)\n") - fmt.sbprintfln(sb, "DECODE_INDEX_%s := [4][256]Decode_Index{{", esc_name) - - for prefix in 0..<4 { - strings.write_string(sb, "\t{ // prefix = ") - switch prefix { - case 0: strings.write_string(sb, "none\n") - case 1: strings.write_string(sb, "66\n") - case 2: strings.write_string(sb, "F3\n") - case 3: strings.write_string(sb, "F2\n") - } - - for opcode in 0..<256 { - // Find start and count for this (esc, prefix, opcode) - start: u16 = 0 - count: u8 = 0 - found_start := false - - for entry, idx in entries { - if entry.esc == esc && entry.prefix == u8(prefix) && entry.opcode == u8(opcode) { - if !found_start { - start = u16(idx) - found_start = true - } - count += 1 - } else if found_start { - // Entries are sorted, so we've passed all matching entries - break - } - } - - if count > 0 { - fmt.sbprintfln(sb, "\t\t0x%02X = {{% 4d, % 2d}},", opcode, start, count) - } - } - - strings.write_string(sb, "\t},\n") - } - - strings.write_string(sb, "}\n\n") - } -} diff --git a/core/rexcode/x86/tools/gen_mnemonic_builders.odin b/core/rexcode/x86/tools/gen_mnemonic_builders.odin index 6f70e14d7..e67828eba 100644 --- a/core/rexcode/x86/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/x86/tools/gen_mnemonic_builders.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -41,6 +43,8 @@ Proc_Entry :: struct { proc_name: string, } +GEN_ATTRIB :: "// rexcode · Brendan Punsky (dotbmp@github), original author\n\n" + main :: proc() { fmt.println("Generating mnemonic builders from ENCODING_TABLE...") @@ -65,7 +69,8 @@ main :: proc() { for mnemonic in x86.Mnemonic { if mnemonic == .INVALID { continue } - encodings := x86.ENCODING_TABLE[mnemonic] + _run := x86.ENCODE_RUNS[u16(mnemonic)] + encodings := x86.ENCODE_FORMS[_run.start:][:_run.count] if len(encodings) == 0 { continue } for enc in encodings { @@ -197,7 +202,7 @@ main :: proc() { output := strings.to_string(sb) - err := os.write_entire_file("mnemonic_builders.odin", transmute([]u8)output) + err := os.write_entire_file("mnemonic_builders.odin", transmute([]u8)strings.concatenate({GEN_ATTRIB, output})) if err == nil { fmt.println("Generated mnemonic_builders.odin successfully!") fmt.printf("Total mnemonics with builders: %d\n", len(mnemonic_list)) diff --git a/core/rexcode/x86/tools/verify_against_llvm.odin b/core/rexcode/x86/tools/verify_against_llvm.odin index 9958b894e..c58d596f0 100644 --- a/core/rexcode/x86/tools/verify_against_llvm.odin +++ b/core/rexcode/x86/tools/verify_against_llvm.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main import "core:fmt" diff --git a/core/rexcode/x86/tools/verify_tables.odin b/core/rexcode/x86/tools/verify_tables.odin index 4e6e5287d..f4b4a0a1f 100644 --- a/core/rexcode/x86/tools/verify_tables.odin +++ b/core/rexcode/x86/tools/verify_tables.odin @@ -1,3 +1,5 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + package main // ============================================================================= @@ -79,7 +81,8 @@ main :: proc() { // Check that each entry in LEGACY_DECODE_ENTRIES corresponds to something in ENC_TABLE for entry in x86.LEGACY_DECODE_ENTRIES { // Find matching encoding in ENC_TABLE - encodings := x86.ENCODING_TABLE[entry.mnemonic] + _run := x86.ENCODE_RUNS[u16(entry.mnemonic)] + encodings := x86.ENCODE_FORMS[_run.start:][:_run.count] found := false for enc in encodings { if enc.opcode == entry.opcode && @@ -130,10 +133,10 @@ main :: proc() { for tc in test_cases { idx: x86.Decode_Index switch tc.esc { - case .NONE: idx = x86.DECODE_INDEX_LEGACY[tc.prefix][tc.opcode] - case ._0F: idx = x86.DECODE_INDEX_ESC_0F[tc.prefix][tc.opcode] - case ._0F38: idx = x86.DECODE_INDEX_ESC_0F38[tc.prefix][tc.opcode] - case ._0F3A: idx = x86.DECODE_INDEX_ESC_0F3A[tc.prefix][tc.opcode] + case .NONE: idx = x86.DECODE_INDEX_LEGACY[(int(tc.prefix) << 8) | int(tc.opcode)] + case ._0F: idx = x86.DECODE_INDEX_ESC_0F[(int(tc.prefix) << 8) | int(tc.opcode)] + case ._0F38: idx = x86.DECODE_INDEX_ESC_0F38[(int(tc.prefix) << 8) | int(tc.opcode)] + case ._0F3A: idx = x86.DECODE_INDEX_ESC_0F3A[(int(tc.prefix) << 8) | int(tc.opcode)] } if idx.count == 0 {