From c67282dfbd2c07c6a95eae336e4b66d5f233722b Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 19:29:20 -0400 Subject: [PATCH] rexcode/arm64: an instruction can hold five operands SME's outer products take five -- `smopa za0.s, p0/m, p1/m, z0.b, z1.b` -- and Instruction held four, so the 14 forms in that family could not be represented at all, let alone printed. They named one vector where the instruction multiplies two. Five Operands is 55 bytes, which is odd, so Mnemonic's alignment costs one more; three bytes of padding still land Instruction on exactly one 64-byte cache line, as before. Encoding and Decode_Entry each grow by two. The tile number was wrong as well: it sits in the low bits, as wide as the element size leaves room for -- three for .d down to none for .b -- not at bits 23:22 where the encoding read it. Every MOP form named a tile it was not writing. Note for anyone regenerating: tablegen re-emits tables.odin from a template inside gen.odin, so a struct change there has to go in the template, and the package has to compile before tablegen can run at all. Same for the builders. SVE/SME2 against llvm-mc: 697 byte-exact and 0 mismatched, of 704. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/clobber_types.odin | 2 +- core/rexcode/isa/arm64/decoder.odin | 12 +- core/rexcode/isa/arm64/encoder.odin | 24 +- core/rexcode/isa/arm64/encoding_types.odin | 6 +- core/rexcode/isa/arm64/instructions.odin | 25 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 3832 ++++++------ core/rexcode/isa/arm64/tablegen/gen.odin | 20 +- .../tablegen/generated/decode_tables.odin | 5346 ++++++++--------- .../tablegen/generated/encode_tables.odin | 5342 ++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 5342 ++++++++-------- core/rexcode/isa/arm64/tables.odin | 6 +- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 53420 -> 58762 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 53460 -> 58806 bytes .../isa/arm64/tests/pipeline_smoke.odin | 47 +- .../arm64/tools/gen_mnemonic_builders.odin | 12 +- 15 files changed, 10014 insertions(+), 10002 deletions(-) diff --git a/core/rexcode/isa/arm64/clobber_types.odin b/core/rexcode/isa/arm64/clobber_types.odin index 406094291..e9800c032 100644 --- a/core/rexcode/isa/arm64/clobber_types.odin +++ b/core/rexcode/isa/arm64/clobber_types.odin @@ -1,6 +1,6 @@ package rexcode_arm64 -Operand_Set :: distinct bit_set[0..<4; u8] +Operand_Set :: distinct bit_set[0..<5; u8] NZCV_Flags :: distinct bit_set[NZCV_Flag; u8] NZCV_Flag :: enum u8 { diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 7eeed8420..94c98341b 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -128,6 +128,10 @@ decode_one_inline :: #force_inline proc "contextless" ( if entry.ops[3] != .NONE { inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3]) cnt_used = 4 + if entry.ops[4] != .NONE { + inst.ops[4] = extract_operand_inline(word, pc, entry.ops[4], entry.enc[4]) + cnt_used = 5 + } } } } @@ -572,16 +576,16 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- SME ZA tile fields ---- case .ZA_TILE_NUM_B: - return Operand{reg = Register(REG_ZA | 0), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x0)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_H: - return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x1)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x1)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_S: - return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x3)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x3)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_D: - return Operand{reg = Register(REG_ZA | u16((word >> 21) & 0x7)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x7)), kind = .REGISTER, size = za_elem_for_type(ot)} case .SME_PATTERN_FIELD: return Operand{immediate = i64((word >> 5) & 0xF), kind = .IMMEDIATE, size = 1} diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 1d445803d..58a5699d3 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -145,6 +145,7 @@ encode_one_inline :: #force_inline proc( if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], form, pc, inst_idx, relocs, inst) } if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], form, pc, inst_idx, relocs, inst) } if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], form, pc, inst_idx, relocs, inst) } + if form.enc[4] != .NONE { word |= pack_operand_inline(&inst.ops[4], form.enc[4], form, pc, inst_idx, relocs, inst) } return word, true } @@ -155,7 +156,8 @@ encoding_matches_inline :: #force_inline proc "contextless" ( return operand_matches_inline(&inst.ops[0], form.ops[0], form) && operand_matches_inline(&inst.ops[1], form.ops[1], form) && operand_matches_inline(&inst.ops[2], form.ops[2], form) && - operand_matches_inline(&inst.ops[3], form.ops[3], form) + operand_matches_inline(&inst.ops[3], form.ops[3], form) && + operand_matches_inline(&inst.ops[4], form.ops[4], form) } @(private="file") @@ -721,17 +723,21 @@ pack_operand_inline :: #force_inline proc( // SME ZA tile number fields (position depends on element size). case .ZA_TILE_NUM_B: - // ZA0.B only -- nothing to encode (single tile of byte form). - return 0 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x0 case .ZA_TILE_NUM_H: - // ZA0.H..ZA1.H -- 1-bit tile number at bit 22. - return (u32(op.immediate) & 0x1) << 22 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x1 case .ZA_TILE_NUM_S: - // ZA0.S..ZA3.S -- 2-bit tile number at bits 23:22. - return (u32(op.immediate) & 0x3) << 22 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x3 case .ZA_TILE_NUM_D: - // ZA0.D..ZA7.D -- 3-bit tile number at bits 23:21. - return (u32(op.immediate) & 0x7) << 21 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x7 case .SME_PATTERN_FIELD: // 4-bit SME pattern/list at bits 8:5 (ZERO instruction list mask). return (u32(op.immediate) & 0xF) << 5 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 50f2ec90d..b0f8092e4 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -459,11 +459,11 @@ Operand_Encoding :: enum u8 { Encoding :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 -- static field pattern mask: u32, // 4 -- which bits are static feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Encoding) == 20) +#assert(size_of(Encoding) == 22) diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index 26ad8bd3f..f40d31a45 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -28,12 +28,13 @@ Instruction_Flags :: bit_field u8 { // The spare bytes are free: they cost nothing over a 48-byte struct that // straddles, and new fields land in them without changing the layout. Instruction :: struct #align(64) { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) = 44 + ops: [5]Operand `fmt:"v,operand_count"`, // 5 * size_of(Operand) = 55 mnemonic: Mnemonic, // 2 operand_count: u8, // 1 flags: Instruction_Flags, // 1 length: u8, // 1 -- always 4 - _: [15]u8, + // 55 is odd, so mnemonic's alignment costs a byte here; 3 more reach 64. + _: [3]u8, } #assert(size_of(Instruction) == 64) #assert(align_of(Instruction) == 64) @@ -52,70 +53,70 @@ inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction { @(require_results) inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 1, length = 4, - ops = {op_reg(r), {}, {}, {}}} + ops = {op_reg(r), {}, {}, {}, {}}} } // 2-register (e.g. CLZ, RBIT). @(require_results) inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rd), op_reg(rn), {}, {}}} + ops = {op_reg(rd), op_reg(rn), {}, {}, {}}} } // 3-register (e.g. ADD shifted, MUL, UDIV, ASRV). @(require_results) inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}}} + ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}, {}}} } // 4-register R4-type (MADD, MSUB, SMADDL, ...). @(require_results) inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 4, length = 4, - ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra)}} + ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra), {}}} } // 2-register + immediate (e.g. ADD imm). @(require_results) inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register, imm: i64) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_reg(rn), op_imm(imm), {}}} + ops = {op_reg(rd), op_reg(rn), op_imm(imm), {}, {}}} } // 1-register + immediate (e.g. MOVZ). @(require_results) inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rd), op_imm(imm), {}, {}}} + ops = {op_reg(rd), op_imm(imm), {}, {}, {}}} } // MOVZ/MOVN/MOVK with explicit hw shift (0/16/32/48). @(require_results) inst_mov_imm :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64, hw: u8) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_imm(imm), op_imm(i64(hw), 1), {}}} + ops = {op_reg(rd), op_imm(imm), op_imm(i64(hw), 1), {}, {}}} } // Load/store register: Rt + memory. @(require_results) inst_ldst :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, mm: Memory) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rt), op_mem(mm), {}, {}}} + ops = {op_reg(rt), op_mem(mm), {}, {}, {}}} } // Load/store pair: Rt, Rt2, memory. @(require_results) inst_ldp_stp :: #force_inline proc "contextless" (m: Mnemonic, rt, rt2: Register, mm: Memory) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rt), op_reg(rt2), op_mem(mm), {}}} + ops = {op_reg(rt), op_reg(rt2), op_mem(mm), {}, {}}} } // PC-relative branch (B, BL). @(require_results) inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction { return Instruction{mnemonic = m, operand_count = 1, length = 4, - ops = {op_label(label_id, 4), {}, {}, {}}} + ops = {op_label(label_id, 4), {}, {}, {}, {}}} } // NOTE: the conditional branches, inst_cbz (+cbnz), inst_tbz (+tbnz) and diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index b38fa7d59..606deca71 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -22,23 +22,23 @@ package rexcode_arm64 // ============================================================================= inst_add_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD, dst, src, imm) } -inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_add_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_add_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_add_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_add_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_add_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_add_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_add_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_add_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_add_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_add_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_add_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } +inst_add_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_add_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_add_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_add_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_add_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_add_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_add_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_add_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_add_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_add_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_add_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -58,26 +58,26 @@ emit_add_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_add_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_add_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } -inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } emit_adds_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_r_r_i(dst, src, imm)) } emit_adds_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_adds_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } inst_sub_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB, dst, src, imm) } -inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_sub_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_sub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_sub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } +inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_sub_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_sub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_sub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -94,29 +94,29 @@ emit_sub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_sub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } -inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } emit_subs_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_r_r_i(dst, src, imm)) } emit_subs_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_subs_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } -inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } -inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } -inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } -inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } -inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } -inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_and_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_and_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } emit_and_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v16b_v16b_v16b(dst, src, src2)) } @@ -125,20 +125,20 @@ emit_and_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_and_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_and_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_and_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_ands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } emit_ands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } -inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_orr_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } @@ -147,14 +147,14 @@ emit_orr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_orr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_orr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_orr_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } -inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_eor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_eor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } emit_eor_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v16b_v16b_v16b(dst, src, src2)) } @@ -163,13 +163,13 @@ emit_eor_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_eor_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_eor_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_eor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_bic_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_bic_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bic_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v16b_v16b_v16b(dst, src, src2)) } emit_bic_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -177,23 +177,23 @@ emit_bic_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_bic_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_bic_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_bic_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_bics_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bics_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_orn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } emit_orn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } -inst_lsl_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsl_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsl_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsl_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsl_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsl_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsl_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsl_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } emit_lsl_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -202,10 +202,10 @@ emit_lsl_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_lsl_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } -inst_lsr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } emit_lsr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -214,10 +214,10 @@ emit_lsr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_lsr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } -inst_asr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_asr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_asr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_asr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_asr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_asr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_asr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_asr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } emit_asr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -230,14 +230,14 @@ inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -inst_udiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_udiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_udiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_udiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } emit_udiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_udiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -inst_sdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } emit_sdiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sdiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } @@ -254,36 +254,36 @@ emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Inst inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -inst_smulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } emit_smulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_smulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -inst_umulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } emit_umulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_umulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } -inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_clz_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_clz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_clz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_clz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_clz_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_clz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_clz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_clz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } emit_clz_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8b_v8b(dst, src)) } emit_clz_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v16b_v16b(dst, src)) } @@ -296,16 +296,16 @@ emit_clz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_clz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zs_p_zs(rz, rz2, rz3)) } emit_clz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zd_p_zd(rz, rz2, rz3)) } inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } -inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cls_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_cls_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_cls_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_cls_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cls_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_cls_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_cls_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_cls_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } emit_cls_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8b_v8b(dst, src)) } emit_cls_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v16b_v16b(dst, src)) } @@ -318,17 +318,17 @@ emit_cls_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_cls_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zs_p_zs(rz, rz2, rz3)) } emit_cls_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zd_p_zd(rz, rz2, rz3)) } inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } -inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } emit_rbit_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v8b_v8b(dst, src)) } emit_rbit_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v16b_v16b(dst, src)) } inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}}} } -inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}}} } -inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}}} } -inst_rev_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } +inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}, {}}} } +inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}, {}}} } +inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}, {}}} } +inst_rev_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } emit_rev_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zb_zb(rz, rz2)) } emit_rev_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zh_zh(rz, rz2)) } @@ -336,48 +336,48 @@ emit_rev_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_rev_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zd_zd(rz, rz2)) } emit_rev_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_pb_pb(rz, rz2)) } inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } -inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } emit_rev16_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v8b_v8b(dst, src)) } emit_rev16_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v16b_v16b(dst, src)) } inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } -inst_rev32_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev32_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_rev32_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_rev32_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_rev32_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev32_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_rev32_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_rev32_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } emit_rev32_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8b_v8b(dst, src)) } emit_rev32_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v16b_v16b(dst, src)) } emit_rev32_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v4h_v4h(dst, src)) } emit_rev32_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8h_v8h(dst, src)) } -inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } -inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } -inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } -inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } -inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond), {}}} } +inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond), {}}} } emit_ccmp_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_r_r_i_c(dst, src, imm, cond)) } emit_ccmp_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_r_i_i_c(dst, imm, imm2, cond)) } -inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond), {}}} } +inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond), {}}} } emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } -inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}, {}}} } emit_cset_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_cset_r_c(dst, cond)) } -inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}, {}}} } emit_csetm_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_csetm_r_c(dst, cond)) } -inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cinc_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinc_r_r_c(dst, src, cond)) } -inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cinv_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinv_r_r_c(dst, src, cond)) } -inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cneg_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cneg_r_r_c(dst, src, cond)) } -inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } +inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1), {}}} } emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } @@ -423,28 +423,28 @@ inst_b_al_l :: #force_inline proc "contextless" (label: u32) - emit_b_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_al_l(label)) } inst_b_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NV, label) } emit_b_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_nv_l(label)) } -inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } -inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } -inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}, {}}} } emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } -inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}, {}}} } emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } -inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } +inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } +inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } +inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } @@ -501,39 +501,39 @@ inst_sev_none :: #force_inline proc "contextless" () -> Instruct emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } -inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}}} } +inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}, {}}} } emit_mrs_r_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, sysreg: System_Register) { append(instructions, inst_mrs_r_s(dst, sysreg)) } -inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } -inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}}} } +inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}, {}}} } +inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}, {}}} } emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } emit_msr_s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, sysreg: System_Register, src: Register) { append(instructions, inst_msr_s_r(sysreg, src)) } -inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } -inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } -inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } -inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } -inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } -inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } -inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } -inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } inst_fmov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV, dst, src) } inst_fmov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV, dst, imm) } -inst_fmov_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } emit_fmov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_r_r(dst, src)) } emit_fmov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_r_i(dst, imm)) } emit_fmov_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v2s_i(dst, imm)) } @@ -542,14 +542,14 @@ emit_fmov_v2d_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmov_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v4h_i(dst, imm)) } emit_fmov_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v8h_i(dst, imm)) } inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } -inst_fabs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fabs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fabs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fabs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fabs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fabs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fabs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fabs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } emit_fabs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2s_v2s(dst, src)) } emit_fabs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4s_v4s(dst, src)) } @@ -560,14 +560,14 @@ emit_fabs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fabs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zs_p_zs(rz, rz2, rz3)) } emit_fabs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zd_p_zd(rz, rz2, rz3)) } inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } -inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fneg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fneg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fneg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fneg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fneg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fneg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } emit_fneg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2s_v2s(dst, src)) } emit_fneg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4s_v4s(dst, src)) } @@ -578,14 +578,14 @@ emit_fneg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fneg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zs_p_zs(rz, rz2, rz3)) } emit_fneg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zd_p_zd(rz, rz2, rz3)) } inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } -inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fsqrt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fsqrt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fsqrt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fsqrt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fsqrt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fsqrt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } emit_fsqrt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2s_v2s(dst, src)) } emit_fsqrt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4s_v4s(dst, src)) } @@ -596,15 +596,15 @@ emit_fsqrt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fsqrt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zs_p_zs(rz, rz2, rz3)) } emit_fsqrt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zd_p_zd(rz, rz2, rz3)) } inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } -inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fadd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fadd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fadd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fadd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } emit_fadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2s_v2s_v2s(dst, src, src2)) } emit_fadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v4s_v4s_v4s(dst, src, src2)) } @@ -616,15 +616,15 @@ emit_fadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fadd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fadd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } -inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fsub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fsub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fsub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fsub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } emit_fsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2s_v2s_v2s(dst, src, src2)) } emit_fsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v4s_v4s_v4s(dst, src, src2)) } @@ -636,15 +636,15 @@ emit_fsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fsub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fsub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } -inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } emit_fmul_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2s_v2s_v2s(dst, src, src2)) } emit_fmul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v4s_v4s_v4s(dst, src, src2)) } @@ -656,12 +656,12 @@ emit_fmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } -inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fdiv_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fdiv_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } emit_fdiv_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2s_v2s_v2s(dst, src, src2)) } emit_fdiv_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v4s_v4s_v4s(dst, src, src2)) } @@ -683,17 +683,17 @@ inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } -inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } -inst_fmax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } emit_fmax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2s_v2s_v2s(dst, src, src2)) } emit_fmax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4s_v4s_v4s(dst, src, src2)) } @@ -704,14 +704,14 @@ emit_fmax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } -inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } emit_fmin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2s_v2s_v2s(dst, src, src2)) } emit_fmin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4s_v4s_v4s(dst, src, src2)) } @@ -722,14 +722,14 @@ emit_fmin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } -inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmaxnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmaxnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmaxnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmaxnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } emit_fmaxnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4s_v4s_v4s(dst, src, src2)) } @@ -740,14 +740,14 @@ emit_fmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmaxnm_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmaxnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } -inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fminnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fminnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fminnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fminnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } emit_fminnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2s_v2s_v2s(dst, src, src2)) } emit_fminnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4s_v4s_v4s(dst, src, src2)) } @@ -760,11 +760,11 @@ emit_fminnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } -inst_scvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_scvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_scvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_scvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_scvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_scvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_scvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_scvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_scvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_scvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } emit_scvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v2s_v2s(dst, src)) } emit_scvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4s_v4s(dst, src)) } @@ -772,11 +772,11 @@ emit_scvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_scvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4h_v4h(dst, src)) } emit_scvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v8h_v8h(dst, src)) } inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } -inst_ucvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_ucvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_ucvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_ucvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_ucvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_ucvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_ucvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_ucvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_ucvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_ucvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } emit_ucvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v2s_v2s(dst, src)) } emit_ucvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4s_v4s(dst, src)) } @@ -784,11 +784,11 @@ emit_ucvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_ucvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4h_v4h(dst, src)) } emit_ucvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v8h_v8h(dst, src)) } inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } -inst_fcvtzs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtzs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtzs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtzs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtzs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtzs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtzs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtzs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtzs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtzs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } emit_fcvtzs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v2s_v2s(dst, src)) } emit_fcvtzs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4s_v4s(dst, src)) } @@ -796,11 +796,11 @@ emit_fcvtzs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtzs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4h_v4h(dst, src)) } emit_fcvtzs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v8h_v8h(dst, src)) } inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } -inst_fcvtzu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtzu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtzu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtzu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtzu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtzu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtzu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtzu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtzu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtzu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } emit_fcvtzu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v2s_v2s(dst, src)) } emit_fcvtzu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4s_v4s(dst, src)) } @@ -808,11 +808,11 @@ emit_fcvtzu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtzu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4h_v4h(dst, src)) } emit_fcvtzu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v8h_v8h(dst, src)) } inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } -inst_fcvtas_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtas_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtas_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtas_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtas_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtas_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtas_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtas_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtas_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtas_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } emit_fcvtas_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v2s_v2s(dst, src)) } emit_fcvtas_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4s_v4s(dst, src)) } @@ -820,11 +820,11 @@ emit_fcvtas_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtas_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4h_v4h(dst, src)) } emit_fcvtas_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v8h_v8h(dst, src)) } inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } -inst_fcvtau_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtau_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtau_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtau_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtau_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtau_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtau_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtau_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtau_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtau_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } emit_fcvtau_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v2s_v2s(dst, src)) } emit_fcvtau_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4s_v4s(dst, src)) } @@ -832,11 +832,11 @@ emit_fcvtau_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtau_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4h_v4h(dst, src)) } emit_fcvtau_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v8h_v8h(dst, src)) } inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } -inst_fcvtns_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtns_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtns_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtns_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtns_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtns_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtns_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtns_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtns_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtns_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } emit_fcvtns_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v2s_v2s(dst, src)) } emit_fcvtns_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4s_v4s(dst, src)) } @@ -844,11 +844,11 @@ emit_fcvtns_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtns_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4h_v4h(dst, src)) } emit_fcvtns_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v8h_v8h(dst, src)) } inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } -inst_fcvtnu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtnu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtnu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtnu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtnu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtnu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtnu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtnu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtnu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtnu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } emit_fcvtnu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v2s_v2s(dst, src)) } emit_fcvtnu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4s_v4s(dst, src)) } @@ -856,11 +856,11 @@ emit_fcvtnu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtnu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4h_v4h(dst, src)) } emit_fcvtnu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v8h_v8h(dst, src)) } inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } -inst_fcvtps_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtps_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtps_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtps_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtps_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtps_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtps_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtps_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtps_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtps_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } emit_fcvtps_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v2s_v2s(dst, src)) } emit_fcvtps_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4s_v4s(dst, src)) } @@ -868,11 +868,11 @@ emit_fcvtps_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtps_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4h_v4h(dst, src)) } emit_fcvtps_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v8h_v8h(dst, src)) } inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } -inst_fcvtpu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtpu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtpu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtpu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtpu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtpu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtpu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtpu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtpu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtpu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } emit_fcvtpu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v2s_v2s(dst, src)) } emit_fcvtpu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4s_v4s(dst, src)) } @@ -880,11 +880,11 @@ emit_fcvtpu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtpu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4h_v4h(dst, src)) } emit_fcvtpu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v8h_v8h(dst, src)) } inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } -inst_fcvtms_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtms_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtms_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtms_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtms_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtms_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtms_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtms_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtms_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtms_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } emit_fcvtms_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v2s_v2s(dst, src)) } emit_fcvtms_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4s_v4s(dst, src)) } @@ -892,11 +892,11 @@ emit_fcvtms_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtms_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4h_v4h(dst, src)) } emit_fcvtms_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v8h_v8h(dst, src)) } inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } -inst_fcvtmu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtmu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtmu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtmu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtmu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtmu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtmu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtmu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtmu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtmu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } emit_fcvtmu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v2s_v2s(dst, src)) } emit_fcvtmu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4s_v4s(dst, src)) } @@ -904,14 +904,14 @@ emit_fcvtmu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtmu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4h_v4h(dst, src)) } emit_fcvtmu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v8h_v8h(dst, src)) } inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } -inst_frinta_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinta_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frinta_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frinta_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frinta_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frinta_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frinta_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frinta_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } emit_frinta_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2s_v2s(dst, src)) } emit_frinta_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4s_v4s(dst, src)) } @@ -922,14 +922,14 @@ emit_frinta_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frinta_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zs_p_zs(rz, rz2, rz3)) } emit_frinta_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zd_p_zd(rz, rz2, rz3)) } inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } -inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinti_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frinti_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frinti_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frinti_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frinti_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frinti_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } emit_frinti_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2s_v2s(dst, src)) } emit_frinti_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4s_v4s(dst, src)) } @@ -940,14 +940,14 @@ emit_frinti_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frinti_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zs_p_zs(rz, rz2, rz3)) } emit_frinti_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zd_p_zd(rz, rz2, rz3)) } inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } -inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintm_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintm_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintm_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintm_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintm_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintm_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } emit_frintm_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2s_v2s(dst, src)) } emit_frintm_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4s_v4s(dst, src)) } @@ -958,14 +958,14 @@ emit_frintm_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintm_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zs_p_zs(rz, rz2, rz3)) } emit_frintm_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zd_p_zd(rz, rz2, rz3)) } inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } -inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintn_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintn_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintn_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintn_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintn_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintn_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } emit_frintn_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2s_v2s(dst, src)) } emit_frintn_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4s_v4s(dst, src)) } @@ -976,14 +976,14 @@ emit_frintn_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintn_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zs_p_zs(rz, rz2, rz3)) } emit_frintn_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zd_p_zd(rz, rz2, rz3)) } inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } -inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintp_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintp_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintp_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintp_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintp_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintp_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } emit_frintp_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2s_v2s(dst, src)) } emit_frintp_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4s_v4s(dst, src)) } @@ -994,14 +994,14 @@ emit_frintp_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintp_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zs_p_zs(rz, rz2, rz3)) } emit_frintp_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zd_p_zd(rz, rz2, rz3)) } inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } -inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } emit_frintx_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2s_v2s(dst, src)) } emit_frintx_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4s_v4s(dst, src)) } @@ -1012,14 +1012,14 @@ emit_frintx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zs_p_zs(rz, rz2, rz3)) } emit_frintx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zd_p_zd(rz, rz2, rz3)) } inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } -inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } emit_frintz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2s_v2s(dst, src)) } emit_frintz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4s_v4s(dst, src)) } @@ -1030,7 +1030,7 @@ emit_frintz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zs_p_zs(rz, rz2, rz3)) } emit_frintz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zd_p_zd(rz, rz2, rz3)) } inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } -inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } emit_tst_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_r_sh(dst, src, src_shift, src_amount)) } inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } @@ -1057,11 +1057,11 @@ inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } -inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem), {}}} } emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } -inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem), {}}} } emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } @@ -1273,9 +1273,9 @@ inst_bti_none :: #force_inline proc "contextless" () -> Instruct emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } -inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1), {}}} } emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } -inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1), {}}} } emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } @@ -1317,113 +1317,113 @@ inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } -inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aese_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aese_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_aese_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_v16b_v16b(dst, src)) } emit_aese_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aese_zb_zb_zb(rz, rz2, rz3)) } -inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_aesd_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_v16b_v16b(dst, src)) } emit_aesd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aesd_zb_zb_zb(rz, rz2, rz3)) } -inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesmc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesmc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_aesmc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_v16b_v16b(dst, src)) } emit_aesmc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesmc_zb_zb(rz, rz2)) } -inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesimc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesimc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_aesimc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_v16b_v16b(dst, src)) } emit_aesimc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesimc_zb_zb(rz, rz2)) } inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } -inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1c_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_v4s(dst, src, src2)) } -inst_sha1p_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1p_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1p_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_v4s(dst, src, src2)) } -inst_sha1m_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1m_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1m_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_v4s(dst, src, src2)) } -inst_sha1su0_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sha1su0_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sha1su0_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_v4s_v4s_v4s(dst, src, src2)) } -inst_sha1su1_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sha1su1_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sha1su1_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_v4s_v4s(dst, src)) } -inst_sha256h_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha256h_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha256h_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_v4s(dst, src, src2)) } -inst_sha256h2_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha256h2_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha256h2_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_v4s(dst, src, src2)) } -inst_sha256su0_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sha256su0_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sha256su0_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_v4s_v4s(dst, src)) } -inst_sha256su1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sha256su1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sha256su1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_v4s_v4s_v4s(dst, src, src2)) } -inst_sha512h_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +inst_sha512h_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}, {}}} } emit_sha512h_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_v2d(dst, src, src2)) } -inst_sha512h2_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +inst_sha512h2_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}, {}}} } emit_sha512h2_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_v2d(dst, src, src2)) } -inst_sha512su0_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_sha512su0_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_sha512su0_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_v2d_v2d(dst, src)) } -inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_sha512su1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_v2d_v2d_v2d(dst, src, src2)) } -inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_eor3_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3), {}}} } +inst_eor3_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_eor3_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } emit_eor3_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_bcax_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3), {}}} } +inst_bcax_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bcax_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } emit_bcax_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rax1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_v2d_v2d_v2d(dst, src, src2)) } -inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } -inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4)}} } +inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } +inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4), {}}} } emit_xar_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_v2d_v2d_v2d_i(dst, src, src2, imm)) } emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm3partw1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_v4s_v4s_v4s(dst, src, src2)) } -inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm3partw2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_v4s_v4s_v4s(dst, src, src2)) } -inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3)}} } +inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3), {}}} } emit_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_v4s_v4s_v4s_v4s(dst, src, src2, src3)) } -inst_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1a_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1b_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2a_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2b_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sm4e_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_v4s_v4s(dst, src)) } -inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm4ekey_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_v4s_v4s_v4s(dst, src, src2)) } -inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_pmull_v1q_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_1d(src), op_v_1d(src2), {}}} } +inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_pmull_v1q_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_1d(src), op_v_1d(src2), {}, {}}} } emit_pmull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v8h_v8b_v8b(dst, src, src2)) } emit_pmull_v1q_v1d_v1d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v1q_v1d_v1d(dst, src, src2)) } -inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_pmull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v8h_v16b_v16b(dst, src, src2)) } emit_pmull2_v1q_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v1q_v2d_v2d(dst, src, src2)) } inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -inst_bfcvt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_bfcvt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } emit_bfcvt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_zh_p_zs(rz, rz2, rz3)) } -inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfdot_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmmla_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmlalb_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmlalb_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmlalb_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmlalt_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmlalt_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmlalt_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_v4s_v8h_v8h(dst, src, src2)) } -inst_bfcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_bfcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } emit_bfcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_v4h_v4s(dst, src)) } -inst_bfcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_bfcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } emit_bfcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_v8h_v4s(dst, src)) } -inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_mul_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_mul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_mul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_mul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_mul_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_mul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_mul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_mul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_mul_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v16b_v16b_v16b(dst, src, src2)) } emit_mul_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v8h_v8h_v8h(dst, src, src2)) } emit_mul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v4s_v4s_v4s(dst, src, src2)) } @@ -1431,42 +1431,42 @@ emit_mul_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_mul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_mul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_mul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_mla_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mla_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_mla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_mla_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mla_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_mla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_mla_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8b_v8b_v8b(dst, src, src2)) } emit_mla_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v16b_v16b_v16b(dst, src, src2)) } emit_mla_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4h_v4h_v4h(dst, src, src2)) } emit_mla_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8h_v8h_v8h(dst, src, src2)) } emit_mla_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v2s_v2s_v2s(dst, src, src2)) } emit_mla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4s_v4s_v4s(dst, src, src2)) } -inst_mls_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_mls_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mls_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_mls_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mls_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_mls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_mls_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_mls_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mls_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_mls_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mls_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_mls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_mls_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8b_v8b_v8b(dst, src, src2)) } emit_mls_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v16b_v16b_v16b(dst, src, src2)) } emit_mls_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4h_v4h_v4h(dst, src, src2)) } emit_mls_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8h_v8h_v8h(dst, src, src2)) } emit_mls_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v2s_v2s_v2s(dst, src, src2)) } emit_mls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4s_v4s_v4s(dst, src, src2)) } -inst_neg_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_neg_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_neg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_neg_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_neg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_neg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_neg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } -inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_neg_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_neg_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_neg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_neg_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_neg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_neg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_neg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } +inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_neg_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v8b_v8b(dst, src)) } emit_neg_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v16b_v16b(dst, src)) } emit_neg_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v4h_v4h(dst, src)) } @@ -1479,17 +1479,17 @@ emit_neg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_neg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zs_p_zs(rz, rz2, rz3)) } emit_neg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zd_p_zd(rz, rz2, rz3)) } emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } -inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_abs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_abs_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_abs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_abs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_abs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_abs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_abs_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_abs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_abs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_abs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_abs_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v8b_v8b(dst, src)) } emit_abs_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v16b_v16b(dst, src)) } emit_abs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4h_v4h(dst, src)) } @@ -1501,89 +1501,89 @@ emit_abs_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_abs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zh_p_zh(rz, rz2, rz3)) } emit_abs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zs_p_zs(rz, rz2, rz3)) } emit_abs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zd_p_zd(rz, rz2, rz3)) } -inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_shadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_shadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_shadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_shadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_shadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_shadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_shadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8b_v8b_v8b(dst, src, src2)) } emit_shadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v16b_v16b_v16b(dst, src, src2)) } emit_shadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4h_v4h_v4h(dst, src, src2)) } emit_shadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8h_v8h_v8h(dst, src, src2)) } emit_shadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v2s_v2s_v2s(dst, src, src2)) } emit_shadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4s_v4s_v4s(dst, src, src2)) } -inst_uhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8b_v8b_v8b(dst, src, src2)) } emit_uhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v16b_v16b_v16b(dst, src, src2)) } emit_uhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4h_v4h_v4h(dst, src, src2)) } emit_uhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8h_v8h_v8h(dst, src, src2)) } emit_uhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v2s_v2s_v2s(dst, src, src2)) } emit_uhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_shsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_shsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_shsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_shsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_shsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_shsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_shsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_shsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_shsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_shsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_shsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_shsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_shsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8b_v8b_v8b(dst, src, src2)) } emit_shsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v16b_v16b_v16b(dst, src, src2)) } emit_shsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4h_v4h_v4h(dst, src, src2)) } emit_shsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8h_v8h_v8h(dst, src, src2)) } emit_shsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v2s_v2s_v2s(dst, src, src2)) } emit_shsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4s_v4s_v4s(dst, src, src2)) } -inst_uhsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uhsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uhsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uhsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uhsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uhsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uhsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uhsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uhsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uhsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uhsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uhsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uhsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8b_v8b_v8b(dst, src, src2)) } emit_uhsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v16b_v16b_v16b(dst, src, src2)) } emit_uhsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4h_v4h_v4h(dst, src, src2)) } emit_uhsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8h_v8h_v8h(dst, src, src2)) } emit_uhsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v2s_v2s_v2s(dst, src, src2)) } emit_uhsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4s_v4s_v4s(dst, src, src2)) } -inst_srhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_srhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_srhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_srhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_srhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_srhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_srhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_srhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_srhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_srhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_srhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_srhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_srhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8b_v8b_v8b(dst, src, src2)) } emit_srhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v16b_v16b_v16b(dst, src, src2)) } emit_srhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4h_v4h_v4h(dst, src, src2)) } emit_srhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8h_v8h_v8h(dst, src, src2)) } emit_srhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v2s_v2s_v2s(dst, src, src2)) } emit_srhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_urhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_urhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_urhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_urhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_urhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_urhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_urhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_urhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_urhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_urhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_urhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_urhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_urhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8b_v8b_v8b(dst, src, src2)) } emit_urhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v16b_v16b_v16b(dst, src, src2)) } emit_urhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4h_v4h_v4h(dst, src, src2)) } emit_urhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8h_v8h_v8h(dst, src, src2)) } emit_urhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v2s_v2s_v2s(dst, src, src2)) } emit_urhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_sqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v8b_v8b_v8b(dst, src, src2)) } emit_sqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v16b_v16b_v16b(dst, src, src2)) } emit_sqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1595,17 +1595,17 @@ emit_sqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zh_zh_zh(rz, rz2, rz3)) } emit_sqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zs_zs_zs(rz, rz2, rz3)) } emit_sqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zd_zd_zd(rz, rz2, rz3)) } -inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_uqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v8b_v8b_v8b(dst, src, src2)) } emit_uqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v16b_v16b_v16b(dst, src, src2)) } emit_uqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1617,17 +1617,17 @@ emit_uqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zh_zh_zh(rz, rz2, rz3)) } emit_uqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zs_zs_zs(rz, rz2, rz3)) } emit_uqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zd_zd_zd(rz, rz2, rz3)) } -inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v8b_v8b_v8b(dst, src, src2)) } emit_sqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v16b_v16b_v16b(dst, src, src2)) } emit_sqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1639,17 +1639,17 @@ emit_sqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zh_zh_zh(rz, rz2, rz3)) } emit_sqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zs_zs_zs(rz, rz2, rz3)) } emit_sqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zd_zd_zd(rz, rz2, rz3)) } -inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_uqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v8b_v8b_v8b(dst, src, src2)) } emit_uqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v16b_v16b_v16b(dst, src, src2)) } emit_uqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1661,16 +1661,16 @@ emit_uqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zh_zh_zh(rz, rz2, rz3)) } emit_uqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zs_zs_zs(rz, rz2, rz3)) } emit_uqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zd_zd_zd(rz, rz2, rz3)) } -inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_smax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8b_v8b_v8b(dst, src, src2)) } emit_smax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v16b_v16b_v16b(dst, src, src2)) } emit_smax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4h_v4h_v4h(dst, src, src2)) } @@ -1681,16 +1681,16 @@ emit_smax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_smax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_umax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8b_v8b_v8b(dst, src, src2)) } emit_umax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v16b_v16b_v16b(dst, src, src2)) } emit_umax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4h_v4h_v4h(dst, src, src2)) } @@ -1701,16 +1701,16 @@ emit_umax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_umax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_smin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8b_v8b_v8b(dst, src, src2)) } emit_smin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v16b_v16b_v16b(dst, src, src2)) } emit_smin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4h_v4h_v4h(dst, src, src2)) } @@ -1721,16 +1721,16 @@ emit_smin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_smin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_umin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8b_v8b_v8b(dst, src, src2)) } emit_umin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v16b_v16b_v16b(dst, src, src2)) } emit_umin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4h_v4h_v4h(dst, src, src2)) } @@ -1741,16 +1741,16 @@ emit_umin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_umin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_sabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_sabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_sabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_sabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8b_v8b_v8b(dst, src, src2)) } emit_sabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v16b_v16b_v16b(dst, src, src2)) } emit_sabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4h_v4h_v4h(dst, src, src2)) } @@ -1761,16 +1761,16 @@ emit_sabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_sabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_uabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_uabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_uabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_uabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_uabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_uabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_uabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8b_v8b_v8b(dst, src, src2)) } emit_uabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v16b_v16b_v16b(dst, src, src2)) } emit_uabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4h_v4h_v4h(dst, src, src2)) } @@ -1781,37 +1781,37 @@ emit_uabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_uabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_uabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_saba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_saba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_saba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_saba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_saba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_saba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_saba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8b_v8b_v8b(dst, src, src2)) } emit_saba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v16b_v16b_v16b(dst, src, src2)) } emit_saba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4h_v4h_v4h(dst, src, src2)) } emit_saba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8h_v8h_v8h(dst, src, src2)) } emit_saba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v2s_v2s_v2s(dst, src, src2)) } emit_saba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4s_v4s_v4s(dst, src, src2)) } -inst_uaba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uaba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uaba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uaba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uaba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uaba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uaba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uaba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uaba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uaba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uaba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uaba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uaba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8b_v8b_v8b(dst, src, src2)) } emit_uaba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v16b_v16b_v16b(dst, src, src2)) } emit_uaba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4h_v4h_v4h(dst, src, src2)) } emit_uaba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8h_v8h_v8h(dst, src, src2)) } emit_uaba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v2s_v2s_v2s(dst, src, src2)) } emit_uaba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4s_v4s_v4s(dst, src, src2)) } -inst_addp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_addp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_addp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_addp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_addp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_addp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_addp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_addp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_addp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v8b_v8b_v8b(dst, src, src2)) } emit_addp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v16b_v16b_v16b(dst, src, src2)) } emit_addp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4h_v4h_v4h(dst, src, src2)) } @@ -1819,496 +1819,496 @@ emit_addp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_addp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2s_v2s_v2s(dst, src, src2)) } emit_addp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4s_v4s_v4s(dst, src, src2)) } emit_addp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2d_v2d_v2d(dst, src, src2)) } -inst_addv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_addv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_addv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_addv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_addv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_addv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_addv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_addv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_addv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_addv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_addv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8b(dst, src)) } emit_addv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v16b(dst, src)) } emit_addv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4h(dst, src)) } emit_addv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8h(dst, src)) } emit_addv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4s(dst, src)) } -inst_saddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_saddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_saddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_saddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_saddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_saddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_saddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_saddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_saddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_saddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_saddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_saddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_saddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4h_v8b(dst, src)) } emit_saddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v8h_v16b(dst, src)) } emit_saddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2s_v4h(dst, src)) } emit_saddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4s_v8h(dst, src)) } emit_saddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v1d_v2s(dst, src)) } emit_saddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2d_v4s(dst, src)) } -inst_uaddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_uaddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uaddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_uaddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uaddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_uaddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uaddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uaddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uaddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uaddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uaddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_uaddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uaddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4h_v8b(dst, src)) } emit_uaddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v8h_v16b(dst, src)) } emit_uaddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2s_v4h(dst, src)) } emit_uaddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4s_v8h(dst, src)) } emit_uaddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v1d_v2s(dst, src)) } emit_uaddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2d_v4s(dst, src)) } -inst_sadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_sadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_sadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_sadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_sadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_sadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_sadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_sadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_sadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_sadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_sadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_sadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_sadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4h_v8b(dst, src)) } emit_sadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v8h_v16b(dst, src)) } emit_sadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2s_v4h(dst, src)) } emit_sadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4s_v8h(dst, src)) } emit_sadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v1d_v2s(dst, src)) } emit_sadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2d_v4s(dst, src)) } -inst_uadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_uadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_uadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_uadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_uadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4h_v8b(dst, src)) } emit_uadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v8h_v16b(dst, src)) } emit_uadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2s_v4h(dst, src)) } emit_uadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4s_v8h(dst, src)) } emit_uadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v1d_v2s(dst, src)) } emit_uadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2d_v4s(dst, src)) } -inst_saddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_saddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_saddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_saddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_saddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_saddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_saddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_saddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_saddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_saddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_saddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8b(dst, src)) } emit_saddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v16b(dst, src)) } emit_saddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4h(dst, src)) } emit_saddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8h(dst, src)) } emit_saddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4s(dst, src)) } -inst_uaddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_uaddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_uaddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_uaddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_uaddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_uaddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_uaddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_uaddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_uaddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_uaddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_uaddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8b(dst, src)) } emit_uaddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v16b(dst, src)) } emit_uaddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4h(dst, src)) } emit_uaddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8h(dst, src)) } emit_uaddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4s(dst, src)) } -inst_smaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_smaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_smaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_smaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_smaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_smaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_smaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_smaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_smaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_smaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_smaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8b(dst, src)) } emit_smaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v16b(dst, src)) } emit_smaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4h(dst, src)) } emit_smaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8h(dst, src)) } emit_smaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4s(dst, src)) } -inst_umaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_umaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_umaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_umaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_umaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_umaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_umaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_umaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_umaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_umaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_umaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8b(dst, src)) } emit_umaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v16b(dst, src)) } emit_umaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4h(dst, src)) } emit_umaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8h(dst, src)) } emit_umaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4s(dst, src)) } -inst_sminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_sminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_sminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_sminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_sminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_sminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_sminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_sminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_sminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_sminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_sminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8b(dst, src)) } emit_sminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v16b(dst, src)) } emit_sminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4h(dst, src)) } emit_sminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8h(dst, src)) } emit_sminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4s(dst, src)) } -inst_uminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_uminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_uminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_uminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_uminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_uminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_uminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_uminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_uminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_uminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_uminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8b(dst, src)) } emit_uminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v16b(dst, src)) } emit_uminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4h(dst, src)) } emit_uminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8h(dst, src)) } emit_uminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4s(dst, src)) } -inst_smaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8b_v8b_v8b(dst, src, src2)) } emit_smaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v16b_v16b_v16b(dst, src, src2)) } emit_smaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4h_v4h_v4h(dst, src, src2)) } emit_smaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8h_v8h_v8h(dst, src, src2)) } emit_smaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v2s_v2s_v2s(dst, src, src2)) } emit_smaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4s_v4s_v4s(dst, src, src2)) } -inst_umaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8b_v8b_v8b(dst, src, src2)) } emit_umaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v16b_v16b_v16b(dst, src, src2)) } emit_umaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4h_v4h_v4h(dst, src, src2)) } emit_umaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8h_v8h_v8h(dst, src, src2)) } emit_umaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v2s_v2s_v2s(dst, src, src2)) } emit_umaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4s_v4s_v4s(dst, src, src2)) } -inst_sminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8b_v8b_v8b(dst, src, src2)) } emit_sminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v16b_v16b_v16b(dst, src, src2)) } emit_sminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4h_v4h_v4h(dst, src, src2)) } emit_sminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8h_v8h_v8h(dst, src, src2)) } emit_sminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v2s_v2s_v2s(dst, src, src2)) } emit_sminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4s_v4s_v4s(dst, src, src2)) } -inst_uminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8b_v8b_v8b(dst, src, src2)) } emit_uminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v16b_v16b_v16b(dst, src, src2)) } emit_uminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4h_v4h_v4h(dst, src, src2)) } emit_uminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8h_v8h_v8h(dst, src, src2)) } emit_uminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v2s_v2s_v2s(dst, src, src2)) } emit_uminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4s_v4s_v4s(dst, src, src2)) } -inst_saddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_saddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_saddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_saddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_saddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_saddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_saddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v8h_v8b_v8b(dst, src, src2)) } emit_saddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v4s_v4h_v4h(dst, src, src2)) } emit_saddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v2d_v2s_v2s(dst, src, src2)) } -inst_saddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_saddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_saddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_saddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_saddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_saddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_saddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v8h_v16b_v16b(dst, src, src2)) } emit_saddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v4s_v8h_v8h(dst, src, src2)) } emit_saddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v2d_v4s_v4s(dst, src, src2)) } -inst_uaddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uaddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uaddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uaddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uaddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uaddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_uaddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v8h_v8b_v8b(dst, src, src2)) } emit_uaddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v4s_v4h_v4h(dst, src, src2)) } emit_uaddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v2d_v2s_v2s(dst, src, src2)) } -inst_uaddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uaddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uaddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uaddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uaddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uaddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uaddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v8h_v16b_v16b(dst, src, src2)) } emit_uaddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v4s_v8h_v8h(dst, src, src2)) } emit_uaddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v2d_v4s_v4s(dst, src, src2)) } -inst_ssubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_ssubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_ssubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_ssubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_ssubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_ssubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_ssubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v8h_v8b_v8b(dst, src, src2)) } emit_ssubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v4s_v4h_v4h(dst, src, src2)) } emit_ssubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v2d_v2s_v2s(dst, src, src2)) } -inst_ssubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_ssubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_ssubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_ssubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_ssubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_ssubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_ssubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v8h_v16b_v16b(dst, src, src2)) } emit_ssubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v4s_v8h_v8h(dst, src, src2)) } emit_ssubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v2d_v4s_v4s(dst, src, src2)) } -inst_usubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_usubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_usubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_usubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_usubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_usubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_usubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v8h_v8b_v8b(dst, src, src2)) } emit_usubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v4s_v4h_v4h(dst, src, src2)) } emit_usubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v2d_v2s_v2s(dst, src, src2)) } -inst_usubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_usubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_usubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_usubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_usubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_usubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_usubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v8h_v16b_v16b(dst, src, src2)) } emit_usubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v4s_v8h_v8h(dst, src, src2)) } emit_usubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v2d_v4s_v4s(dst, src, src2)) } -inst_saddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_saddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_saddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_saddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_saddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_saddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_saddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v8h_v8h_v8b(dst, src, src2)) } emit_saddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v4s_v4s_v4h(dst, src, src2)) } emit_saddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v2d_v2d_v2s(dst, src, src2)) } -inst_saddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_saddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_saddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_saddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_saddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_saddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_saddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v8h_v8h_v16b(dst, src, src2)) } emit_saddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v4s_v4s_v8h(dst, src, src2)) } emit_saddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v2d_v2d_v4s(dst, src, src2)) } -inst_uaddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_uaddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_uaddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_uaddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_uaddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_uaddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_uaddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v8h_v8h_v8b(dst, src, src2)) } emit_uaddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v4s_v4s_v4h(dst, src, src2)) } emit_uaddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v2d_v2d_v2s(dst, src, src2)) } -inst_uaddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_uaddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_uaddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_uaddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_uaddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_uaddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_uaddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v8h_v8h_v16b(dst, src, src2)) } emit_uaddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v4s_v4s_v8h(dst, src, src2)) } emit_uaddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v2d_v2d_v4s(dst, src, src2)) } -inst_ssubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_ssubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_ssubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_ssubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_ssubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_ssubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_ssubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v8h_v8h_v8b(dst, src, src2)) } emit_ssubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v4s_v4s_v4h(dst, src, src2)) } emit_ssubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v2d_v2d_v2s(dst, src, src2)) } -inst_ssubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_ssubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_ssubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_ssubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_ssubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_ssubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_ssubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v8h_v8h_v16b(dst, src, src2)) } emit_ssubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v4s_v4s_v8h(dst, src, src2)) } emit_ssubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v2d_v2d_v4s(dst, src, src2)) } -inst_usubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_usubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_usubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_usubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_usubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_usubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_usubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v8h_v8h_v8b(dst, src, src2)) } emit_usubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v4s_v4s_v4h(dst, src, src2)) } emit_usubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v2d_v2d_v2s(dst, src, src2)) } -inst_usubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_usubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_usubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_usubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_usubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_usubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_usubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v8h_v8h_v16b(dst, src, src2)) } emit_usubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v4s_v4s_v8h(dst, src, src2)) } emit_usubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v2d_v2d_v4s(dst, src, src2)) } -inst_raddhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_raddhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_raddhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_raddhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_raddhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_raddhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_raddhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v8b_v8h_v8h(dst, src, src2)) } emit_raddhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v4h_v4s_v4s(dst, src, src2)) } emit_raddhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v2s_v2d_v2d(dst, src, src2)) } -inst_raddhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_raddhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_raddhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_raddhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_raddhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_raddhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_raddhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v16b_v8h_v8h(dst, src, src2)) } emit_raddhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v8h_v4s_v4s(dst, src, src2)) } emit_raddhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_rsubhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_rsubhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_rsubhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rsubhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_rsubhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_rsubhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rsubhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v8b_v8h_v8h(dst, src, src2)) } emit_rsubhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v4h_v4s_v4s(dst, src, src2)) } emit_rsubhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v2s_v2d_v2d(dst, src, src2)) } -inst_rsubhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_rsubhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_rsubhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rsubhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_rsubhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_rsubhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rsubhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v16b_v8h_v8h(dst, src, src2)) } emit_rsubhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v8h_v4s_v4s(dst, src, src2)) } emit_rsubhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_addhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v8b_v8h_v8h(dst, src, src2)) } emit_addhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v4h_v4s_v4s(dst, src, src2)) } emit_addhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v2s_v2d_v2d(dst, src, src2)) } -inst_addhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v16b_v8h_v8h(dst, src, src2)) } emit_addhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v8h_v4s_v4s(dst, src, src2)) } emit_addhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_subhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_subhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_subhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_subhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_subhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_subhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_subhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v8b_v8h_v8h(dst, src, src2)) } emit_subhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v4h_v4s_v4s(dst, src, src2)) } emit_subhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v2s_v2d_v2d(dst, src, src2)) } -inst_subhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_subhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_subhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_subhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_subhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_subhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_subhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v16b_v8h_v8h(dst, src, src2)) } emit_subhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v8h_v4s_v4s(dst, src, src2)) } emit_subhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_xtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_xtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_xtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_xtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_xtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_xtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_xtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v8b_v8h(dst, src)) } emit_xtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v4h_v4s(dst, src)) } emit_xtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v2s_v2d(dst, src)) } -inst_xtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_xtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_xtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_xtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_xtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_xtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_xtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v16b_v8h(dst, src)) } emit_xtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v8h_v4s(dst, src)) } emit_xtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v4s_v2d(dst, src)) } -inst_sqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v8b_v8h(dst, src)) } emit_sqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v4h_v4s(dst, src)) } emit_sqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v2s_v2d(dst, src)) } -inst_sqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v16b_v8h(dst, src)) } emit_sqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v8h_v4s(dst, src)) } emit_sqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v4s_v2d(dst, src)) } -inst_uqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_uqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_uqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_uqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_uqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_uqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_uqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v8b_v8h(dst, src)) } emit_uqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v4h_v4s(dst, src)) } emit_uqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v2s_v2d(dst, src)) } -inst_uqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_uqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_uqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_uqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_uqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_uqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_uqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v16b_v8h(dst, src)) } emit_uqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v8h_v4s(dst, src)) } emit_uqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v4s_v2d(dst, src)) } -inst_sqxtun_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtun_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtun_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtun_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtun_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtun_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtun_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v8b_v8h(dst, src)) } emit_sqxtun_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v4h_v4s(dst, src)) } emit_sqxtun_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v2s_v2d(dst, src)) } -inst_sqxtun2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtun2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtun2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtun2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtun2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtun2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtun2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v16b_v8h(dst, src)) } emit_sqxtun2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v8h_v4s(dst, src)) } emit_sqxtun2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v4s_v2d(dst, src)) } -inst_smull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v8h_v8b_v8b(dst, src, src2)) } emit_smull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v4s_v4h_v4h(dst, src, src2)) } emit_smull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v2d_v2s_v2s(dst, src, src2)) } -inst_smull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v8h_v16b_v16b(dst, src, src2)) } emit_smull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v4s_v8h_v8h(dst, src, src2)) } emit_smull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v2d_v4s_v4s(dst, src, src2)) } -inst_umull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v8h_v8b_v8b(dst, src, src2)) } emit_umull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v4s_v4h_v4h(dst, src, src2)) } emit_umull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v2d_v2s_v2s(dst, src, src2)) } -inst_umull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v8h_v16b_v16b(dst, src, src2)) } emit_umull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v4s_v8h_v8h(dst, src, src2)) } emit_umull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v2d_v4s_v4s(dst, src, src2)) } -inst_smlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v8h_v8b_v8b(dst, src, src2)) } emit_smlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v4s_v4h_v4h(dst, src, src2)) } emit_smlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v2d_v2s_v2s(dst, src, src2)) } -inst_smlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v8h_v16b_v16b(dst, src, src2)) } emit_smlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v4s_v8h_v8h(dst, src, src2)) } emit_smlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_umlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v8h_v8b_v8b(dst, src, src2)) } emit_umlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v4s_v4h_v4h(dst, src, src2)) } emit_umlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v2d_v2s_v2s(dst, src, src2)) } -inst_umlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v8h_v16b_v16b(dst, src, src2)) } emit_umlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v4s_v8h_v8h(dst, src, src2)) } emit_umlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_smlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v8h_v8b_v8b(dst, src, src2)) } emit_smlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v4s_v4h_v4h(dst, src, src2)) } emit_smlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_smlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v8h_v16b_v16b(dst, src, src2)) } emit_smlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_smlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_umlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v8h_v8b_v8b(dst, src, src2)) } emit_umlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v4s_v4h_v4h(dst, src, src2)) } emit_umlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_umlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v8h_v16b_v16b(dst, src, src2)) } emit_umlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_umlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4h_v4h_v4h(dst, src, src2)) } emit_sqdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v8h_v8h_v8h(dst, src, src2)) } emit_sqdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v2s_v2s_v2s(dst, src, src2)) } emit_sqdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4s_v4s_v4s(dst, src, src2)) } -inst_sqrdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqrdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqrdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqrdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqrdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqrdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqrdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqrdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqrdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4h_v4h_v4h(dst, src, src2)) } emit_sqrdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v8h_v8h_v8h(dst, src, src2)) } emit_sqrdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v2s_v2s_v2s(dst, src, src2)) } emit_sqrdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4s_v4s_v4s(dst, src, src2)) } -inst_sdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_sdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v2s_v8b_v8b(dst, src, src2)) } emit_sdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v4s_v16b_v16b(dst, src, src2)) } -inst_udot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_udot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_udot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_udot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_udot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v2s_v8b_v8b(dst, src, src2)) } emit_udot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v4s_v16b_v16b(dst, src, src2)) } -inst_usdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_usdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_usdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_usdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_usdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v2s_v8b_v8b(dst, src, src2)) } emit_usdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v4s_v16b_v16b(dst, src, src2)) } -inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_fmla_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } -inst_fmla_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } -inst_fmla_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } +inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_fmla_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm), {}}} } +inst_fmla_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm), {}}} } +inst_fmla_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm), {}}} } emit_fmla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v4s_v4s_v4s(dst, src, src2)) } emit_fmla_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v2d_v2d_v2d(dst, src, src2)) } emit_fmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } @@ -2317,14 +2317,14 @@ emit_fmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmla_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zh_zh_zh_i(rz, rz2, rz3, imm)) } emit_fmla_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zs_zs_zs_i(rz, rz2, rz3, imm)) } emit_fmla_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zd_zd_zd_i(rz, rz2, rz3, imm)) } -inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_fmls_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } -inst_fmls_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } -inst_fmls_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } +inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_fmls_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm), {}}} } +inst_fmls_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm), {}}} } +inst_fmls_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm), {}}} } emit_fmls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v4s_v4s_v4s(dst, src, src2)) } emit_fmls_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v2d_v2d_v2d(dst, src, src2)) } emit_fmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } @@ -2333,108 +2333,108 @@ emit_fmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmls_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zh_zh_zh_i(rz, rz2, rz3, imm)) } emit_fmls_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zs_zs_zs_i(rz, rz2, rz3, imm)) } emit_fmls_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zd_zd_zd_i(rz, rz2, rz3, imm)) } -inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmulx_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmulx_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmulx_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmulx_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmulx_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2s_v2s_v2s(dst, src, src2)) } emit_fmulx_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4s_v4s_v4s(dst, src, src2)) } emit_fmulx_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2d_v2d_v2d(dst, src, src2)) } emit_fmulx_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4h_v4h_v4h(dst, src, src2)) } emit_fmulx_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4s_v4s_v4s(dst, src, src2)) } emit_fmaxp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2d_v2d_v2d(dst, src, src2)) } emit_fmaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4h_v4h_v4h(dst, src, src2)) } emit_fmaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v8h_v8h_v8h(dst, src, src2)) } -inst_fminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2s_v2s_v2s(dst, src, src2)) } emit_fminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4s_v4s_v4s(dst, src, src2)) } emit_fminp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2d_v2d_v2d(dst, src, src2)) } emit_fminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4h_v4h_v4h(dst, src, src2)) } emit_fminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmaxnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmaxnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4s_v4s_v4s(dst, src, src2)) } emit_fmaxnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2d_v2d_v2d(dst, src, src2)) } emit_fmaxnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4h_v4h_v4h(dst, src, src2)) } emit_fmaxnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v8h_v8h_v8h(dst, src, src2)) } -inst_fminnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fminnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fminnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2s_v2s_v2s(dst, src, src2)) } emit_fminnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4s_v4s_v4s(dst, src, src2)) } emit_fminnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2d_v2d_v2d(dst, src, src2)) } emit_fminnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4h_v4h_v4h(dst, src, src2)) } emit_fminnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fmaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fmaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fmaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fmaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fmaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fmaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4s(dst, src)) } emit_fmaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4h(dst, src)) } emit_fmaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v8h(dst, src)) } -inst_fminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4s(dst, src)) } emit_fminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4h(dst, src)) } emit_fminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v8h(dst, src)) } -inst_fmaxnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fmaxnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fmaxnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fmaxnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fmaxnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fmaxnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fmaxnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4s(dst, src)) } emit_fmaxnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4h(dst, src)) } emit_fmaxnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v8h(dst, src)) } -inst_fminnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fminnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fminnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fminnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fminnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fminnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fminnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4s(dst, src)) } emit_fminnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4h(dst, src)) } emit_fminnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v8h(dst, src)) } -inst_frecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frecpe_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frecpe_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frecpe_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frecpe_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frecpe_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frecpe_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_frecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2s_v2s(dst, src)) } emit_frecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4s_v4s(dst, src)) } emit_frecpe_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2d_v2d(dst, src)) } emit_frecpe_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4h_v4h(dst, src)) } emit_frecpe_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v8h_v8h(dst, src)) } -inst_frsqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frsqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frsqrte_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frsqrte_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frsqrte_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frsqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frsqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frsqrte_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frsqrte_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frsqrte_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_frsqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2s_v2s(dst, src)) } emit_frsqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4s_v4s(dst, src)) } emit_frsqrte_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2d_v2d(dst, src)) } emit_frsqrte_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4h_v4h(dst, src)) } emit_frsqrte_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v8h_v8h(dst, src)) } -inst_frecps_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frecps_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_frecps_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_frecps_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_frecps_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_frecps_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_frecps_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_frecps_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_frecps_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2s_v2s_v2s(dst, src, src2)) } emit_frecps_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4s_v4s_v4s(dst, src, src2)) } emit_frecps_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2d_v2d_v2d(dst, src, src2)) } @@ -2443,14 +2443,14 @@ emit_frecps_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_frecps_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zh_zh_zh(rz, rz2, rz3)) } emit_frecps_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zs_zs_zs(rz, rz2, rz3)) } emit_frecps_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zd_zd_zd(rz, rz2, rz3)) } -inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frsqrts_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_frsqrts_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_frsqrts_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_frsqrts_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_frsqrts_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_frsqrts_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_frsqrts_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2s_v2s_v2s(dst, src, src2)) } emit_frsqrts_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4s_v4s_v4s(dst, src, src2)) } emit_frsqrts_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2d_v2d_v2d(dst, src, src2)) } @@ -2460,51 +2460,51 @@ emit_frsqrts_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frsqrts_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zs_zs_zs(rz, rz2, rz3)) } emit_frsqrts_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zd_zd_zd(rz, rz2, rz3)) } inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } -inst_frecpx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frecpx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frecpx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frecpx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frecpx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frecpx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } emit_frecpx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zh_p_zh(rz, rz2, rz3)) } emit_frecpx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zs_p_zs(rz, rz2, rz3)) } emit_frecpx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zd_p_zd(rz, rz2, rz3)) } -inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_faddp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_faddp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_faddp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_faddp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_faddp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2s_v2s_v2s(dst, src, src2)) } emit_faddp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4s_v4s_v4s(dst, src, src2)) } emit_faddp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2d_v2d_v2d(dst, src, src2)) } emit_faddp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4h_v4h_v4h(dst, src, src2)) } emit_faddp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v8h_v8h_v8h(dst, src, src2)) } -inst_fcvtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_fcvtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_fcvtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_fcvtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v4s_v4h(dst, src)) } emit_fcvtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v2d_v2s(dst, src)) } -inst_fcvtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_fcvtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_fcvtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcvtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_fcvtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v4s_v8h(dst, src)) } emit_fcvtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v2d_v4s(dst, src)) } -inst_fcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_fcvtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v4h_v4s(dst, src)) } emit_fcvtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v2s_v2d(dst, src)) } -inst_fcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_fcvtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v8h_v4s(dst, src)) } emit_fcvtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v4s_v2d(dst, src)) } -inst_fcvtxn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtxn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtxn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_v2s_v2d(dst, src)) } -inst_fcvtxn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtxn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtxn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_v4s_v2d(dst, src)) } -inst_fcmeq_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmeq_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmeq_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2s_v2s_v2s(dst, src, src2)) } emit_fcmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4s_v4s_v4s(dst, src, src2)) } emit_fcmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2d_v2d_v2d(dst, src, src2)) } @@ -2513,14 +2513,14 @@ emit_fcmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2s_v2s_v2s(dst, src, src2)) } emit_fcmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4s_v4s_v4s(dst, src, src2)) } emit_fcmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2d_v2d_v2d(dst, src, src2)) } @@ -2529,14 +2529,14 @@ emit_fcmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2s_v2s_v2s(dst, src, src2)) } emit_fcmgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4s_v4s_v4s(dst, src, src2)) } emit_fcmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2d_v2d_v2d(dst, src, src2)) } @@ -2545,14 +2545,14 @@ emit_fcmgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmle_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fcmle_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fcmle_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcmle_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fcmle_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fcmle_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fcmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2s_v2s(dst, src)) } emit_fcmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4s_v4s(dst, src)) } emit_fcmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2d_v2d(dst, src)) } @@ -2561,14 +2561,14 @@ emit_fcmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmle_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ph_p_zh(rz, rz2, rz3)) } emit_fcmle_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ps_p_zs(rz, rz2, rz3)) } emit_fcmle_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_pd_p_zd(rz, rz2, rz3)) } -inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmlt_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fcmlt_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fcmlt_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcmlt_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fcmlt_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fcmlt_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fcmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2s_v2s(dst, src)) } emit_fcmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4s_v4s(dst, src)) } emit_fcmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2d_v2d(dst, src)) } @@ -2577,41 +2577,41 @@ emit_fcmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmlt_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ph_p_zh(rz, rz2, rz3)) } emit_fcmlt_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ps_p_zs(rz, rz2, rz3)) } emit_fcmlt_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_pd_p_zd(rz, rz2, rz3)) } -inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_facge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_facge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_facge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_facge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_facge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2s_v2s_v2s(dst, src, src2)) } emit_facge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4s_v4s_v4s(dst, src, src2)) } emit_facge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2d_v2d_v2d(dst, src, src2)) } emit_facge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4h_v4h_v4h(dst, src, src2)) } emit_facge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v8h_v8h_v8h(dst, src, src2)) } -inst_facgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_facgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_facgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_facgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_facgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_facgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_facgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_facgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_facgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_facgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_facgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2s_v2s_v2s(dst, src, src2)) } emit_facgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4s_v4s_v4s(dst, src, src2)) } emit_facgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2d_v2d_v2d(dst, src, src2)) } emit_facgt_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4h_v4h_v4h(dst, src, src2)) } emit_facgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v8h_v8h_v8h(dst, src, src2)) } -inst_cmeq_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmeq_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmeq_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v16b_v16b_v16b(dst, src, src2)) } emit_cmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v8h_v8h_v8h(dst, src, src2)) } emit_cmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v4s_v4s_v4s(dst, src, src2)) } emit_cmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v2d_v2d_v2d(dst, src, src2)) } -inst_cmge_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmge_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmge_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmge_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmge_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v8b_v8b_v8b(dst, src, src2)) } emit_cmge_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v16b_v16b_v16b(dst, src, src2)) } emit_cmge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4h_v4h_v4h(dst, src, src2)) } @@ -2619,21 +2619,21 @@ emit_cmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2s_v2s_v2s(dst, src, src2)) } emit_cmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4s_v4s_v4s(dst, src, src2)) } emit_cmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2d_v2d_v2d(dst, src, src2)) } -inst_cmgt_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmgt_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmgt_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v16b_v16b_v16b(dst, src, src2)) } emit_cmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v2d_v2d_v2d(dst, src, src2)) } -inst_cmhi_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmhi_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmhi_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmhi_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmhi_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v16b_v16b_v16b(dst, src, src2)) } emit_cmhi_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v2d_v2d_v2d(dst, src, src2)) } -inst_cmhs_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmhs_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmhs_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmhs_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmhs_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmhs_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmhs_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmhs_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmhs_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmhs_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmhs_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmhs_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmhs_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmhs_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmhs_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v8b_v8b_v8b(dst, src, src2)) } emit_cmhs_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v16b_v16b_v16b(dst, src, src2)) } emit_cmhs_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4h_v4h_v4h(dst, src, src2)) } @@ -2641,13 +2641,13 @@ emit_cmhs_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmhs_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2s_v2s_v2s(dst, src, src2)) } emit_cmhs_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4s_v4s_v4s(dst, src, src2)) } emit_cmhs_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2d_v2d_v2d(dst, src, src2)) } -inst_cmle_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cmle_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_cmle_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cmle_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_cmle_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v8b_v8b(dst, src)) } emit_cmle_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v16b_v16b(dst, src)) } emit_cmle_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4h_v4h(dst, src)) } @@ -2655,13 +2655,13 @@ emit_cmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2s_v2s(dst, src)) } emit_cmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4s_v4s(dst, src)) } emit_cmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2d_v2d(dst, src)) } -inst_cmlt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cmlt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_cmlt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cmlt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_cmlt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v8b_v8b(dst, src)) } emit_cmlt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v16b_v16b(dst, src)) } emit_cmlt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4h_v4h(dst, src)) } @@ -2669,13 +2669,13 @@ emit_cmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2s_v2s(dst, src)) } emit_cmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4s_v4s(dst, src)) } emit_cmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2d_v2d(dst, src)) } -inst_cmtst_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmtst_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmtst_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmtst_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmtst_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmtst_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmtst_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmtst_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmtst_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmtst_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmtst_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmtst_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmtst_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmtst_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmtst_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v8b_v8b_v8b(dst, src, src2)) } emit_cmtst_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v16b_v16b_v16b(dst, src, src2)) } emit_cmtst_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4h_v4h_v4h(dst, src, src2)) } @@ -2683,27 +2683,27 @@ emit_cmtst_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmtst_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2s_v2s_v2s(dst, src, src2)) } emit_cmtst_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4s_v4s_v4s(dst, src, src2)) } emit_cmtst_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2d_v2d_v2d(dst, src, src2)) } -inst_mvn_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_mvn_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_mvn_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_mvn_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } emit_mvn_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v8b_v8b(dst, src)) } emit_mvn_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v16b_v16b(dst, src)) } emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } -inst_bit_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bit_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_bit_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_v16b_v16b_v16b(dst, src, src2)) } -inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_bif_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_v16b_v16b_v16b(dst, src, src2)) } -inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_bsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_v16b_v16b_v16b(dst, src, src2)) } emit_bsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_shl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_shl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v8b_v8b_i(dst, src, imm)) } emit_shl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v16b_v16b_i(dst, src, imm)) } emit_shl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4h_v4h_i(dst, src, imm)) } @@ -2711,13 +2711,13 @@ emit_shl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_shl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2s_v2s_i(dst, src, imm)) } emit_shl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4s_v4s_i(dst, src, imm)) } emit_shl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2d_v2d_i(dst, src, imm)) } -inst_sqshl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sqshl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sqshl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sqshl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sqshl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v8b_v8b_i(dst, src, imm)) } emit_sqshl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v16b_v16b_i(dst, src, imm)) } emit_sqshl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4h_v4h_i(dst, src, imm)) } @@ -2725,13 +2725,13 @@ emit_sqshl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqshl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2s_v2s_i(dst, src, imm)) } emit_sqshl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4s_v4s_i(dst, src, imm)) } emit_sqshl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2d_v2d_i(dst, src, imm)) } -inst_sqshlu_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshlu_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v8b_v8b_i(dst, src, imm)) } emit_sqshlu_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v16b_v16b_i(dst, src, imm)) } emit_sqshlu_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4h_v4h_i(dst, src, imm)) } @@ -2739,13 +2739,13 @@ emit_sqshlu_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqshlu_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2s_v2s_i(dst, src, imm)) } emit_sqshlu_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4s_v4s_i(dst, src, imm)) } emit_sqshlu_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2d_v2d_i(dst, src, imm)) } -inst_srshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_srshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_srshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_srshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_srshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_srshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_srshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_srshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_srshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_srshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_srshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_srshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_srshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_srshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_srshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v8b_v8b_v8b(dst, src, src2)) } emit_srshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v16b_v16b_v16b(dst, src, src2)) } emit_srshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2753,13 +2753,13 @@ emit_srshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_srshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2s_v2s_v2s(dst, src, src2)) } emit_srshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4s_v4s_v4s(dst, src, src2)) } emit_srshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2d_v2d_v2d(dst, src, src2)) } -inst_urshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_urshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_urshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_urshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_urshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_urshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_urshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_urshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_urshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_urshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_urshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_urshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_urshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_urshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_urshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v8b_v8b_v8b(dst, src, src2)) } emit_urshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v16b_v16b_v16b(dst, src, src2)) } emit_urshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2767,13 +2767,13 @@ emit_urshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_urshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2s_v2s_v2s(dst, src, src2)) } emit_urshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4s_v4s_v4s(dst, src, src2)) } emit_urshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2d_v2d_v2d(dst, src, src2)) } -inst_sshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v8b_v8b_i(dst, src, imm)) } emit_sshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v16b_v16b_i(dst, src, imm)) } emit_sshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4h_v4h_i(dst, src, imm)) } @@ -2781,13 +2781,13 @@ emit_sshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2s_v2s_i(dst, src, imm)) } emit_sshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4s_v4s_i(dst, src, imm)) } emit_sshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2d_v2d_i(dst, src, imm)) } -inst_ushr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ushr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ushr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ushr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ushr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ushr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ushr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ushr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ushr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v8b_v8b_i(dst, src, imm)) } emit_ushr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v16b_v16b_i(dst, src, imm)) } emit_ushr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4h_v4h_i(dst, src, imm)) } @@ -2795,13 +2795,13 @@ emit_ushr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ushr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2s_v2s_i(dst, src, imm)) } emit_ushr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4s_v4s_i(dst, src, imm)) } emit_ushr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2d_v2d_i(dst, src, imm)) } -inst_ssra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ssra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ssra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ssra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ssra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ssra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ssra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ssra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ssra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v8b_v8b_i(dst, src, imm)) } emit_ssra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v16b_v16b_i(dst, src, imm)) } emit_ssra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4h_v4h_i(dst, src, imm)) } @@ -2809,13 +2809,13 @@ emit_ssra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ssra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2s_v2s_i(dst, src, imm)) } emit_ssra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4s_v4s_i(dst, src, imm)) } emit_ssra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2d_v2d_i(dst, src, imm)) } -inst_usra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_usra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_usra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_usra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_usra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_usra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_usra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_usra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_usra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v8b_v8b_i(dst, src, imm)) } emit_usra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v16b_v16b_i(dst, src, imm)) } emit_usra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4h_v4h_i(dst, src, imm)) } @@ -2823,13 +2823,13 @@ emit_usra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_usra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2s_v2s_i(dst, src, imm)) } emit_usra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4s_v4s_i(dst, src, imm)) } emit_usra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2d_v2d_i(dst, src, imm)) } -inst_srshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_srshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_srshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_srshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_srshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_srshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_srshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_srshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_srshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v8b_v8b_i(dst, src, imm)) } emit_srshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v16b_v16b_i(dst, src, imm)) } emit_srshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4h_v4h_i(dst, src, imm)) } @@ -2837,13 +2837,13 @@ emit_srshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_srshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2s_v2s_i(dst, src, imm)) } emit_srshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4s_v4s_i(dst, src, imm)) } emit_srshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2d_v2d_i(dst, src, imm)) } -inst_urshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_urshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_urshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_urshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_urshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_urshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_urshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_urshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_urshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v8b_v8b_i(dst, src, imm)) } emit_urshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v16b_v16b_i(dst, src, imm)) } emit_urshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4h_v4h_i(dst, src, imm)) } @@ -2851,13 +2851,13 @@ emit_urshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_urshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2s_v2s_i(dst, src, imm)) } emit_urshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4s_v4s_i(dst, src, imm)) } emit_urshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2d_v2d_i(dst, src, imm)) } -inst_srsra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_srsra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_srsra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_srsra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_srsra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_srsra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_srsra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_srsra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_srsra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v8b_v8b_i(dst, src, imm)) } emit_srsra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v16b_v16b_i(dst, src, imm)) } emit_srsra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4h_v4h_i(dst, src, imm)) } @@ -2865,13 +2865,13 @@ emit_srsra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_srsra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2s_v2s_i(dst, src, imm)) } emit_srsra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4s_v4s_i(dst, src, imm)) } emit_srsra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2d_v2d_i(dst, src, imm)) } -inst_ursra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ursra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ursra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ursra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ursra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ursra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ursra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ursra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ursra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v8b_v8b_i(dst, src, imm)) } emit_ursra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v16b_v16b_i(dst, src, imm)) } emit_ursra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4h_v4h_i(dst, src, imm)) } @@ -2879,13 +2879,13 @@ emit_ursra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ursra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2s_v2s_i(dst, src, imm)) } emit_ursra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4s_v4s_i(dst, src, imm)) } emit_ursra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2d_v2d_i(dst, src, imm)) } -inst_sshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_sshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v8b_v8b_v8b(dst, src, src2)) } emit_sshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v16b_v16b_v16b(dst, src, src2)) } emit_sshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2893,13 +2893,13 @@ emit_sshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_sshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2s_v2s_v2s(dst, src, src2)) } emit_sshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4s_v4s_v4s(dst, src, src2)) } emit_sshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2d_v2d_v2d(dst, src, src2)) } -inst_ushl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_ushl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_ushl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_ushl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_ushl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_ushl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_ushl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_ushl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_ushl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_ushl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_ushl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_ushl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_ushl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_ushl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_ushl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v8b_v8b_v8b(dst, src, src2)) } emit_ushl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v16b_v16b_v16b(dst, src, src2)) } emit_ushl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4h_v4h_v4h(dst, src, src2)) } @@ -2907,13 +2907,13 @@ emit_ushl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_ushl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2s_v2s_v2s(dst, src, src2)) } emit_ushl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4s_v4s_v4s(dst, src, src2)) } emit_ushl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2d_v2d_v2d(dst, src, src2)) } -inst_sli_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sli_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sli_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sli_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sli_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sli_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sli_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sli_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sli_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v8b_v8b_i(dst, src, imm)) } emit_sli_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v16b_v16b_i(dst, src, imm)) } emit_sli_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4h_v4h_i(dst, src, imm)) } @@ -2921,13 +2921,13 @@ emit_sli_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sli_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2s_v2s_i(dst, src, imm)) } emit_sli_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4s_v4s_i(dst, src, imm)) } emit_sli_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2d_v2d_i(dst, src, imm)) } -inst_sri_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sri_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sri_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sri_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sri_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sri_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sri_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sri_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sri_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v8b_v8b_i(dst, src, imm)) } emit_sri_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v16b_v16b_i(dst, src, imm)) } emit_sri_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4h_v4h_i(dst, src, imm)) } @@ -2935,168 +2935,168 @@ emit_sri_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sri_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2s_v2s_i(dst, src, imm)) } emit_sri_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4s_v4s_i(dst, src, imm)) } emit_sri_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2d_v2d_i(dst, src, imm)) } -inst_sshll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sshll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sshll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sshll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sshll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sshll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } emit_sshll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v8h_v8b_i(dst, src, imm)) } emit_sshll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v4s_v4h_i(dst, src, imm)) } emit_sshll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v2d_v2s_i(dst, src, imm)) } -inst_sshll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sshll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sshll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sshll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sshll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sshll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } emit_sshll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v8h_v16b_i(dst, src, imm)) } emit_sshll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v4s_v8h_i(dst, src, imm)) } emit_sshll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v2d_v4s_i(dst, src, imm)) } -inst_ushll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ushll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ushll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_ushll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ushll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ushll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } emit_ushll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v8h_v8b_i(dst, src, imm)) } emit_ushll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v4s_v4h_i(dst, src, imm)) } emit_ushll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v2d_v2s_i(dst, src, imm)) } -inst_ushll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ushll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ushll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_ushll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ushll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ushll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } emit_ushll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v8h_v16b_i(dst, src, imm)) } emit_ushll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v4s_v8h_i(dst, src, imm)) } emit_ushll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v2d_v4s_i(dst, src, imm)) } -inst_sxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } -inst_sxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_sxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_sxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}, {}}} } +inst_sxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_sxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_sxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v8h_v8b(dst, src)) } emit_sxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v4s_v4h(dst, src)) } emit_sxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v2d_v2s(dst, src)) } -inst_sxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_sxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_sxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_sxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_sxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_sxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_sxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v8h_v16b(dst, src)) } emit_sxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v4s_v8h(dst, src)) } emit_sxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v2d_v4s(dst, src)) } -inst_uxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } -inst_uxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_uxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_uxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_uxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v8h_v8b(dst, src)) } emit_uxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v4s_v4h(dst, src)) } emit_uxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v2d_v2s(dst, src)) } -inst_uxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v8h_v16b(dst, src)) } emit_uxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v4s_v8h(dst, src)) } emit_uxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v2d_v4s(dst, src)) } -inst_shrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v8b_v8h_i(dst, src, imm)) } emit_shrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v4h_v4s_i(dst, src, imm)) } emit_shrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v2s_v2d_i(dst, src, imm)) } -inst_shrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v16b_v8h_i(dst, src, imm)) } emit_shrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v8h_v4s_i(dst, src, imm)) } emit_shrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v4s_v2d_i(dst, src, imm)) } -inst_rshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_rshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_rshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_rshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_rshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v8b_v8h_i(dst, src, imm)) } emit_rshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v4h_v4s_i(dst, src, imm)) } emit_rshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v2s_v2d_i(dst, src, imm)) } -inst_rshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_rshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_rshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_rshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_rshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v16b_v8h_i(dst, src, imm)) } emit_rshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v8h_v4s_i(dst, src, imm)) } emit_rshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v8b_v8h_i(dst, src, imm)) } emit_sqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v4h_v4s_i(dst, src, imm)) } emit_sqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v2s_v2d_i(dst, src, imm)) } -inst_sqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v16b_v8h_i(dst, src, imm)) } emit_sqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v8h_v4s_i(dst, src, imm)) } emit_sqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v4s_v2d_i(dst, src, imm)) } -inst_uqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v8b_v8h_i(dst, src, imm)) } emit_uqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v4h_v4s_i(dst, src, imm)) } emit_uqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v2s_v2d_i(dst, src, imm)) } -inst_uqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v16b_v8h_i(dst, src, imm)) } emit_uqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v8h_v4s_i(dst, src, imm)) } emit_uqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v8b_v8h_i(dst, src, imm)) } emit_sqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v4h_v4s_i(dst, src, imm)) } emit_sqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v2s_v2d_i(dst, src, imm)) } -inst_sqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v16b_v8h_i(dst, src, imm)) } emit_sqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v8h_v4s_i(dst, src, imm)) } emit_sqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v4s_v2d_i(dst, src, imm)) } -inst_uqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v8b_v8h_i(dst, src, imm)) } emit_uqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v4h_v4s_i(dst, src, imm)) } emit_uqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v2s_v2d_i(dst, src, imm)) } -inst_uqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v16b_v8h_i(dst, src, imm)) } emit_uqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v8h_v4s_i(dst, src, imm)) } emit_uqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v8b_v8h_i(dst, src, imm)) } emit_sqshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v4h_v4s_i(dst, src, imm)) } emit_sqshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v2s_v2d_i(dst, src, imm)) } -inst_sqshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v16b_v8h_i(dst, src, imm)) } emit_sqshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v8h_v4s_i(dst, src, imm)) } emit_sqshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v4s_v2d_i(dst, src, imm)) } -inst_sqrshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v8b_v8h_i(dst, src, imm)) } emit_sqrshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v4h_v4s_i(dst, src, imm)) } emit_sqrshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v2s_v2d_i(dst, src, imm)) } -inst_sqrshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v16b_v8h_i(dst, src, imm)) } emit_sqrshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v8h_v4s_i(dst, src, imm)) } emit_sqrshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v4s_v2d_i(dst, src, imm)) } -inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } -inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } -inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } -inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } -inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } -inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } -inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_lane_index(imm), {}}} } -inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}}} } -inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}}} } -inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}}} } -inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_reg(src), {}, {}}} } -inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}}} } -inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}}} } -inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}}} } -inst_dup_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -inst_dup_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } -inst_dup_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } -inst_dup_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } +inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_lane_index(imm), {}, {}}} } +inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_lane_index(imm), {}, {}}} } +inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_lane_index(imm), {}, {}}} } +inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_lane_index(imm), {}, {}}} } +inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_lane_index(imm), {}, {}}} } +inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_lane_index(imm), {}, {}}} } +inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_lane_index(imm), {}, {}}} } +inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}, {}}} } +inst_dup_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}, {}}} } emit_dup_v8b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v8b_veb_i(dst, src, imm)) } emit_dup_v16b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v16b_veb_i(dst, src, imm)) } emit_dup_v4h_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v4h_veh_i(dst, src, imm)) } @@ -3115,14 +3115,14 @@ emit_dup_zb_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_dup_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zh_r(rz, src)) } emit_dup_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zs_r(rz, src)) } emit_dup_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zd_r(rz, src)) } -inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2)}} } -inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2)}} } -inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2)}} } -inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_v_elem_d(src), op_lane_index(imm2)}} } -inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_reg(src), {}}} } +inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2), {}}} } +inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2), {}}} } +inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2), {}}} } +inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_v_elem_d(src), op_lane_index(imm2), {}}} } +inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_reg(src), {}, {}}} } emit_ins_veb_i_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veb_i_veb_i(dst, imm, src, imm2)) } emit_ins_veh_i_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veh_i_veh_i(dst, imm, src, imm2)) } emit_ins_ves_i_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_ves_i_ves_i(dst, imm, src, imm2)) } @@ -3131,14 +3131,14 @@ emit_ins_veb_i_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_ins_veh_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_veh_i_r(dst, imm, src)) } emit_ins_ves_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ves_i_r(dst, imm, src)) } emit_ins_ved_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ved_i_r(dst, imm, src)) } -inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_mov_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } -inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_mov_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_mov_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } +inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } +inst_mov_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV, dst, src) } inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } emit_mov_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v8b_v8b(dst, src)) } @@ -3151,42 +3151,42 @@ emit_mov_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Inst emit_mov_pb_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_pb_p(rz, rz2)) } emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } -inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4)}} } -inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4)}} } -inst_ext_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4), {}}} } +inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4), {}}} } +inst_ext_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4), {}}} } emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } emit_ext_zb_zb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_zb_zb_zb_i(rz, rz2, rz3, imm)) } -inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } -inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } +inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } +inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } emit_tbl_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zb_zb(rz, rz2, rz3)) } emit_tbl_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zh_zh_zh(rz, rz2, rz3)) } emit_tbl_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zs_zs_zs(rz, rz2, rz3)) } emit_tbl_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zd_zd_zd(rz, rz2, rz3)) } -inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } -inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } +inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } +inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } emit_tbx_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_zb_zb_zb(rz, rz2, rz3)) } -inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_zip1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_zip1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8b_v8b_v8b(dst, src, src2)) } emit_zip1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v16b_v16b_v16b(dst, src, src2)) } emit_zip1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4h_v4h_v4h(dst, src, src2)) } @@ -3199,18 +3199,18 @@ emit_zip1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zs_zs_zs(rz, rz2, rz3)) } emit_zip1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zd_zd_zd(rz, rz2, rz3)) } emit_zip1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_pb_pb_pb(rz, rz2, rz3)) } -inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_zip2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_zip2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8b_v8b_v8b(dst, src, src2)) } emit_zip2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v16b_v16b_v16b(dst, src, src2)) } emit_zip2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4h_v4h_v4h(dst, src, src2)) } @@ -3223,18 +3223,18 @@ emit_zip2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zs_zs_zs(rz, rz2, rz3)) } emit_zip2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zd_zd_zd(rz, rz2, rz3)) } emit_zip2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_pb_pb_pb(rz, rz2, rz3)) } -inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_uzp1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_uzp1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8b_v8b_v8b(dst, src, src2)) } emit_uzp1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v16b_v16b_v16b(dst, src, src2)) } emit_uzp1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4h_v4h_v4h(dst, src, src2)) } @@ -3247,18 +3247,18 @@ emit_uzp1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zs_zs_zs(rz, rz2, rz3)) } emit_uzp1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zd_zd_zd(rz, rz2, rz3)) } emit_uzp1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_pb_pb_pb(rz, rz2, rz3)) } -inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_uzp2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_uzp2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8b_v8b_v8b(dst, src, src2)) } emit_uzp2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v16b_v16b_v16b(dst, src, src2)) } emit_uzp2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4h_v4h_v4h(dst, src, src2)) } @@ -3271,18 +3271,18 @@ emit_uzp2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zs_zs_zs(rz, rz2, rz3)) } emit_uzp2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zd_zd_zd(rz, rz2, rz3)) } emit_uzp2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_pb_pb_pb(rz, rz2, rz3)) } -inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_trn1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_trn1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8b_v8b_v8b(dst, src, src2)) } emit_trn1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v16b_v16b_v16b(dst, src, src2)) } emit_trn1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4h_v4h_v4h(dst, src, src2)) } @@ -3295,18 +3295,18 @@ emit_trn1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zs_zs_zs(rz, rz2, rz3)) } emit_trn1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zd_zd_zd(rz, rz2, rz3)) } emit_trn1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_pb_pb_pb(rz, rz2, rz3)) } -inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_trn2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_trn2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8b_v8b_v8b(dst, src, src2)) } emit_trn2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v16b_v16b_v16b(dst, src, src2)) } emit_trn2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4h_v4h_v4h(dst, src, src2)) } @@ -3319,51 +3319,51 @@ emit_trn2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zs_zs_zs(rz, rz2, rz3)) } emit_trn2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zd_zd_zd(rz, rz2, rz3)) } emit_trn2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_pb_pb_pb(rz, rz2, rz3)) } -inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_not_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_not_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_not_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v8b_v8b(dst, src)) } emit_not_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v16b_v16b(dst, src)) } emit_not_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_pb_p_pb(rz, rz2, rz3)) } -inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_rev64_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_rev64_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_rev64_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_rev64_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_rev64_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_rev64_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_rev64_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8b_v8b(dst, src)) } emit_rev64_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v16b_v16b(dst, src)) } emit_rev64_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4h_v4h(dst, src)) } emit_rev64_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8h_v8h(dst, src)) } emit_rev64_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v2s_v2s(dst, src)) } emit_rev64_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4s_v4s(dst, src)) } -inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cnt_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_cnt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_cnt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_cnt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cnt_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_cnt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_cnt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_cnt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_cnt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v8b_v8b(dst, src)) } emit_cnt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v16b_v16b(dst, src)) } emit_cnt_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zb_p_zb(rz, rz2, rz3)) } emit_cnt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zh_p_zh(rz, rz2, rz3)) } emit_cnt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zs_p_zs(rz, rz2, rz3)) } emit_cnt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zd_p_zd(rz, rz2, rz3)) } -inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_urecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v2s_v2s(dst, src)) } emit_urecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v4s_v4s(dst, src)) } -inst_ursqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_ursqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_ursqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_ursqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_ursqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v2s_v2s(dst, src)) } emit_ursqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v4s_v4s(dst, src)) } -inst_movi_v8b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v16b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v8b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v16b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}, {}}} } emit_movi_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v8b_i(dst, imm)) } emit_movi_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v16b_i(dst, imm)) } emit_movi_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4h_i(dst, imm)) } @@ -3371,22 +3371,22 @@ emit_movi_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_movi_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2s_i(dst, imm)) } emit_movi_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4s_i(dst, imm)) } emit_movi_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2d_i(dst, imm)) } -inst_mvni_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } +inst_mvni_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } emit_mvni_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4h_i(dst, imm)) } emit_mvni_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v8h_i(dst, imm)) } emit_mvni_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v2s_i(dst, imm)) } emit_mvni_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4s_i(dst, imm)) } -inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } -inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } -inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } -inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } -inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v16b_m(dst, mem)) } emit_ld1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v8h_m(dst, mem)) } emit_ld1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v4s_m(dst, mem)) } @@ -3395,44 +3395,44 @@ emit_ld1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_ld1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_veh_i_m(dst, imm, mem)) } emit_ld1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ves_i_m(dst, imm, mem)) } emit_ld1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ved_i_m(dst, imm, mem)) } -inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } -inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } +inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_v16b_m(dst, mem)) } emit_ld2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veb_i_m(dst, imm, mem)) } emit_ld2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veh_i_m(dst, imm, mem)) } emit_ld2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ves_i_m(dst, imm, mem)) } emit_ld2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ved_i_m(dst, imm, mem)) } -inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } -inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } +inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_v16b_m(dst, mem)) } emit_ld3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veb_i_m(dst, imm, mem)) } emit_ld3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veh_i_m(dst, imm, mem)) } emit_ld3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ves_i_m(dst, imm, mem)) } emit_ld3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ved_i_m(dst, imm, mem)) } -inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } -inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } +inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_v16b_m(dst, mem)) } emit_ld4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veb_i_m(dst, imm, mem)) } emit_ld4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veh_i_m(dst, imm, mem)) } emit_ld4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ves_i_m(dst, imm, mem)) } emit_ld4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ved_i_m(dst, imm, mem)) } -inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } -inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } -inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } -inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } -inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v16b_m(dst, mem)) } emit_st1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v8h_m(dst, mem)) } emit_st1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v4s_m(dst, mem)) } @@ -3441,481 +3441,481 @@ emit_st1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_st1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_veh_i_m(dst, imm, mem)) } emit_st1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ves_i_m(dst, imm, mem)) } emit_st1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ved_i_m(dst, imm, mem)) } -inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } -inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } +inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_v16b_m(dst, mem)) } emit_st2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veb_i_m(dst, imm, mem)) } emit_st2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veh_i_m(dst, imm, mem)) } emit_st2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ves_i_m(dst, imm, mem)) } emit_st2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ved_i_m(dst, imm, mem)) } -inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } -inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } +inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_v16b_m(dst, mem)) } emit_st3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veb_i_m(dst, imm, mem)) } emit_st3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veh_i_m(dst, imm, mem)) } emit_st3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ves_i_m(dst, imm, mem)) } emit_st3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ved_i_m(dst, imm, mem)) } -inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } -inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } +inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_v16b_m(dst, mem)) } emit_st4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veb_i_m(dst, imm, mem)) } emit_st4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veh_i_m(dst, imm, mem)) } emit_st4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ves_i_m(dst, imm, mem)) } emit_st4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ved_i_m(dst, imm, mem)) } -inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } +inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } emit_ld1r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_v16b_m(dst, mem)) } -inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } +inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } emit_ld2r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_v16b_m(dst, mem)) } -inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } +inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } emit_ld3r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_v16b_m(dst, mem)) } -inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } +inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } emit_ld4r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_v16b_m(dst, mem)) } -inst_subr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_subr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_subr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_subr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_subr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_subr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_subr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_subr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_subr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_subr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_subr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_subr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_asrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_asrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_asrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_asrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_asrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_asrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_asrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_asrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_asrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_asrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_asrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_asrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_lslr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lslr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lslr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lslr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lslr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lslr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lslr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lslr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_lslr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_lslr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_lslr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_lslr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_lsrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_lsrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_lsrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_lsrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_lsrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_ftsmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_ftsmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_ftsmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_ftsmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_ftsmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_ftsmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_ftsmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zh_zh_zh(rz, rz2, rz3)) } emit_ftsmul_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zs_zs_zs(rz, rz2, rz3)) } emit_ftsmul_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zd_zd_zd(rz, rz2, rz3)) } -inst_fsubr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fsubr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fsubr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fsubr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fsubr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fsubr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fsubr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fsubr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fsubr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fdivr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fdivr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fdivr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fdivr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fdivr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fdivr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fdivr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fdivr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fdivr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fnmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fnmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fnmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fnmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fnmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fnmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fnmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmla_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fnmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fnmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fnmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fnmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fnmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_nand_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nand_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nand_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_sel_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orrs_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orrs_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orrs_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_eors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orns_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orns_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orns_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_movs_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_movs_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_movs_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_pb_p_p(rz, rz2, rz3)) } -inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}, {}}} } emit_ptrue_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_pb_i(rz, imm)) } -inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}, {}}} } emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } -inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } -inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } -inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } -inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkb_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_pb_p_pb(rz, rz2, rz3)) } -inst_brkas_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkas_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkas_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_pb_p_pb(rz, rz2, rz3)) } -inst_brkbs_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkbs_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkbs_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pb_p_pb(rz, rz2, rz3)) } -inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkpa_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkpb_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_brkn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_rdffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_pb(rz)) } -inst_wrffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_wrffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_wrffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_pb(rz)) } inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } -inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpeq_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpne_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpne_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpne_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpge_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpge_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpge_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpgt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpgt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpgt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmple_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmple_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmple_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmple_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmple_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmple_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmple_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmple_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmple_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmple_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmple_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmple_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmplt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmplt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmplt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmplt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmplt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmplt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmplt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmplt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmplt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmplt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmplt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmplt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmphi_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmphi_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmphi_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmphi_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmphi_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmphi_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmphi_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmphi_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmphi_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmphi_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmphi_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmphi_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmphs_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmphs_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmphs_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmphs_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmphs_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmphs_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmphs_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmphs_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmphs_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmphs_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmphs_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmphs_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmplo_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmplo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmplo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmplo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmplo_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmplo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmplo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmplo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmplo_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmplo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmplo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmplo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpls_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpls_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpls_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpls_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpls_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpls_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpls_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpls_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpls_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpls_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpls_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpls_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmuo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmuo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmuo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmuo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmuo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmuo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmuo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmuo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmuo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_insr_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -inst_insr_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } -inst_insr_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } -inst_insr_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } +inst_insr_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}, {}}} } emit_insr_zb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zb_r(rz, src)) } emit_insr_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zh_r(rz, src)) } emit_insr_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zs_r(rz, src)) } emit_insr_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zd_r(rz, src)) } -inst_cpy_zb_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zh_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zs_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zd_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +inst_cpy_zb_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zh_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zs_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zd_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } emit_cpy_zb_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zb_p_r(rz, rz2, src)) } emit_cpy_zh_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zh_p_r(rz, rz2, src)) } emit_cpy_zs_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zs_p_r(rz, rz2, src)) } emit_cpy_zd_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zd_p_r(rz, rz2, src)) } -inst_compact_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_compact_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_compact_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_compact_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_compact_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zs_p_zs(rz, rz2, rz3)) } emit_compact_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zd_p_zd(rz, rz2, rz3)) } -inst_ld1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zpb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1b_zqb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zpb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1b_zqb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zb_p_m(rz, rz2, mem)) } emit_ld1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zs_p_m(rz, rz2, mem)) } emit_ld1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zd_p_m(rz, rz2, mem)) } emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } emit_ld1b_zpb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zpb_pnz_m(rz, rz2, mem)) } emit_ld1b_zqb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zqb_pnz_m(rz, rz2, mem)) } -inst_ld1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zph_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1h_zqh_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zph_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1h_zqh_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zh_p_m(rz, rz2, mem)) } emit_ld1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zs_p_m(rz, rz2, mem)) } emit_ld1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zd_p_m(rz, rz2, mem)) } emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } emit_ld1h_zph_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zph_pnz_m(rz, rz2, mem)) } emit_ld1h_zqh_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zqh_pnz_m(rz, rz2, mem)) } -inst_ld1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_zps_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1w_zqs_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_zps_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1w_zqs_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zs_p_m(rz, rz2, mem)) } emit_ld1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zd_p_m(rz, rz2, mem)) } emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } emit_ld1w_zps_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zps_pnz_m(rz, rz2, mem)) } emit_ld1w_zqs_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zqs_pnz_m(rz, rz2, mem)) } -inst_ld1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1d_zpd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1d_zqd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1d_zpd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1d_zqd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zd_p_m(rz, rz2, mem)) } emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } emit_ld1d_zpd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zpd_pnz_m(rz, rz2, mem)) } emit_ld1d_zqd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zqd_pnz_m(rz, rz2, mem)) } -inst_ld1sb_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sb_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sb_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sb_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sb_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zh_p_m(rz, rz2, mem)) } emit_ld1sb_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zs_p_m(rz, rz2, mem)) } emit_ld1sb_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zd_p_m(rz, rz2, mem)) } -inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sh_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zd_p_m(rz, rz2, mem)) } emit_ld1sh_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zs_p_m(rz, rz2, mem)) } -inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sw_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_zd_p_m(rz, rz2, mem)) } -inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zpb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1b_zqb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zpb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1b_zqb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zb_p_m(rz, rz2, mem)) } emit_st1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zs_p_m(rz, rz2, mem)) } emit_st1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zd_p_m(rz, rz2, mem)) } emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } emit_st1b_zpb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zpb_pn_m(rz, rz2, mem)) } emit_st1b_zqb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zqb_pn_m(rz, rz2, mem)) } -inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_st1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zh_p_m(rz, rz2, mem)) } emit_st1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zd_p_m(rz, rz2, mem)) } emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } emit_st1h_zph_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zph_pn_m(rz, rz2, mem)) } emit_st1h_zqh_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zqh_pn_m(rz, rz2, mem)) } emit_st1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zs_p_m(rz, rz2, mem)) } -inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1w_zps_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1w_zqs_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_zps_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1w_zqs_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zs_p_m(rz, rz2, mem)) } emit_st1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zd_p_m(rz, rz2, mem)) } emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } emit_st1w_zps_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zps_pn_m(rz, rz2, mem)) } emit_st1w_zqs_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zqs_pn_m(rz, rz2, mem)) } -inst_st1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1d_zpd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1d_zqd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1d_zpd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1d_zqd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zd_p_m(rz, rz2, mem)) } emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } emit_st1d_zpd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zpd_pn_m(rz, rz2, mem)) } emit_st1d_zqd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zqd_pn_m(rz, rz2, mem)) } -inst_ldff1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_zb_p_m(rz, rz2, mem)) } -inst_ldff1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_zh_p_m(rz, rz2, mem)) } -inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_zs_p_m(rz, rz2, mem)) } -inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_zd_p_m(rz, rz2, mem)) } -inst_whilege_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilege_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilege_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pb_r_r(rz, src, src2)) } emit_whilege_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ph_r_r(rz, src, src2)) } emit_whilege_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ps_r_r(rz, src, src2)) } emit_whilege_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pd_r_r(rz, src, src2)) } -inst_whilegt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilegt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilegt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pb_r_r(rz, src, src2)) } emit_whilegt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ph_r_r(rz, src, src2)) } emit_whilegt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ps_r_r(rz, src, src2)) } emit_whilegt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pd_r_r(rz, src, src2)) } -inst_whilele_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilele_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilele_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pb_r_r(rz, src, src2)) } emit_whilele_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ph_r_r(rz, src, src2)) } emit_whilele_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ps_r_r(rz, src, src2)) } emit_whilele_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pd_r_r(rz, src, src2)) } -inst_whilelt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilelt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pb_r_r(rz, src, src2)) } emit_whilelt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ph_r_r(rz, src, src2)) } emit_whilelt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ps_r_r(rz, src, src2)) } emit_whilelt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pd_r_r(rz, src, src2)) } -inst_whilehi_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehi_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilehi_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pb_r_r(rz, src, src2)) } emit_whilehi_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ph_r_r(rz, src, src2)) } emit_whilehi_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ps_r_r(rz, src, src2)) } emit_whilehi_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pd_r_r(rz, src, src2)) } -inst_whilehs_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehs_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilehs_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pb_r_r(rz, src, src2)) } emit_whilehs_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ph_r_r(rz, src, src2)) } emit_whilehs_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ps_r_r(rz, src, src2)) } emit_whilehs_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pd_r_r(rz, src, src2)) } -inst_whilelo_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelo_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilelo_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pb_r_r(rz, src, src2)) } emit_whilelo_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ph_r_r(rz, src, src2)) } emit_whilelo_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ps_r_r(rz, src, src2)) } emit_whilelo_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pd_r_r(rz, src, src2)) } -inst_whilels_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilels_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilels_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pb_r_r(rz, src, src2)) } emit_whilels_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ph_r_r(rz, src, src2)) } emit_whilels_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ps_r_r(rz, src, src2)) } emit_whilels_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pd_r_r(rz, src, src2)) } -inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqrdmlah_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqrdmlah_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqrdmlah_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zb_zb_zb(rz, rz2, rz3)) } emit_sqrdmlah_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zh_zh_zh(rz, rz2, rz3)) } emit_sqrdmlah_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zs_zs_zs(rz, rz2, rz3)) } emit_sqrdmlah_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zd_zd_zd(rz, rz2, rz3)) } -inst_sqrdmlsh_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqrdmlsh_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqrdmlsh_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqrdmlsh_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqrdmlsh_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqrdmlsh_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqrdmlsh_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqrdmlsh_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqrdmlsh_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zb_zb_zb(rz, rz2, rz3)) } emit_sqrdmlsh_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zh_zh_zh(rz, rz2, rz3)) } emit_sqrdmlsh_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zs_zs_zs(rz, rz2, rz3)) } emit_sqrdmlsh_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zd_zd_zd(rz, rz2, rz3)) } -inst_adclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_adclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_adclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_adclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_adclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zs_zs_zs(rz, rz2, rz3)) } emit_adclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zd_zd_zd(rz, rz2, rz3)) } -inst_adclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_adclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_adclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_adclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_adclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zs_zs_zs(rz, rz2, rz3)) } emit_adclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zd_zd_zd(rz, rz2, rz3)) } -inst_sbclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sbclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sbclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sbclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sbclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zs_zs_zs(rz, rz2, rz3)) } emit_sbclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zd_zd_zd(rz, rz2, rz3)) } -inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sbclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zs_zs_zs(rz, rz2, rz3)) } emit_sbclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zd_zd_zd(rz, rz2, rz3)) } -inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_tbl2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_zb_zb_zb(rz, rz2, rz3)) } -inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_match_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_match_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_ph_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_nmatch_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_nmatch_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_nmatch_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_nmatch_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_nmatch_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_nmatch_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_ph_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_histcnt_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_histcnt_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_histcnt_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_histcnt_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_histcnt_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_histcnt_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_histseg_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_histseg_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_histseg_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_zb_zb_zb(rz, rz2, rz3)) } inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } @@ -3923,163 +3923,163 @@ inst_smstop_none :: #force_inline proc "contextless" () -> Instruct emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } -inst_addha_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +inst_addha_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_addha_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_addva_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +inst_addva_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_addva_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } +inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}, {}}} } emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } -inst_fmopa_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmopa_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_fmops_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmops_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_bfmopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_bfmops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_smopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_smopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_smopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_smopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_smops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_smops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_smops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_smops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_umopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_umopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_umopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_umopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_umops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_umops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_umops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_umops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_usmopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_usmopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -inst_sumopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sumopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -inst_cntb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_fmopa_i_p_p_zs_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_fmopa_i_p_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmopa_i_p_p_zs_zs(imm, rz1, rz2, rz3, rz4)) } +inst_fmops_i_p_p_zs_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_fmops_i_p_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmops_i_p_p_zs_zs(imm, rz1, rz2, rz3, rz4)) } +inst_bfmopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_bfmops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_smopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_smopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_smopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_smops_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_smops_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smops_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_smops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_umopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_umopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_umopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_umops_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_umops_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umops_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_umops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_usmopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_usmopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_usmopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +inst_sumopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sumopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sumopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +inst_cntb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntb_r_i_i(dst, imm, imm2)) } -inst_cnth_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cnth_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cnth_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cnth_r_i_i(dst, imm, imm2)) } -inst_cntw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cntw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntw_r_i_i(dst, imm, imm2)) } -inst_cntd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cntd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntd_r_i_i(dst, imm, imm2)) } -inst_incb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incb_r_i_i(dst, imm, imm2)) } -inst_inch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_inch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_inch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_inch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_inch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_inch_r_i_i(dst, imm, imm2)) } emit_inch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_inch_zh_i_i(rz, imm, imm2)) } -inst_incw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_incw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_incw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incw_r_i_i(dst, imm, imm2)) } emit_incw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incw_zs_i_i(rz, imm, imm2)) } -inst_incd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_incd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_incd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incd_r_i_i(dst, imm, imm2)) } emit_incd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incd_zd_i_i(rz, imm, imm2)) } -inst_decb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decb_r_i_i(dst, imm, imm2)) } -inst_dech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_dech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_dech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_dech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_dech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_dech_r_i_i(dst, imm, imm2)) } emit_dech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_dech_zh_i_i(rz, imm, imm2)) } -inst_decw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_decw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_decw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decw_r_i_i(dst, imm, imm2)) } emit_decw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decw_zs_i_i(rz, imm, imm2)) } -inst_decd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decd_r_i_i(dst, imm, imm2)) } emit_decd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decd_zd_i_i(rz, imm, imm2)) } -inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } +inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_i_i(dst, imm, imm2)) } emit_sqincb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_r_i_i(dst, src, imm, imm2)) } -inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqinch_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqinch_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_i_i(dst, imm, imm2)) } emit_sqinch_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_r_i_i(dst, src, imm, imm2)) } emit_sqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqinch_zh_i_i(rz, imm, imm2)) } -inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_i_i(dst, imm, imm2)) } emit_sqincw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_r_i_i(dst, src, imm, imm2)) } emit_sqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincw_zs_i_i(rz, imm, imm2)) } -inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_i_i(dst, imm, imm2)) } emit_sqincd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_r_i_i(dst, src, imm, imm2)) } emit_sqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincd_zd_i_i(rz, imm, imm2)) } -inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } +inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_i_i(dst, imm, imm2)) } emit_sqdecb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_r_i_i(dst, src, imm, imm2)) } -inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdech_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdech_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_i_i(dst, imm, imm2)) } emit_sqdech_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_r_i_i(dst, src, imm, imm2)) } emit_sqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdech_zh_i_i(rz, imm, imm2)) } -inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_i_i(dst, imm, imm2)) } emit_sqdecw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_zs_i_i(rz, imm, imm2)) } -inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_i_i(dst, imm, imm2)) } emit_sqdecd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_zd_i_i(rz, imm, imm2)) } -inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincb_r_i_i(dst, imm, imm2)) } -inst_uqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqinch_r_i_i(dst, imm, imm2)) } emit_uqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqinch_zh_i_i(rz, imm, imm2)) } -inst_uqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincw_r_i_i(dst, imm, imm2)) } emit_uqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincw_zs_i_i(rz, imm, imm2)) } -inst_uqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincd_r_i_i(dst, imm, imm2)) } emit_uqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincd_zd_i_i(rz, imm, imm2)) } -inst_uqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecb_r_i_i(dst, imm, imm2)) } -inst_uqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdech_r_i_i(dst, imm, imm2)) } emit_uqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdech_zh_i_i(rz, imm, imm2)) } -inst_uqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_r_i_i(dst, imm, imm2)) } emit_uqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_zs_i_i(rz, imm, imm2)) } -inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_r_i_i(dst, imm, imm2)) } emit_uqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_zd_i_i(rz, imm, imm2)) } -inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } emit_cntp_r_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pb(dst, rz1, rz2)) } emit_cntp_r_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ph(dst, rz1, rz2)) } emit_cntp_r_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ps(dst, rz1, rz2)) } emit_cntp_r_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pd(dst, rz1, rz2)) } -inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_incp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pb(dst, rz1)) } emit_incp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ph(dst, rz1)) } emit_incp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ps(dst, rz1)) } @@ -4087,13 +4087,13 @@ emit_incp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_incp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_ph(rz, rz2)) } emit_incp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_ps(rz, rz2)) } emit_incp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_pd(rz, rz2)) } -inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_decp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pb(dst, rz1)) } emit_decp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ph(dst, rz1)) } emit_decp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ps(dst, rz1)) } @@ -4101,17 +4101,17 @@ emit_decp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_decp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_ph(rz, rz2)) } emit_decp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_ps(rz, rz2)) } emit_decp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_pd(rz, rz2)) } -inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_sqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pb(dst, rz1)) } emit_sqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ph(dst, rz1)) } emit_sqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ps(dst, rz1)) } @@ -4123,17 +4123,17 @@ emit_sqincp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_ph(rz, rz2)) } emit_sqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_ps(rz, rz2)) } emit_sqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_pd(rz, rz2)) } -inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_sqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pb(dst, rz1)) } emit_sqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ph(dst, rz1)) } emit_sqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ps(dst, rz1)) } @@ -4145,13 +4145,13 @@ emit_sqdecp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_ph(rz, rz2)) } emit_sqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_ps(rz, rz2)) } emit_sqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_pd(rz, rz2)) } -inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_uqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pb(dst, rz1)) } emit_uqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ph(dst, rz1)) } emit_uqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ps(dst, rz1)) } @@ -4159,13 +4159,13 @@ emit_uqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_ph(rz, rz2)) } emit_uqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_ps(rz, rz2)) } emit_uqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_pd(rz, rz2)) } -inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_uqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pb(dst, rz1)) } emit_uqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ph(dst, rz1)) } emit_uqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ps(dst, rz1)) } @@ -4173,72 +4173,72 @@ emit_uqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_ph(rz, rz2)) } emit_uqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_ps(rz, rz2)) } emit_uqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_pd(rz, rz2)) } -inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } -inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } -inst_mova_zb_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } -inst_mova_i_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +inst_mova_zb_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_mova_i_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}, {}}} } emit_mova_zb_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_zb_p_i(rz, rz2, imm)) } emit_mova_i_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_zb(imm, rz1, rz2)) } -inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } -inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } -inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } -inst_fcmla_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } emit_fcmla_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4h_v4h_v4h_i(dst, src, src2, imm)) } emit_fcmla_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v8h_v8h_v8h_i(dst, src, src2, imm)) } emit_fcmla_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4s_v4s_v4s_i(dst, src, src2, imm)) } emit_fcmla_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v2d_v2d_v2d_i(dst, src, src2, imm)) } -inst_fcadd_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } -inst_fcadd_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } -inst_fcadd_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } -inst_fcadd_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +inst_fcadd_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } emit_fcadd_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4h_v4h_v4h_i(dst, src, src2, imm)) } emit_fcadd_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v8h_v8h_v8h_i(dst, src, src2, imm)) } emit_fcadd_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4s_v4s_v4s_i(dst, src, src2, imm)) } emit_fcadd_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v2d_v2d_v2d_i(dst, src, src2, imm)) } -inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfb_i_p_m(imm, rz1, mem)) } -inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfh_i_p_m(imm, rz1, mem)) } -inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } -inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } -inst_ldnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_zb_p_m(rz, rz2, mem)) } -inst_ldnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_zh_p_m(rz, rz2, mem)) } -inst_ldnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_zs_p_m(rz, rz2, mem)) } -inst_ldnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_zd_p_m(rz, rz2, mem)) } -inst_stnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_zb_p_m(rz, rz2, mem)) } -inst_stnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_zh_p_m(rz, rz2, mem)) } -inst_stnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_zs_p_m(rz, rz2, mem)) } -inst_stnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_zd_p_m(rz, rz2, mem)) } -inst_splice_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_splice_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } emit_splice_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_zb_p_zb_zb(rz, rz2, rz3, rz4)) } -inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zh_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zh_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zh_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zs_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zs_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zs_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zd_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zd_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_reg(src2), {}}} } +inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zh_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zh_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zh_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zs_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zs_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zs_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zd_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zd_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_reg(src2), {}, {}}} } emit_index_zb_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zb_i_i(rz, imm, imm2)) } emit_index_zb_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zb_i_r(rz, imm, src)) } emit_index_zb_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zb_r_i(rz, src, imm)) } @@ -4255,19 +4255,19 @@ emit_index_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_index_zd_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zd_i_r(rz, imm, src)) } emit_index_zd_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zd_r_i(rz, src, imm)) } emit_index_zd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zd_r_r(rz, src, src2)) } -inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl1n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl2n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_nbsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_nbsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_nbsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_pmul_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_pmul_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_pmul_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_zb_zb_zb(rz, rz2, rz3)) } -inst_pmullb_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_pmullb_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } emit_pmullb_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_zd_zs_zs(rz, rz2, rz3)) } -inst_pmullt_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_pmullt_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } emit_pmullt_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_zd_zs_zs(rz, rz2, rz3)) } -inst_bfcvtnt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_bfcvtnt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } emit_bfcvtnt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_zh_p_zs(rz, rz2, rz3)) } inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } @@ -4277,7 +4277,7 @@ inst_tstart_r :: #force_inline proc "contextless" (dst: Register emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } -inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } @@ -4359,21 +4359,21 @@ inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_bfadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_zh_zh_zh(rz, rz2, rz3)) } -inst_bfsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_bfmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } @@ -4391,30 +4391,30 @@ inst_bti_c_none :: #force_inline proc "contextless" () -> Instruct emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_bfclamp_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfclamp_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfclamp_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfminnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_luti2_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti2_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti2_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti2_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti2_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti2_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } emit_luti2_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zpb_zt_z_i(rz, rz2, imm)) } emit_luti2_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zph_zt_z_i(rz, rz2, imm)) } emit_luti2_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zps_zt_z_i(rz, rz2, imm)) } -inst_luti4_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti4_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti4_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti4_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti4_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti4_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } emit_luti4_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zpb_zt_z_i(rz, rz2, imm)) } emit_luti4_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zph_zt_z_i(rz, rz2, imm)) } emit_luti4_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zps_zt_z_i(rz, rz2, imm)) } -inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_zip_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_zpb_zb_zb(rz, rz2, rz3)) } emit_zip_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_zqb_zqb(rz, rz2)) } -inst_uzp_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_uzp_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_uzp_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_zpb_zb_zb(rz, rz2, rz3)) } emit_uzp_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_zqb_zqb(rz, rz2)) } inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } @@ -4579,22 +4579,22 @@ inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruct emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } -inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } +inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } +inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}, {}}} } emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } emit_prfm_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_i_l(imm, label)) } -inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } -inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } -inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } +inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}, {}}} } inst_cmp_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP, dst, imm) } emit_cmp_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_r_sh(dst, src, src_shift, src_amount)) } emit_cmp_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_r_ex(dst, src, src_ext, src_amount)) } emit_cmp_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_i(dst, imm)) } -inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } +inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}, {}}} } inst_cmn_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN, dst, imm) } emit_cmn_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_r_sh(dst, src, src_shift, src_amount)) } emit_cmn_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_r_ex(dst, src, src_ext, src_amount)) } @@ -5870,26 +5870,26 @@ inst_addva :: inst_addva_i_p_p_zs emit_addva :: emit_addva_i_p_p_zs inst_zero :: inst_zero_i emit_zero :: emit_zero_i -inst_fmopa :: inst_fmopa_i_p_p_zs -emit_fmopa :: emit_fmopa_i_p_p_zs -inst_fmops :: inst_fmops_i_p_p_zs -emit_fmops :: emit_fmops_i_p_p_zs -inst_bfmopa :: inst_bfmopa_i_p_p_zh -emit_bfmopa :: emit_bfmopa_i_p_p_zh -inst_bfmops :: inst_bfmops_i_p_p_zh -emit_bfmops :: emit_bfmops_i_p_p_zh -inst_smopa :: inst_smopa_i_p_p_zb -emit_smopa :: emit_smopa_i_p_p_zb -inst_smops :: inst_smops_i_p_p_zb -emit_smops :: emit_smops_i_p_p_zb -inst_umopa :: inst_umopa_i_p_p_zb -emit_umopa :: emit_umopa_i_p_p_zb -inst_umops :: inst_umops_i_p_p_zb -emit_umops :: emit_umops_i_p_p_zb -inst_usmopa :: inst_usmopa_i_p_p_zb -emit_usmopa :: emit_usmopa_i_p_p_zb -inst_sumopa :: inst_sumopa_i_p_p_zb -emit_sumopa :: emit_sumopa_i_p_p_zb +inst_fmopa :: inst_fmopa_i_p_p_zs_zs +emit_fmopa :: emit_fmopa_i_p_p_zs_zs +inst_fmops :: inst_fmops_i_p_p_zs_zs +emit_fmops :: emit_fmops_i_p_p_zs_zs +inst_bfmopa :: inst_bfmopa_i_p_p_zh_zh +emit_bfmopa :: emit_bfmopa_i_p_p_zh_zh +inst_bfmops :: inst_bfmops_i_p_p_zh_zh +emit_bfmops :: emit_bfmops_i_p_p_zh_zh +inst_smopa :: inst_smopa_i_p_p_zb_zb +emit_smopa :: emit_smopa_i_p_p_zb_zb +inst_smops :: inst_smops_i_p_p_zb_zb +emit_smops :: emit_smops_i_p_p_zb_zb +inst_umopa :: inst_umopa_i_p_p_zb_zb +emit_umopa :: emit_umopa_i_p_p_zb_zb +inst_umops :: inst_umops_i_p_p_zb_zb +emit_umops :: emit_umops_i_p_p_zb_zb +inst_usmopa :: inst_usmopa_i_p_p_zb_zb +emit_usmopa :: emit_usmopa_i_p_p_zb_zb +inst_sumopa :: inst_sumopa_i_p_p_zb_zb +emit_sumopa :: emit_sumopa_i_p_p_zb_zb inst_cntb :: inst_cntb_r_i_i emit_cntb :: emit_cntb_r_i_i inst_cnth :: inst_cnth_r_i_i diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index 74ea5654e..283cabe73 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -44,8 +44,8 @@ PATH_LOADER :: #directory + "/../tables.odin" Entry :: struct { mnemonic: lib.Mnemonic, - ops: [4]lib.Operand_Type, - enc: [4]lib.Operand_Encoding, + ops: [5]lib.Operand_Type, + enc: [5]lib.Operand_Encoding, bits: u32, mask: u32, feature: lib.Feature, @@ -260,13 +260,13 @@ emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { // Shared row + flags formatting (compact, matching arm64's original generator) // ----------------------------------------------------------------------------- -write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, - enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { - fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", - mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags, ops)) +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [5]lib.Operand_Type, + enc: [5]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], ops[4], enc[0], enc[1], enc[2], enc[3], enc[4], bits, mask, feature, flags_lit(flags, ops)) } -flags_lit :: proc(f: lib.Encoding_Flags, ops: [4]lib.Operand_Type) -> string { +flags_lit :: proc(f: lib.Encoding_Flags, ops: [5]lib.Operand_Type) -> string { parts: [dynamic]string defer delete(parts) if f.branch { append(&parts, "branch=true") } @@ -321,14 +321,14 @@ Encode_Run :: struct { Decode_Entry :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 22) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index cc2ec5558..e3c910592 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -9,2679 +9,2679 @@ import lib "../.." @(rodata) DECODE_ENTRIES := [2673]lib.Decode_Entry{ - { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, - { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, - { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, - { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, - { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 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.UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, - { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, 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0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, 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{explicit_count=4} }, - { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, 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- { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, - { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, 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{.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, 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{.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .ST1, 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.NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, 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0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, 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{.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, 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{explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, - { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, - { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, - { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {} }, - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {} }, - { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, - { .PACIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, - { .PACIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {} }, - { .AUTIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {} }, - { .AUTIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {} }, - { .PACIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {} }, - { .PACIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {} }, - { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, - { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, - { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, - { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, - { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, - { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, - { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, - { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, - { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, - { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, - { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, - { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, - { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, - { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, - { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, 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{.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, + { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, 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{explicit_count=5} }, + { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800010, 0xFFE08010, .SME, {explicit_count=5} }, + { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800000, 0xFFE08010, .SME, {explicit_count=5} }, + { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800010, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, + { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=5} }, + { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=5} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, + { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, + { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, + { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .SETFFR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, + { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PD,.NONE}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, 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{.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, 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{.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, 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.FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, 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0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, 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0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, 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{.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, 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{ .USHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6,.NONE}, {.VD,.VN,.VM,.IMM6,.NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTW, 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{.RD,.RN,.RM,.NONE,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 7c4ba00a4..5dbff414b 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -10,3531 +10,3531 @@ import lib "../.." @(rodata) ENCODE_FORMS := [2671]lib.Encoding{ // .ADD - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ADDS - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SUB - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SUBS - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .MOVZ - { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVN - { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVK - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .ADR - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, // .ADRP - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, // .AND - { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS - { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR - { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR - { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC - { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS - { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN - { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON - { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, // .LSL - { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LSR - { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ASR - { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ROR - { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .ROR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, // .UDIV - { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SDIV - { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MADD - { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .MSUB - { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMADDL - { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMSUBL - { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMADDL - { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMSUBL - { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMULH - { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMULH - { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .CLZ - { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLZ, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, // .CLS - { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLS, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLS, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLS, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, // .RBIT - { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .RBIT, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .RBIT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV - { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .REV, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 - { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV16, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV16, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV32 - { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV32, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CSEL - { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSEL, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSEL, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINC - { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINC, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINC, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINV - { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINV, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINV, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSNEG - { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CCMP - { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CCMN - { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CSET - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, // .CSETM - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, // .CINC - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .CINV - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .CNEG - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .EXTR - { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .B - { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .B, {.REL_26,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BL - { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .BL, {.REL_26,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BR - { .BR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BR, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .BLR - { .BLR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLR, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .RET - { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, - { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, + { .RET, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .RET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .B_EQ - { .B_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_EQ, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_NE - { .B_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_CS - { .B_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_CC - { .B_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_MI - { .B_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_MI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_PL - { .B_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_PL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_VS - { .B_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_VC - { .B_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_HI - { .B_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_HI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LS - { .B_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_GE - { .B_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LT - { .B_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_GT - { .B_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LE - { .B_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_AL - { .B_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_AL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_NV - { .B_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NV, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .CBZ - { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, - { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBZ, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBZ, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .CBNZ - { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, - { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .TBZ - { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .TBNZ - { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .LDR - { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR - { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, + { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB - { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRB - { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSB - { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRH - { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRH - { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSH - { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRSW - { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDAR - { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLR - { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .LDARB - { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRB - { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDARH - { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRH - { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDXR - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STXR - { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .LDAXR - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLXR - { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .NOP - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, // .YIELD - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, // .WFE - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, // .WFI - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {} }, // .SEV - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {} }, // .SEVL - { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, + { .SEVL, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, // .HINT - { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, + { .HINT, {.IMM_8,.NONE,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, // .MRS - { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, + { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, // .MSR - { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, - { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, + { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, + { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, // .ISB - { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .ISB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DSB - { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .DSB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DMB - { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .DMB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .SVC - { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .SVC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HVC - { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .HVC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .SMC - { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .SMC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .BRK - { .BRK, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .BRK, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HLT - { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .HLT, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .ERET - { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, + { .ERET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .FMOV - { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FMOV, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, // .FABS - { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, // .FNEG - { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FNEG, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, // .FSQRT - { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, // .FADD - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FSUB - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMUL - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIV - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMUL - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMADD - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FMSUB - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMADD - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMSUB - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FCMP - { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCMPE - { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCSEL - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, // .FMAX - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMIN - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMAXNM - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMINNM - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FCVT - { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.S_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.H_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.H_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.S_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .SCVTF - { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .UCVTF - { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZS - { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZU - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAS - { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAU - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNS - { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNU - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPS - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPU - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMS - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMU - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRINTA - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTI - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTM - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTN - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTP - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTX - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTZ - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .TST - { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDUR - { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .STUR - { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .LDURB - { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURB - { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSB - { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURH - { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURH - { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSH - { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSW - { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDXP - { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STXP - { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDAXP - { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STLXP - { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDXRB - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRB - { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRB - { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRB - { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDXRH - { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRH - { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRH - { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRH - { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAPR - { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, // .LDAPRB - { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDAPRH - { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDADD - { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDA - { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDL - { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDAL - { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLR - { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRA - { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRL - { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRAL - { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEOR - { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORA - { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORL - { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORAL - { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSET - { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETA - { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETL - { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETAL - { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAX - { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXA - { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXL - { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXAL - { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMIN - { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINA - { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINL - { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINAL - { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAX - { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXA - { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXL - { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXAL - { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMIN - { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINA - { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINL - { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINAL - { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWP - { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPA - { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPL - { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPAL - { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CAS - { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASA - { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASL - { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASAL - { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASB - { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAB - { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLB - { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALB - { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASH - { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAH - { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLH - { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALH - { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASP - { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPA - { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPL - { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPAL - { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .PACIA - { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIB - { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDA - { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDB - { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIZA - { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACIZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIZB - { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACIZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZA - { .PACDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACDZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZB - { .PACDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACDZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIA - { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIB - { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDA - { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDB - { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIZA - { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIZB - { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZA - { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZB - { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIASP - { .PACIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, + { .PACIASP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, // .PACIBSP - { .PACIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {} }, + { .PACIBSP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {} }, // .AUTIASP - { .AUTIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIASP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {} }, // .AUTIBSP - { .AUTIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIBSP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {} }, // .PACIA1716 - { .PACIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {} }, + { .PACIA1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {} }, // .PACIB1716 - { .PACIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {} }, + { .PACIB1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {} }, // .AUTIA1716 - { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, + { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, // .AUTIB1716 - { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, // .PACGA - { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, + { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, // .XPACI - { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .XPACI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACD - { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .XPACD, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACLRI - { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, + { .XPACLRI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, // .RETAA - { .RETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .RETAA, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .RETAB - { .RETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .RETAB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BRAA - { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAB - { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAAZ - { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BRABZ - { .BRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRABZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRAA - { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAB - { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAAZ - { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRABZ - { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .ERETAA - { .ERETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .ERETAA, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .ERETAB - { .ERETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .ERETAB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BTI - { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, // .IRG - { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .ADDG - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .SUBG - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .GMI - { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBP - { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBPS - { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true, explicit_count=3} }, // .LDG - { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STG - { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .ST2G - { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZG - { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZ2G - { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, // .LDGM - { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGM - { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZGM - { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .CRC32B - { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32H - { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32W - { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32X - { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, + { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .CRC32CB - { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CH - { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CW - { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CX - { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, + { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .AESE - { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESE, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESD - { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESMC - { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESMC, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .AESIMC - { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .SHA1H - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA1C - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1P - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1M - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU0 - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU1 - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256H - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256H2 - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256SU0 - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256SU1 - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H2 - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512SU0 - { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA512SU1 - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .EOR3 - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .BCAX - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .RAX1 - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .XAR - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6,.NONE}, {.VD,.VN,.VM,.IMM6,.NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, // .SM3PARTW1 - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3PARTW2 - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3SS1 - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, // .SM3TT1A - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT1B - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2A - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2B - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM4E - { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SM4E, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SM4EKEY - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL2 - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .BFCVT - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMMLA - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALB - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALT - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFCVTN - { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .BFCVTN2 - { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .MUL - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MLA - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MLS - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .NEG - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, - { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, // .ABS - { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, // .SHADD - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHADD - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHSUB - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHSUB - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SRHADD - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URHADD - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQADD - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQADD - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SQSUB - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQSUB - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SMAX - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMAX - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SMIN - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMIN - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABD - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UABD - { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABA - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UABA - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDP - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDV - { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLP - { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLP - { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADALP - { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADALP - { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLV - { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLV - { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXV - { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMAXV - { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMINV - { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMINV - { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXP - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMAXP - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMINP - { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMINP - { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL - { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL2 - { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL - { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL2 - { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL - { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL2 - { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL - { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL2 - { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW - { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW2 - { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW - { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW2 - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW - { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW2 - { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW - { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW2 - { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN - { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN2 - { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN - { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN2 - { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN - { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN2 - { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN - { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN2 - { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .XTN - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .XTN2 - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN - { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN2 - { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN - { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN2 - { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN - { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN2 - { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMULL - { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMULL2 - { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL - { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL2 - { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL - { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL2 - { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL - { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL2 - { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL - { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL2 - { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL - { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL2 - { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL - { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL2 - { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL - { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL2 - { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL - { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL2 - { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULH - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRDMULH - { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SDOT - { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .UDOT - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .USDOT - { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .FMLA - { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMLS - { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMULX - { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXP - { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINP - { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXNMP - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINNMP - { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXV - { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINV - { .FMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMAXNMV - { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINNMV - { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPE - { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRSQRTE - { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPS - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRSQRTS - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRECPX - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FADDP - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FCVTL - { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTL2 - { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN - { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN2 - { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN - { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN2 - { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCMEQ - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGE - { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGT - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMLE - { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FCMLT - { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FACGE - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FACGT - { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .CMEQ - { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGE - { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGT - { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHI - { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHS - { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMLE - { .CMLE, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMLT - { .CMLT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMTST - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MVN - { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .MVN, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .BIT - { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIT, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BIF - { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIF, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BSL - { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .SHL - { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHL - { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHLU - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHL - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URSHL - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHR - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USHR - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSRA - { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USRA - { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHR - { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSHR - { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSRA - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSRA - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHL - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHL - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SLI - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRI - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHLL - { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHLL2 - { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL - { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL2 - { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SXTL - { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_8H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_4S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SXTL2 - { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL - { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_8H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_4S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL2 - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SHRN - { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHRN2 - { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN - { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN2 - { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN - { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN2 - { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN - { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN2 - { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN - { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN2 - { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN - { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN2 - { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN - { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN2 - { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN - { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN2 - { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .DUP - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_16B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .INS - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, // .MOV - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, - { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, - { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, // .EXT - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .TBX - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .ZIP1 - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT - { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NOT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 - { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CNT - { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, // .URECPE - { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .URSQRTE - { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .MOVI - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .MVNI - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .LD1 - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD2 - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD3 - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD4 - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST1 - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST2 - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST3 - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST4 - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD1R - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD2R - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD3R - { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD4R - { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SUBR - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ASRR - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSLR - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSRR - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FTSMUL - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FSUBR - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIVR - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLA - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLS - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE - { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES - { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, // .PFALSE - { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PD,.NONE}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR - { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR - { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR - { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, + { .SETFFR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ - { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPNE - { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGE - { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGT - { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLE - { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLT - { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHI - { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHS - { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLO - { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLS - { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .FCMNE - { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMUO - { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .INSR - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .CPY - { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .COMPACT - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, // .ST1W - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LDFF1B - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1H - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1W - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1D - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE - { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT - { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELE - { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI - { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS - { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELO - { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELS - { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .SQRDMLAH - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SQRDMLSH - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLB - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLT - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLB - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLT - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .TBL2 - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .MATCH - { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .NMATCH - { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .HISTCNT - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, // .HISTSEG - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .SMSTART - { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, + { .SMSTART, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, // .SMSTOP - { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, + { .SMSTOP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, // .ADDHA - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, + { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZA_TILE_LOW,.PG,.PM3,.VN,.NONE}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ADDVA - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, + { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZA_TILE_LOW,.PG,.PM3,.VN,.NONE}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ZERO - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, // .FMOPA - { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800000, 0xFFE08010, .SME, {explicit_count=5} }, // .FMOPS - { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800010, 0xFFE08010, .SME, {explicit_count=5} }, // .BFMOPA - { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800000, 0xFFE08010, .SME, {explicit_count=5} }, // .BFMOPS - { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800010, 0xFFE08010, .SME, {explicit_count=5} }, // .SMOPA - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .SMOPS - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .UMOPA - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .UMOPS - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .USMOPA - { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=5} }, // .SUMOPA - { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, + { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=5} }, // .CNTB - { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTH - { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTW - { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTD - { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .INCB - { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .INCH - { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .INCW - { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .INCD - { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECB - { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .DECH - { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECW - { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECD - { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCB - { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQINCH - { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCW - { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCD - { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECB - { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQDECH - { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECW - { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECD - { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCB - { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCH - { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCW - { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCD - { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECB - { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECH - { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECW - { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECD - { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .CNTP - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, // .INCP - { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .DECP - { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQINCP - { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQDECP - { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQINCP - { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQDECP - { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .LD1Q - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, // .FCADD - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, // .PRFB - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFH - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFW - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFD - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1B - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1H - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1W - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1D - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .STNT1B - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1H - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1W - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1D - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SPLICE - { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, // .BSL1N - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .BSL2N - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .NBSL - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .PMUL - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .BFCVTNT - { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .LDRAA - { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .LDRAB - { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .TSTART - { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TSTART, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TCOMMIT - { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, + { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, // .TCANCEL - { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, + { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, // .TTEST - { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TTEST, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFET - { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .WFET, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFIT - { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .WFIT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .BC_EQ - { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_NE - { .BC_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_CS - { .BC_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_CC - { .BC_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_MI - { .BC_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_MI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_PL - { .BC_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_PL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_VS - { .BC_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_VC - { .BC_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_HI - { .BC_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_HI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LS - { .BC_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_GE - { .BC_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LT - { .BC_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_GT - { .BC_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LE - { .BC_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_AL - { .BC_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_AL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_NV - { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NV, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .UXTB - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTH - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTW - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .SXTB - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTH - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTW - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .SXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .ADC - { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ADC, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ADCS - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SBC - { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SBC, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .SBCS - { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .NGC - { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .NGC, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .NGC, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .NGCS - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDAPUR - { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .STLUR - { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDAPURB - { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURB - { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURH - { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURH - { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSB - { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSH - { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSW - { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .BFADD - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFSUB - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMUL - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMLA - { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .BFMLS - { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .SB - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, + { .SB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, // .CSDB - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, // .DGH - { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, + { .DGH, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, // .PSB_CSYNC - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, // .TSB_CSYNC - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, // .BTI_J - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_C - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC - { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, + { .BTI_JC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMAXNM - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .BFMINNM - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .LUTI2 - { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .LUTI4 - { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .ZIP - { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, // .UZP - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, // .TLBI_RPALOS - { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_RPAOS - { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1A - { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIPAPA - { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIGDPAPA - { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_PAALL - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDY - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STX - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STY - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZ - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZ - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZI - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZI - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRX - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRY - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA64 - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS64 - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA32 - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS32 - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MAC16 - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA16 - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS16 - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_SET - { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, + { .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, // .AMX_CLR - { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, + { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, // .AMX_VECINT - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_VECFP - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATINT - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATFP - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_GENLUT - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .CPYP - { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYM - { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYE - { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFP - { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFM - { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFE - { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETP - { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETM - { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, // .SETE - { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, + { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, // .DC_IVAC - { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ISW - { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CSW - { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CISW - { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ZVA - { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAC - { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAU - { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIVAC - { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .IC_IALLUIS - { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, + { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, // .IC_IALLU - { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, + { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, // .IC_IVAU - { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1R - { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1W - { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0R - { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0W - { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2R - { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2W - { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3R - { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3W - { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1R - { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1W - { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0R - { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0W - { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VMALLE1 - { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VMALLE1IS - { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VAE1 - { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAE1IS - { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1 - { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1IS - { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1 - { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1IS - { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1 - { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1IS - { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1 - { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1IS - { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ALLE1 - { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE1IS - { .TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE2 - { .TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE2IS - { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE3 - { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE3IS - { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, // .PRFM - { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, // .PRFUM - { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .NEGS - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, - { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMP - { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMN - { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index d9ed00761..89a3fbc05 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -105,4384 +105,4384 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, .ADD = { - {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04000000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04400000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04800000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04000000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04400000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04800000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ADDS = { - {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SUB = { - {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04010000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04410000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04810000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04010000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04410000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04810000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SUBS = { - {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .AND = { - {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x041A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ANDS = { - {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { - {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04180000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04180000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EOR = { - {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04190000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04190000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BIC = { - {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x041B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BICS = { - {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { - {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EON = { - {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LSL = { - {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04138000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04538000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04938000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04138000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04538000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04938000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .LSR = { - {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04118000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04518000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04918000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04118000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04518000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04918000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ASR = { - {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04108000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04508000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04908000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04108000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04508000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04908000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ROR = { - {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04950000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04950000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04940000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04940000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04120000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04520000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04920000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04120000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04520000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04920000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04130000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04530000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04930000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04130000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04530000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04930000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMP = { - {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMN = { - {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSET = { - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSETM = { - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINC = { - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINV = { - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CNEG = { - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6, .NONE}, {.RD, .RN, .RM, .IMM6, .NONE}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .RM, .IMM6, .NONE}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_EQ = { - {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_NE = { - {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_NE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_CS = { - {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_CC = { - {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_MI = { - {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_MI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_PL = { - {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_PL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_VS = { - {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_VC = { - {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_HI = { - {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_HI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_LS = { - {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_LS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_GE = { - {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_GE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_LT = { - {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_LT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_GT = { - {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_GT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_LE = { - {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_LE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_AL = { - {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B_AL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .B_NV = { - {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B_NV, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, - {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, - {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, }, .FMOV = { - {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, - {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, - {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, - {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65408000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65808000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65408000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65808000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65418000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65818000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65418000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65818000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65428000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65828000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65428000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65828000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x654D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x658D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65468000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65868000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65468000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65868000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65478000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65878000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65478000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65878000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65448000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65848000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65448000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65848000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65458000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65858000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65458000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65858000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .TST = { - {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4, .NONE}, {.RD, .RN, .IMM6, .IMM_HW, .NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4, .NONE}, {.RD, .RN, .IMM6, .IMM_HW, .NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6, .NONE}, {.VD, .VN, .VM, .IMM6, .NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .MUL = { - {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04100000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04500000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04900000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04100000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04500000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04900000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MLA = { - {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .MLS = { - {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .NEG = { - {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ABS = { - {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04080000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04480000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04880000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04080000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04480000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04880000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04090000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04490000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04890000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04090000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04490000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04890000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ADDP = { - {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SMULL = { - {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMULL2 = { - {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL = { - {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL2 = { - {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .FMLA = { - {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H, .NONE}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S, .NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D, .NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMLS = { - {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H, .NONE}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S, .NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D, .NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMAXP = { - {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINP = { - {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXV = { - {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINV = { - {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, }, .FADDP = { - {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SHL = { - {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHL = { - {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .DUP = { - {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, }, .MOV = { - {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, - {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .EXT = { - {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_EXT_IDX, .NONE}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_EXT_IDX, .NONE}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT, .NONE}, {.VD, .VD, .VN, .SVE_EXT_IMM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT, .NONE}, {.VD, .VD, .VN, .SVE_EXT_IMM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .NOT = { - {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .URECPE = { - {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSQRTE = { - {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04030000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04430000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04830000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04030000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04430000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04830000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ASRR = { - {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSLR = { - {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSRR = { - {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .FTSMUL = { - {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUBR = { - {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIVR = { - {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMLA = { - {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .FNMLS = { - {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, + {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, + {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PD, .NONE, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PD, .NONE, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PD, .NONE}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, }, .SETFFR = { - {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { - {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .CPY = { - {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .COMPACT = { - {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4C08000, 0xFFE0A000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE4C08000, 0xFFE0A000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { - {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQRDMLSH = { - {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .ADCLB = { - {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADCLT = { - {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLB = { - {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLT = { - {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { - {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .HISTSEG = { - {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMSTART = { - {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .SMSTOP = { - {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, }, .ADDHA = { - {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZA_TILE_LOW, .PG, .PM3, .VN, .NONE}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ADDVA = { - {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZA_TILE_LOW, .PG, .PM3, .VN, .NONE}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, }, .FMOPA = { - {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMOPS = { - {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPA = { - {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPS = { - {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SMOPA = { - {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SMOPS = { - {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPA = { - {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPS = { - {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .USMOPA = { - {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SUMOPA = { - {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .CNTB = { - {{.CNTB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTH = { - {{.CNTH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTW = { - {{.CNTW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTD = { - {{.CNTD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .INCB = { - {{.INCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, }, .INCH = { - {{.INCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .INCW = { - {{.INCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .INCD = { - {{.INCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECB = { - {{.DECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, }, .DECH = { - {{.DECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECW = { - {{.DECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECD = { - {{.DECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .SQINCB = { - {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCH = { - {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCW = { - {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCD = { - {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECB = { - {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECH = { - {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECW = { - {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECD = { - {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCB = { - {{.UQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCH = { - {{.UQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCW = { - {{.UQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCD = { - {{.UQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECB = { - {{.UQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECH = { - {{.UQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECW = { - {{.UQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECD = { - {{.UQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .CNTP = { - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .INCP = { - {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .DECP = { - {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .SQINCP = { - {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .SQDECP = { - {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQINCP = { - {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQDECP = { - {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { - {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { - {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BSL1N = { - {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BSL2N = { - {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NBSL = { - {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .PMUL = { - {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVTNT = { - {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .LDRAA = { - {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .LDRAB = { - {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, }, .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, }, .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, }, .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, + {{.WFET, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .BC_EQ = { - {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_NE = { - {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_CS = { - {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_CC = { - {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_MI = { - {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_PL = { - {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_VS = { - {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_VC = { - {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_HI = { - {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_LS = { - {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_GE = { - {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_LT = { - {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_GT = { - {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_LE = { - {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_AL = { - {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BC_NV = { - {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, }, .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLUR = { - {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURB = { - {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURH = { - {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65008000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65008000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65018000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65018000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65028000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65028000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { - {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLS = { - {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.SB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.CSDB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.DGH, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BFCLAMP = { - {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65048000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65048000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65058000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, }, .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .PRFM = { - {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, - {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, }, .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMP = { - {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMN = { - {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, } diff --git a/core/rexcode/isa/arm64/tables.odin b/core/rexcode/isa/arm64/tables.odin index 1f19e6ed1..a4ada97b1 100644 --- a/core/rexcode/isa/arm64/tables.odin +++ b/core/rexcode/isa/arm64/tables.odin @@ -25,14 +25,14 @@ Encode_Run :: struct { Decode_Entry :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 22) Decode_Index :: struct #packed { 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b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin @@ -108,7 +108,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_shifted(a.X2, .LSL, 3), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_shifted(a.X2, .LSL, 3), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -126,7 +126,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.SP), a.op_extended(a.W1, .UXTW, 2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.SP), a.op_extended(a.W1, .UXTW, 2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -281,7 +281,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADR, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_label(0, 4), {}, {}}, + ops = {a.op_reg(a.X0), a.op_label(0, 4), {}, {}, {}}, }, a.inst_none(.NOP), a.inst_none(.NOP), @@ -308,11 +308,11 @@ run_pipeline_tests :: proc() { a.inst_none(.NOP), a.Instruction{ mnemonic = .SVC, operand_count = 1, length = 4, - ops = {a.op_imm(1, 2), {}, {}, {}}, + ops = {a.op_imm(1, 2), {}, {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}}, + ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -484,7 +484,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), {}}, + ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -511,7 +511,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 4, length = 4, - ops = {a.op_z_s(0), a.op_reg(p0), a.op_z_s(0), a.op_z_s(1)}, + ops = {a.op_z_s(0), a.op_reg(p0), a.op_z_s(0), a.op_z_s(1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -529,7 +529,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .PTRUE, operand_count = 2, length = 4, - ops = {a.op_reg(p0), a.op_imm(0x1F, 1), {}, {}}, + ops = {a.op_reg(p0), a.op_imm(0x1F, 1), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -568,8 +568,9 @@ run_pipeline_tests :: proc() { p1 := a.Register(a.REG_P | 1) insts := []a.Instruction{ a.Instruction{ - mnemonic = .FMOPA, operand_count = 4, length = 4, - ops = {a.op_imm(0, 1), a.op_reg(p0), a.op_reg(p1), a.op_z_s(0)}, + mnemonic = .FMOPA, operand_count = 5, length = 4, + ops = {a.op_reg(a.Register(a.REG_ZA | 0)), a.op_reg(p0), a.op_reg(p1), + a.op_z_s(0), a.op_z_s(0)}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -698,19 +699,19 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}}, + ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X1), a.op_sysreg(a.TPIDR_EL0), {}, {}}, + ops = {a.op_reg(a.X1), a.op_sysreg(a.TPIDR_EL0), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X2), a.op_sysreg(a.CNTVCT_EL0), {}, {}}, + ops = {a.op_reg(a.X2), a.op_sysreg(a.CNTVCT_EL0), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X3), a.op_sysreg(a.DCZID_EL0), {}, {}}, + ops = {a.op_reg(a.X3), a.op_sysreg(a.DCZID_EL0), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -753,7 +754,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .CMP, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_shifted(a.X1, .LSL, 0), {}, {}}, + ops = {a.op_reg(a.X0), a.op_shifted(a.X1, .LSL, 0), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -775,15 +776,15 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .CPYP, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, a.Instruction{ mnemonic = .CPYM, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, a.Instruction{ mnemonic = .CPYE, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -805,7 +806,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .FMLA, operand_count = 4, length = 4, - ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), a.op_imm(2, 1)}, + ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), a.op_imm(2, 1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -832,7 +833,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .LD1W, operand_count = 3, length = 4, - ops = {a.op_z_s(0), a.op_reg(p0), a.op_mem(mem), {}}, + ops = {a.op_z_s(0), a.op_reg(p0), a.op_mem(mem), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -859,7 +860,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .LD1B, operand_count = 3, length = 4, - ops = {a.op_za_slice(0, 2, 5, a.ZSHAPE_B, true), a.op_reg(p5), a.op_mem(mem), {}}, + ops = {a.op_za_slice(0, 2, 5, a.ZSHAPE_B, true), a.op_reg(p5), a.op_mem(mem), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -888,7 +889,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .FCMLA, operand_count = 4, length = 4, - ops = {a.op_v_4s(a.V0), a.op_v_4s(a.V1), a.op_v_4s(a.V2), a.op_imm(0, 1)}, + ops = {a.op_v_4s(a.V0), a.op_v_4s(a.V1), a.op_v_4s(a.V2), a.op_imm(0, 1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -958,7 +959,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X7), a.op_sysreg(a.RNDR), {}, {}}, + ops = {a.op_reg(a.X7), a.op_sysreg(a.RNDR), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) diff --git a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin index 1baf215a4..5108643b5 100644 --- a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin @@ -77,12 +77,12 @@ Operand_Category :: enum { } Operand_Signature :: struct { - types: [4]a.Operand_Type, + types: [5]a.Operand_Type, // The encoding each operand uses. Needed because the operand TYPE is not // always enough: .VEC_INDEX is a lane index under NEON_IDX*/NEON_LANE_*, // which prints glued to its register, but EXT's byte index shares the type // and prints as a plain `#3`. - encs: [4]a.Operand_Encoding, + encs: [5]a.Operand_Encoding, count: int, } @@ -305,7 +305,7 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { // included; only truly implicit operands (enc == .IMPL, which AArch64's tables // never actually use) carry no param. build_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) { - for i in 0..<4 { + for i in 0..<5 { op := form.ops[i] if op == .NONE { continue } @@ -333,8 +333,8 @@ Param :: struct { // the shift/extend kind and amount. This is the single source of truth for // parameter names; param_list derives the typed declarations from it so the // declared params always match the expressions that reference them. -operand_primary_names :: proc(sig: Operand_Signature) -> [4][3]string { - result: [4][3]string +operand_primary_names :: proc(sig: Operand_Signature) -> [5][3]string { + result: [5][3]string reg_count := 0 imm_count := 0 zp_count := 0 @@ -620,7 +620,7 @@ write_inst_fallback :: proc(sb: ^strings.Builder, entry: Proc_Entry) { defer delete(mstr) fmt.sbprintf(sb, "Instruction{{mnemonic = .%s, operand_count = %d, length = 4, ops = {{", mstr, sig.count) - for i in 0..<4 { + for i in 0..<5 { if i > 0 { strings.write_string(sb, ", ") } if i < sig.count { write_operand_expr(sb, sig.types[i], sig.encs[i], pnames[i])