diff --git a/core/rexcode/arm64/mnemonic_builders.odin b/core/rexcode/arm64/mnemonic_builders.odin index c9507200c..1ac009f7a 100644 --- a/core/rexcode/arm64/mnemonic_builders.odin +++ b/core/rexcode/arm64/mnemonic_builders.odin @@ -1351,6 +1351,12 @@ inst_sve_lsl_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_lsl_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsl_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_lsr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_lsr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_asrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_asrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_lslr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSLR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_lslr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lslr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_lsrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_lsrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_abs_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ABS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } emit_sve_abs_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_abs_pred_z_p_z(rz, rz2, rz3)) } inst_sve_neg_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NEG_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } @@ -1377,10 +1383,14 @@ inst_sve_fadd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_fadd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fadd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fsub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_sve_fsub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsub_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fsubr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUBR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fsubr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsubr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fmul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_sve_fmul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmul_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIV_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_sve_fdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fdivr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIVR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fdivr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdivr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fmax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAX_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_sve_fmax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fmin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMIN_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } @@ -1395,6 +1405,22 @@ inst_sve_fneg_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_fneg_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fneg_z_z_p_z(rz, rz2, rz3)) } inst_sve_fsqrt_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSQRT_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } emit_sve_fsqrt_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsqrt_z_z_p_z(rz, rz2, rz3)) } +inst_sve_frecpx_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPX_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frecpx_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecpx_z_z_p_z(rz, rz2, rz3)) } +inst_sve_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintn_z_p_z(rz, rz2, rz3)) } +inst_sve_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintp_z_p_z(rz, rz2, rz3)) } +inst_sve_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintm_z_p_z(rz, rz2, rz3)) } +inst_sve_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintz_z_p_z(rz, rz2, rz3)) } +inst_sve_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinta_z_p_z(rz, rz2, rz3)) } +inst_sve_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintx_z_p_z(rz, rz2, rz3)) } +inst_sve_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinti_z_p_z(rz, rz2, rz3)) } inst_sve_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_sve_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } @@ -1427,6 +1453,12 @@ inst_sve_orrs_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_orrs_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orrs_p_p_p_p_p(rz, rz2, rz3, rz4)) } inst_sve_eors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_sve_eors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eors_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_nands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_nands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nands_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_nors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_nors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nors_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_orns_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORNS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_orns_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orns_p_p_p_p_p(rz, rz2, rz3, rz4)) } inst_sve_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } emit_sve_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrue_p_i(rz, imm)) } inst_sve_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } @@ -1437,6 +1469,18 @@ inst_sve_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pfirst_p_p_p(rz, rz2, rz3)) } inst_sve_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_sve_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pnext_p_p_p(rz, rz2, rz3)) } +inst_sve_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brka_p_p_p(rz, rz2, rz3)) } +inst_sve_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkb_p_p_p(rz, rz2, rz3)) } +inst_sve_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkas_p_p_p(rz, rz2, rz3)) } +inst_sve_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkbs_p_p_p(rz, rz2, rz3)) } +inst_sve_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } inst_sve_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } @@ -1445,12 +1489,36 @@ inst_sve_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmle_p_p_z(rz, rz2, rz3)) } +inst_sve_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmlt_p_p_z(rz, rz2, rz3)) } +inst_sve_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_dup_z_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_DUP_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } emit_sve_dup_z_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_dup_z_z_r(rz, src)) } +inst_sve_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_sve_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_insr_z_r(rz, src)) } inst_sve_rev_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_sve_rev_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_z_z_z(rz, rz2)) } inst_sve_rev_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } @@ -1481,6 +1549,8 @@ inst_sve_trn1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2 emit_sve_trn1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_p_p_p_p(rz, rz2, rz3)) } inst_sve_trn2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_sve_trn2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_p_p_p_p(rz, rz2, rz3)) } +inst_sve_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_sve_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_compact_z_p_z(rz, rz2, rz3)) } inst_sve_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } emit_sve_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_z_p_m(rz, rz2, mem)) } inst_sve_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } @@ -1559,6 +1629,10 @@ inst_sve_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> emit_sve_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesmc_z(rz)) } inst_sve_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } emit_sve_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesimc_z(rz)) } +inst_sve_bcax_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BCAX_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_bcax_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bcax_z_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_sve_eor3_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR3_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_eor3_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor3_z_z_z_z_z(rz, rz2, rz3, rz4)) } inst_sve_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_sve_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_match_p_p_z_z(rz, rz2, rz3, rz4)) } inst_sve_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } @@ -3422,6 +3496,12 @@ inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z +inst_sve_asrr_pred :: inst_sve_asrr_pred_z_p_z_z +emit_sve_asrr_pred :: emit_sve_asrr_pred_z_p_z_z +inst_sve_lslr_pred :: inst_sve_lslr_pred_z_p_z_z +emit_sve_lslr_pred :: emit_sve_lslr_pred_z_p_z_z +inst_sve_lsrr_pred :: inst_sve_lsrr_pred_z_p_z_z +emit_sve_lsrr_pred :: emit_sve_lsrr_pred_z_p_z_z inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z @@ -3448,10 +3528,14 @@ inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z +inst_sve_fsubr_pred :: inst_sve_fsubr_pred_z_p_z_z +emit_sve_fsubr_pred :: emit_sve_fsubr_pred_z_p_z_z inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z +inst_sve_fdivr_pred :: inst_sve_fdivr_pred_z_p_z_z +emit_sve_fdivr_pred :: emit_sve_fdivr_pred_z_p_z_z inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z @@ -3466,6 +3550,22 @@ inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z +inst_sve_frecpx_z :: inst_sve_frecpx_z_z_p_z +emit_sve_frecpx_z :: emit_sve_frecpx_z_z_p_z +inst_sve_frintn :: inst_sve_frintn_z_p_z +emit_sve_frintn :: emit_sve_frintn_z_p_z +inst_sve_frintp :: inst_sve_frintp_z_p_z +emit_sve_frintp :: emit_sve_frintp_z_p_z +inst_sve_frintm :: inst_sve_frintm_z_p_z +emit_sve_frintm :: emit_sve_frintm_z_p_z +inst_sve_frintz :: inst_sve_frintz_z_p_z +emit_sve_frintz :: emit_sve_frintz_z_p_z +inst_sve_frinta :: inst_sve_frinta_z_p_z +emit_sve_frinta :: emit_sve_frinta_z_p_z +inst_sve_frintx :: inst_sve_frintx_z_p_z +emit_sve_frintx :: emit_sve_frintx_z_p_z +inst_sve_frinti :: inst_sve_frinti_z_p_z +emit_sve_frinti :: emit_sve_frinti_z_p_z inst_sve_fmla :: inst_sve_fmla_z_p_z_z emit_sve_fmla :: emit_sve_fmla_z_p_z_z inst_sve_fmls :: inst_sve_fmls_z_p_z_z @@ -3498,6 +3598,12 @@ inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p +inst_sve_nands_p :: inst_sve_nands_p_p_p_p_p +emit_sve_nands_p :: emit_sve_nands_p_p_p_p_p +inst_sve_nors_p :: inst_sve_nors_p_p_p_p_p +emit_sve_nors_p :: emit_sve_nors_p_p_p_p_p +inst_sve_orns_p :: inst_sve_orns_p_p_p_p_p +emit_sve_orns_p :: emit_sve_orns_p_p_p_p_p inst_sve_ptrue :: inst_sve_ptrue_p_i emit_sve_ptrue :: emit_sve_ptrue_p_i inst_sve_ptrues :: inst_sve_ptrues_p_i @@ -3508,6 +3614,18 @@ inst_sve_pfirst :: inst_sve_pfirst_p_p_p emit_sve_pfirst :: emit_sve_pfirst_p_p_p inst_sve_pnext :: inst_sve_pnext_p_p_p emit_sve_pnext :: emit_sve_pnext_p_p_p +inst_sve_brka :: inst_sve_brka_p_p_p +emit_sve_brka :: emit_sve_brka_p_p_p +inst_sve_brkb :: inst_sve_brkb_p_p_p +emit_sve_brkb :: emit_sve_brkb_p_p_p +inst_sve_brkas :: inst_sve_brkas_p_p_p +emit_sve_brkas :: emit_sve_brkas_p_p_p +inst_sve_brkbs :: inst_sve_brkbs_p_p_p +emit_sve_brkbs :: emit_sve_brkbs_p_p_p +inst_sve_brkpa :: inst_sve_brkpa_p_p_p_p +emit_sve_brkpa :: emit_sve_brkpa_p_p_p_p +inst_sve_brkpb :: inst_sve_brkpb_p_p_p_p +emit_sve_brkpb :: emit_sve_brkpb_p_p_p_p inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z @@ -3516,12 +3634,36 @@ inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z +inst_sve_cmple :: inst_sve_cmple_p_p_z_z +emit_sve_cmple :: emit_sve_cmple_p_p_z_z +inst_sve_cmplt :: inst_sve_cmplt_p_p_z_z +emit_sve_cmplt :: emit_sve_cmplt_p_p_z_z inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z +inst_sve_cmplo :: inst_sve_cmplo_p_p_z_z +emit_sve_cmplo :: emit_sve_cmplo_p_p_z_z +inst_sve_cmpls :: inst_sve_cmpls_p_p_z_z +emit_sve_cmpls :: emit_sve_cmpls_p_p_z_z +inst_sve_fcmeq :: inst_sve_fcmeq_p_p_z_z +emit_sve_fcmeq :: emit_sve_fcmeq_p_p_z_z +inst_sve_fcmne :: inst_sve_fcmne_p_p_z_z +emit_sve_fcmne :: emit_sve_fcmne_p_p_z_z +inst_sve_fcmge :: inst_sve_fcmge_p_p_z_z +emit_sve_fcmge :: emit_sve_fcmge_p_p_z_z +inst_sve_fcmgt :: inst_sve_fcmgt_p_p_z_z +emit_sve_fcmgt :: emit_sve_fcmgt_p_p_z_z +inst_sve_fcmle :: inst_sve_fcmle_p_p_z +emit_sve_fcmle :: emit_sve_fcmle_p_p_z +inst_sve_fcmlt :: inst_sve_fcmlt_p_p_z +emit_sve_fcmlt :: emit_sve_fcmlt_p_p_z +inst_sve_fcmuo :: inst_sve_fcmuo_p_p_z_z +emit_sve_fcmuo :: emit_sve_fcmuo_p_p_z_z inst_sve_dup_z :: inst_sve_dup_z_z_r emit_sve_dup_z :: emit_sve_dup_z_z_r +inst_sve_insr :: inst_sve_insr_z_r +emit_sve_insr :: emit_sve_insr_z_r inst_sve_rev_z :: inst_sve_rev_z_z_z emit_sve_rev_z :: emit_sve_rev_z_z_z inst_sve_rev_p :: inst_sve_rev_p_p_p @@ -3552,6 +3694,8 @@ inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p +inst_sve_compact :: inst_sve_compact_z_p_z +emit_sve_compact :: emit_sve_compact_z_p_z inst_sve_ld1b :: inst_sve_ld1b_z_p_m emit_sve_ld1b :: emit_sve_ld1b_z_p_m inst_sve_ld1h :: inst_sve_ld1h_z_p_m @@ -3630,6 +3774,10 @@ inst_sve_aesmc :: inst_sve_aesmc_z emit_sve_aesmc :: emit_sve_aesmc_z inst_sve_aesimc :: inst_sve_aesimc_z emit_sve_aesimc :: emit_sve_aesimc_z +inst_sve_bcax_z :: inst_sve_bcax_z_z_z_z_z +emit_sve_bcax_z :: emit_sve_bcax_z_z_z_z_z +inst_sve_eor3_z :: inst_sve_eor3_z_z_z_z_z +emit_sve_eor3_z :: emit_sve_eor3_z_z_z_z_z inst_sve_match :: inst_sve_match_p_p_z_z emit_sve_match :: emit_sve_match_p_p_z_z inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z diff --git a/core/rexcode/arm64/tablegen/encoding_table.odin b/core/rexcode/arm64/tablegen/encoding_table.odin index 391442b1e..f0311769a 100644 --- a/core/rexcode/arm64/tablegen/encoding_table.odin +++ b/core/rexcode/arm64/tablegen/encoding_table.odin @@ -4583,5 +4583,177 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, }, + + // SVE predicated / compare / predicate-logical / SVE2. + .SVE_FRINTN = { + {.SVE_FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTP = { + {.SVE_FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTM = { + {.SVE_FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTZ = { + {.SVE_FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTA = { + {.SVE_FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTX = { + {.SVE_FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRINTI = { + {.SVE_FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FRECPX_Z = { + {.SVE_FRECPX_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRECPX_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, + {.SVE_FRECPX_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_ASRR_PRED = { + {.SVE_ASRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, + {.SVE_ASRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, + {.SVE_ASRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, + {.SVE_ASRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_LSLR_PRED = { + {.SVE_LSLR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSLR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSLR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSLR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_LSRR_PRED = { + {.SVE_LSRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, + {.SVE_LSRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FSUBR_PRED = { + {.SVE_FSUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, + {.SVE_FSUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, + {.SVE_FSUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FDIVR_PRED = { + {.SVE_FDIVR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, + {.SVE_FDIVR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, + {.SVE_FDIVR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, + }, + .SVE_FCMEQ = { + {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, + }, + .SVE_FCMGE = { + {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, + }, + .SVE_FCMGT = { + {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, + }, + .SVE_FCMNE = { + {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, + }, + .SVE_FCMUO = { + {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, + {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, + }, + .SVE_FCMLE = { + {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, + {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, + {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, + }, + .SVE_FCMLT = { + {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, + {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, + {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, + }, + .SVE_CMPLE = { + {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, + }, + .SVE_CMPLO = { + {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, + }, + .SVE_CMPLS = { + {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, + }, + .SVE_CMPLT = { + {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, + {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, + }, + .SVE_NANDS_P = { + {.SVE_NANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, + }, + .SVE_NORS_P = { + {.SVE_NORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, + }, + .SVE_ORNS_P = { + {.SVE_ORNS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, + }, + .SVE_BRKPA = { + {.SVE_BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, + }, + .SVE_BRKPB = { + {.SVE_BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, + }, + .SVE_BRKA = { + {.SVE_BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, + }, + .SVE_BRKB = { + {.SVE_BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, + }, + .SVE_BRKAS = { + {.SVE_BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, + }, + .SVE_BRKBS = { + {.SVE_BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, + }, + .SVE_EOR3_Z = { + {.SVE_EOR3_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, + }, + .SVE_BCAX_Z = { + {.SVE_BCAX_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, + }, + .SVE_INSR = { + {.SVE_INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, + {.SVE_INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, + {.SVE_INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, + {.SVE_INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, + }, + .SVE_COMPACT = { + {.SVE_COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, + {.SVE_COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, + }, // SPECGEN:END } diff --git a/core/rexcode/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/arm64/tablegen/generated/decode_tables.odin index e5d0487d7..940a8a43d 100644 --- a/core/rexcode/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2277]lib.Decode_Entry{ +DECODE_ENTRIES := [2373]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, @@ -92,108 +92,166 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SVE_REV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, { .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, - { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, + { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .SVE_INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, { .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, { .SVE_AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, { .SME_RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .SVE_BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, + { .SVE_BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, + { .SVE_BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .SVE_BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, { .SVE_AND_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, { .SVE_ORR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, { .SVE_EOR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, { .SVE_BIC_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_ASRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_ASRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, + { .SVE_ASRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, + { .SVE_ASRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_LSRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_LSRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .SVE_FSUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, + { .SVE_FSUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, + { .SVE_FSUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FDIVR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FDIVR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, + { .SVE_FDIVR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRECPX_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRECPX_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRECPX_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, { .SVE_ZIP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, { .SVE_ZIP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, { .SVE_UZP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, { .SVE_UZP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, { .SVE_TRN1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, { .SVE_TRN2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, + { .SVE_COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, + { .SVE_COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, { .SVE_SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, + { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, + { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, @@ -204,6 +262,8 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .SVE_TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, { .SVE_TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, + { .SVE_BCAX_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_EOR3_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, { .SVE_FMLA_IDX_S, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, { .SVE_FMLA_IDX_D, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, @@ -224,6 +284,11 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SVE_BFSUB_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, { .SVE_BFMUL_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, { .SVE_BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, + { .SVE_NANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .SVE_NORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .SVE_ORNS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .SVE_BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, + { .SVE_BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, { .SVE_WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, { .SVE_WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, { .SVE_WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, @@ -247,162 +312,193 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, { .SVE_LDR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, { .SVE_STR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, + { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, { .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, + { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, { .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, + { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, + { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, { .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, + { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, { .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, + { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, { .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, + { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, + { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, { .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, { .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, @@ -511,10 +607,10 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .CASP, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true} }, { .CASPA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true} }, { .CASPA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {} }, - { .CASPL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, { .CASPL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {} }, - { .CASPAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, { .CASPAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {} }, + { .CASPAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, { .STXP, {.W_REG,.X_REG,.X_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true} }, { .STXP, {.W_REG,.W_REG,.W_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, @@ -543,20 +639,20 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .MOV_REG, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, - { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, { .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, { .ADD_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, { .ADDS_ER, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} }, @@ -591,18 +687,18 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .EON_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, { .LD1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, { .ST1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} }, - { .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, { .LD1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, - { .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, + { .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, { .ST1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, + { .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, { .LD1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, { .ST1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} }, - { .LDP_V, {.Q_REG,.Q_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, - { .LDP_V, {.D_REG,.D_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, { .LDP_V, {.S_REG,.S_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .STP_V, {.S_REG,.S_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .LDP_V, {.D_REG,.D_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP_V, {.Q_REG,.Q_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, { .STP_V, {.Q_REG,.Q_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, { .STP_V, {.D_REG,.D_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .STP_V, {.S_REG,.S_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {} }, { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {} }, { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {} }, @@ -611,340 +707,340 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, + { .NEG_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, + { .NEG_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, + { .NEG_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, { .NEG_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, { .NEG_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, 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{.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {} }, + { .MVN_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {} }, + { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {} }, + { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {} }, { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {} }, - { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {} }, { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {} }, + { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {} }, { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {} }, { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {} }, + { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {} }, { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {} }, + { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {} }, { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, { .DUP_V, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {} }, + { .DUP_V, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, { .DUP_V, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {} }, - { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + { .DUP_V, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, + { .DUP_V, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, + { .DUP_V, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, + { .DUP_V, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, { .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, { .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, { .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, { .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, { .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, { .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, { .DUP_V, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {} }, - { .DUP_V, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, { .DUP_V, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {} }, + { .DUP_V, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {} }, { .SHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, { .SHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, { .SQSHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {} }, + { .SQSHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {} }, - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {} }, { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {} }, { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {} }, { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {} }, { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {} }, @@ -953,16 +1049,16 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {} }, { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {} }, { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {} }, - { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {} }, + { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {} }, - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {} }, { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {} }, { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {} }, { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {} }, @@ -986,46 +1082,46 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .DUP_V, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, { .DUP_V, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {} }, + { .FMOV_V_IMM, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV_V_IMM, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, { .FMOV_V_IMM, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, { .FMOV_V_IMM, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, { .FMOV_V_IMM, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, { .SHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, { .SHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, { .SQSHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, { .SQSHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {} }, { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {} }, { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {} }, { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {} }, { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {} }, { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {} }, { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {} }, { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {} }, { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {} }, { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {} }, { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {} }, { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {} }, { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {} }, { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {} }, { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {} }, { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {} }, { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {} }, { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {} }, { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {} }, @@ -1661,10 +1757,10 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {} }, { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, - { .CMP_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, { .CMP_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMP_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, { .CMN_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true} }, { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true} }, { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, @@ -1683,8 +1779,8 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, { .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, { .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, { .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, { .TST_IMM, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, @@ -1964,16 +2060,16 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .LDGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, { .STGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true} }, { .STZGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} }, - { .LDAPUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, + { .LDAPUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, { .STLUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} }, { .STLUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} }, { .STLURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {} }, { .LDAPURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {} }, { .STLURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {} }, - { .LDAPURSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPURSB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPURSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, { .LDAPURSH, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPURSW, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, @@ -2030,8 +2126,8 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, { .LSLV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, { .LSLV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, { .LSRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -2059,12 +2155,12 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {} }, { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {} }, { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, - { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, { .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, @@ -2291,18 +2387,18 @@ DECODE_ENTRIES := [2277]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 75}, - 0x02 = { 75, 379}, - 0x04 = { 454, 76}, - 0x05 = { 530, 50}, - 0x06 = { 580, 14}, - 0x07 = { 594, 1058}, - 0x08 = {1652, 16}, - 0x09 = {1668, 34}, - 0x0A = {1702, 100}, - 0x0B = {1802, 21}, - 0x0C = {1823, 167}, - 0x0D = {1990, 92}, - 0x0E = {2082, 19}, - 0x0F = {2101, 176}, + 0x02 = { 75, 475}, + 0x04 = { 550, 76}, + 0x05 = { 626, 50}, + 0x06 = { 676, 14}, + 0x07 = { 690, 1058}, + 0x08 = {1748, 16}, + 0x09 = {1764, 34}, + 0x0A = {1798, 100}, + 0x0B = {1898, 21}, + 0x0C = {1919, 167}, + 0x0D = {2086, 92}, + 0x0E = {2178, 19}, + 0x0F = {2197, 176}, } diff --git a/core/rexcode/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/arm64/tablegen/generated/encode_tables.odin index b9353c550..2f940ae65 100644 --- a/core/rexcode/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2275]lib.Encoding{ +ENCODE_FORMS := [2371]lib.Encoding{ // .ADD_IMM { .ADD_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, @@ -2428,6 +2428,21 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SVE_ASRR_PRED + { .SVE_ASRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, + { .SVE_ASRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, + { .SVE_ASRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, + { .SVE_ASRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_LSLR_PRED + { .SVE_LSLR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSLR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_LSRR_PRED + { .SVE_LSRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .SVE_LSRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, // .SVE_ABS_PRED { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, @@ -2485,6 +2500,10 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SVE_FSUBR_PRED + { .SVE_FSUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, + { .SVE_FSUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, + { .SVE_FSUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, // .SVE_FMUL_PRED { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, @@ -2493,6 +2512,10 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SVE_FDIVR_PRED + { .SVE_FDIVR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, + { .SVE_FDIVR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, + { .SVE_FDIVR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, // .SVE_FMAX_PRED { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, @@ -2521,6 +2544,38 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SVE_FRECPX_Z + { .SVE_FRECPX_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRECPX_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRECPX_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTN + { .SVE_FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTP + { .SVE_FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTM + { .SVE_FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTZ + { .SVE_FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTA + { .SVE_FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTX + { .SVE_FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .SVE_FRINTI + { .SVE_FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .SVE_FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, // .SVE_FMLA { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, @@ -2561,6 +2616,12 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, // .SVE_EORS_P { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .SVE_NANDS_P + { .SVE_NANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, + // .SVE_NORS_P + { .SVE_NORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, + // .SVE_ORNS_P + { .SVE_ORNS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, // .SVE_PTRUE { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, // .SVE_PTRUES @@ -2571,6 +2632,18 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {} }, // .SVE_PNEXT { .SVE_PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {} }, + // .SVE_BRKA + { .SVE_BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, + // .SVE_BRKB + { .SVE_BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, + // .SVE_BRKAS + { .SVE_BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, + // .SVE_BRKBS + { .SVE_BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, + // .SVE_BRKPA + { .SVE_BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, + // .SVE_BRKPB + { .SVE_BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, // .SVE_CMPEQ { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, @@ -2591,6 +2664,16 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .SVE_CMPLE + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .SVE_CMPLT + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, // .SVE_CMPHI { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, @@ -2601,11 +2684,54 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .SVE_CMPLO + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .SVE_CMPLS + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .SVE_FCMEQ + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, + // .SVE_FCMNE + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, + // .SVE_FCMGE + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, + // .SVE_FCMGT + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, + // .SVE_FCMLE + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, + // .SVE_FCMLT + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, + { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + // .SVE_FCMUO + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, + { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, // .SVE_DUP_Z { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, + // .SVE_INSR + { .SVE_INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .SVE_INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, // .SVE_REV_Z { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, @@ -2660,6 +2786,9 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_TRN1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, // .SVE_TRN2_P { .SVE_TRN2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, + // .SVE_COMPACT + { .SVE_COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, + { .SVE_COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, // .SVE_LD1B { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, // .SVE_LD1H @@ -2748,6 +2877,10 @@ ENCODE_FORMS := [2275]lib.Encoding{ { .SVE_AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {} }, // .SVE_AESIMC { .SVE_AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {} }, + // .SVE_BCAX_Z + { .SVE_BCAX_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, + // .SVE_EOR3_Z + { .SVE_EOR3_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, // .SVE_MATCH { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, @@ -4008,437 +4141,437 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .SVE_ASR_PRED = { 1745, 4}, .SVE_LSL_PRED = { 1749, 4}, .SVE_LSR_PRED = { 1753, 4}, - .SVE_ASRR_PRED = { 1757, 0}, - .SVE_LSLR_PRED = { 1757, 0}, - .SVE_LSRR_PRED = { 1757, 0}, - .SVE_ABS_PRED = { 1757, 4}, - .SVE_NEG_PRED = { 1761, 4}, - .SVE_CLS_PRED = { 1765, 4}, - .SVE_CLZ_PRED = { 1769, 4}, - .SVE_CNT_PRED = { 1773, 4}, - .SVE_MOV_PRED = { 1777, 0}, - .SVE_FADD_Z = { 1777, 3}, - .SVE_FSUB_Z = { 1780, 3}, - .SVE_FMUL_Z = { 1783, 3}, - .SVE_FRECPS = { 1786, 3}, - .SVE_FRSQRTS = { 1789, 3}, - .SVE_FTSMUL = { 1792, 3}, - .SVE_FADD_PRED = { 1795, 3}, - .SVE_FSUB_PRED = { 1798, 3}, - .SVE_FSUBR_PRED = { 1801, 0}, - .SVE_FMUL_PRED = { 1801, 3}, - .SVE_FDIV_PRED = { 1804, 3}, - .SVE_FDIVR_PRED = { 1807, 0}, - .SVE_FMAX_PRED = { 1807, 3}, - .SVE_FMIN_PRED = { 1810, 3}, - .SVE_FMAXNM_PRED = { 1813, 3}, - .SVE_FMINNM_PRED = { 1816, 3}, - .SVE_FABS_Z = { 1819, 3}, - .SVE_FNEG_Z = { 1822, 3}, - .SVE_FSQRT_Z = { 1825, 3}, - .SVE_FRECPX_Z = { 1828, 0}, - .SVE_FRINTN = { 1828, 0}, - .SVE_FRINTP = { 1828, 0}, - .SVE_FRINTM = { 1828, 0}, - .SVE_FRINTZ = { 1828, 0}, - .SVE_FRINTA = { 1828, 0}, - .SVE_FRINTX = { 1828, 0}, - .SVE_FRINTI = { 1828, 0}, - .SVE_FMLA = { 1828, 3}, - .SVE_FMLS = { 1831, 3}, - .SVE_FNMLA = { 1834, 3}, - .SVE_FNMLS = { 1837, 3}, - .SVE_AND_P = { 1840, 1}, - .SVE_BIC_P = { 1841, 1}, - .SVE_ORR_P = { 1842, 1}, - .SVE_EOR_P = { 1843, 1}, - .SVE_NAND_P = { 1844, 1}, - .SVE_NOR_P = { 1845, 1}, - .SVE_ORN_P = { 1846, 1}, - .SVE_SEL_P = { 1847, 1}, - .SVE_ANDS_P = { 1848, 1}, - .SVE_BICS_P = { 1849, 1}, - .SVE_ORRS_P = { 1850, 1}, - .SVE_EORS_P = { 1851, 1}, - .SVE_NANDS_P = { 1852, 0}, - .SVE_NORS_P = { 1852, 0}, - .SVE_ORNS_P = { 1852, 0}, - .SVE_NOT_P = { 1852, 0}, - .SVE_MOV_P = { 1852, 0}, - .SVE_MOVS_P = { 1852, 0}, - .SVE_PTRUE = { 1852, 1}, - .SVE_PTRUES = { 1853, 1}, - .SVE_PFALSE = { 1854, 1}, - .SVE_PFIRST = { 1855, 1}, - .SVE_PNEXT = { 1856, 1}, - .SVE_BRKA = { 1857, 0}, - .SVE_BRKB = { 1857, 0}, - .SVE_BRKAS = { 1857, 0}, - .SVE_BRKBS = { 1857, 0}, - .SVE_BRKPA = { 1857, 0}, - .SVE_BRKPB = { 1857, 0}, - .SVE_BRKN = { 1857, 0}, - .SVE_RDFFR = { 1857, 0}, - .SVE_WRFFR = { 1857, 0}, - .SVE_SETFFR = { 1857, 0}, - .SVE_CMPEQ = { 1857, 4}, - .SVE_CMPNE = { 1861, 4}, - .SVE_CMPGE = { 1865, 4}, - .SVE_CMPGT = { 1869, 4}, - .SVE_CMPLE = { 1873, 0}, - .SVE_CMPLT = { 1873, 0}, - .SVE_CMPHI = { 1873, 4}, - .SVE_CMPHS = { 1877, 4}, - .SVE_CMPLO = { 1881, 0}, - .SVE_CMPLS = { 1881, 0}, - .SVE_FCMEQ = { 1881, 0}, - .SVE_FCMNE = { 1881, 0}, - .SVE_FCMGE = { 1881, 0}, - .SVE_FCMGT = { 1881, 0}, - .SVE_FCMLE = { 1881, 0}, - .SVE_FCMLT = { 1881, 0}, - .SVE_FCMUO = { 1881, 0}, - .SVE_DUP_Z = { 1881, 4}, - .SVE_INSR = { 1885, 0}, - .SVE_REV_Z = { 1885, 4}, - .SVE_REV_P = { 1889, 1}, - .SVE_TBL = { 1890, 4}, - .SVE_ZIP1_Z = { 1894, 4}, - .SVE_ZIP2_Z = { 1898, 4}, - .SVE_UZP1_Z = { 1902, 4}, - .SVE_UZP2_Z = { 1906, 4}, - .SVE_TRN1_Z = { 1910, 4}, - .SVE_TRN2_Z = { 1914, 4}, - .SVE_ZIP1_P = { 1918, 1}, - .SVE_ZIP2_P = { 1919, 1}, - .SVE_UZP1_P = { 1920, 1}, - .SVE_UZP2_P = { 1921, 1}, - .SVE_TRN1_P = { 1922, 1}, - .SVE_TRN2_P = { 1923, 1}, - .SVE_CPY_Z = { 1924, 0}, - .SVE_COMPACT = { 1924, 0}, - .SVE_EXT_Z = { 1924, 0}, - .SVE_LD1B = { 1924, 1}, - .SVE_LD1H = { 1925, 1}, - .SVE_LD1W = { 1926, 1}, - .SVE_LD1D = { 1927, 1}, - .SVE_LD1SB = { 1928, 1}, - .SVE_LD1SH = { 1929, 1}, - .SVE_LD1SW = { 1930, 1}, - .SVE_ST1B = { 1931, 1}, - .SVE_ST1H = { 1932, 1}, - .SVE_ST1W = { 1933, 1}, - .SVE_ST1D = { 1934, 1}, - .SVE_LDR_Z = { 1935, 1}, - .SVE_STR_Z = { 1936, 1}, - .SVE_LDR_P = { 1937, 1}, - .SVE_STR_P = { 1938, 1}, - .SVE_LDFF1B = { 1939, 1}, - .SVE_LDFF1H = { 1940, 1}, - .SVE_LDFF1W = { 1941, 1}, - .SVE_LDFF1D = { 1942, 1}, - .SVE_WHILEGE = { 1943, 1}, - .SVE_WHILEGT = { 1944, 1}, - .SVE_WHILELE = { 1945, 1}, - .SVE_WHILELT = { 1946, 1}, - .SVE_WHILEHI = { 1947, 1}, - .SVE_WHILEHS = { 1948, 1}, - .SVE_WHILELO = { 1949, 1}, - .SVE_WHILELS = { 1950, 1}, - .SVE_SQRDMLAH = { 1951, 4}, - .SVE_SQRDMLSH = { 1955, 4}, - .SVE_ADCLB = { 1959, 2}, - .SVE_ADCLT = { 1961, 2}, - .SVE_SBCLB = { 1963, 2}, - .SVE_SBCLT = { 1965, 2}, - .SVE_TBL2 = { 1967, 1}, - .SVE_TBX = { 1968, 1}, - .SVE_AESE = { 1969, 1}, - .SVE_AESD = { 1970, 1}, - .SVE_AESMC = { 1971, 1}, - .SVE_AESIMC = { 1972, 1}, - .SVE_BCAX_Z = { 1973, 0}, - .SVE_XAR_Z = { 1973, 0}, - .SVE_EOR3_Z = { 1973, 0}, - .SVE_MATCH = { 1973, 2}, - .SVE_NMATCH = { 1975, 2}, - .SVE_HISTCNT = { 1977, 2}, - .SVE_HISTSEG = { 1979, 1}, - .SME_SMSTART = { 1980, 1}, - .SME_SMSTOP = { 1981, 1}, - .SME_RDSVL = { 1982, 1}, - .SME_ADDHA = { 1983, 0}, - .SME_ADDVA = { 1983, 0}, - .SME_ZERO = { 1983, 1}, - .SME_FMOPA = { 1984, 1}, - .SME_FMOPS = { 1985, 1}, - .SME_BFMOPA = { 1986, 1}, - .SME_BFMOPS = { 1987, 1}, - .SME_SMOPA = { 1988, 2}, - .SME_SMOPS = { 1990, 2}, - .SME_UMOPA = { 1992, 2}, - .SME_UMOPS = { 1994, 2}, - .SME_USMOPA = { 1996, 1}, - .SME_SUMOPA = { 1997, 1}, - .SME_MOVA_TO_Z = { 1998, 0}, - .SME_MOVA_TO_ZA = { 1998, 0}, - .SME_LD1B_ZA = { 1998, 0}, - .SME_LD1H_ZA = { 1998, 0}, - .SME_LD1W_ZA = { 1998, 0}, - .SME_LD1D_ZA = { 1998, 0}, - .SME_LD1Q_ZA = { 1998, 0}, - .SME_ST1B_ZA = { 1998, 0}, - .SME_ST1H_ZA = { 1998, 0}, - .SME_ST1W_ZA = { 1998, 0}, - .SME_ST1D_ZA = { 1998, 0}, - .SME_ST1Q_ZA = { 1998, 0}, - .SME_LDR_ZA = { 1998, 1}, - .SME_STR_ZA = { 1999, 1}, - .SVE_FMLA_IDX_H = { 2000, 1}, - .SVE_FMLA_IDX_S = { 2001, 1}, - .SVE_FMLA_IDX_D = { 2002, 1}, - .SVE_FMLS_IDX_H = { 2003, 1}, - .SVE_FMLS_IDX_S = { 2004, 1}, - .SVE_FMLS_IDX_D = { 2005, 1}, - .SVE_LD1B_GATHER_S = { 2006, 1}, - .SVE_LD1B_GATHER_D = { 2007, 1}, - .SVE_LD1H_GATHER_S = { 2008, 1}, - .SVE_LD1H_GATHER_D = { 2009, 1}, - .SVE_LD1W_GATHER_S = { 2010, 1}, - .SVE_LD1W_GATHER_D = { 2011, 1}, - .SVE_LD1D_GATHER_D = { 2012, 1}, - .SVE_LD1SB_GATHER_S = { 2013, 1}, - .SVE_LD1SB_GATHER_D = { 2014, 1}, - .SVE_LD1SH_GATHER_S = { 2015, 1}, - .SVE_LD1SH_GATHER_D = { 2016, 1}, - .SVE_LD1SW_GATHER_D = { 2017, 1}, - .SVE_ST1B_SCATTER_S = { 2018, 1}, - .SVE_ST1B_SCATTER_D = { 2019, 1}, - .SVE_ST1H_SCATTER_S = { 2020, 1}, - .SVE_ST1H_SCATTER_D = { 2021, 1}, - .SVE_ST1W_SCATTER_S = { 2022, 1}, - .SVE_ST1W_SCATTER_D = { 2023, 1}, - .SVE_ST1D_SCATTER_D = { 2024, 1}, - .SME_LD1B_TILE = { 2025, 1}, - .SME_LD1H_TILE = { 2026, 1}, - .SME_LD1W_TILE = { 2027, 1}, - .SME_LD1D_TILE = { 2028, 1}, - .SME_LD1Q_TILE = { 2029, 1}, - .SME_ST1B_TILE = { 2030, 1}, - .SME_ST1H_TILE = { 2031, 1}, - .SME_ST1W_TILE = { 2032, 1}, - .SME_ST1D_TILE = { 2033, 1}, - .SME_ST1Q_TILE = { 2034, 1}, - .SME_MOVA_Z_FROM_TILE = { 2035, 1}, - .SME_MOVA_TILE_FROM_Z = { 2036, 1}, - .FCMLA_4H = { 2037, 1}, - .FCMLA_8H = { 2038, 1}, - .FCMLA_4S = { 2039, 1}, - .FCMLA_2D = { 2040, 1}, - .FCADD_4H = { 2041, 1}, - .FCADD_8H = { 2042, 1}, - .FCADD_4S = { 2043, 1}, - .FCADD_2D = { 2044, 1}, - .SVE_PRFB = { 2045, 1}, - .SVE_PRFH = { 2046, 1}, - .SVE_PRFW = { 2047, 1}, - .SVE_PRFD = { 2048, 1}, - .SVE_LDNT1B = { 2049, 1}, - .SVE_LDNT1H = { 2050, 1}, - .SVE_LDNT1W = { 2051, 1}, - .SVE_LDNT1D = { 2052, 1}, - .SVE_STNT1B = { 2053, 1}, - .SVE_STNT1H = { 2054, 1}, - .SVE_STNT1W = { 2055, 1}, - .SVE_STNT1D = { 2056, 1}, - .SVE_EXT = { 2057, 1}, - .SVE_SPLICE = { 2058, 1}, - .SVE_INDEX_II = { 2059, 1}, - .SVE_INDEX_IR = { 2060, 1}, - .SVE_INDEX_RI = { 2061, 1}, - .SVE_INDEX_RR = { 2062, 1}, - .SVE_BSL = { 2063, 1}, - .SVE_BSL1N = { 2064, 1}, - .SVE_BSL2N = { 2065, 1}, - .SVE_NBSL = { 2066, 1}, - .SVE_PMUL_VEC = { 2067, 1}, - .SVE_PMULLB = { 2068, 1}, - .SVE_PMULLT = { 2069, 1}, - .SVE_BFCVT = { 2070, 1}, - .SVE_BFCVTNT = { 2071, 1}, - .LDRAA = { 2072, 1}, - .LDRAB = { 2073, 1}, - .LDRAA_PRE = { 2074, 1}, - .LDRAB_PRE = { 2075, 1}, - .TSTART = { 2076, 1}, - .TCOMMIT = { 2077, 1}, - .TCANCEL = { 2078, 1}, - .TTEST = { 2079, 1}, - .WFET = { 2080, 1}, - .WFIT = { 2081, 1}, - .BC_COND = { 2082, 1}, - .UXTB = { 2083, 1}, - .UXTH = { 2084, 1}, - .UXTW = { 2085, 1}, - .SXTB = { 2086, 1}, - .SXTH = { 2087, 1}, - .SXTW = { 2088, 1}, - .ADC = { 2089, 2}, - .ADCS = { 2091, 2}, - .SBC = { 2093, 2}, - .SBCS = { 2095, 2}, - .NGC = { 2097, 2}, - .NGCS = { 2099, 2}, - .LDAPUR = { 2101, 2}, - .STLUR = { 2103, 2}, - .LDAPURB = { 2105, 1}, - .STLURB = { 2106, 1}, - .LDAPURH = { 2107, 1}, - .STLURH = { 2108, 1}, - .LDAPURSB = { 2109, 2}, - .LDAPURSH = { 2111, 2}, - .LDAPURSW = { 2113, 1}, - .SVE_BFADD = { 2114, 1}, - .SVE_BFSUB = { 2115, 1}, - .SVE_BFMUL = { 2116, 1}, - .SVE_BFMLA = { 2117, 1}, - .SVE_BFMLS = { 2118, 1}, - .SB = { 2119, 1}, - .CSDB = { 2120, 1}, - .DGH = { 2121, 1}, - .PSB_CSYNC = { 2122, 1}, - .TSB_CSYNC = { 2123, 1}, - .BTI_J = { 2124, 1}, - .BTI_C = { 2125, 1}, - .BTI_JC = { 2126, 1}, - .MOV_V_ALIAS = { 2127, 2}, - .NOT_V_ALIAS = { 2129, 2}, - .LSL_IMM = { 2131, 2}, - .LSR_IMM = { 2133, 2}, - .ASR_IMM = { 2135, 2}, - .ROR_IMM = { 2137, 2}, - .SVE_BFADD_UNPRED = { 2139, 1}, - .SVE_BFSUB_UNPRED = { 2140, 1}, - .SVE_BFMUL_UNPRED = { 2141, 1}, - .SVE_BFCLAMP = { 2142, 1}, - .SVE_BFMAXNM = { 2143, 1}, - .SVE_BFMINNM = { 2144, 1}, - .SME2_LUTI2_B = { 2145, 1}, - .SME2_LUTI4_B = { 2146, 1}, - .SME2_LD1B_X2 = { 2147, 1}, - .SME2_LD1H_X2 = { 2148, 1}, - .SME2_LD1W_X2 = { 2149, 1}, - .SME2_LD1D_X2 = { 2150, 1}, - .SME2_LD1B_X4 = { 2151, 1}, - .SME2_LD1H_X4 = { 2152, 1}, - .SME2_LD1W_X4 = { 2153, 1}, - .SME2_LD1D_X4 = { 2154, 1}, - .SME2_ST1B_X2 = { 2155, 1}, - .SME2_ST1H_X2 = { 2156, 1}, - .SME2_ST1W_X2 = { 2157, 1}, - .SME2_ST1D_X2 = { 2158, 1}, - .SME2_ST1B_X4 = { 2159, 1}, - .SME2_ST1H_X4 = { 2160, 1}, - .SME2_ST1W_X4 = { 2161, 1}, - .SME2_ST1D_X4 = { 2162, 1}, - .SME2_ZIP_3 = { 2163, 1}, - .SME2_ZIP_4 = { 2164, 1}, - .SME2_UZP_3 = { 2165, 1}, - .SME2_UZP_4 = { 2166, 1}, - .TLBI_RPALOS = { 2167, 1}, - .TLBI_RPAOS = { 2168, 1}, - .AT_S1E1A = { 2169, 1}, - .DC_CIPAPA = { 2170, 1}, - .DC_CIGDPAPA = { 2171, 1}, - .TLBI_PAALL = { 2172, 1}, - .TLBI_PAALLOS = { 2173, 1}, - .AMX_LDX = { 2174, 1}, - .AMX_LDY = { 2175, 1}, - .AMX_STX = { 2176, 1}, - .AMX_STY = { 2177, 1}, - .AMX_LDZ = { 2178, 1}, - .AMX_STZ = { 2179, 1}, - .AMX_LDZI = { 2180, 1}, - .AMX_STZI = { 2181, 1}, - .AMX_EXTRX = { 2182, 1}, - .AMX_EXTRY = { 2183, 1}, - .AMX_FMA64 = { 2184, 1}, - .AMX_FMS64 = { 2185, 1}, - .AMX_FMA32 = { 2186, 1}, - .AMX_FMS32 = { 2187, 1}, - .AMX_MAC16 = { 2188, 1}, - .AMX_FMA16 = { 2189, 1}, - .AMX_FMS16 = { 2190, 1}, - .AMX_SET = { 2191, 1}, - .AMX_CLR = { 2192, 1}, - .AMX_VECINT = { 2193, 1}, - .AMX_VECFP = { 2194, 1}, - .AMX_MATINT = { 2195, 1}, - .AMX_MATFP = { 2196, 1}, - .AMX_GENLUT = { 2197, 1}, - .CPYP = { 2198, 1}, - .CPYM = { 2199, 1}, - .CPYE = { 2200, 1}, - .CPYFP = { 2201, 1}, - .CPYFM = { 2202, 1}, - .CPYFE = { 2203, 1}, - .SETP = { 2204, 1}, - .SETM = { 2205, 1}, - .SETE = { 2206, 1}, - .DC_IVAC = { 2207, 1}, - .DC_ISW = { 2208, 1}, - .DC_CSW = { 2209, 1}, - .DC_CISW = { 2210, 1}, - .DC_ZVA = { 2211, 1}, - .DC_CVAC = { 2212, 1}, - .DC_CVAU = { 2213, 1}, - .DC_CIVAC = { 2214, 1}, - .IC_IALLUIS = { 2215, 1}, - .IC_IALLU = { 2216, 1}, - .IC_IVAU = { 2217, 1}, - .AT_S1E1R = { 2218, 1}, - .AT_S1E1W = { 2219, 1}, - .AT_S1E0R = { 2220, 1}, - .AT_S1E0W = { 2221, 1}, - .AT_S1E2R = { 2222, 1}, - .AT_S1E2W = { 2223, 1}, - .AT_S1E3R = { 2224, 1}, - .AT_S1E3W = { 2225, 1}, - .AT_S12E1R = { 2226, 1}, - .AT_S12E1W = { 2227, 1}, - .AT_S12E0R = { 2228, 1}, - .AT_S12E0W = { 2229, 1}, - .TLBI_VMALLE1 = { 2230, 1}, - .TLBI_VMALLE1IS = { 2231, 1}, - .TLBI_VAE1 = { 2232, 1}, - .TLBI_VAE1IS = { 2233, 1}, - .TLBI_ASIDE1 = { 2234, 1}, - .TLBI_ASIDE1IS = { 2235, 1}, - .TLBI_VAAE1 = { 2236, 1}, - .TLBI_VAAE1IS = { 2237, 1}, - .TLBI_VALE1 = { 2238, 1}, - .TLBI_VALE1IS = { 2239, 1}, - .TLBI_VAALE1 = { 2240, 1}, - .TLBI_VAALE1IS = { 2241, 1}, - .TLBI_ALLE1 = { 2242, 1}, - .TLBI_ALLE1IS = { 2243, 1}, - .TLBI_ALLE2 = { 2244, 1}, - .TLBI_ALLE2IS = { 2245, 1}, - .TLBI_ALLE3 = { 2246, 1}, - .TLBI_ALLE3IS = { 2247, 1}, - .PRFM = { 2248, 1}, - .PRFUM = { 2249, 1}, - .PRFM_LIT = { 2250, 1}, - .MOV_REG = { 2251, 2}, - .MOV_BITMASK = { 2253, 2}, - .MVN = { 2255, 2}, - .NEG_SR = { 2257, 2}, - .NEGS = { 2259, 2}, - .CMP_SR = { 2261, 2}, - .CMP_ER = { 2263, 2}, - .CMP_IMM = { 2265, 2}, - .CMN_SR = { 2267, 2}, - .CMN_ER = { 2269, 2}, - .CMN_IMM = { 2271, 2}, - .TST_SR = { 2273, 2}, + .SVE_ASRR_PRED = { 1757, 4}, + .SVE_LSLR_PRED = { 1761, 4}, + .SVE_LSRR_PRED = { 1765, 4}, + .SVE_ABS_PRED = { 1769, 4}, + .SVE_NEG_PRED = { 1773, 4}, + .SVE_CLS_PRED = { 1777, 4}, + .SVE_CLZ_PRED = { 1781, 4}, + .SVE_CNT_PRED = { 1785, 4}, + .SVE_MOV_PRED = { 1789, 0}, + .SVE_FADD_Z = { 1789, 3}, + .SVE_FSUB_Z = { 1792, 3}, + .SVE_FMUL_Z = { 1795, 3}, + .SVE_FRECPS = { 1798, 3}, + .SVE_FRSQRTS = { 1801, 3}, + .SVE_FTSMUL = { 1804, 3}, + .SVE_FADD_PRED = { 1807, 3}, + .SVE_FSUB_PRED = { 1810, 3}, + .SVE_FSUBR_PRED = { 1813, 3}, + .SVE_FMUL_PRED = { 1816, 3}, + .SVE_FDIV_PRED = { 1819, 3}, + .SVE_FDIVR_PRED = { 1822, 3}, + .SVE_FMAX_PRED = { 1825, 3}, + .SVE_FMIN_PRED = { 1828, 3}, + .SVE_FMAXNM_PRED = { 1831, 3}, + .SVE_FMINNM_PRED = { 1834, 3}, + .SVE_FABS_Z = { 1837, 3}, + .SVE_FNEG_Z = { 1840, 3}, + .SVE_FSQRT_Z = { 1843, 3}, + .SVE_FRECPX_Z = { 1846, 3}, + .SVE_FRINTN = { 1849, 3}, + .SVE_FRINTP = { 1852, 3}, + .SVE_FRINTM = { 1855, 3}, + .SVE_FRINTZ = { 1858, 3}, + .SVE_FRINTA = { 1861, 3}, + .SVE_FRINTX = { 1864, 3}, + .SVE_FRINTI = { 1867, 3}, + .SVE_FMLA = { 1870, 3}, + .SVE_FMLS = { 1873, 3}, + .SVE_FNMLA = { 1876, 3}, + .SVE_FNMLS = { 1879, 3}, + .SVE_AND_P = { 1882, 1}, + .SVE_BIC_P = { 1883, 1}, + .SVE_ORR_P = { 1884, 1}, + .SVE_EOR_P = { 1885, 1}, + .SVE_NAND_P = { 1886, 1}, + .SVE_NOR_P = { 1887, 1}, + .SVE_ORN_P = { 1888, 1}, + .SVE_SEL_P = { 1889, 1}, + .SVE_ANDS_P = { 1890, 1}, + .SVE_BICS_P = { 1891, 1}, + .SVE_ORRS_P = { 1892, 1}, + .SVE_EORS_P = { 1893, 1}, + .SVE_NANDS_P = { 1894, 1}, + .SVE_NORS_P = { 1895, 1}, + .SVE_ORNS_P = { 1896, 1}, + .SVE_NOT_P = { 1897, 0}, + .SVE_MOV_P = { 1897, 0}, + .SVE_MOVS_P = { 1897, 0}, + .SVE_PTRUE = { 1897, 1}, + .SVE_PTRUES = { 1898, 1}, + .SVE_PFALSE = { 1899, 1}, + .SVE_PFIRST = { 1900, 1}, + .SVE_PNEXT = { 1901, 1}, + .SVE_BRKA = { 1902, 1}, + .SVE_BRKB = { 1903, 1}, + .SVE_BRKAS = { 1904, 1}, + .SVE_BRKBS = { 1905, 1}, + .SVE_BRKPA = { 1906, 1}, + .SVE_BRKPB = { 1907, 1}, + .SVE_BRKN = { 1908, 0}, + .SVE_RDFFR = { 1908, 0}, + .SVE_WRFFR = { 1908, 0}, + .SVE_SETFFR = { 1908, 0}, + .SVE_CMPEQ = { 1908, 4}, + .SVE_CMPNE = { 1912, 4}, + .SVE_CMPGE = { 1916, 4}, + .SVE_CMPGT = { 1920, 4}, + .SVE_CMPLE = { 1924, 4}, + .SVE_CMPLT = { 1928, 4}, + .SVE_CMPHI = { 1932, 4}, + .SVE_CMPHS = { 1936, 4}, + .SVE_CMPLO = { 1940, 4}, + .SVE_CMPLS = { 1944, 4}, + .SVE_FCMEQ = { 1948, 3}, + .SVE_FCMNE = { 1951, 3}, + .SVE_FCMGE = { 1954, 3}, + .SVE_FCMGT = { 1957, 3}, + .SVE_FCMLE = { 1960, 3}, + .SVE_FCMLT = { 1963, 3}, + .SVE_FCMUO = { 1966, 3}, + .SVE_DUP_Z = { 1969, 4}, + .SVE_INSR = { 1973, 4}, + .SVE_REV_Z = { 1977, 4}, + .SVE_REV_P = { 1981, 1}, + .SVE_TBL = { 1982, 4}, + .SVE_ZIP1_Z = { 1986, 4}, + .SVE_ZIP2_Z = { 1990, 4}, + .SVE_UZP1_Z = { 1994, 4}, + .SVE_UZP2_Z = { 1998, 4}, + .SVE_TRN1_Z = { 2002, 4}, + .SVE_TRN2_Z = { 2006, 4}, + .SVE_ZIP1_P = { 2010, 1}, + .SVE_ZIP2_P = { 2011, 1}, + .SVE_UZP1_P = { 2012, 1}, + .SVE_UZP2_P = { 2013, 1}, + .SVE_TRN1_P = { 2014, 1}, + .SVE_TRN2_P = { 2015, 1}, + .SVE_CPY_Z = { 2016, 0}, + .SVE_COMPACT = { 2016, 2}, + .SVE_EXT_Z = { 2018, 0}, + .SVE_LD1B = { 2018, 1}, + .SVE_LD1H = { 2019, 1}, + .SVE_LD1W = { 2020, 1}, + .SVE_LD1D = { 2021, 1}, + .SVE_LD1SB = { 2022, 1}, + .SVE_LD1SH = { 2023, 1}, + .SVE_LD1SW = { 2024, 1}, + .SVE_ST1B = { 2025, 1}, + .SVE_ST1H = { 2026, 1}, + .SVE_ST1W = { 2027, 1}, + .SVE_ST1D = { 2028, 1}, + .SVE_LDR_Z = { 2029, 1}, + .SVE_STR_Z = { 2030, 1}, + .SVE_LDR_P = { 2031, 1}, + .SVE_STR_P = { 2032, 1}, + .SVE_LDFF1B = { 2033, 1}, + .SVE_LDFF1H = { 2034, 1}, + .SVE_LDFF1W = { 2035, 1}, + .SVE_LDFF1D = { 2036, 1}, + .SVE_WHILEGE = { 2037, 1}, + .SVE_WHILEGT = { 2038, 1}, + .SVE_WHILELE = { 2039, 1}, + .SVE_WHILELT = { 2040, 1}, + .SVE_WHILEHI = { 2041, 1}, + .SVE_WHILEHS = { 2042, 1}, + .SVE_WHILELO = { 2043, 1}, + .SVE_WHILELS = { 2044, 1}, + .SVE_SQRDMLAH = { 2045, 4}, + .SVE_SQRDMLSH = { 2049, 4}, + .SVE_ADCLB = { 2053, 2}, + .SVE_ADCLT = { 2055, 2}, + .SVE_SBCLB = { 2057, 2}, + .SVE_SBCLT = { 2059, 2}, + .SVE_TBL2 = { 2061, 1}, + .SVE_TBX = { 2062, 1}, + .SVE_AESE = { 2063, 1}, + .SVE_AESD = { 2064, 1}, + .SVE_AESMC = { 2065, 1}, + .SVE_AESIMC = { 2066, 1}, + .SVE_BCAX_Z = { 2067, 1}, + .SVE_XAR_Z = { 2068, 0}, + .SVE_EOR3_Z = { 2068, 1}, + .SVE_MATCH = { 2069, 2}, + .SVE_NMATCH = { 2071, 2}, + .SVE_HISTCNT = { 2073, 2}, + .SVE_HISTSEG = { 2075, 1}, + .SME_SMSTART = { 2076, 1}, + .SME_SMSTOP = { 2077, 1}, + .SME_RDSVL = { 2078, 1}, + .SME_ADDHA = { 2079, 0}, + .SME_ADDVA = { 2079, 0}, + .SME_ZERO = { 2079, 1}, + .SME_FMOPA = { 2080, 1}, + .SME_FMOPS = { 2081, 1}, + .SME_BFMOPA = { 2082, 1}, + .SME_BFMOPS = { 2083, 1}, + .SME_SMOPA = { 2084, 2}, + .SME_SMOPS = { 2086, 2}, + .SME_UMOPA = { 2088, 2}, + .SME_UMOPS = { 2090, 2}, + .SME_USMOPA = { 2092, 1}, + .SME_SUMOPA = { 2093, 1}, + .SME_MOVA_TO_Z = { 2094, 0}, + .SME_MOVA_TO_ZA = { 2094, 0}, + .SME_LD1B_ZA = { 2094, 0}, + .SME_LD1H_ZA = { 2094, 0}, + .SME_LD1W_ZA = { 2094, 0}, + .SME_LD1D_ZA = { 2094, 0}, + .SME_LD1Q_ZA = { 2094, 0}, + .SME_ST1B_ZA = { 2094, 0}, + .SME_ST1H_ZA = { 2094, 0}, + .SME_ST1W_ZA = { 2094, 0}, + .SME_ST1D_ZA = { 2094, 0}, + .SME_ST1Q_ZA = { 2094, 0}, + .SME_LDR_ZA = { 2094, 1}, + .SME_STR_ZA = { 2095, 1}, + .SVE_FMLA_IDX_H = { 2096, 1}, + .SVE_FMLA_IDX_S = { 2097, 1}, + .SVE_FMLA_IDX_D = { 2098, 1}, + .SVE_FMLS_IDX_H = { 2099, 1}, + .SVE_FMLS_IDX_S = { 2100, 1}, + .SVE_FMLS_IDX_D = { 2101, 1}, + .SVE_LD1B_GATHER_S = { 2102, 1}, + .SVE_LD1B_GATHER_D = { 2103, 1}, + .SVE_LD1H_GATHER_S = { 2104, 1}, + .SVE_LD1H_GATHER_D = { 2105, 1}, + .SVE_LD1W_GATHER_S = { 2106, 1}, + .SVE_LD1W_GATHER_D = { 2107, 1}, + .SVE_LD1D_GATHER_D = { 2108, 1}, + .SVE_LD1SB_GATHER_S = { 2109, 1}, + .SVE_LD1SB_GATHER_D = { 2110, 1}, + .SVE_LD1SH_GATHER_S = { 2111, 1}, + .SVE_LD1SH_GATHER_D = { 2112, 1}, + .SVE_LD1SW_GATHER_D = { 2113, 1}, + .SVE_ST1B_SCATTER_S = { 2114, 1}, + .SVE_ST1B_SCATTER_D = { 2115, 1}, + .SVE_ST1H_SCATTER_S = { 2116, 1}, + .SVE_ST1H_SCATTER_D = { 2117, 1}, + .SVE_ST1W_SCATTER_S = { 2118, 1}, + .SVE_ST1W_SCATTER_D = { 2119, 1}, + .SVE_ST1D_SCATTER_D = { 2120, 1}, + .SME_LD1B_TILE = { 2121, 1}, + .SME_LD1H_TILE = { 2122, 1}, + .SME_LD1W_TILE = { 2123, 1}, + .SME_LD1D_TILE = { 2124, 1}, + .SME_LD1Q_TILE = { 2125, 1}, + .SME_ST1B_TILE = { 2126, 1}, + .SME_ST1H_TILE = { 2127, 1}, + .SME_ST1W_TILE = { 2128, 1}, + .SME_ST1D_TILE = { 2129, 1}, + .SME_ST1Q_TILE = { 2130, 1}, + .SME_MOVA_Z_FROM_TILE = { 2131, 1}, + .SME_MOVA_TILE_FROM_Z = { 2132, 1}, + .FCMLA_4H = { 2133, 1}, + .FCMLA_8H = { 2134, 1}, + .FCMLA_4S = { 2135, 1}, + .FCMLA_2D = { 2136, 1}, + .FCADD_4H = { 2137, 1}, + .FCADD_8H = { 2138, 1}, + .FCADD_4S = { 2139, 1}, + .FCADD_2D = { 2140, 1}, + .SVE_PRFB = { 2141, 1}, + .SVE_PRFH = { 2142, 1}, + .SVE_PRFW = { 2143, 1}, + .SVE_PRFD = { 2144, 1}, + .SVE_LDNT1B = { 2145, 1}, + .SVE_LDNT1H = { 2146, 1}, + .SVE_LDNT1W = { 2147, 1}, + .SVE_LDNT1D = { 2148, 1}, + .SVE_STNT1B = { 2149, 1}, + .SVE_STNT1H = { 2150, 1}, + .SVE_STNT1W = { 2151, 1}, + .SVE_STNT1D = { 2152, 1}, + .SVE_EXT = { 2153, 1}, + .SVE_SPLICE = { 2154, 1}, + .SVE_INDEX_II = { 2155, 1}, + .SVE_INDEX_IR = { 2156, 1}, + .SVE_INDEX_RI = { 2157, 1}, + .SVE_INDEX_RR = { 2158, 1}, + .SVE_BSL = { 2159, 1}, + .SVE_BSL1N = { 2160, 1}, + .SVE_BSL2N = { 2161, 1}, + .SVE_NBSL = { 2162, 1}, + .SVE_PMUL_VEC = { 2163, 1}, + .SVE_PMULLB = { 2164, 1}, + .SVE_PMULLT = { 2165, 1}, + .SVE_BFCVT = { 2166, 1}, + .SVE_BFCVTNT = { 2167, 1}, + .LDRAA = { 2168, 1}, + .LDRAB = { 2169, 1}, + .LDRAA_PRE = { 2170, 1}, + .LDRAB_PRE = { 2171, 1}, + .TSTART = { 2172, 1}, + .TCOMMIT = { 2173, 1}, + .TCANCEL = { 2174, 1}, + .TTEST = { 2175, 1}, + .WFET = { 2176, 1}, + .WFIT = { 2177, 1}, + .BC_COND = { 2178, 1}, + .UXTB = { 2179, 1}, + .UXTH = { 2180, 1}, + .UXTW = { 2181, 1}, + .SXTB = { 2182, 1}, + .SXTH = { 2183, 1}, + .SXTW = { 2184, 1}, + .ADC = { 2185, 2}, + .ADCS = { 2187, 2}, + .SBC = { 2189, 2}, + .SBCS = { 2191, 2}, + .NGC = { 2193, 2}, + .NGCS = { 2195, 2}, + .LDAPUR = { 2197, 2}, + .STLUR = { 2199, 2}, + .LDAPURB = { 2201, 1}, + .STLURB = { 2202, 1}, + .LDAPURH = { 2203, 1}, + .STLURH = { 2204, 1}, + .LDAPURSB = { 2205, 2}, + .LDAPURSH = { 2207, 2}, + .LDAPURSW = { 2209, 1}, + .SVE_BFADD = { 2210, 1}, + .SVE_BFSUB = { 2211, 1}, + .SVE_BFMUL = { 2212, 1}, + .SVE_BFMLA = { 2213, 1}, + .SVE_BFMLS = { 2214, 1}, + .SB = { 2215, 1}, + .CSDB = { 2216, 1}, + .DGH = { 2217, 1}, + .PSB_CSYNC = { 2218, 1}, + .TSB_CSYNC = { 2219, 1}, + .BTI_J = { 2220, 1}, + .BTI_C = { 2221, 1}, + .BTI_JC = { 2222, 1}, + .MOV_V_ALIAS = { 2223, 2}, + .NOT_V_ALIAS = { 2225, 2}, + .LSL_IMM = { 2227, 2}, + .LSR_IMM = { 2229, 2}, + .ASR_IMM = { 2231, 2}, + .ROR_IMM = { 2233, 2}, + .SVE_BFADD_UNPRED = { 2235, 1}, + .SVE_BFSUB_UNPRED = { 2236, 1}, + .SVE_BFMUL_UNPRED = { 2237, 1}, + .SVE_BFCLAMP = { 2238, 1}, + .SVE_BFMAXNM = { 2239, 1}, + .SVE_BFMINNM = { 2240, 1}, + .SME2_LUTI2_B = { 2241, 1}, + .SME2_LUTI4_B = { 2242, 1}, + .SME2_LD1B_X2 = { 2243, 1}, + .SME2_LD1H_X2 = { 2244, 1}, + .SME2_LD1W_X2 = { 2245, 1}, + .SME2_LD1D_X2 = { 2246, 1}, + .SME2_LD1B_X4 = { 2247, 1}, + .SME2_LD1H_X4 = { 2248, 1}, + .SME2_LD1W_X4 = { 2249, 1}, + .SME2_LD1D_X4 = { 2250, 1}, + .SME2_ST1B_X2 = { 2251, 1}, + .SME2_ST1H_X2 = { 2252, 1}, + .SME2_ST1W_X2 = { 2253, 1}, + .SME2_ST1D_X2 = { 2254, 1}, + .SME2_ST1B_X4 = { 2255, 1}, + .SME2_ST1H_X4 = { 2256, 1}, + .SME2_ST1W_X4 = { 2257, 1}, + .SME2_ST1D_X4 = { 2258, 1}, + .SME2_ZIP_3 = { 2259, 1}, + .SME2_ZIP_4 = { 2260, 1}, + .SME2_UZP_3 = { 2261, 1}, + .SME2_UZP_4 = { 2262, 1}, + .TLBI_RPALOS = { 2263, 1}, + .TLBI_RPAOS = { 2264, 1}, + .AT_S1E1A = { 2265, 1}, + .DC_CIPAPA = { 2266, 1}, + .DC_CIGDPAPA = { 2267, 1}, + .TLBI_PAALL = { 2268, 1}, + .TLBI_PAALLOS = { 2269, 1}, + .AMX_LDX = { 2270, 1}, + .AMX_LDY = { 2271, 1}, + .AMX_STX = { 2272, 1}, + .AMX_STY = { 2273, 1}, + .AMX_LDZ = { 2274, 1}, + .AMX_STZ = { 2275, 1}, + .AMX_LDZI = { 2276, 1}, + .AMX_STZI = { 2277, 1}, + .AMX_EXTRX = { 2278, 1}, + .AMX_EXTRY = { 2279, 1}, + .AMX_FMA64 = { 2280, 1}, + .AMX_FMS64 = { 2281, 1}, + .AMX_FMA32 = { 2282, 1}, + .AMX_FMS32 = { 2283, 1}, + .AMX_MAC16 = { 2284, 1}, + .AMX_FMA16 = { 2285, 1}, + .AMX_FMS16 = { 2286, 1}, + .AMX_SET = { 2287, 1}, + .AMX_CLR = { 2288, 1}, + .AMX_VECINT = { 2289, 1}, + .AMX_VECFP = { 2290, 1}, + .AMX_MATINT = { 2291, 1}, + .AMX_MATFP = { 2292, 1}, + .AMX_GENLUT = { 2293, 1}, + .CPYP = { 2294, 1}, + .CPYM = { 2295, 1}, + .CPYE = { 2296, 1}, + .CPYFP = { 2297, 1}, + .CPYFM = { 2298, 1}, + .CPYFE = { 2299, 1}, + .SETP = { 2300, 1}, + .SETM = { 2301, 1}, + .SETE = { 2302, 1}, + .DC_IVAC = { 2303, 1}, + .DC_ISW = { 2304, 1}, + .DC_CSW = { 2305, 1}, + .DC_CISW = { 2306, 1}, + .DC_ZVA = { 2307, 1}, + .DC_CVAC = { 2308, 1}, + .DC_CVAU = { 2309, 1}, + .DC_CIVAC = { 2310, 1}, + .IC_IALLUIS = { 2311, 1}, + .IC_IALLU = { 2312, 1}, + .IC_IVAU = { 2313, 1}, + .AT_S1E1R = { 2314, 1}, + .AT_S1E1W = { 2315, 1}, + .AT_S1E0R = { 2316, 1}, + .AT_S1E0W = { 2317, 1}, + .AT_S1E2R = { 2318, 1}, + .AT_S1E2W = { 2319, 1}, + .AT_S1E3R = { 2320, 1}, + .AT_S1E3W = { 2321, 1}, + .AT_S12E1R = { 2322, 1}, + .AT_S12E1W = { 2323, 1}, + .AT_S12E0R = { 2324, 1}, + .AT_S12E0W = { 2325, 1}, + .TLBI_VMALLE1 = { 2326, 1}, + .TLBI_VMALLE1IS = { 2327, 1}, + .TLBI_VAE1 = { 2328, 1}, + .TLBI_VAE1IS = { 2329, 1}, + .TLBI_ASIDE1 = { 2330, 1}, + .TLBI_ASIDE1IS = { 2331, 1}, + .TLBI_VAAE1 = { 2332, 1}, + .TLBI_VAAE1IS = { 2333, 1}, + .TLBI_VALE1 = { 2334, 1}, + .TLBI_VALE1IS = { 2335, 1}, + .TLBI_VAALE1 = { 2336, 1}, + .TLBI_VAALE1IS = { 2337, 1}, + .TLBI_ALLE1 = { 2338, 1}, + .TLBI_ALLE1IS = { 2339, 1}, + .TLBI_ALLE2 = { 2340, 1}, + .TLBI_ALLE2IS = { 2341, 1}, + .TLBI_ALLE3 = { 2342, 1}, + .TLBI_ALLE3IS = { 2343, 1}, + .PRFM = { 2344, 1}, + .PRFUM = { 2345, 1}, + .PRFM_LIT = { 2346, 1}, + .MOV_REG = { 2347, 2}, + .MOV_BITMASK = { 2349, 2}, + .MVN = { 2351, 2}, + .NEG_SR = { 2353, 2}, + .NEGS = { 2355, 2}, + .CMP_SR = { 2357, 2}, + .CMP_ER = { 2359, 2}, + .CMP_IMM = { 2361, 2}, + .CMN_SR = { 2363, 2}, + .CMN_ER = { 2365, 2}, + .CMN_IMM = { 2367, 2}, + .TST_SR = { 2369, 2}, } diff --git a/core/rexcode/arm64/tablegen/specgen.lua b/core/rexcode/arm64/tablegen/specgen.lua index ec0ae8706..fad35b91e 100644 --- a/core/rexcode/arm64/tablegen/specgen.lua +++ b/core/rexcode/arm64/tablegen/specgen.lua @@ -538,6 +538,148 @@ do sections[#sections+1] = "\t// NEON modified immediate (MOVI/MVNI).\n" .. table.concat(blk, "\n") end +-- ---- SVE (predicated FP/round/compare, predicate logical/break, SVE2) ------- +-- These iterate element sizes; the predicate-destination forms select size via +-- the Z-register operands. `bits`/`mask` come from llvm-mc: assemble all-zero, +-- then one variant per field set to its max (Z reg 31, 3-bit Pg 7, 4-bit Pd/ +-- Pg/Pn/Pm 15, GPR 31 = wzr/xzr) and mask = ~union of the deltas. +SVE_LLVM = "llvm-mc --assemble --arch=aarch64 --mattr=+sve,+sve2,+sve2-aes,+fullfp16 --show-encoding" +local function sve_word(line) + local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, SVE_LLVM)) + local out = p:read("*a"); p:close() + local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)") + if not b1 then return nil end + return tonumber(b4..b3..b2..b1, 16) +end +do + local blk = {} + local E_HSD = {{"h","Z_REG_H",""},{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}} + local E_BHSD = {{"b","Z_REG_B",""},{"h","Z_REG_H",""},{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}} + local E_SD = {{"s","Z_REG_S",""},{"d","Z_REG_D","is_64=true"}} + local function emit1(mnem, ops, enc, flags, fields, build) + local zero = {}; for i=1,#fields do zero[i]=0 end + local b0 = sve_word(build(zero)); if not b0 then skips[#skips+1]=mnem..":b0"; return nil end + local vs = {} + for i=1,#fields do + local v={}; for j=1,#fields do v[j]=0 end; v[i]=fields[i] + local w=sve_word(build(v)); if not w then skips[#skips+1]=mnem..":v"..i; return nil end; vs[#vs+1]=w + end + n_forms=n_forms+1 + return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .SVE, {%s}},", + mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags) + end + local function block(mnem, rows) + local r={}; for _,x in ipairs(rows) do if x then r[#r+1]=x end end + if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(r,"\n")); n_mnem=n_mnem+1 end + end + local function g(v, x) if v==0 then return x and "x0" or "w0" else return x and "xzr" or "wzr" end end + + -- predicated FP round: Zd.T, Pg/m, Zn.T (H/S/D) + for _, it in ipairs({{"SVE_FRINTN","frintn"},{"SVE_FRINTP","frintp"},{"SVE_FRINTM","frintm"}, + {"SVE_FRINTZ","frintz"},{"SVE_FRINTA","frinta"},{"SVE_FRINTX","frintx"},{"SVE_FRINTI","frinti"},{"SVE_FRECPX_Z","frecpx"}}) do + local rows={} + for _,e in ipairs(E_HSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .NONE}",e[2],e[2]), + "{.VD, .PG, .VN, .NONE}", e[3], {31,7,31}, + function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s", it[2], v[1],t, v[2], v[3],t) end) + end + block(it[1], rows) + end + -- reversed predicated shifts: Zd.T, Pg/m, Zd.T, Zm.T (B/H/S/D) + for _, it in ipairs({{"SVE_ASRR_PRED","asrr"},{"SVE_LSLR_PRED","lslr"},{"SVE_LSRR_PRED","lsrr"}}) do + local rows={} + for _,e in ipairs(E_BHSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .%s}",e[2],e[2],e[2]), + "{.VD, .PG, .VD, .VN}", e[3], {31,7,31}, + function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[1],t, v[3],t) end) + end + block(it[1], rows) + end + -- reversed predicated FP: Zd.T, Pg/m, Zd.T, Zm.T (H/S/D) + for _, it in ipairs({{"SVE_FSUBR_PRED","fsubr"},{"SVE_FDIVR_PRED","fdivr"}}) do + local rows={} + for _,e in ipairs(E_HSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.%s, .P_REG_MERGE, .%s, .%s}",e[2],e[2],e[2]), + "{.VD, .PG, .VD, .VN}", e[3], {31,7,31}, + function(v) return string.format("%s z%d.%s, p%d/m, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[1],t, v[3],t) end) + end + block(it[1], rows) + end + -- FP compare (reg) -> Pd.T: Pd.T, Pg/z, Zn.T, Zm.T (H/S/D) + for _, it in ipairs({{"SVE_FCMEQ","fcmeq"},{"SVE_FCMGE","fcmge"},{"SVE_FCMGT","fcmgt"},{"SVE_FCMNE","fcmne"},{"SVE_FCMUO","fcmuo"}}) do + local rows={} + for _,e in ipairs(E_HSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .%s}",e[2],e[2]), + "{.PD, .PG, .VN, .VM}", e[3], {15,7,31,31}, + function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[3],t, v[4],t) end) + end + block(it[1], rows) + end + -- FP compare vs zero -> Pd.T: Pd.T, Pg/z, Zn.T, #0.0 (H/S/D) + for _, it in ipairs({{"SVE_FCMLE","fcmle"},{"SVE_FCMLT","fcmlt"}}) do + local rows={} + for _,e in ipairs(E_HSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .NONE}",e[2]), + "{.PD, .PG, .VN, .NONE}", e[3], {15,7,31}, + function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, #0.0", it[2], v[1],t, v[2], v[3],t) end) + end + block(it[1], rows) + end + -- integer compare (reg) -> Pd.T: Pd.T, Pg/z, Zn.T, Zm.T (B/H/S/D) + for _, it in ipairs({{"SVE_CMPLE","cmple"},{"SVE_CMPLO","cmplo"},{"SVE_CMPLS","cmpls"},{"SVE_CMPLT","cmplt"}}) do + local rows={} + for _,e in ipairs(E_BHSD) do local t=e[1] + rows[#rows+1]=emit1(it[1], string.format("{.P_REG, .P_REG_ZERO, .%s, .%s}",e[2],e[2]), + "{.PD, .PG, .VM, .VN}", "sets_flags=true"..(e[3]~="" and ", "..e[3] or ""), {15,7,31,31}, + function(v) return string.format("%s p%d.%s, p%d/z, z%d.%s, z%d.%s", it[2], v[1],t, v[2], v[3],t, v[4],t) end) + end + block(it[1], rows) + end + -- predicate logical (3-source) -> Pd.B: Pd.B, Pg/z, Pn.B, Pm.B + for _, it in ipairs({{"SVE_NANDS_P","nands"},{"SVE_NORS_P","nors"},{"SVE_ORNS_P","orns"}}) do + block(it[1], { emit1(it[1], "{.P_REG, .P_REG_ZERO, .P_REG, .P_REG}", "{.PD, .PG4, .PN, .PM}", "sets_flags=true", {15,15,15,15}, + function(v) return string.format("%s p%d.b, p%d/z, p%d.b, p%d.b", it[2], v[1], v[2], v[3], v[4]) end) }) + end + -- predicate break (pair) -> Pd.B: Pd.B, Pg/z, Pn.B, Pm.B + for _, it in ipairs({{"SVE_BRKPA","brkpa"},{"SVE_BRKPB","brkpb"},{"SVE_BRKN","brkn"}}) do + block(it[1], { emit1(it[1], "{.P_REG, .P_REG_ZERO, .P_REG, .P_REG}", "{.PD, .PG4, .PN, .PM}", "", {15,15,15,15}, + function(v) return string.format("%s p%d.b, p%d/z, p%d.b, p%d.b", it[2], v[1], v[2], v[3], v[4]) end) }) + end + -- predicate break (single) -> Pd.B: Pd.B, Pg/m, Pn.B (BRKA/BRKB merge; BRKAS/BRKBS /z+flags) + for _, it in ipairs({{"SVE_BRKA","brka","/m",""},{"SVE_BRKB","brkb","/m",""}, + {"SVE_BRKAS","brkas","/z","sets_flags=true"},{"SVE_BRKBS","brkbs","/z","sets_flags=true"}}) do + local pred = it[3]=="/m" and ".P_REG_MERGE" or ".P_REG_ZERO" + block(it[1], { emit1(it[1], "{.P_REG, "..pred..", .P_REG, .NONE}", "{.PD, .PG4, .PN, .NONE}", it[4], {15,15,15}, + function(v) return string.format("%s p%d.b, p%d%s, p%d.b", it[2], v[1], v[2], it[3], v[3]) end) }) + end + -- SVE2 crypto three-source (.D): Zd.D, Zd.D, Zn.D, Zm.D + for _, it in ipairs({{"SVE_EOR3_Z","eor3"},{"SVE_BCAX_Z","bcax"}}) do + block(it[1], { emit1(it[1], "{.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}", "{.VD, .VD, .VM, .VN}", "is_64=true", {31,31,31}, + function(v) return string.format("%s z%d.d, z%d.d, z%d.d, z%d.d", it[2], v[1], v[1], v[2], v[3]) end) }) + end + -- INSR: Zd.T, Wn/Xn (X for .D) + do + local rows={} + for _,e in ipairs(E_BHSD) do local t=e[1]; local x=(t=="d") + rows[#rows+1]=emit1("SVE_INSR", string.format("{.%s, .%s, .NONE, .NONE}",e[2], x and "X_REG" or "W_REG"), + "{.VD, .VN, .NONE, .NONE}", e[3], {31,31}, + function(v) return string.format("insr z%d.%s, %s", v[1],t, g(v[2],x)) end) + end + block("SVE_INSR", rows) + end + -- COMPACT: Zd.T, Pg, Zn.T (S/D) + do + local rows={} + for _,e in ipairs(E_SD) do local t=e[1] + rows[#rows+1]=emit1("SVE_COMPACT", string.format("{.%s, .P_REG_GOV, .%s, .NONE}",e[2],e[2]), + "{.VD, .PG, .VN, .NONE}", e[3], {31,7,31}, + function(v) return string.format("compact z%d.%s, p%d, z%d.%s", v[1],t, v[2], v[3],t) end) + end + block("SVE_COMPACT", rows) + end + sections[#sections+1] = "\t// SVE predicated / compare / predicate-logical / SVE2.\n" .. table.concat(blk, "\n") +end + -- ---- splice into the SoT --------------------------------------------------- local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() diff --git a/core/rexcode/arm64/tables/arm64.encode_forms.bin b/core/rexcode/arm64/tables/arm64.encode_forms.bin index 1a0ac7d9e..7f83efe85 100644 Binary files a/core/rexcode/arm64/tables/arm64.encode_forms.bin and b/core/rexcode/arm64/tables/arm64.encode_forms.bin differ diff --git a/core/rexcode/arm64/tables/arm64.encode_runs.bin b/core/rexcode/arm64/tables/arm64.encode_runs.bin index 641ecee46..d966af676 100644 Binary files a/core/rexcode/arm64/tables/arm64.encode_runs.bin and b/core/rexcode/arm64/tables/arm64.encode_runs.bin differ diff --git a/core/rexcode/arm64/tables/arm64.entries.bin b/core/rexcode/arm64/tables/arm64.entries.bin index 069afaf57..1cd86eacf 100644 Binary files a/core/rexcode/arm64/tables/arm64.entries.bin and b/core/rexcode/arm64/tables/arm64.entries.bin differ diff --git a/core/rexcode/arm64/tables/arm64.idx_op0.bin b/core/rexcode/arm64/tables/arm64.idx_op0.bin index 4c5ab5b96..18632d0f0 100644 Binary files a/core/rexcode/arm64/tables/arm64.idx_op0.bin and b/core/rexcode/arm64/tables/arm64.idx_op0.bin differ