From cef68b02a26cd3f08ba535351f0007f0d1d3a910 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:33:06 -0400 Subject: [PATCH] rexcode/arm32: register lists, compare-with-zero, and the VCMPE E bit Three unrelated things the A32 sweep turned up, all of them in what an instruction prints rather than what it encodes. VTBL and VTBX read their table from a run of one to four D registers, and the run length is a fixed pattern bit of the form rather than something the operand encodes. They printed a bare `d0`, which is not the syntax -- the table is a list even when it holds one register. The length now rides in the operand encoding, the way the NEON structure-list lengths already do, and the encoder checks it, so `{d0}` and `{d0, d1}` select different forms instead of both landing on whichever sorted first. The NEON compare-with-zero forms and VCMP/VCMPE against zero take a literal `#0` that no field encodes. Modelling it as an implicit operand is enough for it to print; nothing is emitted for it. VCMP left bit 7 out of its mask. That bit is the E, which is the only thing separating VCMP from VCMPE, so VCMP matched both and VCMPE could never be decoded at all. Also: VPUSH and VPOP take no data type, but the printer's fallback guessed one from the register bank whenever the table gave none, and produced `vpop.f64 {d0}`. A leading register list now suppresses it -- the load/store-multiple forms are exactly the ones that lead with a list. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 19 +- core/rexcode/isa/arm32/encoder.odin | 25 ++- core/rexcode/isa/arm32/encoding_types.odin | 7 + core/rexcode/isa/arm32/mnemonic_builders.odin | 12 +- core/rexcode/isa/arm32/printer.odin | 4 + .../isa/arm32/tablegen/encoding_table.odin | 76 +++---- .../tablegen/generated/decode_tables.odin | 208 +++++++++--------- .../tablegen/generated/encode_tables.odin | 76 +++---- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10670 -> 10670 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3298 -> 3298 bytes 12 files changed, 231 insertions(+), 196 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 7e7c740f1..c7d453b38 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -463,16 +463,19 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) op.list = {count = count, stride = 1} return op + case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: + n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), table_run_length(enc)) case .VFP_S_LIST: // {S, ...} -- imm8 counts the registers, and the run starts at Vd. // Both halves matter: keeping only the count printed the wrong bank // and the wrong registers. n := ((word >> 12) & 0xF) << 1 | ((word >> 22) & 1) - return op_reg_run(Register(REG_SPR | u16(n)), u8(word & 0xFF)) + return op_reg_run(Register(REG_SPR | u16(n)), max(u8(word & 0xFF), 1)) case .VFP_D_LIST: // {D, ...} -- imm8 counts half-words here, two per D register. n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) - return op_reg_run(Register(REG_DPR | u16(n)), u8((word & 0xFF) / 2)) + return op_reg_run(Register(REG_DPR | u16(n)), max(u8((word & 0xFF) / 2), 1)) // ---- Branch fields (decoded into RELATIVE) ---- case .BRANCH_24: @@ -639,6 +642,18 @@ decode_max_instruction_count :: #force_inline proc "contextless" (data: []u8) -> return len(data) / 2 } +// How many D registers a VTBL/VTBX table spans. +@(private="file", require_results) +table_run_length :: #force_inline proc "contextless" (e: Operand_Encoding) -> u8 { + #partial switch e { + case .NEON_VN_TABLE_1: return 1 + case .NEON_VN_TABLE_2: return 2 + case .NEON_VN_TABLE_3: return 3 + case .NEON_VN_TABLE_4: return 4 + } + return 1 +} + // Typical-case estimate of the instruction count for `data`. @(require_results) decode_estimate_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int { diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 666266a27..9b675919e 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -264,14 +264,14 @@ mem_mode_matches :: #force_inline proc "contextless" (inst: ^Instruction, form: @(private="file") encoding_matches_inline :: #force_inline proc "contextless" (inst: ^Instruction, form: ^Encoding) -> bool { - return operand_matches_inline(&inst.ops[0], form.ops[0]) && - operand_matches_inline(&inst.ops[1], form.ops[1]) && - operand_matches_inline(&inst.ops[2], form.ops[2]) && - operand_matches_inline(&inst.ops[3], form.ops[3]) + return operand_matches_inline(&inst.ops[0], form.ops[0], form.enc[0]) && + operand_matches_inline(&inst.ops[1], form.ops[1], form.enc[1]) && + operand_matches_inline(&inst.ops[2], form.ops[2], form.enc[2]) && + operand_matches_inline(&inst.ops[3], form.ops[3], form.enc[3]) } @(private="file") -operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Operand_Type) -> bool { +operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Operand_Type, enc: Operand_Encoding) -> bool { #partial switch ot { case .NONE: return op.kind == .NONE @@ -292,7 +292,16 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op case .SPR_LIST: return op.kind == .REGISTER && is_spr(op.reg) case .DPR_LIST: - return op.kind == .REGISTER && is_dpr(op.reg) + if op.kind != .REGISTER || !is_dpr(op.reg) { return false } + // Forms whose run length is a fixed pattern bit are told apart only + // by that length -- {d0} and {d0, d1} are different instructions. + #partial switch enc { + case .NEON_VN_TABLE_1: return op.list.count == 1 + case .NEON_VN_TABLE_2: return op.list.count == 2 + case .NEON_VN_TABLE_3: return op.list.count == 3 + case .NEON_VN_TABLE_4: return op.list.count == 4 + } + return true case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, @@ -509,6 +518,10 @@ pack_operand_inline :: #force_inline proc( n := u32(reg_hw(op.reg)) & 0x1F shift, mask, _ := neon_lane_shape(enc) return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift + case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: + // The run length is already a fixed bit of the form; only Vn is ours. + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 4) & 1) << 7 | (n & 0xF) << 16 case .VFP_S_LIST: n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF) diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 82643db9d..4ac261bbd 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -329,6 +329,13 @@ Operand_Encoding :: enum u8 { // ---- VFP / NEON list ---- VFP_S_LIST, // VLDM/VSTM single-prec list (8-bit count, start in Vd_S) VFP_D_LIST, // VLDM/VSTM double-prec list (8-bit count, start in Vd_D) + + // VTBL/VTBX read their table from a run of one to four D registers + // starting at Vn. Which run length applies is the `len` field, which is + // a fixed pattern bit of each form rather than something the operand + // encodes -- so the length rides in the encoding, the way the NEON + // structure-list lengths already do, and the encoder emits only Vn. + NEON_VN_TABLE_1, NEON_VN_TABLE_2, NEON_VN_TABLE_3, NEON_VN_TABLE_4, // NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list, // the register count is part of the form's type field at bits 11:8, so the // encoding writes only Vd; how many registers -- and whether the run steps diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 9e53fb4ac..5e4bdd9a3 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -976,13 +976,9 @@ inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } -inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) } -inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) } inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } @@ -2187,10 +2183,10 @@ inst_vrev64 :: inst_vrev64_d_d emit_vrev64 :: emit_vrev64_d_d inst_vext :: inst_vext_d_d_d_imm4 emit_vext :: emit_vext_d_d_d_imm4 -inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d } -emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d } -inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d } -emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d } +inst_vtbl :: inst_vtbl_d_dlist_d +emit_vtbl :: emit_vtbl_d_dlist_d +inst_vtbx :: inst_vtbx_d_dlist_d +emit_vtbx :: emit_vtbx_d_dlist_d inst_vtrn :: inst_vtrn_d_d emit_vtrn :: emit_vtrn_d_d inst_vuzp :: inst_vuzp_d_d diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 889ac3cfe..e7ac5999d 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -213,6 +213,10 @@ infer_dt_suffix_from_inst :: proc(inst: ^Instruction) -> string { if inst.operand_count == 0 { return "" } op0 := &inst.ops[0] if op0.kind != .REGISTER { return "" } + // A register list leads the load/store-multiple forms -- VPUSH, VPOP and + // friends -- and none of them take a data type. Guessing one from the + // bank produced `vpop.f64 {d0}`, which is not accepted syntax. + if op0.list.count > 0 { return "" } switch reg_class(op0.reg) { case REG_SPR: return ".f32" case REG_DPR: return ".f64" diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index ec127ce1a..562003868 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1498,14 +1498,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCMP / VCMPE: cond 1110 1011 D 0100 Vd 101 sz E 1 M 0 Vm (E=1 raises invalid op on QNaN) .VCMP = { - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VCMP with zero: cond 1110 1011 D 0101 Vd 101 sz E 1 (0) 0 0000 - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMP, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .IMPL, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, // MVE VCMP Qn, Qm -- writes VPR.P0. Per LLVM: // vcmp.i8 eq,q2,q3 -> 0xFE05_0F06 base 0xFE01_0F00 // vcmp.f32 eq,q2,q3 -> 0xEE35_0F06 base 0xEE31_0F00 @@ -1513,10 +1513,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VCMPE = { - {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, - {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .IMPL, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VCVT family: int<->float and float<->float @@ -1883,11 +1883,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 @@ -1906,10 +1906,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 @@ -1927,10 +1927,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { @@ -2261,19 +2261,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // len = 00,01,10,11 selects 1/2/3/4-vec table; op=0 TBL, 1 TBX .VTBL = { // 1-vec table - {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_1, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 2-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_2, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 3-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_3, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 4-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_4, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VTBX = { - {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_1, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_2, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_3, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_4, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VRECPE / VRSQRTE (reciprocal estimates) ---- @@ -3623,10 +3623,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, @@ -3643,10 +3643,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index fbf32d8d7..cf783d63c 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -262,8 +262,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -367,25 +367,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -398,10 +398,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -436,14 +436,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -469,8 +469,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -684,12 +684,12 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -726,17 +726,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, @@ -745,11 +745,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, @@ -759,26 +759,26 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -805,14 +805,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -1110,11 +1110,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, @@ -1138,6 +1138,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, @@ -1173,11 +1178,6 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, @@ -1673,24 +1673,24 @@ DECODE_FORM_IDX := [1649]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 24, 23, 25, 21, 22, 0, 0, 0, 19, 12, - 17, 14, 20, 18, 10, 16, 13, 15, 11, 0, 0, 0, 0, 11, 10, 0, - 6, 0, 0, 7, 2, 6, 3, 4, 9, 5, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 23, 24, 25, 22, 21, 0, 0, 0, 19, 20, + 14, 17, 16, 13, 18, 10, 12, 11, 15, 0, 0, 0, 0, 11, 10, 0, + 6, 0, 0, 7, 2, 4, 6, 9, 3, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, - 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 3, 1, 1, 3, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, + 0, 0, 2, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, @@ -1704,12 +1704,12 @@ DECODE_FORM_IDX := [1649]u16{ 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 9, 4, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 5, 4, 6, 8, 9, 2, 3, 7, 3, 7, 5, 6, 4, 2, 9, + 0, 5, 4, 3, 9, 6, 7, 8, 2, 3, 7, 5, 6, 4, 2, 9, 8, 10, 1, 0, 2, 0, 5, 1, 2, 3, 4, 2, 1, 0, 2, 0, - 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 5, 1, 3, - 2, 0, 4, 2, 0, 4, 5, 1, 3, 0, 5, 1, 3, 2, 4, 0, - 1, 2, 3, 4, 5, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 10, - 13, 12, 15, 12, 13, 14, 13, 14, 12, 15, 17, 15, 16, 14, 14, 16, + 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 1, 3, 5, + 2, 0, 4, 2, 0, 1, 4, 5, 3, 0, 5, 1, 3, 2, 4, 0, + 2, 3, 4, 5, 1, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 12, + 10, 13, 12, 15, 13, 14, 12, 14, 15, 13, 17, 14, 16, 15, 14, 16, 15, 17, 1, 2, 0, 3, 0, 1, 0, 1, 0, 1, 3, 5, 0, 2, 1, 3, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 2, 0, 2, @@ -1732,10 +1732,10 @@ DECODE_FORM_IDX := [1649]u16{ 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, 3, 2, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, - 0, 1, 0, 1, 1, 0, 2, 0, 1, 19, 18, 20, 17, 14, 12, 9, - 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, 0, 1, 0, 1, 2, - 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 4, 0, - 1, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, + 0, 1, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 19, 18, + 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, + 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, + 0, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, @@ -1905,38 +1905,38 @@ DECODE_BUCKET_LIST := [5335]u16{ 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, 1008, 995, 996, 1007, 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, - 1007, 1008, 997, 998, 992, 993, 994, 1011, 1010, 1007, 1012, 1008, 995, 1013, 996, 1015, + 1007, 1008, 997, 998, 992, 993, 994, 1010, 1011, 1007, 1012, 1008, 995, 1013, 996, 1015, 1014, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 1021, 995, 996, 1018, 1019, - 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, + 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, + 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1020, 1021, 995, 996, 1031, 1030, 1018, 1019, 1023, 1022, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, - 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, - 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, 1035, 1034, 1036, 1037, - 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1034, 1035, 1007, 1008, 1007, 1008, - 1018, 1019, 1033, 1032, 1018, 1019, 1034, 1035, 1018, 1019, 1018, 1019, 1018, 1019, 1033, 1032, - 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, 1042, 1044, 1043, 1045, - 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1055, 1043, 1044, 1056, 1007, - 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, 1064, 1065, 1066, 1044, - 1043, 1067, 1007, 1069, 1068, 1070, 1071, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1072, - 1073, 1007, 1075, 1074, 1076, 1077, 1008, 1061, 1052, 1062, 1054, 1041, 1078, 1042, 1044, 1043, + 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1020, 1021, 995, 996, + 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, 1035, 1034, 1037, 1036, + 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1035, 1034, 1007, 1008, 1007, 1008, + 1018, 1019, 1033, 1032, 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1018, 1019, 1033, 1032, + 1018, 1019, 1034, 1035, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, 1042, 1043, 1044, 1045, + 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1055, 1044, 1043, 1056, 1007, + 1058, 1057, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, 1064, 1065, 1066, 1044, + 1043, 1067, 1007, 1068, 1069, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1072, + 1073, 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1041, 1078, 1042, 1044, 1043, 1045, 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1007, - 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, 1065, 1066, 1043, 1044, - 1067, 1007, 1069, 1068, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1044, 1043, 1056, 1072, 1073, - 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1083, 1084, - 1085, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, 1092, 1094, 1093, 1061, - 1052, 1062, 1054, 1095, 1096, 1097, 1098, 1099, 1100, 1051, 1052, 1053, 1054, 1102, 1103, 1101, - 1104, 1105, 1107, 1106, 1108, 1109, 1110, 1111, 1113, 1112, 1114, 1115, 1116, 1117, 1118, 1119, - 1121, 1120, 1123, 1122, 1125, 1124, 1126, 1128, 1127, 1129, 1137, 1130, 1145, 1132, 1139, 1143, - 1146, 1133, 1134, 1144, 1131, 1142, 1138, 1141, 1136, 1135, 1140, 1148, 1147, 1149, 1150, 1152, - 1151, 1154, 1153, 1155, 1156, 1157, 1158, 1159, 1160, 1162, 1161, 1163, 1165, 1166, 1164, 1167, + 1058, 1057, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, 1065, 1066, 1043, 1044, + 1067, 1007, 1068, 1069, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1044, 1043, 1056, 1072, 1073, + 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, 1082, 1081, 1083, 1084, + 1085, 1086, 1088, 1087, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, 1092, 1094, 1093, 1061, + 1052, 1062, 1054, 1095, 1096, 1097, 1098, 1099, 1100, 1051, 1052, 1053, 1054, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1113, 1112, 1114, 1115, 1117, 1116, 1119, 1118, + 1121, 1120, 1123, 1122, 1125, 1124, 1128, 1127, 1126, 1129, 1130, 1131, 1133, 1132, 1151, 1150, + 1137, 1145, 1142, 1139, 1149, 1143, 1134, 1138, 1144, 1148, 1147, 1141, 1146, 1136, 1135, 1140, + 1153, 1152, 1154, 1155, 1158, 1159, 1156, 1157, 1160, 1161, 1163, 1162, 1165, 1164, 1167, 1166, 1168, 1169, 1170, 1172, 1171, 1056, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1084, 1083, 1085, 1173, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1092, 1091, 1094, 1093, 1061, 1052, 1062, 1054, 1174, 1175, 1095, 1096, 1098, 1097, 1099, 1100, 1051, 1052, 1053, 1054, 1176, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1111, 1110, 1113, 1112, 1115, 1114, - 1116, 1117, 1119, 1118, 1120, 1121, 1122, 1123, 1124, 1125, 1128, 1127, 1126, 1136, 1133, 1134, - 1135, 1137, 1130, 1131, 1132, 1129, 1138, 1145, 1144, 1142, 1139, 1140, 1141, 1143, 1146, 1148, - 1147, 1149, 1150, 1151, 1152, 1153, 1154, 1155, 1156, 1158, 1157, 1159, 1160, 1162, 1161, 1163, - 1166, 1164, 1165, 1168, 1167, 1170, 1169, 1171, 1172, 1056, 1061, 1052, 1062, 1054, 1007, 1008, + 1116, 1117, 1119, 1118, 1120, 1121, 1122, 1123, 1124, 1125, 1128, 1127, 1126, 1130, 1131, 1129, + 1133, 1132, 1151, 1136, 1134, 1135, 1137, 1138, 1145, 1144, 1142, 1148, 1149, 1150, 1147, 1139, + 1140, 1141, 1143, 1146, 1152, 1153, 1155, 1154, 1159, 1158, 1157, 1156, 1160, 1161, 1163, 1162, + 1164, 1165, 1166, 1167, 1168, 1170, 1169, 1171, 1172, 1056, 1061, 1052, 1062, 1054, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 7b0e2b271..f7b48caaa 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -1040,19 +1040,19 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VCMP - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VCMPE - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VCVT { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, @@ -1468,10 +1468,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1485,10 +1485,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1502,10 +1502,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1521,10 +1521,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1540,10 +1540,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -1745,15 +1745,15 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, // .VTBL - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTBX - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, diff --git 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