From cfb8a109b620c13b419b182554d2a08ff0c6bd9e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 20 Aug 2026 17:51:47 +0100 Subject: [PATCH] Begin work on pseudo-aliases --- core/rexcode/isa/riscv/encoding_types.odin | 13 +- core/rexcode/isa/riscv/mnemonics.odin | 85 ++ core/rexcode/isa/riscv/pseudo_aliases.odin | 171 +++ .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 1007 +++++++++++++++++ core/rexcode/isa/riscv/tablegen/gen.odin | 8 +- .../tablegen/generated/decode_tables.odin | 238 ++-- .../tablegen/generated/encode_tables.odin | 809 +++++++++---- .../isa/riscv/tablegen/instruction_table.odin | 322 ++++++ core/rexcode/isa/riscv/tables.odin | 4 +- .../isa/riscv/tables/riscv.clobber_forms.bin | Bin 1782 -> 2547 bytes .../isa/riscv/tables/riscv.encode_forms.bin | Bin 3960 -> 5943 bytes .../isa/riscv/tables/riscv.encode_runs.bin | Bin 1592 -> 2256 bytes .../isa/riscv/tables/riscv.entries.bin | Bin 3960 -> 5943 bytes .../isa/riscv/tables/riscv.idx_op_fp.bin | Bin 512 -> 512 bytes .../isa/riscv/tables/riscv.idx_opcode.bin | Bin 512 -> 512 bytes .../isa/riscv/tables/riscv.idx_rvc.bin | Bin 128 -> 128 bytes .../x86/tablegen/cpp-compiler/cpp-gen.odin | 18 + 17 files changed, 2403 insertions(+), 272 deletions(-) create mode 100644 core/rexcode/isa/riscv/pseudo_aliases.odin create mode 100644 core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin diff --git a/core/rexcode/isa/riscv/encoding_types.odin b/core/rexcode/isa/riscv/encoding_types.odin index bf3e1bd11..cd0527c73 100644 --- a/core/rexcode/isa/riscv/encoding_types.odin +++ b/core/rexcode/isa/riscv/encoding_types.odin @@ -40,7 +40,7 @@ LABEL_UNDEFINED :: isa.LABEL_UNDEFINED Label_Map :: isa.Label_Map // Extension this entry belongs to (metadata, not used by the matcher). -Feature :: enum u8 { +Feature :: enum u16 { I, // RV32I / RV64I base integer M, // multiply / divide A, // atomics @@ -49,6 +49,13 @@ Feature :: enum u8 { ZICSR, // CSR access (CSRRW/S/C + immediate forms) ZIFENCEI, // FENCE.I (instruction-fetch fence) C, // 16-bit compressed instructions + ZBA, // address-generation bit-manip + ZBB, // basic bit-manip + ZBC, // carry-less multiply + ZBS, // single-bit bit-manip + ZICOND, // conditional zeroing + ZFH, // half-precision (binary16) FP + PRIV, // privileged trap-return / TLB maintenance } Encoding_Flags :: bit_field u8 { @@ -150,10 +157,10 @@ Encoding :: struct #packed { enc: [4]Operand_Encoding, // 4 bits: u32, // 4 -- static bit pattern mask: u32, // 4 -- which bits are static - feature: Feature, // 1 + feature: Feature, // 2 flags: Encoding_Flags, // 1 } -#assert(size_of(Encoding) == 20) +#assert(size_of(Encoding) == 21) // inst_size_from_bits returns 2 for compressed (RVC) instructions, 4 for the // standard 32-bit base ISA. RISC-V uses a length-encoding convention where diff --git a/core/rexcode/isa/riscv/mnemonics.odin b/core/rexcode/isa/riscv/mnemonics.odin index e492c4e82..02335bb93 100644 --- a/core/rexcode/isa/riscv/mnemonics.odin +++ b/core/rexcode/isa/riscv/mnemonics.odin @@ -139,4 +139,89 @@ Mnemonic :: enum u16 { C_FLDSP, C_FSDSP, C_JR, C_JALR, C_MV, C_ADD, C_FLWSP, C_FSWSP, + + + SH1ADD, + SH2ADD, + SH3ADD, + ADD_UW, + SH1ADD_UW, + SH2ADD_UW, + SH3ADD_UW, + SLLI_UW, + ANDN, + ORN, + XNOR, + CLZ, + CTZ, + CPOP, + SEXT_B, + SEXT_H, + ZEXT_H, + MIN, + MINU, + MAX, + MAXU, + ROL, + ROR, + RORI, + ORC_B, + REV8, + CLZW, + CTZW, + CPOPW, + ROLW, + RORW, + RORIW, + CLMUL, + CLMULH, + CLMULR, + BCLR, + BCLRI, + BEXT, + BEXTI, + BINV, + BINVI, + BSET, + BSETI, + CZERO_EQZ, + CZERO_NEZ, + FLH, + FSH, + FMADD_H, + FMSUB_H, + FNMSUB_H, + FNMADD_H, + FADD_H, + FSUB_H, + FMUL_H, + FDIV_H, + FSQRT_H, + FSGNJ_H, + FSGNJN_H, + FSGNJX_H, + FMIN_H, + FMAX_H, + FCVT_W_H, + FCVT_WU_H, + FCVT_L_H, + FCVT_LU_H, + FCVT_H_W, + FCVT_H_WU, + FCVT_H_L, + FCVT_H_LU, + FCVT_S_H, + FCVT_H_S, + FCVT_D_H, + FCVT_H_D, + FMV_X_H, + FMV_H_X, + FCLASS_H, + FEQ_H, + FLT_H, + FLE_H, + MRET, + SRET, + WFI, + SFENCE_VMA, } diff --git a/core/rexcode/isa/riscv/pseudo_aliases.odin b/core/rexcode/isa/riscv/pseudo_aliases.odin new file mode 100644 index 000000000..a7a3f037a --- /dev/null +++ b/core/rexcode/isa/riscv/pseudo_aliases.odin @@ -0,0 +1,171 @@ +package rexcode_riscv + +// ============================================================================= +// RISC-V PSEUDO-INSTRUCTION ALIAS TABLE +// +// Every entry here lowers to exactly ONE real INSTRUCTION_TABLE mnemonic by +// filling that target's operand slots. The real entry supplies the encoding +// and the clobber set for free — a pseudo's dataflow is its target's dataflow. +// +// Pseudos that CANNOT be expressed this way (value-dependent expansions and a +// couple of fixed-word HINTs) are listed as comments at the bottom; they stay +// procedures or dedicated table rows. +// ============================================================================= + +// How each operand slot of the target instruction is filled. +Alias_Src :: enum u8 { + NONE, // slot unused + ARG0, // user's 1st operand + ARG1, // user's 2nd operand + ARG2, // user's 3rd operand + X0, // hardwired zero (x0) + X1, // link register (ra / x1) + LIT, // the `lit` field below (immediate literal) + CSR_LIT, // the `csr` field below (fixed 12-bit CSR address) +} + +Pseudo_Alias :: struct { + target: Mnemonic, // real instruction emitted + src: [4]Alias_Src, // how to fill target's four operand slots + lit: i16, // immediate when a src slot is .LIT + csr: u16, // CSR address when a src slot is .CSR_LIT + nargs: u8, // operands the user supplies (ARG0.. generated/ + this file + // odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin + // odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals + // + \n\n + """) + + + // strings.write_string(&sb, "struct Asm_a + fmt.sbprintf(&sb, "struct Asm_%s {{\n", ISA_NAME) + { + strings.write_string(&sb, "\tenum Mnemonic : u16 {\n") + defer strings.write_string(&sb, "\t};\n"); + + iota := 0 + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + assert(int(mnemonic) == iota) + fmt.sbprintf(&sb, "M_%s, ", mnemonic) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + iota += 1 + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n\n"); + strings.write_string(&sb, "\t\tMNEMONIC_COUNT\n"); + } + + strings.write_string(&sb, "\tstatic String const mnemonic_strings[MNEMONIC_COUNT];\n") + + { + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + enum Prefix : u8 { + PREFIX_INVALID, + PREFIX_COUNT + }; + enum PrefixKind : u8 { PrefixKind_None }; + \n + """) + } + { + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + static const u16 REG_CLASS_NONE = 0x000; + static const u16 REG_CLASS_GPR64 = 0x100; + static const u16 REG_CLASS_GPR32 = 0x200; + static const u16 REG_CLASS_GPR16 = 0x300; + static const u16 REG_CLASS_GPR8 = 0x400; + static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs + static const u16 REG_CLASS_XMM = 0x600; + static const u16 REG_CLASS_YMM = 0x700; + static const u16 REG_CLASS_ZMM = 0x800; + static const u16 REG_CLASS_K = 0x900; // opmask + static const u16 REG_CLASS_SEG = 0xA00; // segment + static const u16 REG_CLASS_CR = 0xB00; // control + static const u16 REG_CLASS_DR = 0xC00; // debug + static const u16 REG_CLASS_BND = 0xD00; // bound + static const u16 REG_CLASS_MM = 0xE00; // MMX + static const u16 REG_CLASS_ST = 0xF00; // x87 FPU + \n + """) + { + count := uint(0) + ROW_COUNT :: 16 + strings.write_string(&sb, "\tenum Register : u16 {\n") + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + fmt.sbprintf(&sb, "REG_%s, ", reg) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\t\tREG_COUNT\n") + strings.write_string(&sb, "\t};\n") + } + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + + enum ClobberFFlags : u8 { + ClobberFFlag_NV = 1<<0, // invalid operation + ClobberFFlag_DZ = 1<<1, // divide by zero + ClobberFFlag_OF = 1<<2, // overflow + ClobberFFlag_UF = 1<<3, // underflow + ClobberFFlag_NX = 1<<4, // inexact + }; + + enum ClobberRegs : u8 { + ClobberReg_RA = 1<<0, // x1, implicit link on C.JAL / C.JALR + ClobberReg_SP = 1<<1, // x2, implicit base on the *SP compressed forms + }; + + static u8 const CLOBBER_REGS_NAMED = ClobberReg_RA|ClobberReg_SP; + + enum SideEffectFlags : u8 { + SideEffectFlag_CONTROL = 1<<0, // writes pc: branches, jumps, and trap redirects + SideEffectFlag_TRAP = 1<<1, // synchronous environment trap (ECALL / EBREAK) + SideEffectFlag_FENCE = 1<<2, // explicit memory-ordering barrier (FENCE) + SideEffectFlag_IFENCE = 1<<3, // instruction-fetch synchronization (FENCE.I) + SideEffectFlag_ATOMIC = 1<<4, // indivisible memory RMW (AMO*, and the LR/SC pair) + SideEffectFlag_RESERVATION = 1<<5, // sets or tests an LR/SC reservation + }; + + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + + u16 clobber_bit_for_reg_name(String const &pin) { + static const struct { String name; u16 bit; } table[] = { + {str_lit(\"ra\"), ClobberReg_RA}, + {str_lit(\"sp\"), ClobberReg_SP}, + {str_lit(\"x1\"), ClobberReg_RA}, + {str_lit(\"x2\"), ClobberReg_SP}, + }; + for (auto const &t : table) { + if (pin == t.name) { + return t.bit; + } + } + return 0; + } + + char const *clobber_reg_bit_name(u16 bit) { + switch (bit) { + case ClobberReg_RA: return \"ra\"; + case ClobberReg_SP: return \"sp\"; + } + return \"\"; + } + + i32 flag_bit_from_name(String const &name, i32 *width_) { + static const struct { String name; i32 bit; } table[] = { + // fflags: accrued FP exception flags (fcsr[4:0]) + {str_lit(\"nx\"), 0}, // Inexact + {str_lit(\"uf\"), 1}, // Underflow + {str_lit(\"of\"), 2}, // Overflow + {str_lit(\"dz\"), 3}, // Divide by Zero + {str_lit(\"nv\"), 4}, // Invalid Operation + // frm: rounding mode (fcsr[7:5], 3-bit field, low bit) + {str_lit(\"frm\"), 5}, // Rounding Mode + }; + + for (auto const &t : table) { + if (name == t.name) { + if (width_) { + if (t.name == \"frm\") { + *width_ = 3; + } else { + *width_ = 1; + } + } + return t.bit; + } + } + return -1; + } + + + struct Clobber { + OperandSet written; // operand slots whose register/CSR is written + OperandSet read; // operand slots whose register/CSR/mem-base is read + ClobberRegs implicit_wr; // implicit reg writes (ra on C.JAL/C.JALR) + ClobberRegs implicit_rd; // implicit reg reads (sp on the *SP forms) + ClobberFFlags fflags_wr; // accrued exception flags this op may raise + bool reads_frm; // consumes the dynamic rounding mode from fcsr + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; + + bool implies_clobber_flags() const { + return (fflags_wr != 0); + } + bool implies_clobber_memory() const { + return writes_mem || reads_mem || + (side_effects & (SideEffectFlag_FENCE|SideEffectFlag_ATOMIC)) != 0; + } + bool implies_side_effects() const { + return side_effects != 0; + } + u8 is_call_or_mem() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0 || + (cast(u16)implicit_wr & ClobberReg_SP) != 0; + } + bool has_control() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0; + } + bool has_halt() const { + return (cast(u16)side_effects & SideEffectFlag_TRAP) != 0; + } + bool is_conditional() const { + return has_control(); + } + }; + + void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { + u8 regs = cast(u8)implicit_regs; + + for (u8 bit = 1; bit != 0; bit <<= 1) { + if ((regs & bit) == 0) { + continue; + } + char const *rname = clobber_reg_bit_name(bit); + string_set_update(clobber_registers_set, make_string_c(rname)); + } + } + """) + strings.write_string(&sb, "\n") + + strings.write_string(&sb, "\n") + { + strings.write_string(&sb, """ + enum AliasSrc : u8 { + AliasSrc_NONE, // slot unused + AliasSrc_ARG0, // user's 1st operand + AliasSrc_ARG1, // user's 2nd operand + AliasSrc_ARG2, // user's 3rd operand + AliasSrc_X0, // hardwired zero (x0) + AliasSrc_X1, // link register (ra / x1) + AliasSrc_LIT, // the `lit` field below (immediate literal) + AliasSrc_CSR_LIT, // the `csr` field below (fixed 12-bit CSR address) + }; + + struct PseudoAlias { + Mnemonic target; // real instruction emitted + AliasSrc src[4]; // how to fill target's four operand slots + i16 lit; // immediate when a src slot is AliasSrc_LIT + u16 csr; // CSR address when a src slot is AliasSrc_CSR_LIT + u8 nargs; // operands the user supplies (ARG0..>%du)&1) != 0;", bit_offset) + strings.write_string(&sb, " }\n") + } + { + bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "explicit_count") + bit_size := intrinsics.type_field_bit_size(Encoding_Flags, "explicit_count") + strings.write_string(&sb, "\t\tu8 explicit_count() const { ") + fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) + strings.write_string(&sb, " }\n") + } + // { + // bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "op_count") + // bit_size := intrinsics.type_field_bit_size(Encoding_Flags, "op_count") + // strings.write_string(&sb, "\t\tu8 op_count () const { ") + // fmt.sbprintf(&sb, "return cast(u8)((flags>>%du)&((1u<<%d)-1));", bit_offset, bit_size) + // strings.write_string(&sb, " }\n") + // } + // { + // bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "lock_ok") + // strings.write_string(&sb, "\t\tbool lock_ok () const { ") + // fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) + // strings.write_string(&sb, " }\n") + // } + // { + // bit_offset := intrinsics.type_field_bit_offset(Encoding_Flags, "rep_ok") + // strings.write_string(&sb, "\t\tbool rep_ok () const { ") + // fmt.sbprintf(&sb, "return ((flags>>%du)&1) != 0;", bit_offset) + // strings.write_string(&sb, " }\n") + // } + } + strings.write_string(&sb, "\n\n") + { + strings.write_string(&sb, "\t// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.\n") + strings.write_string(&sb, "\tstruct EncodeRun {\n") + strings.write_string(&sb, "\t\tu32 start; // start index in ENCODE_FORMS\n") + strings.write_string(&sb, "\t\tu32 count; // number of forms for this mnemonic\n") + strings.write_string(&sb, "\t};\n") + } + + strings.write_string(&sb, "\n\n") + fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs [%d];\n", len(raw_encode_runs)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms [%d];\n", len(raw_encode_forms)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_forms [%d];\n", len(raw_clobber_forms)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_pseudo_aliases[%d];\n", len(raw_pseudo_aliases)) + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\tStringMap mnemonic_map;\n") + strings.write_string(&sb, "\tStringMap register_map;\n") + strings.write_string(&sb, "\tStringMap pseudo_register_map;\n") + + strings.write_string(&sb, """ + + u16 XLEN; + u16 FLEN; + + bool init(i64 word_size) { + XLEN = cast(u16)word_size; + FLEN = cast(u16)word_size; + + string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); + for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { + string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); + } + + string_map_init(&mnemonic_map, PSEUDO_MNEMONIC_COUNT*2); + for (u16 m = PM_INVALID+1; m < PSEUDO_MNEMONIC_COUNT; m++) { + string_map_set(&pseudo_mnemonic_map, pseudo_mnemonic_strings[m], cast(PseudoMnemonic)m); + } + + string_map_init(®ister_map, REG_COUNT*2); + for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_strings[r], cast(Register)r); + } + return true; + } + + Mnemonic mnemonic_lookup(String const &name) { + Mnemonic *found = string_map_get(&mnemonic_map, name); + return found ? *found : M_INVALID; + } + Prefix prefix_lookup(String const &name) { + return PREFIX_INVALID; + } + static String const prefix_strings[PREFIX_COUNT]; + + Register register_lookup(String const &name) { + Register *found = string_map_get(®ister_map, name); + return found ? *found : REG_INVALID; + } + Slice encoding_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; + return Slice{ENCODE_FORMS+r.start, r.count}; + } + Slice clobber_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms; + return Slice{CLOBBER_FORMS+r.start, r.count}; + } + u16 reg_class(/*Register*/ u16 r) const { + return 0xFF00 & r; + } + // size in bits for register + u16 reg_size(Register r) const { + switch (reg_class(register_codes[r])) { + case REG_CLASS_GPR64: return 64; + case REG_CLASS_GPR32: return 32; + case REG_CLASS_GPR16: return 16; + case REG_CLASS_GPR8: return 8; + case REG_CLASS_GPR8H: return 8; + case REG_CLASS_XMM: return 128; + case REG_CLASS_YMM: return 256; + case REG_CLASS_ZMM: return 512; + case REG_CLASS_K: return 64; + case REG_CLASS_MM: return 64; + case REG_CLASS_ST: return 80; + case REG_CLASS_SEG: return 16; + case REG_CLASS_CR: return 64; + case REG_CLASS_DR: return 64; + case REG_CLASS_BND: return 128; + } + return 0; + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmOperandKind kind_from_operand_type(OperandType type) const { + switch (type) { + case OP_NONE: + return AsmOperand_Invalid; + + // Registers + case OP_GPR: + case OP_FPR: + case OP_GPR_C: + case OP_GPR_SP: + case OP_GPR_NONZERO: + case OP_FPR_C: + return AsmOperand_Register; + + case OP_CSR: // 12-bit CSR address; treat as immediate (no CSR reg class exists) + // TODO(bill): what should this be? + return AsmOperand_Immediate; + + // Immediates (incl. things that ultimately encode as an immediate field: + // CSR address, fence flags, rounding mode). + case OP_IMM12: + case OP_IMM12U: + case OP_IMM5: + case OP_IMM6: + case OP_IMM20: + case OP_FENCE_FLAGS: // iorw mask -> 4-bit immediate field + case OP_ROUND_MODE: // rm -> 3-bit immediate field + case OP_ZIMM5: + case OP_IMM_C6S: + case OP_IMM_C6U: + case OP_IMM_C8U: + case OP_IMM_C10S: + case OP_IMM_C18S: + return AsmOperand_Immediate; + + // Branch/jump targets are written as labels. + case OP_REL13: + case OP_REL21: + case OP_REL9: + case OP_REL12: + return AsmOperand_Label; + + // Memory + case OP_MEM: + case OP_MEM_C_W: + case OP_MEM_C_D: + case OP_MEM_C_SP_W: + case OP_MEM_C_SP_D: + return AsmOperand_Memory; + } + return AsmOperand_Invalid; + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmRegClass reg_class_from_operand_type(OperandType type) const { + switch (type) { + case OP_GPR: + case OP_GPR_C: + case OP_GPR_SP: + case OP_GPR_NONZERO: + return AsmRegClass_Integer; + + case OP_FPR: + case OP_FPR_C: + return AsmRegClass_Float; + + // No vector/mask operand types are present in this list; everything + // else (immediates, memory, labels, CSR, etc.) has no register class. + default: + return AsmRegClass_Unknown; + } + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + bool operand_type_is_implicit(OperandType t) const { + switch (t) { + // sp is fixed by the mnemonic (c.addi16sp / c.*sp bases) and isn't a + // register the user freely chooses, so it's encoded implicitly. + // If your parser actually reads `sp` from the operand text, flip this. + case OP_GPR_SP: + return true; + default: + return false; + } + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmRegClass operand_type_reg_class(OperandType t) const { + // Same mapping as reg_class_from_operand_type — these two look + // redundant; consider collapsing them into one. + return reg_class_from_operand_type(t); + } + """) + + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + u16 operand_type_bit_width(OperandType t) const { + switch (t) { + case OP_NONE: + return 0; + + // Registers -> architectural register data width (like OP_R*, OP_XMM). + // RISC-V doesn't encode width in the operand type: GPR is XLEN, FPR is + // FLEN, both target-config dependent -> treat as data-dependent = 0, + // same as x86 OP_K. (Or hardcode 32/64 if your assembler is fixed-config.) + // The _C / _SP / _NONZERO variants only restrict *which* regs, not width. + case OP_GPR: + case OP_GPR_C: + case OP_GPR_SP: + case OP_GPR_NONZERO: + return XLEN; + case OP_FPR: + case OP_FPR_C: + return FLEN; + + // Memory -> access size (like OP_M*). Base OP_MEM's size comes from the opcode. + // Compressed forms name the size. + case OP_MEM: + return 0; + case OP_MEM_C_W: + case OP_MEM_C_SP_W: + return 32; + case OP_MEM_C_D: + case OP_MEM_C_SP_D: + return 64; + + // Immediates -> value width + case OP_IMM12: + case OP_IMM12U: + case OP_CSR: + return 12; + case OP_IMM5: + case OP_ZIMM5: + return 5; + case OP_IMM6: + return 6; + case OP_IMM20: + return 20; + case OP_FENCE_FLAGS: + return 4; + case OP_ROUND_MODE: + return 3; + case OP_IMM_C6S: + case OP_IMM_C6U: + return 6; + case OP_IMM_C8U: + return 8; + case OP_IMM_C10S: + return 10; + case OP_IMM_C18S: + return 18; + + // Rels -> displacement value width + case OP_REL13: + return 13; + case OP_REL21: + return 21; + case OP_REL9: + return 9; + case OP_REL12: + return 12; + } + return 0; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + int form_explicit_slot(Encoding const &form, int explicit_index) const { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const { + // RISC-V does not have prefixes + return false; + } + """) + + strings.write_string(&sb, "\n};\n") + + strings.write_string(&sb, "\n\n\n") + + fmt.sbprintf(&sb, "gb_global Asm_{0:s} g_asm_{0:s};\n", ISA_NAME) + + strings.write_string(&sb, "\n\n\n") + + fmt.sbprintf(&sb, "String const Asm_{0:s}::prefix_strings[Asm_{0:s}::PREFIX_COUNT]{{}};\n", ISA_NAME) + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::mnemonic_strings[Asm_{0:s}::MNEMONIC_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t") + } + + #partial switch mnemonic { + case .INVALID: + strings.write_string(&sb, "str_lit(\"\"), ") + case: + str := strings.to_lower(reflect.enum_string(mnemonic)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "u16 const Asm_{0:s}::register_codes[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + fmt.sbprintf(&sb, "%d, ", REG_CODES[reg]) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::register_strings[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if reg == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else { + str := strings.to_lower(reflect.enum_string(reg)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::pseudo_mnemonic_strings[Asm_{0:s}::PSEUDO_MNEMONIC_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 8 + for pm in riscv.Pseudo_Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if pm == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else { + str := strings.to_lower(reflect.enum_string(pm)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "Asm_{0:s}::EncodeRun const Asm_{0:s}::raw_encode_runs[{1:d}] = {{\n", ISA_NAME, len(raw_encode_runs)) + defer strings.write_string(&sb, "};\n"); + + ROW_COUNT :: 16 + count := 0 + for run in raw_encode_runs { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "{{% 4d, % 2d}}, ", run.start, run.count) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_encode_forms[%d] = {{\n", ISA_NAME, len(raw_encode_forms)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_encode_forms { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_clobber_forms[%d] = {{\n", ISA_NAME, len(raw_clobber_forms)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_clobber_forms { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_pseudo_aliases[%d] = {{\n", ISA_NAME, len(raw_pseudo_aliases)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_pseudo_aliases { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + + + + path := fmt.tprintf("%s/src/asm_tables_%s.cpp", ODIN_ROOT, ISA_NAME) + + if err := os.write_entire_file(path, strings.to_string(sb)); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", path, err) + os.exit(1) + } +} + +Operand_Encoding :: type_of(gen.Encoding{}.enc[0]) +Feature :: type_of(gen.Encoding{}.feature) + + + +Register :: enum u16 { + INVALID, + ZERO, + RA, + SP, + GP, + TP, + T0, + T1, + T2, + S0, + S1, + A0, + A1, + A2, + A3, + A4, + A5, + A6, + A7, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + T3, + T4, + T5, + T6, + FT0, + FT1, + FT2, + FT3, + FT4, + FT5, + FT6, + FT7, + FS0, + FS1, + FA0, + FA1, + FA2, + FA3, + FA4, + FA5, + FA6, + FA7, + FS2, + FS3, + FS4, + FS5, + FS6, + FS7, + FS8, + FS9, + FS10, + FS11, + FT8, + FT9, + FT10, + FT11, +} + +REG_NONE :: 0x0000 +REG_GPR :: 0x0100 // x0..x31 +REG_FPR :: 0x0200 // f0..f31 + +@(rodata) +REG_CODES := [Register]riscv.Register{ + .INVALID = 0, + + .ZERO = riscv.Register(REG_GPR | 0), + .RA = riscv.Register(REG_GPR | 1), + .SP = riscv.Register(REG_GPR | 2), + .GP = riscv.Register(REG_GPR | 3), + .TP = riscv.Register(REG_GPR | 4), + .T0 = riscv.Register(REG_GPR | 5), .T1 = riscv.Register(REG_GPR | 6), .T2 = riscv.Register(REG_GPR | 7), + .S0 = riscv.Register(REG_GPR | 8), .S1 = riscv.Register(REG_GPR | 9), + .A0 = riscv.Register(REG_GPR | 10), .A1 = riscv.Register(REG_GPR | 11), .A2 = riscv.Register(REG_GPR | 12), .A3 = riscv.Register(REG_GPR | 13), + .A4 = riscv.Register(REG_GPR | 14), .A5 = riscv.Register(REG_GPR | 15), .A6 = riscv.Register(REG_GPR | 16), .A7 = riscv.Register(REG_GPR | 17), + .S2 = riscv.Register(REG_GPR | 18), .S3 = riscv.Register(REG_GPR | 19), .S4 = riscv.Register(REG_GPR | 20), .S5 = riscv.Register(REG_GPR | 21), + .S6 = riscv.Register(REG_GPR | 22), .S7 = riscv.Register(REG_GPR | 23), .S8 = riscv.Register(REG_GPR | 24), .S9 = riscv.Register(REG_GPR | 25), + .S10 = riscv.Register(REG_GPR | 26), .S11 = riscv.Register(REG_GPR | 27), + .T3 = riscv.Register(REG_GPR | 28), .T4 = riscv.Register(REG_GPR | 29), .T5 = riscv.Register(REG_GPR | 30), .T6 = riscv.Register(REG_GPR | 31), + + .FT0 = riscv.Register(REG_FPR | 0), .FT1 = riscv.Register(REG_FPR | 1), .FT2 = riscv.Register(REG_FPR | 2), .FT3 = riscv.Register(REG_FPR | 3), + .FT4 = riscv.Register(REG_FPR | 4), .FT5 = riscv.Register(REG_FPR | 5), .FT6 = riscv.Register(REG_FPR | 6), .FT7 = riscv.Register(REG_FPR | 7), + .FS0 = riscv.Register(REG_FPR | 8), .FS1 = riscv.Register(REG_FPR | 9), + .FA0 = riscv.Register(REG_FPR | 10), .FA1 = riscv.Register(REG_FPR | 11), .FA2 = riscv.Register(REG_FPR | 12), .FA3 = riscv.Register(REG_FPR | 13), + .FA4 = riscv.Register(REG_FPR | 14), .FA5 = riscv.Register(REG_FPR | 15), .FA6 = riscv.Register(REG_FPR | 16), .FA7 = riscv.Register(REG_FPR | 17), + .FS2 = riscv.Register(REG_FPR | 18), .FS3 = riscv.Register(REG_FPR | 19), .FS4 = riscv.Register(REG_FPR | 20), .FS5 = riscv.Register(REG_FPR | 21), + .FS6 = riscv.Register(REG_FPR | 22), .FS7 = riscv.Register(REG_FPR | 23), .FS8 = riscv.Register(REG_FPR | 24), .FS9 = riscv.Register(REG_FPR | 25), + .FS10 = riscv.Register(REG_FPR | 26), .FS11 = riscv.Register(REG_FPR | 27), + .FT8 = riscv.Register(REG_FPR | 28), .FT9 = riscv.Register(REG_FPR | 29), .FT10 = riscv.Register(REG_FPR | 30), .FT11 = riscv.Register(REG_FPR | 31), + +} \ No newline at end of file diff --git a/core/rexcode/isa/riscv/tablegen/gen.odin b/core/rexcode/isa/riscv/tablegen/gen.odin index 0a7ee797a..c04385301 100644 --- a/core/rexcode/isa/riscv/tablegen/gen.odin +++ b/core/rexcode/isa/riscv/tablegen/gen.odin @@ -331,6 +331,10 @@ flags_lit :: proc(f: lib.Encoding_Flags) -> string { if f.rv64_only { append(&parts, "rv64_only=true") } if f.branch { append(&parts, "branch=true") } if f.fp_round { append(&parts, "fp_round=true") } + if f.explicit_count > 0 { + append(&parts, fmt.tprintf("explicit_count=%d", f.explicit_count)) + } + if f.has_implicit { append(&parts, "has_implicit=true") } return strings.join(parts[:], ", ", context.temp_allocator) } @@ -375,9 +379,9 @@ Decode_Entry :: struct #packed { bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 - flags: Encoding_Flags, // 1 + flags: Encoding_Flags, // 2 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 21) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/riscv/tablegen/generated/decode_tables.odin b/core/rexcode/isa/riscv/tablegen/generated/decode_tables.odin index a737af544..8d5c3e980 100644 --- a/core/rexcode/isa/riscv/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/riscv/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_riscv_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [198]lib.Decode_Entry{ +DECODE_ENTRIES := [283]lib.Decode_Entry{ { .LB, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00000003, 0x0000707F, .I, {} }, { .LH, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001003, 0x0000707F, .I, {} }, { .LW, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002003, 0x0000707F, .I, {} }, @@ -18,11 +18,25 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .LD, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003003, 0x0000707F, .I, {rv64_only=true} }, { .FLW, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002007, 0x0000707F, .F, {} }, { .FLD, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003007, 0x0000707F, .D, {} }, + { .FLH, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001007, 0x0000707F, .ZFH, {} }, { .FENCE_I, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000100F, 0xFFFFFFFF, .ZIFENCEI, {} }, { .FENCE, {.FENCE_FLAGS,.FENCE_FLAGS,.NONE,.NONE}, {.FENCE_PRED,.FENCE_SUCC,.NONE,.NONE}, 0x0000000F, 0x0000707F, .I, {} }, + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60001013, 0xFFF0707F, .ZBB, {} }, + { .CTZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60101013, 0xFFF0707F, .ZBB, {} }, + { .CPOP, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60201013, 0xFFF0707F, .ZBB, {} }, + { .SEXT_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60401013, 0xFFF0707F, .ZBB, {} }, + { .SEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60501013, 0xFFF0707F, .ZBB, {} }, + { .ORC_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x28705013, 0xFFF0707F, .ZBB, {} }, + { .REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x69805013, 0xFFF0707F, .ZBB, {rv32_only=true} }, + { .REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6B805013, 0xFFF0707F, .ZBB, {rv64_only=true} }, { .SLLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00001013, 0xFC00707F, .I, {} }, { .SRLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00005013, 0xFC00707F, .I, {} }, { .SRAI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x40005013, 0xFC00707F, .I, {} }, + { .RORI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x60005013, 0xFC00707F, .ZBB, {} }, + { .BCLRI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48001013, 0xFC00707F, .ZBS, {} }, + { .BEXTI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48005013, 0xFC00707F, .ZBS, {} }, + { .BINVI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x68001013, 0xFC00707F, .ZBS, {} }, + { .BSETI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x28001013, 0xFC00707F, .ZBS, {} }, { .ADDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00000013, 0x0000707F, .I, {} }, { .SLTI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00002013, 0x0000707F, .I, {} }, { .SLTIU, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00003013, 0x0000707F, .I, {} }, @@ -30,9 +44,14 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .ORI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00006013, 0x0000707F, .I, {} }, { .ANDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00007013, 0x0000707F, .I, {} }, { .AUIPC, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000017, 0x0000007F, .I, {} }, + { .CLZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6000101B, 0xFFF0707F, .ZBB, {rv64_only=true} }, + { .CTZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6010101B, 0xFFF0707F, .ZBB, {rv64_only=true} }, + { .CPOPW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6020101B, 0xFFF0707F, .ZBB, {rv64_only=true} }, { .SLLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000101B, 0xFE00707F, .I, {rv64_only=true} }, { .SRLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000501B, 0xFE00707F, .I, {rv64_only=true} }, { .SRAIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x4000501B, 0xFE00707F, .I, {rv64_only=true} }, + { .RORIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x6000501B, 0xFE00707F, .ZBB, {rv64_only=true} }, + { .SLLI_UW, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x0800101B, 0xFC00707F, .ZBA, {rv64_only=true} }, { .ADDIW, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x0000001B, 0x0000707F, .I, {rv64_only=true} }, { .SB, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00000023, 0x0000707F, .I, {} }, { .SH, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001023, 0x0000707F, .I, {} }, @@ -40,6 +59,7 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .SD, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003023, 0x0000707F, .I, {rv64_only=true} }, { .FSW, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00002027, 0x0000707F, .F, {} }, { .FSD, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003027, 0x0000707F, .D, {} }, + { .FSH, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001027, 0x0000707F, .ZFH, {} }, { .LR_W, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000202F, 0xF9F0707F, .A, {} }, { .LR_D, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000302F, 0xF9F0707F, .A, {rv64_only=true} }, { .SC_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x1800202F, 0xF800707F, .A, {} }, @@ -62,6 +82,7 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .AMOMAX_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xA000302F, 0xF800707F, .A, {rv64_only=true} }, { .AMOMINU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xC000302F, 0xF800707F, .A, {rv64_only=true} }, { .AMOMAXU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xE000302F, 0xF800707F, .A, {rv64_only=true} }, + { .ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x08004033, 0xFFF0707F, .ZBB, {rv32_only=true} }, { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000033, 0xFE00707F, .I, {} }, { .SUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40000033, 0xFE00707F, .I, {} }, { .SLL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00001033, 0xFE00707F, .I, {} }, @@ -80,7 +101,29 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02005033, 0xFE00707F, .M, {} }, { .REM, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02006033, 0xFE00707F, .M, {} }, { .REMU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02007033, 0xFE00707F, .M, {} }, + { .SH1ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002033, 0xFE00707F, .ZBA, {} }, + { .SH2ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20004033, 0xFE00707F, .ZBA, {} }, + { .SH3ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20006033, 0xFE00707F, .ZBA, {} }, + { .ANDN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40007033, 0xFE00707F, .ZBB, {} }, + { .ORN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40006033, 0xFE00707F, .ZBB, {} }, + { .XNOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40004033, 0xFE00707F, .ZBB, {} }, + { .MIN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A004033, 0xFE00707F, .ZBB, {} }, + { .MINU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A005033, 0xFE00707F, .ZBB, {} }, + { .MAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A006033, 0xFE00707F, .ZBB, {} }, + { .MAXU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A007033, 0xFE00707F, .ZBB, {} }, + { .ROL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60001033, 0xFE00707F, .ZBB, {} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60005033, 0xFE00707F, .ZBB, {} }, + { .CLMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A001033, 0xFE00707F, .ZBC, {} }, + { .CLMULH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A003033, 0xFE00707F, .ZBC, {} }, + { .CLMULR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A002033, 0xFE00707F, .ZBC, {} }, + { .BCLR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48001033, 0xFE00707F, .ZBS, {} }, + { .BEXT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48005033, 0xFE00707F, .ZBS, {} }, + { .BINV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x68001033, 0xFE00707F, .ZBS, {} }, + { .BSET, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001033, 0xFE00707F, .ZBS, {} }, + { .CZERO_EQZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E005033, 0xFE00707F, .ZICOND, {} }, + { .CZERO_NEZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E007033, 0xFE00707F, .ZICOND, {} }, { .LUI, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000037, 0x0000007F, .I, {} }, + { .ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x0800403B, 0xFFF0707F, .ZBB, {rv64_only=true} }, { .ADDW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000003B, 0xFE00707F, .I, {rv64_only=true} }, { .SUBW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x4000003B, 0xFE00707F, .I, {rv64_only=true} }, { .SLLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000103B, 0xFE00707F, .I, {rv64_only=true} }, @@ -91,42 +134,69 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .DIVUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200503B, 0xFE00707F, .M, {rv64_only=true} }, { .REMW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200603B, 0xFE00707F, .M, {rv64_only=true} }, { .REMUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200703B, 0xFE00707F, .M, {rv64_only=true} }, + { .ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0800003B, 0xFE00707F, .ZBA, {rv64_only=true} }, + { .SH1ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000203B, 0xFE00707F, .ZBA, {rv64_only=true} }, + { .SH2ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000403B, 0xFE00707F, .ZBA, {rv64_only=true} }, + { .SH3ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000603B, 0xFE00707F, .ZBA, {rv64_only=true} }, + { .ROLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000103B, 0xFE00707F, .ZBB, {rv64_only=true} }, + { .RORW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000503B, 0xFE00707F, .ZBB, {rv64_only=true} }, { .FMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000043, 0x0600007F, .F, {fp_round=true} }, { .FMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000043, 0x0600007F, .D, {fp_round=true} }, + { .FMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000043, 0x0600007F, .ZFH, {fp_round=true} }, { .FMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000047, 0x0600007F, .F, {fp_round=true} }, { .FMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000047, 0x0600007F, .D, {fp_round=true} }, + { .FMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000047, 0x0600007F, .ZFH, {fp_round=true} }, { .FNMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004B, 0x0600007F, .F, {fp_round=true} }, { .FNMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004B, 0x0600007F, .D, {fp_round=true} }, + { .FNMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004B, 0x0600007F, .ZFH, {fp_round=true} }, { .FNMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004F, 0x0600007F, .F, {fp_round=true} }, { .FNMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004F, 0x0600007F, .D, {fp_round=true} }, + { .FNMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004F, 0x0600007F, .ZFH, {fp_round=true} }, { .FADD_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000053, 0xFE00007F, .F, {fp_round=true} }, { .FADD_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02000053, 0xFE00007F, .D, {fp_round=true} }, + { .FADD_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x04000053, 0xFE00007F, .ZFH, {fp_round=true} }, { .FSUB_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x08000053, 0xFE00007F, .F, {fp_round=true} }, { .FSUB_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A000053, 0xFE00007F, .D, {fp_round=true} }, + { .FSUB_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0C000053, 0xFE00007F, .ZFH, {fp_round=true} }, { .FMUL_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x10000053, 0xFE00007F, .F, {fp_round=true} }, { .FMUL_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x12000053, 0xFE00007F, .D, {fp_round=true} }, + { .FMUL_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x14000053, 0xFE00007F, .ZFH, {fp_round=true} }, { .FDIV_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x18000053, 0xFE00007F, .F, {fp_round=true} }, { .FDIV_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1A000053, 0xFE00007F, .D, {fp_round=true} }, + { .FDIV_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1C000053, 0xFE00007F, .ZFH, {fp_round=true} }, { .FSGNJ_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20000053, 0xFE00707F, .F, {} }, { .FSGNJN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20001053, 0xFE00707F, .F, {} }, { .FSGNJX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002053, 0xFE00707F, .F, {} }, { .FSGNJ_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22000053, 0xFE00707F, .D, {} }, { .FSGNJN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22001053, 0xFE00707F, .D, {} }, { .FSGNJX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22002053, 0xFE00707F, .D, {} }, + { .FSGNJ_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24000053, 0xFE00707F, .ZFH, {} }, + { .FSGNJN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24001053, 0xFE00707F, .ZFH, {} }, + { .FSGNJX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24002053, 0xFE00707F, .ZFH, {} }, { .FMIN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28000053, 0xFE00707F, .F, {} }, { .FMAX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001053, 0xFE00707F, .F, {} }, { .FMIN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A000053, 0xFE00707F, .D, {} }, { .FMAX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A001053, 0xFE00707F, .D, {} }, + { .FMIN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C000053, 0xFE00707F, .ZFH, {} }, + { .FMAX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C001053, 0xFE00707F, .ZFH, {} }, { .FCVT_S_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40100053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_S_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40200053, 0xFFF0007F, .ZFH, {fp_round=true} }, { .FCVT_D_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_D_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42200053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_H_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44000053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_H_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44100053, 0xFFF0007F, .ZFH, {fp_round=true} }, { .FSQRT_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x58000053, 0xFFF0007F, .F, {fp_round=true} }, { .FSQRT_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5A000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FSQRT_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5C000053, 0xFFF0007F, .ZFH, {fp_round=true} }, { .FEQ_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0002053, 0xFE00707F, .F, {} }, { .FLT_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0001053, 0xFE00707F, .F, {} }, { .FLE_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0000053, 0xFE00707F, .F, {} }, { .FEQ_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2002053, 0xFE00707F, .D, {} }, { .FLT_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2001053, 0xFE00707F, .D, {} }, { .FLE_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2000053, 0xFE00707F, .D, {} }, + { .FEQ_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4002053, 0xFE00707F, .ZFH, {} }, + { .FLT_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4001053, 0xFE00707F, .ZFH, {} }, + { .FLE_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4000053, 0xFE00707F, .ZFH, {} }, { .FCVT_W_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0000053, 0xFFF0007F, .F, {fp_round=true} }, { .FCVT_WU_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0100053, 0xFFF0007F, .F, {fp_round=true} }, { .FCVT_L_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, @@ -135,6 +205,10 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .FCVT_WU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2100053, 0xFFF0007F, .D, {fp_round=true} }, { .FCVT_L_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, { .FCVT_LU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_W_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4000053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_WU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4100053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_L_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4200053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true} }, + { .FCVT_LU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4300053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true} }, { .FCVT_S_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0000053, 0xFFF0007F, .F, {fp_round=true} }, { .FCVT_S_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0100053, 0xFFF0007F, .F, {fp_round=true} }, { .FCVT_S_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, @@ -143,12 +217,19 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .FCVT_D_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2100053, 0xFFF0007F, .D, {fp_round=true} }, { .FCVT_D_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, { .FCVT_D_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_H_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4000053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_H_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4100053, 0xFFF0007F, .ZFH, {fp_round=true} }, + { .FCVT_H_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4200053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true} }, + { .FCVT_H_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4300053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true} }, { .FMV_X_W, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0000053, 0xFFF0707F, .F, {} }, { .FCLASS_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0001053, 0xFFF0707F, .F, {} }, { .FCLASS_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2001053, 0xFFF0707F, .D, {} }, { .FMV_X_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2000053, 0xFFF0707F, .D, {rv64_only=true} }, + { .FMV_X_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4000053, 0xFFF0707F, .ZFH, {} }, + { .FCLASS_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4001053, 0xFFF0707F, .ZFH, {} }, { .FMV_W_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF0000053, 0xFFF0707F, .F, {} }, { .FMV_D_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF2000053, 0xFFF0707F, .D, {rv64_only=true} }, + { .FMV_H_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF4000053, 0xFFF0707F, .ZFH, {} }, { .BEQ, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00000063, 0x0000707F, .I, {branch=true} }, { .BNE, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00001063, 0x0000707F, .I, {branch=true} }, { .BLT, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00004063, 0x0000707F, .I, {branch=true} }, @@ -159,6 +240,10 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ { .JAL, {.GPR,.REL21,.NONE,.NONE}, {.RD,.IMM_J,.NONE,.NONE}, 0x0000006F, 0x0000007F, .I, {branch=true} }, { .ECALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000073, 0xFFFFFFFF, .I, {branch=true} }, { .EBREAK, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00100073, 0xFFFFFFFF, .I, {branch=true} }, + { .MRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x30200073, 0xFFFFFFFF, .PRIV, {branch=true} }, + { .SRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10200073, 0xFFFFFFFF, .PRIV, {branch=true} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10500073, 0xFFFFFFFF, .PRIV, {} }, + { .SFENCE_VMA, {.GPR,.GPR,.NONE,.NONE}, {.RS1,.RS2,.NONE,.NONE}, 0x12000073, 0xFE007FFF, .PRIV, {} }, { .CSRRW, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00001073, 0x0000707F, .ZICSR, {} }, { .CSRRS, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00002073, 0x0000707F, .ZICSR, {} }, { .CSRRC, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00003073, 0x0000707F, .ZICSR, {} }, @@ -212,82 +297,95 @@ DECODE_ENTRIES := [198]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OPCODE := [128]lib.Decode_Index{ 0x03 = { 0, 7}, - 0x07 = { 7, 2}, - 0x0F = { 9, 2}, - 0x13 = { 11, 9}, - 0x17 = { 20, 1}, - 0x1B = { 21, 4}, - 0x23 = { 25, 4}, - 0x27 = { 29, 2}, - 0x2F = { 31, 22}, - 0x33 = { 53, 18}, - 0x37 = { 71, 1}, - 0x3B = { 72, 10}, - 0x43 = { 82, 2}, - 0x47 = { 84, 2}, - 0x4B = { 86, 2}, - 0x4F = { 88, 2}, - 0x53 = { 90, 50}, - 0x63 = { 140, 6}, - 0x67 = { 146, 1}, - 0x6F = { 147, 1}, - 0x73 = { 148, 8}, + 0x07 = { 7, 3}, + 0x0F = { 10, 2}, + 0x13 = { 12, 22}, + 0x17 = { 34, 1}, + 0x1B = { 35, 9}, + 0x23 = { 44, 4}, + 0x27 = { 48, 3}, + 0x2F = { 51, 22}, + 0x33 = { 73, 40}, + 0x37 = { 113, 1}, + 0x3B = { 114, 17}, + 0x43 = { 131, 3}, + 0x47 = { 134, 3}, + 0x4B = { 137, 3}, + 0x4F = { 140, 3}, + 0x53 = { 143, 78}, + 0x63 = { 221, 6}, + 0x67 = { 227, 1}, + 0x6F = { 228, 1}, + 0x73 = { 229, 12}, } @(rodata) DECODE_INDEX_OP_FP := [128]lib.Decode_Index{ - 0x00 = { 90, 1}, - 0x01 = { 91, 1}, - 0x04 = { 92, 1}, - 0x05 = { 93, 1}, - 0x08 = { 94, 1}, - 0x09 = { 95, 1}, - 0x0C = { 96, 1}, - 0x0D = { 97, 1}, - 0x10 = { 98, 3}, - 0x11 = { 101, 3}, - 0x14 = { 104, 2}, - 0x15 = { 106, 2}, - 0x20 = { 108, 1}, - 0x21 = { 109, 1}, - 0x2C = { 110, 1}, - 0x2D = { 111, 1}, - 0x50 = { 112, 3}, - 0x51 = { 115, 3}, - 0x60 = { 118, 4}, - 0x61 = { 122, 4}, - 0x68 = { 126, 4}, - 0x69 = { 130, 4}, - 0x70 = { 134, 2}, - 0x71 = { 136, 2}, - 0x78 = { 138, 1}, - 0x79 = { 139, 1}, + 0x00 = { 143, 1}, + 0x01 = { 144, 1}, + 0x02 = { 145, 1}, + 0x04 = { 146, 1}, + 0x05 = { 147, 1}, + 0x06 = { 148, 1}, + 0x08 = { 149, 1}, + 0x09 = { 150, 1}, + 0x0A = { 151, 1}, + 0x0C = { 152, 1}, + 0x0D = { 153, 1}, + 0x0E = { 154, 1}, + 0x10 = { 155, 3}, + 0x11 = { 158, 3}, + 0x12 = { 161, 3}, + 0x14 = { 164, 2}, + 0x15 = { 166, 2}, + 0x16 = { 168, 2}, + 0x20 = { 170, 2}, + 0x21 = { 172, 2}, + 0x22 = { 174, 2}, + 0x2C = { 176, 1}, + 0x2D = { 177, 1}, + 0x2E = { 178, 1}, + 0x50 = { 179, 3}, + 0x51 = { 182, 3}, + 0x52 = { 185, 3}, + 0x60 = { 188, 4}, + 0x61 = { 192, 4}, + 0x62 = { 196, 4}, + 0x68 = { 200, 4}, + 0x69 = { 204, 4}, + 0x6A = { 208, 4}, + 0x70 = { 212, 2}, + 0x71 = { 214, 2}, + 0x72 = { 216, 2}, + 0x78 = { 218, 1}, + 0x79 = { 219, 1}, + 0x7A = { 220, 1}, } @(rodata) DECODE_INDEX_RVC := [32]lib.Decode_Index{ - 0x00 = { 156, 1}, - 0x01 = { 157, 2}, - 0x02 = { 159, 1}, - 0x04 = { 160, 1}, - 0x05 = { 161, 2}, - 0x06 = { 163, 1}, - 0x08 = { 164, 1}, - 0x09 = { 165, 1}, - 0x0A = { 166, 1}, - 0x0C = { 167, 2}, - 0x0D = { 169, 2}, - 0x0E = { 171, 2}, - 0x11 = { 173, 9}, - 0x12 = { 182, 5}, - 0x14 = { 187, 1}, - 0x15 = { 188, 1}, - 0x16 = { 189, 1}, - 0x18 = { 190, 1}, - 0x19 = { 191, 1}, - 0x1A = { 192, 1}, - 0x1C = { 193, 2}, - 0x1D = { 195, 1}, - 0x1E = { 196, 2}, + 0x00 = { 241, 1}, + 0x01 = { 242, 2}, + 0x02 = { 244, 1}, + 0x04 = { 245, 1}, + 0x05 = { 246, 2}, + 0x06 = { 248, 1}, + 0x08 = { 249, 1}, + 0x09 = { 250, 1}, + 0x0A = { 251, 1}, + 0x0C = { 252, 2}, + 0x0D = { 254, 2}, + 0x0E = { 256, 2}, + 0x11 = { 258, 9}, + 0x12 = { 267, 5}, + 0x14 = { 272, 1}, + 0x15 = { 273, 1}, + 0x16 = { 274, 1}, + 0x18 = { 275, 1}, + 0x19 = { 276, 1}, + 0x1A = { 277, 1}, + 0x1C = { 278, 2}, + 0x1D = { 280, 1}, + 0x1E = { 281, 2}, } diff --git a/core/rexcode/isa/riscv/tablegen/generated/encode_tables.odin b/core/rexcode/isa/riscv/tablegen/generated/encode_tables.odin index 4bed4668a..d66ef1d02 100644 --- a/core/rexcode/isa/riscv/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/riscv/tablegen/generated/encode_tables.odin @@ -8,107 +8,107 @@ package rexcode_riscv_generated import lib "../.." @(rodata) -ENCODE_FORMS := [198]lib.Encoding{ +ENCODE_FORMS := [283]lib.Encoding{ // .LUI - { .LUI, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000037, 0x0000007F, .I, {} }, + { .LUI, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000037, 0x0000007F, .I, {explicit_count=2} }, // .AUIPC - { .AUIPC, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000017, 0x0000007F, .I, {} }, + { .AUIPC, {.GPR,.IMM20,.NONE,.NONE}, {.RD,.IMM_U,.NONE,.NONE}, 0x00000017, 0x0000007F, .I, {explicit_count=2} }, // .JAL - { .JAL, {.GPR,.REL21,.NONE,.NONE}, {.RD,.IMM_J,.NONE,.NONE}, 0x0000006F, 0x0000007F, .I, {branch=true} }, + { .JAL, {.GPR,.REL21,.NONE,.NONE}, {.RD,.IMM_J,.NONE,.NONE}, 0x0000006F, 0x0000007F, .I, {branch=true, explicit_count=2} }, // .JALR - { .JALR, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00000067, 0x0000707F, .I, {branch=true} }, + { .JALR, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00000067, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BEQ - { .BEQ, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00000063, 0x0000707F, .I, {branch=true} }, + { .BEQ, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00000063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BNE - { .BNE, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00001063, 0x0000707F, .I, {branch=true} }, + { .BNE, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00001063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BLT - { .BLT, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00004063, 0x0000707F, .I, {branch=true} }, + { .BLT, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00004063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BGE - { .BGE, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00005063, 0x0000707F, .I, {branch=true} }, + { .BGE, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00005063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BLTU - { .BLTU, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00006063, 0x0000707F, .I, {branch=true} }, + { .BLTU, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00006063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .BGEU - { .BGEU, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00007063, 0x0000707F, .I, {branch=true} }, + { .BGEU, {.GPR,.GPR,.REL13,.NONE}, {.RS1,.RS2,.IMM_B,.NONE}, 0x00007063, 0x0000707F, .I, {branch=true, explicit_count=3} }, // .LB - { .LB, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00000003, 0x0000707F, .I, {} }, + { .LB, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00000003, 0x0000707F, .I, {explicit_count=2} }, // .LH - { .LH, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001003, 0x0000707F, .I, {} }, + { .LH, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001003, 0x0000707F, .I, {explicit_count=2} }, // .LW - { .LW, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002003, 0x0000707F, .I, {} }, + { .LW, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002003, 0x0000707F, .I, {explicit_count=2} }, // .LBU - { .LBU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00004003, 0x0000707F, .I, {} }, + { .LBU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00004003, 0x0000707F, .I, {explicit_count=2} }, // .LHU - { .LHU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00005003, 0x0000707F, .I, {} }, + { .LHU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00005003, 0x0000707F, .I, {explicit_count=2} }, // .SB - { .SB, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00000023, 0x0000707F, .I, {} }, + { .SB, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00000023, 0x0000707F, .I, {explicit_count=2} }, // .SH - { .SH, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001023, 0x0000707F, .I, {} }, + { .SH, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001023, 0x0000707F, .I, {explicit_count=2} }, // .SW - { .SW, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00002023, 0x0000707F, .I, {} }, + { .SW, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00002023, 0x0000707F, .I, {explicit_count=2} }, // .LWU - { .LWU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00006003, 0x0000707F, .I, {rv64_only=true} }, + { .LWU, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00006003, 0x0000707F, .I, {rv64_only=true, explicit_count=2} }, // .LD - { .LD, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003003, 0x0000707F, .I, {rv64_only=true} }, + { .LD, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003003, 0x0000707F, .I, {rv64_only=true, explicit_count=2} }, // .SD - { .SD, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003023, 0x0000707F, .I, {rv64_only=true} }, + { .SD, {.GPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003023, 0x0000707F, .I, {rv64_only=true, explicit_count=2} }, // .ADDI - { .ADDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00000013, 0x0000707F, .I, {} }, + { .ADDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00000013, 0x0000707F, .I, {explicit_count=3} }, // .SLTI - { .SLTI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00002013, 0x0000707F, .I, {} }, + { .SLTI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00002013, 0x0000707F, .I, {explicit_count=3} }, // .SLTIU - { .SLTIU, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00003013, 0x0000707F, .I, {} }, + { .SLTIU, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00003013, 0x0000707F, .I, {explicit_count=3} }, // .XORI - { .XORI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00004013, 0x0000707F, .I, {} }, + { .XORI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00004013, 0x0000707F, .I, {explicit_count=3} }, // .ORI - { .ORI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00006013, 0x0000707F, .I, {} }, + { .ORI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00006013, 0x0000707F, .I, {explicit_count=3} }, // .ANDI - { .ANDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00007013, 0x0000707F, .I, {} }, + { .ANDI, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x00007013, 0x0000707F, .I, {explicit_count=3} }, // .SLLI - { .SLLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00001013, 0xFC00707F, .I, {} }, + { .SLLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00001013, 0xFC00707F, .I, {explicit_count=3} }, // .SRLI - { .SRLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00005013, 0xFC00707F, .I, {} }, + { .SRLI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x00005013, 0xFC00707F, .I, {explicit_count=3} }, // .SRAI - { .SRAI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x40005013, 0xFC00707F, .I, {} }, + { .SRAI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x40005013, 0xFC00707F, .I, {explicit_count=3} }, // .ADDIW - { .ADDIW, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x0000001B, 0x0000707F, .I, {rv64_only=true} }, + { .ADDIW, {.GPR,.GPR,.IMM12,.NONE}, {.RD,.RS1,.IMM_I,.NONE}, 0x0000001B, 0x0000707F, .I, {rv64_only=true, explicit_count=3} }, // .SLLIW - { .SLLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000101B, 0xFE00707F, .I, {rv64_only=true} }, + { .SLLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000101B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SRLIW - { .SRLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000501B, 0xFE00707F, .I, {rv64_only=true} }, + { .SRLIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x0000501B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SRAIW - { .SRAIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x4000501B, 0xFE00707F, .I, {rv64_only=true} }, + { .SRAIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x4000501B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .ADD - { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000033, 0xFE00707F, .I, {} }, + { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000033, 0xFE00707F, .I, {explicit_count=3} }, // .SUB - { .SUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40000033, 0xFE00707F, .I, {} }, + { .SUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40000033, 0xFE00707F, .I, {explicit_count=3} }, // .SLL - { .SLL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00001033, 0xFE00707F, .I, {} }, + { .SLL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00001033, 0xFE00707F, .I, {explicit_count=3} }, // .SLT - { .SLT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00002033, 0xFE00707F, .I, {} }, + { .SLT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00002033, 0xFE00707F, .I, {explicit_count=3} }, // .SLTU - { .SLTU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00003033, 0xFE00707F, .I, {} }, + { .SLTU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00003033, 0xFE00707F, .I, {explicit_count=3} }, // .XOR - { .XOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00004033, 0xFE00707F, .I, {} }, + { .XOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00004033, 0xFE00707F, .I, {explicit_count=3} }, // .SRL - { .SRL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00005033, 0xFE00707F, .I, {} }, + { .SRL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00005033, 0xFE00707F, .I, {explicit_count=3} }, // .SRA - { .SRA, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40005033, 0xFE00707F, .I, {} }, + { .SRA, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40005033, 0xFE00707F, .I, {explicit_count=3} }, // .OR - { .OR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00006033, 0xFE00707F, .I, {} }, + { .OR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00006033, 0xFE00707F, .I, {explicit_count=3} }, // .AND - { .AND, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00007033, 0xFE00707F, .I, {} }, + { .AND, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00007033, 0xFE00707F, .I, {explicit_count=3} }, // .ADDW - { .ADDW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000003B, 0xFE00707F, .I, {rv64_only=true} }, + { .ADDW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000003B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SUBW - { .SUBW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x4000003B, 0xFE00707F, .I, {rv64_only=true} }, + { .SUBW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x4000003B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SLLW - { .SLLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000103B, 0xFE00707F, .I, {rv64_only=true} }, + { .SLLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000103B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SRLW - { .SRLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000503B, 0xFE00707F, .I, {rv64_only=true} }, + { .SRLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0000503B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .SRAW - { .SRAW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x4000503B, 0xFE00707F, .I, {rv64_only=true} }, + { .SRAW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x4000503B, 0xFE00707F, .I, {rv64_only=true, explicit_count=3} }, // .FENCE - { .FENCE, {.FENCE_FLAGS,.FENCE_FLAGS,.NONE,.NONE}, {.FENCE_PRED,.FENCE_SUCC,.NONE,.NONE}, 0x0000000F, 0x0000707F, .I, {} }, + { .FENCE, {.FENCE_FLAGS,.FENCE_FLAGS,.NONE,.NONE}, {.FENCE_PRED,.FENCE_SUCC,.NONE,.NONE}, 0x0000000F, 0x0000707F, .I, {explicit_count=2} }, // .FENCE_I { .FENCE_I, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000100F, 0xFFFFFFFF, .ZIFENCEI, {} }, // .ECALL @@ -116,299 +116,467 @@ ENCODE_FORMS := [198]lib.Encoding{ // .EBREAK { .EBREAK, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00100073, 0xFFFFFFFF, .I, {branch=true} }, // .CSRRW - { .CSRRW, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00001073, 0x0000707F, .ZICSR, {} }, + { .CSRRW, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00001073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .CSRRS - { .CSRRS, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00002073, 0x0000707F, .ZICSR, {} }, + { .CSRRS, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00002073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .CSRRC - { .CSRRC, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00003073, 0x0000707F, .ZICSR, {} }, + { .CSRRC, {.GPR,.CSR,.GPR,.NONE}, {.RD,.CSR_FIELD,.RS1,.NONE}, 0x00003073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .CSRRWI - { .CSRRWI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00005073, 0x0000707F, .ZICSR, {} }, + { .CSRRWI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00005073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .CSRRSI - { .CSRRSI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00006073, 0x0000707F, .ZICSR, {} }, + { .CSRRSI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00006073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .CSRRCI - { .CSRRCI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00007073, 0x0000707F, .ZICSR, {} }, + { .CSRRCI, {.GPR,.CSR,.ZIMM5,.NONE}, {.RD,.CSR_FIELD,.ZIMM_FIELD,.NONE}, 0x00007073, 0x0000707F, .ZICSR, {explicit_count=3} }, // .MUL - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02000033, 0xFE00707F, .M, {} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02000033, 0xFE00707F, .M, {explicit_count=3} }, // .MULH - { .MULH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02001033, 0xFE00707F, .M, {} }, + { .MULH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02001033, 0xFE00707F, .M, {explicit_count=3} }, // .MULHSU - { .MULHSU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02002033, 0xFE00707F, .M, {} }, + { .MULHSU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02002033, 0xFE00707F, .M, {explicit_count=3} }, // .MULHU - { .MULHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02003033, 0xFE00707F, .M, {} }, + { .MULHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02003033, 0xFE00707F, .M, {explicit_count=3} }, // .DIV - { .DIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02004033, 0xFE00707F, .M, {} }, + { .DIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02004033, 0xFE00707F, .M, {explicit_count=3} }, // .DIVU - { .DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02005033, 0xFE00707F, .M, {} }, + { .DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02005033, 0xFE00707F, .M, {explicit_count=3} }, // .REM - { .REM, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02006033, 0xFE00707F, .M, {} }, + { .REM, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02006033, 0xFE00707F, .M, {explicit_count=3} }, // .REMU - { .REMU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02007033, 0xFE00707F, .M, {} }, + { .REMU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02007033, 0xFE00707F, .M, {explicit_count=3} }, // .MULW - { .MULW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200003B, 0xFE00707F, .M, {rv64_only=true} }, + { .MULW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200003B, 0xFE00707F, .M, {rv64_only=true, explicit_count=3} }, // .DIVW - { .DIVW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200403B, 0xFE00707F, .M, {rv64_only=true} }, + { .DIVW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200403B, 0xFE00707F, .M, {rv64_only=true, explicit_count=3} }, // .DIVUW - { .DIVUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200503B, 0xFE00707F, .M, {rv64_only=true} }, + { .DIVUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200503B, 0xFE00707F, .M, {rv64_only=true, explicit_count=3} }, // .REMW - { .REMW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200603B, 0xFE00707F, .M, {rv64_only=true} }, + { .REMW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200603B, 0xFE00707F, .M, {rv64_only=true, explicit_count=3} }, // .REMUW - { .REMUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200703B, 0xFE00707F, .M, {rv64_only=true} }, + { .REMUW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0200703B, 0xFE00707F, .M, {rv64_only=true, explicit_count=3} }, // .LR_W - { .LR_W, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000202F, 0xF9F0707F, .A, {} }, + { .LR_W, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000202F, 0xF9F0707F, .A, {explicit_count=2} }, // .SC_W - { .SC_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x1800202F, 0xF800707F, .A, {} }, + { .SC_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x1800202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOSWAP_W - { .AMOSWAP_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0800202F, 0xF800707F, .A, {} }, + { .AMOSWAP_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0800202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOADD_W - { .AMOADD_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0000202F, 0xF800707F, .A, {} }, + { .AMOADD_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOXOR_W - { .AMOXOR_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x2000202F, 0xF800707F, .A, {} }, + { .AMOXOR_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x2000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOAND_W - { .AMOAND_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x6000202F, 0xF800707F, .A, {} }, + { .AMOAND_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x6000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOOR_W - { .AMOOR_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x4000202F, 0xF800707F, .A, {} }, + { .AMOOR_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x4000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOMIN_W - { .AMOMIN_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x8000202F, 0xF800707F, .A, {} }, + { .AMOMIN_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x8000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOMAX_W - { .AMOMAX_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xA000202F, 0xF800707F, .A, {} }, + { .AMOMAX_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xA000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOMINU_W - { .AMOMINU_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xC000202F, 0xF800707F, .A, {} }, + { .AMOMINU_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xC000202F, 0xF800707F, .A, {explicit_count=3} }, // .AMOMAXU_W - { .AMOMAXU_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xE000202F, 0xF800707F, .A, {} }, + { .AMOMAXU_W, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xE000202F, 0xF800707F, .A, {explicit_count=3} }, // .LR_D - { .LR_D, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000302F, 0xF9F0707F, .A, {rv64_only=true} }, + { .LR_D, {.GPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_A,.NONE,.NONE}, 0x1000302F, 0xF9F0707F, .A, {rv64_only=true, explicit_count=2} }, // .SC_D - { .SC_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x1800302F, 0xF800707F, .A, {rv64_only=true} }, + { .SC_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x1800302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOSWAP_D - { .AMOSWAP_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0800302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOSWAP_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0800302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOADD_D - { .AMOADD_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOADD_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x0000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOXOR_D - { .AMOXOR_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x2000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOXOR_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x2000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOAND_D - { .AMOAND_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x6000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOAND_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x6000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOOR_D - { .AMOOR_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x4000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOOR_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x4000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOMIN_D - { .AMOMIN_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x8000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOMIN_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0x8000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOMAX_D - { .AMOMAX_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xA000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOMAX_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xA000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOMINU_D - { .AMOMINU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xC000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOMINU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xC000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .AMOMAXU_D - { .AMOMAXU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xE000302F, 0xF800707F, .A, {rv64_only=true} }, + { .AMOMAXU_D, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RS2,.OFFSET_BASE_A,.NONE}, 0xE000302F, 0xF800707F, .A, {rv64_only=true, explicit_count=3} }, // .FLW - { .FLW, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002007, 0x0000707F, .F, {} }, + { .FLW, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00002007, 0x0000707F, .F, {explicit_count=2} }, // .FSW - { .FSW, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00002027, 0x0000707F, .F, {} }, + { .FSW, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00002027, 0x0000707F, .F, {explicit_count=2} }, // .FMADD_S - { .FMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000043, 0x0600007F, .F, {fp_round=true} }, + { .FMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000043, 0x0600007F, .F, {fp_round=true, explicit_count=4} }, // .FMSUB_S - { .FMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000047, 0x0600007F, .F, {fp_round=true} }, + { .FMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x00000047, 0x0600007F, .F, {fp_round=true, explicit_count=4} }, // .FNMSUB_S - { .FNMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004B, 0x0600007F, .F, {fp_round=true} }, + { .FNMSUB_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004B, 0x0600007F, .F, {fp_round=true, explicit_count=4} }, // .FNMADD_S - { .FNMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004F, 0x0600007F, .F, {fp_round=true} }, + { .FNMADD_S, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0000004F, 0x0600007F, .F, {fp_round=true, explicit_count=4} }, // .FADD_S - { .FADD_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000053, 0xFE00007F, .F, {fp_round=true} }, + { .FADD_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x00000053, 0xFE00007F, .F, {fp_round=true, explicit_count=3} }, // .FSUB_S - { .FSUB_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x08000053, 0xFE00007F, .F, {fp_round=true} }, + { .FSUB_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x08000053, 0xFE00007F, .F, {fp_round=true, explicit_count=3} }, // .FMUL_S - { .FMUL_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x10000053, 0xFE00007F, .F, {fp_round=true} }, + { .FMUL_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x10000053, 0xFE00007F, .F, {fp_round=true, explicit_count=3} }, // .FDIV_S - { .FDIV_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x18000053, 0xFE00007F, .F, {fp_round=true} }, + { .FDIV_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x18000053, 0xFE00007F, .F, {fp_round=true, explicit_count=3} }, // .FSQRT_S - { .FSQRT_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x58000053, 0xFFF0007F, .F, {fp_round=true} }, + { .FSQRT_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x58000053, 0xFFF0007F, .F, {fp_round=true, explicit_count=2} }, // .FSGNJ_S - { .FSGNJ_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20000053, 0xFE00707F, .F, {} }, + { .FSGNJ_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20000053, 0xFE00707F, .F, {explicit_count=3} }, // .FSGNJN_S - { .FSGNJN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20001053, 0xFE00707F, .F, {} }, + { .FSGNJN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20001053, 0xFE00707F, .F, {explicit_count=3} }, // .FSGNJX_S - { .FSGNJX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002053, 0xFE00707F, .F, {} }, + { .FSGNJX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002053, 0xFE00707F, .F, {explicit_count=3} }, // .FMIN_S - { .FMIN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28000053, 0xFE00707F, .F, {} }, + { .FMIN_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28000053, 0xFE00707F, .F, {explicit_count=3} }, // .FMAX_S - { .FMAX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001053, 0xFE00707F, .F, {} }, + { .FMAX_S, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001053, 0xFE00707F, .F, {explicit_count=3} }, // .FCVT_W_S - { .FCVT_W_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0000053, 0xFFF0007F, .F, {fp_round=true} }, + { .FCVT_W_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0000053, 0xFFF0007F, .F, {fp_round=true, explicit_count=2} }, // .FCVT_WU_S - { .FCVT_WU_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0100053, 0xFFF0007F, .F, {fp_round=true} }, + { .FCVT_WU_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0100053, 0xFFF0007F, .F, {fp_round=true, explicit_count=2} }, // .FMV_X_W - { .FMV_X_W, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0000053, 0xFFF0707F, .F, {} }, + { .FMV_X_W, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0000053, 0xFFF0707F, .F, {explicit_count=2} }, // .FEQ_S - { .FEQ_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0002053, 0xFE00707F, .F, {} }, + { .FEQ_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0002053, 0xFE00707F, .F, {explicit_count=3} }, // .FLT_S - { .FLT_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0001053, 0xFE00707F, .F, {} }, + { .FLT_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0001053, 0xFE00707F, .F, {explicit_count=3} }, // .FLE_S - { .FLE_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0000053, 0xFE00707F, .F, {} }, + { .FLE_S, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA0000053, 0xFE00707F, .F, {explicit_count=3} }, // .FCLASS_S - { .FCLASS_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0001053, 0xFFF0707F, .F, {} }, + { .FCLASS_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE0001053, 0xFFF0707F, .F, {explicit_count=2} }, // .FCVT_S_W - { .FCVT_S_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0000053, 0xFFF0007F, .F, {fp_round=true} }, + { .FCVT_S_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0000053, 0xFFF0007F, .F, {fp_round=true, explicit_count=2} }, // .FCVT_S_WU - { .FCVT_S_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0100053, 0xFFF0007F, .F, {fp_round=true} }, + { .FCVT_S_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0100053, 0xFFF0007F, .F, {fp_round=true, explicit_count=2} }, // .FMV_W_X - { .FMV_W_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF0000053, 0xFFF0707F, .F, {} }, + { .FMV_W_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF0000053, 0xFFF0707F, .F, {explicit_count=2} }, // .FCVT_L_S - { .FCVT_L_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, + { .FCVT_L_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_LU_S - { .FCVT_LU_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, + { .FCVT_LU_S, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_S_L - { .FCVT_S_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, + { .FCVT_S_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0200053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_S_LU - { .FCVT_S_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true} }, + { .FCVT_S_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD0300053, 0xFFF0007F, .F, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FLD - { .FLD, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003007, 0x0000707F, .D, {} }, + { .FLD, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00003007, 0x0000707F, .D, {explicit_count=2} }, // .FSD - { .FSD, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003027, 0x0000707F, .D, {} }, + { .FSD, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00003027, 0x0000707F, .D, {explicit_count=2} }, // .FMADD_D - { .FMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000043, 0x0600007F, .D, {fp_round=true} }, + { .FMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000043, 0x0600007F, .D, {fp_round=true, explicit_count=4} }, // .FMSUB_D - { .FMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000047, 0x0600007F, .D, {fp_round=true} }, + { .FMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x02000047, 0x0600007F, .D, {fp_round=true, explicit_count=4} }, // .FNMSUB_D - { .FNMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004B, 0x0600007F, .D, {fp_round=true} }, + { .FNMSUB_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004B, 0x0600007F, .D, {fp_round=true, explicit_count=4} }, // .FNMADD_D - { .FNMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004F, 0x0600007F, .D, {fp_round=true} }, + { .FNMADD_D, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0200004F, 0x0600007F, .D, {fp_round=true, explicit_count=4} }, // .FADD_D - { .FADD_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02000053, 0xFE00007F, .D, {fp_round=true} }, + { .FADD_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x02000053, 0xFE00007F, .D, {fp_round=true, explicit_count=3} }, // .FSUB_D - { .FSUB_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A000053, 0xFE00007F, .D, {fp_round=true} }, + { .FSUB_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A000053, 0xFE00007F, .D, {fp_round=true, explicit_count=3} }, // .FMUL_D - { .FMUL_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x12000053, 0xFE00007F, .D, {fp_round=true} }, + { .FMUL_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x12000053, 0xFE00007F, .D, {fp_round=true, explicit_count=3} }, // .FDIV_D - { .FDIV_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1A000053, 0xFE00007F, .D, {fp_round=true} }, + { .FDIV_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1A000053, 0xFE00007F, .D, {fp_round=true, explicit_count=3} }, // .FSQRT_D - { .FSQRT_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5A000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FSQRT_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5A000053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FSGNJ_D - { .FSGNJ_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22000053, 0xFE00707F, .D, {} }, + { .FSGNJ_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22000053, 0xFE00707F, .D, {explicit_count=3} }, // .FSGNJN_D - { .FSGNJN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22001053, 0xFE00707F, .D, {} }, + { .FSGNJN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22001053, 0xFE00707F, .D, {explicit_count=3} }, // .FSGNJX_D - { .FSGNJX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22002053, 0xFE00707F, .D, {} }, + { .FSGNJX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x22002053, 0xFE00707F, .D, {explicit_count=3} }, // .FMIN_D - { .FMIN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A000053, 0xFE00707F, .D, {} }, + { .FMIN_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A000053, 0xFE00707F, .D, {explicit_count=3} }, // .FMAX_D - { .FMAX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A001053, 0xFE00707F, .D, {} }, + { .FMAX_D, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2A001053, 0xFE00707F, .D, {explicit_count=3} }, // .FCVT_S_D - { .FCVT_S_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40100053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_S_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40100053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FCVT_D_S - { .FCVT_D_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_D_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42000053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FEQ_D - { .FEQ_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2002053, 0xFE00707F, .D, {} }, + { .FEQ_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2002053, 0xFE00707F, .D, {explicit_count=3} }, // .FLT_D - { .FLT_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2001053, 0xFE00707F, .D, {} }, + { .FLT_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2001053, 0xFE00707F, .D, {explicit_count=3} }, // .FLE_D - { .FLE_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2000053, 0xFE00707F, .D, {} }, + { .FLE_D, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA2000053, 0xFE00707F, .D, {explicit_count=3} }, // .FCLASS_D - { .FCLASS_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2001053, 0xFFF0707F, .D, {} }, + { .FCLASS_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2001053, 0xFFF0707F, .D, {explicit_count=2} }, // .FCVT_W_D - { .FCVT_W_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_W_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2000053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FCVT_WU_D - { .FCVT_WU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2100053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_WU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2100053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FCVT_D_W - { .FCVT_D_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2000053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_D_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2000053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FCVT_D_WU - { .FCVT_D_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2100053, 0xFFF0007F, .D, {fp_round=true} }, + { .FCVT_D_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2100053, 0xFFF0007F, .D, {fp_round=true, explicit_count=2} }, // .FCVT_L_D - { .FCVT_L_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_L_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_LU_D - { .FCVT_LU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_LU_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_D_L - { .FCVT_D_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_D_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2200053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FCVT_D_LU - { .FCVT_D_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true} }, + { .FCVT_D_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD2300053, 0xFFF0007F, .D, {rv64_only=true, fp_round=true, explicit_count=2} }, // .FMV_X_D - { .FMV_X_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2000053, 0xFFF0707F, .D, {rv64_only=true} }, + { .FMV_X_D, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE2000053, 0xFFF0707F, .D, {rv64_only=true, explicit_count=2} }, // .FMV_D_X - { .FMV_D_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF2000053, 0xFFF0707F, .D, {rv64_only=true} }, + { .FMV_D_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF2000053, 0xFFF0707F, .D, {rv64_only=true, explicit_count=2} }, // .C_NOP { .C_NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000001, 0x0000FFFF, .C, {} }, // .C_EBREAK { .C_EBREAK, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00009002, 0x0000FFFF, .C, {} }, // .C_ADDI4SPN - { .C_ADDI4SPN, {.GPR_C,.GPR_SP,.IMM_C8U,.NONE}, {.C_RD_PRIMED,.NONE,.C_IMM_CIW,.NONE}, 0x00000000, 0x0000E003, .C, {} }, + { .C_ADDI4SPN, {.GPR_C,.GPR_SP,.IMM_C8U,.NONE}, {.C_RD_PRIMED,.NONE,.C_IMM_CIW,.NONE}, 0x00000000, 0x0000E003, .C, {explicit_count=2, has_implicit=true} }, // .C_LW - { .C_LW, {.GPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x00004000, 0x0000E003, .C, {} }, + { .C_LW, {.GPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x00004000, 0x0000E003, .C, {explicit_count=2} }, // .C_LD - { .C_LD, {.GPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x00006000, 0x0000E003, .C, {rv64_only=true} }, + { .C_LD, {.GPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x00006000, 0x0000E003, .C, {rv64_only=true, explicit_count=2} }, // .C_SW - { .C_SW, {.GPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x0000C000, 0x0000E003, .C, {} }, + { .C_SW, {.GPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x0000C000, 0x0000E003, .C, {explicit_count=2} }, // .C_SD - { .C_SD, {.GPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x0000E000, 0x0000E003, .C, {rv64_only=true} }, + { .C_SD, {.GPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x0000E000, 0x0000E003, .C, {rv64_only=true, explicit_count=2} }, // .C_FLW - { .C_FLW, {.FPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x00006000, 0x0000E003, .F, {rv32_only=true} }, + { .C_FLW, {.FPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x00006000, 0x0000E003, .F, {rv32_only=true, explicit_count=2} }, // .C_FSW - { .C_FSW, {.FPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x0000E000, 0x0000E003, .F, {rv32_only=true} }, + { .C_FSW, {.FPR_C,.MEM_C_W,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_W,.NONE,.NONE}, 0x0000E000, 0x0000E003, .F, {rv32_only=true, explicit_count=2} }, // .C_FLD - { .C_FLD, {.FPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x00002000, 0x0000E003, .D, {} }, + { .C_FLD, {.FPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RD_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x00002000, 0x0000E003, .D, {explicit_count=2} }, // .C_FSD - { .C_FSD, {.FPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x0000A000, 0x0000E003, .D, {} }, + { .C_FSD, {.FPR_C,.MEM_C_D,.NONE,.NONE}, {.C_RS2_PRIMED,.C_OFFSET_BASE_D,.NONE,.NONE}, 0x0000A000, 0x0000E003, .D, {explicit_count=2} }, // .C_ADDI - { .C_ADDI, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00000001, 0x0000E003, .C, {} }, + { .C_ADDI, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00000001, 0x0000E003, .C, {explicit_count=2} }, // .C_ADDIW - { .C_ADDIW, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00002001, 0x0000E003, .C, {rv64_only=true} }, + { .C_ADDIW, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00002001, 0x0000E003, .C, {rv64_only=true, explicit_count=2} }, // .C_LI - { .C_LI, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00004001, 0x0000E003, .C, {} }, + { .C_LI, {.GPR_NONZERO,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_S,.NONE,.NONE}, 0x00004001, 0x0000E003, .C, {explicit_count=2} }, // .C_LUI - { .C_LUI, {.GPR_NONZERO,.IMM_C18S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_LUI,.NONE,.NONE}, 0x00006001, 0x0000E003, .C, {} }, + { .C_LUI, {.GPR_NONZERO,.IMM_C18S,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_LUI,.NONE,.NONE}, 0x00006001, 0x0000E003, .C, {explicit_count=2} }, // .C_ADDI16SP - { .C_ADDI16SP, {.GPR_SP,.IMM_C10S,.NONE,.NONE}, {.NONE,.C_IMM_ADDI16SP,.NONE,.NONE}, 0x00006101, 0x0000EF83, .C, {} }, + { .C_ADDI16SP, {.GPR_SP,.IMM_C10S,.NONE,.NONE}, {.NONE,.C_IMM_ADDI16SP,.NONE,.NONE}, 0x00006101, 0x0000EF83, .C, {explicit_count=1, has_implicit=true} }, // .C_SRLI - { .C_SRLI, {.GPR_C,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_U,.NONE,.NONE}, 0x00008001, 0x0000EC03, .C, {} }, + { .C_SRLI, {.GPR_C,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_U,.NONE,.NONE}, 0x00008001, 0x0000EC03, .C, {explicit_count=2} }, // .C_SRAI - { .C_SRAI, {.GPR_C,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_U,.NONE,.NONE}, 0x00008401, 0x0000EC03, .C, {} }, + { .C_SRAI, {.GPR_C,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_U,.NONE,.NONE}, 0x00008401, 0x0000EC03, .C, {explicit_count=2} }, // .C_ANDI - { .C_ANDI, {.GPR_C,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_S,.NONE,.NONE}, 0x00008801, 0x0000EC03, .C, {} }, + { .C_ANDI, {.GPR_C,.IMM_C6S,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_IMM_CI_S,.NONE,.NONE}, 0x00008801, 0x0000EC03, .C, {explicit_count=2} }, // .C_SUB - { .C_SUB, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C01, 0x0000FC63, .C, {} }, + { .C_SUB, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C01, 0x0000FC63, .C, {explicit_count=2} }, // .C_XOR - { .C_XOR, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C21, 0x0000FC63, .C, {} }, + { .C_XOR, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C21, 0x0000FC63, .C, {explicit_count=2} }, // .C_OR - { .C_OR, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C41, 0x0000FC63, .C, {} }, + { .C_OR, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C41, 0x0000FC63, .C, {explicit_count=2} }, // .C_AND - { .C_AND, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C61, 0x0000FC63, .C, {} }, + { .C_AND, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00008C61, 0x0000FC63, .C, {explicit_count=2} }, // .C_SUBW - { .C_SUBW, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00009C01, 0x0000FC63, .C, {rv64_only=true} }, + { .C_SUBW, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00009C01, 0x0000FC63, .C, {rv64_only=true, explicit_count=2} }, // .C_ADDW - { .C_ADDW, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00009C21, 0x0000FC63, .C, {rv64_only=true} }, + { .C_ADDW, {.GPR_C,.GPR_C,.NONE,.NONE}, {.C_RD_RS1_PRIMED,.C_RS2_PRIMED,.NONE,.NONE}, 0x00009C21, 0x0000FC63, .C, {rv64_only=true, explicit_count=2} }, // .C_J - { .C_J, {.REL12,.NONE,.NONE,.NONE}, {.C_BRANCH12,.NONE,.NONE,.NONE}, 0x0000A001, 0x0000E003, .C, {branch=true} }, + { .C_J, {.REL12,.NONE,.NONE,.NONE}, {.C_BRANCH12,.NONE,.NONE,.NONE}, 0x0000A001, 0x0000E003, .C, {branch=true, explicit_count=1} }, // .C_JAL - { .C_JAL, {.REL12,.NONE,.NONE,.NONE}, {.C_BRANCH12,.NONE,.NONE,.NONE}, 0x00002001, 0x0000E003, .C, {rv32_only=true, branch=true} }, + { .C_JAL, {.REL12,.NONE,.NONE,.NONE}, {.C_BRANCH12,.NONE,.NONE,.NONE}, 0x00002001, 0x0000E003, .C, {rv32_only=true, branch=true, explicit_count=1} }, // .C_BEQZ - { .C_BEQZ, {.GPR_C,.REL9,.NONE,.NONE}, {.C_RS1_PRIMED,.C_BRANCH9,.NONE,.NONE}, 0x0000C001, 0x0000E003, .C, {branch=true} }, + { .C_BEQZ, {.GPR_C,.REL9,.NONE,.NONE}, {.C_RS1_PRIMED,.C_BRANCH9,.NONE,.NONE}, 0x0000C001, 0x0000E003, .C, {branch=true, explicit_count=2} }, // .C_BNEZ - { .C_BNEZ, {.GPR_C,.REL9,.NONE,.NONE}, {.C_RS1_PRIMED,.C_BRANCH9,.NONE,.NONE}, 0x0000E001, 0x0000E003, .C, {branch=true} }, + { .C_BNEZ, {.GPR_C,.REL9,.NONE,.NONE}, {.C_RS1_PRIMED,.C_BRANCH9,.NONE,.NONE}, 0x0000E001, 0x0000E003, .C, {branch=true, explicit_count=2} }, // .C_SLLI - { .C_SLLI, {.GPR_NONZERO,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_U,.NONE,.NONE}, 0x00000002, 0x0000E003, .C, {} }, + { .C_SLLI, {.GPR_NONZERO,.IMM_C6U,.NONE,.NONE}, {.C_RD_RS1,.C_IMM_CI_U,.NONE,.NONE}, 0x00000002, 0x0000E003, .C, {explicit_count=2} }, // .C_LWSP - { .C_LWSP, {.GPR_NONZERO,.MEM_C_SP_W,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_W,.NONE,.NONE}, 0x00004002, 0x0000E003, .C, {} }, + { .C_LWSP, {.GPR_NONZERO,.MEM_C_SP_W,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_W,.NONE,.NONE}, 0x00004002, 0x0000E003, .C, {explicit_count=2} }, // .C_LDSP - { .C_LDSP, {.GPR_NONZERO,.MEM_C_SP_D,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_D,.NONE,.NONE}, 0x00006002, 0x0000E003, .C, {rv64_only=true} }, + { .C_LDSP, {.GPR_NONZERO,.MEM_C_SP_D,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_D,.NONE,.NONE}, 0x00006002, 0x0000E003, .C, {rv64_only=true, explicit_count=2} }, // .C_SWSP - { .C_SWSP, {.GPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_W,.NONE,.NONE}, 0x0000C002, 0x0000E003, .C, {} }, + { .C_SWSP, {.GPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_W,.NONE,.NONE}, 0x0000C002, 0x0000E003, .C, {explicit_count=2} }, // .C_SDSP - { .C_SDSP, {.GPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_D,.NONE,.NONE}, 0x0000E002, 0x0000E003, .C, {rv64_only=true} }, + { .C_SDSP, {.GPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_D,.NONE,.NONE}, 0x0000E002, 0x0000E003, .C, {rv64_only=true, explicit_count=2} }, // .C_FLDSP - { .C_FLDSP, {.FPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_D,.NONE,.NONE}, 0x00002002, 0x0000E003, .D, {} }, + { .C_FLDSP, {.FPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_D,.NONE,.NONE}, 0x00002002, 0x0000E003, .D, {explicit_count=2} }, // .C_FSDSP - { .C_FSDSP, {.FPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_D,.NONE,.NONE}, 0x0000A002, 0x0000E003, .D, {} }, + { .C_FSDSP, {.FPR,.MEM_C_SP_D,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_D,.NONE,.NONE}, 0x0000A002, 0x0000E003, .D, {explicit_count=2} }, // .C_JR - { .C_JR, {.GPR_NONZERO,.NONE,.NONE,.NONE}, {.C_RD_RS1,.NONE,.NONE,.NONE}, 0x00008002, 0x0000F07F, .C, {branch=true} }, + { .C_JR, {.GPR_NONZERO,.NONE,.NONE,.NONE}, {.C_RD_RS1,.NONE,.NONE,.NONE}, 0x00008002, 0x0000F07F, .C, {branch=true, explicit_count=1} }, // .C_JALR - { .C_JALR, {.GPR_NONZERO,.NONE,.NONE,.NONE}, {.C_RD_RS1,.NONE,.NONE,.NONE}, 0x00009002, 0x0000F07F, .C, {branch=true} }, + { .C_JALR, {.GPR_NONZERO,.NONE,.NONE,.NONE}, {.C_RD_RS1,.NONE,.NONE,.NONE}, 0x00009002, 0x0000F07F, .C, {branch=true, explicit_count=1} }, // .C_MV - { .C_MV, {.GPR_NONZERO,.GPR_NONZERO,.NONE,.NONE}, {.C_RD_RS1,.C_RS2,.NONE,.NONE}, 0x00008002, 0x0000F003, .C, {} }, + { .C_MV, {.GPR_NONZERO,.GPR_NONZERO,.NONE,.NONE}, {.C_RD_RS1,.C_RS2,.NONE,.NONE}, 0x00008002, 0x0000F003, .C, {explicit_count=2} }, // .C_ADD - { .C_ADD, {.GPR_NONZERO,.GPR_NONZERO,.NONE,.NONE}, {.C_RD_RS1,.C_RS2,.NONE,.NONE}, 0x00009002, 0x0000F003, .C, {} }, + { .C_ADD, {.GPR_NONZERO,.GPR_NONZERO,.NONE,.NONE}, {.C_RD_RS1,.C_RS2,.NONE,.NONE}, 0x00009002, 0x0000F003, .C, {explicit_count=2} }, // .C_FLWSP - { .C_FLWSP, {.FPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_W,.NONE,.NONE}, 0x00006002, 0x0000E003, .F, {rv32_only=true} }, + { .C_FLWSP, {.FPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RD_RS1,.C_SP_OFFSET_W,.NONE,.NONE}, 0x00006002, 0x0000E003, .F, {rv32_only=true, explicit_count=2} }, // .C_FSWSP - { .C_FSWSP, {.FPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_W,.NONE,.NONE}, 0x0000E002, 0x0000E003, .F, {rv32_only=true} }, + { .C_FSWSP, {.FPR,.MEM_C_SP_W,.NONE,.NONE}, {.C_RS2,.C_IMM_CSS_W,.NONE,.NONE}, 0x0000E002, 0x0000E003, .F, {rv32_only=true, explicit_count=2} }, + // .SH1ADD + { .SH1ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002033, 0xFE00707F, .ZBA, {explicit_count=3} }, + // .SH2ADD + { .SH2ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20004033, 0xFE00707F, .ZBA, {explicit_count=3} }, + // .SH3ADD + { .SH3ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20006033, 0xFE00707F, .ZBA, {explicit_count=3} }, + // .ADD_UW + { .ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0800003B, 0xFE00707F, .ZBA, {rv64_only=true, explicit_count=3} }, + // .SH1ADD_UW + { .SH1ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000203B, 0xFE00707F, .ZBA, {rv64_only=true, explicit_count=3} }, + // .SH2ADD_UW + { .SH2ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000403B, 0xFE00707F, .ZBA, {rv64_only=true, explicit_count=3} }, + // .SH3ADD_UW + { .SH3ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000603B, 0xFE00707F, .ZBA, {rv64_only=true, explicit_count=3} }, + // .SLLI_UW + { .SLLI_UW, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x0800101B, 0xFC00707F, .ZBA, {rv64_only=true, explicit_count=3} }, + // .ANDN + { .ANDN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40007033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .ORN + { .ORN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40006033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .XNOR + { .XNOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40004033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .CLZ + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60001013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .CTZ + { .CTZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60101013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .CPOP + { .CPOP, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60201013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .SEXT_B + { .SEXT_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60401013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .SEXT_H + { .SEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60501013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .ZEXT_H + { .ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x08004033, 0xFFF0707F, .ZBB, {rv32_only=true, explicit_count=2} }, + { .ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x0800403B, 0xFFF0707F, .ZBB, {rv64_only=true, explicit_count=2} }, + // .MIN + { .MIN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A004033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .MINU + { .MINU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A005033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .MAX + { .MAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A006033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .MAXU + { .MAXU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A007033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .ROL + { .ROL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60001033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .ROR + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60005033, 0xFE00707F, .ZBB, {explicit_count=3} }, + // .RORI + { .RORI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x60005013, 0xFC00707F, .ZBB, {explicit_count=3} }, + // .ORC_B + { .ORC_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x28705013, 0xFFF0707F, .ZBB, {explicit_count=2} }, + // .REV8 + { .REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x69805013, 0xFFF0707F, .ZBB, {rv32_only=true, explicit_count=2} }, + { .REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6B805013, 0xFFF0707F, .ZBB, {rv64_only=true, explicit_count=2} }, + // .CLZW + { .CLZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6000101B, 0xFFF0707F, .ZBB, {rv64_only=true, explicit_count=2} }, + // .CTZW + { .CTZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6010101B, 0xFFF0707F, .ZBB, {rv64_only=true, explicit_count=2} }, + // .CPOPW + { .CPOPW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6020101B, 0xFFF0707F, .ZBB, {rv64_only=true, explicit_count=2} }, + // .ROLW + { .ROLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000103B, 0xFE00707F, .ZBB, {rv64_only=true, explicit_count=3} }, + // .RORW + { .RORW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000503B, 0xFE00707F, .ZBB, {rv64_only=true, explicit_count=3} }, + // .RORIW + { .RORIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x6000501B, 0xFE00707F, .ZBB, {rv64_only=true, explicit_count=3} }, + // .CLMUL + { .CLMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A001033, 0xFE00707F, .ZBC, {explicit_count=3} }, + // .CLMULH + { .CLMULH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A003033, 0xFE00707F, .ZBC, {explicit_count=3} }, + // .CLMULR + { .CLMULR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A002033, 0xFE00707F, .ZBC, {explicit_count=3} }, + // .BCLR + { .BCLR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48001033, 0xFE00707F, .ZBS, {explicit_count=3} }, + // .BCLRI + { .BCLRI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48001013, 0xFC00707F, .ZBS, {explicit_count=3} }, + // .BEXT + { .BEXT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48005033, 0xFE00707F, .ZBS, {explicit_count=3} }, + // .BEXTI + { .BEXTI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48005013, 0xFC00707F, .ZBS, {explicit_count=3} }, + // .BINV + { .BINV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x68001033, 0xFE00707F, .ZBS, {explicit_count=3} }, + // .BINVI + { .BINVI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x68001013, 0xFC00707F, .ZBS, {explicit_count=3} }, + // .BSET + { .BSET, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001033, 0xFE00707F, .ZBS, {explicit_count=3} }, + // .BSETI + { .BSETI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x28001013, 0xFC00707F, .ZBS, {explicit_count=3} }, + // .CZERO_EQZ + { .CZERO_EQZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E005033, 0xFE00707F, .ZICOND, {explicit_count=3} }, + // .CZERO_NEZ + { .CZERO_NEZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E007033, 0xFE00707F, .ZICOND, {explicit_count=3} }, + // .FLH + { .FLH, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001007, 0x0000707F, .ZFH, {explicit_count=2} }, + // .FSH + { .FSH, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001027, 0x0000707F, .ZFH, {explicit_count=2} }, + // .FMADD_H + { .FMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000043, 0x0600007F, .ZFH, {fp_round=true, explicit_count=4} }, + // .FMSUB_H + { .FMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000047, 0x0600007F, .ZFH, {fp_round=true, explicit_count=4} }, + // .FNMSUB_H + { .FNMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004B, 0x0600007F, .ZFH, {fp_round=true, explicit_count=4} }, + // .FNMADD_H + { .FNMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004F, 0x0600007F, .ZFH, {fp_round=true, explicit_count=4} }, + // .FADD_H + { .FADD_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x04000053, 0xFE00007F, .ZFH, {fp_round=true, explicit_count=3} }, + // .FSUB_H + { .FSUB_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0C000053, 0xFE00007F, .ZFH, {fp_round=true, explicit_count=3} }, + // .FMUL_H + { .FMUL_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x14000053, 0xFE00007F, .ZFH, {fp_round=true, explicit_count=3} }, + // .FDIV_H + { .FDIV_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1C000053, 0xFE00007F, .ZFH, {fp_round=true, explicit_count=3} }, + // .FSQRT_H + { .FSQRT_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5C000053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FSGNJ_H + { .FSGNJ_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24000053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FSGNJN_H + { .FSGNJN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24001053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FSGNJX_H + { .FSGNJX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24002053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FMIN_H + { .FMIN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C000053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FMAX_H + { .FMAX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C001053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FCVT_W_H + { .FCVT_W_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4000053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_WU_H + { .FCVT_WU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4100053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_L_H + { .FCVT_L_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4200053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true, explicit_count=2} }, + // .FCVT_LU_H + { .FCVT_LU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4300053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true, explicit_count=2} }, + // .FCVT_H_W + { .FCVT_H_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4000053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_H_WU + { .FCVT_H_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4100053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_H_L + { .FCVT_H_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4200053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true, explicit_count=2} }, + // .FCVT_H_LU + { .FCVT_H_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4300053, 0xFFF0007F, .ZFH, {rv64_only=true, fp_round=true, explicit_count=2} }, + // .FCVT_S_H + { .FCVT_S_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40200053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_H_S + { .FCVT_H_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44000053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_D_H + { .FCVT_D_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42200053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FCVT_H_D + { .FCVT_H_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44100053, 0xFFF0007F, .ZFH, {fp_round=true, explicit_count=2} }, + // .FMV_X_H + { .FMV_X_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4000053, 0xFFF0707F, .ZFH, {explicit_count=2} }, + // .FMV_H_X + { .FMV_H_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF4000053, 0xFFF0707F, .ZFH, {explicit_count=2} }, + // .FCLASS_H + { .FCLASS_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4001053, 0xFFF0707F, .ZFH, {explicit_count=2} }, + // .FEQ_H + { .FEQ_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4002053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FLT_H + { .FLT_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4001053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .FLE_H + { .FLE_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4000053, 0xFE00707F, .ZFH, {explicit_count=3} }, + // .MRET + { .MRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x30200073, 0xFFFFFFFF, .PRIV, {branch=true} }, + // .SRET + { .SRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10200073, 0xFFFFFFFF, .PRIV, {branch=true} }, + // .WFI + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10500073, 0xFFFFFFFF, .PRIV, {} }, + // .SFENCE_VMA + { .SFENCE_VMA, {.GPR,.GPR,.NONE,.NONE}, {.RS1,.RS2,.NONE,.NONE}, 0x12000073, 0xFE007FFF, .PRIV, {explicit_count=2} }, } @(rodata) -CLOBBER_FORMS := [198]lib.Clobber{ +CLOBBER_FORMS := [283]lib.Clobber{ // .LUI {written={0}}, // .AUIPC @@ -805,6 +973,174 @@ CLOBBER_FORMS := [198]lib.Clobber{ {written={0}, implicit_rd={.SP}, reads_mem=true}, // .C_FSWSP {read={0}, implicit_rd={.SP}, writes_mem=true}, + // .SH1ADD + {written={0}, read={1, 2}}, + // .SH2ADD + {written={0}, read={1, 2}}, + // .SH3ADD + {written={0}, read={1, 2}}, + // .ADD_UW + {written={0}, read={1, 2}}, + // .SH1ADD_UW + {written={0}, read={1, 2}}, + // .SH2ADD_UW + {written={0}, read={1, 2}}, + // .SH3ADD_UW + {written={0}, read={1, 2}}, + // .SLLI_UW + {written={0}, read={1}}, + // .ANDN + {written={0}, read={1, 2}}, + // .ORN + {written={0}, read={1, 2}}, + // .XNOR + {written={0}, read={1, 2}}, + // .CLZ + {written={0}, read={1}}, + // .CTZ + {written={0}, read={1}}, + // .CPOP + {written={0}, read={1}}, + // .SEXT_B + {written={0}, read={1}}, + // .SEXT_H + {written={0}, read={1}}, + // .ZEXT_H + {written={0}, read={1}}, + {written={0}, read={1}}, + // .MIN + {written={0}, read={1, 2}}, + // .MINU + {written={0}, read={1, 2}}, + // .MAX + {written={0}, read={1, 2}}, + // .MAXU + {written={0}, read={1, 2}}, + // .ROL + {written={0}, read={1, 2}}, + // .ROR + {written={0}, read={1, 2}}, + // .RORI + {written={0}, read={1}}, + // .ORC_B + {written={0}, read={1}}, + // .REV8 + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CLZW + {written={0}, read={1}}, + // .CTZW + {written={0}, read={1}}, + // .CPOPW + {written={0}, read={1}}, + // .ROLW + {written={0}, read={1, 2}}, + // .RORW + {written={0}, read={1, 2}}, + // .RORIW + {written={0}, read={1}}, + // .CLMUL + {written={0}, read={1, 2}}, + // .CLMULH + {written={0}, read={1, 2}}, + // .CLMULR + {written={0}, read={1, 2}}, + // .BCLR + {written={0}, read={1, 2}}, + // .BCLRI + {written={0}, read={1}}, + // .BEXT + {written={0}, read={1, 2}}, + // .BEXTI + {written={0}, read={1}}, + // .BINV + {written={0}, read={1, 2}}, + // .BINVI + {written={0}, read={1}}, + // .BSET + {written={0}, read={1, 2}}, + // .BSETI + {written={0}, read={1}}, + // .CZERO_EQZ + {written={0}, read={1, 2}}, + // .CZERO_NEZ + {written={0}, read={1, 2}}, + // .FLH + {written={0}, read={1}, reads_mem=true}, + // .FSH + {read={0, 1}, writes_mem=true}, + // .FMADD_H + {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FMSUB_H + {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FNMSUB_H + {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FNMADD_H + {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FADD_H + {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FSUB_H + {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FMUL_H + {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FDIV_H + {written={0}, read={1, 2}, fflags_wr={.NV, .DZ, .OF, .UF, .NX}, reads_frm=true}, + // .FSQRT_H + {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}, + // .FSGNJ_H + {written={0}, read={1, 2}}, + // .FSGNJN_H + {written={0}, read={1, 2}}, + // .FSGNJX_H + {written={0}, read={1, 2}}, + // .FMIN_H + {written={0}, read={1, 2}, fflags_wr={.NV}}, + // .FMAX_H + {written={0}, read={1, 2}, fflags_wr={.NV}}, + // .FCVT_W_H + {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}, + // .FCVT_WU_H + {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}, + // .FCVT_L_H + {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}, + // .FCVT_LU_H + {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}, + // .FCVT_H_W + {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}, + // .FCVT_H_WU + {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}, + // .FCVT_H_L + {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}, + // .FCVT_H_LU + {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}, + // .FCVT_S_H + {written={0}, read={1}, fflags_wr={.NV}, reads_frm=true}, + // .FCVT_H_S + {written={0}, read={1}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FCVT_D_H + {written={0}, read={1}, fflags_wr={.NV}, reads_frm=true}, + // .FCVT_H_D + {written={0}, read={1}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}, + // .FMV_X_H + {written={0}, read={1}}, + // .FMV_H_X + {written={0}, read={1}}, + // .FCLASS_H + {written={0}, read={1}}, + // .FEQ_H + {written={0}, read={1, 2}, fflags_wr={.NV}}, + // .FLT_H + {written={0}, read={1, 2}, fflags_wr={.NV}}, + // .FLE_H + {written={0}, read={1, 2}, fflags_wr={.NV}}, + // .MRET + {side_effects={.CONTROL}}, + // .SRET + {side_effects={.CONTROL}}, + // .WFI + {}, + // .SFENCE_VMA + {read={0, 1}, side_effects={.FENCE}}, } @(rodata) @@ -1008,4 +1344,87 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .C_ADD = { 195, 1}, .C_FLWSP = { 196, 1}, .C_FSWSP = { 197, 1}, + .SH1ADD = { 198, 1}, + .SH2ADD = { 199, 1}, + .SH3ADD = { 200, 1}, + .ADD_UW = { 201, 1}, + .SH1ADD_UW = { 202, 1}, + .SH2ADD_UW = { 203, 1}, + .SH3ADD_UW = { 204, 1}, + .SLLI_UW = { 205, 1}, + .ANDN = { 206, 1}, + .ORN = { 207, 1}, + .XNOR = { 208, 1}, + .CLZ = { 209, 1}, + .CTZ = { 210, 1}, + .CPOP = { 211, 1}, + .SEXT_B = { 212, 1}, + .SEXT_H = { 213, 1}, + .ZEXT_H = { 214, 2}, + .MIN = { 216, 1}, + .MINU = { 217, 1}, + .MAX = { 218, 1}, + .MAXU = { 219, 1}, + .ROL = { 220, 1}, + .ROR = { 221, 1}, + .RORI = { 222, 1}, + .ORC_B = { 223, 1}, + .REV8 = { 224, 2}, + .CLZW = { 226, 1}, + .CTZW = { 227, 1}, + .CPOPW = { 228, 1}, + .ROLW = { 229, 1}, + .RORW = { 230, 1}, + .RORIW = { 231, 1}, + .CLMUL = { 232, 1}, + .CLMULH = { 233, 1}, + .CLMULR = { 234, 1}, + .BCLR = { 235, 1}, + .BCLRI = { 236, 1}, + .BEXT = { 237, 1}, + .BEXTI = { 238, 1}, + .BINV = { 239, 1}, + .BINVI = { 240, 1}, + .BSET = { 241, 1}, + .BSETI = { 242, 1}, + .CZERO_EQZ = { 243, 1}, + .CZERO_NEZ = { 244, 1}, + .FLH = { 245, 1}, + .FSH = { 246, 1}, + .FMADD_H = { 247, 1}, + .FMSUB_H = { 248, 1}, + .FNMSUB_H = { 249, 1}, + .FNMADD_H = { 250, 1}, + .FADD_H = { 251, 1}, + .FSUB_H = { 252, 1}, + .FMUL_H = { 253, 1}, + .FDIV_H = { 254, 1}, + .FSQRT_H = { 255, 1}, + .FSGNJ_H = { 256, 1}, + .FSGNJN_H = { 257, 1}, + .FSGNJX_H = { 258, 1}, + .FMIN_H = { 259, 1}, + .FMAX_H = { 260, 1}, + .FCVT_W_H = { 261, 1}, + .FCVT_WU_H = { 262, 1}, + .FCVT_L_H = { 263, 1}, + .FCVT_LU_H = { 264, 1}, + .FCVT_H_W = { 265, 1}, + .FCVT_H_WU = { 266, 1}, + .FCVT_H_L = { 267, 1}, + .FCVT_H_LU = { 268, 1}, + .FCVT_S_H = { 269, 1}, + .FCVT_H_S = { 270, 1}, + .FCVT_D_H = { 271, 1}, + .FCVT_H_D = { 272, 1}, + .FMV_X_H = { 273, 1}, + .FMV_H_X = { 274, 1}, + .FCLASS_H = { 275, 1}, + .FEQ_H = { 276, 1}, + .FLT_H = { 277, 1}, + .FLE_H = { 278, 1}, + .MRET = { 279, 1}, + .SRET = { 280, 1}, + .WFI = { 281, 1}, + .SFENCE_VMA = { 282, 1}, } diff --git a/core/rexcode/isa/riscv/tablegen/instruction_table.odin b/core/rexcode/isa/riscv/tablegen/instruction_table.odin index ca076d516..2bfc7bb02 100644 --- a/core/rexcode/isa/riscv/tablegen/instruction_table.odin +++ b/core/rexcode/isa/riscv/tablegen/instruction_table.odin @@ -687,4 +687,326 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .C_FSWSP = { {{.C_FSWSP, {.FPR, .MEM_C_SP_W, .NONE, .NONE}, {.C_RS2, .C_IMM_CSS_W, .NONE, .NONE}, 0xE002, 0xE003, .F, {rv32_only=true}}, {read={0}, implicit_rd={.SP}, writes_mem=true}}, }, + + // ========================================================================= + // §7 Zba — address generation. Pure dataflow, no flags, no traps. + // ========================================================================= + .SH1ADD = { + {{.SH1ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20002033, MASK_R, .ZBA, {}}, {written={0}, read={1, 2}}}, + }, + .SH2ADD = { + {{.SH2ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20004033, MASK_R, .ZBA, {}}, {written={0}, read={1, 2}}}, + }, + .SH3ADD = { + {{.SH3ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x20006033, MASK_R, .ZBA, {}}, {written={0}, read={1, 2}}}, + }, + + // *.UW forms zero-extend rs1's low word; RV64-only by construction. + .ADD_UW = { + {{.ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0800003B, MASK_R, .ZBA, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + .SH1ADD_UW = { + {{.SH1ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000203B, MASK_R, .ZBA, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + .SH2ADD_UW = { + {{.SH2ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000403B, MASK_R, .ZBA, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + .SH3ADD_UW = { + {{.SH3ADD_UW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2000603B, MASK_R, .ZBA, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + + // SLLI.UW: OP-IMM-32 opcode but a 6-bit shamt (funct6 @31-26 = 000010). + .SLLI_UW = { + {{.SLLI_UW, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x0800101B, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBA, {rv64_only=true}}, {written={0}, read={1}}}, + }, + + // ========================================================================= + // §8 Zbb — basic bit-manipulation. All pure dataflow, no flags, no traps. + // ========================================================================= + + // Logic with negated operand (R-type) + .ANDN = { + {{.ANDN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40007033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .ORN = { + {{.ORN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40006033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .XNOR = { + {{.XNOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x40004033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + + // Count leading/trailing zeros, popcount (unary; rs2 is a selector) + .CLZ = { + {{.CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60001013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + .CTZ = { + {{.CTZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60101013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + .CPOP = { + {{.CPOP, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60201013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + + // Sign/zero extend (unary) + .SEXT_B = { + {{.SEXT_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60401013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + .SEXT_H = { + {{.SEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x60501013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + // ZEXT.H differs by base: OP (0x33) on RV32, OP-32 (0x3B) on RV64. + // Two forms in one slice keeps the same mnemonic valid on both. + .ZEXT_H = { + {{.ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x08004033, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv32_only=true}}, {written={0}, read={1}}}, + {{.ZEXT_H, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x0800403B, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + + // Min / max (R-type) + .MIN = { + {{.MIN, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A004033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .MINU = { + {{.MINU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A005033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .MAX = { + {{.MAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A006033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .MAXU = { + {{.MAXU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A007033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + + // Rotate (R-type) + rotate-immediate (6-bit funct6 shift-imm) + .ROL = { + {{.ROL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60001033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .ROR = { + {{.ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x60005033, MASK_R, .ZBB, {}}, {written={0}, read={1, 2}}}, + }, + .RORI = { + {{.RORI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x60005013, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBB, {}}, {written={0}, read={1}}}, + }, + + // Byte-granule ops (unary) + .ORC_B = { + {{.ORC_B, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x28705013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {}}, {written={0}, read={1}}}, + }, + // REV8 byte-reverse: RV32 uses funct7=0110100, RV64 uses 0110101 (imm[11:0] + // widens with XLEN). Two forms cover both bases. + .REV8 = { + {{.REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x69805013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv32_only=true}}, {written={0}, read={1}}}, + {{.REV8, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6B805013, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + + // Word variants — RV64 only + .CLZW = { + {{.CLZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6000101B, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + .CTZW = { + {{.CTZW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6010101B, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + .CPOPW = { + {{.CPOPW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x6020101B, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RS2, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + .ROLW = { + {{.ROLW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000103B, MASK_R, .ZBB, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + .RORW = { + {{.RORW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x6000503B, MASK_R, .ZBB, {rv64_only=true}}, {written={0}, read={1, 2}}}, + }, + // RORIW: OP-IMM-32 with a 5-bit shamt, so funct7 is fully fixed (MASK_R). + .RORIW = { + {{.RORIW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RS1,.SHAMT5,.NONE}, 0x6000501B, MASK_R, .ZBB, {rv64_only=true}}, {written={0}, read={1}}}, + }, + + // ========================================================================= + // §9 Zbc — carry-less multiply. Pure dataflow. + // ========================================================================= + .CLMUL = { + {{.CLMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A001033, MASK_R, .ZBC, {}}, {written={0}, read={1, 2}}}, + }, + .CLMULH = { + {{.CLMULH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A003033, MASK_R, .ZBC, {}}, {written={0}, read={1, 2}}}, + }, + .CLMULR = { + {{.CLMULR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0A002033, MASK_R, .ZBC, {}}, {written={0}, read={1, 2}}}, + }, + + // ========================================================================= + // §10 Zbs — single-bit ops. Register and 6-bit-immediate forms. + // ========================================================================= + .BCLR = { + {{.BCLR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48001033, MASK_R, .ZBS, {}}, {written={0}, read={1, 2}}}, + }, + .BCLRI = { + {{.BCLRI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48001013, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBS, {}}, {written={0}, read={1}}}, + }, + .BEXT = { + {{.BEXT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x48005033, MASK_R, .ZBS, {}}, {written={0}, read={1, 2}}}, + }, + .BEXTI = { + {{.BEXTI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x48005013, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBS, {}}, {written={0}, read={1}}}, + }, + .BINV = { + {{.BINV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x68001033, MASK_R, .ZBS, {}}, {written={0}, read={1, 2}}}, + }, + .BINVI = { + {{.BINVI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x68001013, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBS, {}}, {written={0}, read={1}}}, + }, + .BSET = { + {{.BSET, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x28001033, MASK_R, .ZBS, {}}, {written={0}, read={1, 2}}}, + }, + .BSETI = { + {{.BSETI, {.GPR,.GPR,.IMM6,.NONE}, {.RD,.RS1,.SHAMT6,.NONE}, 0x28001013, MASK_OPCODE | MASK_FUNCT3 | 0xFC000000, .ZBS, {}}, {written={0}, read={1}}}, + }, + + // ========================================================================= + // §11 Zicond — conditional zero. rd = (cond on rs2) ? 0 : rs1. + // ========================================================================= + .CZERO_EQZ = { + {{.CZERO_EQZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E005033, MASK_R, .ZICOND, {}}, {written={0}, read={1, 2}}}, + }, + .CZERO_NEZ = { + {{.CZERO_NEZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0E007033, MASK_R, .ZICOND, {}}, {written={0}, read={1, 2}}}, + }, + + // ========================================================================= + // §12 Zfh (half-precision, binary16) — mirrors §5 with fmt=10 (bits 26-25). + // reads_frm == encoding fp_round, exactly as in the F/D sections. + // ========================================================================= + .FLH = { + {{.FLH, {.FPR,.MEM,.NONE,.NONE}, {.RD,.OFFSET_BASE_I,.NONE,.NONE}, 0x00001007, MASK_I, .ZFH, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .FSH = { + {{.FSH, {.FPR,.MEM,.NONE,.NONE}, {.RS2,.OFFSET_BASE_S,.NONE,.NONE}, 0x00001027, MASK_S, .ZFH, {}}, {read={0, 1}, writes_mem=true}}, + }, + + .FMADD_H = { + {{.FMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000043, 0x0600007F, .ZFH, {fp_round=true}}, {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FMSUB_H = { + {{.FMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x04000047, 0x0600007F, .ZFH, {fp_round=true}}, {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FNMSUB_H = { + {{.FNMSUB_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004B, 0x0600007F, .ZFH, {fp_round=true}}, {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FNMADD_H = { + {{.FNMADD_H, {.FPR,.FPR,.FPR,.FPR}, {.RD,.RS1,.RS2,.RS3}, 0x0400004F, 0x0600007F, .ZFH, {fp_round=true}}, {written={0}, read={1, 2, 3}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + + .FADD_H = { + {{.FADD_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x04000053, MASK_OPCODE | MASK_FUNCT7, .ZFH, {fp_round=true}}, {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FSUB_H = { + {{.FSUB_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x0C000053, MASK_OPCODE | MASK_FUNCT7, .ZFH, {fp_round=true}}, {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FMUL_H = { + {{.FMUL_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x14000053, MASK_OPCODE | MASK_FUNCT7, .ZFH, {fp_round=true}}, {written={0}, read={1, 2}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FDIV_H = { + {{.FDIV_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x1C000053, MASK_OPCODE | MASK_FUNCT7, .ZFH, {fp_round=true}}, {written={0}, read={1, 2}, fflags_wr={.NV, .DZ, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FSQRT_H = { + {{.FSQRT_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x5C000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}}, + }, + + .FSGNJ_H = { + {{.FSGNJ_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24000053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}}}, + }, + .FSGNJN_H = { + {{.FSGNJN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24001053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}}}, + }, + .FSGNJX_H = { + {{.FSGNJX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x24002053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}}}, + }, + + .FMIN_H = { + {{.FMIN_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C000053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}, fflags_wr={.NV}}}, + }, + .FMAX_H = { + {{.FMAX_H, {.FPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0x2C001053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}, fflags_wr={.NV}}}, + }, + + // Half <-> integer conversions. Int->half can overflow the narrow range, + // so those carry OF alongside NX. + .FCVT_W_H = { + {{.FCVT_W_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}}, + }, + .FCVT_WU_H = { + {{.FCVT_WU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4100053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}}, + }, + .FCVT_L_H = { + {{.FCVT_L_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4200053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true, rv64_only=true}}, {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}}, + }, + .FCVT_LU_H = { + {{.FCVT_LU_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xC4300053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true, rv64_only=true}}, {written={0}, read={1}, fflags_wr={.NV, .NX}, reads_frm=true}}, + }, + .FCVT_H_W = { + {{.FCVT_H_W, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}}, + }, + .FCVT_H_WU = { + {{.FCVT_H_WU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4100053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}}, + }, + .FCVT_H_L = { + {{.FCVT_H_L, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4200053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true, rv64_only=true}}, {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}}, + }, + .FCVT_H_LU = { + {{.FCVT_H_LU, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xD4300053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true, rv64_only=true}}, {written={0}, read={1}, fflags_wr={.OF, .NX}, reads_frm=true}}, + }, + + // Half <-> single/double. Widening (H->S, H->D) is value-exact -> {.NV} + // only; narrowing (S->H, D->H) can round -> full flag set. Requires F/D. + .FCVT_S_H = { + {{.FCVT_S_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x40200053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV}, reads_frm=true}}, + }, + .FCVT_H_S = { + {{.FCVT_H_S, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + .FCVT_D_H = { + {{.FCVT_D_H, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x42200053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV}, reads_frm=true}}, + }, + .FCVT_H_D = { + {{.FCVT_H_D, {.FPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0x44100053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2, .ZFH, {fp_round=true}}, {written={0}, read={1}, fflags_wr={.NV, .OF, .UF, .NX}, reads_frm=true}}, + }, + + // Bit-pattern move / classify (no rounding, no flags) + .FMV_X_H = { + {{.FMV_X_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2 | MASK_FUNCT3, .ZFH, {}}, {written={0}, read={1}}}, + }, + .FMV_H_X = { + {{.FMV_H_X, {.FPR,.GPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xF4000053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2 | MASK_FUNCT3, .ZFH, {}}, {written={0}, read={1}}}, + }, + .FCLASS_H = { + {{.FCLASS_H, {.GPR,.FPR,.NONE,.NONE}, {.RD,.RS1,.NONE,.NONE}, 0xE4001053, MASK_OPCODE | MASK_FUNCT7 | MASK_RS2 | MASK_FUNCT3, .ZFH, {}}, {written={0}, read={1}}}, + }, + + // Comparisons -> GPR result; only NV possible. + .FEQ_H = { + {{.FEQ_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4002053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}, fflags_wr={.NV}}}, + }, + .FLT_H = { + {{.FLT_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4001053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}, fflags_wr={.NV}}}, + }, + .FLE_H = { + {{.FLE_H, {.GPR,.FPR,.FPR,.NONE}, {.RD,.RS1,.RS2,.NONE}, 0xA4000053, MASK_R, .ZFH, {}}, {written={0}, read={1, 2}, fflags_wr={.NV}}}, + }, + + // ========================================================================= + // §13 Privileged — trap-return + TLB maintenance (SYSTEM opcode, 0x73). + // MRET/SRET/WFI are fully fixed 32-bit words (mask 0xFFFFFFFF, no operands). + // ========================================================================= + .MRET = { + {{.MRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x30200073, 0xFFFFFFFF, .PRIV, {branch=true}}, {side_effects={.CONTROL}}}, + }, + .SRET = { + {{.SRET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10200073, 0xFFFFFFFF, .PRIV, {branch=true}}, {side_effects={.CONTROL}}}, + }, + // WFI: wait-for-interrupt hint. No PC redirect and no register effects in the + // architectural sense; execution resumes after the wakeup event. + .WFI = { + {{.WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x10500073, 0xFFFFFFFF, .PRIV, {}}, {}}, + }, + // SFENCE.VMA rs1(vaddr), rs2(asid): both operands optional (x0 = "all"). + // Reads rs1/rs2; acts as an address-translation ordering fence. + .SFENCE_VMA = { + {{.SFENCE_VMA, {.GPR,.GPR,.NONE,.NONE}, {.RS1,.RS2,.NONE,.NONE}, 0x12000073, MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7 | MASK_RD, .PRIV, {}}, {read={0, 1}, side_effects={.FENCE}}}, + }, } diff --git a/core/rexcode/isa/riscv/tables.odin b/core/rexcode/isa/riscv/tables.odin index 4d708c3d3..627f0a2ab 100644 --- a/core/rexcode/isa/riscv/tables.odin +++ b/core/rexcode/isa/riscv/tables.odin @@ -30,9 +30,9 @@ Decode_Entry :: struct #packed { bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 - flags: Encoding_Flags, // 1 + flags: Encoding_Flags, // 2 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 21) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/riscv/tables/riscv.clobber_forms.bin b/core/rexcode/isa/riscv/tables/riscv.clobber_forms.bin index 047a2b041c0c42c712945ad31938704bf71dd435..7da4138f7dba2eb403d6d554871255730030a2f6 100644 GIT binary patch delta 197 zcmeyy`&oFyH@3;bOb(1plM@-0C*HK5oXKbgp@hIMhLPY1O*rv>LDuG5rPhIK@Nmq09=q0A(#Lcg4wJ4rzREXd5uz@UtS5QIC)$Pif&rrn5vhlhbdP>6wnA7T*$1A_u6 z6hYaUfq`Fuf#LuE|Nq$-7)&4{3=9m#3=lyE1{PB!K>@Hz1_l;021ag121b4+hGK}5 z7+4t$%n^c+Kn4j~AOsYgajQ(&>A5K2|AFV4cwc? z3=B;51q}Zf84PR@f&y?sJA|MDT+kjNXaE;10E02g$D z3tGe7Y2=C!gj;0fh7g2XWaN$zgj;0ffe?gSWaJ4hLm2rO81xkw1nLVu{A6NK@M2(O zg93qF7fh9JCY0Q06&C_<$H1Js*FVaS3|ZyJRo3qrkV6oD)V z^`=oIvLMu(Mp4LuP;VMVBMU;kX%vGj2=%5>EV3Zfn?`ZSf>3W7#WOH*F))DY4t8ih zVrEcC01JYu33Y^EA_Ef>6B8p7GmA4QYcnvgF*A51!3EtBg2`|}Z-ih9T+kmOm?^>2C|?8R4|i)iHU)Mk%@sJn1Lapp5eoPW(JKc zWR;+h|HsT=kc|)&V1NncAOscQg1HDm1_ljKA;8RFkcSWyfD7h>ZHC%@0BU;ylAr)g zunjYfgkUpB5E94`!GA0a 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