From d1cb08b72f2e3c7bc5223c63ac7fa3cdb5379457 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:18:16 -0400 Subject: [PATCH] rexcode/arm32: masks that could not separate sibling forms Forty-one groups of forms differed only in bits their own mask left free, so they all matched each other's words and whichever sorted first answered for the lot. That is where the NEON element sizes went: `vabs.s8`, `.s16` and `.s32` are three patterns differing at bits 19:18, and with those bits outside the mask the first one spoke for all three. 121 rows. Two things that exposed: - LDM and STM differ only in the writeback bit, and nothing in the operand model recorded it, so the two forms printed identically. Instruction carries it now and the base register wears its `!`. - The T32 shifts left the S bit free, and their patterns sort ahead of MOV's, so `movs.w r1, r2` came back as `lsl r1, r2, #0`. There is no LSLS form in the table for it to have become instead; pinning the bit at least stops it answering for a word that is not its own. Also: r0 could not be used as an index register. The printer took a register-offset operand to be immediate-only unless the index was non-zero, when the class alone already says whether there is one -- `[r0, -r0]` printed as `[r0]`. And a displacement of zero lost its U bit, which llvm-mc writes as `#-0` because it is a different word. Against llvm-mc, A32 entries whose disassembly assembles back to the same word: 760 of 1139, from 683. Wrong: 81, from 158. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 36 +- core/rexcode/isa/arm32/encoder.odin | 22 +- core/rexcode/isa/arm32/instructions.odin | 5 +- core/rexcode/isa/arm32/printer.odin | 19 +- .../isa/arm32/tablegen/encoding_table.odin | 258 +-- .../tablegen/generated/decode_tables.odin | 1836 ++++++++--------- .../tablegen/generated/encode_tables.odin | 258 +-- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10718 -> 10670 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3298 -> 3298 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 38 +- 16 files changed, 1260 insertions(+), 1212 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index ef8b1e7dc..633ad28e6 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -165,6 +165,14 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in if e.flags.sets_flags { inst.sets_flags = true } + // LDM/STM carry the writeback in bit 21; nothing else in the operand + // model records it, and without it the two forms print identically. + for k in 0 ..< len(e.enc) { + if e.enc[k] == .A32_REG_LIST { + inst.writeback = (word >> 21) & 1 != 0 + break + } + } for _, k in e.enc { if e.enc[k] == .NONE { continue } @@ -379,13 +387,17 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm(base, disp)) + mm := mem_imm(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_IMM8_OFFSET: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm(base, disp)) + mm := mem_imm(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_REG_OFFSET: base := Register(REG_GPR | u16((word >> 16) & 0xF)) idx := Register(REG_GPR | u16(word & 0xF)) @@ -566,24 +578,36 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op base := Register(REG_GPR | u16((word >> 16) & 0xF)) disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if (word >> 23) & 1 == 0 { disp = -disp } - return op_mem(mem_imm_pre(base, disp)) + mm := mem_imm_pre(base, disp) + + if (word >> 23) & 1 == 0 { mm.sign = -1 } + + return op_mem(mm) case .MEM_IMM8_POST_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if (word >> 23) & 1 == 0 { disp = -disp } - return op_mem(mem_imm_post(base, disp)) + mm := mem_imm_post(base, disp) + + if (word >> 23) & 1 == 0 { mm.sign = -1 } + + return op_mem(mm) case .MEM_PRE_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm_pre(base, disp)) + mm := mem_imm_pre(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_POST_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm_post(base, disp)) + mm := mem_imm_post(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_LITERAL: // PC-relative literal load: U bit + 12-bit signed disp u_bit := (word >> 23) & 1 diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 7243cf6aa..d5b8a68b1 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -164,6 +164,7 @@ encode_one_inline :: #force_inline proc( (want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) && encoding_matches_inline(inst, f) && inst.sets_flags == f.flags.sets_flags && + writeback_matches(inst, f) && mem_mode_matches(inst, f) { form = f } @@ -180,6 +181,7 @@ encode_one_inline :: #force_inline proc( if !encoding_matches_inline(inst, &f) { continue } if inst.sets_flags && !f.flags.sets_flags { continue } if !inst.sets_flags && f.flags.sets_flags { continue } + if !writeback_matches(inst, &f) { continue } if !mem_mode_matches(inst, &f) { continue } form = &f break @@ -516,7 +518,7 @@ pack_operand_inline :: #force_inline proc( case .MEM_IMM12_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .RT2_A32_PAIR: @@ -524,7 +526,7 @@ pack_operand_inline :: #force_inline proc( case .MEM_IMM8_PRE_INDEX, .MEM_IMM8_POST_INDEX, .MEM_IMM8_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFF return base | (u_bit << 23) | ((disp >> 4) & 0xF) << 8 | (disp & 0xF) case .MEM_REG_OFFSET: @@ -538,14 +540,14 @@ pack_operand_inline :: #force_inline proc( // P=1, W=1 in bits 24/21 to select pre-index addressing mode. m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .MEM_POST_INDEX: // Same layout as MEM_IMM12_OFFSET; form bits select P=0 in bit 24. m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .MEM_LITERAL: @@ -882,3 +884,15 @@ neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (sh case: return 7, 0x1, 4 } } + +// LDM/STM come in a writeback form and a plain one that differ only in bit 21, +// so the operand shapes cannot tell them apart. +@(private="file", require_results) +writeback_matches :: #force_inline proc "contextless" (inst: ^Instruction, f: ^Encoding) -> bool { + for e in f.enc { + if e == .A32_REG_LIST { + return ((f.bits >> 21) & 1 != 0) == inst.writeback + } + } + return true +} diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 5cb3ed3aa..e27e2558e 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -39,7 +39,10 @@ Instruction :: struct #align(64) { length: u8 | 3, // 2 or 4 bytes on the wire sets_flags: bool | 1, // S bit (writes APSR.NZCV) wide: bool | 1, // force the T32 wide form when both exist - // 3 bits spare + // LDM/STM write the updated base back when this is set, which the + // syntax shows as a `!` after the base register. + writeback: bool | 1, + // 2 bits spare }, // Form-id hint: when non-zero, this is (1 + the index into // ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index dd21c4e68..889ac3cfe 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -136,6 +136,9 @@ sbprint :: proc( for k in 0.. 0 { strings.write_string(sb, ", ") } write_operand(sb, &inst.ops[k], inst, offset, &display, opts) + // LDM/STM write the updated base back, and the syntax marks + // that with a `!` on the base register itself. + if k == 0 && inst.writeback { strings.write_byte(sb, '!') } } } strings.write_string(sb, "\n") @@ -573,7 +576,10 @@ write_operand :: proc( write_memory :: proc(sb: ^strings.Builder, m: Memory) { strings.write_string(sb, "[") write_register(sb, m.base) - if reg_class(m.index) == REG_GPR && reg_hw(m.index) != 0 { + // An immediate-only form leaves index at Register(0), whose class is not + // REG_GPR -- so the class alone says whether there is an index. Excluding + // hw 0 as well made r0 unusable as one. + if reg_class(m.index) == REG_GPR { // Register offset switch m.mode { case .OFFSET: @@ -595,15 +601,18 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory) { } else { // An indexed form writes its displacement even when it is zero: the // writeback is the point, and `[r0]` alone is the plain offset form. + // The U bit also survives a zero displacement, and an assembler needs + // to see it -- `#-0` and `#0` are different words. + neg := m.disp == 0 && m.sign < 0 ? "-" : "" switch m.mode { case .OFFSET: - if m.disp != 0 { - fmt.sbprintf(sb, ", #%d]", m.disp) + if m.disp != 0 || m.sign < 0 { + fmt.sbprintf(sb, ", #%s%d]", neg, m.disp) } else { strings.write_string(sb, "]") } - case .PRE_INDEX: fmt.sbprintf(sb, ", #%d]!", m.disp) - case .POST_INDEX: fmt.sbprintf(sb, "], #%d", m.disp) + case .PRE_INDEX: fmt.sbprintf(sb, ", #%s%d]!", neg, m.disp) + case .POST_INDEX: fmt.sbprintf(sb, "], #%s%d", neg, m.disp) } } } diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 56a3f0579..1f67e57ea 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -164,11 +164,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4 AND: 010000 0000 Rm Rd {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 AND imm12: high=11110 i 0 0000 S Rn low=0 imm3 Rd imm8 - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 AND reg: high=11101 01 0000 S Rn low=imm3 Rd imm2 type Rm - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .EOR = { {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {}}, @@ -224,11 +224,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 5 hi-reg MOV: 010001 10 H1 H2 Rm Rd {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MOV imm12-mod (encoding T2): high=11110 i 0 0010 S 1111 low=0 imm3 Rd imm8 - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 MOV reg (encoding T3): high=11101 01 0010 S 1111 low=0 imm3 Rd imm2 00 Rm - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .MVN = { {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {}}, @@ -1116,17 +1116,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // base register + register-list into Rn + register_list operand slots. .LDM = { // LDM IA (default) - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {}}, // LDMIA writeback (LDM Rn!, {reglist}): W=1 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {}}, // T16 Format 15 LDMIA: 11001 Rb reg_list8 {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14 {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STM = { - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {}}, // T16 Format 15 STMIA: 11000 Rb reg_list8 {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STMIA: 0xE8800000 @@ -1442,23 +1442,23 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1110 .I8 → 0xF2800E10 // 1111 .F32 (special: high bit = 0) → 0xF2800F10 (limited to specific imm patterns) // 1110 op=1 + bit 5 set → .I64 → 0xF2800E30 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) // Q forms (Q=1, bit 6 = 1) - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q // ---- VMOV scalar to/from GPR (lane access) ---- // VMOV. Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000 // VMOV. Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000 @@ -1883,11 +1883,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 @@ -1906,10 +1906,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 @@ -1927,10 +1927,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { @@ -2136,15 +2136,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer: 1111 0011 1011 size 01 Vd 0011 0 Q M 0 Vm - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 (size=10, bit 10 = 1) - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vabs.s8 q,q = FFB1_0340; vabs.f32 q,q = FFB9_0740 (bit 19 = 1 for FP). {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, @@ -2153,15 +2153,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer (bit 7 = 1 distinguishes VNEG from VABS) - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vneg.s8 q,q = FFB1_03C0; vneg.f32 q,q = FFB9_07C0. {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, @@ -2173,36 +2173,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VCLZ = { - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VCLS = { - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VREV16 / VREV32 / VREV64 (byte/half/word reverse within block) ---- .VREV64 = { - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VREV32 = { - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, }, .VREV16 = { {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, @@ -2234,26 +2234,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---- VTRN / VUZP / VZIP (interleave / deinterleave) ---- .VTRN = { - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VUZP = { - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VZIP = { - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTBL / VTBX (table lookup) ---- @@ -2510,26 +2510,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .VMOVN = { // VMOVN.I D, Q : 1111 0011 1 D 11 size 10 Vd 0010 0 0 M 0 Vm - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 }, .VQMOVN = { // VQMOVN. (signed saturating narrowing move) // .S: 1111 0011 1 D 11 size 10 Vd 0010 1 0 M 0 Vm // .U: same with op bit 6 = 1 - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, .VQMOVUN = { // VQMOVUN (signed input, unsigned saturating output): 1111 0011 1 D 11 size 10 Vd 0010 0 1 M 0 Vm (bit 6=1, bit 7=0) - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, }, // ---- VSHLL / VSHRN / VRSHRN / VQSHRN / VQRSHRN ---- @@ -2538,9 +2538,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm @@ -2571,13 +2571,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1111 0011 1 D 11 size 00 Vd 0010 op Q M 0 Vm (op=0 add long, op=1 accumulate) .VPADDL = { // .S: - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // Q form {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .U variants: bit 7 = 1 - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VPADAL = { @@ -2655,9 +2655,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: LSL reg (Rd = Rd <<= Rs) {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSL imm (encoded as MOV with shift LSL): high=11101010 0100 1111 low=0 imm3 Rd imm2 00 Rm - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSL reg: high=11111010 0000 Rn low=1111 Rd 0000 Rm - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LSR = { {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2667,9 +2667,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: LSR reg {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSR imm (MOV with shift LSR): bits 5:4 = 01 - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSR reg: 0xFA20F000 - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ASR = { {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2679,9 +2679,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: ASR reg {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ASR imm: bits 5:4 = 10 - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ASR reg: 0xFA40F000 - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ROR = { {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2689,9 +2689,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: ROR reg {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ROR imm: bits 5:4 = 11 - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ROR reg: 0xFA60F000 - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RRX = { // RRX is ROR with imm=0 (cond 00011010 0000 Rd 00000110 Rm) @@ -3623,10 +3623,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, @@ -3643,10 +3643,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 779676d58..f7f3870a1 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -215,8 +215,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -267,8 +267,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -367,41 +367,41 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -469,8 +469,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -491,8 +491,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, @@ -518,8 +518,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -583,8 +583,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -656,8 +656,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -682,123 +682,123 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -822,10 +822,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -988,11 +988,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1210,19 +1210,19 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1367,13 +1367,13 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1443,6 +1443,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1492,10 +1496,6 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1674,46 +1674,46 @@ DECODE_FORM_IDX := [1649]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, - 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 23, 25, 22, 21, 0, 0, - 0, 0, 11, 10, 19, 20, 17, 18, 10, 12, 14, 16, 13, 15, 11, 0, - 6, 0, 0, 7, 4, 3, 9, 2, 6, 5, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 24, 23, 25, 21, 22, 0, 0, 0, 19, 12, + 17, 14, 20, 18, 10, 16, 13, 15, 11, 0, 0, 0, 0, 11, 10, 0, + 6, 0, 0, 7, 2, 6, 3, 4, 9, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 3, 1, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, - 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, + 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, + 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, - 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, + 20, 14, 13, 9, 4, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 10, 0, 2, 1, 3, 1, 2, 0, 3, 0, 0, 0, 9, 5, 4, - 7, 8, 3, 2, 6, 5, 7, 6, 3, 4, 8, 9, 2, 1, 0, 0, - 1, 2, 0, 1, 3, 5, 4, 2, 0, 2, 1, 11, 10, 13, 12, 12, - 15, 13, 14, 14, 12, 15, 13, 16, 14, 17, 15, 17, 16, 14, 15, 5, - 2, 1, 0, 4, 3, 1, 0, 3, 2, 2, 1, 3, 1, 5, 4, 0, - 2, 3, 1, 3, 2, 4, 0, 5, 1, 0, 0, 1, 1, 0, 3, 2, - 5, 2, 1, 0, 4, 3, 1, 0, 2, 3, 4, 5, 2, 1, 0, 4, - 3, 2, 1, 0, 4, 3, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, - 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 0, 2, 0, - 2, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, + 0, 5, 4, 6, 8, 9, 2, 3, 7, 3, 7, 5, 6, 4, 2, 9, + 8, 10, 1, 0, 2, 0, 5, 1, 2, 3, 4, 2, 1, 0, 2, 0, + 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 5, 1, 3, + 2, 0, 4, 2, 0, 4, 5, 1, 3, 0, 5, 1, 3, 2, 4, 0, + 1, 2, 3, 4, 5, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 10, + 13, 12, 15, 12, 13, 14, 13, 14, 12, 15, 17, 15, 16, 14, 14, 16, + 15, 17, 1, 2, 0, 3, 0, 1, 0, 1, 0, 1, 3, 5, 0, 2, + 1, 3, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, + 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 2, 0, 2, + 0, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, @@ -1751,10 +1751,10 @@ DECODE_FORM_IDX := [1649]u16{ 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, - 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, + 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, + 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, @@ -1769,7 +1769,7 @@ DECODE_FORM_IDX := [1649]u16{ } @(rodata) -DECODE_BUCKET_LIST := [5359]u16{ +DECODE_BUCKET_LIST := [5335]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1807,26 +1807,26 @@ DECODE_BUCKET_LIST := [5359]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 365, 361, 362, 363, - 364, 366, 367, 368, 369, 370, 371, 374, 380, 372, 379, 381, 378, 377, 373, 375, - 376, 382, 383, 384, 385, 386, 387, 389, 388, 394, 391, 393, 392, 390, 395, 396, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 361, 360, 362, 359, 363, 364, + 365, 370, 375, 376, 369, 374, 371, 368, 372, 367, 373, 366, 377, 378, 379, 380, + 381, 382, 384, 383, 385, 386, 392, 388, 387, 393, 391, 390, 389, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 427, 428, - 430, 429, 431, 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, + 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 428, 427, + 429, 430, 431, 432, 433, 434, 436, 435, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 441, - 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, - 457, 459, 458, 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, + 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 454, 455, 456, + 457, 458, 459, 461, 460, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 468, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, - 412, 413, 469, 470, 471, 468, 358, 359, 360, 365, 364, 363, 362, 361, 366, 367, - 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, 375, 383, + 412, 413, 469, 470, 471, 468, 362, 360, 361, 359, 358, 363, 364, 365, 376, 375, + 374, 372, 371, 370, 373, 368, 369, 367, 366, 377, 378, 379, 380, 382, 381, 383, 384, 385, 386, 394, 393, 392, 391, 389, 390, 388, 387, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 472, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, 429, 430, 431, + 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 473, 472, 442, 443, - 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 455, 454, 456, 457, 459, 458, - 461, 460, 463, 462, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, + 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 457, 456, 458, 459, + 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 474, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 469, 470, 475, 474, 477, 476, 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, @@ -1835,37 +1835,37 @@ DECODE_BUCKET_LIST := [5359]u16{ 520, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, - 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, + 569, 570, 571, 572, 573, 575, 574, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 477, 476, - 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, - 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, - 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, + 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 494, + 493, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 510, + 509, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 527, 526, 528, 529, 530, 531, 532, 615, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 616, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, - 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, - 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 617, 618, 619, 620, - 365, 364, 363, 361, 362, 621, 622, 623, 624, 370, 371, 382, 380, 379, 381, 378, - 375, 376, 377, 374, 373, 372, 625, 626, 627, 394, 393, 390, 391, 392, 389, 388, + 586, 587, 589, 588, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, + 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 617, 361, 362, 360, + 359, 358, 618, 619, 620, 376, 373, 374, 375, 372, 371, 370, 368, 367, 369, 366, + 621, 622, 623, 624, 382, 381, 625, 626, 627, 394, 393, 390, 391, 392, 389, 388, 387, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, - 640, 641, 642, 644, 643, 645, 646, 647, 648, 649, 650, 628, 629, 395, 396, 397, + 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, - 651, 630, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, - 667, 666, 669, 668, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, - 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 672, 673, 677, 675, 674, - 676, 680, 679, 678, 681, 682, 683, 684, 692, 690, 687, 688, 689, 691, 685, 686, - 698, 694, 700, 697, 696, 693, 699, 695, 702, 701, 704, 703, 705, 711, 709, 710, - 708, 706, 707, 713, 712, 714, 718, 716, 717, 715, 719, 721, 720, 722, 724, 725, - 726, 723, 730, 729, 727, 728, 733, 731, 734, 732, 740, 737, 735, 738, 739, 736, - 743, 744, 742, 741, 745, 746, 747, 752, 748, 753, 749, 750, 751, 759, 757, 755, - 754, 758, 756, 760, 761, 762, 763, 765, 766, 764, 767, 771, 773, 769, 768, 772, - 770, 777, 775, 779, 776, 778, 774, 780, 784, 783, 782, 781, 789, 787, 788, 785, - 786, 791, 790, 792, 793, 794, 795, 797, 799, 798, 796, 802, 800, 803, 801, 805, + 651, 630, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 665, 664, + 667, 666, 668, 669, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, + 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 672, 675, 674, 673, 680, + 679, 678, 677, 676, 683, 687, 688, 682, 685, 684, 686, 681, 689, 692, 690, 691, + 695, 698, 693, 697, 696, 694, 701, 700, 699, 704, 702, 703, 705, 709, 708, 706, + 707, 711, 713, 710, 712, 714, 716, 715, 718, 717, 720, 722, 721, 719, 724, 728, + 725, 727, 726, 723, 733, 730, 729, 731, 734, 732, 740, 738, 739, 735, 737, 736, + 742, 741, 743, 746, 745, 744, 747, 748, 749, 753, 752, 751, 750, 757, 755, 756, + 754, 760, 761, 759, 758, 765, 762, 763, 764, 767, 769, 766, 768, 773, 770, 771, + 772, 775, 774, 776, 777, 779, 778, 781, 780, 782, 785, 783, 784, 787, 786, 789, + 788, 791, 790, 792, 793, 794, 795, 797, 799, 798, 796, 802, 800, 803, 801, 805, 804, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 412, 413, 806, 672, 618, 619, 620, 365, 364, 363, 361, 362, - 621, 622, 623, 624, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373, 377, + 408, 409, 410, 411, 412, 413, 806, 672, 362, 361, 359, 360, 358, 618, 619, 620, + 376, 374, 373, 372, 369, 370, 371, 375, 366, 367, 368, 621, 622, 623, 624, 382, 381, 625, 626, 627, 394, 392, 393, 391, 390, 387, 388, 389, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 807, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, @@ -1873,14 +1873,14 @@ DECODE_BUCKET_LIST := [5359]u16{ 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 808, 807, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, 667, 666, 669, 668, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 412, 413, 809, 673, 677, 675, 674, 676, 680, 678, 679, 681, - 682, 683, 684, 690, 691, 692, 687, 688, 686, 685, 689, 700, 699, 698, 696, 695, - 693, 694, 697, 701, 702, 705, 704, 703, 711, 707, 708, 709, 706, 710, 714, 712, - 713, 717, 716, 715, 718, 721, 722, 720, 719, 726, 725, 724, 723, 728, 729, 730, - 727, 734, 733, 732, 731, 739, 740, 736, 737, 738, 735, 742, 741, 743, 744, 745, - 747, 746, 753, 750, 751, 752, 748, 749, 758, 759, 756, 754, 755, 757, 761, 760, - 763, 762, 764, 765, 766, 767, 772, 771, 769, 768, 770, 773, 778, 776, 777, 775, - 774, 779, 782, 780, 784, 781, 783, 786, 787, 785, 789, 788, 791, 790, 792, 793, + 408, 409, 410, 411, 412, 413, 809, 680, 677, 678, 679, 675, 674, 673, 676, 687, + 688, 686, 685, 683, 682, 681, 684, 689, 690, 691, 692, 698, 696, 695, 693, 694, + 697, 700, 701, 699, 705, 704, 703, 702, 707, 708, 709, 706, 711, 712, 713, 710, + 716, 714, 715, 721, 722, 720, 719, 717, 718, 728, 726, 727, 725, 724, 723, 734, + 733, 732, 729, 730, 731, 739, 740, 736, 737, 738, 735, 742, 741, 743, 744, 745, + 746, 747, 748, 749, 753, 750, 751, 752, 756, 754, 755, 757, 761, 758, 759, 760, + 764, 763, 762, 765, 769, 766, 767, 768, 772, 771, 770, 773, 775, 774, 776, 777, + 778, 779, 780, 781, 785, 784, 782, 783, 786, 787, 788, 789, 791, 790, 792, 793, 794, 795, 799, 797, 798, 796, 802, 800, 801, 803, 804, 805, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, @@ -1897,214 +1897,213 @@ DECODE_BUCKET_LIST := [5359]u16{ 938, 939, 940, 941, 942, 943, 939, 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 952, 954, 970, 970, 971, 972, 960, 971, 972, 967, 973, 974, 973, 975, 976, - 977, 975, 976, 977, 978, 976, 978, 976, 979, 981, 976, 983, 980, 979, 981, 976, - 982, 983, 980, 978, 976, 978, 976, 984, 976, 985, 986, 984, 976, 985, 978, 976, - 978, 976, 987, 976, 988, 987, 976, 988, 978, 976, 978, 976, 989, 990, 989, 990, + 977, 975, 976, 977, 978, 976, 978, 976, 979, 976, 980, 981, 976, 982, 983, 978, + 976, 978, 976, 984, 976, 985, 986, 984, 976, 985, 978, 976, 978, 976, 987, 976, + 988, 987, 976, 988, 978, 976, 978, 976, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, - 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 991, 989, 991, + 989, 990, 989, 990, 989, 990, 989, 990, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, - 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, - 1008, 995, 996, 1007, 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 995, 996, 1009, 1007, 1008, 997, 998, 992, 993, 994, 1010, 1011, 1007, 1012, 1008, - 995, 1013, 996, 1014, 1015, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, - 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 1021, - 995, 996, 1018, 1019, 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, - 1020, 1021, 995, 996, 1031, 1030, 1018, 1019, 1022, 1023, 997, 998, 1018, 1019, 1021, 1020, - 995, 996, 1018, 1019, 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, - 1020, 1021, 995, 996, 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, - 1034, 1035, 1037, 1036, 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1034, 1035, - 1007, 1008, 1007, 1008, 1018, 1019, 1033, 1032, 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, - 1018, 1019, 1033, 1032, 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, - 1042, 1043, 1044, 1045, 1046, 1007, 1047, 1048, 1050, 1049, 1008, 1051, 1052, 1053, 1054, 1055, - 1043, 1044, 1056, 1007, 1058, 1057, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, - 1064, 1065, 1066, 1043, 1044, 1067, 1007, 1069, 1068, 1070, 1071, 1008, 1051, 1052, 1053, 1054, - 1044, 1043, 1056, 1072, 1073, 1007, 1075, 1074, 1076, 1077, 1008, 1061, 1052, 1062, 1054, 1041, - 1078, 1042, 1043, 1044, 1045, 1046, 1007, 1047, 1048, 1050, 1049, 1008, 1051, 1052, 1053, 1054, - 1043, 1044, 1056, 1007, 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, - 1065, 1066, 1043, 1044, 1067, 1007, 1068, 1069, 1070, 1071, 1008, 1051, 1052, 1053, 1054, 1043, - 1044, 1056, 1072, 1073, 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, - 1081, 1082, 1083, 1084, 1085, 1086, 1088, 1087, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, - 1092, 1094, 1093, 1061, 1052, 1062, 1054, 1095, 1096, 1098, 1097, 1099, 1100, 1051, 1052, 1053, - 1054, 1102, 1101, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1115, 1114, - 1116, 1117, 1119, 1118, 1120, 1121, 1123, 1122, 1124, 1125, 1126, 1127, 1128, 1129, 1131, 1139, - 1130, 1140, 1137, 1142, 1135, 1133, 1143, 1136, 1145, 1132, 1134, 1138, 1141, 1144, 1146, 1148, - 1147, 1150, 1149, 1154, 1151, 1152, 1153, 1156, 1155, 1157, 1158, 1160, 1159, 1161, 1162, 1163, - 1164, 1166, 1165, 1168, 1167, 1170, 1169, 1172, 1171, 1056, 1061, 1052, 1062, 1054, 1079, 1080, - 1082, 1081, 1083, 1084, 1085, 1173, 1086, 1088, 1087, 1051, 1052, 1053, 1054, 1056, 1089, 1090, - 1092, 1091, 1093, 1094, 1061, 1052, 1062, 1054, 1174, 1175, 1095, 1096, 1097, 1098, 1099, 1100, - 1051, 1052, 1053, 1054, 1176, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1109, 1108, 1111, 1110, - 1113, 1112, 1114, 1115, 1117, 1116, 1118, 1119, 1120, 1121, 1122, 1123, 1125, 1124, 1128, 1126, - 1127, 1134, 1131, 1132, 1133, 1135, 1129, 1130, 1136, 1143, 1142, 1140, 1137, 1146, 1145, 1138, - 1139, 1141, 1144, 1147, 1148, 1149, 1150, 1151, 1154, 1152, 1153, 1156, 1155, 1157, 1158, 1159, - 1160, 1161, 1162, 1163, 1164, 1166, 1165, 1168, 1167, 1170, 1169, 1172, 1171, 1056, 1061, 1052, - 1062, 1054, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, - 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1177, 1177, 1177, 1177, 1177, 1177, - 1177, 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, - 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, - 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, - 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, - 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, - 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, - 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, - 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, + 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, 1008, 995, 996, 1007, + 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, + 1007, 1008, 997, 998, 992, 993, 994, 1011, 1010, 1007, 1012, 1008, 995, 1013, 996, 1015, + 1014, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 1021, 995, 996, 1018, 1019, + 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, + 1031, 1030, 1018, 1019, 1023, 1022, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, + 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, + 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, 1035, 1034, 1036, 1037, + 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1034, 1035, 1007, 1008, 1007, 1008, + 1018, 1019, 1033, 1032, 1018, 1019, 1034, 1035, 1018, 1019, 1018, 1019, 1018, 1019, 1033, 1032, + 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, 1042, 1044, 1043, 1045, + 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1055, 1043, 1044, 1056, 1007, + 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, 1064, 1065, 1066, 1044, + 1043, 1067, 1007, 1069, 1068, 1070, 1071, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1072, + 1073, 1007, 1075, 1074, 1076, 1077, 1008, 1061, 1052, 1062, 1054, 1041, 1078, 1042, 1044, 1043, + 1045, 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1007, + 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, 1065, 1066, 1043, 1044, + 1067, 1007, 1069, 1068, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1044, 1043, 1056, 1072, 1073, + 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1083, 1084, + 1085, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, 1092, 1094, 1093, 1061, + 1052, 1062, 1054, 1095, 1096, 1097, 1098, 1099, 1100, 1051, 1052, 1053, 1054, 1102, 1103, 1101, + 1104, 1105, 1107, 1106, 1108, 1109, 1110, 1111, 1113, 1112, 1114, 1115, 1116, 1117, 1118, 1119, + 1121, 1120, 1123, 1122, 1125, 1124, 1126, 1128, 1127, 1129, 1137, 1130, 1145, 1132, 1139, 1143, + 1146, 1133, 1134, 1144, 1131, 1142, 1138, 1141, 1136, 1135, 1140, 1148, 1147, 1149, 1150, 1152, + 1151, 1154, 1153, 1155, 1156, 1157, 1158, 1159, 1160, 1162, 1161, 1163, 1165, 1166, 1164, 1167, + 1168, 1169, 1170, 1172, 1171, 1056, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1084, 1083, + 1085, 1173, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1092, 1091, 1094, 1093, + 1061, 1052, 1062, 1054, 1174, 1175, 1095, 1096, 1098, 1097, 1099, 1100, 1051, 1052, 1053, 1054, + 1176, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1111, 1110, 1113, 1112, 1115, 1114, + 1116, 1117, 1119, 1118, 1120, 1121, 1122, 1123, 1124, 1125, 1128, 1127, 1126, 1136, 1133, 1134, + 1135, 1137, 1130, 1131, 1132, 1129, 1138, 1145, 1144, 1142, 1139, 1140, 1141, 1143, 1146, 1148, + 1147, 1149, 1150, 1151, 1152, 1153, 1154, 1155, 1156, 1158, 1157, 1159, 1160, 1162, 1161, 1163, + 1166, 1164, 1165, 1168, 1167, 1170, 1169, 1171, 1172, 1056, 1061, 1052, 1062, 1054, 1007, 1008, + 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, + 1007, 1008, 1177, 1007, 1008, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1178, 1179, + 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, + 1196, 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, + 1212, 1213, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, + 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, + 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, + 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, + 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, + 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, + 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, + 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, + 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, 1355, + 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, + 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, 1384, 1385, 1386, 1387, + 1388, 1389, 1390, 1391, 1392, 1393, 1347, 1348, 1394, 1395, 1396, 1352, 1353, 1397, 1398, 1399, + 1400, 1401, 1362, 1402, 1403, 1372, 1371, 1373, 1347, 1348, 1352, 1353, 1354, 1355, 1356, 1357, + 1359, 1358, 1360, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1372, 1371, 1373, 1404, + 1405, 1406, 1347, 1348, 1352, 1353, 1407, 1362, 1402, 1403, 1372, 1371, 1373, 1408, 1409, 1410, + 1411, 1412, 1413, 1414, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425, 1426, + 1427, 1428, 1429, 1430, 1431, 1432, 1433, 1434, 1435, 1436, 1437, 1438, 1439, 1440, 1441, 1442, + 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1453, 1454, 1455, 1456, 1457, 1458, + 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468, 1469, 1470, 1471, 1472, 1473, 1474, + 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, 1483, 1484, 1485, 1486, 1487, 1488, 1489, 1490, + 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1504, 1505, 1506, + 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1517, 1516, 1519, 1518, 1521, 1520, 1522, + 1523, 1239, 1240, 1241, 1242, 1243, 1244, 1524, 1525, 1526, 1527, 1528, 1529, 1530, 1531, 1532, + 1533, 1534, 1535, 1536, 1537, 1538, 1251, 1252, 1253, 1254, 1255, 1256, 1539, 1540, 1541, 1261, + 1262, 1263, 1542, 1270, 1271, 1272, 1273, 1274, 1275, 1277, 1278, 1543, 1279, 1280, 1544, 1281, + 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1545, 1546, 1547, 1548, 1549, 1550, + 1551, 1552, 1292, 1553, 1293, 1294, 1295, 1296, 1554, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, - 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, - 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, - 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, - 1368, 1369, 1370, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, - 1384, 1385, 1386, 1387, 1388, 1389, 1390, 1391, 1392, 1393, 1347, 1348, 1394, 1395, 1396, 1352, - 1353, 1397, 1398, 1399, 1400, 1401, 1362, 1402, 1403, 1372, 1371, 1373, 1347, 1348, 1352, 1353, - 1354, 1355, 1356, 1357, 1359, 1358, 1360, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, - 1372, 1371, 1373, 1404, 1405, 1406, 1347, 1348, 1352, 1353, 1407, 1362, 1402, 1403, 1372, 1371, - 1373, 1408, 1409, 1410, 1411, 1412, 1413, 1414, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, - 1423, 1424, 1425, 1426, 1427, 1428, 1429, 1430, 1431, 1432, 1433, 1434, 1435, 1436, 1437, 1438, - 1439, 1440, 1441, 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1453, 1454, - 1455, 1456, 1457, 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468, 1469, 1470, - 1471, 1472, 1473, 1474, 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, 1483, 1484, 1485, 1486, - 1487, 1488, 1489, 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, - 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1517, 1516, 1519, - 1518, 1521, 1520, 1522, 1523, 1239, 1240, 1241, 1242, 1243, 1244, 1524, 1525, 1526, 1527, 1528, - 1529, 1530, 1531, 1532, 1533, 1534, 1535, 1536, 1537, 1538, 1251, 1252, 1253, 1254, 1255, 1256, - 1539, 1540, 1541, 1261, 1262, 1263, 1542, 1270, 1271, 1272, 1273, 1274, 1275, 1277, 1278, 1543, - 1279, 1280, 1544, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1545, 1546, - 1547, 1548, 1549, 1550, 1551, 1552, 1292, 1553, 1293, 1294, 1295, 1296, 1554, 1297, 1298, 1299, - 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, - 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1555, - 1556, 1557, 1558, 1559, 1560, 1561, 1562, 1333, 1334, 1335, 1336, 1563, 1564, 1565, 1566, 1567, - 1568, 1569, 1569, 1570, 1570, 1571, 1571, 1572, 1573, 1574, 1575, 1576, 1576, 1577, 1577, 1578, - 1578, 1579, 1579, 1580, 1581, 1582, 1583, 1584, 1585, 1586, 1587, 1588, 1589, 1590, 1591, 1592, - 1593, 1594, 1595, 1596, 1597, 1598, 1599, 1600, 1601, 1602, 1603, 1603, 1604, 1605, 1606, 1607, - 1608, 1609, 1610, 1611, 1612, 1612, 1613, 1613, 1614, 1614, 1615, 1615, 1616, 1616, 1617, 1617, - 1618, 1618, 1619, 1619, 1620, 1620, 1621, 1621, 1622, 1623, 1624, 1625, 1626, 1627, 1628, 1629, - 1630, 1631, 1632, 1633, 1634, 1635, 1636, 1637, 1638, 1639, 1640, 1641, 1642, 1643, 1643, 1644, - 1644, 1645, 1645, 1645, 1646, 1647, 1645, 1648, 1648, 1186, 1187, 1188, 1189, 1194, 1200, 1190, - 1199, 1200, 1199, 1196, 1195, 1196, 1193, 1195, 1183, 1184, 1191, 1200, 1179, 1180, 1181, 1182, - 1185, 1199, 1200, 1199, 1198, 1197, 1192, 1198, 1197, 1200, 1199, 1200, 1178, 1199, 1200, 1199, - 1200, 1199, 1213, 1212, 1205, 1213, 1212, 1219, 1219, 1201, 1202, 1203, 1204, 1210, 1209, 1218, - 1201, 1202, 1203, 1204, 1209, 1210, 1218, 1211, 1211, 1214, 1206, 1214, 1208, 1216, 1216, 1217, - 1217, 1207, 1215, 1215, 1230, 1237, 1238, 1230, 1234, 1236, 1233, 1235, 1230, 1237, 1238, 1220, - 1221, 1222, 1223, 1230, 1234, 1236, 1233, 1235, 1237, 1238, 1234, 1236, 1233, 1235, 1237, 1238, - 1234, 1236, 1233, 1235, 1220, 1221, 1222, 1223, 1227, 1228, 1229, 1232, 1224, 1225, 1226, 1231, - 1227, 1228, 1229, 1232, 1224, 1225, 1226, 1231, 1257, 1261, 1262, 1264, 1276, 1277, 1278, 1279, - 1290, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1341, - 1257, 1261, 1262, 1265, 1276, 1277, 1278, 1279, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, - 1305, 1306, 1315, 1316, 1317, 1318, 1341, 1261, 1262, 1264, 1276, 1277, 1278, 1279, 1291, 1294, - 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1341, 1247, 1248, 1249, - 1250, 1261, 1262, 1263, 1265, 1276, 1277, 1278, 1279, 1280, 1289, 1291, 1294, 1297, 1298, 1301, - 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1341, 1261, 1262, 1264, 1277, 1278, 1279, - 1290, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, - 1341, 1261, 1262, 1265, 1277, 1278, 1279, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, - 1306, 1315, 1316, 1317, 1318, 1337, 1341, 1261, 1262, 1264, 1277, 1278, 1279, 1291, 1294, 1297, - 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, 1341, 1247, 1248, 1249, - 1250, 1261, 1262, 1263, 1265, 1277, 1278, 1279, 1280, 1289, 1291, 1294, 1297, 1298, 1301, 1302, - 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, 1341, 1239, 1240, 1258, 1259, 1260, 1272, - 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, - 1314, 1331, 1332, 1336, 1339, 1342, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, - 1339, 1342, 1258, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1339, 1342, 1270, - 1271, 1281, 1282, 1287, 1288, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1339, - 1342, 1258, 1259, 1260, 1272, 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1299, 1300, 1307, 1308, - 1309, 1310, 1311, 1312, 1313, 1314, 1331, 1332, 1336, 1338, 1340, 1342, 1299, 1300, 1307, 1308, - 1309, 1310, 1311, 1312, 1313, 1314, 1338, 1340, 1342, 1241, 1242, 1243, 1244, 1253, 1254, 1255, - 1256, 1258, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1338, 1340, 1342, 1245, - 1246, 1251, 1252, 1270, 1271, 1281, 1282, 1287, 1288, 1299, 1300, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1338, 1340, 1342, 1266, 1292, 1295, 1319, 1320, 1321, 1322, 1323, 1324, 1325, + 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1555, 1556, 1557, 1558, 1559, + 1560, 1561, 1562, 1333, 1334, 1335, 1336, 1563, 1564, 1565, 1566, 1567, 1568, 1569, 1569, 1570, + 1570, 1571, 1571, 1572, 1573, 1574, 1575, 1576, 1576, 1577, 1577, 1578, 1578, 1579, 1579, 1580, + 1581, 1582, 1583, 1584, 1585, 1586, 1587, 1588, 1589, 1590, 1591, 1592, 1593, 1594, 1595, 1596, + 1597, 1598, 1599, 1600, 1601, 1602, 1603, 1603, 1604, 1605, 1606, 1607, 1608, 1609, 1610, 1611, + 1612, 1612, 1613, 1613, 1614, 1614, 1615, 1615, 1616, 1616, 1617, 1617, 1618, 1618, 1619, 1619, + 1620, 1620, 1621, 1621, 1622, 1623, 1624, 1625, 1626, 1627, 1628, 1629, 1630, 1631, 1632, 1633, + 1634, 1635, 1636, 1637, 1638, 1639, 1640, 1641, 1642, 1643, 1643, 1644, 1644, 1645, 1645, 1645, + 1646, 1647, 1645, 1648, 1648, 1186, 1187, 1188, 1189, 1194, 1200, 1190, 1199, 1200, 1199, 1196, + 1195, 1196, 1193, 1195, 1183, 1184, 1191, 1200, 1179, 1180, 1181, 1182, 1185, 1199, 1200, 1199, + 1198, 1197, 1192, 1198, 1197, 1200, 1199, 1200, 1178, 1199, 1200, 1199, 1200, 1199, 1213, 1205, + 1212, 1219, 1219, 1201, 1202, 1203, 1204, 1210, 1218, 1209, 1218, 1211, 1211, 1214, 1206, 1214, + 1208, 1216, 1216, 1217, 1217, 1207, 1215, 1215, 1230, 1237, 1238, 1230, 1234, 1236, 1233, 1235, + 1230, 1237, 1238, 1220, 1221, 1222, 1223, 1230, 1234, 1236, 1233, 1235, 1237, 1238, 1234, 1236, + 1233, 1235, 1237, 1238, 1234, 1236, 1233, 1235, 1220, 1221, 1222, 1223, 1227, 1228, 1229, 1232, + 1224, 1225, 1226, 1231, 1227, 1228, 1229, 1232, 1224, 1225, 1226, 1231, 1257, 1261, 1262, 1264, + 1276, 1277, 1278, 1279, 1290, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, + 1316, 1317, 1318, 1341, 1257, 1261, 1262, 1265, 1276, 1277, 1278, 1279, 1291, 1294, 1297, 1298, + 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1341, 1261, 1262, 1264, 1276, 1277, + 1278, 1279, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, + 1341, 1247, 1248, 1249, 1250, 1261, 1262, 1263, 1265, 1276, 1277, 1278, 1279, 1280, 1289, 1291, + 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1341, 1261, 1262, + 1264, 1277, 1278, 1279, 1290, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, + 1316, 1317, 1318, 1337, 1341, 1261, 1262, 1265, 1277, 1278, 1279, 1291, 1294, 1297, 1298, 1301, + 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, 1341, 1261, 1262, 1264, 1277, 1278, + 1279, 1291, 1294, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, + 1341, 1247, 1248, 1249, 1250, 1261, 1262, 1263, 1265, 1277, 1278, 1279, 1280, 1289, 1291, 1294, + 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1337, 1341, 1239, 1240, + 1258, 1259, 1260, 1272, 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1299, 1300, 1307, 1308, 1309, + 1310, 1311, 1312, 1313, 1314, 1331, 1332, 1336, 1339, 1342, 1299, 1300, 1307, 1308, 1309, 1310, + 1311, 1312, 1313, 1314, 1339, 1342, 1258, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, + 1314, 1339, 1342, 1270, 1271, 1281, 1282, 1287, 1288, 1299, 1300, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1339, 1342, 1258, 1259, 1260, 1272, 1273, 1274, 1275, 1283, 1284, 1285, 1286, + 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1331, 1332, 1336, 1338, 1340, 1342, + 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1338, 1340, 1342, 1241, 1242, 1243, + 1244, 1253, 1254, 1255, 1256, 1258, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, + 1338, 1340, 1342, 1245, 1246, 1251, 1252, 1270, 1271, 1281, 1282, 1287, 1288, 1299, 1300, 1307, + 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1338, 1340, 1342, 1266, 1292, 1295, 1319, 1320, 1321, + 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1267, 1292, 1295, 1319, 1320, 1321, 1322, + 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1268, 1293, 1296, 1319, 1320, 1321, 1322, 1323, + 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1269, 1293, 1296, 1319, 1320, 1321, 1322, 1323, 1324, + 1325, 1326, 1327, 1328, 1329, 1330, 1266, 1292, 1295, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1267, 1292, 1295, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1268, 1293, 1296, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1269, 1293, 1296, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, - 1329, 1330, 1266, 1292, 1295, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, - 1330, 1267, 1292, 1295, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, - 1268, 1293, 1296, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1269, - 1293, 1296, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1333, 1334, - 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, - 1333, 1334, 1335, 1333, 1334, 1335, 1343, 1345, 1346, 1349, 1353, 1361, 1362, 1363, 1364, 1372, - 1371, 1373, 1345, 1346, 1350, 1354, 1361, 1362, 1363, 1364, 1372, 1371, 1373, 1345, 1346, 1361, - 1362, 1370, 1371, 1372, 1373, 1345, 1346, 1361, 1362, 1370, 1371, 1372, 1373, 1344, 1351, 1352, - 1359, 1358, 1369, 1372, 1371, 1373, 1358, 1359, 1369, 1372, 1371, 1373, 1347, 1360, 1372, 1371, + 1329, 1330, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, + 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1333, 1334, 1335, 1343, 1345, 1346, 1349, 1353, 1361, + 1362, 1363, 1371, 1372, 1373, 1345, 1346, 1350, 1354, 1361, 1362, 1364, 1371, 1372, 1373, 1345, + 1346, 1361, 1362, 1370, 1371, 1372, 1373, 1345, 1346, 1361, 1362, 1370, 1372, 1371, 1373, 1344, + 1351, 1352, 1358, 1369, 1372, 1371, 1373, 1359, 1369, 1371, 1372, 1373, 1347, 1360, 1371, 1372, 1373, 1348, 1360, 1371, 1372, 1373, 1353, 1362, 1365, 1371, 1372, 1373, 1355, 1362, 1365, 1371, - 1372, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1352, 1372, 1371, 1373, 1372, 1371, - 1373, 1347, 1371, 1372, 1373, 1348, 1371, 1372, 1373, 1346, 1353, 1361, 1362, 1372, 1371, 1373, + 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, 1372, 1371, 1373, 1371, 1372, + 1373, 1347, 1371, 1372, 1373, 1348, 1372, 1371, 1373, 1346, 1353, 1361, 1362, 1372, 1371, 1373, 1346, 1357, 1361, 1362, 1372, 1371, 1373, 1346, 1361, 1362, 1372, 1371, 1373, 1346, 1361, 1362, - 1371, 1372, 1373, 1352, 1367, 1371, 1372, 1373, 1367, 1371, 1372, 1373, 1347, 1368, 1371, 1372, - 1373, 1348, 1368, 1371, 1372, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1362, - 1372, 1371, 1373, 1356, 1362, 1371, 1372, 1373, 1352, 1366, 1372, 1371, 1373, 1366, 1372, 1371, - 1373, 1347, 1372, 1371, 1373, 1348, 1371, 1372, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1371, + 1372, 1371, 1373, 1352, 1367, 1371, 1372, 1373, 1367, 1371, 1372, 1373, 1347, 1368, 1372, 1371, + 1373, 1348, 1368, 1372, 1371, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1362, + 1372, 1371, 1373, 1356, 1362, 1371, 1372, 1373, 1352, 1366, 1371, 1372, 1373, 1366, 1371, 1372, + 1373, 1347, 1371, 1372, 1373, 1348, 1371, 1372, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1352, 1402, 1371, 1372, 1373, 1371, - 1372, 1373, 1347, 1372, 1371, 1373, 1348, 1372, 1371, 1373, 1353, 1362, 1372, 1371, 1373, 1362, - 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, 1403, 1372, 1371, 1373, + 1372, 1373, 1347, 1371, 1372, 1373, 1348, 1371, 1372, 1373, 1353, 1362, 1372, 1371, 1373, 1362, + 1372, 1371, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, 1403, 1371, 1372, 1373, 1371, 1372, 1373, 1347, 1371, 1372, 1373, 1348, 1371, 1372, 1373, 1353, 1400, 1362, 1371, 1372, - 1373, 1362, 1371, 1372, 1373, 1394, 1400, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, - 1398, 1372, 1371, 1373, 1372, 1371, 1373, 1347, 1396, 1397, 1371, 1372, 1373, 1348, 1371, 1372, - 1373, 1393, 1353, 1401, 1362, 1372, 1371, 1373, 1362, 1371, 1372, 1373, 1374, 1375, 1376, 1377, + 1373, 1362, 1372, 1371, 1373, 1394, 1400, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, + 1398, 1372, 1371, 1373, 1372, 1371, 1373, 1347, 1396, 1397, 1371, 1372, 1373, 1348, 1372, 1371, + 1373, 1393, 1353, 1401, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1374, 1375, 1376, 1377, 1378, 1380, 1381, 1382, 1383, 1385, 1386, 1387, 1388, 1395, 1401, 1362, 1372, 1371, 1373, 1379, - 1384, 1390, 1391, 1392, 1362, 1372, 1371, 1373, 1352, 1399, 1371, 1372, 1373, 1372, 1371, 1373, - 1389, 1347, 1372, 1371, 1373, 1348, 1371, 1372, 1373, 1353, 1362, 1363, 1364, 1372, 1371, 1373, - 1354, 1362, 1364, 1363, 1371, 1372, 1373, 1362, 1370, 1371, 1372, 1373, 1362, 1370, 1372, 1371, - 1373, 1352, 1359, 1358, 1369, 1372, 1371, 1373, 1358, 1359, 1369, 1372, 1371, 1373, 1347, 1360, - 1371, 1372, 1373, 1348, 1360, 1371, 1372, 1373, 1353, 1362, 1365, 1372, 1371, 1373, 1355, 1362, - 1365, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, 1371, 1372, 1373, - 1371, 1372, 1373, 1347, 1371, 1372, 1373, 1348, 1372, 1371, 1373, 1353, 1362, 1372, 1371, 1373, - 1357, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1352, 1367, 1371, - 1372, 1373, 1367, 1372, 1371, 1373, 1347, 1368, 1372, 1371, 1373, 1348, 1368, 1372, 1371, 1373, - 1353, 1362, 1372, 1371, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, 1356, 1362, 1371, - 1372, 1373, 1352, 1366, 1372, 1371, 1373, 1366, 1372, 1371, 1373, 1347, 1372, 1371, 1373, 1348, - 1371, 1372, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1362, 1371, 1372, 1373, - 1362, 1371, 1372, 1373, 1352, 1402, 1372, 1371, 1373, 1371, 1372, 1373, 1347, 1372, 1371, 1373, - 1348, 1371, 1372, 1373, 1353, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, - 1373, 1362, 1371, 1372, 1373, 1352, 1403, 1372, 1371, 1373, 1372, 1371, 1373, 1347, 1372, 1371, - 1373, 1348, 1371, 1372, 1373, 1353, 1362, 1372, 1371, 1373, 1362, 1371, 1372, 1373, 1362, 1372, - 1371, 1373, 1362, 1372, 1371, 1373, 1352, 1372, 1371, 1373, 1372, 1371, 1373, 1347, 1371, 1372, - 1373, 1348, 1371, 1372, 1373, 1404, 1405, 1406, 1353, 1362, 1372, 1371, 1373, 1362, 1372, 1371, - 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1352, 1371, 1372, 1373, 1372, 1371, 1373, - 1347, 1371, 1372, 1373, 1348, 1407, 1372, 1371, 1373, 1411, 1410, 1413, 1412, 1417, 1409, 1408, - 1419, 1423, 1416, 1422, 1425, 1424, 1421, 1419, 1420, 1414, 1415, 1418, 1426, 1427, 1430, 1483, - 1489, 1433, 1483, 1492, 1429, 1484, 1488, 1432, 1484, 1491, 1428, 1485, 1487, 1431, 1485, 1490, - 1486, 1486, 1439, 1440, 1441, 1442, 1443, 1449, 1455, 1461, 1467, 1473, 1435, 1436, 1437, 1438, - 1444, 1450, 1456, 1462, 1468, 1474, 1445, 1451, 1457, 1463, 1469, 1475, 1434, 1447, 1453, 1459, - 1465, 1471, 1477, 1448, 1454, 1460, 1466, 1472, 1478, 1446, 1452, 1458, 1464, 1470, 1476, 1479, - 1493, 1494, 1482, 1497, 1480, 1495, 1481, 1498, 1496, 1521, 1520, 1511, 1517, 1519, 1511, 1516, - 1518, 1521, 1520, 1517, 1519, 1516, 1518, 1505, 1506, 1507, 1508, 1509, 1510, 1521, 1499, 1500, - 1501, 1502, 1503, 1504, 1512, 1513, 1514, 1515, 1520, 1511, 1517, 1519, 1511, 1516, 1518, 1505, - 1506, 1507, 1508, 1509, 1510, 1521, 1499, 1500, 1501, 1502, 1503, 1504, 1520, 1517, 1519, 1516, - 1518, 1511, 1511, 1512, 1513, 1514, 1515, 1511, 1511, 1538, 1261, 1262, 1277, 1278, 1279, 1544, - 1290, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, - 1315, 1316, 1317, 1318, 1567, 1261, 1262, 1277, 1278, 1279, 1544, 1291, 1549, 1550, 1551, 1552, - 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1567, 1261, - 1262, 1277, 1278, 1279, 1544, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, - 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1567, 1523, 1532, 1533, 1261, 1262, 1263, 1277, - 1278, 1279, 1280, 1544, 1289, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, - 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1567, 1538, 1261, 1262, 1277, 1278, 1279, 1544, - 1290, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, - 1315, 1316, 1317, 1318, 1563, 1567, 1261, 1262, 1277, 1278, 1279, 1544, 1291, 1549, 1550, 1551, - 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1563, - 1567, 1261, 1262, 1277, 1278, 1279, 1544, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, - 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1563, 1567, 1522, 1532, 1533, 1261, - 1262, 1263, 1277, 1278, 1279, 1280, 1544, 1289, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, - 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1563, 1567, 1239, 1240, 1272, - 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, - 1309, 1310, 1311, 1312, 1313, 1314, 1559, 1560, 1561, 1562, 1336, 1565, 1568, 1545, 1546, 1547, - 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1565, 1568, 1545, 1546, - 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1565, 1568, 1530, - 1531, 1270, 1271, 1281, 1282, 1287, 1288, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, - 1309, 1310, 1311, 1312, 1313, 1314, 1555, 1556, 1557, 1558, 1565, 1568, 1272, 1273, 1274, 1275, - 1283, 1284, 1285, 1286, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1559, 1560, 1561, 1562, 1336, 1564, 1566, 1568, 1545, 1546, 1547, 1548, 1554, - 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1241, 1242, 1243, - 1244, 1253, 1254, 1255, 1256, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, - 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1530, 1531, 1251, 1252, 1270, 1271, 1281, 1282, 1287, - 1288, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, - 1555, 1556, 1557, 1558, 1564, 1566, 1568, 1542, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, - 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, - 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, - 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, - 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1542, 1543, - 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, - 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1544, 1293, 1553, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, + 1384, 1390, 1391, 1392, 1362, 1371, 1372, 1373, 1352, 1399, 1372, 1371, 1373, 1372, 1371, 1373, + 1389, 1347, 1372, 1371, 1373, 1348, 1372, 1371, 1373, 1353, 1362, 1363, 1372, 1371, 1373, 1354, + 1362, 1364, 1372, 1371, 1373, 1362, 1370, 1371, 1372, 1373, 1362, 1370, 1371, 1372, 1373, 1352, + 1358, 1369, 1372, 1371, 1373, 1359, 1369, 1371, 1372, 1373, 1347, 1360, 1371, 1372, 1373, 1348, + 1360, 1372, 1371, 1373, 1353, 1362, 1365, 1371, 1372, 1373, 1355, 1362, 1365, 1372, 1371, 1373, + 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1352, 1371, 1372, 1373, 1371, 1372, 1373, 1347, + 1372, 1371, 1373, 1348, 1372, 1371, 1373, 1353, 1362, 1371, 1372, 1373, 1357, 1362, 1372, 1371, + 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1352, 1367, 1372, 1371, 1373, 1367, 1372, + 1371, 1373, 1347, 1368, 1372, 1371, 1373, 1348, 1368, 1372, 1371, 1373, 1353, 1362, 1372, 1371, + 1373, 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1356, 1362, 1372, 1371, 1373, 1352, 1366, + 1371, 1372, 1373, 1366, 1371, 1372, 1373, 1347, 1371, 1372, 1373, 1348, 1372, 1371, 1373, 1353, + 1362, 1371, 1372, 1373, 1362, 1372, 1371, 1373, 1362, 1371, 1372, 1373, 1362, 1371, 1372, 1373, + 1352, 1402, 1372, 1371, 1373, 1371, 1372, 1373, 1347, 1371, 1372, 1373, 1348, 1371, 1372, 1373, + 1353, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, + 1373, 1352, 1403, 1371, 1372, 1373, 1371, 1372, 1373, 1347, 1372, 1371, 1373, 1348, 1371, 1372, + 1373, 1353, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1362, 1372, + 1371, 1373, 1352, 1371, 1372, 1373, 1372, 1371, 1373, 1347, 1372, 1371, 1373, 1348, 1371, 1372, + 1373, 1404, 1405, 1406, 1353, 1362, 1372, 1371, 1373, 1362, 1372, 1371, 1373, 1362, 1372, 1371, + 1373, 1362, 1372, 1371, 1373, 1352, 1372, 1371, 1373, 1372, 1371, 1373, 1347, 1372, 1371, 1373, + 1348, 1407, 1371, 1372, 1373, 1411, 1410, 1413, 1412, 1417, 1409, 1408, 1419, 1423, 1416, 1422, + 1425, 1424, 1421, 1419, 1420, 1414, 1415, 1418, 1426, 1427, 1430, 1434, 1489, 1433, 1492, 1429, + 1435, 1488, 1432, 1491, 1428, 1436, 1487, 1431, 1490, 1437, 1443, 1444, 1445, 1446, 1447, 1453, + 1459, 1465, 1471, 1477, 1439, 1440, 1441, 1442, 1448, 1454, 1460, 1466, 1472, 1478, 1449, 1455, + 1461, 1467, 1473, 1479, 1438, 1451, 1457, 1463, 1469, 1475, 1481, 1452, 1458, 1464, 1470, 1476, + 1482, 1450, 1456, 1462, 1468, 1474, 1480, 1483, 1493, 1494, 1486, 1497, 1484, 1495, 1485, 1498, + 1496, 1521, 1520, 1511, 1517, 1519, 1511, 1516, 1518, 1521, 1520, 1517, 1519, 1516, 1518, 1505, + 1506, 1507, 1508, 1509, 1510, 1521, 1499, 1500, 1501, 1502, 1503, 1504, 1512, 1513, 1514, 1515, + 1520, 1511, 1517, 1519, 1511, 1516, 1518, 1505, 1506, 1507, 1508, 1509, 1510, 1521, 1499, 1500, + 1501, 1502, 1503, 1504, 1520, 1517, 1519, 1516, 1518, 1511, 1511, 1512, 1513, 1514, 1515, 1511, + 1511, 1538, 1261, 1262, 1277, 1278, 1279, 1544, 1290, 1291, 1549, 1550, 1551, 1552, 1294, 1554, + 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1567, 1261, 1262, 1277, + 1278, 1279, 1544, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, + 1305, 1306, 1315, 1316, 1317, 1318, 1567, 1261, 1262, 1277, 1278, 1279, 1544, 1291, 1549, 1550, + 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, + 1567, 1523, 1532, 1533, 1261, 1262, 1263, 1277, 1278, 1279, 1280, 1544, 1289, 1291, 1549, 1550, + 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, + 1567, 1538, 1261, 1262, 1277, 1278, 1279, 1544, 1290, 1291, 1549, 1550, 1551, 1552, 1294, 1554, + 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1563, 1567, 1261, 1262, + 1277, 1278, 1279, 1544, 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, + 1304, 1305, 1306, 1315, 1316, 1317, 1318, 1563, 1567, 1261, 1262, 1277, 1278, 1279, 1544, 1291, + 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, 1316, + 1317, 1318, 1563, 1567, 1522, 1532, 1533, 1261, 1262, 1263, 1277, 1278, 1279, 1280, 1544, 1289, + 1291, 1549, 1550, 1551, 1552, 1294, 1554, 1297, 1298, 1301, 1302, 1303, 1304, 1305, 1306, 1315, + 1316, 1317, 1318, 1563, 1567, 1239, 1240, 1272, 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1545, + 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1559, 1560, + 1561, 1562, 1336, 1565, 1568, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, + 1311, 1312, 1313, 1314, 1565, 1568, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, + 1310, 1311, 1312, 1313, 1314, 1565, 1568, 1530, 1531, 1270, 1271, 1281, 1282, 1287, 1288, 1545, + 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1555, 1556, + 1557, 1558, 1565, 1568, 1272, 1273, 1274, 1275, 1283, 1284, 1285, 1286, 1545, 1546, 1547, 1548, + 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1559, 1560, 1561, 1562, 1336, + 1564, 1566, 1568, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, + 1313, 1314, 1564, 1566, 1568, 1241, 1242, 1243, 1244, 1253, 1254, 1255, 1256, 1545, 1546, 1547, + 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1530, + 1531, 1251, 1252, 1270, 1271, 1281, 1282, 1287, 1288, 1545, 1546, 1547, 1548, 1554, 1299, 1300, + 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1555, 1556, 1557, 1558, 1564, 1566, 1568, 1542, + 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, + 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, - 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, - 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, - 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, - 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, + 1326, 1327, 1328, 1329, 1330, 1544, 1293, 1553, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, + 1325, 1326, 1327, 1328, 1329, 1330, 1542, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, + 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, + 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, + 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, + 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, + 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, + 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, + 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, + 1539, 1540, 1541, 1554, 1333, 1334, 1335, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2237,519 +2236,518 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x85 = { 2037, 1}, 0x86 = { 2038, 1}, 0x87 = { 2039, 1}, - 0x88 = { 2040, 2}, - 0x89 = { 2042, 3}, - 0x8A = { 2045, 2}, - 0x8B = { 2047, 4}, - 0x8C = { 2051, 1}, - 0x8D = { 2052, 1}, - 0x8E = { 2053, 1}, - 0x8F = { 2054, 1}, - 0x90 = { 2055, 1}, - 0x91 = { 2056, 2}, - 0x92 = { 2058, 2}, - 0x93 = { 2060, 2}, - 0x94 = { 2062, 1}, - 0x95 = { 2063, 1}, - 0x96 = { 2064, 1}, - 0x97 = { 2065, 1}, - 0x98 = { 2066, 1}, - 0x99 = { 2067, 2}, - 0x9A = { 2069, 1}, - 0x9B = { 2070, 2}, - 0x9C = { 2072, 1}, - 0x9D = { 2073, 1}, - 0x9E = { 2074, 1}, - 0x9F = { 2075, 1}, - 0xA0 = { 2076, 2}, - 0xA1 = { 2078, 2}, - 0xA2 = { 2080, 2}, - 0xA3 = { 2082, 2}, - 0xA4 = { 2084, 2}, - 0xA5 = { 2086, 2}, - 0xA6 = { 2088, 2}, - 0xA7 = { 2090, 2}, - 0xA8 = { 2092, 2}, - 0xA9 = { 2094, 2}, - 0xAA = { 2096, 2}, - 0xAB = { 2098, 2}, - 0xAC = { 2100, 2}, - 0xAD = { 2102, 2}, - 0xAE = { 2104, 2}, - 0xAF = { 2106, 2}, - 0xB0 = { 2108, 2}, - 0xB1 = { 2110, 2}, - 0xB2 = { 2112, 2}, - 0xB3 = { 2114, 2}, - 0xB4 = { 2116, 2}, - 0xB5 = { 2118, 2}, - 0xB6 = { 2120, 2}, - 0xB7 = { 2122, 2}, - 0xB8 = { 2124, 2}, - 0xB9 = { 2126, 2}, - 0xBA = { 2128, 2}, - 0xBB = { 2130, 2}, - 0xBC = { 2132, 2}, - 0xBD = { 2134, 2}, - 0xBE = { 2136, 2}, - 0xBF = { 2138, 2}, - 0xC0 = { 2140, 7}, - 0xC1 = { 2147, 4}, - 0xC2 = { 2151, 12}, - 0xC3 = { 2163, 5}, - 0xC4 = { 2168, 11}, - 0xC5 = { 2179, 8}, - 0xC6 = { 2187, 12}, - 0xC7 = { 2199, 5}, - 0xC8 = { 2204, 6}, - 0xC9 = { 2210, 6}, - 0xCA = { 2216, 12}, - 0xCB = { 2228, 8}, - 0xCC = { 2236, 6}, - 0xCD = { 2242, 6}, - 0xCE = { 2248, 12}, - 0xCF = { 2260, 6}, - 0xD0 = { 2266, 4}, - 0xD1 = { 2270, 4}, - 0xD2 = { 2274, 4}, - 0xD3 = { 2278, 2}, - 0xD4 = { 2280, 4}, - 0xD5 = { 2284, 4}, - 0xD6 = { 2288, 2}, - 0xD7 = { 2290, 2}, - 0xD8 = { 2292, 4}, - 0xD9 = { 2296, 4}, - 0xDA = { 2300, 2}, - 0xDB = { 2302, 2}, - 0xDC = { 2304, 4}, - 0xDD = { 2308, 4}, - 0xDE = { 2312, 2}, - 0xDF = { 2314, 2}, - 0xE0 = { 2316, 19}, - 0xE1 = { 2335, 14}, - 0xE2 = { 2349, 19}, - 0xE3 = { 2368, 15}, - 0xE4 = { 2383, 17}, - 0xE5 = { 2400, 13}, - 0xE6 = { 2413, 18}, - 0xE7 = { 2431, 15}, - 0xE8 = { 2446, 14}, - 0xE9 = { 2460, 11}, - 0xEA = { 2471, 10}, - 0xEB = { 2481, 77}, - 0xEC = { 2558, 15}, - 0xED = { 2573, 11}, - 0xEE = { 2584, 12}, - 0xEF = { 2596, 78}, - 0xF0 = { 2674, 3}, - 0xF1 = { 2677, 3}, - 0xF2 = { 2680, 3}, - 0xF3 = { 2683, 3}, - 0xF4 = { 2686, 3}, - 0xF5 = { 2689, 3}, - 0xF6 = { 2692, 3}, - 0xF7 = { 2695, 3}, - 0xF8 = { 2698, 1}, - 0xF9 = { 2699, 1}, - 0xFA = { 2700, 1}, - 0xFB = { 2701, 1}, - 0xFC = { 2702, 1}, - 0xFD = { 2703, 1}, - 0xFE = { 2704, 1}, - 0xFF = { 2705, 1}, + 0x88 = { 2040, 1}, + 0x89 = { 2041, 2}, + 0x8A = { 2043, 1}, + 0x8B = { 2044, 3}, + 0x8C = { 2047, 1}, + 0x8D = { 2048, 1}, + 0x8E = { 2049, 1}, + 0x8F = { 2050, 1}, + 0x90 = { 2051, 1}, + 0x91 = { 2052, 2}, + 0x92 = { 2054, 2}, + 0x93 = { 2056, 2}, + 0x94 = { 2058, 1}, + 0x95 = { 2059, 1}, + 0x96 = { 2060, 1}, + 0x97 = { 2061, 1}, + 0x98 = { 2062, 1}, + 0x99 = { 2063, 2}, + 0x9A = { 2065, 1}, + 0x9B = { 2066, 2}, + 0x9C = { 2068, 1}, + 0x9D = { 2069, 1}, + 0x9E = { 2070, 1}, + 0x9F = { 2071, 1}, + 0xA0 = { 2072, 2}, + 0xA1 = { 2074, 2}, + 0xA2 = { 2076, 2}, + 0xA3 = { 2078, 2}, + 0xA4 = { 2080, 2}, + 0xA5 = { 2082, 2}, + 0xA6 = { 2084, 2}, + 0xA7 = { 2086, 2}, + 0xA8 = { 2088, 2}, + 0xA9 = { 2090, 2}, + 0xAA = { 2092, 2}, + 0xAB = { 2094, 2}, + 0xAC = { 2096, 2}, + 0xAD = { 2098, 2}, + 0xAE = { 2100, 2}, + 0xAF = { 2102, 2}, + 0xB0 = { 2104, 2}, + 0xB1 = { 2106, 2}, + 0xB2 = { 2108, 2}, + 0xB3 = { 2110, 2}, + 0xB4 = { 2112, 2}, + 0xB5 = { 2114, 2}, + 0xB6 = { 2116, 2}, + 0xB7 = { 2118, 2}, + 0xB8 = { 2120, 2}, + 0xB9 = { 2122, 2}, + 0xBA = { 2124, 2}, + 0xBB = { 2126, 2}, + 0xBC = { 2128, 2}, + 0xBD = { 2130, 2}, + 0xBE = { 2132, 2}, + 0xBF = { 2134, 2}, + 0xC0 = { 2136, 7}, + 0xC1 = { 2143, 4}, + 0xC2 = { 2147, 12}, + 0xC3 = { 2159, 5}, + 0xC4 = { 2164, 11}, + 0xC5 = { 2175, 8}, + 0xC6 = { 2183, 12}, + 0xC7 = { 2195, 5}, + 0xC8 = { 2200, 6}, + 0xC9 = { 2206, 6}, + 0xCA = { 2212, 12}, + 0xCB = { 2224, 8}, + 0xCC = { 2232, 6}, + 0xCD = { 2238, 6}, + 0xCE = { 2244, 12}, + 0xCF = { 2256, 6}, + 0xD0 = { 2262, 4}, + 0xD1 = { 2266, 4}, + 0xD2 = { 2270, 4}, + 0xD3 = { 2274, 2}, + 0xD4 = { 2276, 4}, + 0xD5 = { 2280, 4}, + 0xD6 = { 2284, 2}, + 0xD7 = { 2286, 2}, + 0xD8 = { 2288, 4}, + 0xD9 = { 2292, 4}, + 0xDA = { 2296, 2}, + 0xDB = { 2298, 2}, + 0xDC = { 2300, 4}, + 0xDD = { 2304, 4}, + 0xDE = { 2308, 2}, + 0xDF = { 2310, 2}, + 0xE0 = { 2312, 19}, + 0xE1 = { 2331, 14}, + 0xE2 = { 2345, 19}, + 0xE3 = { 2364, 15}, + 0xE4 = { 2379, 17}, + 0xE5 = { 2396, 13}, + 0xE6 = { 2409, 18}, + 0xE7 = { 2427, 15}, + 0xE8 = { 2442, 14}, + 0xE9 = { 2456, 11}, + 0xEA = { 2467, 10}, + 0xEB = { 2477, 77}, + 0xEC = { 2554, 15}, + 0xED = { 2569, 11}, + 0xEE = { 2580, 12}, + 0xEF = { 2592, 78}, + 0xF0 = { 2670, 3}, + 0xF1 = { 2673, 3}, + 0xF2 = { 2676, 3}, + 0xF3 = { 2679, 3}, + 0xF4 = { 2682, 3}, + 0xF5 = { 2685, 3}, + 0xF6 = { 2688, 3}, + 0xF7 = { 2691, 3}, + 0xF8 = { 2694, 1}, + 0xF9 = { 2695, 1}, + 0xFA = { 2696, 1}, + 0xFB = { 2697, 1}, + 0xFC = { 2698, 1}, + 0xFD = { 2699, 1}, + 0xFE = { 2700, 1}, + 0xFF = { 2701, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2706, 23}, - 0x75 = { 2729, 19}, - 0x76 = { 2748, 19}, - 0x77 = { 2767, 104}, - 0x78 = { 2871, 31}, - 0x79 = { 2902, 38}, - 0x7A = { 2940, 23}, - 0x7B = { 2963, 14}, - 0x7C = { 2977, 20}, - 0x7D = { 2997, 71}, - 0x7E = { 3068, 23}, - 0x7F = { 3091, 126}, + 0x74 = { 2702, 23}, + 0x75 = { 2725, 19}, + 0x76 = { 2744, 19}, + 0x77 = { 2763, 104}, + 0x78 = { 2867, 31}, + 0x79 = { 2898, 38}, + 0x7A = { 2936, 23}, + 0x7B = { 2959, 14}, + 0x7C = { 2973, 20}, + 0x7D = { 2993, 71}, + 0x7E = { 3064, 23}, + 0x7F = { 3087, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3217, 1}, - 0x01 = { 3218, 1}, - 0x02 = { 3219, 1}, - 0x03 = { 3220, 1}, - 0x04 = { 3221, 1}, - 0x05 = { 3222, 1}, - 0x06 = { 3223, 2}, - 0x07 = { 3225, 2}, - 0x08 = { 3227, 1}, - 0x09 = { 3228, 1}, - 0x0A = { 3229, 1}, - 0x0B = { 3230, 1}, - 0x0C = { 3231, 1}, - 0x0D = { 3232, 1}, - 0x0E = { 3233, 1}, - 0x0F = { 3234, 1}, - 0x10 = { 3235, 16}, - 0x11 = { 3251, 7}, - 0x12 = { 3258, 1}, - 0x13 = { 3259, 1}, - 0x14 = { 3260, 2}, - 0x15 = { 3262, 2}, - 0x16 = { 3264, 2}, - 0x17 = { 3266, 2}, - 0x18 = { 3268, 1}, - 0x19 = { 3269, 1}, - 0x1A = { 3270, 1}, - 0x1B = { 3271, 1}, - 0x1C = { 3272, 1}, - 0x1D = { 3273, 1}, - 0x1E = { 3274, 1}, - 0x1F = { 3275, 1}, - 0x20 = { 3276, 1}, - 0x21 = { 3277, 1}, - 0x22 = { 3278, 1}, - 0x23 = { 3279, 1}, - 0x24 = { 3280, 1}, - 0x25 = { 3281, 1}, - 0x26 = { 3282, 1}, - 0x27 = { 3283, 1}, - 0x28 = { 3284, 1}, - 0x29 = { 3285, 1}, - 0x2A = { 3286, 1}, - 0x2B = { 3287, 1}, - 0x2C = { 3288, 7}, - 0x2D = { 3295, 2}, - 0x2E = { 3297, 4}, - 0x2F = { 3301, 8}, - 0x30 = { 3309, 1}, - 0x31 = { 3310, 1}, - 0x32 = { 3311, 1}, - 0x33 = { 3312, 1}, - 0x34 = { 3313, 1}, - 0x35 = { 3314, 1}, - 0x36 = { 3315, 1}, - 0x37 = { 3316, 3}, - 0x38 = { 3319, 1}, - 0x39 = { 3320, 1}, + 0x00 = { 3213, 1}, + 0x01 = { 3214, 1}, + 0x02 = { 3215, 1}, + 0x03 = { 3216, 1}, + 0x04 = { 3217, 1}, + 0x05 = { 3218, 1}, + 0x06 = { 3219, 2}, + 0x07 = { 3221, 2}, + 0x08 = { 3223, 1}, + 0x09 = { 3224, 1}, + 0x0A = { 3225, 1}, + 0x0B = { 3226, 1}, + 0x0C = { 3227, 1}, + 0x0D = { 3228, 1}, + 0x0E = { 3229, 1}, + 0x0F = { 3230, 1}, + 0x10 = { 3231, 16}, + 0x11 = { 3247, 7}, + 0x12 = { 3254, 1}, + 0x13 = { 3255, 1}, + 0x14 = { 3256, 2}, + 0x15 = { 3258, 2}, + 0x16 = { 3260, 2}, + 0x17 = { 3262, 2}, + 0x18 = { 3264, 1}, + 0x19 = { 3265, 1}, + 0x1A = { 3266, 1}, + 0x1B = { 3267, 1}, + 0x1C = { 3268, 1}, + 0x1D = { 3269, 1}, + 0x1E = { 3270, 1}, + 0x1F = { 3271, 1}, + 0x20 = { 3272, 1}, + 0x21 = { 3273, 1}, + 0x22 = { 3274, 1}, + 0x23 = { 3275, 1}, + 0x24 = { 3276, 1}, + 0x25 = { 3277, 1}, + 0x26 = { 3278, 1}, + 0x27 = { 3279, 1}, + 0x28 = { 3280, 1}, + 0x29 = { 3281, 1}, + 0x2A = { 3282, 1}, + 0x2B = { 3283, 1}, + 0x2C = { 3284, 7}, + 0x2D = { 3291, 2}, + 0x2E = { 3293, 4}, + 0x2F = { 3297, 8}, + 0x30 = { 3305, 1}, + 0x31 = { 3306, 1}, + 0x32 = { 3307, 1}, + 0x33 = { 3308, 1}, + 0x34 = { 3309, 1}, + 0x35 = { 3310, 1}, + 0x36 = { 3311, 1}, + 0x37 = { 3312, 3}, + 0x38 = { 3315, 1}, + 0x39 = { 3316, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3321, 6}, - 0xE85 = { 3327, 2}, - 0xE86 = { 3329, 1}, - 0xE87 = { 3330, 1}, - 0xE88 = { 3331, 1}, - 0xE89 = { 3332, 1}, - 0xE8A = { 3333, 1}, - 0xE8B = { 3334, 2}, - 0xE8C = { 3336, 4}, - 0xE8D = { 3340, 6}, - 0xE8E = { 3346, 1}, - 0xE8F = { 3347, 1}, - 0xE90 = { 3348, 1}, - 0xE91 = { 3349, 1}, - 0xE92 = { 3350, 2}, - 0xE93 = { 3352, 1}, - 0xE94 = { 3353, 1}, - 0xE95 = { 3354, 1}, - 0xE96 = { 3355, 1}, - 0xE97 = { 3356, 2}, - 0xE9C = { 3358, 1}, - 0xE9D = { 3359, 1}, - 0xE9E = { 3360, 1}, - 0xE9F = { 3361, 1}, - 0xEA0 = { 3362, 2}, - 0xEA1 = { 3364, 3}, - 0xEA2 = { 3367, 1}, - 0xEA3 = { 3368, 1}, - 0xEA4 = { 3369, 7}, - 0xEA5 = { 3376, 7}, - 0xEA6 = { 3383, 1}, - 0xEA7 = { 3384, 1}, - 0xEA8 = { 3385, 1}, - 0xEA9 = { 3386, 2}, - 0xEB1 = { 3388, 1}, - 0xEB4 = { 3389, 1}, - 0xEB5 = { 3390, 1}, - 0xEB6 = { 3391, 1}, - 0xEB7 = { 3392, 1}, - 0xEBB = { 3393, 1}, - 0xEBC = { 3394, 1}, - 0xEBD = { 3395, 1}, - 0xEC0 = { 3396, 2}, - 0xEC1 = { 3398, 1}, - 0xEC2 = { 3399, 3}, - 0xEC3 = { 3402, 2}, - 0xEC4 = { 3404, 2}, - 0xEC5 = { 3406, 1}, - 0xEC6 = { 3407, 7}, - 0xEC7 = { 3414, 2}, - 0xEC8 = { 3416, 1}, - 0xEC9 = { 3417, 1}, - 0xECA = { 3418, 2}, - 0xECB = { 3420, 2}, - 0xECC = { 3422, 1}, - 0xECD = { 3423, 1}, - 0xECE = { 3424, 2}, - 0xECF = { 3426, 2}, - 0xED6 = { 3428, 4}, - 0xED8 = { 3432, 4}, - 0xED9 = { 3436, 4}, - 0xEDC = { 3440, 4}, - 0xEDD = { 3444, 4}, - 0xEE0 = { 3448, 24}, - 0xEE1 = { 3472, 23}, - 0xEE2 = { 3495, 22}, - 0xEE3 = { 3517, 29}, - 0xEE4 = { 3546, 23}, - 0xEE5 = { 3569, 22}, - 0xEE6 = { 3591, 22}, - 0xEE7 = { 3613, 29}, - 0xEE8 = { 3642, 28}, - 0xEE9 = { 3670, 12}, - 0xEEA = { 3682, 13}, - 0xEEB = { 3695, 18}, - 0xEEC = { 3713, 27}, - 0xEED = { 3740, 13}, - 0xEEE = { 3753, 22}, - 0xEEF = { 3775, 23}, - 0xEF0 = { 3798, 15}, - 0xEF1 = { 3813, 15}, - 0xEF2 = { 3828, 15}, - 0xEF3 = { 3843, 15}, - 0xEF4 = { 3858, 15}, - 0xEF5 = { 3873, 15}, - 0xEF6 = { 3888, 15}, - 0xEF7 = { 3903, 15}, - 0xEF8 = { 3918, 3}, - 0xEF9 = { 3921, 3}, - 0xEFA = { 3924, 3}, - 0xEFB = { 3927, 3}, - 0xEFC = { 3930, 3}, - 0xEFD = { 3933, 3}, - 0xEFE = { 3936, 3}, - 0xEFF = { 3939, 3}, - 0xF00 = { 3942, 12}, - 0xF01 = { 3954, 11}, - 0xF02 = { 3965, 8}, - 0xF03 = { 3973, 8}, - 0xF04 = { 3981, 9}, - 0xF05 = { 3990, 6}, - 0xF06 = { 3996, 5}, - 0xF07 = { 4001, 5}, - 0xF08 = { 4006, 6}, - 0xF09 = { 4012, 6}, - 0xF0A = { 4018, 4}, - 0xF0B = { 4022, 4}, - 0xF0C = { 4026, 4}, - 0xF0D = { 4030, 3}, - 0xF0E = { 4033, 4}, - 0xF0F = { 4037, 4}, - 0xF10 = { 4041, 7}, - 0xF11 = { 4048, 7}, - 0xF12 = { 4055, 6}, - 0xF13 = { 4061, 6}, - 0xF14 = { 4067, 5}, - 0xF15 = { 4072, 4}, - 0xF16 = { 4076, 5}, - 0xF17 = { 4081, 5}, - 0xF18 = { 4086, 5}, - 0xF19 = { 4091, 4}, - 0xF1A = { 4095, 4}, - 0xF1B = { 4099, 5}, - 0xF1C = { 4104, 5}, - 0xF1D = { 4109, 4}, - 0xF1E = { 4113, 4}, - 0xF1F = { 4117, 4}, - 0xF20 = { 4121, 5}, - 0xF21 = { 4126, 4}, - 0xF22 = { 4130, 4}, - 0xF23 = { 4134, 4}, - 0xF24 = { 4138, 5}, - 0xF25 = { 4143, 3}, - 0xF26 = { 4146, 4}, - 0xF27 = { 4150, 4}, - 0xF28 = { 4154, 5}, - 0xF29 = { 4159, 4}, - 0xF2A = { 4163, 4}, - 0xF2B = { 4167, 4}, - 0xF2C = { 4171, 5}, - 0xF2D = { 4176, 3}, - 0xF2E = { 4179, 4}, - 0xF2F = { 4183, 4}, - 0xF30 = { 4187, 6}, - 0xF31 = { 4193, 4}, - 0xF32 = { 4197, 6}, - 0xF33 = { 4203, 4}, - 0xF34 = { 4207, 5}, - 0xF35 = { 4212, 3}, - 0xF36 = { 4215, 6}, - 0xF37 = { 4221, 4}, - 0xF38 = { 4225, 7}, - 0xF39 = { 4232, 4}, - 0xF3A = { 4236, 19}, - 0xF3B = { 4255, 9}, - 0xF3C = { 4264, 5}, - 0xF3D = { 4269, 3}, - 0xF3E = { 4272, 5}, - 0xF3F = { 4277, 4}, - 0xF40 = { 4281, 7}, - 0xF41 = { 4288, 7}, - 0xF42 = { 4295, 5}, - 0xF43 = { 4300, 5}, - 0xF44 = { 4305, 7}, - 0xF45 = { 4312, 6}, - 0xF46 = { 4318, 5}, - 0xF47 = { 4323, 5}, - 0xF48 = { 4328, 6}, - 0xF49 = { 4334, 6}, - 0xF4A = { 4340, 4}, - 0xF4B = { 4344, 4}, - 0xF4C = { 4348, 4}, - 0xF4D = { 4352, 3}, - 0xF4E = { 4355, 4}, - 0xF4F = { 4359, 4}, - 0xF50 = { 4363, 5}, - 0xF51 = { 4368, 5}, - 0xF52 = { 4373, 4}, - 0xF53 = { 4377, 4}, - 0xF54 = { 4381, 5}, - 0xF55 = { 4386, 4}, - 0xF56 = { 4390, 5}, - 0xF57 = { 4395, 5}, - 0xF58 = { 4400, 5}, - 0xF59 = { 4405, 4}, - 0xF5A = { 4409, 4}, - 0xF5B = { 4413, 5}, - 0xF5C = { 4418, 5}, - 0xF5D = { 4423, 4}, - 0xF5E = { 4427, 4}, - 0xF5F = { 4431, 4}, - 0xF60 = { 4435, 5}, - 0xF61 = { 4440, 4}, - 0xF62 = { 4444, 4}, - 0xF63 = { 4448, 4}, - 0xF64 = { 4452, 5}, - 0xF65 = { 4457, 3}, - 0xF66 = { 4460, 4}, - 0xF67 = { 4464, 4}, - 0xF68 = { 4468, 5}, - 0xF69 = { 4473, 4}, - 0xF6A = { 4477, 4}, - 0xF6B = { 4481, 4}, - 0xF6C = { 4485, 5}, - 0xF6D = { 4490, 3}, - 0xF6E = { 4493, 4}, - 0xF6F = { 4497, 4}, - 0xF70 = { 4501, 5}, - 0xF71 = { 4506, 4}, - 0xF72 = { 4510, 4}, - 0xF73 = { 4514, 4}, - 0xF74 = { 4518, 4}, - 0xF75 = { 4522, 3}, - 0xF76 = { 4525, 4}, - 0xF77 = { 4529, 4}, - 0xF78 = { 4533, 8}, - 0xF79 = { 4541, 4}, - 0xF7A = { 4545, 4}, - 0xF7B = { 4549, 4}, - 0xF7C = { 4553, 4}, - 0xF7D = { 4557, 3}, - 0xF7E = { 4560, 4}, - 0xF7F = { 4564, 5}, - 0xF80 = { 4569, 1}, - 0xF81 = { 4570, 1}, - 0xF82 = { 4571, 1}, - 0xF83 = { 4572, 2}, - 0xF84 = { 4574, 1}, - 0xF85 = { 4575, 2}, - 0xF88 = { 4577, 1}, - 0xF89 = { 4578, 2}, - 0xF8A = { 4580, 1}, - 0xF8B = { 4581, 1}, - 0xF8C = { 4582, 1}, - 0xF8D = { 4583, 2}, - 0xF91 = { 4585, 1}, - 0xF93 = { 4586, 1}, - 0xF99 = { 4587, 2}, - 0xF9B = { 4589, 1}, - 0xFA0 = { 4590, 3}, - 0xFA1 = { 4593, 3}, - 0xFA2 = { 4596, 3}, - 0xFA3 = { 4599, 3}, - 0xFA4 = { 4602, 3}, - 0xFA5 = { 4605, 3}, - 0xFA6 = { 4608, 1}, - 0xFA7 = { 4609, 1}, - 0xFA8 = { 4610, 10}, - 0xFA9 = { 4620, 10}, - 0xFAA = { 4630, 6}, - 0xFAB = { 4636, 1}, - 0xFAC = { 4637, 6}, - 0xFAD = { 4643, 6}, - 0xFAE = { 4649, 6}, - 0xFB0 = { 4655, 3}, - 0xFB5 = { 4658, 1}, - 0xFB8 = { 4659, 1}, - 0xFB9 = { 4660, 1}, - 0xFBA = { 4661, 1}, - 0xFBB = { 4662, 1}, - 0xFBC = { 4663, 1}, - 0xFBE = { 4664, 1}, - 0xFC0 = { 4665, 1}, - 0xFC1 = { 4666, 1}, - 0xFC2 = { 4667, 3}, - 0xFC3 = { 4670, 3}, - 0xFC4 = { 4673, 1}, - 0xFC5 = { 4674, 1}, - 0xFC6 = { 4675, 2}, - 0xFC7 = { 4677, 2}, - 0xFC8 = { 4679, 7}, - 0xFC9 = { 4686, 11}, - 0xFCA = { 4697, 3}, - 0xFCB = { 4700, 3}, - 0xFCC = { 4703, 7}, - 0xFCD = { 4710, 7}, - 0xFCE = { 4717, 2}, - 0xFCF = { 4719, 2}, - 0xFD2 = { 4721, 1}, - 0xFD3 = { 4722, 1}, - 0xFD9 = { 4723, 4}, - 0xFDA = { 4727, 1}, - 0xFDB = { 4728, 1}, - 0xFE0 = { 4729, 28}, - 0xFE1 = { 4757, 26}, - 0xFE2 = { 4783, 26}, - 0xFE3 = { 4809, 32}, - 0xFE4 = { 4841, 29}, - 0xFE5 = { 4870, 27}, - 0xFE6 = { 4897, 27}, - 0xFE7 = { 4924, 33}, - 0xFE8 = { 4957, 32}, - 0xFE9 = { 4989, 17}, - 0xFEA = { 5006, 17}, - 0xFEB = { 5023, 29}, - 0xFEC = { 5052, 31}, - 0xFED = { 5083, 18}, - 0xFEE = { 5101, 26}, - 0xFEF = { 5127, 32}, - 0xFF0 = { 5159, 19}, - 0xFF1 = { 5178, 18}, - 0xFF2 = { 5196, 17}, - 0xFF3 = { 5213, 17}, - 0xFF4 = { 5230, 19}, - 0xFF5 = { 5249, 18}, - 0xFF6 = { 5267, 17}, - 0xFF7 = { 5284, 17}, - 0xFF8 = { 5301, 4}, - 0xFF9 = { 5305, 4}, - 0xFFA = { 5309, 4}, - 0xFFB = { 5313, 17}, - 0xFFC = { 5330, 4}, - 0xFFD = { 5334, 4}, - 0xFFE = { 5338, 4}, - 0xFFF = { 5342, 17}, + 0xE84 = { 3317, 6}, + 0xE85 = { 3323, 2}, + 0xE86 = { 3325, 1}, + 0xE87 = { 3326, 1}, + 0xE88 = { 3327, 1}, + 0xE89 = { 3328, 1}, + 0xE8A = { 3329, 1}, + 0xE8B = { 3330, 2}, + 0xE8C = { 3332, 4}, + 0xE8D = { 3336, 6}, + 0xE8E = { 3342, 1}, + 0xE8F = { 3343, 1}, + 0xE90 = { 3344, 1}, + 0xE91 = { 3345, 1}, + 0xE92 = { 3346, 2}, + 0xE93 = { 3348, 1}, + 0xE94 = { 3349, 1}, + 0xE95 = { 3350, 1}, + 0xE96 = { 3351, 1}, + 0xE97 = { 3352, 2}, + 0xE9C = { 3354, 1}, + 0xE9D = { 3355, 1}, + 0xE9E = { 3356, 1}, + 0xE9F = { 3357, 1}, + 0xEA0 = { 3358, 1}, + 0xEA1 = { 3359, 2}, + 0xEA2 = { 3361, 1}, + 0xEA3 = { 3362, 1}, + 0xEA4 = { 3363, 6}, + 0xEA5 = { 3369, 2}, + 0xEA6 = { 3371, 1}, + 0xEA7 = { 3372, 1}, + 0xEA8 = { 3373, 1}, + 0xEA9 = { 3374, 2}, + 0xEB1 = { 3376, 1}, + 0xEB4 = { 3377, 1}, + 0xEB5 = { 3378, 1}, + 0xEB6 = { 3379, 1}, + 0xEB7 = { 3380, 1}, + 0xEBB = { 3381, 1}, + 0xEBC = { 3382, 1}, + 0xEBD = { 3383, 1}, + 0xEC0 = { 3384, 2}, + 0xEC1 = { 3386, 1}, + 0xEC2 = { 3387, 3}, + 0xEC3 = { 3390, 2}, + 0xEC4 = { 3392, 2}, + 0xEC5 = { 3394, 1}, + 0xEC6 = { 3395, 7}, + 0xEC7 = { 3402, 2}, + 0xEC8 = { 3404, 1}, + 0xEC9 = { 3405, 1}, + 0xECA = { 3406, 2}, + 0xECB = { 3408, 2}, + 0xECC = { 3410, 1}, + 0xECD = { 3411, 1}, + 0xECE = { 3412, 2}, + 0xECF = { 3414, 2}, + 0xED6 = { 3416, 4}, + 0xED8 = { 3420, 4}, + 0xED9 = { 3424, 4}, + 0xEDC = { 3428, 4}, + 0xEDD = { 3432, 4}, + 0xEE0 = { 3436, 24}, + 0xEE1 = { 3460, 23}, + 0xEE2 = { 3483, 22}, + 0xEE3 = { 3505, 29}, + 0xEE4 = { 3534, 23}, + 0xEE5 = { 3557, 22}, + 0xEE6 = { 3579, 22}, + 0xEE7 = { 3601, 29}, + 0xEE8 = { 3630, 28}, + 0xEE9 = { 3658, 12}, + 0xEEA = { 3670, 13}, + 0xEEB = { 3683, 18}, + 0xEEC = { 3701, 27}, + 0xEED = { 3728, 13}, + 0xEEE = { 3741, 22}, + 0xEEF = { 3763, 23}, + 0xEF0 = { 3786, 15}, + 0xEF1 = { 3801, 15}, + 0xEF2 = { 3816, 15}, + 0xEF3 = { 3831, 15}, + 0xEF4 = { 3846, 15}, + 0xEF5 = { 3861, 15}, + 0xEF6 = { 3876, 15}, + 0xEF7 = { 3891, 15}, + 0xEF8 = { 3906, 3}, + 0xEF9 = { 3909, 3}, + 0xEFA = { 3912, 3}, + 0xEFB = { 3915, 3}, + 0xEFC = { 3918, 3}, + 0xEFD = { 3921, 3}, + 0xEFE = { 3924, 3}, + 0xEFF = { 3927, 3}, + 0xF00 = { 3930, 11}, + 0xF01 = { 3941, 10}, + 0xF02 = { 3951, 8}, + 0xF03 = { 3959, 8}, + 0xF04 = { 3967, 8}, + 0xF05 = { 3975, 5}, + 0xF06 = { 3980, 5}, + 0xF07 = { 3985, 5}, + 0xF08 = { 3990, 6}, + 0xF09 = { 3996, 6}, + 0xF0A = { 4002, 4}, + 0xF0B = { 4006, 4}, + 0xF0C = { 4010, 4}, + 0xF0D = { 4014, 3}, + 0xF0E = { 4017, 4}, + 0xF0F = { 4021, 4}, + 0xF10 = { 4025, 7}, + 0xF11 = { 4032, 7}, + 0xF12 = { 4039, 6}, + 0xF13 = { 4045, 6}, + 0xF14 = { 4051, 5}, + 0xF15 = { 4056, 4}, + 0xF16 = { 4060, 5}, + 0xF17 = { 4065, 5}, + 0xF18 = { 4070, 5}, + 0xF19 = { 4075, 4}, + 0xF1A = { 4079, 4}, + 0xF1B = { 4083, 5}, + 0xF1C = { 4088, 5}, + 0xF1D = { 4093, 4}, + 0xF1E = { 4097, 4}, + 0xF1F = { 4101, 4}, + 0xF20 = { 4105, 5}, + 0xF21 = { 4110, 4}, + 0xF22 = { 4114, 4}, + 0xF23 = { 4118, 4}, + 0xF24 = { 4122, 5}, + 0xF25 = { 4127, 3}, + 0xF26 = { 4130, 4}, + 0xF27 = { 4134, 4}, + 0xF28 = { 4138, 5}, + 0xF29 = { 4143, 4}, + 0xF2A = { 4147, 4}, + 0xF2B = { 4151, 4}, + 0xF2C = { 4155, 5}, + 0xF2D = { 4160, 3}, + 0xF2E = { 4163, 4}, + 0xF2F = { 4167, 4}, + 0xF30 = { 4171, 6}, + 0xF31 = { 4177, 4}, + 0xF32 = { 4181, 6}, + 0xF33 = { 4187, 4}, + 0xF34 = { 4191, 5}, + 0xF35 = { 4196, 3}, + 0xF36 = { 4199, 6}, + 0xF37 = { 4205, 4}, + 0xF38 = { 4209, 7}, + 0xF39 = { 4216, 4}, + 0xF3A = { 4220, 19}, + 0xF3B = { 4239, 9}, + 0xF3C = { 4248, 5}, + 0xF3D = { 4253, 3}, + 0xF3E = { 4256, 5}, + 0xF3F = { 4261, 4}, + 0xF40 = { 4265, 6}, + 0xF41 = { 4271, 6}, + 0xF42 = { 4277, 5}, + 0xF43 = { 4282, 5}, + 0xF44 = { 4287, 6}, + 0xF45 = { 4293, 5}, + 0xF46 = { 4298, 5}, + 0xF47 = { 4303, 5}, + 0xF48 = { 4308, 6}, + 0xF49 = { 4314, 6}, + 0xF4A = { 4320, 4}, + 0xF4B = { 4324, 4}, + 0xF4C = { 4328, 4}, + 0xF4D = { 4332, 3}, + 0xF4E = { 4335, 4}, + 0xF4F = { 4339, 4}, + 0xF50 = { 4343, 5}, + 0xF51 = { 4348, 5}, + 0xF52 = { 4353, 4}, + 0xF53 = { 4357, 4}, + 0xF54 = { 4361, 5}, + 0xF55 = { 4366, 4}, + 0xF56 = { 4370, 5}, + 0xF57 = { 4375, 5}, + 0xF58 = { 4380, 5}, + 0xF59 = { 4385, 4}, + 0xF5A = { 4389, 4}, + 0xF5B = { 4393, 5}, + 0xF5C = { 4398, 5}, + 0xF5D = { 4403, 4}, + 0xF5E = { 4407, 4}, + 0xF5F = { 4411, 4}, + 0xF60 = { 4415, 5}, + 0xF61 = { 4420, 4}, + 0xF62 = { 4424, 4}, + 0xF63 = { 4428, 4}, + 0xF64 = { 4432, 5}, + 0xF65 = { 4437, 3}, + 0xF66 = { 4440, 4}, + 0xF67 = { 4444, 4}, + 0xF68 = { 4448, 5}, + 0xF69 = { 4453, 4}, + 0xF6A = { 4457, 4}, + 0xF6B = { 4461, 4}, + 0xF6C = { 4465, 5}, + 0xF6D = { 4470, 3}, + 0xF6E = { 4473, 4}, + 0xF6F = { 4477, 4}, + 0xF70 = { 4481, 5}, + 0xF71 = { 4486, 4}, + 0xF72 = { 4490, 4}, + 0xF73 = { 4494, 4}, + 0xF74 = { 4498, 4}, + 0xF75 = { 4502, 3}, + 0xF76 = { 4505, 4}, + 0xF77 = { 4509, 4}, + 0xF78 = { 4513, 8}, + 0xF79 = { 4521, 4}, + 0xF7A = { 4525, 4}, + 0xF7B = { 4529, 4}, + 0xF7C = { 4533, 4}, + 0xF7D = { 4537, 3}, + 0xF7E = { 4540, 4}, + 0xF7F = { 4544, 5}, + 0xF80 = { 4549, 1}, + 0xF81 = { 4550, 1}, + 0xF82 = { 4551, 1}, + 0xF83 = { 4552, 2}, + 0xF84 = { 4554, 1}, + 0xF85 = { 4555, 2}, + 0xF88 = { 4557, 1}, + 0xF89 = { 4558, 2}, + 0xF8A = { 4560, 1}, + 0xF8B = { 4561, 1}, + 0xF8C = { 4562, 1}, + 0xF8D = { 4563, 2}, + 0xF91 = { 4565, 1}, + 0xF93 = { 4566, 1}, + 0xF99 = { 4567, 2}, + 0xF9B = { 4569, 1}, + 0xFA0 = { 4570, 3}, + 0xFA1 = { 4573, 2}, + 0xFA2 = { 4575, 3}, + 0xFA3 = { 4578, 2}, + 0xFA4 = { 4580, 3}, + 0xFA5 = { 4583, 2}, + 0xFA6 = { 4585, 1}, + 0xFA8 = { 4586, 10}, + 0xFA9 = { 4596, 10}, + 0xFAA = { 4606, 6}, + 0xFAB = { 4612, 1}, + 0xFAC = { 4613, 6}, + 0xFAD = { 4619, 6}, + 0xFAE = { 4625, 6}, + 0xFB0 = { 4631, 3}, + 0xFB5 = { 4634, 1}, + 0xFB8 = { 4635, 1}, + 0xFB9 = { 4636, 1}, + 0xFBA = { 4637, 1}, + 0xFBB = { 4638, 1}, + 0xFBC = { 4639, 1}, + 0xFBE = { 4640, 1}, + 0xFC0 = { 4641, 1}, + 0xFC1 = { 4642, 1}, + 0xFC2 = { 4643, 3}, + 0xFC3 = { 4646, 3}, + 0xFC4 = { 4649, 1}, + 0xFC5 = { 4650, 1}, + 0xFC6 = { 4651, 2}, + 0xFC7 = { 4653, 2}, + 0xFC8 = { 4655, 7}, + 0xFC9 = { 4662, 11}, + 0xFCA = { 4673, 3}, + 0xFCB = { 4676, 3}, + 0xFCC = { 4679, 7}, + 0xFCD = { 4686, 7}, + 0xFCE = { 4693, 2}, + 0xFCF = { 4695, 2}, + 0xFD2 = { 4697, 1}, + 0xFD3 = { 4698, 1}, + 0xFD9 = { 4699, 4}, + 0xFDA = { 4703, 1}, + 0xFDB = { 4704, 1}, + 0xFE0 = { 4705, 28}, + 0xFE1 = { 4733, 26}, + 0xFE2 = { 4759, 26}, + 0xFE3 = { 4785, 32}, + 0xFE4 = { 4817, 29}, + 0xFE5 = { 4846, 27}, + 0xFE6 = { 4873, 27}, + 0xFE7 = { 4900, 33}, + 0xFE8 = { 4933, 32}, + 0xFE9 = { 4965, 17}, + 0xFEA = { 4982, 17}, + 0xFEB = { 4999, 29}, + 0xFEC = { 5028, 31}, + 0xFED = { 5059, 18}, + 0xFEE = { 5077, 26}, + 0xFEF = { 5103, 32}, + 0xFF0 = { 5135, 19}, + 0xFF1 = { 5154, 18}, + 0xFF2 = { 5172, 17}, + 0xFF3 = { 5189, 17}, + 0xFF4 = { 5206, 19}, + 0xFF5 = { 5225, 18}, + 0xFF6 = { 5243, 17}, + 0xFF7 = { 5260, 17}, + 0xFF8 = { 5277, 4}, + 0xFF9 = { 5281, 4}, + 0xFFA = { 5285, 4}, + 0xFFB = { 5289, 17}, + 0xFFC = { 5306, 4}, + 0xFFD = { 5310, 4}, + 0xFFE = { 5314, 4}, + 0xFFF = { 5318, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 66dc5bdfc..9bcca5dae 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -17,10 +17,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .EOR { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -139,10 +139,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .BIC { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -168,28 +168,28 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSR { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ASR { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ROR { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RRX { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} }, // .ADR @@ -799,13 +799,13 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .STLEXD { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDM - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STM - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDMIB @@ -1012,27 +1012,27 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VABS { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VNEG { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VSQRT @@ -1109,22 +1109,22 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, @@ -1429,20 +1429,20 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMOVN - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, // .VQMOVN - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, // .VQMOVUN - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, // .VMOVL { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1468,10 +1468,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1485,10 +1485,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1502,10 +1502,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1521,10 +1521,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1540,10 +1540,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -1603,11 +1603,11 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, // .VPADDL - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VPADAL { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1706,23 +1706,23 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCLS - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, // .VCLZ - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCNT { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -1730,17 +1730,17 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VREV32 - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, // .VREV64 - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VEXT { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, @@ -1755,24 +1755,24 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VUZP - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VZIP - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VDUP { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 1b4ef0d76fdf0f4fe94248d6e8eae01468d2e2a9..c75971ba562968bce3bb9d5a771edc47d7be903e 100644 GIT binary patch delta 2143 zcmcZ?ye@dd78dtR#tg%A6ChJ3FJ(2K zY{veD*`CR6vMxs<^E<}3lNWNxPF}$-Hu(xi0kbcY&ty*yL*q=QOh%B+AbYczvYB$2 zDi}){%NWa{HWx7FGZr%DG3GMmG37HAFoEn{%^5v8hR15M1D6c&UD z=>pRwri)DHnXWM1V7kh5o#`6WWv07Kx0r4+-DbMSbcg9l4$~v1$4vK`9x^>(ddBpW z={eIYrk6}Fm|iozVS3B-k?8}|d!~0xUzt8LePQ~<^n>Xq(|4wCOn;evG5u!x!}Ont zk@+7J12Zc#6Eib23o|=28#4zpCo?xQ7c(z24>KRLATvL+0JAW&5VI(=$mB-u06lP= zWiX~O!a}c%v6Qidv5>Kdv6!)(F^@5yu>cWzlmBzSuV2BmlxZ2$a%e~`0f)~zrnO9~ znN~5aWLm?t5ga~Sn07JkVA{^Km1!H(PNqFfdzp4K9b`Jdw4Z4o(_y9~Oh=gxF&$?* z0S==xOsAMmGhJl5#B_n_JkwdGb4)jwt}$I_y2^Bg=`zzjrn^jcm~JxNV!F-rnCVG9 z(*vf5OploELqq5V(@UmT@DO^(^q%PhICMTUeP#N|^o{8|(+{RUOuw0aG5rOH&wnNc zW)@~<7C9FA$@_(*Cr1hK zaD!B7v%F{4Wzm`ZUPylO1R)VYkQj>2$yeOA1RGO9o3iOD0PpOBPEdOAbphOF2swOD;`lUSy( zOlDDFQDu=~QDc!~F=w%0v1GAgv0<@hv1OUcV#fmVgrJD9xEqTrT-7v|=`8Ln9xPrg zo|CObWa~j*2xkccdm)-73hae=mN=FKmPD2$mSmO`mQ=6@(pU<>j?M>rB%39NC6lFy zrIMwBrHrMRrG%vv>@AoV>RB3C8d;h^USMfsX+`n@$o;)66Il9LCb3Lpnasp8W%Esu zTvpMoEPGfEvm9pG$g+uLGs_m1T`Y%Kc5cp=Dr6ClW{qKuWp!kAVs&HnVhv;sVhv%9 zW{sKrT~1auhBcZsmeqmPoz;WYk2R7N!uMy51gqGoC_6bwUS#qsMFHj**67K96(uK6 zlGhW3sPbS92dQF>h0v2dm82(skXK=c*cUc=zJlcBS4v!y?G!X7uTT(}tfR~|`HvFc zJBhHSya)q9%7~kYdKT~qB@t=8OnEo z(w?kAtie#W7ucr|l|iggARAd@SrIHOK4y(&b!H8Ks&ruufSTkf!WzUH3KjMSvq8b( zs31ByLO}uQVc*Gx%98A$Kmp4s8Bg|8U=#I$d&Yw`3~EByzI-T_r>s;2wtV>vzvMys?&bpR$GwV*){j5h>=d&(gUC6qK zbp`7>)-9~NSP!rsV_nI*o^>nhZq|dW$64pGu4diHx}9||>tWWDtZP^|vF>2q$9jbI z6zeM14XoQ(_plyfJ;8dK^(yN%)^i-JH(AfHUS~bKIakG>WwM5*!sI&|K9l!oC`{g^ Kp)@&5vjhNhYf^Fm delta 2229 zcmZ1%d@p#z78dt(#tg<>#!SX6#%#tM#yrM+#sbDd#v;aI#xlkl#uCPA##+WI#!ALg z#&X6A#yZA&#ssTcwe_-QaKf!pC@igP9$^Y5RC*NT;Fic~F*qXzb&6vfQiDGLVV=ZG1V>Q^$3dS|dDenCvI( zauiPPU{_%N%lL2dL5}9hZX71YnM_$s*-SZ1xr`utK|ao9%45oBDqsTnwhnA7$gd!O zRzhr^yqYtbxrM2Day*auWCt#p$(wkr>K8CAWLnC!m}wEy5~dYQ%bAujtz=row3=xR z(-x*pOzW98Fl}Vo%(Rwi9n&tRZA^QZb~5c?+RC(>X*<(CroBuDnD#RrWIE1tl<64L z5vD^-hnY??onSh}bdKo^(^;m|Oy`*{GF@Q0#B_z}D$_Nl%S^YJZZchGy1{gp={D0n zraMeea+n@6-Di5l^qA=Z({rX5OwX8}GQDJa#q^r#1JfI(k4$fw-Z8yr`p)!~=`+(O zrf*DNn0_$*WctPQo9QppKc+uS|CyMXS(zD`8JJm^nV315*_pYSIheVa*_e5l1(^An z`Ivc`MVW<}MVJMdg(f$02k7AlwPMC1Mo6etF;*~^GnO%yFqSe_PX5pRz8*P*mN6}d zhtMXb%}iUsVYH5EEz?G(Jxsfqb}{W>+Rn6 zV>-ojg6SmFS*9~gr126OjnpLGu>di$#je9I@3L-yG(bOZZkb* zdQ#8yfaxLABc}V{&;fB(fy4B(bEhq_U*3q_bqOWU^$l6tiTpl&}=Cl(FQqYCU!V=CB#uCXA!4kz1%@WHJ z!xG055B6yiOEOC;OA1Q{*spmk*(^CMxh(lCnJif>1uW$(Wnf=du~f1Yu@r;-TFp|! zQp-}uQqR%^^C{S)?JOOr9_2##bn``#TvpXREL&Ojvg~0w%yO7zBg-b1%`973cCqYa zIRxkJWZAVjSgMdkI)pWbHJUY+)sfYS)s5AQHIOxkHJBAFI{CJotadbO3~MZ_1FJi$ z2dh7;A8RC3y&tPTobAjS01}-nFRwoNhCJWoEMwHhp2tDw#t%^EX# zxq_)A#Nctww z8p0Y3RTIP-g~WoHfY1LBH@L6{K=paD2C;^M?3!#UuLunVh#F_83Kx(pYb+~BCBz0_ z)}YC@@{*9Snk=bg4Dz$255zC5v8*1f;E-XBh0v2hA=IQ~F!_s;(Bup9VxnL_gVlk< z2;$et@0H{yt10kJz9-KCj~ORrt;uT2e7q1BxvqXX?tfyJ8uuf$? z!+L>r2J0Et%dAsa&$6Cpoz8le^%Cnj)^n`$Sr@P_WL?C%m~|!Vde*J1yIBvi&Sss% zI+t}G>k`>Q%OjvF>3##JZGqHS0#!?W}uQ53|lsamp diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index ce6fa5c9788bbda0fcacfd010ca623695c8148a7..c3ad6e7d879195a4272a1d51340cb07fb7813497 100644 GIT binary patch delta 2182 zcmZ3!f@%2*rU@JMKm2BARA69WWME_zV&LWxXJB9u_`uKr5>|u=vodh=@G>wkFuY=D z_%QK-7~_YH-&;A|{zEkKF)#`-FmQwPF~omhXaET-GBEHlFfuYQaD(;vzhY?k{~v4( zvT!^|c=I7H0VWBktRMp;BO}DN4-CIPeE2Z=6;BaNQV2;>0W4X<3zrl|l5_w|{^N~? z=@dbdOaMu4F666Jk@&z5@)W}Z21a%U24-atX9EWV!-vUC#x5|)he(nOK$4r|jLZ09 z_x~3Fg$+L=Cnp1gx+Vhy1M}9;7x=-#Obp1vJ7L1i4E&5-Tnr3aIt&aB%o}0Cj3~lj zLna$KiAjKs0_lOIejG07ROT>x(70f?28^_<1r zz-BWsAWMSH26>7Z**u7qAYnda)ezy$UCvin88=Lh_Y|w&z`x_400RRzgA60500V9m|X&3^#;@A&8NSlVS6eBvvMg-5~v( z3?c9o=fDU`PY>&G%EZ7$LHZ454tX2N)n)71Q8aktA6lTK&@y zTEpO49iUn#ro*)&NkX;mPmh4x8V=Wb0P0}7_ScYy2w2{SWPBD}$}0Vd3d zA`CWUa$-5udS-?yxD5>uJ(K&(q1JPuNW$&mW~hSOa{!_TWIZQ}FxVcDFvt*CX?cJJ zY{+D$ilW%lsAU$AV5r$fX4GbWkfQ3P-;YJ~=u7exG09L(!^2G|M2Spf= zB_Y=TuMpD*=QLr4I=DR!U<1LzAU!a992g*aTq^%C?w{;f1vj<{Zf64nB--+;pcz=0 zp$Ts60S0*96G0IM>j8y_tFvM|UHu&@Y2Gu&(kuxhZAg(1Q`kV=UW zq|u=vodh=@G>wkFuY=D zcrfvS7~_MD-&;A|-a|C3{~v4( zvT!^|c=I7H0VWBktRMp;BO}DN4-CIPe0VVV6;BaNQV2;>0W4X<3zrl|l5_w|{^N~? z=@dbdOaMu4F666Jk+{GQ@)W}Z21a%U24-atX9EWV!-dIA#x5|)he(nOK$4r|jLZ09 zH~$v^g$+L=Cnp1gx+Vhy1M}9;7x=-#Obp1vJ7L1i4E&5-Tnr3aIt&aB%o}0Cj3~lj zLna$KiAjKs0_lOIejG07ROT>x(70f?28^_<1r zz-BWsAWMSH26>7Z**u7qAYnda)ezy$UCvin87EAR_Y|w2z`x_400RRzgA60500V9m|X&3^#;@A&8NSlVS6eBvvL!YUE@H zfu}eJMsOmZyfFppd_H7JR&a{jd_P5t5u%lmAr!9l00Ts;Vj5g4k|Ya6tA83oYZzRs z161q8bhuU|NvPKS=@D>S!{J&FKpm`~3D=4w33YI6W&|T712Hm0z_mIsfgKDALXa># z&$5A?3KHf+Rt*u}{5z|b1?KrAcrIpO+5(RD3HhLmzC2%-ar5S@`LEa*H%~rL26Y)1 zLj@@08MMGf4>&?5zbg}il}nWf!&tzEfn31EfGoTNWCuu?nV}Nl4VDcsVMY{TupyHZ z%c0gYGgQHCXn^RM++Pm0o(n}1ZVxv@72KW!5IrF4IZ=ec_JD*zhQLb811w-eCNotO zK|CnTP>Zmh0j@`cp%!5S1KcMd)o`PbRoB4{VSuQfe6a%RK@kRINr?6TE5!7{IZc?M z4sMSFs(~j4Fj zC_^*cC-pLMiE9bq#16u1FC8+E(RV*rNjtUK3Sj|>RM5T7Pu7+5KWWqs-eZ2 e2ty0p!~+mXi2caIU;{zIsH(x9*gUJcR{{VA4k`Np diff --git a/core/rexcode/isa/arm32/tables/arm32.entries.bin b/core/rexcode/isa/arm32/tables/arm32.entries.bin index 1d706797820a288792a67d1b66ce31117af37bc4..b6b1772d5e44e8387cf1b8157340c4116f4e0661 100644 GIT binary patch delta 3002 zcmZ3!f@%2*rVW*XlP3uBOwJP&pFBtK1CIbN!zTg$4gUog82BbP3Q26j@cn7Mfcz$ye87QDY<`iIHP-kFZ z5a4h4v;kr|AA<}dT$lwe3^E2T%-is3!{m30V){@$Tu6Eh_~3d#E`sX;2~R$tC>9IV zgJK{LTn~yc8+KtXxG=KC0!$!R-BOq|Ia8@_vW~LeKd910=x{LVR5+m zh3;0?$!*5Un-3VLvQ4(J5}vGRCBE6;N`tAMpOK4;fk8`$fx&@!F)*m>FfcH%ZL0?d zq9_9cFP}d`oM{_aSb%|nn*mvP6HJ&3MR*rXn1>+%Zb$cY7T|~#%!2d z8W46eBPnk{C}%+uK7cTs4MiC4aCU}3xKkV;hD=s)5UU5LFJ=@;BzGpkBb9+^2h3N@ z49LP8V8VrHH3?cAp=ruF(8@J1b0dU13Xy?Gaw6tV-{j3 zvM@YSMH!ml4nF`fWby-7F$r+O6+w{%>zT~wCZ-RT6lQ3K>vUiQOM>hXMG*#DKe^FO z%mk{Z1+M1+vL0k%upW?6B9mQh-2_A6Ivf~5rO@ulehy;wyFmIUAdL8T>Fn2#X@ z9xx2Z!l7`Z4zM7p4uz|3U;x_yGMkYBNj0i4Cnp0Wp*A3!5(YQi0aEp1{Gt02O|SB)kA5JlP~dm+`~q zq=>1)6950RGb%7J2r)1+iZXEXGB5}*_`fn}_&=FHM+_z@0+%#^O4{ZWG5(*tAxDhy z|K#I2x)LA$vok6(FfcMOGO{vo^YDUP@QR_~!)BgbHeQMUzrl9!F)#`-FmQ{5B;!9Y zH2j~eRTVAq0U`;~D#XCe1CkZ^0Ma_Q%92e`kb#kr5n|#8hF>2(e3A9{rsa}SW zQ-Fa%oq>TtfWP6>1cdQ0VFNz6Fvwt-umCSyn41B~5QJ(@WMKyEs#%yDK24Y`uPEjQ zwHf3{xD`CuHL+nA<^maYKv9fw!sJAyw#hom;*&*{#V0!}i%)*8q_;Ur`5)`#d`;oW zA)4Zwn>4R8a&t0#4uC|5z+_)-iOn_IUQCnk>hetHkm2EC_zaCIfz2;;x3Y5cDSQr; z-w293zR44fB{m;0PGy^HVym_MM+E@NWiN z!+<2ryb&hM$iR;_TK= zB&Q$?BO6i=_fP|>;V>sQAp27Qp&HpkNQR>dBMd?Ej~~L}tQ#hCxpCF|A&h0+01FQW z27g4PGHrqhbD;=>;u;)d+$h4kV5)f-0^o);APiwb5w3@u!i*$-0HK@>MHp^42Z}J< z5OyTt1}3;_7KT8$QydUxGcg1TAc=#OPrhd-<_7i_GeZbGv>X`Wfyl`a0uM3+jGHH)cNVJ$8_38I3ODco3s?yx!6OMX!0iF4hQ}eY>M(@$IE0Z62?JTF z49R4u%HghsD4#sf1?q7=hH$tQ4G14HGK7Q70vmMz;zNk@k%S?tCkwiYIf1>*#}ENG zih&Ku%SggZNM4SB+u*>oak8SDVto=qKhq9a(qd*n7Ty9AW&xo#4Z z&$#K?*CJfX0JlVh0a+Lx48jbxaKjEjR8O{d1?9&Hj$*Ok#3{;92RD#`0qz-8VI+Hy zRU_F`2e-!oYR^8H4Z;jfa2pyJ;AukyMHrkmK*55l8eAHIghd&e;5Hm!0IQxH?*vUr zAfwwe#K6r1k`?#> z(mJ=wl5Mk5V>*k5AOj;KBgEJb48J~n0NDn0GfY?kBs}?FgP0Ul669u>WCBR?Kl|pX Ht&{iw?0w%( diff --git a/core/rexcode/isa/arm32/tables/arm32.form_idx.bin b/core/rexcode/isa/arm32/tables/arm32.form_idx.bin index f5d440b3ae738b87b68f0e39e11a11b683749835..a21e91375364b67873ec7be431d19f1d2ebb5ffe 100644 GIT binary patch delta 486 zcmaDP`ABj@3!^kA12Y3N10w?q10w??0|@XkurjbRa56AYp3f-F%)r1g@uKkL3ydbr z%nWRk*_mXS85y`Ht1~Tim0%EOkYo^L5CiFAU|snVW%k@?Yk9 zFkR2m&&4)2I2gFVUSMKiU|?ln z1ginbfV>3~19=icgFFmkF*7hRFfuTMRfE_JV3R;3NIx^w9FPnP0|NtNJ=9261||j; z28b|75y(#<@9{G5Fz_?*Fz_<)fiZ|D$iUAaz`)1A#~{GK&mahP76SuF7sy!<3~~Si z)F}*LFF?dW=7KQ9D+~;i9oVGULGET^VA!0VUEp-JcWnhqC5ND8N5MvO9a2XgFxEZ(@gc(E_1Q~=FxEOdC_!tBj zcp3N^xEUB2*ubjT8CXEZGcYl*O%`NsXJ%wzo;;gblbMHsZ}M?wV`g3k?#X|d>%nwA zOFuIU1IJ`RR>OKO1_lNu21c-RnHU%tn8BtoFmN)kGO#ePGjK34gUn=LWngDuV_;@r zVc=lk1nU4PWMly80qF**2C+eAfn3YWz{9}9z|X+Tz{kJ`WeG6wF$gm7GYB$(So{pE z3{3Ul@Buj;6iy(kKn8%q4rCz6X&^R8oP~jbffcNp0UD|xQC6r^U?wnuoro+7GLHcq vI3Rr>M}siP;UKS0c3_iY2U)|wz_dA$?J~<`8}1}_P+YMxuxy^o?aBxMXVe|L diff --git a/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin b/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin index 8083bb2baab3ed5ba6e5632b1e930e1a0a2db5ef..8f0df6fffd87e3b923a509e517b73e83d7f6936c 100644 GIT binary patch delta 369 zcmZqRXyDkO#FWa&@ROa1;Ws-Y!yk5LhX3r03=ABM42&F%3``u149pyi3@jW>3~U@s z3>+Lx3|t(H4BQ-y3_Ki+47?nS4164n4E!8S41yet3_=`C3?dwi45A#23}PIN4B{M& z3=$kn3{o6Slk1tP>)9FNIanById~ZIIanD=IJg<=IXD>FId~W*bFebZ;9z5z$HB(1 zgoB4+0|y7g4h}YkeH?5IM>u#GE^x3hT;pJ2xW&Q3aF2t9;SmQD!xIh`h8G+x3~xA? z7~XL(F?`@)Vfezq!tjHGiQyLq6T=@476t}R76ukhCI&W6CI*grPGJUVPCf=rPGJTc zPJRY&PCqglJ=VD~&;9_Lx%;bLUy8wWZ2Hb$gqQliD4HH6T==JCWd`H zObiEj7#R-oFfttCVPrVW!^m)ihmqkZ4LvuBLgk~00jjmeEf{%;aHWn9ak;Fo%bcVJ;6N z!#o~FhWR{<3=4P|85Z&|GA!a@WLV52z_6KzonaRbBg1YUMut5+Obq*Ym>3T5FfknB zVVaol9LLCTm4}hx8V@7Gbsk2B8$9d`_j#BY9`dj-JmukFc+11c@Q#O(;XMx{!v`Kl ghL1dq44-%y89wtcGJN4-X86v-$nb-QkpUL~0ODLE8vpgAgwh zg9tApgD5W}gBUL(gE%iEg9I-VhF_(485yK`85v}F85v}G85!hw85!hxnHUs#85xv# z85xv$*%&l=nHaQr85wkV85wkW85#7jn1gJv0WTw*YskyUV8qMFV9d+NV1gtLQeeu< z$Y93H$Y72nZo$jMV8zSGV9m?SV8_eE;K0ko;Ka+w;LOX;;Kj?t;KR$v;LFR%;K$3v z5WvgC5X8&K5X{TS5W>sE5QfKH5xguQD;Z*VSr`(aY>+?-FAGBk58~Irnw(_$u?Br)>IKa=&aGalw;VeHJ!)1O}h8z4W z40rfh86NVpGCbpFWq8fc!tkD-h2b+lE5i?dR))X)EDVeSEDWpyEDW3itPFetEDS;d zEDT}-EDTZttPJu3%nV8bEDUM_EDTx#tPJ`BEDXj1EDYuXEDY8HtPBnU%nZ%~EDY`f zEDYWPYz%<{EDWInYz)x?EDZ4itPCjv%na!QYz(;qEDVJL>W0|6F>Cju-CF9cW^-Uu)=ycb|$_$1D_xZ zgODIAgSa3ogNz_6gQ6e{gQ_44gQg%WgPtHOgRvkBgSj9JgS8+FgS{XtgNq;wgNGms zgO4B!Lx3PFL#QA#Lxdm;LyRB`LxLbHL#iMPL#7}LL#`kTL!lrmLzy5mL!}@KL#-eS zL!%%oLz^HALzf^6L!TfE!z4i#hG~M#3^N5;80HGHFf0`0U|1>0!mw75g<+#03&U1H z7KWXI%nW-3Sr`rovN9YMWMnud$jES9kdfhpAQQtWK}Lqtf{1*3R*;e5oFEg!1wlrJ zi-L>{mjoFZE+ff<()3k9NdCJ9r9ooI_&QYmO)T=a1eqD`3NkU=7i4C5B*?_@M39-` zxgZn6OQ_mcf?Nz=1i2Xg39>P;2r)9S3b8S83$ZZ>3bBE$5Eo(w)5wIB5X3zoF=-)2 z1{onn23a9S200-{26?EQ0+d!1Vq{PfVq{PjVrEbiVrI}3Vr0+~Vr0-3Vq(x0Vq(x2 zVrMWD;%0CZVrFm=VrFm`VrTFZVrK{yVqypvLWEPK5FyHL#>b$!*n4jhK)iB3>SrD8Quv=GjIw^GpGnFGPnvWFr*3#GL#7mGPDcJGAt36 zXE-b@#Bfzuis8Mm0t3H@FoTka5QB+`AcL!jAVZjlFhiz@5JRSu;&~Yv5_p*ylJK}Ig_i|nB|`=;3quZ+4H78eWnm~m;#crWFihYTXIRcF z#;})Hmf;q!IKxL?F$Q)%F$P&aSq3XU8HO-E9)=`7UWR-=A%;diX@)s`ybLS(#2EJT zi8EZ|<7arv$ItMEkDq~=pPxa9pPxaIpP#{ipP#{=pP#{xpP3<$pP3ukC;8bKF7UH6T<2$FxXaJR@R*;K;RQbn z!yA59hL8NL4Bz-!8GiG#F#P9dVPF~;VQ?2 zO^}sATacB(K#-NeRFH+iQjmqgR*;p!NsyJnU66&rTabmpUyy|%Sdf(=LXd?aMv#Re zL6C(ZMUa&tQ;?Y)|EFq{-* zVK^(u%y2=Fh2e@IE5l7eMuuC0j10F085!;fGBMl}WMsH6h{(4O1sNG02{JJ}5oBa| zD#*z2OpuY`Ig&gmO}`X`Ug3JuR1eqEB z3NkY=2r)7+3NbP;32`y-2yrop39&KA2r)9q3b8RL3$Zb13bBE$&=+C`)5wI85X3zo zF=HV{1`{Dh22&wM1~VZ>26L#K1(dcFVq~xqVq~xuVrH-tVrFm@Vq|aH3@3#Y7+wm=GO!6tGbjp6GuQ|#GQrZm diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index 0c5aa80aa..bb56137a0 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -102,7 +102,7 @@ run_smoke :: proc() { check("STRH imm", .STRH, 0, 0x014000B0, 0x0F7000F0) check("LDRSB imm", .LDRSB, 0, 0x015000D0, 0x0F7000F0) check("LDRD", .LDRD, 0, 0x014000D0, 0x0F7000F0) - check("LDM", .LDM, 0, 0x08900000, 0x0FD00000) + check("LDM", .LDM, 0, 0x08900000, 0x0FF00000) check("STM DB", .STMDB, 0, 0x09000000, 0x0FD00000) check("PUSH", .PUSH, 0, 0x092D0000, 0x0FFF0000) check("POP", .POP, 0, 0x08BD0000, 0x0FFF0000) @@ -174,18 +174,18 @@ run_smoke :: proc() { check("VABD.S8 D", .VABD, 0, 0xF2000700, 0xFFB00F10) check("VPADD.I8 D", .VPADD, 0, 0xF2000B10, 0xFFB00F10) // NEON unary + shifts - check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFB30FD0) - check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFB30FD0) + check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFBF0FD0) + check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFBF0FD0) check("VMVN", .VMVN, 0, 0xF3B00580, 0xFFB30FD0) check("VCNT", .VCNT, 0, 0xF3B00500, 0xFFB30FD0) - check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFB30FD0) + check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFBF0FD0) check("VSHR.S8 D imm", .VSHR, 0, 0xF2800010, 0xFE800F10) check("VSHL reg.S8 D", .VSHL, 0, 0xF2000400, 0xFFB00F10) check("VEXT D", .VEXT, 0, 0xF2B00000, 0xFFB00010) check("VDUP from Rt D", .VDUP, 0, 0x0EC00B10, 0x0FF00FD0) - check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFB30FD0) - check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFB30FD0) - check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB30FD0) + check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFBF0FD0) + check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFBF0FD0) + check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB70FD0) check("VTBL", .VTBL, 0, 0xF3B00800, 0xFFB00F70) check("VRECPE F32 D", .VRECPE, 2, 0xF3BB0500, 0xFFBF0FD0) check("VLD1 1-reg", .VLD1, 0, 0xF420070F, 0xFFF00F0F) @@ -289,8 +289,8 @@ run_smoke :: proc() { check("CLREX T32", .CLREX, 1, 0xF3BF8F2F, 0xFFFFFFFF) // ---- T32 32-bit Thumb-2 data-processing ---- - check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBE08000) - check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFE08000) + check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBF08000) + check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFF08000) check("EOR T32 imm", .EOR, 7, 0xF0800000, 0xFBE08000) check("ORR T32 imm", .ORR, 7, 0xF0400000, 0xFBE08000) check("BIC T32 imm", .BIC, 7, 0xF0200000, 0xFBE08000) @@ -337,12 +337,12 @@ run_smoke :: proc() { check("VQRDMULH.S16", .VQRDMULH, 0, 0xF3100B00, 0xFFB00F10) check("VQDMULL.S16", .VQDMULL, 0, 0xF2900D00, 0xFFB00F50) check("VMOVL.S8", .VMOVL, 0, 0xF2880A10, 0xFFB80FD0) - check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFB30FD0) - check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFB30FD0) - check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFB30FD0) + check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFBF0FD0) + check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFBF0FD0) + check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFBF0FD0) check("VSHRN imm", .VSHRN, 0, 0xF2800810, 0xFE800FD0) check("VQSHRN.S", .VQSHRN, 0, 0xF2800910, 0xFE800FD0) - check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFB30FD0) + check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFBF0FD0) check("VPADAL.S8", .VPADAL, 0, 0xF3B00600, 0xFFB30FD0) check("VSWP.I8", .VSWP, 0, 0xF3B20000, 0xFFB30FD0) check("VACGE.F32 D", .VACGE, 0, 0xF3000E10, 0xFFB00F10) @@ -537,12 +537,12 @@ run_smoke :: proc() { check("VCVT F16", .VCVT, 19, 0x0EBE0940, 0x0FBF0FD0) // ---- NEON compare-with-zero ---- - check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFB30FD0) - check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFB30FD0) - check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFB30FD0) - check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFB30FD0) - check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFB30FD0) - check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFB30FD0) + check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFBB0FD0) + check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFBB0FD0) + check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFBB0FD0) + check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFBB0FD0) + check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFBB0FD0) + check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFBB0FD0) // ---- NEON replicate loads ---- check("VLD2R", .VLD2R, 0, 0xF4A00D0F, 0xFFB00F0F)