diff --git a/core/rexcode/arm64/mnemonic_builders.odin b/core/rexcode/arm64/mnemonic_builders.odin index 7c511c436..40fc9a512 100644 --- a/core/rexcode/arm64/mnemonic_builders.odin +++ b/core/rexcode/arm64/mnemonic_builders.odin @@ -827,6 +827,26 @@ inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Regist emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) } inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) } +inst_not_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_not_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_r_r(dst, src)) } +inst_rbit_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_rbit_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v_r_r(dst, src)) } +inst_rev16_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_rev16_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v_r_r(dst, src)) } +inst_rev32_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_rev32_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v_r_r(dst, src)) } +inst_rev64_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_rev64_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_r_r(dst, src)) } +inst_cls_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_cls_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v_r_r(dst, src)) } +inst_clz_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_clz_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v_r_r(dst, src)) } +inst_cnt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_cnt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_r_r(dst, src)) } +inst_urecpe_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_urecpe_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v_r_r(dst, src)) } +inst_ursqrte_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_ursqrte_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v_r_r(dst, src)) } inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) } inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } @@ -2440,6 +2460,26 @@ inst_bif :: inst_bif_r_r_r emit_bif :: emit_bif_r_r_r inst_bsl :: inst_bsl_r_r_r emit_bsl :: emit_bsl_r_r_r +inst_not_v :: inst_not_v_r_r +emit_not_v :: emit_not_v_r_r +inst_rbit_v :: inst_rbit_v_r_r +emit_rbit_v :: emit_rbit_v_r_r +inst_rev16_v :: inst_rev16_v_r_r +emit_rev16_v :: emit_rev16_v_r_r +inst_rev32_v :: inst_rev32_v_r_r +emit_rev32_v :: emit_rev32_v_r_r +inst_rev64 :: inst_rev64_r_r +emit_rev64 :: emit_rev64_r_r +inst_cls_v :: inst_cls_v_r_r +emit_cls_v :: emit_cls_v_r_r +inst_clz_v :: inst_clz_v_r_r +emit_clz_v :: emit_clz_v_r_r +inst_cnt :: inst_cnt_r_r +emit_cnt :: emit_cnt_r_r +inst_urecpe_v :: inst_urecpe_v_r_r +emit_urecpe_v :: emit_urecpe_v_r_r +inst_ursqrte_v :: inst_ursqrte_v_r_r +emit_ursqrte_v :: emit_ursqrte_v_r_r inst_ld1 :: inst_ld1_r_m emit_ld1 :: emit_ld1_r_m inst_st1 :: inst_st1_r_m diff --git a/core/rexcode/arm64/tablegen/encoding_table.odin b/core/rexcode/arm64/tablegen/encoding_table.odin index ebf696317..a701fed38 100644 --- a/core/rexcode/arm64/tablegen/encoding_table.odin +++ b/core/rexcode/arm64/tablegen/encoding_table.odin @@ -3182,5 +3182,61 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, }, + + // Advanced SIMD two-register misc. + .NOT_V = { + {.NOT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, + {.NOT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, + }, + .RBIT_V = { + {.RBIT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, + {.RBIT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, + }, + .REV16_V = { + {.REV16_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, + {.REV16_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, + }, + .REV32_V = { + {.REV32_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, + {.REV32_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, + {.REV32_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, + {.REV32_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, + }, + .REV64 = { + {.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, + {.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, + {.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, + {.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, + {.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, + {.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, + }, + .CLS_V = { + {.CLS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, + {.CLS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, + {.CLS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, + {.CLS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, + {.CLS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, + {.CLS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, + }, + .CLZ_V = { + {.CLZ_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, + {.CLZ_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, + {.CLZ_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, + {.CLZ_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, + {.CLZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, + {.CLZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, + }, + .CNT = { + {.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, + {.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, + }, + .URECPE_V = { + {.URECPE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, + {.URECPE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, + }, + .URSQRTE_V = { + {.URSQRTE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, + {.URSQRTE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, + }, // SPECGEN:END } diff --git a/core/rexcode/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/arm64/tablegen/generated/decode_tables.odin index e1fbbd544..f2f6865dd 100644 --- a/core/rexcode/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1355]lib.Decode_Entry{ +DECODE_ENTRIES := [1389]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, @@ -60,8 +60,8 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SME_FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, { .SME_BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, { .SME_BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, - { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, + { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SME_SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .SME_SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, { .SME_UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, @@ -92,14 +92,14 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SVE_REV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, { .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, - { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, + { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, { .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, { .SVE_AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, { .SME_RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, @@ -116,92 +116,92 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SVE_SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, { .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, { .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, { .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .SVE_TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, { .SVE_TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, { .SVE_HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, @@ -246,164 +246,164 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SVE_BICS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_LDR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, { .SVE_STR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, + { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, + { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, - { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, + { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, + { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, + { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, { .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, + { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, { .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, + { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, { .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, { .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, { .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, { .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, { .SVE_LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, @@ -541,20 +541,20 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .STGP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MOV_REG, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, { .MOV_REG, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, - { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, { .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, @@ -591,10 +591,10 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .EON_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, { .LD1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, { .ST1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} }, - { .LD1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, { .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, - { .ST1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, + { .LD1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, { .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, + { .ST1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, { .LD1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, { .ST1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} }, { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {} }, @@ -605,6 +605,40 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, + { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, + { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, + { .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, + { .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, + { .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, + { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {} }, @@ -736,12 +770,12 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {} }, { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {} }, { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {} }, + { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {} }, @@ -825,8 +859,8 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {} }, { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} }, { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, { .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, @@ -843,8 +877,8 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {} }, { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, - { .CMP_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, { .CMP_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMP_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true} }, @@ -865,10 +899,10 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, { .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, { .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, { .TST_IMM, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, { .MOV_BITMASK, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, { .TST_IMM, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, @@ -1127,8 +1161,8 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .LDGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, { .STGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true} }, { .STZGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} }, - { .LDAPUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, { .LDAPUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, { .STLUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} }, { .STLUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} }, { .LDAPURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} }, @@ -1193,8 +1227,8 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, { .LSLV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, { .LSLV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, { .LSRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -1222,14 +1256,14 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {} }, { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {} }, { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} }, - { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, { .CCMP_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, { .CCMN_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, @@ -1259,10 +1293,10 @@ DECODE_ENTRIES := [1355]lib.Decode_Entry{ { .LDR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, { .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, { .STR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, - { .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, { .STR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, { .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, { .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, + { .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, { .FMOV_REG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, { .FMOV_REG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, { .FMOV_GEN, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} }, @@ -1373,14 +1407,14 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x04 = { 454, 76}, 0x05 = { 530, 50}, 0x06 = { 580, 8}, - 0x07 = { 588, 246}, - 0x08 = { 834, 16}, - 0x09 = { 850, 34}, - 0x0A = { 884, 98}, - 0x0B = { 982, 21}, - 0x0C = {1003, 150}, - 0x0D = {1153, 88}, - 0x0E = {1241, 13}, - 0x0F = {1254, 101}, + 0x07 = { 588, 280}, + 0x08 = { 868, 16}, + 0x09 = { 884, 34}, + 0x0A = { 918, 98}, + 0x0B = {1016, 21}, + 0x0C = {1037, 150}, + 0x0D = {1187, 88}, + 0x0E = {1275, 13}, + 0x0F = {1288, 101}, } diff --git a/core/rexcode/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/arm64/tablegen/generated/encode_tables.odin index a053a5224..7db10ca11 100644 --- a/core/rexcode/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1353]lib.Encoding{ +ENCODE_FORMS := [1387]lib.Encoding{ // .ADD_IMM { .ADD_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, @@ -1136,6 +1136,50 @@ ENCODE_FORMS := [1353]lib.Encoding{ { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} }, // .BSL { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} }, + // .NOT_V + { .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + // .RBIT_V + { .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, + { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, + // .REV16_V + { .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, + { .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, + // .REV32_V + { .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, + // .REV64 + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, + // .CLS_V + { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, + // .CLZ_V + { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, + // .CNT + { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, + // .URECPE_V + { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, + // .URSQRTE_V + { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, // .LD1 { .LD1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, { .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, @@ -2791,503 +2835,503 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .UZP2 = { 725, 0}, .TRN1 = { 725, 0}, .TRN2 = { 725, 0}, - .NOT_V = { 725, 0}, - .RBIT_V = { 725, 0}, - .REV16_V = { 725, 0}, - .REV32_V = { 725, 0}, - .REV64 = { 725, 0}, - .CLS_V = { 725, 0}, - .CLZ_V = { 725, 0}, - .CNT = { 725, 0}, - .URECPE_V = { 725, 0}, - .URSQRTE_V = { 725, 0}, - .MOVI = { 725, 0}, - .MVNI = { 725, 0}, - .FMOV_V_IMM = { 725, 0}, - .LD1 = { 725, 4}, - .LD2 = { 729, 0}, - .LD3 = { 729, 0}, - .LD4 = { 729, 0}, - .ST1 = { 729, 4}, - .ST2 = { 733, 0}, - .ST3 = { 733, 0}, - .ST4 = { 733, 0}, - .LD1R = { 733, 0}, - .LD2R = { 733, 0}, - .LD3R = { 733, 0}, - .LD4R = { 733, 0}, - .LD1_LANE = { 733, 0}, - .LD2_LANE = { 733, 0}, - .LD3_LANE = { 733, 0}, - .LD4_LANE = { 733, 0}, - .ST1_LANE = { 733, 0}, - .ST2_LANE = { 733, 0}, - .ST3_LANE = { 733, 0}, - .ST4_LANE = { 733, 0}, - .LDR_V = { 733, 5}, - .STR_V = { 738, 5}, - .LDP_V = { 743, 0}, - .STP_V = { 743, 0}, - .LDUR_V = { 743, 0}, - .STUR_V = { 743, 0}, - .SVE_ADD_Z = { 743, 4}, - .SVE_SUB_Z = { 747, 4}, - .SVE_SQADD_Z = { 751, 4}, - .SVE_UQADD_Z = { 755, 4}, - .SVE_SQSUB_Z = { 759, 4}, - .SVE_UQSUB_Z = { 763, 4}, - .SVE_ADD_PRED = { 767, 4}, - .SVE_SUB_PRED = { 771, 4}, - .SVE_SUBR_PRED = { 775, 4}, - .SVE_MUL_PRED = { 779, 4}, - .SVE_SMULH_PRED = { 783, 4}, - .SVE_UMULH_PRED = { 787, 4}, - .SVE_SDIV_PRED = { 791, 2}, - .SVE_UDIV_PRED = { 793, 2}, - .SVE_SMAX_PRED = { 795, 4}, - .SVE_UMAX_PRED = { 799, 4}, - .SVE_SMIN_PRED = { 803, 4}, - .SVE_UMIN_PRED = { 807, 4}, - .SVE_SABD_PRED = { 811, 4}, - .SVE_UABD_PRED = { 815, 4}, - .SVE_AND_PRED = { 819, 1}, - .SVE_ORR_PRED = { 820, 1}, - .SVE_EOR_PRED = { 821, 1}, - .SVE_BIC_PRED = { 822, 1}, - .SVE_ASR_PRED = { 823, 4}, - .SVE_LSL_PRED = { 827, 4}, - .SVE_LSR_PRED = { 831, 4}, - .SVE_ASRR_PRED = { 835, 0}, - .SVE_LSLR_PRED = { 835, 0}, - .SVE_LSRR_PRED = { 835, 0}, - .SVE_ABS_PRED = { 835, 4}, - .SVE_NEG_PRED = { 839, 4}, - .SVE_CLS_PRED = { 843, 4}, - .SVE_CLZ_PRED = { 847, 4}, - .SVE_CNT_PRED = { 851, 4}, - .SVE_MOV_PRED = { 855, 0}, - .SVE_FADD_Z = { 855, 3}, - .SVE_FSUB_Z = { 858, 3}, - .SVE_FMUL_Z = { 861, 3}, - .SVE_FRECPS = { 864, 3}, - .SVE_FRSQRTS = { 867, 3}, - .SVE_FTSMUL = { 870, 3}, - .SVE_FADD_PRED = { 873, 3}, - .SVE_FSUB_PRED = { 876, 3}, - .SVE_FSUBR_PRED = { 879, 0}, - .SVE_FMUL_PRED = { 879, 3}, - .SVE_FDIV_PRED = { 882, 3}, - .SVE_FDIVR_PRED = { 885, 0}, - .SVE_FMAX_PRED = { 885, 3}, - .SVE_FMIN_PRED = { 888, 3}, - .SVE_FMAXNM_PRED = { 891, 3}, - .SVE_FMINNM_PRED = { 894, 3}, - .SVE_FABS_Z = { 897, 3}, - .SVE_FNEG_Z = { 900, 3}, - .SVE_FSQRT_Z = { 903, 3}, - .SVE_FRECPX_Z = { 906, 0}, - .SVE_FRINTN = { 906, 0}, - .SVE_FRINTP = { 906, 0}, - .SVE_FRINTM = { 906, 0}, - .SVE_FRINTZ = { 906, 0}, - .SVE_FRINTA = { 906, 0}, - .SVE_FRINTX = { 906, 0}, - .SVE_FRINTI = { 906, 0}, - .SVE_FMLA = { 906, 3}, - .SVE_FMLS = { 909, 3}, - .SVE_FNMLA = { 912, 3}, - .SVE_FNMLS = { 915, 3}, - .SVE_AND_P = { 918, 1}, - .SVE_BIC_P = { 919, 1}, - .SVE_ORR_P = { 920, 1}, - .SVE_EOR_P = { 921, 1}, - .SVE_NAND_P = { 922, 1}, - .SVE_NOR_P = { 923, 1}, - .SVE_ORN_P = { 924, 1}, - .SVE_SEL_P = { 925, 1}, - .SVE_ANDS_P = { 926, 1}, - .SVE_BICS_P = { 927, 1}, - .SVE_ORRS_P = { 928, 1}, - .SVE_EORS_P = { 929, 1}, - .SVE_NANDS_P = { 930, 0}, - .SVE_NORS_P = { 930, 0}, - .SVE_ORNS_P = { 930, 0}, - .SVE_NOT_P = { 930, 0}, - .SVE_MOV_P = { 930, 0}, - .SVE_MOVS_P = { 930, 0}, - .SVE_PTRUE = { 930, 1}, - .SVE_PTRUES = { 931, 1}, - .SVE_PFALSE = { 932, 1}, - .SVE_PFIRST = { 933, 1}, - .SVE_PNEXT = { 934, 1}, - .SVE_BRKA = { 935, 0}, - .SVE_BRKB = { 935, 0}, - .SVE_BRKAS = { 935, 0}, - .SVE_BRKBS = { 935, 0}, - .SVE_BRKPA = { 935, 0}, - .SVE_BRKPB = { 935, 0}, - .SVE_BRKN = { 935, 0}, - .SVE_RDFFR = { 935, 0}, - .SVE_WRFFR = { 935, 0}, - .SVE_SETFFR = { 935, 0}, - .SVE_CMPEQ = { 935, 4}, - .SVE_CMPNE = { 939, 4}, - .SVE_CMPGE = { 943, 4}, - .SVE_CMPGT = { 947, 4}, - .SVE_CMPLE = { 951, 0}, - .SVE_CMPLT = { 951, 0}, - .SVE_CMPHI = { 951, 4}, - .SVE_CMPHS = { 955, 4}, - .SVE_CMPLO = { 959, 0}, - .SVE_CMPLS = { 959, 0}, - .SVE_FCMEQ = { 959, 0}, - .SVE_FCMNE = { 959, 0}, - .SVE_FCMGE = { 959, 0}, - .SVE_FCMGT = { 959, 0}, - .SVE_FCMLE = { 959, 0}, - .SVE_FCMLT = { 959, 0}, - .SVE_FCMUO = { 959, 0}, - .SVE_DUP_Z = { 959, 4}, - .SVE_INSR = { 963, 0}, - .SVE_REV_Z = { 963, 4}, - .SVE_REV_P = { 967, 1}, - .SVE_TBL = { 968, 4}, - .SVE_ZIP1_Z = { 972, 4}, - .SVE_ZIP2_Z = { 976, 4}, - .SVE_UZP1_Z = { 980, 4}, - .SVE_UZP2_Z = { 984, 4}, - .SVE_TRN1_Z = { 988, 4}, - .SVE_TRN2_Z = { 992, 4}, - .SVE_ZIP1_P = { 996, 1}, - .SVE_ZIP2_P = { 997, 1}, - .SVE_UZP1_P = { 998, 1}, - .SVE_UZP2_P = { 999, 1}, - .SVE_TRN1_P = { 1000, 1}, - .SVE_TRN2_P = { 1001, 1}, - .SVE_CPY_Z = { 1002, 0}, - .SVE_COMPACT = { 1002, 0}, - .SVE_EXT_Z = { 1002, 0}, - .SVE_LD1B = { 1002, 1}, - .SVE_LD1H = { 1003, 1}, - .SVE_LD1W = { 1004, 1}, - .SVE_LD1D = { 1005, 1}, - .SVE_LD1SB = { 1006, 1}, - .SVE_LD1SH = { 1007, 1}, - .SVE_LD1SW = { 1008, 1}, - .SVE_ST1B = { 1009, 1}, - .SVE_ST1H = { 1010, 1}, - .SVE_ST1W = { 1011, 1}, - .SVE_ST1D = { 1012, 1}, - .SVE_LDR_Z = { 1013, 1}, - .SVE_STR_Z = { 1014, 1}, - .SVE_LDR_P = { 1015, 1}, - .SVE_STR_P = { 1016, 1}, - .SVE_LDFF1B = { 1017, 1}, - .SVE_LDFF1H = { 1018, 1}, - .SVE_LDFF1W = { 1019, 1}, - .SVE_LDFF1D = { 1020, 1}, - .SVE_WHILEGE = { 1021, 1}, - .SVE_WHILEGT = { 1022, 1}, - .SVE_WHILELE = { 1023, 1}, - .SVE_WHILELT = { 1024, 1}, - .SVE_WHILEHI = { 1025, 1}, - .SVE_WHILEHS = { 1026, 1}, - .SVE_WHILELO = { 1027, 1}, - .SVE_WHILELS = { 1028, 1}, - .SVE_SQRDMLAH = { 1029, 4}, - .SVE_SQRDMLSH = { 1033, 4}, - .SVE_ADCLB = { 1037, 2}, - .SVE_ADCLT = { 1039, 2}, - .SVE_SBCLB = { 1041, 2}, - .SVE_SBCLT = { 1043, 2}, - .SVE_TBL2 = { 1045, 1}, - .SVE_TBX = { 1046, 1}, - .SVE_AESE = { 1047, 1}, - .SVE_AESD = { 1048, 1}, - .SVE_AESMC = { 1049, 1}, - .SVE_AESIMC = { 1050, 1}, - .SVE_BCAX_Z = { 1051, 0}, - .SVE_XAR_Z = { 1051, 0}, - .SVE_EOR3_Z = { 1051, 0}, - .SVE_MATCH = { 1051, 2}, - .SVE_NMATCH = { 1053, 2}, - .SVE_HISTCNT = { 1055, 2}, - .SVE_HISTSEG = { 1057, 1}, - .SME_SMSTART = { 1058, 1}, - .SME_SMSTOP = { 1059, 1}, - .SME_RDSVL = { 1060, 1}, - .SME_ADDHA = { 1061, 0}, - .SME_ADDVA = { 1061, 0}, - .SME_ZERO = { 1061, 1}, - .SME_FMOPA = { 1062, 1}, - .SME_FMOPS = { 1063, 1}, - .SME_BFMOPA = { 1064, 1}, - .SME_BFMOPS = { 1065, 1}, - .SME_SMOPA = { 1066, 2}, - .SME_SMOPS = { 1068, 2}, - .SME_UMOPA = { 1070, 2}, - .SME_UMOPS = { 1072, 2}, - .SME_USMOPA = { 1074, 1}, - .SME_SUMOPA = { 1075, 1}, - .SME_MOVA_TO_Z = { 1076, 0}, - .SME_MOVA_TO_ZA = { 1076, 0}, - .SME_LD1B_ZA = { 1076, 0}, - .SME_LD1H_ZA = { 1076, 0}, - .SME_LD1W_ZA = { 1076, 0}, - .SME_LD1D_ZA = { 1076, 0}, - .SME_LD1Q_ZA = { 1076, 0}, - .SME_ST1B_ZA = { 1076, 0}, - .SME_ST1H_ZA = { 1076, 0}, - .SME_ST1W_ZA = { 1076, 0}, - .SME_ST1D_ZA = { 1076, 0}, - .SME_ST1Q_ZA = { 1076, 0}, - .SME_LDR_ZA = { 1076, 1}, - .SME_STR_ZA = { 1077, 1}, - .SVE_FMLA_IDX_H = { 1078, 1}, - .SVE_FMLA_IDX_S = { 1079, 1}, - .SVE_FMLA_IDX_D = { 1080, 1}, - .SVE_FMLS_IDX_H = { 1081, 1}, - .SVE_FMLS_IDX_S = { 1082, 1}, - .SVE_FMLS_IDX_D = { 1083, 1}, - .SVE_LD1B_GATHER_S = { 1084, 1}, - .SVE_LD1B_GATHER_D = { 1085, 1}, - .SVE_LD1H_GATHER_S = { 1086, 1}, - .SVE_LD1H_GATHER_D = { 1087, 1}, - .SVE_LD1W_GATHER_S = { 1088, 1}, - .SVE_LD1W_GATHER_D = { 1089, 1}, - .SVE_LD1D_GATHER_D = { 1090, 1}, - .SVE_LD1SB_GATHER_S = { 1091, 1}, - .SVE_LD1SB_GATHER_D = { 1092, 1}, - .SVE_LD1SH_GATHER_S = { 1093, 1}, - .SVE_LD1SH_GATHER_D = { 1094, 1}, - .SVE_LD1SW_GATHER_D = { 1095, 1}, - .SVE_ST1B_SCATTER_S = { 1096, 1}, - .SVE_ST1B_SCATTER_D = { 1097, 1}, - .SVE_ST1H_SCATTER_S = { 1098, 1}, - .SVE_ST1H_SCATTER_D = { 1099, 1}, - .SVE_ST1W_SCATTER_S = { 1100, 1}, - .SVE_ST1W_SCATTER_D = { 1101, 1}, - .SVE_ST1D_SCATTER_D = { 1102, 1}, - .SME_LD1B_TILE = { 1103, 1}, - .SME_LD1H_TILE = { 1104, 1}, - .SME_LD1W_TILE = { 1105, 1}, - .SME_LD1D_TILE = { 1106, 1}, - .SME_LD1Q_TILE = { 1107, 1}, - .SME_ST1B_TILE = { 1108, 1}, - .SME_ST1H_TILE = { 1109, 1}, - .SME_ST1W_TILE = { 1110, 1}, - .SME_ST1D_TILE = { 1111, 1}, - .SME_ST1Q_TILE = { 1112, 1}, - .SME_MOVA_Z_FROM_TILE = { 1113, 1}, - .SME_MOVA_TILE_FROM_Z = { 1114, 1}, - .FCMLA_4H = { 1115, 1}, - .FCMLA_8H = { 1116, 1}, - .FCMLA_4S = { 1117, 1}, - .FCMLA_2D = { 1118, 1}, - .FCADD_4H = { 1119, 1}, - .FCADD_8H = { 1120, 1}, - .FCADD_4S = { 1121, 1}, - .FCADD_2D = { 1122, 1}, - .SVE_PRFB = { 1123, 1}, - .SVE_PRFH = { 1124, 1}, - .SVE_PRFW = { 1125, 1}, - .SVE_PRFD = { 1126, 1}, - .SVE_LDNT1B = { 1127, 1}, - .SVE_LDNT1H = { 1128, 1}, - .SVE_LDNT1W = { 1129, 1}, - .SVE_LDNT1D = { 1130, 1}, - .SVE_STNT1B = { 1131, 1}, - .SVE_STNT1H = { 1132, 1}, - .SVE_STNT1W = { 1133, 1}, - .SVE_STNT1D = { 1134, 1}, - .SVE_EXT = { 1135, 1}, - .SVE_SPLICE = { 1136, 1}, - .SVE_INDEX_II = { 1137, 1}, - .SVE_INDEX_IR = { 1138, 1}, - .SVE_INDEX_RI = { 1139, 1}, - .SVE_INDEX_RR = { 1140, 1}, - .SVE_BSL = { 1141, 1}, - .SVE_BSL1N = { 1142, 1}, - .SVE_BSL2N = { 1143, 1}, - .SVE_NBSL = { 1144, 1}, - .SVE_PMUL_VEC = { 1145, 1}, - .SVE_PMULLB = { 1146, 1}, - .SVE_PMULLT = { 1147, 1}, - .SVE_BFCVT = { 1148, 1}, - .SVE_BFCVTNT = { 1149, 1}, - .LDRAA = { 1150, 1}, - .LDRAB = { 1151, 1}, - .LDRAA_PRE = { 1152, 1}, - .LDRAB_PRE = { 1153, 1}, - .TSTART = { 1154, 1}, - .TCOMMIT = { 1155, 1}, - .TCANCEL = { 1156, 1}, - .TTEST = { 1157, 1}, - .WFET = { 1158, 1}, - .WFIT = { 1159, 1}, - .BC_COND = { 1160, 1}, - .UXTB = { 1161, 1}, - .UXTH = { 1162, 1}, - .UXTW = { 1163, 1}, - .SXTB = { 1164, 1}, - .SXTH = { 1165, 1}, - .SXTW = { 1166, 1}, - .ADC = { 1167, 2}, - .ADCS = { 1169, 2}, - .SBC = { 1171, 2}, - .SBCS = { 1173, 2}, - .NGC = { 1175, 2}, - .NGCS = { 1177, 2}, - .LDAPUR = { 1179, 2}, - .STLUR = { 1181, 2}, - .LDAPURB = { 1183, 1}, - .STLURB = { 1184, 1}, - .LDAPURH = { 1185, 1}, - .STLURH = { 1186, 1}, - .LDAPURSB = { 1187, 2}, - .LDAPURSH = { 1189, 2}, - .LDAPURSW = { 1191, 1}, - .SVE_BFADD = { 1192, 1}, - .SVE_BFSUB = { 1193, 1}, - .SVE_BFMUL = { 1194, 1}, - .SVE_BFMLA = { 1195, 1}, - .SVE_BFMLS = { 1196, 1}, - .SB = { 1197, 1}, - .CSDB = { 1198, 1}, - .DGH = { 1199, 1}, - .PSB_CSYNC = { 1200, 1}, - .TSB_CSYNC = { 1201, 1}, - .BTI_J = { 1202, 1}, - .BTI_C = { 1203, 1}, - .BTI_JC = { 1204, 1}, - .MOV_V_ALIAS = { 1205, 2}, - .NOT_V_ALIAS = { 1207, 2}, - .LSL_IMM = { 1209, 2}, - .LSR_IMM = { 1211, 2}, - .ASR_IMM = { 1213, 2}, - .ROR_IMM = { 1215, 2}, - .SVE_BFADD_UNPRED = { 1217, 1}, - .SVE_BFSUB_UNPRED = { 1218, 1}, - .SVE_BFMUL_UNPRED = { 1219, 1}, - .SVE_BFCLAMP = { 1220, 1}, - .SVE_BFMAXNM = { 1221, 1}, - .SVE_BFMINNM = { 1222, 1}, - .SME2_LUTI2_B = { 1223, 1}, - .SME2_LUTI4_B = { 1224, 1}, - .SME2_LD1B_X2 = { 1225, 1}, - .SME2_LD1H_X2 = { 1226, 1}, - .SME2_LD1W_X2 = { 1227, 1}, - .SME2_LD1D_X2 = { 1228, 1}, - .SME2_LD1B_X4 = { 1229, 1}, - .SME2_LD1H_X4 = { 1230, 1}, - .SME2_LD1W_X4 = { 1231, 1}, - .SME2_LD1D_X4 = { 1232, 1}, - .SME2_ST1B_X2 = { 1233, 1}, - .SME2_ST1H_X2 = { 1234, 1}, - .SME2_ST1W_X2 = { 1235, 1}, - .SME2_ST1D_X2 = { 1236, 1}, - .SME2_ST1B_X4 = { 1237, 1}, - .SME2_ST1H_X4 = { 1238, 1}, - .SME2_ST1W_X4 = { 1239, 1}, - .SME2_ST1D_X4 = { 1240, 1}, - .SME2_ZIP_3 = { 1241, 1}, - .SME2_ZIP_4 = { 1242, 1}, - .SME2_UZP_3 = { 1243, 1}, - .SME2_UZP_4 = { 1244, 1}, - .TLBI_RPALOS = { 1245, 1}, - .TLBI_RPAOS = { 1246, 1}, - .AT_S1E1A = { 1247, 1}, - .DC_CIPAPA = { 1248, 1}, - .DC_CIGDPAPA = { 1249, 1}, - .TLBI_PAALL = { 1250, 1}, - .TLBI_PAALLOS = { 1251, 1}, - .AMX_LDX = { 1252, 1}, - .AMX_LDY = { 1253, 1}, - .AMX_STX = { 1254, 1}, - .AMX_STY = { 1255, 1}, - .AMX_LDZ = { 1256, 1}, - .AMX_STZ = { 1257, 1}, - .AMX_LDZI = { 1258, 1}, - .AMX_STZI = { 1259, 1}, - .AMX_EXTRX = { 1260, 1}, - .AMX_EXTRY = { 1261, 1}, - .AMX_FMA64 = { 1262, 1}, - .AMX_FMS64 = { 1263, 1}, - .AMX_FMA32 = { 1264, 1}, - .AMX_FMS32 = { 1265, 1}, - .AMX_MAC16 = { 1266, 1}, - .AMX_FMA16 = { 1267, 1}, - .AMX_FMS16 = { 1268, 1}, - .AMX_SET = { 1269, 1}, - .AMX_CLR = { 1270, 1}, - .AMX_VECINT = { 1271, 1}, - .AMX_VECFP = { 1272, 1}, - .AMX_MATINT = { 1273, 1}, - .AMX_MATFP = { 1274, 1}, - .AMX_GENLUT = { 1275, 1}, - .CPYP = { 1276, 1}, - .CPYM = { 1277, 1}, - .CPYE = { 1278, 1}, - .CPYFP = { 1279, 1}, - .CPYFM = { 1280, 1}, - .CPYFE = { 1281, 1}, - .SETP = { 1282, 1}, - .SETM = { 1283, 1}, - .SETE = { 1284, 1}, - .DC_IVAC = { 1285, 1}, - .DC_ISW = { 1286, 1}, - .DC_CSW = { 1287, 1}, - .DC_CISW = { 1288, 1}, - .DC_ZVA = { 1289, 1}, - .DC_CVAC = { 1290, 1}, - .DC_CVAU = { 1291, 1}, - .DC_CIVAC = { 1292, 1}, - .IC_IALLUIS = { 1293, 1}, - .IC_IALLU = { 1294, 1}, - .IC_IVAU = { 1295, 1}, - .AT_S1E1R = { 1296, 1}, - .AT_S1E1W = { 1297, 1}, - .AT_S1E0R = { 1298, 1}, - .AT_S1E0W = { 1299, 1}, - .AT_S1E2R = { 1300, 1}, - .AT_S1E2W = { 1301, 1}, - .AT_S1E3R = { 1302, 1}, - .AT_S1E3W = { 1303, 1}, - .AT_S12E1R = { 1304, 1}, - .AT_S12E1W = { 1305, 1}, - .AT_S12E0R = { 1306, 1}, - .AT_S12E0W = { 1307, 1}, - .TLBI_VMALLE1 = { 1308, 1}, - .TLBI_VMALLE1IS = { 1309, 1}, - .TLBI_VAE1 = { 1310, 1}, - .TLBI_VAE1IS = { 1311, 1}, - .TLBI_ASIDE1 = { 1312, 1}, - .TLBI_ASIDE1IS = { 1313, 1}, - .TLBI_VAAE1 = { 1314, 1}, - .TLBI_VAAE1IS = { 1315, 1}, - .TLBI_VALE1 = { 1316, 1}, - .TLBI_VALE1IS = { 1317, 1}, - .TLBI_VAALE1 = { 1318, 1}, - .TLBI_VAALE1IS = { 1319, 1}, - .TLBI_ALLE1 = { 1320, 1}, - .TLBI_ALLE1IS = { 1321, 1}, - .TLBI_ALLE2 = { 1322, 1}, - .TLBI_ALLE2IS = { 1323, 1}, - .TLBI_ALLE3 = { 1324, 1}, - .TLBI_ALLE3IS = { 1325, 1}, - .PRFM = { 1326, 1}, - .PRFUM = { 1327, 1}, - .PRFM_LIT = { 1328, 1}, - .MOV_REG = { 1329, 2}, - .MOV_BITMASK = { 1331, 2}, - .MVN = { 1333, 2}, - .NEG_SR = { 1335, 2}, - .NEGS = { 1337, 2}, - .CMP_SR = { 1339, 2}, - .CMP_ER = { 1341, 2}, - .CMP_IMM = { 1343, 2}, - .CMN_SR = { 1345, 2}, - .CMN_ER = { 1347, 2}, - .CMN_IMM = { 1349, 2}, - .TST_SR = { 1351, 2}, + .NOT_V = { 725, 2}, + .RBIT_V = { 727, 2}, + .REV16_V = { 729, 2}, + .REV32_V = { 731, 4}, + .REV64 = { 735, 6}, + .CLS_V = { 741, 6}, + .CLZ_V = { 747, 6}, + .CNT = { 753, 2}, + .URECPE_V = { 755, 2}, + .URSQRTE_V = { 757, 2}, + .MOVI = { 759, 0}, + .MVNI = { 759, 0}, + .FMOV_V_IMM = { 759, 0}, + .LD1 = { 759, 4}, + .LD2 = { 763, 0}, + .LD3 = { 763, 0}, + .LD4 = { 763, 0}, + .ST1 = { 763, 4}, + .ST2 = { 767, 0}, + .ST3 = { 767, 0}, + .ST4 = { 767, 0}, + .LD1R = { 767, 0}, + .LD2R = { 767, 0}, + .LD3R = { 767, 0}, + .LD4R = { 767, 0}, + .LD1_LANE = { 767, 0}, + .LD2_LANE = { 767, 0}, + .LD3_LANE = { 767, 0}, + .LD4_LANE = { 767, 0}, + .ST1_LANE = { 767, 0}, + .ST2_LANE = { 767, 0}, + .ST3_LANE = { 767, 0}, + .ST4_LANE = { 767, 0}, + .LDR_V = { 767, 5}, + .STR_V = { 772, 5}, + .LDP_V = { 777, 0}, + .STP_V = { 777, 0}, + .LDUR_V = { 777, 0}, + .STUR_V = { 777, 0}, + .SVE_ADD_Z = { 777, 4}, + .SVE_SUB_Z = { 781, 4}, + .SVE_SQADD_Z = { 785, 4}, + .SVE_UQADD_Z = { 789, 4}, + .SVE_SQSUB_Z = { 793, 4}, + .SVE_UQSUB_Z = { 797, 4}, + .SVE_ADD_PRED = { 801, 4}, + .SVE_SUB_PRED = { 805, 4}, + .SVE_SUBR_PRED = { 809, 4}, + .SVE_MUL_PRED = { 813, 4}, + .SVE_SMULH_PRED = { 817, 4}, + .SVE_UMULH_PRED = { 821, 4}, + .SVE_SDIV_PRED = { 825, 2}, + .SVE_UDIV_PRED = { 827, 2}, + .SVE_SMAX_PRED = { 829, 4}, + .SVE_UMAX_PRED = { 833, 4}, + .SVE_SMIN_PRED = { 837, 4}, + .SVE_UMIN_PRED = { 841, 4}, + .SVE_SABD_PRED = { 845, 4}, + .SVE_UABD_PRED = { 849, 4}, + .SVE_AND_PRED = { 853, 1}, + .SVE_ORR_PRED = { 854, 1}, + .SVE_EOR_PRED = { 855, 1}, + .SVE_BIC_PRED = { 856, 1}, + .SVE_ASR_PRED = { 857, 4}, + .SVE_LSL_PRED = { 861, 4}, + .SVE_LSR_PRED = { 865, 4}, + .SVE_ASRR_PRED = { 869, 0}, + .SVE_LSLR_PRED = { 869, 0}, + .SVE_LSRR_PRED = { 869, 0}, + .SVE_ABS_PRED = { 869, 4}, + .SVE_NEG_PRED = { 873, 4}, + .SVE_CLS_PRED = { 877, 4}, + .SVE_CLZ_PRED = { 881, 4}, + .SVE_CNT_PRED = { 885, 4}, + .SVE_MOV_PRED = { 889, 0}, + .SVE_FADD_Z = { 889, 3}, + .SVE_FSUB_Z = { 892, 3}, + .SVE_FMUL_Z = { 895, 3}, + .SVE_FRECPS = { 898, 3}, + .SVE_FRSQRTS = { 901, 3}, + .SVE_FTSMUL = { 904, 3}, + .SVE_FADD_PRED = { 907, 3}, + .SVE_FSUB_PRED = { 910, 3}, + .SVE_FSUBR_PRED = { 913, 0}, + .SVE_FMUL_PRED = { 913, 3}, + .SVE_FDIV_PRED = { 916, 3}, + .SVE_FDIVR_PRED = { 919, 0}, + .SVE_FMAX_PRED = { 919, 3}, + .SVE_FMIN_PRED = { 922, 3}, + .SVE_FMAXNM_PRED = { 925, 3}, + .SVE_FMINNM_PRED = { 928, 3}, + .SVE_FABS_Z = { 931, 3}, + .SVE_FNEG_Z = { 934, 3}, + .SVE_FSQRT_Z = { 937, 3}, + .SVE_FRECPX_Z = { 940, 0}, + .SVE_FRINTN = { 940, 0}, + .SVE_FRINTP = { 940, 0}, + .SVE_FRINTM = { 940, 0}, + .SVE_FRINTZ = { 940, 0}, + .SVE_FRINTA = { 940, 0}, + .SVE_FRINTX = { 940, 0}, + .SVE_FRINTI = { 940, 0}, + .SVE_FMLA = { 940, 3}, + .SVE_FMLS = { 943, 3}, + .SVE_FNMLA = { 946, 3}, + .SVE_FNMLS = { 949, 3}, + .SVE_AND_P = { 952, 1}, + .SVE_BIC_P = { 953, 1}, + .SVE_ORR_P = { 954, 1}, + .SVE_EOR_P = { 955, 1}, + .SVE_NAND_P = { 956, 1}, + .SVE_NOR_P = { 957, 1}, + .SVE_ORN_P = { 958, 1}, + .SVE_SEL_P = { 959, 1}, + .SVE_ANDS_P = { 960, 1}, + .SVE_BICS_P = { 961, 1}, + .SVE_ORRS_P = { 962, 1}, + .SVE_EORS_P = { 963, 1}, + .SVE_NANDS_P = { 964, 0}, + .SVE_NORS_P = { 964, 0}, + .SVE_ORNS_P = { 964, 0}, + .SVE_NOT_P = { 964, 0}, + .SVE_MOV_P = { 964, 0}, + .SVE_MOVS_P = { 964, 0}, + .SVE_PTRUE = { 964, 1}, + .SVE_PTRUES = { 965, 1}, + .SVE_PFALSE = { 966, 1}, + .SVE_PFIRST = { 967, 1}, + .SVE_PNEXT = { 968, 1}, + .SVE_BRKA = { 969, 0}, + .SVE_BRKB = { 969, 0}, + .SVE_BRKAS = { 969, 0}, + .SVE_BRKBS = { 969, 0}, + .SVE_BRKPA = { 969, 0}, + .SVE_BRKPB = { 969, 0}, + .SVE_BRKN = { 969, 0}, + .SVE_RDFFR = { 969, 0}, + .SVE_WRFFR = { 969, 0}, + .SVE_SETFFR = { 969, 0}, + .SVE_CMPEQ = { 969, 4}, + .SVE_CMPNE = { 973, 4}, + .SVE_CMPGE = { 977, 4}, + .SVE_CMPGT = { 981, 4}, + .SVE_CMPLE = { 985, 0}, + .SVE_CMPLT = { 985, 0}, + .SVE_CMPHI = { 985, 4}, + .SVE_CMPHS = { 989, 4}, + .SVE_CMPLO = { 993, 0}, + .SVE_CMPLS = { 993, 0}, + .SVE_FCMEQ = { 993, 0}, + .SVE_FCMNE = { 993, 0}, + .SVE_FCMGE = { 993, 0}, + .SVE_FCMGT = { 993, 0}, + .SVE_FCMLE = { 993, 0}, + .SVE_FCMLT = { 993, 0}, + .SVE_FCMUO = { 993, 0}, + .SVE_DUP_Z = { 993, 4}, + .SVE_INSR = { 997, 0}, + .SVE_REV_Z = { 997, 4}, + .SVE_REV_P = { 1001, 1}, + .SVE_TBL = { 1002, 4}, + .SVE_ZIP1_Z = { 1006, 4}, + .SVE_ZIP2_Z = { 1010, 4}, + .SVE_UZP1_Z = { 1014, 4}, + .SVE_UZP2_Z = { 1018, 4}, + .SVE_TRN1_Z = { 1022, 4}, + .SVE_TRN2_Z = { 1026, 4}, + .SVE_ZIP1_P = { 1030, 1}, + .SVE_ZIP2_P = { 1031, 1}, + .SVE_UZP1_P = { 1032, 1}, + .SVE_UZP2_P = { 1033, 1}, + .SVE_TRN1_P = { 1034, 1}, + .SVE_TRN2_P = { 1035, 1}, + .SVE_CPY_Z = { 1036, 0}, + .SVE_COMPACT = { 1036, 0}, + .SVE_EXT_Z = { 1036, 0}, + .SVE_LD1B = { 1036, 1}, + .SVE_LD1H = { 1037, 1}, + .SVE_LD1W = { 1038, 1}, + .SVE_LD1D = { 1039, 1}, + .SVE_LD1SB = { 1040, 1}, + .SVE_LD1SH = { 1041, 1}, + .SVE_LD1SW = { 1042, 1}, + .SVE_ST1B = { 1043, 1}, + .SVE_ST1H = { 1044, 1}, + .SVE_ST1W = { 1045, 1}, + .SVE_ST1D = { 1046, 1}, + .SVE_LDR_Z = { 1047, 1}, + .SVE_STR_Z = { 1048, 1}, + .SVE_LDR_P = { 1049, 1}, + .SVE_STR_P = { 1050, 1}, + .SVE_LDFF1B = { 1051, 1}, + .SVE_LDFF1H = { 1052, 1}, + .SVE_LDFF1W = { 1053, 1}, + .SVE_LDFF1D = { 1054, 1}, + .SVE_WHILEGE = { 1055, 1}, + .SVE_WHILEGT = { 1056, 1}, + .SVE_WHILELE = { 1057, 1}, + .SVE_WHILELT = { 1058, 1}, + .SVE_WHILEHI = { 1059, 1}, + .SVE_WHILEHS = { 1060, 1}, + .SVE_WHILELO = { 1061, 1}, + .SVE_WHILELS = { 1062, 1}, + .SVE_SQRDMLAH = { 1063, 4}, + .SVE_SQRDMLSH = { 1067, 4}, + .SVE_ADCLB = { 1071, 2}, + .SVE_ADCLT = { 1073, 2}, + .SVE_SBCLB = { 1075, 2}, + .SVE_SBCLT = { 1077, 2}, + .SVE_TBL2 = { 1079, 1}, + .SVE_TBX = { 1080, 1}, + .SVE_AESE = { 1081, 1}, + .SVE_AESD = { 1082, 1}, + .SVE_AESMC = { 1083, 1}, + .SVE_AESIMC = { 1084, 1}, + .SVE_BCAX_Z = { 1085, 0}, + .SVE_XAR_Z = { 1085, 0}, + .SVE_EOR3_Z = { 1085, 0}, + .SVE_MATCH = { 1085, 2}, + .SVE_NMATCH = { 1087, 2}, + .SVE_HISTCNT = { 1089, 2}, + .SVE_HISTSEG = { 1091, 1}, + .SME_SMSTART = { 1092, 1}, + .SME_SMSTOP = { 1093, 1}, + .SME_RDSVL = { 1094, 1}, + .SME_ADDHA = { 1095, 0}, + .SME_ADDVA = { 1095, 0}, + .SME_ZERO = { 1095, 1}, + .SME_FMOPA = { 1096, 1}, + .SME_FMOPS = { 1097, 1}, + .SME_BFMOPA = { 1098, 1}, + .SME_BFMOPS = { 1099, 1}, + .SME_SMOPA = { 1100, 2}, + .SME_SMOPS = { 1102, 2}, + .SME_UMOPA = { 1104, 2}, + .SME_UMOPS = { 1106, 2}, + .SME_USMOPA = { 1108, 1}, + .SME_SUMOPA = { 1109, 1}, + .SME_MOVA_TO_Z = { 1110, 0}, + .SME_MOVA_TO_ZA = { 1110, 0}, + .SME_LD1B_ZA = { 1110, 0}, + .SME_LD1H_ZA = { 1110, 0}, + .SME_LD1W_ZA = { 1110, 0}, + .SME_LD1D_ZA = { 1110, 0}, + .SME_LD1Q_ZA = { 1110, 0}, + .SME_ST1B_ZA = { 1110, 0}, + .SME_ST1H_ZA = { 1110, 0}, + .SME_ST1W_ZA = { 1110, 0}, + .SME_ST1D_ZA = { 1110, 0}, + .SME_ST1Q_ZA = { 1110, 0}, + .SME_LDR_ZA = { 1110, 1}, + .SME_STR_ZA = { 1111, 1}, + .SVE_FMLA_IDX_H = { 1112, 1}, + .SVE_FMLA_IDX_S = { 1113, 1}, + .SVE_FMLA_IDX_D = { 1114, 1}, + .SVE_FMLS_IDX_H = { 1115, 1}, + .SVE_FMLS_IDX_S = { 1116, 1}, + .SVE_FMLS_IDX_D = { 1117, 1}, + .SVE_LD1B_GATHER_S = { 1118, 1}, + .SVE_LD1B_GATHER_D = { 1119, 1}, + .SVE_LD1H_GATHER_S = { 1120, 1}, + .SVE_LD1H_GATHER_D = { 1121, 1}, + .SVE_LD1W_GATHER_S = { 1122, 1}, + .SVE_LD1W_GATHER_D = { 1123, 1}, + .SVE_LD1D_GATHER_D = { 1124, 1}, + .SVE_LD1SB_GATHER_S = { 1125, 1}, + .SVE_LD1SB_GATHER_D = { 1126, 1}, + .SVE_LD1SH_GATHER_S = { 1127, 1}, + .SVE_LD1SH_GATHER_D = { 1128, 1}, + .SVE_LD1SW_GATHER_D = { 1129, 1}, + .SVE_ST1B_SCATTER_S = { 1130, 1}, + .SVE_ST1B_SCATTER_D = { 1131, 1}, + .SVE_ST1H_SCATTER_S = { 1132, 1}, + .SVE_ST1H_SCATTER_D = { 1133, 1}, + .SVE_ST1W_SCATTER_S = { 1134, 1}, + .SVE_ST1W_SCATTER_D = { 1135, 1}, + .SVE_ST1D_SCATTER_D = { 1136, 1}, + .SME_LD1B_TILE = { 1137, 1}, + .SME_LD1H_TILE = { 1138, 1}, + .SME_LD1W_TILE = { 1139, 1}, + .SME_LD1D_TILE = { 1140, 1}, + .SME_LD1Q_TILE = { 1141, 1}, + .SME_ST1B_TILE = { 1142, 1}, + .SME_ST1H_TILE = { 1143, 1}, + .SME_ST1W_TILE = { 1144, 1}, + .SME_ST1D_TILE = { 1145, 1}, + .SME_ST1Q_TILE = { 1146, 1}, + .SME_MOVA_Z_FROM_TILE = { 1147, 1}, + .SME_MOVA_TILE_FROM_Z = { 1148, 1}, + .FCMLA_4H = { 1149, 1}, + .FCMLA_8H = { 1150, 1}, + .FCMLA_4S = { 1151, 1}, + .FCMLA_2D = { 1152, 1}, + .FCADD_4H = { 1153, 1}, + .FCADD_8H = { 1154, 1}, + .FCADD_4S = { 1155, 1}, + .FCADD_2D = { 1156, 1}, + .SVE_PRFB = { 1157, 1}, + .SVE_PRFH = { 1158, 1}, + .SVE_PRFW = { 1159, 1}, + .SVE_PRFD = { 1160, 1}, + .SVE_LDNT1B = { 1161, 1}, + .SVE_LDNT1H = { 1162, 1}, + .SVE_LDNT1W = { 1163, 1}, + .SVE_LDNT1D = { 1164, 1}, + .SVE_STNT1B = { 1165, 1}, + .SVE_STNT1H = { 1166, 1}, + .SVE_STNT1W = { 1167, 1}, + .SVE_STNT1D = { 1168, 1}, + .SVE_EXT = { 1169, 1}, + .SVE_SPLICE = { 1170, 1}, + .SVE_INDEX_II = { 1171, 1}, + .SVE_INDEX_IR = { 1172, 1}, + .SVE_INDEX_RI = { 1173, 1}, + .SVE_INDEX_RR = { 1174, 1}, + .SVE_BSL = { 1175, 1}, + .SVE_BSL1N = { 1176, 1}, + .SVE_BSL2N = { 1177, 1}, + .SVE_NBSL = { 1178, 1}, + .SVE_PMUL_VEC = { 1179, 1}, + .SVE_PMULLB = { 1180, 1}, + .SVE_PMULLT = { 1181, 1}, + .SVE_BFCVT = { 1182, 1}, + .SVE_BFCVTNT = { 1183, 1}, + .LDRAA = { 1184, 1}, + .LDRAB = { 1185, 1}, + .LDRAA_PRE = { 1186, 1}, + .LDRAB_PRE = { 1187, 1}, + .TSTART = { 1188, 1}, + .TCOMMIT = { 1189, 1}, + .TCANCEL = { 1190, 1}, + .TTEST = { 1191, 1}, + .WFET = { 1192, 1}, + .WFIT = { 1193, 1}, + .BC_COND = { 1194, 1}, + .UXTB = { 1195, 1}, + .UXTH = { 1196, 1}, + .UXTW = { 1197, 1}, + .SXTB = { 1198, 1}, + .SXTH = { 1199, 1}, + .SXTW = { 1200, 1}, + .ADC = { 1201, 2}, + .ADCS = { 1203, 2}, + .SBC = { 1205, 2}, + .SBCS = { 1207, 2}, + .NGC = { 1209, 2}, + .NGCS = { 1211, 2}, + .LDAPUR = { 1213, 2}, + .STLUR = { 1215, 2}, + .LDAPURB = { 1217, 1}, + .STLURB = { 1218, 1}, + .LDAPURH = { 1219, 1}, + .STLURH = { 1220, 1}, + .LDAPURSB = { 1221, 2}, + .LDAPURSH = { 1223, 2}, + .LDAPURSW = { 1225, 1}, + .SVE_BFADD = { 1226, 1}, + .SVE_BFSUB = { 1227, 1}, + .SVE_BFMUL = { 1228, 1}, + .SVE_BFMLA = { 1229, 1}, + .SVE_BFMLS = { 1230, 1}, + .SB = { 1231, 1}, + .CSDB = { 1232, 1}, + .DGH = { 1233, 1}, + .PSB_CSYNC = { 1234, 1}, + .TSB_CSYNC = { 1235, 1}, + .BTI_J = { 1236, 1}, + .BTI_C = { 1237, 1}, + .BTI_JC = { 1238, 1}, + .MOV_V_ALIAS = { 1239, 2}, + .NOT_V_ALIAS = { 1241, 2}, + .LSL_IMM = { 1243, 2}, + .LSR_IMM = { 1245, 2}, + .ASR_IMM = { 1247, 2}, + .ROR_IMM = { 1249, 2}, + .SVE_BFADD_UNPRED = { 1251, 1}, + .SVE_BFSUB_UNPRED = { 1252, 1}, + .SVE_BFMUL_UNPRED = { 1253, 1}, + .SVE_BFCLAMP = { 1254, 1}, + .SVE_BFMAXNM = { 1255, 1}, + .SVE_BFMINNM = { 1256, 1}, + .SME2_LUTI2_B = { 1257, 1}, + .SME2_LUTI4_B = { 1258, 1}, + .SME2_LD1B_X2 = { 1259, 1}, + .SME2_LD1H_X2 = { 1260, 1}, + .SME2_LD1W_X2 = { 1261, 1}, + .SME2_LD1D_X2 = { 1262, 1}, + .SME2_LD1B_X4 = { 1263, 1}, + .SME2_LD1H_X4 = { 1264, 1}, + .SME2_LD1W_X4 = { 1265, 1}, + .SME2_LD1D_X4 = { 1266, 1}, + .SME2_ST1B_X2 = { 1267, 1}, + .SME2_ST1H_X2 = { 1268, 1}, + .SME2_ST1W_X2 = { 1269, 1}, + .SME2_ST1D_X2 = { 1270, 1}, + .SME2_ST1B_X4 = { 1271, 1}, + .SME2_ST1H_X4 = { 1272, 1}, + .SME2_ST1W_X4 = { 1273, 1}, + .SME2_ST1D_X4 = { 1274, 1}, + .SME2_ZIP_3 = { 1275, 1}, + .SME2_ZIP_4 = { 1276, 1}, + .SME2_UZP_3 = { 1277, 1}, + .SME2_UZP_4 = { 1278, 1}, + .TLBI_RPALOS = { 1279, 1}, + .TLBI_RPAOS = { 1280, 1}, + .AT_S1E1A = { 1281, 1}, + .DC_CIPAPA = { 1282, 1}, + .DC_CIGDPAPA = { 1283, 1}, + .TLBI_PAALL = { 1284, 1}, + .TLBI_PAALLOS = { 1285, 1}, + .AMX_LDX = { 1286, 1}, + .AMX_LDY = { 1287, 1}, + .AMX_STX = { 1288, 1}, + .AMX_STY = { 1289, 1}, + .AMX_LDZ = { 1290, 1}, + .AMX_STZ = { 1291, 1}, + .AMX_LDZI = { 1292, 1}, + .AMX_STZI = { 1293, 1}, + .AMX_EXTRX = { 1294, 1}, + .AMX_EXTRY = { 1295, 1}, + .AMX_FMA64 = { 1296, 1}, + .AMX_FMS64 = { 1297, 1}, + .AMX_FMA32 = { 1298, 1}, + .AMX_FMS32 = { 1299, 1}, + .AMX_MAC16 = { 1300, 1}, + .AMX_FMA16 = { 1301, 1}, + .AMX_FMS16 = { 1302, 1}, + .AMX_SET = { 1303, 1}, + .AMX_CLR = { 1304, 1}, + .AMX_VECINT = { 1305, 1}, + .AMX_VECFP = { 1306, 1}, + .AMX_MATINT = { 1307, 1}, + .AMX_MATFP = { 1308, 1}, + .AMX_GENLUT = { 1309, 1}, + .CPYP = { 1310, 1}, + .CPYM = { 1311, 1}, + .CPYE = { 1312, 1}, + .CPYFP = { 1313, 1}, + .CPYFM = { 1314, 1}, + .CPYFE = { 1315, 1}, + .SETP = { 1316, 1}, + .SETM = { 1317, 1}, + .SETE = { 1318, 1}, + .DC_IVAC = { 1319, 1}, + .DC_ISW = { 1320, 1}, + .DC_CSW = { 1321, 1}, + .DC_CISW = { 1322, 1}, + .DC_ZVA = { 1323, 1}, + .DC_CVAC = { 1324, 1}, + .DC_CVAU = { 1325, 1}, + .DC_CIVAC = { 1326, 1}, + .IC_IALLUIS = { 1327, 1}, + .IC_IALLU = { 1328, 1}, + .IC_IVAU = { 1329, 1}, + .AT_S1E1R = { 1330, 1}, + .AT_S1E1W = { 1331, 1}, + .AT_S1E0R = { 1332, 1}, + .AT_S1E0W = { 1333, 1}, + .AT_S1E2R = { 1334, 1}, + .AT_S1E2W = { 1335, 1}, + .AT_S1E3R = { 1336, 1}, + .AT_S1E3W = { 1337, 1}, + .AT_S12E1R = { 1338, 1}, + .AT_S12E1W = { 1339, 1}, + .AT_S12E0R = { 1340, 1}, + .AT_S12E0W = { 1341, 1}, + .TLBI_VMALLE1 = { 1342, 1}, + .TLBI_VMALLE1IS = { 1343, 1}, + .TLBI_VAE1 = { 1344, 1}, + .TLBI_VAE1IS = { 1345, 1}, + .TLBI_ASIDE1 = { 1346, 1}, + .TLBI_ASIDE1IS = { 1347, 1}, + .TLBI_VAAE1 = { 1348, 1}, + .TLBI_VAAE1IS = { 1349, 1}, + .TLBI_VALE1 = { 1350, 1}, + .TLBI_VALE1IS = { 1351, 1}, + .TLBI_VAALE1 = { 1352, 1}, + .TLBI_VAALE1IS = { 1353, 1}, + .TLBI_ALLE1 = { 1354, 1}, + .TLBI_ALLE1IS = { 1355, 1}, + .TLBI_ALLE2 = { 1356, 1}, + .TLBI_ALLE2IS = { 1357, 1}, + .TLBI_ALLE3 = { 1358, 1}, + .TLBI_ALLE3IS = { 1359, 1}, + .PRFM = { 1360, 1}, + .PRFUM = { 1361, 1}, + .PRFM_LIT = { 1362, 1}, + .MOV_REG = { 1363, 2}, + .MOV_BITMASK = { 1365, 2}, + .MVN = { 1367, 2}, + .NEG_SR = { 1369, 2}, + .NEGS = { 1371, 2}, + .CMP_SR = { 1373, 2}, + .CMP_ER = { 1375, 2}, + .CMP_IMM = { 1377, 2}, + .CMN_SR = { 1379, 2}, + .CMN_ER = { 1381, 2}, + .CMN_IMM = { 1383, 2}, + .TST_SR = { 1385, 2}, } diff --git a/core/rexcode/arm64/tablegen/specgen.lua b/core/rexcode/arm64/tablegen/specgen.lua index 234f8a77d..10a52afb2 100644 --- a/core/rexcode/arm64/tablegen/specgen.lua +++ b/core/rexcode/arm64/tablegen/specgen.lua @@ -12,6 +12,8 @@ -- encoding_table.odin in place (the hand-written core is left untouched). Every -- bit pattern is therefore reproducible and llvm-mc-backed. -- +-- Adding a family: pick a SHAPE (operand layout) and list {enum, llvm} pairs. +-- -- Run: luajit tablegen/specgen.lua (from arm64/, or with a full path) local bit = require("bit") @@ -19,26 +21,41 @@ local LLVM = "llvm-mc --assemble --arch=aarch64 --show-encoding" local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." local TABLE = DIR .. "/encoding_table.odin" +-- arrangement token -> { vt = Operand_Type, asm = llvm suffix } local ARR = { ["8B"]={vt="V_8B",asm="8b"}, ["16B"]={vt="V_16B",asm="16b"}, ["4H"]={vt="V_4H",asm="4h"}, ["8H"] ={vt="V_8H", asm="8h"}, ["2S"]={vt="V_2S",asm="2s"}, ["4S"] ={vt="V_4S", asm="4s"}, ["1D"]={vt="V_1D",asm="1d"}, ["2D"] ={vt="V_2D", asm="2d"}, } --- llvm-mc decides which arrangements are legal per instruction; over-specify and --- the invalid ones are reported + skipped. +-- over-specify; llvm-mc decides which arrangements are legal per instruction. local ALL_ARR = {"8B","16B","4H","8H","2S","4S","2D"} --- Advanced SIMD THREE_SAME (Vd.T, Vn.T, Vm.T): {enum, llvm}. -local THREE_SAME = { - {"SHADD","shadd"}, {"UHADD","uhadd"}, {"SHSUB","shsub"}, {"UHSUB","uhsub"}, - {"SRHADD","srhadd"},{"URHADD","urhadd"}, - {"SQADD","sqadd"}, {"UQADD","uqadd"}, {"SQSUB","sqsub"}, {"UQSUB","uqsub"}, - {"SMAX","smax"}, {"UMAX","umax"}, {"SMIN","smin"}, {"UMIN","umin"}, - {"SABD","sabd"}, {"UABD","uabd"}, {"SABA","saba"}, {"UABA","uaba"}, - {"MLA_V","mla"}, {"MLS_V","mls"}, - {"CMGE","cmge"}, {"CMHS","cmhs"}, {"CMTST","cmtst"}, - {"SQDMULH","sqdmulh"}, {"SQRDMULH","sqrdmulh"}, +-- Vector shapes (all operands share one arrangement T). enc lists the register +-- slots, in operand order. The encoder packs each into its 5-bit field. +local SHAPE = { + THREE_SAME = { nreg=3, enc={"VD","VN","VM"} }, -- Vd.T, Vn.T, Vm.T + TWO_SAME = { nreg=2, enc={"VD","VN"} }, -- Vd.T, Vn.T +} + +-- Families: { shape, feature, items = {{enum, llvm}, ...} } +local FAMILIES = { + { shape="THREE_SAME", feature="NEON", title="Advanced SIMD three-same (integer)", items = { + {"SHADD","shadd"}, {"UHADD","uhadd"}, {"SHSUB","shsub"}, {"UHSUB","uhsub"}, + {"SRHADD","srhadd"},{"URHADD","urhadd"}, + {"SQADD","sqadd"}, {"UQADD","uqadd"}, {"SQSUB","sqsub"}, {"UQSUB","uqsub"}, + {"SMAX","smax"}, {"UMAX","umax"}, {"SMIN","smin"}, {"UMIN","umin"}, + {"SABD","sabd"}, {"UABD","uabd"}, {"SABA","saba"}, {"UABA","uaba"}, + {"MLA_V","mla"}, {"MLS_V","mls"}, + {"CMGE","cmge"}, {"CMHS","cmhs"}, {"CMTST","cmtst"}, + {"SQDMULH","sqdmulh"}, {"SQRDMULH","sqrdmulh"}, + }}, + { shape="TWO_SAME", feature="NEON", title="Advanced SIMD two-register misc", items = { + {"NOT_V","not"}, {"RBIT_V","rbit"}, + {"REV16_V","rev16"},{"REV32_V","rev32"},{"REV64","rev64"}, + {"CLS_V","cls"}, {"CLZ_V","clz"}, {"CNT","cnt"}, + {"URECPE_V","urecpe"}, {"URSQRTE_V","ursqrte"}, + }}, } local function word(line) @@ -49,44 +66,58 @@ local function word(line) return tonumber(b4..b3..b2..b1, 16) end -local blocks, skips, n_forms = {}, {}, 0 -for _, e in ipairs(THREE_SAME) do - local mnem, llvm = e[1], e[2] - local rows = {} - for _, a in ipairs(ALL_ARR) do - local s = ARR[a].asm - local w0 = word(string.format("%s v0.%s, v0.%s, v0.%s", llvm, s, s, s)) - local w31 = word(string.format("%s v31.%s, v31.%s, v31.%s", llvm, s, s, s)) - if w0 and w31 then - local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) - local vt = ARR[a].vt - rows[#rows+1] = string.format( - "\t\t{.%s, {.%s, .%s, .%s, .NONE}, {.VD, .VN, .VM, .NONE}, 0x%s, 0x%s, .NEON, {}},", - mnem, vt, vt, vt, bit.tohex(w0):upper(), bit.tohex(mask):upper()) - n_forms = n_forms + 1 - else - skips[#skips+1] = mnem.." ."..a - end - end - if #rows > 0 then - blocks[#blocks+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) - end +local function padded(prefix_tokens, n) + local t = {} + for i = 1, 4 do t[i] = prefix_tokens[i] or ".NONE" end + return "{" .. table.concat(t, ", ") .. "}" end -local region = "\t// SPECGEN:BEGIN\n" .. - "\t// Advanced SIMD three-same (integer).\n" .. - table.concat(blocks, "\n") .. "\n\t// SPECGEN:END" +local sections, skips, n_forms, n_mnem = {}, {}, 0, 0 +for _, fam in ipairs(FAMILIES) do + local sh = SHAPE[fam.shape] + local enc_tokens = {}; for i, e in ipairs(sh.enc) do enc_tokens[i] = "."..e end + local enc_str = padded(enc_tokens, sh.nreg) + local blocks = {} + for _, it in ipairs(fam.items) do + local mnem, llvm = it[1], it[2] + local rows = {} + for _, a in ipairs(ALL_ARR) do + local s = ARR[a].asm + local function mk(reg) + local parts = {}; for i = 1, sh.nreg do parts[i] = "v"..reg.."."..s end + return llvm.." "..table.concat(parts, ", ") + end + local w0, w31 = word(mk(0)), word(mk(31)) + if w0 and w31 then + local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) + local op_tokens = {}; for i = 1, sh.nreg do op_tokens[i] = "."..ARR[a].vt end + rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", + mnem, padded(op_tokens, sh.nreg), enc_str, + bit.tohex(w0):upper(), bit.tohex(mask):upper(), fam.feature) + n_forms = n_forms + 1 + else + skips[#skips+1] = mnem.." ."..a + end + end + if #rows > 0 then + blocks[#blocks+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + n_mnem = n_mnem + 1 + end + end + sections[#sections+1] = string.format("\t// %s.\n%s", fam.title, table.concat(blocks, "\n")) +end + +local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() -local repl = region:gsub("%%", "%%%%") -local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", repl) +local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", (region:gsub("%%", "%%%%"))) if n ~= 1 then io.stderr:write("FATAL: expected exactly one SPECGEN:BEGIN..END region, found "..n.."\n") os.exit(1) end local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close() -io.write(string.format("specgen: wrote %d mnemonics / %d forms into %s\n", #blocks, n_forms, TABLE)) +io.write(string.format("specgen: wrote %d mnemonics / %d forms into %s\n", n_mnem, n_forms, TABLE)) if #skips > 0 then io.write(" skipped "..#skips.." invalid arrangement(s): "..table.concat(skips, ", ").."\n") end diff --git a/core/rexcode/arm64/tables/arm64.encode_forms.bin b/core/rexcode/arm64/tables/arm64.encode_forms.bin index 99687c75d..3796da063 100644 Binary files a/core/rexcode/arm64/tables/arm64.encode_forms.bin and b/core/rexcode/arm64/tables/arm64.encode_forms.bin differ diff --git a/core/rexcode/arm64/tables/arm64.encode_runs.bin b/core/rexcode/arm64/tables/arm64.encode_runs.bin index 227bede88..3d107a7ff 100644 Binary files a/core/rexcode/arm64/tables/arm64.encode_runs.bin and b/core/rexcode/arm64/tables/arm64.encode_runs.bin differ diff --git a/core/rexcode/arm64/tables/arm64.entries.bin b/core/rexcode/arm64/tables/arm64.entries.bin index 2448d59d2..f71ebcdcb 100644 Binary files a/core/rexcode/arm64/tables/arm64.entries.bin and b/core/rexcode/arm64/tables/arm64.entries.bin differ diff --git a/core/rexcode/arm64/tables/arm64.idx_op0.bin b/core/rexcode/arm64/tables/arm64.idx_op0.bin index e9a9f92db..efa5da64f 100644 Binary files a/core/rexcode/arm64/tables/arm64.idx_op0.bin and b/core/rexcode/arm64/tables/arm64.idx_op0.bin differ