diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 2fb303ab1..10c0eb37e 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -213,7 +213,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- NEON copy/permute index fields ------------------------------------ case .VN_VM_DUP: - return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .NEON_IDX5: // imm5 = index << (markerbit+1) | (1 << markerbit); marker = lowest set bit. imm5 := (word >> 16) & 0x1F @@ -246,7 +246,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .PN_PM_DUP, .PN_PG_PM_DUP: return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .ZD_ZM_DUP: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .SVE_EXT_IMM: v := ((word >> 16) & 0x1F) << 3 | ((word >> 10) & 0x7) return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} @@ -338,6 +338,35 @@ extract_operand_inline :: #force_inline proc "contextless" ( }, kind = .MEMORY, size = 4, } + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7 at 21:15, scaled by the transfer size. The + // addressing mode is bits[24:23] of the word (01 post, 11 pre, + // 10 signed offset / 00 no-allocate), not part of the encoding. + base_hw := u8((word >> 5) & 0x1F) + imm7 := i32((word >> 15) & 0x7F) + if imm7 & (1 << 6) != 0 { + imm7 |= ~i32(0x7F) + } + scale := i32(4) + if en == .OFFSET_PAIR_8 { + scale = 8 + } else if en == .OFFSET_PAIR_16 { + scale = 16 + } + mode := Address_Mode.OFFSET + switch (word >> 23) & 0x3 { + case 0b01: mode = .POST_INDEXED + case 0b11: mode = .PRE_INDEXED + } + return Operand{ + mem = Memory{ + base = Register(REG_X | u16(base_hw)), + index = NONE, + disp = imm7 * scale, + mode = mode, + }, + kind = .MEMORY, size = 4, + } case .OFFSET_REG, .OFFSET_EXT: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) @@ -406,18 +435,17 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64(value), kind = .IMMEDIATE, size = is_64 ? 8 : 4} // ---- NEON / SIMD register slots ---- + // The class comes from the operand TYPE, not from the encoding: SVE forms + // use these same Vd/Vn/Vm slots with Z_REG_* operands, so hardcoding + // REG_V here decoded `add z0.d, z0.d, z0.d` as a V register. case .VD: - hw := u16(word & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 0, ot) case .VN: - hw := u16((word >> 5) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 5, ot) case .VM: - hw := u16((word >> 16) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 16, ot) case .VA: - hw := u16((word >> 10) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 10, ot) // ---- NEON / SVE indexed/immediate fields ---- case .NEON_IMM8_FMOV: @@ -607,17 +635,24 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .ENC_LSL_IMM_X: imms := (word >> 10) & 0x3F return Operand{immediate = i64((63 - imms) & 0x3F), kind = .IMMEDIATE, size = 1} + case .ENC_IMM6_LO: + v := i32((word >> 5) & 0x3F) + if v & (1 << 5) != 0 { v |= ~i32(0x3F) } // sign-extend from bit 5 + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + case .ENC_SHIFT_IMMR: + // LSR/ASR immediate: the shift is immr verbatim (bits 21:16). + return Operand{immediate = i64((word >> 16) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_DUAL_RN_RM: // Take the Rn slot (9:5) as the source register. return Operand{reg = Register(REG_X | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} case .ENC_ROR_SHIFT: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: - return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM: - return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} } return {} } @@ -656,7 +691,37 @@ reg_from_field :: #force_inline proc "contextless" ( if (ot == .WSP_REG && hw == 31) || (ot == .XSP_REG && hw == 31) { return Operand{reg = Register(cls | 31), kind = .REGISTER, size = 4} } - return Operand{reg = Register(cls | hw), kind = .REGISTER, size = 4} + // Vector operands carry their arrangement / element view in `size`, using + // the same codes op_v_*/op_z_* produce (see operands.odin). Without this a + // decoded V register would come back as a bare `v0` with no `.4s`, so a + // disassembly could not be fed back to an assembler. + return Operand{reg = Register(cls | hw), kind = .REGISTER, size = reg_size_for_type(ot)} +} + +// The `size` marker an operand of this type carries: the NEON arrangement +// (multiples of 8), an element view (odd), or an SVE element width. 4 is the +// neutral "no vector shape" value used by every scalar class. +@(private="file", require_results) +reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .V_8B: return 8 + case .V_16B: return 16 + case .V_4H, .V_4H_FP16: return 24 + case .V_8H, .V_8H_FP16: return 32 + case .V_2S: return 40 + case .V_4S: return 48 + case .V_1D: return 56 + case .V_2D: return 64 + case .V_ELEM_B: return 1 + case .V_ELEM_H: return 3 + case .V_ELEM_S: return 5 + case .V_ELEM_D: return 7 + case .Z_REG_B: return 1 + case .Z_REG_H: return 2 + case .Z_REG_S: return 4 + case .Z_REG_D: return 8 + } + return 4 } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index b8de703d7..304311f25 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -231,14 +231,16 @@ operand_matches_inline :: #force_inline proc "contextless" ( // Element-indexed V views: element size carried in op.size (B=1,H=2,S=4, // D=8) so DUP/INS forms disambiguate. .S also accepts size 0 so a plain // op_reg (as the hand-written SM3TT forms pass) still matches the .S slot. + // Element-view sizes are odd (1/3/5/7) so they can never be confused with + // an arrangement, which is always a multiple of 8 (see op_v_elem_*). case .V_ELEM_B: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 1 case .V_ELEM_H: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 2 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 3 case .V_ELEM_S: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 4 || op.size == 0) + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 5 || op.size == 0) case .V_ELEM_D: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 8 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 7 // SVE Z registers. Element size carried in op.size: B=1, H=2, S=4, D=8. // op.size==0 (legacy / default-constructed) accepts any width. @@ -440,6 +442,19 @@ pack_operand_inline :: #force_inline proc( // Atomic addressing: [Xn] only -- no displacement, no shift. // Used by load/store exclusives, acquire/release, LSE atomics. return (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7, scaled by the transfer size, at bits 21:15. + // The pre/post marker is already in the form's bits, so nothing is + // ORed into bits 11:10 -- those belong to Rt2. + scale := i32(4) + if enc == .OFFSET_PAIR_8 { + scale = 8 + } else if enc == .OFFSET_PAIR_16 { + scale = 16 + } + base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + imm_bits := u32((i32(op.mem.disp) / scale) & 0x7F) + return base_bits | (imm_bits << 15) case .OFFSET_REG: // [Xn, Xm{, LSL #s}]: option=011, S = shift!=0. base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 @@ -777,6 +792,16 @@ pack_operand_inline :: #force_inline proc( immr := ((~imm + 1) & 0x3F) imms := (63 - imm) & 0x3F return (immr << 16) | (imms << 10) + case .ENC_IMM6_LO: + // Signed 6-bit at bits 10:5 (RDSVL); range -32..31. + return (u32(op.immediate) & 0x3F) << 5 + case .ENC_SHIFT_IMMR: + // LSR/ASR by immediate: immr = shift at bits 21:16. imms is the + // constant 31 / 63 already present in the form's bits, so unlike + // ENC_LSL_IMM_* there is nothing to compute for it. Mask to the + // register width so a W-form shift cannot spill into bit 21. + width := form.flags.is_64 ? u32(0x3F) : u32(0x1F) + return (u32(op.immediate) & width) << 16 case .ENC_DUAL_RN_RM: // Pack the register at both Rn (9:5) AND Rm (20:16) slots // (for ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm). diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 2b8c2775d..17816ae81 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -215,6 +215,13 @@ Operand_Encoding :: enum u8 { IMM6, // bits 10-15 (shift amount; SHAMT) IMM9, // bits 12-20 (signed 9-bit; LDUR/pre/post) IMM_HW, // bits 21-22 (MOVZ/MOVN/MOVK hw field; value is shift/16) + // LSR/ASR by immediate are UBFM/SBFM Rd, Rn, #shift, #(31|63): the shift + // goes to immr and imms is a constant already fixed in the form's bits, + // so unlike LSL (ENC_LSL_IMM_*) only one field is operand-driven. + ENC_SHIFT_IMMR, // bits 16-21 (immr; LSR/ASR immediate aliases) + // RDSVL / the RDVL family put their signed 6-bit immediate at bits 10:5, + // not where IMM6 (bits 15:10) writes it. + ENC_IMM6_LO, // bits 5-10 (signed 6-bit; RDSVL) IMM_SH12, // bit 22 (ADD/SUB imm: LSL #12 flag) SHIFT_TYPE, // bits 22-23 (LSL/LSR/ASR/ROR for shifted-register) EXT_OPT, // bits 13-15 (extend type for extended-register) @@ -232,6 +239,19 @@ Operand_Encoding :: enum u8 { OFFSET_BASE_PRE, // [Xn, #imm]! signed-9 pre-index OFFSET_BASE_POST, // [Xn], #imm signed-9 post-index OFFSET_BASE_A, // [Xn] no displacement (exclusives, acquire/release, LSE) + // LDP/STP family. Nothing like the single-register modes above: the + // displacement is a signed 7-bit value SCALED by the transfer size at + // bits 21:15 (single-register forms use an unscaled 9-bit at 20:12), and + // bits 11:10 are part of Rt2 here, so the pre/post markers the + // single-register encodings OR in would corrupt the second register. + // The scale cannot be read off the register type -- LDPSW pairs X + // registers but loads words (scale 4), STGP pairs X registers and scales + // by 16 -- so it is spelled out per encoding. The addressing mode lives + // in the form's bits[24:23] (01 post, 10 signed offset, 11 pre), which + // is where the decoder reads it back from. + OFFSET_PAIR_4, // [Xn{, #imm}] / [Xn, #imm]! / [Xn], #imm -- imm7 x 4 + OFFSET_PAIR_8, // imm7 x 8 + OFFSET_PAIR_16, // imm7 x 16 OFFSET_REG, // [Xn, Rm{, LSL #s}] register offset OFFSET_EXT, // [Xn, Wm, SXTW|UXTW|SXTX #s] diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 867da7559..0cb0f3c25 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -211,23 +211,28 @@ op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand { } // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides -// in op.size (1/2/4/8) so the matcher can disambiguate DUP/INS forms; the lane -// index is a separate immediate operand. +// in op.size so the matcher can disambiguate DUP/INS forms; the lane index is +// a separate immediate operand. +// +// The codes are ODD (1/3/5/7) on purpose: arrangement operands above use +// multiples of 8, so a size can never mean both. They used to be 1/2/4/8, +// which made an element-D view indistinguishable from an 8B arrangement -- +// the printer cannot tell `.d` from `.8b` if both are size 8. @(require_results) op_v_elem_b :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 1} } @(require_results) op_v_elem_h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 2} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 3} } @(require_results) op_v_elem_s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 5} } @(require_results) op_v_elem_d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 7} } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 1459b062b..ce2015007 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -115,21 +115,35 @@ sbprint :: proc( write_full_mnemonic(sb, inst, opts.uppercase) - // B.cond's condition is encoded into the mnemonic suffix (b.eq), - // so when printing we skip the first operand (it IS the cond). + // B.cond / BC.cond fold the condition into the mnemonic (b.eq), so the + // operand carrying it must not be printed a second time. start_slot := 0 - if inst.mnemonic == .B_COND && inst.operand_count >= 1 && inst.ops[0].kind == .COND { + if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && + inst.operand_count >= 1 && inst.ops[0].kind == .COND { start_slot = 1 } - if int(inst.operand_count) > start_slot { + // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), + // which assemblers write as `lsl #16` and omit entirely when it is zero. + mov_wide := inst.mnemonic == .MOVZ || inst.mnemonic == .MOVN || inst.mnemonic == .MOVK + end_slot := int(inst.operand_count) + if mov_wide && end_slot == 3 && inst.ops[2].kind == .IMMEDIATE && inst.ops[2].immediate == 0 { + end_slot = 2 + } + + if end_slot > start_slot { strings.write_byte(sb, ' ') - for slot in start_slot.. start_slot { strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } - write_operand(sb, &inst.ops[slot], &display, opts) + if mov_wide && slot == 2 { + strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") + write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) + } else { + write_operand(sb, &inst.ops[slot], &display, opts) + } } } strings.write_string(sb, opts.separator) @@ -335,6 +349,56 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { } } +// NEON arrangement (`.4s`), element view (`.d`) or SVE element width (`.s`) +// suffix. Vector operands carry the shape in op.size using the codes +// op_v_*/op_z_* produce and the decoder restores (see operands.odin); +// arrangements are multiples of 8, element views are odd, and the neutral 4 +// that every scalar class uses prints nothing. +// +// NOTE: an element-indexed operand still prints as `v0.s` -- the lane index +// rides in a separate immediate operand, so `v0.s[2]` needs the printer to +// fold that operand into this one, which it does not yet do. +@(private="file") +write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { + shape := "" + switch reg_class(r) { + case REG_V: + switch size { + case 8: shape = "8b" + case 16: shape = "16b" + case 24: shape = "4h" + case 32: shape = "8h" + case 40: shape = "2s" + case 48: shape = "4s" + case 56: shape = "1d" + case 64: shape = "2d" + case 1: shape = "b" + case 3: shape = "h" + case 5: shape = "s" + case 7: shape = "d" + } + case REG_Z: + switch size { + case 1: shape = "b" + case 2: shape = "h" + case 4: shape = "s" + case 8: shape = "d" + } + } + if shape == "" { + return + } + strings.write_byte(sb, '.') + for i in 0..= 'a' && c <= 'z' { + strings.write_byte(sb, c - 32) + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { if r == NONE { strings.write_string(sb, ""); return } @@ -402,6 +466,7 @@ write_operand :: proc( case .REGISTER: write_register(sb, op.reg, opts.uppercase) + write_vector_shape(sb, op.reg, op.size, opts.uppercase) case .IMMEDIATE: strings.write_byte(sb, '#') diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index c22a72863..0557a8304 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -44,12 +44,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, + { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, @@ -64,16 +64,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, @@ -107,16 +107,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, @@ -127,18 +127,18 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, @@ -149,37 +149,37 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, @@ -198,69 +198,69 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, @@ -272,24 +272,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, @@ -318,16 +318,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, @@ -370,8 +370,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, @@ -382,8 +382,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, @@ -449,12 +449,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, @@ -462,13 +462,13 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, @@ -477,24 +477,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, @@ -510,9 +510,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, @@ -638,26 +638,26 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, @@ -668,8 +668,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, @@ -758,12 +758,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, @@ -902,9 +902,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, @@ -912,14 +912,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {} }, @@ -931,17 +931,17 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {} }, @@ -952,12 +952,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {} }, { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {} }, @@ -975,20 +975,20 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {} }, - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, @@ -1119,8 +1119,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, @@ -1270,7 +1270,7 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, @@ -1706,14 +1706,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, @@ -1807,16 +1807,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, @@ -1844,10 +1844,10 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, @@ -1895,11 +1895,11 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 330bd68e0..c16426c73 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -141,8 +141,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ASR { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -150,8 +150,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ROR { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -361,29 +361,29 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, // .LDAR { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, @@ -893,11 +893,11 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .LDURSW { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, // .LDXP { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, @@ -1186,7 +1186,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .STZ2G { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, // .LDGM { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, // .STGM @@ -1291,7 +1291,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, // .BFMMLA { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, // .BFMLALB @@ -2836,7 +2836,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .SMSTOP { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, // .ADDHA { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, // .ADDVA @@ -2875,10 +2875,10 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, // .FCADD { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, @@ -2924,9 +2924,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .PMUL { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, // .BFCVTNT { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, // .LDRAA @@ -3025,9 +3025,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .TSB_CSYNC { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, // .BTI_J - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_C - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP @@ -3057,9 +3057,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .DC_CIGDPAPA { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true} }, // .TLBI_PAALL - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, // .AMX_LDY diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index ec9f178f9..fb287288e 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -254,8 +254,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ASR = { {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -264,8 +264,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ROR = { {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -519,31 +519,31 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, @@ -1132,12 +1132,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, @@ -1546,7 +1546,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, @@ -1697,7 +1697,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3540,7 +3540,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, }, .ADDHA = { {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, @@ -3596,10 +3596,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3665,10 +3665,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .BFCVTNT = { {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3809,10 +3809,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_JC = { {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, @@ -3856,10 +3856,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, diff --git a/core/rexcode/isa/arm64/tablegen/specgen.lua b/core/rexcode/isa/arm64/tablegen/specgen.lua index 5dbd1d4cf..13197ba8a 100644 --- a/core/rexcode/isa/arm64/tablegen/specgen.lua +++ b/core/rexcode/isa/arm64/tablegen/specgen.lua @@ -7,9 +7,16 @@ -- the differing bits are operand-driven, so mask = ~(bits0 ^ bits31). Per-form -- assembly makes it robust: an arrangement llvm-mc rejects is reported, skipped. -- --- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin --- in place; the hand-written core is untouched. Every bit pattern is therefore --- reproducible and llvm-mc-backed. +-- Output is MERGED into instruction_table.odin: a generated form is inserted +-- into its mnemonic's block only if no form with the same (mnemonic, bits, +-- mask) is there already. Existing rows are never rewritten -- their Clobber +-- data is hand-maintained and must not be clobbered (pun intended) by a +-- regeneration. So this is an "add the forms that are missing" tool, which is +-- what it is actually for. Every bit pattern is llvm-mc-backed. +-- +-- Merging (rather than owning a whole region) is required because a Mnemonic +-- is now an ASSEMBLER mnemonic: ADD holds the integer, NEON and SVE forms in +-- one block, so specgen cannot own `.ADD = { ... }` outright. -- -- Two spec kinds: -- * uniform — every operand shares one arrangement T (iterate ALL_ARR). @@ -21,7 +28,7 @@ local bit = require("bit") local LLVM = "llvm-mc --assemble --arch=aarch64 --mattr=+fullfp16 --show-encoding" local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." -local TABLE = DIR .. "/encoding_table.odin" +local TABLE = DIR .. "/instruction_table.odin" local ARR = { ["8B"]={vt="V_8B",asm="8b"}, ["16B"]={vt="V_16B",asm="16b"}, @@ -53,6 +60,78 @@ local function padded(tokens, n) return "{" .. table.concat(t, ", ") .. "}" end +-- The Mnemonic enum holds assembler mnemonics, so the ISA-namespace prefixes +-- and per-encoding suffixes these specs were written against are gone. +local CANON_PRE = {"SVE2_", "SVE_", "SME2_", "SME_"} +local CANON_SUF = { + "_GATHER_S","_GATHER_D","_SCATTER_S","_SCATTER_D","_FROM_TILE","_TILE_FROM", + "_UNPRED","_BITMASK","_SCALAR","_ALIAS","_PRED","_TILE","_LANE", + "_IDX","_GEN","_LIT","_IMM","_VEC","_PRE","_POST","_REG", + "_4H","_8H","_4S","_2D","_1D","_2S","_8B","_16B", + "_II","_IR","_RI","_RR","_X2","_X4","_SR","_ER","_ZA", + "_Z","_P","_V","_H","_S","_D","_B","_3","_4", +} +local CANON_KEEP = { B_COND=true, BC_COND=true } +local CANON_RENAME = { LSLV="LSL", LSRV="LSR", ASRV="ASR", RORV="ROR" } +local function canon(name) + if CANON_KEEP[name] then return name end + for _, k in ipairs({"DC_","IC_","AT_","TLBI_","BTI_","PSB_","TSB_"}) do + if name:sub(1, #k) == k then return name end + end + local c = CANON_RENAME[name] or name + for _, pre in ipairs(CANON_PRE) do + if c:sub(1, #pre) == pre then c = c:sub(#pre + 1); break end + end + local changed = true + while changed do + changed = false + for _, suf in ipairs(CANON_SUF) do + if #c > #suf and c:sub(-#suf) == suf then + local stem = c:sub(1, #c - #suf) + if #stem > 0 and stem:sub(-1) ~= "_" then c = stem; changed = true; break end + end + end + end + return (#c > 0) and c or name +end + +-- A Form is an Encoding plus a Clobber. For the data-processing shapes this +-- tool emits, slot 0 is the destination and every later register-ish slot is a +-- source (a destination repeated in a later slot -- SVE destructive forms -- +-- is therefore correctly counted as a read too). +local REG_SLOT = { + VD=true, VN=true, VM=true, VA=true, RD=true, RN=true, RM=true, RA=true, + PD=true, PN=true, PM=true, PG=true, PG4=true, PM3=true, RT=true, RT2=true, +} +-- The table aligns the operand tuple at a fixed column; keep generated rows +-- looking like the hand-written ones around them. +local function mnem_field(name) + local s = "{{." .. name .. "," + return s .. string.rep(" ", math.max(1, 28 - #s)) +end + +-- The table also aligns the Clobber at a fixed column. Applied once at merge +-- time so every row formatter stays a plain string.format. +-- The table is not uniformly aligned (166..176 across sections); 169 is the +-- dominant column, so new rows land in the majority style. +local CLOBBER_COL = 169 +local function align_row(row) + local head, tail = row:match("^(.-%}%},) (%{.*)$") + if not head then return row end + return head .. string.rep(" ", math.max(1, CLOBBER_COL - #head)) .. tail +end + +local function clobber_of(enc_str) + local slots = {} + for tok in enc_str:gmatch("%.([%w_]+)") do slots[#slots+1] = tok end + local reads = {} + for i = 2, #slots do + if REG_SLOT[slots[i]] then reads[#reads+1] = tostring(i - 1) end + end + if #reads == 0 then return "{written={0}}" end + return string.format("{written={0}, read={%s}}", table.concat(reads, ", ")) +end + local sections, skips, n_forms, n_mnem = {}, {}, 0, 0 -- Emit one mnemonic's block from a list of arrangement tuples (operand order). @@ -72,8 +151,8 @@ local function emit(mnem, llvm, enc_str, feature, variants) for i, t in ipairs(tup) do ops[i] = "."..tok_vt(t) end local f = feature for _, tk in ipairs(tup) do if ARR[tk] and ARR[tk].feat then f = ARR[tk].feat end end - rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", - mnem, padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + rows[#rows+1] = string.format("\t\t%s%s, %s, 0x%s, 0x%s, .%s, {}}, %s},", + mnem_field(canon(mnem)), padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f, clobber_of(enc_str)) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..table.concat(tup, "/") @@ -81,7 +160,7 @@ local function emit(mnem, llvm, enc_str, feature, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- Compare-against-zero: a 2-register shape whose asm carries a literal #0 @@ -97,8 +176,8 @@ local function emit_cmp0(mnem, llvm, fp, arr) local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) local f = ARR[a].feat or "NEON" rows[#rows+1] = string.format( - "\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - mnem, ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + "\t\t{{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + canon(mnem), ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a @@ -106,7 +185,7 @@ local function emit_cmp0(mnem, llvm, fp, arr) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- ---- Uniform shapes (all operands share one arrangement) ------------------- @@ -311,7 +390,7 @@ local function emit_shift(mnem, llvm, dir, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end local SAME_SH = {} for _, a in ipairs({"8B","16B","4H","8H","2S","4S","2D"}) do SAME_SH[#SAME_SH+1] = {a, a} end @@ -366,12 +445,12 @@ local ELEM = { do local blk = {} local function emit_rows(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end local function mkrow(mnem, ops, enc, b0, variants) n_forms = n_forms + 1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .NEON, {}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper()) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .NEON, {}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper(), clobber_of(enc)) end -- MOV Vd.T, Vn.T (= ORR Vd,Vn,Vn): the single source feeds both Vn and Vm. @@ -467,7 +546,7 @@ end do local blk = {} local function block(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end -- scalar FP two-register (FRINTx, FRECPX): Sd, Sn. for _, it in ipairs({ @@ -479,8 +558,8 @@ do local function mk(r) return string.format("%s %s%d, %s%d", it[2], sc[1], r, sc[1], r) end local b0, b31 = word(mk(0)), word(mk(31)) if b0 and b31 then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) n_forms = n_forms + 1 end end @@ -499,8 +578,8 @@ do local bD = word(mk(gp[3], fp[1].."0")) -- Rd field (zero reg) local bN = word(mk(gp[1].."0", fp[1].."31")) -- Rn field if b0 and bD and bN then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) n_forms = n_forms + 1 end end @@ -526,12 +605,12 @@ do local function mk(r,v) return string.format("%s v%d.%s, #%s", llvm, r, ARR[a].asm, tostring(v)) end local b0, bR, bI = word(mk(0,"0")), word(mk(31,"0")), word(mk(0,vmax)) if b0 and bR and bI then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}},", - mnem, ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) + rows[#rows+1] = string.format("\t\t%s{.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}}, {written={0}}},", + mnem_field(canon(mnem)), ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a end end - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end imm8_block("MOVI", "movi", {"8B","16B","4H","8H","2S","4S","2D"}) imm8_block("MVNI", "mvni", {"4H","8H","2S","4S"}) @@ -565,12 +644,12 @@ do local w=sve_word(build(v)); if not w then skips[#skips+1]=mnem..":v"..i; return nil end; vs[#vs+1]=w end n_forms=n_forms+1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .SVE, {%s}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .SVE, {%s}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags, clobber_of(enc)) end local function block(mnem, rows) local r={}; for _,x in ipairs(rows) do if x then r[#r+1]=x end end - if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(r,"\n")); n_mnem=n_mnem+1 end + if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(r,"\n")); n_mnem=n_mnem+1 end end local function g(v, x) if v==0 then return x and "x0" or "w0" else return x and "xzr" or "wzr" end end @@ -690,17 +769,68 @@ do sections[#sections+1] = "\t// SVE predicated / compare / predicate-logical / SVE2.\n" .. table.concat(blk, "\n") end --- ---- splice into the SoT --------------------------------------------------- -local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" +-- ---- merge into the SoT ---------------------------------------------------- +-- +-- Every generated block is `\t.MNEM = {\n\n\t},`. Take it apart, and add +-- each row to that mnemonic's existing block ONLY when no form with the same +-- (mnemonic, bits, mask) is present. Existing rows are left byte-for-byte +-- alone so hand-maintained Clobber data survives a regeneration. local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() -local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", (region:gsub("%%", "%%%%"))) -if n ~= 1 then - io.stderr:write("FATAL: expected exactly one SPECGEN:BEGIN..END region, found "..n.."\n") - os.exit(1) -end -local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close() -io.write(string.format("specgen: wrote %d mnemonics / %d forms into %s\n", n_mnem, n_forms, TABLE)) +local generated = {} -- ordered list of {mnem=, rows={}} +local by_mnem = {} +for _, sec in ipairs(sections) do + for mnem, body in sec:gmatch("\t%.([%w_]+) = {\n(.-)\n\t},") do + local g = by_mnem[mnem] + if not g then + g = {mnem = mnem, rows = {}} + by_mnem[mnem] = g + generated[#generated+1] = g + end + for row in body:gmatch("[^\n]+") do g.rows[#g.rows+1] = row end + end +end + +local added, present, created = 0, 0, 0 +for _, g in ipairs(generated) do + local head = "\t." .. g.mnem .. " = {\n" + local s, e = src:find(head, 1, true) + local fresh = {} + for _, row in ipairs(g.rows) do + -- (bits, mask) uniquely identify a form within one mnemonic's run. + local bits, mask = row:match("(0x%x+), (0x%x+)") + local dup = false + if s and bits then + local _, blk_end = src:find("\n\t},", e, true) + local block = src:sub(e, blk_end or #src) + dup = block:find(bits .. ", " .. mask, 1, true) ~= nil + end + if dup then present = present + 1 else fresh[#fresh+1] = align_row(row) end + end + if #fresh > 0 then + if s then + -- insert BEFORE the block terminator; splitting inside "\n\t}," would + -- leave its comma stranded after the appended rows. + local term = src:find("\n\t},", e, true) + src = src:sub(1, term - 1) .. "\n" .. table.concat(fresh, "\n") .. src:sub(term) + else + src = src:gsub("\n}%s*$", "\n" .. head .. table.concat(fresh, "\n") .. "\n\t},\n}\n", 1) + created = created + 1 + end + added = added + #fresh + end +end + +local wh = assert(io.open(TABLE, "w")); wh:write(src); wh:close() + +io.write(string.format("specgen: %d forms generated across %d mnemonics\n", n_forms, n_mnem)) +io.write(string.format(" already present: %d added: %d new mnemonic blocks: %d\n", present, added, created)) +io.write(" -> " .. TABLE .. "\n") +if added > 0 then + io.write(" NOTE: added rows carry a derived Clobber (dest = slot 0, later\n") + io.write(" register slots = reads). Review it for anything that also\n") + io.write(" touches NZCV/FPSR/memory before committing.\n") +end if #skips > 0 then io.write(" skipped "..#skips.." invalid arrangement(s)\n") end diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 3c031af32..0d8f5415c 100644 Binary files a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin and b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin differ diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index e4180663c..e91371560 100644 Binary files a/core/rexcode/isa/arm64/tables/arm64.entries.bin and b/core/rexcode/isa/arm64/tables/arm64.entries.bin differ diff --git a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin index 774cb03db..dae368cf2 100644 --- a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin @@ -997,7 +997,7 @@ run_pipeline_tests :: proc() { byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) ok("barriers/BTI: encode", success) eq_word("SB", load_le(code[:], 0), 0xD50330FF) - eq_word("BTI j", load_le(code[:], 4), 0xD503245F) + eq_word("BTI j", load_le(code[:], 4), 0xD503249F) eq_word("PSB CSYNC", load_le(code[:], 8), 0xD503223F) } diff --git a/core/rexcode/isa/arm64/tests/smoke.odin b/core/rexcode/isa/arm64/tests/smoke.odin index eafcb39b8..22bece4d5 100644 --- a/core/rexcode/isa/arm64/tests/smoke.odin +++ b/core/rexcode/isa/arm64/tests/smoke.odin @@ -234,7 +234,7 @@ main :: proc() { // ---- SME ---------------------------------------------------------------- check("SME_SMSTART", .SMSTART, 0, 0xD503477F, 0xFFFFFFFF) check("SME_SMSTOP", .SMSTOP, 0, 0xD503467F, 0xFFFFFFFF) - check("SME_RDSVL", .RDSVL, 0, 0x04BF5800, 0xFFFFFC00) + check("SME_RDSVL", .RDSVL, 0, 0x04BF5800, 0xFFFFF800) check("FMOPA S", .FMOPA, 0, 0x80800000, 0xFFE08010) check("SME_BFMOPA", .BFMOPA, 0, 0x81800000, 0xFFE08010) check("SMOPA S", .SMOPA, 0, 0xA0800000, 0xFFE08010) @@ -333,10 +333,10 @@ main :: proc() { check("SME_MOVA_TILE_FROM_Z", .MOVA, 1, 0xC0000000, 0xFFE08010) // ---- NEON FCMLA / FCADD (v8.3-A FCMA) -- verified vs LLVM golden ----- - check("FCMLA_4H", .FCMLA, 0, 0x2E40C400, 0xFFA0CC00) - check("FCMLA_8H", .FCMLA, 1, 0x6E40C400, 0xFFA0CC00) - check("FCMLA_4S", .FCMLA, 2, 0x6E80C400, 0xFFA0CC00) - check("FCMLA_2D", .FCMLA, 3, 0x6EC0C400, 0xFFA0CC00) + check("FCMLA_4H", .FCMLA, 0, 0x2E40C400, 0xFFE0CC00) + check("FCMLA_8H", .FCMLA, 1, 0x6E40C400, 0xFFE0CC00) + check("FCMLA_4S", .FCMLA, 2, 0x6E80C400, 0xFFE0CC00) + check("FCMLA_2D", .FCMLA, 3, 0x6EC0C400, 0xFFE0CC00) check("FCADD_4H", .FCADD, 0, 0x2E40E400, 0xFFA0EC00) check("FCADD_4S", .FCADD, 2, 0x6E80E400, 0xFFA0EC00) @@ -363,8 +363,8 @@ main :: proc() { check("SVE_BSL1N", .BSL1N, 0, 0x04603C00, 0xFFE0FC00) check("SVE_NBSL", .NBSL, 0, 0x04E03C00, 0xFFE0FC00) check("SVE_PMUL_VEC",.PMUL,0,0x04206400, 0xFFE0FC00) - check("SVE_PMULLB", .PMULLB, 0, 0x45006800, 0xFFE0FC00) - check("SVE_PMULLT", .PMULLT, 0, 0x45006C00, 0xFFE0FC00) + check("SVE_PMULLB", .PMULLB, 0, 0x45C06800, 0xFFE0FC00) + check("SVE_PMULLT", .PMULLT, 0, 0x45C06C00, 0xFFE0FC00) // ---- SVE BF16 conversions ------------------------------------------- check("SVE_BFCVT", .BFCVT, 1, 0x658AA000, 0xFFFFE000) @@ -426,8 +426,8 @@ main :: proc() { check("DGH", .DGH, 0, 0xD50320DF, 0xFFFFFFFF) check("PSB CSYNC", .PSB_CSYNC, 0, 0xD503223F, 0xFFFFFFFF) check("TSB CSYNC", .TSB_CSYNC, 0, 0xD503225F, 0xFFFFFFFF) - check("BTI j", .BTI_J, 0, 0xD503245F, 0xFFFFFFFF) - check("BTI c", .BTI_C, 0, 0xD503249F, 0xFFFFFFFF) + check("BTI j", .BTI_J, 0, 0xD503249F, 0xFFFFFFFF) + check("BTI c", .BTI_C, 0, 0xD503245F, 0xFFFFFFFF) check("BTI jc", .BTI_JC, 0, 0xD50324DF, 0xFFFFFFFF) // ---- NEON aliases --------------------------------------------------- @@ -466,8 +466,8 @@ main :: proc() { // ---- RME (Realm Management Extension) ------------------------------- check("TLBI RPALOS", .TLBI_RPALOS, 0, 0xD5084EE0, 0xFFFFFFE0) check("TLBI RPAOS", .TLBI_RPAOS, 0, 0xD5084EA0, 0xFFFFFFE0) - check("TLBI PAALL", .TLBI_PAALL, 0, 0xD508E89F, 0xFFFFFFFF) - check("TLBI PAALLOS", .TLBI_PAALLOS, 0, 0xD508E81F, 0xFFFFFFFF) + check("TLBI PAALL", .TLBI_PAALL, 0, 0xD50E879F, 0xFFFFFFFF) + check("TLBI PAALLOS", .TLBI_PAALLOS, 0, 0xD50E819F, 0xFFFFFFFF) check("AT S1E1A", .AT_S1E1A, 0, 0xD5079140, 0xFFFFFFE0) check("DC CIPAPA", .DC_CIPAPA, 0, 0xD50E7CE0, 0xFFFFFFE0) check("DC CIGDPAPA", .DC_CIGDPAPA, 0, 0xD50E7DE0, 0xFFFFFFE0)