From dd925287ad52814c1b08b6275ac00c85fecae2f2 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Wed, 26 Aug 2026 18:24:26 -0400 Subject: [PATCH] rexcode/arm64: fix the encode, decode and print bugs the mnemonic pass exposed Encoder * LSR/ASR by immediate used the generic IMM12 encoding, which writes bits 10-21 -- straight into the imms field the UBFM/SBFM base pattern already fills, so immr stayed 0 and every shift encoded as #0 (`asr x0,x1,#7` gave 9340fc20, not 9347fc20). They need immr alone, since imms is the constant 31/63 fixed in the form: new ENC_SHIFT_IMMR. * LDP/STP and friends borrowed the single-register addressing encodings, which put an UNSCALED 9-bit displacement at bits 20:12 and OR a pre/post marker into bits 11:10. The pair forms want a SCALED 7-bit value at 21:15, and bits 11:10 are part of Rt2 -- so `ldp x0,x1,[x2,#16]!` came back with Rt2=3. New OFFSET_PAIR_4/8/16 (the scale does not follow from the register type: LDPSW pairs X registers but loads words, STGP scales by 16), with the addressing mode read from bits[24:23] where the architecture keeps it. 26 forms retargeted. Decoder * Vector operands came back with size=4 always, so a decoded V register lost its arrangement and disassembly printed a bare `v0` that no assembler would take. Reconstruct it from the form's operand type. * Vd/Vn/Vm/Va hardcoded REG_V, but SVE forms use those same slots with Z_REG_* operands -- `add z0.d, z0.d, z0.d` decoded as a V register. Take the class from the operand type, as every other slot already does. Printer * V/Z registers now print their arrangement (`add v0.4s, v1.4s, v2.4s`, `add z0.d, ...`). Element views (op_v_elem_*) moved from 1/2/4/8 to odd codes 1/3/5/7, because an element-D view and an 8B arrangement were both size 8 and could not be told apart. * MOVZ/MOVN/MOVK print the hw index as `lsl #16`, omitted when zero. * BC_COND folds its condition into the mnemonic like B_COND already did, instead of printing it twice. Table (each bit pattern re-derived from llvm-mc) * BTI_J and BTI_C had each other's encodings. * FCMLA's mask left size bit 22 free, so .4s and .2d were indistinguishable and .2d decoded as .4s. * BFDOT carried the Q=0 pattern for its .4s/.8h form; PMULLB/PMULLT were missing the size field; TLBI PAALL/PAALLOS had the wrong CRm/op2. * RDSVL's imm6 sits at bits 10:5, not where IMM6 puts it: ENC_IMM6_LO. Nine test expectations that asserted the wrong values were corrected. specgen.lua Was already dead before the mnemonic work -- it wrote to encoding_table.odin and spliced a SPECGEN region, neither of which survived the merge into instruction_table.odin. Retargeted, taught the canonical names, and made it emit Form literals (Encoding + Clobber). It can no longer own whole `.MNEM = { ... }` blocks either, since ADD now holds integer, NEON and SVE forms together, so it MERGES: a form is added only when no (bits, mask) match exists, and existing rows are never rewritten -- their hand-maintained Clobber data has to survive a regeneration. Verified: all 11 rexcode suites match HEAD exactly (arm64 461/461); the three generator stages stay idempotent; a 73-case differential against llvm-mc is byte-exact for both encode and decode round-trip. Over the whole decode table, canonical-form disassembly re-assembled by llvm-mc goes from 594 byte-exact / 1818 unassemblable to 1737 / 678. Re-running specgen re-derives 1130 forms from llvm-mc and finds every one already present, which independently confirms those bit patterns. Still open: multi-vector register lists ({z0.b, z1.b}) and lane indices (v0.s[2]) are not modelled, so those forms print without them. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm64/decoder.odin | 93 +++++-- core/rexcode/isa/arm64/encoder.odin | 31 ++- core/rexcode/isa/arm64/encoding_types.odin | 20 ++ core/rexcode/isa/arm64/operands.odin | 15 +- core/rexcode/isa/arm64/printer.odin | 77 +++++- .../tablegen/generated/decode_tables.odin | 228 +++++++++--------- .../tablegen/generated/encode_tables.odin | 84 +++---- .../isa/arm64/tablegen/instruction_table.odin | 84 +++---- core/rexcode/isa/arm64/tablegen/specgen.lua | 198 ++++++++++++--- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 48720 -> 48720 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 48760 -> 48760 bytes .../isa/arm64/tests/pipeline_smoke.odin | 2 +- core/rexcode/isa/arm64/tests/smoke.odin | 22 +- 13 files changed, 582 insertions(+), 272 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 2fb303ab1..10c0eb37e 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -213,7 +213,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- NEON copy/permute index fields ------------------------------------ case .VN_VM_DUP: - return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .NEON_IDX5: // imm5 = index << (markerbit+1) | (1 << markerbit); marker = lowest set bit. imm5 := (word >> 16) & 0x1F @@ -246,7 +246,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .PN_PM_DUP, .PN_PG_PM_DUP: return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .ZD_ZM_DUP: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .SVE_EXT_IMM: v := ((word >> 16) & 0x1F) << 3 | ((word >> 10) & 0x7) return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} @@ -338,6 +338,35 @@ extract_operand_inline :: #force_inline proc "contextless" ( }, kind = .MEMORY, size = 4, } + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7 at 21:15, scaled by the transfer size. The + // addressing mode is bits[24:23] of the word (01 post, 11 pre, + // 10 signed offset / 00 no-allocate), not part of the encoding. + base_hw := u8((word >> 5) & 0x1F) + imm7 := i32((word >> 15) & 0x7F) + if imm7 & (1 << 6) != 0 { + imm7 |= ~i32(0x7F) + } + scale := i32(4) + if en == .OFFSET_PAIR_8 { + scale = 8 + } else if en == .OFFSET_PAIR_16 { + scale = 16 + } + mode := Address_Mode.OFFSET + switch (word >> 23) & 0x3 { + case 0b01: mode = .POST_INDEXED + case 0b11: mode = .PRE_INDEXED + } + return Operand{ + mem = Memory{ + base = Register(REG_X | u16(base_hw)), + index = NONE, + disp = imm7 * scale, + mode = mode, + }, + kind = .MEMORY, size = 4, + } case .OFFSET_REG, .OFFSET_EXT: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) @@ -406,18 +435,17 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64(value), kind = .IMMEDIATE, size = is_64 ? 8 : 4} // ---- NEON / SIMD register slots ---- + // The class comes from the operand TYPE, not from the encoding: SVE forms + // use these same Vd/Vn/Vm slots with Z_REG_* operands, so hardcoding + // REG_V here decoded `add z0.d, z0.d, z0.d` as a V register. case .VD: - hw := u16(word & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 0, ot) case .VN: - hw := u16((word >> 5) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 5, ot) case .VM: - hw := u16((word >> 16) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 16, ot) case .VA: - hw := u16((word >> 10) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 10, ot) // ---- NEON / SVE indexed/immediate fields ---- case .NEON_IMM8_FMOV: @@ -607,17 +635,24 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .ENC_LSL_IMM_X: imms := (word >> 10) & 0x3F return Operand{immediate = i64((63 - imms) & 0x3F), kind = .IMMEDIATE, size = 1} + case .ENC_IMM6_LO: + v := i32((word >> 5) & 0x3F) + if v & (1 << 5) != 0 { v |= ~i32(0x3F) } // sign-extend from bit 5 + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + case .ENC_SHIFT_IMMR: + // LSR/ASR immediate: the shift is immr verbatim (bits 21:16). + return Operand{immediate = i64((word >> 16) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_DUAL_RN_RM: // Take the Rn slot (9:5) as the source register. return Operand{reg = Register(REG_X | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} case .ENC_ROR_SHIFT: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: - return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM: - return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} } return {} } @@ -656,7 +691,37 @@ reg_from_field :: #force_inline proc "contextless" ( if (ot == .WSP_REG && hw == 31) || (ot == .XSP_REG && hw == 31) { return Operand{reg = Register(cls | 31), kind = .REGISTER, size = 4} } - return Operand{reg = Register(cls | hw), kind = .REGISTER, size = 4} + // Vector operands carry their arrangement / element view in `size`, using + // the same codes op_v_*/op_z_* produce (see operands.odin). Without this a + // decoded V register would come back as a bare `v0` with no `.4s`, so a + // disassembly could not be fed back to an assembler. + return Operand{reg = Register(cls | hw), kind = .REGISTER, size = reg_size_for_type(ot)} +} + +// The `size` marker an operand of this type carries: the NEON arrangement +// (multiples of 8), an element view (odd), or an SVE element width. 4 is the +// neutral "no vector shape" value used by every scalar class. +@(private="file", require_results) +reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .V_8B: return 8 + case .V_16B: return 16 + case .V_4H, .V_4H_FP16: return 24 + case .V_8H, .V_8H_FP16: return 32 + case .V_2S: return 40 + case .V_4S: return 48 + case .V_1D: return 56 + case .V_2D: return 64 + case .V_ELEM_B: return 1 + case .V_ELEM_H: return 3 + case .V_ELEM_S: return 5 + case .V_ELEM_D: return 7 + case .Z_REG_B: return 1 + case .Z_REG_H: return 2 + case .Z_REG_S: return 4 + case .Z_REG_D: return 8 + } + return 4 } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index b8de703d7..304311f25 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -231,14 +231,16 @@ operand_matches_inline :: #force_inline proc "contextless" ( // Element-indexed V views: element size carried in op.size (B=1,H=2,S=4, // D=8) so DUP/INS forms disambiguate. .S also accepts size 0 so a plain // op_reg (as the hand-written SM3TT forms pass) still matches the .S slot. + // Element-view sizes are odd (1/3/5/7) so they can never be confused with + // an arrangement, which is always a multiple of 8 (see op_v_elem_*). case .V_ELEM_B: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 1 case .V_ELEM_H: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 2 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 3 case .V_ELEM_S: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 4 || op.size == 0) + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 5 || op.size == 0) case .V_ELEM_D: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 8 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 7 // SVE Z registers. Element size carried in op.size: B=1, H=2, S=4, D=8. // op.size==0 (legacy / default-constructed) accepts any width. @@ -440,6 +442,19 @@ pack_operand_inline :: #force_inline proc( // Atomic addressing: [Xn] only -- no displacement, no shift. // Used by load/store exclusives, acquire/release, LSE atomics. return (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7, scaled by the transfer size, at bits 21:15. + // The pre/post marker is already in the form's bits, so nothing is + // ORed into bits 11:10 -- those belong to Rt2. + scale := i32(4) + if enc == .OFFSET_PAIR_8 { + scale = 8 + } else if enc == .OFFSET_PAIR_16 { + scale = 16 + } + base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + imm_bits := u32((i32(op.mem.disp) / scale) & 0x7F) + return base_bits | (imm_bits << 15) case .OFFSET_REG: // [Xn, Xm{, LSL #s}]: option=011, S = shift!=0. base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 @@ -777,6 +792,16 @@ pack_operand_inline :: #force_inline proc( immr := ((~imm + 1) & 0x3F) imms := (63 - imm) & 0x3F return (immr << 16) | (imms << 10) + case .ENC_IMM6_LO: + // Signed 6-bit at bits 10:5 (RDSVL); range -32..31. + return (u32(op.immediate) & 0x3F) << 5 + case .ENC_SHIFT_IMMR: + // LSR/ASR by immediate: immr = shift at bits 21:16. imms is the + // constant 31 / 63 already present in the form's bits, so unlike + // ENC_LSL_IMM_* there is nothing to compute for it. Mask to the + // register width so a W-form shift cannot spill into bit 21. + width := form.flags.is_64 ? u32(0x3F) : u32(0x1F) + return (u32(op.immediate) & width) << 16 case .ENC_DUAL_RN_RM: // Pack the register at both Rn (9:5) AND Rm (20:16) slots // (for ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm). diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 2b8c2775d..17816ae81 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -215,6 +215,13 @@ Operand_Encoding :: enum u8 { IMM6, // bits 10-15 (shift amount; SHAMT) IMM9, // bits 12-20 (signed 9-bit; LDUR/pre/post) IMM_HW, // bits 21-22 (MOVZ/MOVN/MOVK hw field; value is shift/16) + // LSR/ASR by immediate are UBFM/SBFM Rd, Rn, #shift, #(31|63): the shift + // goes to immr and imms is a constant already fixed in the form's bits, + // so unlike LSL (ENC_LSL_IMM_*) only one field is operand-driven. + ENC_SHIFT_IMMR, // bits 16-21 (immr; LSR/ASR immediate aliases) + // RDSVL / the RDVL family put their signed 6-bit immediate at bits 10:5, + // not where IMM6 (bits 15:10) writes it. + ENC_IMM6_LO, // bits 5-10 (signed 6-bit; RDSVL) IMM_SH12, // bit 22 (ADD/SUB imm: LSL #12 flag) SHIFT_TYPE, // bits 22-23 (LSL/LSR/ASR/ROR for shifted-register) EXT_OPT, // bits 13-15 (extend type for extended-register) @@ -232,6 +239,19 @@ Operand_Encoding :: enum u8 { OFFSET_BASE_PRE, // [Xn, #imm]! signed-9 pre-index OFFSET_BASE_POST, // [Xn], #imm signed-9 post-index OFFSET_BASE_A, // [Xn] no displacement (exclusives, acquire/release, LSE) + // LDP/STP family. Nothing like the single-register modes above: the + // displacement is a signed 7-bit value SCALED by the transfer size at + // bits 21:15 (single-register forms use an unscaled 9-bit at 20:12), and + // bits 11:10 are part of Rt2 here, so the pre/post markers the + // single-register encodings OR in would corrupt the second register. + // The scale cannot be read off the register type -- LDPSW pairs X + // registers but loads words (scale 4), STGP pairs X registers and scales + // by 16 -- so it is spelled out per encoding. The addressing mode lives + // in the form's bits[24:23] (01 post, 10 signed offset, 11 pre), which + // is where the decoder reads it back from. + OFFSET_PAIR_4, // [Xn{, #imm}] / [Xn, #imm]! / [Xn], #imm -- imm7 x 4 + OFFSET_PAIR_8, // imm7 x 8 + OFFSET_PAIR_16, // imm7 x 16 OFFSET_REG, // [Xn, Rm{, LSL #s}] register offset OFFSET_EXT, // [Xn, Wm, SXTW|UXTW|SXTX #s] diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 867da7559..0cb0f3c25 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -211,23 +211,28 @@ op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand { } // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides -// in op.size (1/2/4/8) so the matcher can disambiguate DUP/INS forms; the lane -// index is a separate immediate operand. +// in op.size so the matcher can disambiguate DUP/INS forms; the lane index is +// a separate immediate operand. +// +// The codes are ODD (1/3/5/7) on purpose: arrangement operands above use +// multiples of 8, so a size can never mean both. They used to be 1/2/4/8, +// which made an element-D view indistinguishable from an 8B arrangement -- +// the printer cannot tell `.d` from `.8b` if both are size 8. @(require_results) op_v_elem_b :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 1} } @(require_results) op_v_elem_h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 2} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 3} } @(require_results) op_v_elem_s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 5} } @(require_results) op_v_elem_d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 7} } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 1459b062b..ce2015007 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -115,21 +115,35 @@ sbprint :: proc( write_full_mnemonic(sb, inst, opts.uppercase) - // B.cond's condition is encoded into the mnemonic suffix (b.eq), - // so when printing we skip the first operand (it IS the cond). + // B.cond / BC.cond fold the condition into the mnemonic (b.eq), so the + // operand carrying it must not be printed a second time. start_slot := 0 - if inst.mnemonic == .B_COND && inst.operand_count >= 1 && inst.ops[0].kind == .COND { + if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && + inst.operand_count >= 1 && inst.ops[0].kind == .COND { start_slot = 1 } - if int(inst.operand_count) > start_slot { + // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), + // which assemblers write as `lsl #16` and omit entirely when it is zero. + mov_wide := inst.mnemonic == .MOVZ || inst.mnemonic == .MOVN || inst.mnemonic == .MOVK + end_slot := int(inst.operand_count) + if mov_wide && end_slot == 3 && inst.ops[2].kind == .IMMEDIATE && inst.ops[2].immediate == 0 { + end_slot = 2 + } + + if end_slot > start_slot { strings.write_byte(sb, ' ') - for slot in start_slot.. start_slot { strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } - write_operand(sb, &inst.ops[slot], &display, opts) + if mov_wide && slot == 2 { + strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") + write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) + } else { + write_operand(sb, &inst.ops[slot], &display, opts) + } } } strings.write_string(sb, opts.separator) @@ -335,6 +349,56 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { } } +// NEON arrangement (`.4s`), element view (`.d`) or SVE element width (`.s`) +// suffix. Vector operands carry the shape in op.size using the codes +// op_v_*/op_z_* produce and the decoder restores (see operands.odin); +// arrangements are multiples of 8, element views are odd, and the neutral 4 +// that every scalar class uses prints nothing. +// +// NOTE: an element-indexed operand still prints as `v0.s` -- the lane index +// rides in a separate immediate operand, so `v0.s[2]` needs the printer to +// fold that operand into this one, which it does not yet do. +@(private="file") +write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { + shape := "" + switch reg_class(r) { + case REG_V: + switch size { + case 8: shape = "8b" + case 16: shape = "16b" + case 24: shape = "4h" + case 32: shape = "8h" + case 40: shape = "2s" + case 48: shape = "4s" + case 56: shape = "1d" + case 64: shape = "2d" + case 1: shape = "b" + case 3: shape = "h" + case 5: shape = "s" + case 7: shape = "d" + } + case REG_Z: + switch size { + case 1: shape = "b" + case 2: shape = "h" + case 4: shape = "s" + case 8: shape = "d" + } + } + if shape == "" { + return + } + strings.write_byte(sb, '.') + for i in 0..= 'a' && c <= 'z' { + strings.write_byte(sb, c - 32) + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { if r == NONE { strings.write_string(sb, ""); return } @@ -402,6 +466,7 @@ write_operand :: proc( case .REGISTER: write_register(sb, op.reg, opts.uppercase) + write_vector_shape(sb, op.reg, op.size, opts.uppercase) case .IMMEDIATE: strings.write_byte(sb, '#') diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index c22a72863..0557a8304 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -44,12 +44,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, + { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, @@ -64,16 +64,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, @@ -107,16 +107,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, @@ -127,18 +127,18 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, @@ -149,37 +149,37 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, @@ -198,69 +198,69 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, @@ -272,24 +272,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, @@ -318,16 +318,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, @@ -370,8 +370,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, @@ -382,8 +382,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, @@ -449,12 +449,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, @@ -462,13 +462,13 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, @@ -477,24 +477,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, @@ -510,9 +510,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, @@ -638,26 +638,26 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, @@ -668,8 +668,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, @@ -758,12 +758,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, @@ -902,9 +902,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, @@ -912,14 +912,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {} }, @@ -931,17 +931,17 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {} }, @@ -952,12 +952,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {} }, { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {} }, @@ -975,20 +975,20 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {} }, - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, @@ -1119,8 +1119,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, @@ -1270,7 +1270,7 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, @@ -1706,14 +1706,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, @@ -1807,16 +1807,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, @@ -1844,10 +1844,10 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, @@ -1895,11 +1895,11 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 330bd68e0..c16426c73 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -141,8 +141,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ASR { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -150,8 +150,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ROR { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -361,29 +361,29 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, // .LDAR { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, @@ -893,11 +893,11 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .LDURSW { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, // .LDXP { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, @@ -1186,7 +1186,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .STZ2G { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, // .LDGM { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, // .STGM @@ -1291,7 +1291,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, // .BFMMLA { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, // .BFMLALB @@ -2836,7 +2836,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .SMSTOP { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, // .ADDHA { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, // .ADDVA @@ -2875,10 +2875,10 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, // .FCADD { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, @@ -2924,9 +2924,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .PMUL { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, // .BFCVTNT { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, // .LDRAA @@ -3025,9 +3025,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .TSB_CSYNC { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, // .BTI_J - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_C - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP @@ -3057,9 +3057,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .DC_CIGDPAPA { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true} }, // .TLBI_PAALL - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, // .AMX_LDY diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index ec9f178f9..fb287288e 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -254,8 +254,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ASR = { {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -264,8 +264,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ROR = { {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -519,31 +519,31 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, @@ -1132,12 +1132,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, @@ -1546,7 +1546,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, @@ -1697,7 +1697,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3540,7 +3540,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, }, .ADDHA = { {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, @@ -3596,10 +3596,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3665,10 +3665,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .BFCVTNT = { {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3809,10 +3809,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_JC = { {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, @@ -3856,10 +3856,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, diff --git a/core/rexcode/isa/arm64/tablegen/specgen.lua b/core/rexcode/isa/arm64/tablegen/specgen.lua index 5dbd1d4cf..13197ba8a 100644 --- a/core/rexcode/isa/arm64/tablegen/specgen.lua +++ b/core/rexcode/isa/arm64/tablegen/specgen.lua @@ -7,9 +7,16 @@ -- the differing bits are operand-driven, so mask = ~(bits0 ^ bits31). Per-form -- assembly makes it robust: an arrangement llvm-mc rejects is reported, skipped. -- --- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin --- in place; the hand-written core is untouched. Every bit pattern is therefore --- reproducible and llvm-mc-backed. +-- Output is MERGED into instruction_table.odin: a generated form is inserted +-- into its mnemonic's block only if no form with the same (mnemonic, bits, +-- mask) is there already. Existing rows are never rewritten -- their Clobber +-- data is hand-maintained and must not be clobbered (pun intended) by a +-- regeneration. So this is an "add the forms that are missing" tool, which is +-- what it is actually for. Every bit pattern is llvm-mc-backed. +-- +-- Merging (rather than owning a whole region) is required because a Mnemonic +-- is now an ASSEMBLER mnemonic: ADD holds the integer, NEON and SVE forms in +-- one block, so specgen cannot own `.ADD = { ... }` outright. -- -- Two spec kinds: -- * uniform — every operand shares one arrangement T (iterate ALL_ARR). @@ -21,7 +28,7 @@ local bit = require("bit") local LLVM = "llvm-mc --assemble --arch=aarch64 --mattr=+fullfp16 --show-encoding" local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." -local TABLE = DIR .. "/encoding_table.odin" +local TABLE = DIR .. "/instruction_table.odin" local ARR = { ["8B"]={vt="V_8B",asm="8b"}, ["16B"]={vt="V_16B",asm="16b"}, @@ -53,6 +60,78 @@ local function padded(tokens, n) return "{" .. table.concat(t, ", ") .. "}" end +-- The Mnemonic enum holds assembler mnemonics, so the ISA-namespace prefixes +-- and per-encoding suffixes these specs were written against are gone. +local CANON_PRE = {"SVE2_", "SVE_", "SME2_", "SME_"} +local CANON_SUF = { + "_GATHER_S","_GATHER_D","_SCATTER_S","_SCATTER_D","_FROM_TILE","_TILE_FROM", + "_UNPRED","_BITMASK","_SCALAR","_ALIAS","_PRED","_TILE","_LANE", + "_IDX","_GEN","_LIT","_IMM","_VEC","_PRE","_POST","_REG", + "_4H","_8H","_4S","_2D","_1D","_2S","_8B","_16B", + "_II","_IR","_RI","_RR","_X2","_X4","_SR","_ER","_ZA", + "_Z","_P","_V","_H","_S","_D","_B","_3","_4", +} +local CANON_KEEP = { B_COND=true, BC_COND=true } +local CANON_RENAME = { LSLV="LSL", LSRV="LSR", ASRV="ASR", RORV="ROR" } +local function canon(name) + if CANON_KEEP[name] then return name end + for _, k in ipairs({"DC_","IC_","AT_","TLBI_","BTI_","PSB_","TSB_"}) do + if name:sub(1, #k) == k then return name end + end + local c = CANON_RENAME[name] or name + for _, pre in ipairs(CANON_PRE) do + if c:sub(1, #pre) == pre then c = c:sub(#pre + 1); break end + end + local changed = true + while changed do + changed = false + for _, suf in ipairs(CANON_SUF) do + if #c > #suf and c:sub(-#suf) == suf then + local stem = c:sub(1, #c - #suf) + if #stem > 0 and stem:sub(-1) ~= "_" then c = stem; changed = true; break end + end + end + end + return (#c > 0) and c or name +end + +-- A Form is an Encoding plus a Clobber. For the data-processing shapes this +-- tool emits, slot 0 is the destination and every later register-ish slot is a +-- source (a destination repeated in a later slot -- SVE destructive forms -- +-- is therefore correctly counted as a read too). +local REG_SLOT = { + VD=true, VN=true, VM=true, VA=true, RD=true, RN=true, RM=true, RA=true, + PD=true, PN=true, PM=true, PG=true, PG4=true, PM3=true, RT=true, RT2=true, +} +-- The table aligns the operand tuple at a fixed column; keep generated rows +-- looking like the hand-written ones around them. +local function mnem_field(name) + local s = "{{." .. name .. "," + return s .. string.rep(" ", math.max(1, 28 - #s)) +end + +-- The table also aligns the Clobber at a fixed column. Applied once at merge +-- time so every row formatter stays a plain string.format. +-- The table is not uniformly aligned (166..176 across sections); 169 is the +-- dominant column, so new rows land in the majority style. +local CLOBBER_COL = 169 +local function align_row(row) + local head, tail = row:match("^(.-%}%},) (%{.*)$") + if not head then return row end + return head .. string.rep(" ", math.max(1, CLOBBER_COL - #head)) .. tail +end + +local function clobber_of(enc_str) + local slots = {} + for tok in enc_str:gmatch("%.([%w_]+)") do slots[#slots+1] = tok end + local reads = {} + for i = 2, #slots do + if REG_SLOT[slots[i]] then reads[#reads+1] = tostring(i - 1) end + end + if #reads == 0 then return "{written={0}}" end + return string.format("{written={0}, read={%s}}", table.concat(reads, ", ")) +end + local sections, skips, n_forms, n_mnem = {}, {}, 0, 0 -- Emit one mnemonic's block from a list of arrangement tuples (operand order). @@ -72,8 +151,8 @@ local function emit(mnem, llvm, enc_str, feature, variants) for i, t in ipairs(tup) do ops[i] = "."..tok_vt(t) end local f = feature for _, tk in ipairs(tup) do if ARR[tk] and ARR[tk].feat then f = ARR[tk].feat end end - rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", - mnem, padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + rows[#rows+1] = string.format("\t\t%s%s, %s, 0x%s, 0x%s, .%s, {}}, %s},", + mnem_field(canon(mnem)), padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f, clobber_of(enc_str)) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..table.concat(tup, "/") @@ -81,7 +160,7 @@ local function emit(mnem, llvm, enc_str, feature, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- Compare-against-zero: a 2-register shape whose asm carries a literal #0 @@ -97,8 +176,8 @@ local function emit_cmp0(mnem, llvm, fp, arr) local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) local f = ARR[a].feat or "NEON" rows[#rows+1] = string.format( - "\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - mnem, ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + "\t\t{{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + canon(mnem), ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a @@ -106,7 +185,7 @@ local function emit_cmp0(mnem, llvm, fp, arr) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- ---- Uniform shapes (all operands share one arrangement) ------------------- @@ -311,7 +390,7 @@ local function emit_shift(mnem, llvm, dir, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end local SAME_SH = {} for _, a in ipairs({"8B","16B","4H","8H","2S","4S","2D"}) do SAME_SH[#SAME_SH+1] = {a, a} end @@ -366,12 +445,12 @@ local ELEM = { do local blk = {} local function emit_rows(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end local function mkrow(mnem, ops, enc, b0, variants) n_forms = n_forms + 1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .NEON, {}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper()) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .NEON, {}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper(), clobber_of(enc)) end -- MOV Vd.T, Vn.T (= ORR Vd,Vn,Vn): the single source feeds both Vn and Vm. @@ -467,7 +546,7 @@ end do local blk = {} local function block(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end -- scalar FP two-register (FRINTx, FRECPX): Sd, Sn. for _, it in ipairs({ @@ -479,8 +558,8 @@ do local function mk(r) return string.format("%s %s%d, %s%d", it[2], sc[1], r, sc[1], r) end local b0, b31 = word(mk(0)), word(mk(31)) if b0 and b31 then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) n_forms = n_forms + 1 end end @@ -499,8 +578,8 @@ do local bD = word(mk(gp[3], fp[1].."0")) -- Rd field (zero reg) local bN = word(mk(gp[1].."0", fp[1].."31")) -- Rn field if b0 and bD and bN then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) n_forms = n_forms + 1 end end @@ -526,12 +605,12 @@ do local function mk(r,v) return string.format("%s v%d.%s, #%s", llvm, r, ARR[a].asm, tostring(v)) end local b0, bR, bI = word(mk(0,"0")), word(mk(31,"0")), word(mk(0,vmax)) if b0 and bR and bI then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}},", - mnem, ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) + rows[#rows+1] = string.format("\t\t%s{.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}}, {written={0}}},", + mnem_field(canon(mnem)), ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a end end - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end imm8_block("MOVI", "movi", {"8B","16B","4H","8H","2S","4S","2D"}) imm8_block("MVNI", "mvni", {"4H","8H","2S","4S"}) @@ -565,12 +644,12 @@ do local w=sve_word(build(v)); if not w then skips[#skips+1]=mnem..":v"..i; return nil end; vs[#vs+1]=w end n_forms=n_forms+1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .SVE, {%s}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .SVE, {%s}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags, clobber_of(enc)) end local function block(mnem, rows) local r={}; for _,x in ipairs(rows) do if x then r[#r+1]=x end end - if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(r,"\n")); n_mnem=n_mnem+1 end + if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(r,"\n")); n_mnem=n_mnem+1 end end local function g(v, x) if v==0 then return x and "x0" or "w0" else return x and "xzr" or "wzr" end end @@ -690,17 +769,68 @@ do sections[#sections+1] = "\t// SVE predicated / compare / predicate-logical / SVE2.\n" .. table.concat(blk, "\n") end --- ---- splice into the SoT --------------------------------------------------- -local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" +-- ---- merge into the SoT ---------------------------------------------------- +-- +-- Every generated block is `\t.MNEM = {\n\n\t},`. Take it apart, and add +-- each row to that mnemonic's existing block ONLY when no form with the same +-- (mnemonic, bits, mask) is present. Existing rows are left byte-for-byte +-- alone so hand-maintained Clobber data survives a regeneration. local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() -local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", (region:gsub("%%", "%%%%"))) -if n ~= 1 then - io.stderr:write("FATAL: expected exactly one SPECGEN:BEGIN..END region, found "..n.."\n") - os.exit(1) -end -local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close() -io.write(string.format("specgen: wrote %d mnemonics / %d forms into %s\n", n_mnem, n_forms, TABLE)) +local generated = {} -- ordered list of {mnem=, rows={}} +local by_mnem = {} +for _, sec in ipairs(sections) do + for mnem, body in sec:gmatch("\t%.([%w_]+) = {\n(.-)\n\t},") do + local g = by_mnem[mnem] + if not g then + g = {mnem = mnem, rows = {}} + by_mnem[mnem] = g + generated[#generated+1] = g + end + for row in body:gmatch("[^\n]+") do g.rows[#g.rows+1] = row end + end +end + +local added, present, created = 0, 0, 0 +for _, g in ipairs(generated) do + local head = "\t." .. g.mnem .. " = {\n" + local s, e = src:find(head, 1, true) + local fresh = {} + for _, row in ipairs(g.rows) do + -- (bits, mask) uniquely identify a form within one mnemonic's run. + local bits, mask = row:match("(0x%x+), (0x%x+)") + local dup = false + if s and bits then + local _, blk_end = src:find("\n\t},", e, true) + local block = src:sub(e, blk_end or #src) + dup = block:find(bits .. ", " .. mask, 1, true) ~= nil + end + if dup then present = present + 1 else fresh[#fresh+1] = align_row(row) end + end + if #fresh > 0 then + if s then + -- insert BEFORE the block terminator; splitting inside "\n\t}," would + -- leave its comma stranded after the appended rows. + local term = src:find("\n\t},", e, true) + src = src:sub(1, term - 1) .. "\n" .. table.concat(fresh, "\n") .. src:sub(term) + else + src = src:gsub("\n}%s*$", "\n" .. head .. table.concat(fresh, "\n") .. "\n\t},\n}\n", 1) + created = created + 1 + end + added = added + #fresh + end +end + +local wh = assert(io.open(TABLE, "w")); wh:write(src); wh:close() + +io.write(string.format("specgen: %d forms generated across %d mnemonics\n", n_forms, n_mnem)) +io.write(string.format(" already present: %d added: %d new mnemonic blocks: %d\n", present, added, created)) +io.write(" -> " .. TABLE .. "\n") +if added > 0 then + io.write(" NOTE: added rows carry a derived Clobber (dest = slot 0, later\n") + io.write(" register slots = reads). Review it for anything that also\n") + io.write(" touches NZCV/FPSR/memory before committing.\n") +end if #skips > 0 then io.write(" skipped "..#skips.." invalid arrangement(s)\n") end diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 3c031af32e49af8fdac57442cc1e2e5e34f2833c..0d8f5415c43875fc41b054ff11958565ecf7da08 100644 GIT binary patch literal 48720 zcmZQ%U}m;rU}E85U|?VnWMF9c&%nUQz`_C-n+O&YU}RuqWMyDtVF#(>W?)bNt7Bqf zgNb#6#RNd+u|vfaxEUB8fYq_EaKOa6!D0f83<3fI3>unR3=Ay_ehhye{AXfdWDpV( zf{G=;#Y99zpkfQ)Vq#)qP_YMaF@Ao2sF(sD%sfFsL8w>)TufM47%H{^E+#803lU>b zU;*jnWng5GlaqsrCBVhx<>jGb3*cf33JOrM2M{pHl4J`%+1{Q_~5B`JA zQ<9T|h&jN;T;PJ}>i(h6$ z{IbB}mze<`zbvr$WoCfKFAFSwnUUg`5fVoX%nWky_;rMfA>y|YE{2HTgAg$R7UcLX z1cxaH3v&E^1dB1rCAoFE_GVvcUFo za3j0r6Ws0Ai1Rh;uZ#8WVd*M?PcIacFQTSm;f)bTY?~N;YD@} zG!5}0xkUk*FL{yNA_;X1FTyQOu(0Pta*F~q9q=K!MFE-)_>k;?)gOFFc1T0*;Dg&C z0FPgOWILeo%a3daG=BM!^uppz09h|I-UN{KLgP&U$$hYTO906{SlA09n+FYhL1gow zVK2nM$jAt(R}~IOfyzk+1|bF}CQ#kL&cL8>U=~90nmodDRdM7lW5q z4U^$w@chwm86qYCve%A*i6tGB--01=4zkylfr%x9fq}u{GFVJN7~wt@nEQkg?o)xe zPZ-I4f)G0xgpu4A2p2=RZz5a_;l7IyF|fTL_wh0?)G!1y`~j5*AbUaX<7Hs@<8T=) zCLn@vp9ai*A_(_sz}zQ-20sE{1U51&A2fUby>&!ERvy*$a2y zWU!ckD8hX@F!zZf+@}L`A4r`Y15;)es2mptm+cH7b+%Bk1CzmG0%8dBIAG?9A}(7S4AKk@pthp~$UG*f*le(vfFwd)15BMHLR|v`RGkz96C)#3uL4v|8X?vI6O%!R zF)VO@4~VsLe`O0o%$IA^8`s4#~f8bx8h&t3&t~R40S{tBB;^ z2#7xz6p{Qp11^T}?+u8UfD*#L3^4yHA^gh#^RE)ZzY(x_Q$qMRA^{p7$_Vo~VCE?! z%;SNXr_3NL3yn()3sz8A@iHhg$jQOPD&S)B@-VR-a4`i1nAi`9n1C{aq9Ox>hbO2? zF<}+>_y0dHg9^eeEHJmIAl$+NbBhYXZxW#X;Q#+j3@Qk}Nr2jaATd>hUJjUERfJv+ zSh`n5=;Z*lUm$wn>3{Ttl$I<{*r-4w%&=3XI%b-|ChZX}96I|>USWH5Tfzi$>gvCr$n1KUH9YPGMP8-=gE3jS;ZDjLyfyE@W zkLzo9urvvhbEfWhn7Xw3sFt`q2&;j`aDt2HpSWG~d0n`If2DM5U7(^Ht82&IY z>LH6wfr#ldFo8SfAcgYRhs{xXjJygsPNh}^N2GRw>2bklp{r~^}KLe`~Lx=|h zgNO=9lp#cbf#E*`lQ9FM2Ll5$M9hQ%D#nBm+X5C7GC@{n3KnBBVL(#16)YxX%D`mj z$-u0x3bMqEfq|i(fyoS6%p4+S&cNu+z`!gCQs%G|+zw+fXJA5z{RE2%m?PUO0k#9A z4&lBCuoy_44+8_UGy?+zkHZddx&o;~i2VSIfz3U2>@Q4=7cO=HZk}u)1A|5|sC;Q? zg^bgfGbjc!FnEB(7#dmyz+*S&40eGG4E|s-hKHcE#?N4Z6wVCLaJE1SX9j3ETQD%f z!-@gwUke5%gc#Jn77UE=utHLY5JRYghm``tJcJlr9U}Y~p#HT$3O@#D_*pO@!jAzO zeijUf@MD06p9KRV{2JiqA%)*lNcdSGhu>33_*o!@p8_=eERn*`!4ecl3=Eb?VdY=} zPFEl?co-mw!Tp;6RcD1{9s|@oDM0O#$bo+UxZ$`c?%$70`|z}LGlMk451E^b_E<57#Y18 zm|5jOnNSlFE)EP#Odv6Nkl0GF7+9STRNVn2bs#a2x&uh+d|~P|zQ;co z1RNN+xj}Y-?bQW|F)=tW@bG}dKCv9Fg420CkHalA9TzZULzS zxesJV1ClzB7|4zWBy}M7fz?6X3^ETS237}kvm=t58K7=gGe$xge>V4^`)ir0zZkSTBPclGuExm^+f#eGiB_4?Zw9CsRGl}%ygxAWyb}&Gcfpp`5?j`F6Iy7f^j@tEC9?05%qAfKoA#<=flNw>ZfL*OK|v0b zh8P**8F+YLVhM0DZW{&$CJRuXSV8WA{Dc2sb#So+xEL2)>;YJeogtoq5oQO28p1qS zADclPF2)42mmzH)*ewF_3_P%YH$ysHjEf8Az6W5vAUlL@7#K8k7#JA7Fz_?{`SG8L zA)Y}5A?6Pg6GMpQ!^Fg4Vt*idLFP#y#K3yl84?g-bpRGt35c*d01K-G2DtkUz}%O> z0PpMm0L`m``bP;2@V@R3(D*Y%OiT>g&-(!y1BHl*i^IfzfcwcHw@669#lZb!keHm3 z9JFsA1L^BBBp~&P=fK4fed0S1F@Z#c-y9UdVamvmi13?3B3umaH;0E{F?NPTWWPbj zEfSIa2JI&&G9dX4E{5bcuwIaPNPYvW1BoI077KARLn4yj=EB7ge!B}16G%e%?EuVg zNeI6kfcY&6Dc)dyOG5J7La_Uo7?P0uwh-(-kQl;m58+}6zx@R3WoJlYK=|z^SRF_V z;Wyt@NINkJ$#1=IF@)dFLc|1;8MwK*A!BYDpfm}}m&pt~JUmb_P@05@adB}$#XxED z!GCs!WCr+L?-kG(0BDXmnE^g$cm*^D01<=F8D4?S8zdv<2N@hvLG=eOLo#B1kf8xC z2A>~fH~4nYpHZ;J+;NyP{2OwesDG2{s!2Fwn@UI2TzbOoG z|60KOn}XzDP#y&NEd|NHpgaf>L--ez2O(nc`EC}Ne^U_tWr6uO1!+DM=HC<~|2jha z!H@!qU&!2cLnB-a;opN0F@aQse>q_OO-1;Z1LogUgnv0;{!K;r_YP>B2IP-agn#dV z#%Um8aR1%`jmbd7;Qr-+`8O5eUk;dmQxX2E(flIl#rZxVX3= zVh6xt>i{xfpqfXiZtSOQ!ORL?-f9)QKzIdb88 z1>kyf;d%uWV0v@G~p*@kAa4IZ$7cks%M{W~f*KT#Sp03o7;iEXK}| z57G-MJ3V0Wn-9_p6@$fZKFGgNFiafp~eA;NDNFuxTd{FVXpTOq=488E*UBK&p)7H@?Jza4?aTOq=4M_}<*i0~T= zEZzzceq(Wf`mGSjZ!QowGZZ5EtpzTI@Y@lHm_QN2Zxt}V6(Rgq0rOiC!fzEYzZD_* z4Hj=jNPdIGTM?4qVDVOjsJeshJmnV|^DZ>?}Kgx`)r!~}{Ncwqg7 z14`gFCL=>J12?R1;E)6t&2s_~YfE$Y7wmcI<38FoDLlNAT2Z_Pk zlQ$CKV(|9ljY_ayc7_r}d-6slSRFe8fm@<%0H4B?NT zV7(wako*A-QznLTWPgCe6eNb^54aeTKfroH<{|k5td5Vz@&qi;R4~B(b^?}X zDiC?*1T4=~BKb`f>}E!WN(M%_-%=4`aQ8h0i?K6QG9dh>3U)I{FCzV=BE%4S!D1l2 zNPYu{JrhGEvfsdA4-$jN+lfTD7?R(>dO_yF%w? zyAM=X{Qu9+P=(|-1+bezdJ%q0K!_pqg2h03;eJ~Ii?=F--&VlltqKuuD`4?fg^0Hm zuz0IN#M=s3yj3Il4c51>M)Di1Z(q%T$TP6MeKnHb6v1w0WT-|;lZgm1xZfUv#n>6D z5#`?sSov3t>^Eo}RU`WiE(VXc6_wC zKzb2rQUmN}kX}T*Wgx^5dck5Ky@+^&m5DV-euI^XHAsGgm5DV-@dhgsYmoc~D-&yx z{H6(ZGb2MSQoLm%#Nh6G2^M2#s6~o5O|Y9mdJ%rhM2I2ug2h03k^BY@dnSfjWWRyK z9wY|OZ!2KqIkm`s1M3Bu2hVRSVB`^dk8U9QI5M^~ipM##=qI z-{4~K{I&y@-|CV523E(;&;agVg4caHz{aT?!2L^zSQ^+Lj0_Fn{v|~08CVRY7w*0e zSb5NZa9@Wa*bXL!288=MVC8rNBJ4Y0?rT7}uLD+&H-OsI(D7YRe*v`KrvcQahKhmu z3lK5HI3cLN09v!%i16D1*m!#*!fyxC!Tw-mXhit!z;mz|J3}L)teXKF18qe3Z3b)% zv=QOA8L&Lli16DC*cfOd!f!KRd8QG`Z=il2$RCYJegpOMAYur=f%h2~azrpfM6O!Lxd8P@;Z?HVmgyc6^o@qkz8!XQ>A^8n79tQG9 z6O!LR<6#gngx^5pVIaRXBl!*1=4wXr8?4RMjN~_1o2wb&w+@)!nh}2MfcdQ%;kOQ$ z-wx*K8R54MnBSU_{017!1^J^H$#0;sT!xGl(Utq8w4!17xw!fy_+{ML%_n*%JrwIcjB16G!_BK$T3R+h9P{5Attmb4=L zHUn0cv?BaA16G!_BKZw8W(4v_E0W(pV@41$gx^48Mj*enA^dg#mfzYCemelmZ*2&_ z9f0MxHYC5n;;jwIZ?Jf4L-HFe-rA7-28*{gB)`GptqsX<&Z*!%D-3N&ertw{A^dh2 zA|}wz!05`r0NN@e&%jV5585lk(aykx5c?$0(D0u@qMd<}m4N{?#wgFgkR=b=?*~%H z1{Zq;7L(|J%#}-lrd?s{zB(Ad>&+ly(Dg_ikab27u|1&iNhXF4$T}m4*dLe}c%2bg z?0^kKtP{x&*xIO0Bs&N`ka1b^Pp>I`jONffQT_nKvoA`J2Mfy{s6jm z2D)x!B6OVxXx)edblu1#By|i>b(4_PF+kN#hN=TC>ZtEvXaKDjm<&}17CQkJ6PN;8 zkLk_C%qq*kpwIyt(`R6q!obMH1QR;}7896?Fs}h--c*En4fRm-rXkF0fSET9VP1m* z)V%4CZ~-}`CY}Q{C&$1r18fI${RUKQCPLjGn7UaAb$=M3>SiO<)x>*1%$tKySHl1m zn~PBQ2c~WwLfs#jy7>ro2lnp(&F`}@%!kAq$jt}#{{V{#EI?Lg0TyFeh%8nC5nBYd z!^PE&fq_9`2grS_42!_w2NnAP786*Eq;3IJ-C`tl3!v(jAgN1$s#}7jE&-};DU!Me zP<2a@)IETzTZT|40CV3mggOBQsJi7y>R|3$j-(Fez7l3l}PGf?pukZ z4(7g92z3fD_pL&xQ-HZ|HIh1*`&J{VgSl@Fk~*0C)*z{axo<6!I+**`BB_J9ZyiFN z0nB~t5b6wI?pu$f4(7h~Na|qj+km7F=DrO`>R|5Mh@=kYzKuxgVD8(5Q0D-1-zJ1Q z2blXdBdLSAZ!?lQnESRMse`$13z9mR`?eyfgSl@jk~*0CwjtC7z}&YDp)LUCzU@fr zVD8(Fqz>l39Z2e6?%RQ+4(7g{Na|qj+lizO=DuABbqO%{?Lw$afVposk~*0Cb|a~S zxo;1WI+*+RAgP17Z!eNMnEUo3se`$1A3|LL%zgV1>Iz`)+mECU=Dz(%>R|3WfTRxQ zz5__=VD3AJqz>l3gGlON?mL7~*8p?hA%waHnEMVRse`%iFp@f$`;H)~gSqbrk~*0C zjv}dpx$h{FI+**8A=K3@0I&aJWjKaVSF-@T{*P7QIFh;tP<6+V)IETzJAqL52WH+0 zgt|X4^G+hEgPC^{Ngd3*QwVi63&3?AE5m6du?JAGGYGLiFm-2<#9->qA;fAHfa^w9 zhVw{b51?Wf5MqB|>MkOQ!PH$sh}9@S-Es-xj~WGtc>1@l3~eYn^=1|}xZIScFz z3pINT&$l#TrmF64-@+W z4to|*Lg0|U4r=Rhv3^B}@xa8sf$art)0F3c>{H@m{f-dhfr^pPS)7 z0}Bgu|G5ApOnC$t7+F|s9hg`^GuI6h84euy&m+KyEOrqh#>B`3(<=hg%go5c0*xaE zm>3JP*e*~Tm`8#Yw2Yg98QiB!xC!bv@(8dY#5fe7V(ds_3!q{gNMbO(oJe91pz63l zT^t5xR?uDm2Jm`$9szEMI#Bzb0j7=zNepHOFOnF{Eqsjd{re7({nIQA{0K1@n3w=U z%mXGS$jHbD4QC%nxUdKaA=CxH)CnWRLSSMd2(bv5m?*-$7?^otjEKFy8sNEJW(F}v z_#V#(O0J-^%f}#&P!|DHCyr3}1g1^`p)LcaPJ$5>bQ++P^+3TDR3`EW`_bJFE7*%2belVgjfJfObMY^1EyCQVMhW?oeCo_FZ4X4hJ)DV zT3}*ojPN;|h6Cpy{#9p$ul4JIsncK-5D*a1(A3gqU|={0>WecoXfP@$C@5%XXlXK7 zK+nJt&_q(F09B`nqz-y6j(`@zjvkmD+8{Ao4NWc3p3HNg^97h0v>9b(WkWSIG@Tht zKz1nn=VQ=jl#`Rg5R;de#}HFcP(T$E&_RUN0hqnI2(cqDF+Gr&2*ke*P=Dw%iik)< z){!+hoMSli;6F2i0Ya<=CT55b>wt+FA;fxMV#bKLY=MQn3CLcE9VcLJF=Z5jokR5i zvaX7m!IV)g+!q1 z?=v9dm>dkY$YS8~fP=vfl!hRFn*;F&6N4Qi{2Z@2ur*_Lh_IRiTYqK8h&U$;cCLmU zBYdqNLjYubJA)k~;_QS8a54D0DhAlO8upCvGr*=m!k&r29^t+zF!$Lr!p{Yp0y`JX z9^vLGFgM#X!q<;afvqF6NBCn3%pVTO_JYHdiNOKcUT~O##E|TTtAmHt6xdo_2V{HU z>fmM5lm$@p92w!~GwcAZ2L|n>a72`yJ3#A!A!6`->N{Zj)Eyb&`_y-U?1iX<&++Ym zozLKiNcTHH_CnOb%b^_)p!0r?ptyvlNpWZ#IfCL6Di#hGlZU6>>2NW`IQ4ain1Cbb zxH$$Ub_RwA%naTSm_g^wIWjV_F~G!5gT(}#ki!7HMu~~R2{{bF=@cY}6b5j0NMQh1 zhZF{Ib?`c12Pn=#Vc>))i+6zXDntx%j)NG)9}G@NVGsrvLxjOJxELY~u0g~EoDu1Y z1(u$j5$TErmY$sv>6rzVo}CftnFW@foe}AZ1(u$j5$Tx)B*{WsJ*A?Mk z6_|fr5&l(y`PUWUUlo{t-H`2t`oj&`UZ{WFknM%5gZozn=3h5td*SNf{#Akb*BxQ6 z2+Y6k2zy0f{&h##D+2ScJHo#rF#ozE>=l9e*B#+s5tx5HknM%K&jZ?S-p@ z`&R_!Uk_w^;p*W26@mHJ6Jak8%)g!pdwF2~^+edq1M{yZ!oNH)|9T?q<$?Lv6X9PT zn14M%Z52oz#RJN#ptR-*YO6rR1VC*S(3vZqptcHB4BGZ#@MMIa2`B(N6VMaXMuMt? zoeAiL>^Eo_cp>`@8m3;zeuJxnhba#%Oudl(23H3UQyy5DdLjD_Zig)FJWCOn-@Fih z6M^~73*k2rnBTk*eiMQD%^Tr29ay}1BmAZVi#KnC-*jN{=8cFq9ay}1BmAZVi#KmX zyy?K=%^Tr29ay}1BjQa0<~MJI-y~pu^G5hh0_Hbwgx@4!e)B>08#J7Kko^V?Qy*l% z!PUXzO$QclKFEH9tAodz4lLe$ko^X?10HWOFu(aA{3ZkQn-9WoGBCgSAp9l+^P4Zi zZz-^N^F{bA1r~3<2*0Jk;>{NkZz-^N^F{bA1r~3EItB|{J{-z3qt^sKfK{$2!C|L#Ss2D4G|LvMEIiw z79W8Kf0V%DBM{+_5?Fi$BI2V279W8Kf0V%DBM=cEC9wDiMDhm@#4QYgNdEAFiy{2c z0~bU1;|xShAPCtX(C`aF_6IaRf{^_IR|k)e5?Fi$A^QWa4jvyRu=of<@&_-(Eet_O z{_us1A^gz`7en~tEJREo7~zi^SbPK{{80mok6?s9YGCmZjEIjKSbPK{{80mok6=W6 z)WG5+1leAwe?yS%g@#`Uvb}J1@bIgFgNB#@T-A^Uns)fJuv@Nm>?nk*5`L&;a=tA_h9K3_Sj)0rD?IOblkP2FSl4u?S>)p=)a+knM%`VIvrk?1igC zvKOun$zHfRBzvLiA`$jx!2BDDur~wd-$;bL88H7wGQ#c6fcZC)5pHh=%)gP0aC1;@83enhv5F zxnc2ZQ21rb%Lva4D`5VJWrXL26)=CqA=?3UUmUU>P`AV(+W}XHWCvUw zk{wX7cqBVuc{(1+4p^R!N3sK!r{j_Q0n5|zNdAE3=>%jupzcdRwgc*x1Y|ql>Ja`Y zgsVgNVq zj6w*#a4`{tUZ_|(!rla!z2yjd6JYk1BkWCp*;|3IHvu$H0&;T&!rlZ}8CJmvw>JUi z-%5nN4zT#GMA+*9i{DCwy$-PWtwPxA0E^!$guM>1_^m?N>i~=2YJ|NBFng;J_9npW ztwz|J0JFCSVQ&J=-Wr6x2{3zW5cVd(?5$(Hbi}N0G6)Wk?n<+P3_3`!o}eA(E(Wg?Lf8{ zS{`&D+Y1+i*GC6n`L`2cZv)J~od|myVE*ky__qP(-!6o`4KV+9A?$5{`L_$<-v*d} zyOHgM`mGz;UbqKzOe;Z)_?M2wT0OsFbguM%3{_REhcLB`5 zeF%FO!2H{Xuy+B>zkLY*E`a&BAK6~0-};g5g^R)cy8!0j3CQ+B{WbyFUbq^V=kZc^6>*n1t}h1(-i3Bg~rsGjB4&ya_P#rXb9l05fk2!n_GE z^QI!q+W<3fD#E-CF!QD%%-aAnZyLh94KVYjBiiFzVCGFn^aHlQ^iD^#$G5=jn2zWN zY=N0K1KB)i9L+#B4;uC}kj;augSYRuz~W;jqcChu%#;T3`WH@ynT#T^^)FKzz~=>V zGR#6&2R08RhNKQ`FDJungt|E}^JXK=n*%d%4#IC|U}<*_V(jY-EL`S5$1FjY(Ir66 z=wX-xU2_5wTL2e>j9G%j9zetd=78pB>@_sC!WbA7QW*X$_|FT{D=+V;p{W(lz_1_% zw8jP`rl6nz5{qD9cmNR-n2Y2-SlG`+avyALZZ5)o3NZK0MYvA^=DxX%aQ7*|+&35D zJ{Fk!=7Q#rKyC?VV1c=BE@=J;Bo@KI0(0LyMEu@?l^gRAZoUHx(|HIt-+_hcJVtTY z*sml|lZUVNvv(=N-V-o;mm%qe*}Du$FU;O$NP1!RE@y z6D~)r_qhSvue+QPe(u5z*nZvRjPUa^Zou~Iu0XZ}+J;+!YzH)~Rv_B}7elfGte2f( z1+pDrb?gi)5ozNOEU&Iaq>VqYyt)#RHvYi!>Pke~uz}^(m58)q1Iw!`L1hV~A1?tr zGjk=VEP;x_&dgj1DodbZuro7PA-NA$_pCy4AFTXah2%b1`L_zmeXujxRw20$b|%{@ zg!^P*?puX$pA5`>s}Sy!fw^xrcr7t_ug8yt;I+hz467O8=S2T_2p0pL+Xzwj6D-Eg zuo_f8L)W?aK-Xig29?iHu^zY>VvW}sh?u|{M7Ugml^bgi;c^95ZmdCs%N1C;u?7(? zBCv8}4I*4bVCBYIMiE&4t$_5S*csL`ioxz;s(|&Q)-j5}@^l5H&&1BK4l%z_0qZlZ zXB3C^{W4(Ytw;1pGGOLyV3a_p1NZ6J88#sL9~m(7HX`c zz|#0;L|8q6rSZ*(uzCVZ%k>fi1}H1J_4P3|o-h2d*nXV(@joPhfGm1=)RIz3dEIklhE?3lf97 z&jIGXEsToFQ1>~&+y@eay3YaTzO6{^gVi5fk=zHXKei%;AFTe^isU|6{jn9veX#mt zD?I!J;O+y7LEI+*cOOU$;ywYm`?evKlOXqj=I*v3m6IU%LB!zePj7(S2N6S*lRv;| zh@D{@QaSkpoQ6PRipp{f9^RS^0t$ht0uMlEKx_krA5?52l9&Qi>>@-=U^~KnFF<7& z$lmP;_q_m>VGuF6`(A*`Fo+o3eJ@~VoNq_C@5K*j{@4x*Kd`+FaQA`4;T0PL=2wB-+A_i|0>cG;_P9!^EX=oQ>&Y=h9=3R*XM-R-+yAbyF!0g?H@LLbe z-rb0K4I5awu^VBB4XoVQjp+B-!1__U5%$`^%97oPFt7oo1CZZ#Biv#GN(T@zco^7# z(g8?p55is(n7w-tZZ?6b+l#CYocEa+_9Cl;itR)88@SwHV%Ue!YXb|veaL=;tAo$k z*ucVcAF|)z>fn7k8(28+L%78T7S8(-Yq4j5(jO?@??t55N=rkigSn8}Um7LeE>M7Tu2;^+_}jv`=j zbO^LH4Z7A|LF>VP(4BRM7@0ul!h+Z2E35*G2^>cFLk1KdAUlpAiGkt+Bz6=@3>3c* zG5DS&8_0S`K7nJ5{QRK|8kzv00%mJ|-? zT^}b9Zb=c)hlIfigj-Ss@?m0dx1=cOL&D$$!YwHZ`7klKTT&eIA>ncok)A_f>G>og zenVjC`6Qyu34x{OlZf&(1eTspBFdZ)Sb9E*C{IIR>G>q0%n5;|=TpdTftFXNklg|; zCr=@}1+EUBw?bfP@)WXL;OgLcD+HFtPa(SnYR74492qh&u)xyGX=ogQ#h~fsG&GJt zVzBgb8X8AnF=%=@4NWf~F<5#z4UHqP7&N_{hNc&g7%aVmKMYu%-mXFRN+#&)CmvhK&friUDWVb-W=tM_c?H=m&@%A~vRmNl;N`9h ztlYhV>=w8>c)9BWD|fFTy9H{;RcIW6+YHb+x(baWuoyIsu0rDoBnGP+uR`MpEC!9E ztI#+CiNWf|tI#+Ci$UY)Dm0EjVz9dL8q_U@3=A%?diomFEnqRITdqOf0uqC{s2 zU@@p$u0h=b5`($r8q_UdF{oRvLEQopgSq88qY$huwFH)rt}}|j+D%JfdFDE!7_5!7 z1eQN;FbcuiTuWg2?FOR=tbMfvmbY#&iox1aOJMovCbGTI__&E|FEoGLM79^27j7Zj z3k|DV$o4|R|cl&eC!MCUy#@x#QIpUe<5P< zwXk6SLd4+fUcvqaiQPrES0A)5pNZivvb}IIBzvJ^_mJ()hv>bBSo^yK)LsMGaSt&L zw*=HS1Bu;d`vhU{6qvnF5cW=i+4}@x?-ZE5Pm%3~rst=~_CnM1Q)GLg z>G>J5z0mah4B1|2dVYp%FEl+rN7y?D=HKTCd*{IX`y65K9GHJ!Anct3^Y06Uy>npx zeSxrd4$QwVk?n>0_a(BuQ2)L}wioK(SIG84{rd{pUZ{UxA=?Y}?`wp;EwHllHNxH& zSULF`VQ&kpOnif|w*}T0dV{dH1(c6KeZ)5ids{&H2-FXKi?Fu`X75{sy*)5{-y-bo zf!X^GVQ&x2-ggLldtmmyL)hB`v-dqCzhoGLhNdwC0}CS`!=H!$nHb(P3LwP%U}Az& zFm+6P41XSj)d?ZQ{9t0j(lB)_d<=h{gVl*3#Qb1lVlpsw9DWRc-hwbULV24@Da4% ziowPkbd|6IE94%52T%!AB9GB7~H?=wg*M9ct`u0a0% zjF>Yt0HrI47<|vS0VrKT#NhWl8i3N(ga5n&Ul8^R!0i2kuvY+P?-zu!6eI@UcboumA1}jKM7Sit!sRPsE;RubE?*IIsR^)f`O2uMsL0^q>BYd{puj5d z4-|gi5dN)z`S%;bzZEe5ena@T0_NXu2>({V{QC{jU#Nij_Zy<`QUUYtH$;D-0_NXu zi1`S%;bzbP>Pena>-1?Jyx2>+(Q{QC{zUl*8vza#uB0rT&7gnuPq{{4>duLR7$ z-x2>J2g1J*F#rBQ_%{OP-yaD7M!@|01L5BYn16pD{2KxD?+=83BVhjhf$(nx z%)dVn{>_2;_XoniIWYhJK=?NY=HDL(|K`B_`vc)$ADDlCBK)fX^Y2fDe>GtK{fY3e z2F$-d5&qSH`S&NnzZx+A{zUj!1LohK2>)up{QDE(-vXF_e7fcf_q!oL|X|NcVwHv{J1UkLwZ!2J6Q;ol6He}5tTn*sChFNA+HVE+Au z@NWjpzrPUvErI#>7s9_KF#rBS__qY+-(Lv-mcab`3*p}on16pm>SRzm0zOaj8&W4j z#K7~(Obovvb*QB$1A`N+4*i4B%K;jv0kvuVAoOy8#%Um8@VO@r&^Qf53_kb70UD=) zh{5NcI6&0-f5QD3O-<{5aPzS#|orM9e4t{s~69#DCg%Q~f zXkUnt3CRw)IwU*b>X7V!s$*gj@Md7p03CW*;NZjX0TgdcOhPcR5(giKFAy;im{^5_ z55o_Lm>5i~#=!^FE@on2Vv-E=X3($)8R)>v@ZkS`keC!m%t4lc!NGx-;R!@c8YJc@ z%fQg!z{~IkA|?Y8bCP9XXmQ|W_yZDSM!2s5W(PBp9SKl7n3)iEBtY$8W7x%01an0g!@_;pyAApa9;z=4t69v6rgsnBiW$_~Pf zK<(f_*x>-Pg9BlQ0?Z#A2s;vB{@_5^u>j@|4ul;`VE*7l*uem^gA>UPm_Im??11@$ z6Uh#kKRA)>fcb+9VaEXnUr65KMiNVait!-C9>CP`B8kD&@i8IJHe`mBlMH-Jh_ely z;bMrhF`D6GkagUkPR?P7m;gV_JWYlM5f;duFZ?j`G#MH~;9^koG#MJEz{Q~EX)-ii zfrtqRAejd`uMe~iN&v|`(0P3jF@$-b^ZFoS2=hSa^?~lp5kxXi6k-R1Ad-2Za502= zQ{iF=^R7a~1caF2_p|fB)^Z9l!TV)Au(g~*Oz?gg4{R-`Fp|Bn`*DPs5cb0E#}Q^i z*n1ed9#aHKFKjKR2$EjdT22upy|A^MqENk>S_}@bb^4-Ey&y5zI(<>7UXU1UoxT`C zZvsrO7(#CXOs^P1ZvsrOIFq8XqN0b7r|l;Xf~jEL@BME+z*T69AhBQYQ}*gN`%6%u`@e)MjAt2xMSj zcp#xF@CTHx6p_RvAz~a#Oo|K)3?88KfuBgIe)tbkrwsB3gNLUF1H*v`Re^sXF%^W^ z5lN_+DwCoTXnezyLBK&kRp1avof?wZ1gMxg)P0@|3=RPhF%AtRu?tW!O^_HkoEZ*) z!tcX>UIs0=m;hW%8z$z#;2;6f%bVL3*^_divWo5x@O&2hzfX96}Kw{8!stX*D#31V|85T4ki9yy`GAuX%5tA^0n;OOF;8HD1CkiTJb?ubNMaE41Qr~Ch)Ed2&0}bQnFkVsn8(lnGY=#NF^{1E zW*$fkVje>S%seBwc>-|rKw=Q{1mNa@#31Ggz|8}RLCh0?n`aC)PfHWwK9Cs5Jdha7 zeIPNAc_1;E`#@qK^FU%S_nE-WL%0tl1~CueK9Cs1JcRo|Vi5BX?lXm&r>P~t01H2m z7|1-37|eYjF_3v6F_`;6Vj%NCVlela!OdfUn+Fnun8&~XGY=#NF^_=(W*$fkVjcqn z%sg|bd0LtX_kqMf=7Gdu=7GdO=7Gdu=7GdO=7Gdu=2^haL%0tl1~CueK9Cs1JcRo| zVi5BX?z3cqt%(+Zuh|BPf%Ix>2_(SQM1#aYdO>2aHPKdZy$lCn>#0Fv5WNfsV0uAf z5WNfsV0x{Y5aZM;kg;Y4YbL}vbqZVzF;2Y%E`}JVegY8_uwjx_VubD)&|rns@it6y zaIp-ym^@r;1zb!)i3zIr1w>51mPuX(dQNo1LWmfHEt7(Z0z_TILx`Aw9h0nb0E32i z5NI5D3AlV=uw#-}4r0*o4gra^FgyV5YqMigK!_ayiwW2<=_m&<#DVlOFgy@oc<`T} z!H&s7Ie;M>BDMfz9!ShmIe;M#B-X$H6|-lOgWJ0RYOg(#y$w)%?UC$lfZA)%q^lgj z5Dzks!2xQoJ;GiEgdK2u7r?|EnB?L1IxGdbkCy=?2KR3(*l!FDNcJ)u1&awdFzG1= zFeHHOZGhVAfUwsAVF%pa128d1CIz^?4Bz$kizr;#0~~0M3^!#K*Q7t;Wq{bXqY-9g$n~zFGvjPJ_cBPI3wwW z#fJ-$-x?rsDF70K>4k-#E0e4uJgq%}guN@1ydqRx1H%(=I5W61DWHo9xH9P|!qS=o zBwQF=nJg4xX-xr|u3VWc6=7)&Cg#Q@2e)?t)Lu6vdmEtkx*^#M6%%k{(p7||wFIcW zZU}o75O%=rT>ukvXOf58>+lrfUyvBwzfU3lbw{$70U{>g&ZMUZOKS_D_PQhNbwJnw zxAy={%!5e*Ztnqzy#gRHn7s{9J3N^56=7-Z0mKdg4}={FQ1b*l5MlZNCgzDKHxd{i zan9g{NPh{iJnfB0R|&BE=7UHt39!82%cRJ}#NYwCbW%V;Rp5`pe?AF6xR?N3%pV~p z0#g?N7h`~n1;WJyBw*@-;9?ALv0#Ll3`|`JTucBi7Rm&lCn;cX0j-baV+cj`Qwkj5 zV(@-SK?7V2-cKnw01*=iLzq_rGcOEbUJ1;+Fhswn1ZG|sqTf>jGcO#W?gE1=#C_oi zbr&2UVgeBebyr~OA`t4Xz|=(|)Lm$R=w*mRsJn0gA|?=pPLT}f!YEfu>`1CEL@!cTpdUZqE4UzrY??2URhpV1GInZ zzyeoLe&b_^V^UC7P=JU%fQSjiBiyn;0pbsa1bExK-W_tk5I;jALd*>&mc+zl%fP_I z$H2f4v7ZGrHpefJ%%rZQByZ>KtI5DH;eZUo|Ns09DM(@yp<<~_pqa~9a0{Q~0KN4SC0t^jMu`H07EL7bBh`KB$4J9SH z7_c1&AYua9aCHI<4G=MgY`8iB2AH}WxH<-g1q&hO<-pZ3Fg$>W3FN}n3Bc9m!qo}D z)#bs}F)%bh^fKfli7kM-rGUvmIe;MvQV%|av@Hsm3>0Bv51?X2OtMNk3>w~X3=9lR z2O#b%V$xBPWrzcfaWgPL#fq5(1qDHS+>;rOIOu`y1Yu$*W)cz-f{Eq9#6(0ypkfVh zF)=YQsMrChSP9I$6ow}bdJJzC{AXe)ftd#q%Y%tQ%}Zf;(f}8OnwP@xWOh9m~6e?em9NMa1Fpft|QP=O@Y02Ql5l+OoX<#QFHd_DlJrx~gd zu*N!v`kT3@V2d!1vzRK+ezR6KFvagPfnuC(w!{201^QPoND^Mx;Q@ z<6~%NQjnL2%-d(c%C!!JSPo3AlL_gLmJ~=^zKaQbFR~;90|Se~4+fqE|G5OZn3#MR z7?`CQ7#Mh9V%nn!#vs59HE$wZOaU%7i7CW`fk8xtfkA+QAw+6KE|7NL`J?Ww1JdX$W;P48mYBhUo|~8<^M( zWWAHY>I7yofi@~Jf#RHjK?;;!7#LKJAttGfjj6PSant_m#1F$Y=QFR+-zT!=p)YiFXsd!`uXf}984Tg7k-EG94y zSzQ%ajAI_Mx?f;1iTO;7-VD%t&Kzcf?m1&%m=8%W;JeQpz;~4~2rNKS#{gBg07)GK zRNX=(bq%hrkNxSgD2EjlD83972dS!o&{4^)d)3fQt720s=?iVhV7v zqi`_?xY#kcSOQ$^I9#j&E_MPgwg4`65-xTCE_Mno_5dz+8ZO2l2y@>VxR?T5>?~Z& z0WNk9E|vfnI}aCYfQwy#i!FeQU4)ArfQwy%i#>pgU51M>2*KQU1s=`{LJFW}@qYn^ zt8g&~xY#wg-UPVb>u|9KxY!N2*aEoNO}N+rxY#YY*aNuOZ6^2~mMjdi3^ot`GYH&4 z5_5ox-9-{>fQsEi5@V2r=)I35<^UCYfF#xc6?@3U0;{)J4nV~oA;er@VviAGEikbs zaDOP2!ScsbxR?W6>={C=3a0KkLaYuZ_5v=ZP{Iw(GcOThRWPwv2(fCI*lUDX9Zc*E zJTB!6IiPv#EkdjmCiV`Yw-l!LJzR{T0_MICa4`kA*hjdS16=GATr2@D_8Bh5P{9NB z+ZVW)0$l7XT#TUtRz`e-iz&dxzQe^D;Cg?+#TLNDe!|5Lz{P&S#U8-Lej~!A9TqNs z5Ms?RvA=M=3hl6P`G*i|hKc=$i#fp6F))J+1hpL<;OZFRVhM0{Ob9W!I%c@o0=POB zgcw{MD_raWTpb%i46cqHp za2uUNfSH8@F7_HM22y7Q+Fs1SAkV;1D9_LUHjf1%_7N;5A&6|RHrNghL1cSZgT*8S gk?qw6+rc4-Z0~BY7)Tw$4nwdVAaw|_jbJee0LJd>TmS$7 literal 48720 zcmZQ%U}m;rU}E85U|?VnWMF9c&%nUQz`_C-n+O&YU}RuqWMyDtVF#(>W?)bNt7Bqf zgNb#6#RNd+u|vfaxEUB8fYq_EaKOa6!D0f83<3fI49Y613=Ay_ehhye{AXfdWDpV( zf{G=;#Y99zpkfQ)Vq#)qP_YMaF@Ao2sF(sD%sfFsL8w>)TufM47%H{^E+#803lU>b zU;*jnWng5GlaqsrCBVhx<>jGb3*cf33JOrM2M{pT;PJ}>i(h6$ z{IbB}mze<`zbvr$WoCfKFAFSwnUUg`5fVoX%nWky_;rMfA>y|YE{2HTgAg$R7UcLX z1cxaH3v&E^1dBWs0Ai1Rh;uZ#8WVd*M?PcIacFQTSm;f)bTY?~N;YD@} zG!5}0xkUk*FL{yNA_;X1FTyQOu(0Pta*F~q9q=K!MFE-)_>k;?)gOFFc1T0*;Dg&C z0FPgOWILeo%a3daG=BM!^uppz09h|I-UN{KLgP&U$$hYTO906{SlA09n+FYhL1gow zVK2nM$jAt(R}~IOfyzk+1|bF}CQ#kL&cL8>U=~90nmodDRdM7lW5q z4U^$w@chwm86qYCve%A*i6se?--01=4zkylfr%xVfq}u{GFVJN7~wt@nEQkg?o)xe zPZ-I4f)G0xgpu4A2p2=RZz5a_;l7IyF|fTL_i->V)G!1y`~j5*AbUaX<6vO;<8T=) zCLn@vp9ai*A_(_sz}zQ-20sE{1U51&A2fUby>&!ERvy*$a2y zWU!ckD8hX@F!zZf+@}L`A4r`Y15-*Ws2mptm+cH7b+%Bk1CzmG0%8dBIAG?9A}(7S4AKk@pthp~$UG*f*le(vfFwd)15BMHLR|v`RGkz96C)#3uL4v|8X?vI6O%!R zF)Vme_&4i07C@Db2 zZbHNa6cPRvf%#Vv;a`yhQ2#0-`%$IA^8`s4&h%= zoec7?B9eb2ApT%bMDp(pxER8}Hy~mHN(lcl!2GL(@Gk?*ze))IM!@1t3E|%eSiC7C z%;SKWr;IR<2WFl!gRCqxE-frrL1D$qpv)jA2NSD+i^=#%}LW_aX&MAb&P*{+G14$i14605W**q(-UJh+! z^LBy7B(#yuL#RWT2UVv7@`o)G3p*DBLxV854q(s$`2#9;U@}-tK$pRtfq_8|)GA?M z5Mf|o_`|@chb%S)BBsy41n!uF6v|(d2bF)U21sJ|P%%R!v3R%`NEZknV2;1`|NsC0 z46H^BAs!42Lh>L{h7bV;hW`vq#te)e3=GT=F%t%;7!yKl3s_9Z1X-OaSd7Vp0ZH9f zu$Yi31CyO61GAC>$PzOK28MbDCNpF)bBLHZ1EV(s1G6|tnZr(SJB-1cfe9h@6D%fR zj%=?4*bb07g!>}EVjy)s3=GVY3=9lB4m-f<3ZxDp_5&;iQs>LSz$^s{SR{1_F@!ol z1_ovs1_lO>1cZ4AF}ONTgqv+aZf0aKXW&AJ)xyNM5n_8`Vmt`3zc4XgxYz->d9r~F z49b3>@};2_GEQU8pcu%&;0zLDXlNAxkKLFv*ab2$c!9+j9)i*uKZ6BQI5R-Q*#aq? z8KB{8!N3R)D+Z{4Ef|;(Vo?8DFfhWy3P~M8451DlRtgC75Mpq3i11^8`qu&}{1~9& zXTg97KL%*{Suh~Nj{zEf77U2+Yk-@F6n;-3;b(yyeorCcXMq%c3efPgL<&C#OHdp! zFjyjmm4gL1U4g{lVSpqC_iqAJofVRK3{dl|kj!I1sDqn_BnCH60jka#DJ~lz<_TCM z*>M0O#$e6B2-o`np%*T;03s$}gQVA?65?MQB=TZiln#)@;N~Sj)!8DM#{f0Y z7RfvYggS(O5n^!j6rf^u$o_?xCt!zU#{q~KgB`Me5qja~Er5s#*dv<<$sZswggQvt z6>wl+Wb|fWW(5^N4w{f~abRF#f{U#Li-FboFfg-%3Zer@>fmBX>UJR z1Eewm3EIQO{6SnWj)#i{fcYSz9xfIL;)3yfxL6RF4BuN!VEG|0IDvG z!GVE+L5zWc;l2U$)&F4g!r@}`;bIYRvHftdNCs;L&?qlxc8TGNJZN5sF$ylm!~heE zhKn)7#bV%M3=9fTy|GAQ4p6Z;kYmC40rPxl+bo`en;Y7%bx@E4r6ER!cm^IGm{}5!s z2X>16?I&0-J3|r!!f!vp>Of)$zxk#@+KEX> ze(QycA^dh0A|{Z`z|GAK8FSMBrAbh}OlIKW;em>Q(j-KTi;D{?21=6;{?~$l#C)sy}!ck`eQR3=MEG`1~Nl0f?AD zGHC1uGS}PS0PzP%FKn*2p#d%iAOCAO01*>NLHO4K=HC>Ae=T7CO<{oh*8=9>6eRzG z@*v1>DMwb_b&&`zo`iSa=`qXitsN7%)hBf{&j-*gCP~kzfEv4gnth~#01h1{*{3FHx1!m z37CJ=5dM{b`8N&W-#;+_rXl?M2j<^22DpF!!2Fwr`M(AyT z>CHy67p6A{To!|u$tWnu$^UuqpOGU6Toyyb65wK>dIlo)04&DNkqg%=0N0xf*DIg^ z)0+z}$3c1p6kvMuKyHSNC-NxBf%=k+40#|oL&Xx{Vq9EYP_YMKF?NQ0kX}gH=>d!1 ze2`wK7%YDCLH>n`!QwX`ktV;u%Gi8Fn*0JQWAhPd@(Zkt&1Vo77l*8!F>wH|#R0iR zLP7#22433(5`(X;XmEq%BZhpWwA%(3L*%z(5HW!Qgx?}yek(xuEdu7Z0)*cpV16q= z@*Au?EkN=ctUN71@*Au?EkN?y0jS>!7!ZCt0QFk|QoeMDxS62<$#3m&F@)caL&O9M z5q`^n`K=J)w+xuy3K4$GfcdQu;kP5Ocq>Hs?FcO13K4!g0*kjogx^?T@m7fN8;b+f zZ-q#HbAh;-p%BS$EpRb}-;O}U1d0%TtAP2f2;sL1nBR&Jeyf1_tq93)uy`v%@*6DP zije#Ui?<>qzro_I2+41-cq>Bkn=8c43`IzOYlVv;{B{%~CQ!`41M4pwPy)9x85xQh zxM6(*ha|Wd7hIh(Sd5*an1KtX?m#kJj2qrxcmx;Yfr%Y}iIp&L!}}yKdrKI2;9@X) zOBlG}eG(;TpQHq-pOOR@ev}dk^BJ(7ehceX7rAYorhKnKm@faF@rHFR% z4MlLA8;`we}MIZ+zf9Q->3wuV`nHs>Ni?|?PUas!Qz*p0xre` zO9u=VP&bz`Ao`LOa4|+$oHP6Y>jl{XkB=P-!C}h8P=@fwj)mYb1&P7^vEw0J4DOE| zKf!uI=E423<0n`hJ3~2=KPjl|?ev}-ko=|rPHT)HF?gEHK#0NJ_W~>i(u+uw8elhr z^djOd10jac3l;~#MLGl}{OsqkQH&~figXA|@nOKYDH%+jc85wGk z;w=*)26x{}uoyc-EmFK`g53<#i||_}LJXl7EC$kx19<1F)MxdJ%prK!_pq zg2h03;eOiz%WriEzwLnKw>m_;?SSRCI)vYL!17xiBHnhu@>@NU-weTSW@M;G@>?N7 z4DP;;klsvqiHUzsFq!;10LWCGXFIWtu7s+qnuxDbZNA?>u-s+M41{Z_pw;izj zR*&pAusU{z25|opyza{ZHcs6D?q5R0(!l;;WM}~QFCk*jz+xc1aQAh<%7X@k`#KcC zb}%tCAl%mhE5{oUVc!9BUjxE@9k6n|0o103j_-o{3!wEr4WKqPR1DN#fQTW+2|@h@ z(3pWL5kvS5)XxL?tqI{b2Uy+Rgz%dKtnO|? z_{{-UcQ+yV4VGt`ko*SAGfhZ-gXNhfB)`G(OcRpdV0oqq$#0j8?26MLGl}{j%q>j8?26MLGl}D+!o}I79_uc#%&>D2)}{GZ9#r( zMflADmfu+W}a9YeV?$04%??A^8m! zZ*53^gT-4LlHXwQ)`sLaSiH3%`3)9tZAgA|P6h8-VQ540TQgh?;kUyOF@bglMpp&~ z&{i3F28JSe&|Vpib_OPd*e7|=9zcn921Zr}2GAIzJOe|PJZQfkNF5to>=jr{q60El zE&-Z$g{}MQU;wW-gNQ-bBXvO589~JMfW{}87&;*9j38ovU}E5PMqsf6HW0B+Bs*Yh zqdJl7V1U}uiDU-@)Q(OhI~bsLbVAlLf$eC3+R=q%2W*{DHv;N*#9-@l`jO3puAS*eQg;9%#xMa{9dzx?MDY3p=-L_Rx{-;<>pYs5-FN39y*J6wrE1Zzg6|X$A&`4$zoB z1H%*sMkXeh*a@(hz*K~J4KVYjBFt;3hnhDHVO|5wylDvY8Wf=BO^1XF$SF1P9H2Ql z28J16JD}?~pkgx->i)pg%|fXA!vIw`8=SWI96vN{W}7{fwju?mRTBCs9y4vq{A3<^6y?qg+G z1P(u_*blInz+xnI3!v&2BdJ>eRks95T>@0y5+rpAP<2a@)IETzTZ*La0aV>GggOD3 z`<5Zp2`E6-Ek{xZbKi0#bujm>KvD;D-wGskF!!xQQU`P2N+fkK_pL&xQ-HZ|6+)c? z%zdko)WO`h8c7|@eQS`^!Q8h7Ngd36YmwB!+_x4<9n5{}5b6wI?pudYX8?2GdL(r) z_pL`#2Xo&BBy}+NZ9q~7bKgcJbujmBL{bNH-zJ1Q2blXdA=Ej*+_xD?9n5{3k<`K5 zw*^TZ%zays)WO`h6-gb;eOr;#!Q8hEp)LUCzHJC~0WkM%M^XoK-*zN*F!$|1QU`P2 z4kUFj_w7Vd2Xo&}By}+N?Lw$afVpoMLR|vPeY=s=!Q8hSNgd36dyv$@+_wiw9n5`u zk<`K5w--qr%zgV1>Iz`)+lNqB0CV4dBy}+N?MG4vbKe0ZbujlGKvD;D-$5jGF!voq zQU`P2A%waHnEMVP)HT4|cNj?>%zcNE)WO_$1W6steMgYg!Q6KgNgd36N0HRQ+;p66tOCc8)IETzJC3C80aV=ygt|X4^G+bt{ehWx5=kA*ypu@k zVCJ1dsH<53uJc$KP9upufQp?#i2Z@7JBuU+Q+Ey_Rn>t4ASo`d-yq8={x0>lO5{cy3DU_OZW4;Om{ z;)1cfBFwzkU_OY5hl{-dalv>#T<2TFfkTnv0b1xFpmT) zXc;#HGq_Kea1+#Td9HA}( zrcNB8?g>nt1VUW~Oq~RyECU0BGALy|P;dp6iF^!_2z3=Ob&?2mPhje#7(r{h!TXar zG~z&RVP=qK|i=~YJ9kpNSt!pO@DJ-*hj0y@03d+i=Dhw9TGjIenk<=+b)oCKB zgPw~cpoOrb2WE#hNX%AQMHRFs^Bm}W0cHkmMp;?eP-SHmI|dVw9SZ;X7_=GXran z!C(hULlD2sf%t=o!HyArj@KO6nlU>>Sj~a0zp`UQoRbARSHq4GzSfT+0J6TF!HyAe zcESX>7<^q71MFN4dq(&fU{fGr&%|JlaNiV|`|KIv=YmavoeO4&K_S z){)sG{4oXQ4+ms>!C}h8;DBr|I7~reNcO_j!NY0_Y^|;Xvb}J1@Um$N=$r)58fHgE z`1uSwKfm#HJ7DKCI3m*h4v@VN zb?|a%#{=lRpCc$Pp=nYa8b^+xxP*#@!^Py`X?HqY3^7i99U>;+2s&<#fr*`g;Q=#) z_XB3od2^18Ol%A=vD08N0Vm`z0IyMEVsJtZ18_P8i6MmnTpdyvz||pz0bCut4%h*T zb5IyKAM0#d{rDtbEx?+K)XJ(>DdL@Ubs4VdS(Ho zD~NgUe8d7uR}e9HdS(HoE0CBg!d?}ae_avws=)l~im+D&=3iHYe^p@qbw&7B1?FE@ zgnw0F{&hpP7wQi;WP73hbwjont`6>B6_|hBknM%5gZozn=3jS&y&^FGx+Clrf%(@R zVXp|xzwQYCiopEqj<8n*=3jS&e??&a^+2{4>OK!-d!hdIK(-gI4(?wOn14Nx?S-p@ z`&R_!Ur&U+JTU)yBJAaX`PUO+FAvPWo(TW)!2Iipu$KqsUr&U8d0_ta1hrKlbrcUM zuY%H=C#bCg5fcElRX}I1c!Jt0P%&uRhryE(ekPy*>`XvUP#X!V4t6G>7qZ`=Vc>=A zH)xo8A^Q!k4j!gFurT#P_8VLsJWP3DVd{nKH@F?}^A1H|e)B^3O$6pQFNEJjV1DyL z_)P@nH*bXBbYSu3jqsZeEZ)2ke$#=)n>QlfbYSu3jqsZeEZ)2k@umZdH*bXBbYSu3 zjfgi1nBTk+ev^Rt%^Tr237Fr!5q^_^`OOE}Z_se|LG~LoOns3323H42LG~Nm4tTuD!2ITe@S6KV*Nv)xqN^1r|qs$o_zEeruj{_uv2A^gz|7en~tG(=1w5aEv!SbPK`{80jnk3fV! zN?`F3h=`98SbPK`{80jnk3d9xl)&O65Xm1r5VtS{BKgAyE{5<&4_pl4k24T4fgogm zK*KKx*&opO2txJ;Tpc_X7V(t3$FE zsxA^?ZwAc2kqCP;VE&Cn*qZ_KZzLn!-VB(3BN^fLX2AR#$q2VM1Lof-WP73Ri$b;+ z>b@vsd*SMk?1igCvKOun$zG_sXhtqr{8|`5(?&ES7c71)44~;CnvolphAax;>bPO? zYf%7K#{-K?iw#h*7-T!3Zizv*1L~F-WIN#MknDh~L$U)Z7K_LWD`5VJMdXDQFn`1% z^1=$3KVli-d0_?2AF+(^ys!f1k2qvIpze!9wgc*xIAlBE>X7V!t3$E_Di)7q2P{v= zBiRAV)A2}l!18oFl0RU1Iv&X%usofBYzNeR3CMOp-I9Q82V5P(ABAvr2!CvZiX|e- z$t9qC1nR#fBFf1npnL=ogO9H*0p%lz7`%L50?J1aG5C1I5>P&Zh{4O}C7^r+5=%n1 z7g~-dA=?YB7m^U=^Agbb8bmLWy>N9%_QK6WvKOi@8DZ}ln17QI_O5~XHyL5?8km2R z5%t0vn17QI^}-sMf0GgQ!Wx)=Q;_Y2x-SLUUa0$0knM%5gZp<4tR753wim7r?%y@A zdN36+X3hZfZz`h*?Cu5znBP(v#b9?gFu?qgh8Ra@fQ3sMVmzAx76xgIVz7H87-0TQ zN46L0zI0@J;bKVkLd7zW?S+O*2C}_yF(iATVwnhg6=43&MA)kU^KT}?zX~w_W+CiV zfcZBIVXp$rzgYKzOe-&Wyo69I9 z1ihO>0OsFZMiCL{-5dfi|K>7^i9zq?5PbKvb|7$lpxy+7lZrP z02aTcjQp^~(;}ZxzB`2Uz@8A?$U4#cwsj-UOJv)d+hNVD?rc>`j2#TZ6DS z0cLLv!rla!y)_7X6JYk%GV;UPW*V@4Hnog`u(p{-BD4)x%P0&x+e-s7XUN1*$0&f% z3vI*IA?6V^VEb|E7)20zq3Y@p_IkkVtw-4F0kgLrVXp_w-Ufud9g3 z?Dc@{&1gin7ur^7M79?$2KTQAY~NTDvc1suOB1raa51=lJz)FGni2MD!1l#7Bka{k zgxcGT@UI5U-WG(t8nFE{EeLxxVEboU5dPJG+1rY!7Y@MERV$)iH~>pmt%&;Q04!a# zA?k$#uyoais22{v(p4LxJ~{wPSMA95Ld&LhWP9Oa@cQTgEdO>O+Y2oZI*{#!i^1!o z1F-ztiLkc;=HE_)y$vw`b|U=S0P}Ab!rlg$f4dO&Ho*Mbh460!%)i~p_Co#EjchMm z4DR0sn16ea?S=ZS2iab@7~H=NF#q-<>|Fr!Z!f~$1u*~iBK*4m=HEVqy$fLe?L*kR z0OsF5gnt*n{M(OgFVt`S$o9g;;Qn0z^X~*?d!c@tfNU>Z4DR0rF#k?O*l_{ow}}Y9 zU4Z#*62iO-Fn>%!_~Qc1ACnR0O@Ns<8DZW8n0ZqW=1qW^Hw9td1ekeK5$0`xnKu<- z-UgU?(-7uufSET9VcrIqdD9W?@hvd(rX%_RTVQ&pBiiFzV0KJL^aHlQ%$tF19yE?- zAe#pb`x(gQ!PUXr_gi4`F_TdkwkBpu19<%lC&Nre5!m{dDGlKBf;bswA*%zM2NFY4 z2ey}!VKzeD9GH2t5$4T-nKuXFw==M`I|niLbp{qLbD(3Epv&kIAZPS2%z>^s0f{Yu zi$TULL1GUeVghqO^E39!Dyo4D3<@a>e-`}b1?iQScT`qU4PszekOEqZ0}@kEPymSq zGcY`WhzZO^avv=0=OVceHa0gG;XVbJ`{p9trvP)`Tt>M26kzU~i*O$c%zbk~^G6`J z1TnC{+&33Ae*_W>W?+H2Zyq9k@4(89c?dV(fraTjgq!cc!gL;^IP7dM8Q2+7^BCdh zU&+AEh?fg7g*bDKEjSKu(sKJgdHZ3HBame^AUEKK-N65Gb})|16IB) zK(YgtP8T5A0b17rY7;I%vIDYS3S=JKA0`LDX_B2`A;OL$Fn=sW*l`5rkA(<3j==n} z5Mc)k%pVI8{$PRmV-b=aFn=sUvIFLiMM!qQ{ILkh4wyd{A=v@*$6~}7&kqA=TV*jL z7yNuy$aok#!(v7*`1!1m@i2CVB}jTVK=m#`(z^lNP6Vk#=!J}ju`?`1=sf|mcPT>e z37EZ05%!*d*}Du$FU;O$NP1!RE<@4_vv)Zoe7(;NSle+qV$IVHSetM;V!h7|*nZvR zjPP?8Zou~IE@yK=VYLF;4!9VS9bmoe3@ecB0IOqXScym* ze_(laB_eJ7f#ubeh_vwsmRDCI(uNHzudYO-4I5ZqT?r~nAnP6^U}t8o1eGOFG1!@z zD?w!mR19`z<|-uj!Rnq>NbZA`f2)w(2P^+pA-NBBCfh0`_rcC&TZM3+49tD25bl$K zxo;K1eKIijtp=|p2JiLwu@JnLn2}*MBmA7`9}nSTpmQ4`>VAU7*cn!X%4g_0Hy`MF z%+;Xs87kHT7elP^Is*|CSc3?cE3k574I*5wz{-s^h;X?AD>v34!bJpDZmdCsiwLaT zSj#8^%fA(neiS>yT1GM0+(`wjAGMBA1eT{OAblowhINSfg$h`oX+5JjtnZfrGjBbj zPm%#MZv&$QLLInI$Ih?;(f`PRnYR&HFF1`eF>FFs2TtQm44V;Q^#qp2HzUI82`r6o zMugQ9SQ_7q2rCs>8sCfvD-~E8-^{3}EGOserlQJ_;E)QrzXBvCFAouGKoV0>fQTJ{ zhzV>#b|1L?!o;uz*?r);0we}s=lcW}ms^nC2iD8Zum#zDV7(wQxceMn?%Tqss0?+V z1I&FOF{t|-VD8(BcGm99f5rc<;4JaLe#P%TUHG$c? z2jONDn7X~l>cDxQiD56YI;hw_WWRyS4JL+t2)#D2@Y{#%H@G_ZoQ(}EO!p!C4XzH} zr?Y{D^FD-IY+&KMAF&pD1}Oc3(*1tKTI?Ahw?M?;Yq4j5#%Lj8@U_@8KyHDE!P{mt zKxqvk249Ok1LPKn7(Bnt0J#Mub^zg)6`(kWh{5+WtpJ5RL=5hh6`(kWh{4^m0u<*E zF}Pb+fZ`k?26xK}P@F@=;BHv~ic65#K|~z&fZPH~2L};x)B|!0L<~NE*#mM5L<}BB zJs`J0#NhLYJs`J0#Nct%19A&Q44(daKyCqv9YTal1T2mYA>t?k7DtCbThpLx?G>~h z{0H4xcZd;uMqksTh418Aw6T>k^K|z?906)W@5C1`8LPBscf0&rCFicE= zAJi8IsS^=_i}}OE#Kd4?4*sC~SD6@&BivE~bIWmrTS_>fZaI!{O9{*^#~I;nDG`9W ztau(qh5m-Jti*SnwEL_ea+#&+YM`sak5rKuvS%h0e zVEO1Q!Yv}Oa5;zU7HGJfLv{-^T+Si81sX2rklg|emvhK&friUDWVb-Ws2ATgL* zu0h=b7K6Iw8q_TyF_>GfGYY}lQcGa@=sKeatlhK(mS?Uriox1QOJMoq2BQ$H&9wxU z-)=C9z}i`xMz;XnKB%Y%erDKSj0|nx3B_+Y3$4&yekf zrsrqK_CnM1bA-KfVE%oMuy+p3zt0i&&Vl*&1;XArF#o)UnA^oft8c55%#vg%EUJa zds|?Ap*IM7TR`~;)JJ@Su(t)2k3jvD68l(Ft9N4G5mS>pNZi;qX0t84<;rk1yjew$MEMdSe+0; z%nv3eEDck~!pHFEIar+tLd*{)CME+@$Kl8D=RH^*KO+N!GU%`&9*|o=<;#0U0fZQM zd=lh7LAV&mEf94=2r;-iVYnE`Ef94g2r;-iF(#P3Ah$r&$%53WFfcG!D6oRcL|%sX zjB;?X1h|+yTx$;#!Ni!L@c}Xq zCdL8{dysidP`x1kg3S8}8I#dvU|^7ewZlF_#$+I3;Pnwq3?D)Jtr*PRR2UczD6m5A zQTzy=dxD51z{No43qZscz{NmwPY|&O5HW#|jEc&N49@PR3=9qosse{Vd!RouDk?HC zID>AOcW8i%F@o;-0gwAIK*xeUB8>$xK*xeUGJ?()W^w|b*raJx|7hfdS^keD!RZM+3!O${18NMRIB>@&LUlDVu39xYaikM4HfQ8FfMny$M24@#n1_lQOR)K$@@cV}FZw1W1 z-w^(-fcf_u!oL+T|9(UGw*uzhZ;1Xv1ln18<^`U@2>|9(TnM+(fp-w^&y zf%*3v!oMjn|9(UGHwEV3ZwUXo!2J6i;a>@uf4?LAD*^NGcZ7c>VE+A%@UH~Szuyu5 zm4Ny8JHo#bF#mo>_*Vkv-|q$n18<`{F?#u?{|cMGhqJxj_|Js%)dVn z{*8e7_Xoni5itM$K=?NT=HDL(|3<+4`vc+M2$+9=Ap9Ev^Y0IYe<%P{QDE(Uk#XleX&_?oxhD?LI1NM$KKH}{Y9Bzv z;B!wLpm7?I*k6Rb5iooIBJ7QT+4~pVj!*`*BNj+O_Fgmm1-Bz0Vo`80P&)!5HVZBW zYDYlCZb8HZ{vqbYPr%kt{X@))pMb5Q`j4y*JV(#O@E=(nG)x(o_+fXGKY`p=4!Vv| z03inLuQD(R!o*q->VyztaCPvz(^(Me;CH99Fu>Kp?@oWh0PVXlBHID&3o$Yw*#TFF zWCvUwk{wWWOiTja3=GPk^CAlzd>B4};*E((2qsqI;KT3*A|?V8t8nmP_yG|UgNfBR z_<-8QObkp+l40Hq%2pr)9e5cY{NE1}lLCoZOEWMyIPfw&frv?i#B8J)7#bXS8Qws| zWI$rJ(hLkO4!jJ1Kw``Y_cg%mU`Dbd0cr;`6T*%Js2$8q2s;v>b}%y`>_~vx!Gf^E z0cHma!VU$PKUffUB*6T^g0N!&%pWWWJC?xw!HTeh0cHm)k{vLAup-$3^9L)E9WZ~e zBH01+2OGkU0tRSYvLVGK12it#m=JNv0F6sFCPZ8^K;x1P;XVciXgISW+~>dm4QDol z`x+Ra;mn3`Ukd{?oY@iXYk=9oj%0@d)DCteI~1UHup`-_0JVc1$qogm9UKTd9AI{E zAnZ_p`GW&tM*_?r90)rW!2H31uwx0#ADjp~7+`jABH01+2PcvpFn@3&*#YwhCz2g7 ze{dn}IN;z5$y?k=VhK<&9)#Efm^xl0F_=0&CdAo>%#d=DfsYAswxKgz3~@F_Gh7U^ zjvLg;ISdgK;D?!~!q6bX0=e^rA7-8kLqiB$3~HVVL&Frf7}Pu!hK4H;F#!Q2^FZhI zf!09@Aejd`uMZ-IFb{NIA4Cjc9_YM2(49GgNal$`>|hW?GA|S^hA?j`Tnu5}Rfw2? z5EJ}qL(vKMwgjxZC#UfBIO!b}Kz4@1{uiXiEQ zt>qL!(hFP5DT1UIww6;As#iso!2z~TUlghrBnDfjFACKQ5`(SN7enYxfaw)O=uLp> z6+`Gvfaw)yQdCw{bar=f6>x&}*(Km&3~(_?CPhV-|rjG^YKsvz745(AkB5`(!9BnC1MBnERI zNDO2iNDSsa6S#Q@_kqM9<{{h%5`&nBa34qvVjjYMrcm=#R0SAd;Rg}}nFkVsxep`; zG7lsMb00_yWFANi<~}pHc?@v#Kw=Q{7#LvYfy5x@F)+Z)1BpS*V_<-pXAU(_RR!Tb zkQm53kQmH7kQm53kQmH7kQm53kQmH73%Gd*_kqM9<{{h%5`&nBa34qvVjjYMmQ1iU z(E{)_+aNKJUKLe=1lXErkQhiWNDQ_n+6u0h;Q(wsHAoDim*D_RFGvicm*D_RuQd~5 zoLU7k*34kdgczqzfr}x=sh7aT5aZNOAYuYGOtMOh&^-ehtdKh1hDi=CmH`)&hl{O% zizz5ELG`|XhzZy-$*VxmiEda35o54rQczKVsB3r#5fiXul2s01P49af)Ah8yP2cUgzc1#Kgu_ItH0Xrrg-=}K;|(xK<%|h z*sFlB18(mEn3w~TJltM~r6Bk5GJwS3{%r;OjlluQUWTJ!F#!iAJ>>v~Xt2EvP`pN+eFz)G!Qg}lQw9cTm^vZ+#=rm#Q)i@bVSwrdi9y}R0E-W2B)zcsa6$5010*g5 zKw>bxu<&zbl2wGKwI`6UcV&`SgsN*`cmfV*23IBpbTI)}CLKjsT2p|83xg|@g(57i zDL~VeE0d)nEUm%B+?eFx_AY?h>xN`+1JqtOBzvJ^0&YyYimH^?m3~;eP zxR`(hOkEIMi~%kdj1ZH7sSAON3Bbidnc(vz1q?2r^|5>mp@@D;fdgC&-cKoLfQ!NV zDFp{0Vgg|Z^Gaamg(1uR z07C;rj3FDYPJjWXE(flTfnmWyhr_Vh9eGo3}+VnXJRO35)u-EiRHn>L_|cOVhwOHF)=Zy*a4_m z3Cz5Bh9?es3~xZ@mB7pciRHn>pytIhJZXT7LCuS2cya(LR?6g{62OoE^6vpqJq?;S zEkhCm)xRLIawIW^R!|z}WvD z1|3LSl%a`9*3OPW*^2=*cgzAR!+61BObp6iEDQ`DkbNRxF(x|(Wfm_61{Y*8CI)3t z{ow->YX+4=kb7@zAm?ZE3A7-ILC(+S6KF*egPfnuC(wo{BT^vd@iDYBDagx1=It|} zWv4&~LM#U+*2#o)M@tH%E#Jiiz86`Xfq{WV;RgfHg8y6sT}(_q3=GVY3=9lBFtKhV zbqk>Cx{=hu#Cky6aTu5x7#I=^l&^yBPGS(~MU+^Q0HH7J%02gBrV1}AE5iX_x7n{Ts;=#ZmB+tMgz`zh9z`*dIfoU=mc#Q}PXblTP zFsMvqV3>jsvw?|CWnu!YB>}0cakvatCom16PKH4kEXFV$A!Y*;n}Mu%GFY9!OeWAq zB_>duGcZVj(hCE_OeQ8K=-pTh470#u0<)0SS%JkkW+AHs-y_B#F&kN36j&X@Y-Dw} zz+wV(kkwUz#W?05tNR5Olb8$f2W0I`6nM`R!(5Q_pnIzrZh^%F<{_)A0*i6XLss_- zEG99ZiP4(@de51|Owc`N3=H!j=|ut*!4BZN$`}L|AgN=3s#}1hjsdD}A(A==Nr-ui zki;0EVvCW)93mm=mLQ2SK*g3K+0g*eE3gzv-2sRg!!l%b5WND+kkvuN7?vZegZM*W z1$3-bS(TxI0dfut!wN*ZiGd*%6!v@!E0NSOLe;HAsAGYtTZN>K394=tLLCQ8-D;>h z(D^S4P<3k%VhS*^weURnAD#!-!Nuk)!SdyLxY&K@9fAxD8{lI0aCIBuV)1aXO$ag2 z-FyE*ckgY6i_M3NZGns3hl_1R_)P_LCd`BXd<@&5{s4t33)pXb4BL^!SfOG&m@F)0 z?bFg#IT##z4lsNGwN-Y4#2g`FT~M)IOct`T3~8XCx}b0n6d(KyyO=C385lCNKx4jU z2SNFlpJ6v#9V1-bZn!$82QYPe;N{Q*KMrWwv==V604}x;9?4Jv7>M?2e{ZVxL5*Q z>^NMk0WNj|F17$Jb`maj04{b4F7^N}b{a0mAP95c8Mv4NT`HQ@EG| zTbg+U(fUk-#A+`pU%v34G4`OJk7Ylew&BgESIpz3%KV$CoyUS>N`TME=3 zXK47zz;NI{g8(nHod*L0vpm>2HyA)|TLC_ZI&k}{;Rm?wBf!th$O^xUE*pFo9S1)% z(*1O=!D12uV0ED8sXPNiwmgHve+CW#usW#NYp|Gv05dZ?0|P`%AsgIA=MZ3K;ed<1 z28)5zS%J0}Gcd?AFciu&G=R-xL5O_>i%AF~+p7(>gF_J6-qm0+2|;9gwZV392qN3N W8Y~7gOacH|kAbQH diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index e4180663c3ce2a6799710f8459fb5679bad40772..e9137156011affcad494c4f3b8abe473a1d8f8c8 100644 GIT binary patch literal 48760 zcmcb@!~g{fLJAE3|Ns9lz;G2V<^UHv%mfl-2B{TLV0ZvhCvXHVrT`Z^3Kw&LiyecD zCBVgw!^IllVkh8Y3*cfW;bI5iVyEC@58z^_;bIJeF!!B-iz&dx&cekU;9}?CVhM1u z^Kh{SxYz}_*aEoNMYz}jxY#AQ*aNuOWw;oF5X^no;9?1IvFmWL2DsP_xYz=?*iE?D z0l3&LxYz@@SSphi0|P@WDBc)24uB$UOgJFJ08*ENBsLK$wu{L^R+b@KQ;UJ&g2F+DKM%m>!NeHhVmp{D zEM)DobF?@Z9C{8gd;qE22@-RJh;>25?3gT-0~qqWgBTbZ7#1)*0I9QMvQQ3S$Oefq zz{KnkVhRW`xZVXYF$aWs2M}U#^BiDejtKJ-pke}!2)z$rVy;XUiZHh*K;7rcWT^;q zGfd14p-urI23NNLCgzS%=YSA{t2+P_^FXLefQkutAnbhr6H5cfQ8YN-8X5!|K;f4T z7ZYHBiDiJqt$eg01*?&g{u>QtILI}6M(DBgR5g;Xn^Qt$VU=e z0JXP>Nk>VRA@8xFRnlS5@Q!0(U|@oZnKRf0GBEfDgOo8mWB`Ys1(KKo zRLqV^M>&8Y4w5Dx2rz)c*`7&PIe;M^Eam_eb70a_4q!+Ci#0&S9GUc$0~iv)Vh12% z0#Oo>86= zrgs5EFT;CA1tyr-1BjTwdq!EfIt7Rr!+SA?$bp5fiXx zLbzoKM2sPciOH6Mfr*cSfgxf)3&W59|M>;BF)Au6FnD-tG6*PKOci+W|35ESOdcvW z5hBI_QYQx$3xtYohwEj4>jjBH)G;U^tAm)wpa3&Zl}S-ak-@{qlR>~iKvm!nC@$5I z#3n$+)R`2OA?g?$0w7`>8c1Rnpkmq}F+~p_PY(tM35Xa27lVS5f`W#(h86>Z6bq;U z!z;jpBqjkB<3$pago^PYiAh7n8bD$U8lbXd!I4ymc?}G5N^(#!7l;@`1B1MhJXEX& zD%OZ3)(#g_P*Q-ZI}Q;OXhbs49U{iigk>_VAVf@{1<8&^h!{gFl3q8s7{ZQY5HW#PB)x4AF@`oI zv1Yg!!p+WbF@$-CAz}jNjB@a>?}CUitY$>0I|C6DSj~tq&j%vLu$mDOZ#_`4uZ)ng z$%}!(L4j4^--G|W4Brr9E-}U;8{s|)m>u2-J0xIs_#oUT1Jmn+&?^Je>x0lMgU|~PD;bzu=78MisG+G9 z&cLuB1)Me*=78(~iA69lJb;J^%tfeUfvKB|P{#sOw-RBm1S~FBg4996SppX4D?#Q# z#b9Y;6+%n~AqJ028JKyi5a!9i%sUDagQOQ5NEq-5d`5(e0jLcJsuw;Z>@Wbe{~%&; zI}AYWI*1rNjtoF;!Uz9(1->B6(}9@B$M6*)mH-jsW%!B+g9Mm)UlH~u!0i1Bax)|h z5@2?GL#RuEsr!boBL!y1H-z34gkHEmQegIeN4O;eAqG#+88Gv{Bh1TynfD#xmJFC% zejvnh5MuDK%7N+qfpBvU%#I%jx8%Uw@)Kci0Zi{tgt`KRI(XVGfZ6*KVMhVXj$a7( zmB7^fLfBCPv*Q;+ZwW##Jp4*v_6jk6k>vh0S_!qh9blY4!D5w z7N0;U6Flq-7$9N{p$Iz)8sK7ZI|>}2Vqpk-OAumkdrM$;gdyxGf!Ps;u%iTKM>s<4 z0)s2qeGK6UH(zjohzUd>#I7L3;NfxwrZ*DFyatF~hDe0o3kM)#0#OLDD+n=!c`&`v z2!Cim;)stS9wD|s0b(9Q6O$~H9fJmoKLdjcB=7Tr#O#=-os89?ns zXk81^%fz6;!p^|p15?)wav!uTfs~zm0xd{lkg}6cpcP3BQWo|9Z(fG^x;1*hb&x-0WKy77ZY%RsndjuF&tok=w;A? ziwVHRe3=xPm>4`j;Vht_D)2|)Kc9pjTucBi=8q5)fvF3Ci!s2(0^wo;5-@c^a4`nB zSTI6N2Bt0qE+zmM<6=-$Rs{7;y%-!o{s7eh+(=>$sse`|{O9H1K@w|#h%xXY#GGJy z`QTy#aP#<)#9-zLAc?`uGiOi?WMJ?Bk8?G&3OoS0#R6IEDMU;gRMv%RXlOb!n1Irn z!hb#nZBV&}A*P_9fGQ@S4N3>7Vho!>V+9Hx-kMqr2?tWab_jsPpRt93WyGATg+a7c?M=$;yJl zUSI(ORLl@=9zz4nJdhYf9YX`MI*54;4KVXS>LB(qG{EdNf}1A*HxDER(JKJg3lf9a zApo}nBnB~00B)W!)I2Rsg!@2ZAoDojK<0tOU~UG9fy@Jm!Q5xU1W7Ming}~U zVi5BX?gNQ|!WpCv7A_z$h#d$wn?l{EsU^SwQwI_QsRN0@+yW8<*#Q!Rxfvt|avw+x z<~}p1`#>E+WHE?d1_qd3kUEGR3=A+kKw=;_gY?4OVh(kmmL|e|ATf|$kQhuaNDO2L zNDO8NNDSmYkQmG@7EFrD5WNU{L1G|#wKN&vVE__?=w)C))(f!%;SWow`!ux#;N=EL z45SVu2FvFlF_3v6F<5zE#iXbVQO9rqrVb1iZLUZcMu{bzziC51C9G=F)%nn#2A=h3RBR?(Ojb!2Dh3)02l-6_ zWCv92CPbZpB9eI#5HSWtkiAfKps{t3UPUB3X28`U#$#_l#01P4WCIx(G(hbVhlW;g z{$Q{`7JCX2OF%Mj4n!|Q0+L%|;9>|n?m)x@5|R9I7cPbv2abh^F(e|{F&8S9gk*_|hh1Ln6h zB)7o)mWE^pEL`%D)PctNLFVNnnFku@2icpCq!%!c3;{^yaYMxdk<|IX#SrG5 zfrtqNBH7ym5n~8MGLHu;7KEg(7cPbfD_^)6!j7{LF@Yc?^LQa*40E97f!c`+plN&# zG|oX{4VX7S zNE!PP^DU$9#sVzc04AbTNVw;*Bye6aZ_Ed~Z>h!_JOZ0<>mf#EPj zOn?tIH>SnFzzh*%;DgOuX)!P~L&Zd)dNs8e9AIH33RMRZgN3Om)LxJnEbPS)dJ|xJ z#SrQe5bEG@lmIhNAJKkZ(4Yd24-SwRsC}=g#jt<@NetSiUT^>+CIM0hX#+DXaDa$$ z*fGf}2QX-W)}}ZxECHLxV9z867h3=ob6}E(i#aTXsB>gefQvnVhzU3$={*1uV{k^& z%K#N~LDJg*u|vR>Nmdc=mM0K9+?eFxVhf;R?o9G>_+{ecd$E2VPTF(FydjJs=C}na` z31CPCh3Nr?7LYn#hB73v2B=s$k{AQDeN}-Z25WOwBK&ax=8r0bKMp{{kD(gjj{~r9 zu0ig>rCp19C>Jj0bzyJwTh6Y49Cp19B1Xe)Pu7(yv0|T_o zS&1aZ2o+m}B*p|4TMZQhl~)Q-u{8)W1(?`2s2Io&7O*-#hV4jVtWYsKCVAx`1`Y2J z(D+ab!voM5s2!66LhJ}wOu!yVtN|{D&*sZbvIvi~*DvU}6nW zbxsJq3=B{^oDl9~0HqC(9iaRH)yn|0*BMDK%zdCd15*cciz}17B2=sa6qg|LT$vQm z#RS}t)Pdp`q|OaV9aKyJl(*pKJ%#wq9Z4N19W40ID*(!GFm<4G01|U%VDe^QUSiI-{b7Krn~hLc6Yl{rZw^9T4Fgnc zE<)WOn7Vlgb$?*$j)BEoT-_KLY8HUQg_YqL*dI_aaM-g797hs+02c#=DMZ}^sNNF@ zb$=E>)tx}t@dswdNhEbJ^G+hEgPC^+CNN#C>>II3x z^fn;rh1tshwHKrgBnGmB0j?L}j|QkZCvccT{Na!ZaSKQc?q4J^ki8(k9ms&Fn+Vkl zvcm!DmWkkagPI5R$0Q^%&{E+8{}~u2A?am+>g57OB?B|70%$cc*j^riLyU}!3=B-{ z3=9vL6|^4wfAF7y;SeKe^8-|D6cTnwR?0jgJknT3Oa0W@VO&!F&Hp5eiN z1_=RXW_Gw(Hdu^95Lw-7u$Y7(vN~LC7Lcnz^b0IUuw zmJJr;5JVQ!hKYgffT~*!7L#CPU}524U;+s;D0DM`!bO0Q0pww*7&lmqfr)_$p>8!; zOoEAlk(nK)R~szG!Hlfe8!X1ajBLkgu$TY~vU#t;ViGLK=4FG$I2ak2nAo6pFmyA3 z!dZZk0Th4`_c3sT#Tb~7#k9d<98Ac1SA)eQn32U!gT(}xk@b3m#TZzS#j?R-94yFs zUxURYxRBLxfyEfOkkxg8#RRyK#a@BMB)F0FW`V^xc#zet0*eXoAgj{?i!tybt2+f2 z6W~Qw=LHsH;6oBqfVz(lNv{Ibef-Gkpl;zuRtI&n0J1u$TLh5RLES8fECzL-AhKSl z``0X4?^q#OdT(h7)%`#lT4U5gNBnV14D}gFT2)GmjHV45p5WNgCu|M_C4j1_xe-HxU2A5Mm2pdRdXgVCvWqVhs#Xy=;iEFJOS$!H%R(0jiDzA+`XfmlH`0 zrjCh83giz5Sq26N2VRCJAb&6;i6ubASP)_fFm9VP^SP>$BHBdQ^$r7V_<;lWk(WIfQoS- z#1vraIFZC)>Kqt&cwp@khg?uQf{DR_ftwp725MV4=)%N!c|l^Jwt&N0h?pY-LW}_} zhS19Z)$5342Lsd&1qKlj=zbiJ1$mJCtH2;E3>VXbi3te6#1!D_`1#>taCL%$FtG%< zn2-=$460WV*$zI49f}M{>il40NbZA+A-M%EhGZ|?JS6u)#grJ}dLt5`Zc$=@tBZiS zSp}g^LIG-r3PPQP0@OTJ2DrT(Fuke>bsP%NFi=I9#{mmJRfK;zU~WlZ5EFxj)sF{I zdlL|0^#heh%5#U1CSUz&VMX`x;YWq z4zM~VhD2od!Nrj51?y#JNMb;U{e+7l{Pqy4HwnotKfz)ky$H7~1nXsDNJ4VULa;g} zh7yF{8V=t&0N@R85FlAz>M79I0 z4kQK-mlLo!szi1lST8$66+&zU%*|B@_pN}ruL|Lo6)^u+A>6V8=H@DdTUNmQTa9c7 z)ZS`jJD_f^Mz#Yi#?DZUYzJ5`6GJt!9bk1#3^hpR!O}quk~&y=sX=lJEUncb*$YdP zHAwct(qApIIpG*J78g7hfucz7S44D zJ9farxenpC9k95pL%4YdEZ*vo&4b!ok8B>)&GpFUfz`1y)FZnOt`1)A?x+Ndu`@Iv z?Cn5^!NZ^fRvt7U?CpS+8x06MI$&wH0paEjMX+0#7#b1on*j^cMugrOuzcQ#aLWu> zx!Z^^Zw4&yHzM3J16J-fA?byMUlWoYusCW$(hG}^CM5U4;-d-4URYcl9`NafDa|OiThHmH`u!M2JR*w}AZy zG7lbBJ78@>CuH}*&4Y*E4p^HojFAi0_TEtlH7|^j6V{gBVTcfewdHphLd^?fg}NmQ*$%iEJp3|X={XA7JgDEI zknM%*g~w3_EFVQPa>3%w!T=f{(Tv=%II<`}h{4i1;?2SUF2(~(8x|X& zdSe*55qhC+iD5)i2X%7{vRmL{NN$0PA=wKxFBXxWSHRpC%Lq@;D`0MkMdXD$v0_KlcL_S&p3zs-#y->HrA*+LnA=wKTL$U+v<~U?GL&f5e+ziWu@ksW<@_9Ux zy|8>9k7OP!Psbzq4VL#4ko7{{mw;>sLJSsfD+;0ROF(uXTphx1hER32jKZ+Kt_GxR zXJV*jzW?ntQ zUJsbP^$7QQz}(k>u-60D-e^GB;Q^~d8xU^sfVrg+*$!wJG$Pvp7lZrPBM~arglq>i zOq-DHfQ!My#RJx6Xh!%~17=<`!d?wnTdx`6J`GqKqy=Gz2CS{pf^drltWDU02p0{Q zy^9g);D-U!eTx~n;NuaHJj2egn2`%UZUM<#>{Ts0KvK-MqxB+X2 zEoX%H4Q{~NYs(RBiyN>sw44#%H@E?7hpj-?3l0Nzh84)_!081f25&RmfVKHoAiEE& zj)`Ffvb|vQm>AYFiooKd0+JWl8P+n2!RqM>Se{wOC<2Si3P@gHXIO`*XDVRnemx?s zWx({VXB3C!=?s`18xZL#1EzNaqXa@7IRCOUY(zE>>W@vxdZGTv>lfQsEgq~|3H z{t&%)5beJu9B?ssn`?;xRO~LY9r_Txcahx!7elfaDs~Uio?If357B!M*FF~P;eK<9XY z?cjjx6^5&0fvWqBB|d&*iMKz9^uhs4FMkl}g#(se{vgr@2P|#;L8LzpSo-^eu!94Z zPX8d>!U0Qbe-UC42r+mcF#@LdAHv=fu(JIh!hI)TW%hq$b>K3BiQzx8I&e7z3R5we zFa`}xV+IBmQ24$7&&2S7Q6`LuLBp7Zfk6f)_MTB#8m0~urqBO_^ok(F{22a##6Wsw z!ZeIEO&C}>@)-6&%##jdgqjD6bC9}t1_>Jm1`Qns28KTj{tSP9{AXu~XAnn-@x#PK zU}9e&>X;bf8N?7``5<*5F=2!lST7U9F-8G_PzDW60|tf=Q2zMwA0)=l4;O=~JC0CS z0#kRK5w5NTlm|h2PawonIP@X*oxG(k9wDXzGw(b?uL{h(3&`rAdM_ZWgW7Qs zq0R(m-bI8u6PS6IkkvuWyM(L`YTi|-7&zYGVn}fb)q4%9&X9q@1r{II5O%o0;^R7_ z5G>BYw&3zgizN53#-QnbyHyKo*>jsfvJ0ntPbkFXUOWH?t6|N z3RxZ0yw?bIEwFHYgHYE33+J~8bv-b3?-1&GVCvp83Q57r5>R>n7+jVJBE~a>iA*mo*>i-!Ngh+>fmJw3ql>d z%z4594HrgaJK$nSdZA&;i0nSN7?QnEy~h{@1wrWwl9jFR2`^nf|++3stzp14^ejpSq!T8 z46@#Qh`O@~F%g(~XAycuVD3AItPZO89I`s79p@41RAAY(m>hO7?izUK&ab71DZK&YDoGw&s`I;eTC zkkvuWdyP=n0t@Fi2z4#6aDIzW*8@}c4xz3GrtUqXfF!KE0<~iwg3Bv@gcu*gACTAw zMoD;i1ylEdQ94W-+8$!bW0(VK`!F&H3kyTe0BZrY9UuH>Vqj$8=jVrtf!cZyF)=YQ zs2HfP0TB}v6oiU_+L#bA0RaK17^v+C5fc&;f{KCKu@Es45fP{us2vLuV`e}S%LA?F zXJTMxK++2rLvjmT49Q-o7#9OvOa|r_9wafCy}U?bp#BlaEqq8~FgFVziNV4knE~#W zD=>A*h%mhZ3%_K9->$&il7gfcW?l-CURZpjAnApfrJ52WCe;gM@?xB;HIM{6KNU&XAAL`vn#T`3O6{z``IO z;pQ)}Fvw>R7Z-<_#|JU50LhL6P&*2c)E$7UgQwjuu&^pXatka>3y|!EgmFB=lhfx?fOK@}m^0uxhbgs0OEn3xtqtOq8h!w8S_128dNgxC?7mHh%$WmA z2lkBcv^E76NA`^H@^1>P{If@xHw9*%J;J;x2=n0KJO$Bi7e%n2r(U)f4vcI(Se1FH^Of^Fu!>t+@b>uQ*VUd zbYTAVMz~K07FOPfFx7#DsSmPVsQY}7-2xYb`%MStHy>m>pkd&H>}I$ayd2j7jp>8J z)CV~Xpmz8o+?N7#pD)6W6qrAJ5q6}&!o?Ti<`h`?`69w91r}Dm2zygtVef}526c-c zvK>%=_#wLwt`45=Q()=d582Idz3?zdfrWuT!hJa~_xU62&4KyNA7O6}EL{8%{>_2; z*B{}J9GKty5pKzWgg^R(% zpad2MLCEfdn+Gp9N?_$iFv8v%nEQee_SV3{AQ)k94b08K2s>(EVGxW6s~T8X1tY?x z1{N+M$aX;e5rV7^>gEt+_rb;B@m2$iw-97|;pV~HFEya~JW!qvMU*9bVC7IK!j3(# zFbGAsWe?2Fp$I$n!2A}9@W&olScM|OY7Z=|LJ?uL2NqU|2z5(f>JkxlEP>gPh|s$P zp%)&POJMFxM7U)M%q@uszb%3JEeY9PXjmm7tAmDf5+V$iz|u<+vRmNl;OTD(Ed3=R zy9H`TGQ!?9F#jea)UAQJIT>N^8kpab5$;<9^G7nmEo)%ml8gwyHL&nYLDma(a|*J( zQ1_)EyALh~Pit#nX)OiW4!Amae5`?mRVt$xYz&0~=H^sHzlQKxkd!b^P z2zwP^{>Vhws{r$FCL&xEVBwO5@P`7-A6W>uD8RxX3*i<8SQum@+X3}QHnLmbVsQT| z!0NXgWP73h$U(LjE(Y&&D!}T{Tt+c5=opy*%pbXoLPF3nG69%>a~VZMpyOczuyDy^ z6cdAva|yuwo5v_30v!(%fcY(tQAh|nZYBT=gM4Irp?=FpwihmjWG_^#0NGxs-wKfJ zfQuoy1u9mEu-5?Q-$I1F1~C5?BK&Ir^KTKtUIUnaixBo2!2DK(2m=FH7!)Jh3-w1a zvK??Sc-R}j@@fgP9Z-LiAlm^KgU5#ftga|!6oln12UwmiW#osAJvhMZC}k9eje$DA z(p4Fw2to{MM;W64LN8oQ2w?|QtQ=uS0?dwbgj*6|ZYf9Dn*g)7f)Q?B0xX?YAnZ+m zmCqFj_a(smTZypO0T!2)2zwo1aaoD5*8!Fesu1Qmz~Z+GVXp%$eyb4fbAZKfHNw0E zn0eI*wkj%+V9?Y1M^3m1czR|jD6+ktEzG`(~ny9F)= zA4@v`i}Ox|9StzQbt2r-01Jaognt`g{_R58(E#&r7s9^{F#mQT+}8l}Z#S}eP``B} zy9F)=9}{eVrTZRad!c^oLADnz2Ct7AVClIRVebN%KY9`NE`WtWFCq*Uz`~#pVebN% zfBO*jE`a&B58>YhF#q-=+X3}kKe8QgF?jqgfW_|wWILdKn}F;VxES2O3t;}8i16

%&=$!!5I~ife1ehID5PB!T^iDz8F#%@BRD^jO zVCGFln709D-ZX@H8(`*5LzuS#X5Mr}8*U3i4Bigg0<&W}qW!l8X2*0yTW<@@jv2^e z&~ToCYzJHn$qr~-&Oo*UDmIf*1U8;Mr2#x&!O1X_Q5ZJvJ*5FW7S72q3t0@T7bJ$H z7i=#l!)%1QIWWDm5q8Xh*)a#v$2kKFmpKT(oq?s@xk&0@eWAHX>R{nAk5L>p7b63k z6PbrlcL!$PJVY4Wf#sul2s`e;+%k_5K360In>(405Ho>{-?KB!N7(TNR))<-*zpBc zM$AXp@dZ}r%}2P|!~q

4^*}&pxCBlwBu=rhxaLXT9I#`LY_YW-2S0e1Sfu*5UNa|qe zZxxbxu=KYINiS@^Y!#AQV0n5KlAB@kU~3S1MPTu<24Tk)SbVHOn0EyhA8Qcqy8?@k zH3&OIVDYgTVTTILZ<`TzJb{JFW`rG2VBxnJVaF3#SZzkwp#ls0Ey#92)AJT&z2Nl6 z#IOZfFIbG7VGFXoV7(x9@Uf96urSz)q!*SBwj$XJOD|iI%!8%1tw{cbrOB;G?t`Vj z9SA#gVBxm|q3#VVoOdA1djoUd4uo5DU~#zv;g&bBc-x6&9?agINan%Zw-d=cnBR6H znFsURP9!(O!etl2jvkmDyAXEt!0gzC7%S+3`C}KNPU(U9cQ?Xb8(4bYjZkL;OB=fp zcG$r3$8LljHn6m|8!-j!m_JS;!ZZXHrY8|$6#@&ZlZdbifrZscL^y}Q z!uce^zag;rIEe_;5LlR=Lbd}M=cka(gNwn_K?p1zoI-XpH2s}Ib{||XyqpYy#nCC` zFo5bk4GllgT0~fwo`!}WSPU8;XOP99VR{BxZ$2cP&mzP`VCJ1g=oNv*|wEh?&65yNJ+h0yFOtvKZ97OUQbm=3PdF zsS7M!T}H&O3oH#?Mx+B5SUR|jh)Wk(`n!yXOBYyLyNpOzF0gcU8IfLGVCnA)vc1rB za0S_Y&^W(>tQW2ho?cvF>E#NtTj1*8b8;@QJbeY(eNa2DLc?X20sNP%1>Y(=CXA~9# zl{uhwo3M27fKdb?<_}5F4-x8mVCo(r)b+s9%VUJPDKK?U5bCDD)ICL32X)^wWOY#Y zJx8dU12gXhLfssgc`uRGLCt%GtPX14YlONMSef_+p{@lM_HPmDdSL3_A=LH2)P02P zsWD<;V32{O=Z}#6I1n*#ACZaSGb6tMbX=K%0WJnF*BBVU{Yxf>FNicGfDnW06@cme zicn_(Q}-2-#w{T2XC{WPh%|12&zz9YmW z5MppUBw%)YN4P}-=9cdWJ0xIsd`GxN0_K+Q2){|d{PrCY1`@C^_dqp>L}2R9A&WuPokxhNz|>tp7K5t0h!8V@sk?+M232V9!v~s9!LzX4r*Qs!;=G0G0?htNoW`_<}tK@*4lpprL`~( zO)XOf1_nKbBcOWq6DUo>#PS$gKw=soF#!!tEo}w{hI62^#+ey3k;D|BVtSxFC<0OE z02R{)rBhoCO)V}4hK6&XbB>uA1elqvK->Bl7~~lk3gsCZ{xfh0FtZ@UK7z$SXHg@> z48dZcGpi9|8^K}{42&!+whl}zTs#a64HFp-9Qe;8z=$k%5h}*O!eRwJi(7Ex#42+C+5V0DNy`Xc?MUcgWL1hU8g9x(T$zU;ob_PaQ1_l;)a5^ZG2c1LD z@sSZE#^eq<3!TB}0W-+Fb_OPdx=)Ze|HudugR0x~fVts6gMbbL6BCmy6AL>R1H*yI zpmYinV`OB6iZuv>#TY~(?#s+#U|?tv2Bk>`22qInz+wj`gT(~67?>Gd8JIv0WMB{i zozKd^06NDSE>;8<}5#@MQ|`o3=*appi6fzgT(|`85pfy z7??PDK<*0yrws;H1}22qC9s$P8?rhfuowdyvbsrNF#&dDu}?5DBs+@0VhmgiEKG2} zLG^;p@`j5+^h)p`tJ?(DE5M5^26dk=$e&;=ufTlu|9{Xu9DZOvh_Hu?fi4yYi7+t4 z!^Hw10t^fc^>DF3xY&HSSP)!nKV0k?T+Ch>VlNlNbGTSNTpE>@8gEK3wc0TdxR}F4cBs1jaIpt9d{D6i2(en2*b}&zLK)1C zr*JU`xY#pKEcHj;9{TQVhj~LP&a>piz&dxzQV;ADq!LF4KAht7yAwu zYk=$h0T){U7yAhpI{+8^1s8h&7yAnrQ)q|z_a8#687B50F6IDN$G{BAaG*5l09VHd z7fXPvV?v0*)iJ}x7Qof9AjIJ6Sm9z1;Of{AVsLfA3^uU*roenv9-OyA8Jry$7|bOY z7~~xouF8M-@t=Vqk^ywJJtqSL10w^&74Y3Aj8SkgCb(EMT#Okm76TV!U{HYSjYSf3 zfQt1o!R%mQNPvhjgfK8UGcYiVfl4ETs|*Yu{xdLyGB`6aFo=NykU;<{X2cNU!N4G* z0#e5iBEZ1#pMhx-6HH8i0VZb5!05rizzk7m!T?rh%)o>Y+X5C7GC>yG3KK)p3u^cO zXJFE0aA#m(PzGDeAOb#3gi#M!Yzjoo5TXKfLlATPHE?~-8V479z&sx+_6aWbpBti% zi}f=?j2|ZU2O-7{(aXj97a_(E6Vqn^r8O3?jQlnEKmY$Tuo@tV*+az)k;LMmV&C9m z@*EJoT&&*_VmvUhUkEV{h`=cP{B|!BqMN;G{AnApR|5MkE9Ofz5_^NFt;2)(hGC*K_oGlTMi=Wg}M0;aNk161rG6AKee?*XXTBZQa>Ozbg2tOX`!&cNiyz`(4?z`($f@PmN|WUn~` zBSLHkSd77(fzg+Nfmw!ufq}&VA?Cxtz$^_q(+(lVgb;(9$Ar)e6|+FHLjh`@1p`7I z16&=#eF|_fMz|de2)zg~ggUsrFm;v;2)zy#5WiU>`wbz62m`2?6_Ppzgc!nJgcw|} z0#wWzDV!HT#00F7!r%c!jKKy;ETID8J{u%^9S~x0dtqX>NPc60sob(ut!!0344JKNP9yH)bxR+gAPdh1tJEGk4_|Yu=waiQU{CkE+loZ zIO;|cgN1z$lGp)g`1K%}*8mX{=tWWo3#&dPF<7|tBZ(b=`nMn1JcyXU1Y|L27_fq_ z$Yo##`#0exDBgGk*brhI3Q#e2B(VihF%Bd#m|jjKu?J9f+z>I)by*BBF&-o_n0dTN zVlaE>GlB0N2D{H;CdhpZ4D&(FHK>~%z;-YQEI<-tfQupYGC=h%L^e+nV%{PoF$SpE zVk9w#NQk;6NMa07v87022cUYFBDtjjA||j5Sq!3AU>UMrh#13iWOWcX3-B@9f$m-g zhd~20O?H8wGe=dP8h+auhSqBsAMiN`_gMkO6t{X`&Ow1gThCq559Cm`o zff>vp=>;P86D%fRfh5KN7XybgSRDgYuO+g1mSDXMR!CwDP%&#H^BN#xpz;OeU$A)x zAY!2M1uo`L2{F$W**vJ29kO{4F;IB`*LwgW1}YEWVhs>C3-Ch18EkI@)NkgOh;sJjL3zk#}H50nqy0*#w-3EW1Asl&wXAjGs`Vs{Z@ z`Y^Fa2r*-r*kgp4IZW&cLd+T__7ovz4-lK0NRYIs^fT>eL*uel(r;Jd?15>ArP{#pNr-D$& z0#m1gP{#sOr;1R=0aJGk+$RS6gW(|9A6x?05n?Pbu^R|64w%?YgcuJ@>>ff)048=H zAtnM7dw>v=fQdash{?dj=0fJiz<2X9M1k+&WthtZ4tt2$EwGrtJY=z7U@?h#$a<^5 zVjQ43AV$a?uL=jGKz(P>)DlQD_>NbF1GB(l0-$*{s5%vxI?((Zw7sSRQwN%BgR0Yj zsRPZmLDgx%)Pd%=pkg`*G0?@sV0(37dc{EZMMK=jfe?ecj{~Mx9HEW}rcN9*{|3>^ z15+o55UX*R4e^^ilGp*L*gFO$CeS=7I|G9OL@$@Xe+GElRsbT#Bf!MS1Z(e#z{Hpt znOLBD8DL^8$YQ%d_VP&ZF~a@p0C6)513yB{1tund5c7bE2{JM=Lc`AoVh4+W5JFu5 zOr0=7ECePdf)I;eWUzZx>jvgf_ByR$ws>ZDjM{Vo2se^{Ro= zRR|LcyD$So!z^%{K|l?ZPGMqFU@-=DgcwT$T#Si{38Ib#rdI>myjx(s0vZUt3=L6W zF$PV97z;uS$vmiD36MHQCKh%!1_lOc$Xv7p$POl`*le(vfFwd)15BMHLR|v`RGkz9 z6C)#3uL4v|8X?vI6O%!RF)V;Q{7z{R)_Vzn@JVD~}P?S+Yf{Q(jC3lXzGvZDcNo(06sV08>|bqISI z;OY?eGC=LMfcOof7iw=j0~Z$qxc*^qcpwL=&p~H-^Dsfh7}Do~#25wQ8Mt9KGZ~85p@?>eS$3Ogu2LG=yH5ItK-~Iv$uhhXklt0>Ui^U~WlZ;D+fv0Mnbm0M~l} zrZ*9x*Wn@9Ja°kA?luoxplB0{f2B2+91q4xkxZxTY?0fah)TVUqpfYm{+c2AI# z|MTEKBS#L{Jc!r>uoyc>4%jUaF$J&~BS$V=uYdwfZ!TP&fC54tD2_mS1r%WB6*KU_ z;_bjAus_%tiW#_JVh#u~E_nDU!`1P?#gxEej3B-6_(+0_fmSww+einJ!D8$TB@BqP zkpzw35(aK~dQpOlalz9I%q=BIX$WR-2?GyY9n9WR287`jK+QHrD&;yy-( zQY1Sd{soJ{-KPxITgJc$3oC{nP&>*Pm|)?;V1ZDF5Cf}YWGG``goPDD1zZe~?kk{r z%aQE(304QXFBPG;5-i5ZP>z(3Ea74Zw^+i>L)cLX6{}!ig8SnMSd5*af&rl}1uVwM zP=REJ3e=7YB!8qJ#1Q6z#lYsl!$1XUUL}&fPr+iKJ5&*FRt1YOGE^dk!BePtl}PSO zMW}<@p$b+9)(a2kRH#@LlD!YWdO>%sBK(^G7Gq?nLb4ZDmQ*2y0jw;kLJ9*|SyF|R z4iuo~RU^4M5g`V5vm!za9)1tOVxYTL5#=PT+^9yf7goMhBe@w?4%Hy}_XX6v8YK5= zfW;UYYLN840EZPjLk*IfGZ5Wx~xvq}`WbF?NPJB>#SZiy`vr2dH^%M(M7;{r+k&v; z0L+e7gqQ=&zpY62!u;Ecu)_i7-!_Ea12BKIA@m-Ag+Uua?*UjCNHK!kr=ba&bI^zb zwTGA)^+E{p$d!qc|8=gUtiS<&TA6^B5UcGs4?6KOVxxK=nRE z-A}L>xNT;`z`$g|z`!7oAooE2!GBOYj2kYd02kwei#-5~u`?tyaB*=#`pFugGV#HG zkQg^NH&hH%CW6dMX5iuBfr^33M37htLazl(ZwdokuLVqR3PP_1Om8Ye9S2NZDncCx zLLJe3MANx;lYL%2@@rZ*j-w*#g(9ig`arZ*j-w*#g(A0g&}5QF>I z1Ex10VTT9Ijsk>O1VRk1Hv*=&0AWW2%#K2Y-VB)DLWG+$V0sG?dNW{pixBE6VCsqx z=2gJVD?;e4fa#THg*RJ!DUV0ZdGRk(U>0 zo&!uw5g`@;6H`X$O@N8zf&2mK6Z0s@f%70Kz@UYC4j{k88Sd( zJdl2^gFL8T3lihz=H`ZoF~G&RxVX3=Vh6xt>!NeHhVmp{D zEM)D|(p5Pa9C{8gd;qE22@-RJh;>25?3gT-0~j*hd>I%T7#1)*0I9QMvQQ3SNCSy6 zz{Knk>J}ix;OZ1$Vh#ws4hS*09S2}yjtKJ}K*aNf2AJL)xH<-g1q;FEG2|fG@c<$wkP80F0ES3NntUL@019V&CSBzKhA6O@160g`Nl!U|AsQ^!02Om&(pL^(hyjZofQSjW zGU+J7%u|4fF}N}5D#FZ5fQq>@=_$g@TL2aFVA5BFnfCx9CQ!g+pd7#u3$f!N#C?TK z28uAT2T(CRP|*(dEW-pHRZtzk%b>)h$iTqh3=(}Jq59$f|Np!UItZ~3l29>Su$T)- z-2@F)`F|jF5{$A83=GO3u?GsSpt^#OK@uVM1SY1;ps2{e;0)62V8SW@)~n2<2_lK#UQt_koft$UHs=CU}6s-Vgm0OW#Q@+AYu&f8Rg(&2~aU>CWPK65HSI3CWIYJAYu&GObERx za501(Dp0W`CMH`31|}|0<*=Uxo;`C@Cl?yD6(OFi5e0 z8Zf*9JV;^^P%&O4F-fQxACj0fRIGtPPDzeI8B}g8a7hK5$I!qauOtr@Yk`X?C@Db2 zjzGi&8bRhk#g44TnwT2AVf@{1<8&^h!{gFl3q8s7((wch?qbtlHN9m7(*M9 zSTkG<5%$h-F@$-CAz}jNjB@b!=z@qbtY$>$^?{2a!oCMChA{68L`>i-BcyC{Wngen zU={fH;6E?JH-wlAOzb;C%mXI&10m)E6Z?q}3xJ9JLWqUH#Q2%yl;q@;-IP@r8bToH zkAa^Fnx0h{8m>UZ1o)X`m1Jch>O>%74E#*;O7ij$u_;h70VMOn;bI8A;&3s99oHdZ z0s=_pO^1jv2qL-VDnv{`5Xmi~5HSWpBzr^QVhHz5g^CFy*#V1lVI(_X@hgmE9xNS* zAc?`^R|LsCSp140nFots8zxyLMrgj&V1?vq8zu!MCaBm8h?sy4lRRAA3Wykk4U-&P zECVWL%cP(J&HD`xAz}iyO!6wwGNNH2M2w-4Nmd0GZ#q!1P9~(Zn*wnQBZGp10)sNB zoz3uo1=P;w6<}nLmzRf%Er5tIFfz!>%0k5y;9_!ea!|1Zs2DRs9SckyGXq>53ql>- z4i=al%m}xzz}%9I5Mwxy3UOaDlKUDUVhqU$I~W|GVkro9EHHH`2z4w7b?`7?f!UFY zP{#pNmx^!;2SOd(9~>|{G#C{W6cm(|RaF=)pkW}Oi6jOM0|8G)xLyHR7Sgd`gvW;f)D8wOgqR3I4DL4(n0a0Z^F(0gc_G{)0&|Nu!aNC>dEN;3 zNx;nWMwll7GtV1go&?N1AB0{Rm|h=*UKyBPAB4R!FnfIv=E=a!n*%b>QCUSbn1SIz z3M6gJ0jUFt1u-xzfQT{7MToH=#1s@1KBQ@iBZwh$TS8cp1JT^d`Xcenr@u0JHZi$jy*2 zNPyY<4Pjmi%)D<1btwpS@bsJlv*R1Wjue<3-x20zz|8xOFfRjU-gkuF41`{|9T_k? zejwE4z|{Rfn3n@H?+3!(9GJa75aE&oGw&xtZvjm2PlO!>Fgt!C%qxJI_Y+}W0nEH# z2)!jRy}uB4l)&uxg)pxKX5KG^c_lFOgqYxAzynKvLQL>7hX& zF?g6>f$5D#_(KB{M|=$N2(bkU5c3$Cm}Kqj7?iyjK$d%MwU=$|ul*BnBxv`2<>##2{rcpFkVJ zeJK$0_!!!m6ku(E3~2ZXbRfiXU}7r}@yoyfu7CL$RwBe$U}CEfVjM8Btq3s{1#p?o z$1n$!p6!)YR0A0pKw=C2^D@juh_S%LWMKU=R{^I3sse{T{O9G6g^Mx3#pK{(0uC^B zns70O0}K$o3|eq80l1hilOhungEJ_c1r$^T{wVzClkkI!3Bbkt5n>`RbpdcO2Dn%t zTueX$rY;CB#sC)!Mu^G4)P=ys1mI#^42sH%puVXqg9FGPpz@v@Nz6f2;LwBryc|48 zVhs>623~}i6HG53TucCN9zT*8%sc@kF_?Mg42ppa49?(ju7*~D2OzgtAd5YPh-rh$ zuux@X6*~qKP+C*?&&Qw*D*rIV0kbpj~rAm$0c z&HKm*8GA5gK*ZZeM)3HR8K^vfh3RjIIujQL26!BaBhsl8Oq~Q=i~%kt2^!}DrwswP zUMYk+a9#kV4QYg!6D)q^L1GNf?jZNU#0;1em7#uHa6knd&JrLoNH_~DaDa$$fW)Bw zUC@9eCMydHdw~TEP%%Tec?=CO^FU${bqo#2>LBJZG{DRQse{;Q?u z+zb)}xdkK!bDtU1eV`5@vKT}!0|QJiNFBru1_qcNATf}eL3&|sF^9TORR!TbkQhiW zNDQVIBnEN|NDO8#NDO2zNDOAL1(TvOL@&Z#kQm5bRTTz!7=Xke<}on9%max*%tQFY z66!t`RRMUp0TKhL1Bt=%K1d8?9!LyUMp!W^DnryU9Du0CkPiqm^TqBCIT801dVB_GBiwpi^0RMApkB09lug#Xt)3o6A(eNLjWSi zAck-s18DpT)Grf5*uelAmjcy|;z;U1V{RaI;z;U1<7*&wa!6v6pmxY1>}3#wi^1K@ z5Cj*4yP4q>=eusBix>1BY7T}MLfU{COk`! zAaw;u=7Hu(AYur;p!pP#-a;hzf#zKxVu)}7&DntT79yDknzI3k6(Q+83XQiSB)7Oi z#2AW@^tM99>=@x;$^a{y>=+T{F09P41I8d z;1BW}Bp)$!LBtsRk=)`17enYh1rZbQM{)}nM2sN-$-k!|Vgdn3c639;7y^*&@P>;a z{L2j$3q-Pm2QG$i%NdB6Kp>JGJrFU5KqNbSpkhHtV!m)OMELc>#SnI!g@_3RA-RPY zBE~QWYA>jrxB!~Q=Rm^%B=!IzCNKwTFGwr_A_f`*0MA>gs4^%Z#2{_~iNVa9i!e_C zX5L4Tc?{;D`PBmntdKJHBgidKu?283P&$REQ-F(s(kVpj0YpsT6Q~bsqYRq5HW_oVD~}9W0hGwXkD0JRRMU}w;7FMEAbs#ZVn2JK} z1&P7JUJRi(0j5_Bp)LWT4jxAdF!S^g?dJszD&Y9w0Et1{zzZ0V#Gq~J1qUEv5+HSu zHZa2i2Z$Jl9h0nb0E04UZHfcK60ms;_Dphcu?0{u2PS#An8Q+tI!7i2xYz@Tn1B=M+jY$qJwg4*T&Lj^PbAYx%JeU;VVh12% z0-gxJCBXdVg>YX2%x~TZ_a(sm=7Vrw0?co5O!CU0Ib2XbWq~WmeS8dYObW`N^$Z}f z2M{rVQYHtL0EPrmm>ytg0jc9LIXrhU+A%30#EyW)1niN-8sK6Gy`VS(>2*L-$8Z#)7nB#^cC>=U z7(jUeCe{E|=Y-J9zyP(w3E@5lP}%_50m>gxy$mpWossmy+y}}tFm*7uxH8ErLd6fDgjLB#|>c?)jdQ;6T(k<@|G!Giz10-*c`QwK^1ATehK zCT|7?W@!cnhClaDfYvfG2skq^BE&ktVhk=wV)Nl*2)*;6dR>v!-RFSlbwd)H4;6Dq z61(pKQRjgqHXkbHi4d!a?*PqzFfe!`+*}iX0xTxr#lXnq&AoV0j4-`_7@&H65O(~5*)bWcj+qq{fb|^=4gdc$Fid7(V)AByik$$9 z2~0((Yk;Ynicr^34^=lE;g*_s4zS-CW`OlV{RS1AiBR_krfwEO-5&<1y4eVIHSr!0 z^X4Gb)i6NC<|5SnfvKB^Q1=I>?ig6i-ocT9p=JR%Tv!>7f&Bp$1BX4Uz;Pt82XHY^ zm_pP&fa*PgQ1@p6RNV=L9e-eUoJ3LwGw&plI+%H<5Mnh8z+u43a2iSM0aWY^LhKJr z-B~0tn7VTav6=D+u%cz|6aX(EA5w-c=-ZFuhli)WPhS!obMHvtIhrZ6xv zGQz|ZT#oH7G#UIWRCW`7kiEN-{7o99YS~aNs|KfCB>~BV0@qEXDv5 z^JQRWl>({LK!}0zkpyUx0Im*_x4>d>^O%_6dRKt;3OF(_GQz|fpyoLuxupTB7bFH( zhol!~F9XzGkUF>+Tra{O4N!GX;4o!o1-ma3;ueq?+`mX-FnbSVK-5h{)(dsZL~y)8 z&4c=55|S7LTnrH|3{bsXpr~Yk=w$%g%Oh}zk&%&sfr*`g;Q_OP)`R~K{xdKfVgzk| zfQqdGiwS&05@UdiA@njp^$IYva4;}{rVQm76kf|SJowKbA;8Sc4j0P?i*X1dt6L2g zlMqB!rwtb4XlGz#h3RF;l4nr(&%n{nz{Ca@dj%GgaAX9jgSeT&`vJ4Ue+C9eMvywF z*lDns06#O5*lVzu1V1y9-fXZKhX7a|#2*Z=A$ACW)j`Fw!D1YO$YRAVCI&ZU#`e2rx2$JPZ}%28%H;F)$(2tp`m;f`fUT?4%0}HZPHdu^<1zGQFu$TlFvN|rX7y}owx-PJo z05`JOE3lXZH?rO=uowpqvbt4ZF##TAby{FC23}-!r@&$YyvXXjz+w!1NMZ_5_wga= zRe-vWA6XsLE&Ryppl%jGRtI&90J1u$n+1`@pzaey)(dqX6O))X1A{WCSyJQR18QF} zF)%X;z{DD0Vk`(T2bdTuLW}_>#)f1b1Jpcrgt`Wp7zaYk0Vc+Y5MzLeaUsMGIQT-` z$BiVG02Sjwh&_O*<3$pKsbgZ23G-%9wv}dJXmQ|W`15~1D3uDq{9EGS!|>(*e~_36 zOsvAehv5fEj2TI90#q*xLTm}lJXRzzm^wCuSPKJGFB=oW4hEJp&pSP*&_!1S^r ziNVydA;cOOpnBO5VPC)iwSyf=odQ%H2SRKCOfM&r7)%`#lN87w*3t|N4i3BwPeA@) zMiNVaim@QX5@70Bk;Gu?*brh43{bu7NMZ_5F%E=S0!$qzk{C=K6O$y!eO921rj8X!45p3^A;!P})ys|~rT`V=K!_>8)Nvw-!PGf0@bJLeB@Vfu zb_5fH0|PfVTuc`x#>)#ATMH3$WI%{9z{L=H8K8O{k?dfA+M&Q8A_Coyx`>pdbTOU4kA=Oh||UCI;23h-?QRM4ci7k~%+_ z7?S(oVn}X*iy_$yHxJ2uP%$M2xZa2as9Tg6;OZh^ZdO64lTd)#p@L8+p#U{cl>u%q z2TZRjLLG;K9>gE22=h2#;iro5F9*ym2@GOl43Mz;@c?RX0wSz_EP&dZfQYvr3*hR+ z#bJ7XfYq@xBrr%wz{SAo*clR$#lT?z5`)M2j|F-VHzy+70anMvkcjL)xEPYXV7=@N zNel?FpKvjR-yTBsCLy`yCs+)m7vYwLV7*KXNl0#42v*0$P=e5VqY~=35`?`sDxqOe zf(XAGieNF2UU<5?p$OIs5`(+%Mj}+K6xj~2z3dF7$mT)aSBeOi8;M|bObn$6H{Vc% zi^0R?MkQD;J3|@5jvYV2_JYLV>UR7DyBQ<~50@Pa!D37dWe7WVEClNXiNXD`;~`Y6 z9N7-ATi6-O5pLcAi;r@I-*&*lz8u*OuwEvHazr@qfW>bG!j2QL_^3drI{}N23WRwl zU}0Z@aLWl;*jFIjasn1_mB@C0-NMdLiL4GBrc4Z#$aa9$fyCh9asn1dmB{V`>t$!C zLWr$^xw#7Az7;U{RUzE60_NW;gj-g?++2ll%L^O_OrIuPpM<#-3oj%I`%9WXnZ z5pM2)xw!>N43@@Q5N_^(<&PF5dtvFm1<8G|yw!qaFDxImBJ7v}i}O~5-WjmCY(>~H z0~VL92)E3DrGr+49W!9*r47jrm_OQ(?0~ti4ap9eKiZJ&fcdu#$qtx5#2Df2CJzm8 zox;o@ju4B0iAf;DGGJno2(b#7m>MIzEN(b(4%FUYW-w-i$7Ksl%!W}2);`UExS4~& z7Fi7J77hkSMtB=;2dvHIh_H7Dtj*=fh^Rwh?Hor&c)N24tR3da2yfTzfVJx!5$@Xo zYb!e<{ITN!IG-~yI3e2st*4!k-3J$ghv^Pj8`BBd4zS-q=E1{i2dqu#gzRRxIwUtk z?FeJ!gtgmu7(&&BF>=A$<2wowVz74mjzWZ9So?m5AzX|b79Tq{LiL6-3d8hjBtX@L zGm62~X~5d2;fz8sw`jop8_p;S>uYGh+P2}0A~5%9B*5(ugt&qOnF!Q#!r02&|B zjNGs|vM4}^!P0?60W=*%GjhS=&B6dK#sfKxk z_aVd(_Cn2zW#od{u>$74SVUe}0rN*JBRq|-fVnT0krQU#3Yb4)5qWC`EL`G{&4aon z4p|*s49O0-7?K@OH^(8n87dZ!+`8*!UZ?JrxfUFnl zz64}D5MuB!Erhx+0oi?UbqK#1LeWfX?>e>EWGJrhGMqaZB3Xe2_@ zP#vNU(15iM>KH{3dZFp6j!^(%2UM&cVV(!fyn2LNJYa6AN4UiU=9UJ8c^=0U@t5!qh27~H=eiBPd7WILc?+JtNeTnz4C4_KR_8R1_In0d_z zw`joHddXu#SaEeJa_U~QEagj+OVZNe5rxM;xaU5rQvKMbJmTg=D>ACG|K8Fq%n zj9l<>3rOB#XIO%y4w45!V(>ikV*}K@B}jTVfYSy$!%~F3Ct&t2MW{Ogvtud3juSAq zEJM-@vtt>OUYH%rko3abw;WOL-+-l;<%ssd4OlyDIU~Gpa0Av}TaKvrZ@|*faz=RH z;0CN6wgOo%I1JbsRv@bbrx%bIyv=X}*5+S<>^`tMCWaNr_JYl0Vpz*40*j9dNM2xP zSj#8|tEVeqd1f7>2rMouAbEkEVI890s(_{Y^@y~V0n@vlQ5=@1GhlXXK%}b-nBEPH z5(stR{L9X;5!pPbKQ0xH3xh)l^CDnja2t_! zmniUq`Wj3Ow;4rX_0|#rxR?;Ej$gt76}y8-&r1~iA$sp1+J8$p;9~GL>k>i@6w?rTxqW2!My>KyjyKadBRO~&Y0O;&276t|e9!7AQWMX*F zC;}H_fr|;j#hBn?{BSWwaCr*SD+m{3f{TfP&hY}z-0sz!+&IT;Bp8QreZQ-49Y5c3=Axw@O%HCiQxmIOc)b` zvK|WqgA7dUJ)^KROdTjppZ^Ex6+wvkG5i6Ef%M9RDeI}|Gq7;vG3k^0fA5kWfg4(h7eHx`0*bk#?KEIgQ`1@P*(y|cbpNft^||^L3&Rh#8No)A@-g? z=uP2(y5%%foen5Wp>~{xssoFG{maB~23Z}{yfet^pyr)Lh>5`5cNU>n1m?bT$YN0Q z&LQiCns*){rUEnXJVLJu%)AT8>Y#crAghDgaS* z_TEBP2etP;Bfk(R4e2m2w7~rPfKdP;294i`2z5O$b&nA0dSK!57@=+oOx+WNx+ySq zPm$F@-S-Sx9n^i#5$fi^%zJ@QHwR|kOJsFW^IjpVgPQjmp{@lM&TkOvT43S)7NM>O zrtTd=T@Os%dqyECSXlxp?;nH95dEMY;YgO@o^7@*<8h-?R33`s9EOc{~g2Ny%K z7pnIdqo5!tU4ha)s4egTTwV!*(-m0EpWzQk>^LJ_tOQiYL&V^EOJI6WAk?LR>TZy_ z69_v}1oR>1orbCdl}#}7PD9m!#rPrW&LE3H^`1f2n-5WU79l1AGw&=yuL#V2=aAJw z^`1jk2esooLY)fCyz>ZkDlqddAghC#cL7-))VzxbbtW+LE+W*Kz|6aZEC$tk30W`H zj;l~Ha2&zK;PDXx3+HPH^IQ;OkhlbuVX!#5&L{#)2jDg#DBf-`iontVxLpSlyNRq0 z>b_gZ>Y#49&nPGYN>`xr3g)*5j6w)8Xu5icP}c)f_Xwe`2NqV35$dME)IC9{n*vk! z6j>eAeb129LEZNpp>7V$ycY;{b71DZL{RMpo{05<}1s2Y45$bwi z>fRyL^}y7_c#Q#g7ouLPAh6P&*bPCL$sN6$7%nV3+;bKT`fr}y83l-yHfQ!k% z+`@w-2D6tJNet9K0=b0`Net#@0VFY47$h^m-Esw{E*TM~S770njPTnPm|Iei^uo+b zLDCD0j}#=mFgK?n#O}b{oQlwU2h{fi`6Cr!#~o0A6(p91Q1=I>E)AjX4?-P0KK{V$ z$Y+p{kbuOSiGv>~j@TLU5qiJC!XO`E#}`-_aR6#Z z0g}1{aCPvs`vn$O1xRjzg=qnjy|C~rM3~3o05z`=q4x;PAB70Fu)zFVh%oO6%pZja z{~m$)w+P7&n461`^upXygrpbdk0KWuJo+5r>OLWuRi#B>f z2as@KW-wzEf|U^uAmIlRgS+nm#J|i87K|dWa^sJK9>{MT43-G7HxA%@&cR@X5c_ig zs?Hi&464o!;pRE8u(xA`ml1OyZee1uV}zGEb71Mfo)MnbroiIJo)KRDO@Wnv_6YN) zz|6Bpm^TGs9z2|x}R(3(UXH2=}qT{OgSHFAL1S&WNyQf%(@N;a?V*e_fE(LEYkl z>=vk-U6AdCtAmFN3#?poL3T4-FFagWVBzA5Fi!>M4_AcyRABCNMVO}o3j^}^#<1Qx%Z2s?OSe)B}Qj|b*HPlWq;VBzA4a0?GC3_KBGzyk{dPlQ`| zU}4~iC}VjbA?KvgKP&h41AE?3>Sl!<2s-*eNdSCAcq0e4qt@(Qef`$Mc9!7^M^0O zjucq9_#)h#0t-K1L|CQ3!paw6Zwf5z{gB0=Zt+951L_YyWcR_b?ME zd*Nd6IM0E_c>uD#&@c!fL$|wRGFJXZBHx1DjVu1N04bgXDfQ3~WqZn+wgaH<& z>B#0m{hN+#FI)`CeNeFsWP720%RsglE{0?;R4fx=uL8^;nFxCoVE)ZSgo^?!T(S`U zP=NU(3*i<8SQum>+@b&rgKT6wp#I24b_-k#?q3C1{g#7lFVr77$o9g;;C)U7SRIrr1Ylv1k8Cg0Z~4gf!o`s6g^Cp*+Y9wu0kR!%F(kJ@#R?Jj8o>Nph_KfH=HEhu ze+^*%Ekf990P}AV!d?TI---}nU;qn)Vq|-v{wPMa11<&+djnWrEkU*e>W>m+JK$pQ z_%MLg6{U=Vu)O5}%hRQd{IIbH2bdkDjKZ)nPzPALDq|Euh(YZrV-!H>g^LLx?0|}u zBkV|k*-?&gO9IR-2 zZv)J~T?jiGVE*kw__qP(-!6pv8esnIMm7)Xw{B#&z{TKWf(@{A--B!~)Neh=_QJ*B z^-%*XJ@+E)T>$e(FT&mhurTOFguwz>81y0RT>$fMAHv=RF#q-;{JQ|=-+p8}pnmH| zwgWB(kKYBb_?>`k2h?v9klg|ogZp;@%)b*6{=ES6??i-KF2MXd31Qv^nBOKL{BZ&1 zkI4wV6JUBLBkY&}vttTE?*y3MDF{0z!0eccFmD6Qyr~HDHo(lAhA?jf%)Ds`^ESZD zn~rG1Z9#~^+hJQ^c1%aK|F*#Fn2u=cZGqV_16d3j&NGnhfQup70gcNU$aX-*W-^Mv z#ali-Glm#E|rY?d4>cjZilSrgt{NjyW(p<{&G#5!7EL`R>io@n&WMFe5^APIpz|5P62!lJYd^8VX#~qkk z<}t$OiezAOC-V_vCXn%ac82)~JHEimu=xl(zQD?e`3O6{!0NpD2sfKR<_Ops79gnu zt>pyu2Nxij2g`#CknDx!tp!NtLFN)b=E418asV7h>R4d*E<~7j1m=&02z!sf z{IL+>z9TSyEJTD03oKj~A(;nr-y$UQVE$NyWFE}Fi;&z0^T#42J7E4;i4e1a#nDQH z9e-f)yAt7+Kd^ML5@GKjSe&m!*lPnzL#vR~!P4IAl!Ea79VR6c8I{@V>7}I6`0>PBkXtr3zy9Z zJD$M8Z!^M_XVl z1G8fnVyvJC=8s*7I;98Z-`xm%ZD8qnH$t5aEN$#Y*kJ?9AG;BD*uc`-Zp7G#4J@tg zMvSZ2!0N``2!GhX^57nXmUF?hXd z1MB1LLk<^kx@Th8hp^WM7WVs){R>wIce4%5Ee8?y_Q1mQAi~W(Fuxr{nAZafzk`VI z>w$&eL4^ByVDWYk;olxu934csxd#@ehY|M5z|zYRBr%xZjv|S{(#tVM5%Ah5(0VS= zT6<7kc8pP27_^28EXEI-7iVHPju0yWt>*`+JC4v>0@Hf}A(jGK8xK-<0--lWK_6n? zNrXQ_VE#CX2-6T)n4Uz0RR}DsP9nl81Qu2&5#byH3+Iyv|AxTg<0K+XLttTg3fT^5 zoS#BA4=x5z2O+R@a0=PY(DZi-*?n-m@G;~NSR9=~4g;v()6nn(twn@|>1k;AfyJQl zaRylo8m4EE_2xsu`7AQrEMTtF6s z>b-!h7iz~vgqR7;yo(6ECNT3ZA&WuHyM(M4YTji;n7Y8y)n!Edy1>%VWkfn~fu)1X zhrK`(`_;rD$$;*gzY#dWA*+Mhd!JEQ3{>WT)@{Pl!2?DSgqS}hJwHUK z>w&3zgizN5OD~TR>ZZWdJwd3O0#o-CSsm1U&ydwY-S-@!ZVt@67YKE8VCKCjk%w4a$6z9RC6 z1wt>pOtgUXIYH{+ZA=SD-xMSUug@(Y?P8D^Jl$JB+O|v#-w^gz!0i2oa9;(?ecupy zx&omWZf^z5-fxI}Spjq3H-tYbVE*`q$mbO>_kBl*Ng%}Fc1XbN_>ORk1k5ep5q3zx z?D&pwiv-Lq-w}S3fcfn^A`B#8VekXtmI#K)5*q z=H?#=dm|9`!u=Zo^Y2fD9U3q@ej@a0!1Vq^*r5Tl<0qp0(?FO9PrDj0fBZ!FR|DqX zp9p_w!2IzGVMhkcj$a7988E%S5Mh-8v*Q=SybOeS@bsJk^V=_k-!fo+`-SjF2FxGF z7{$P49jGjJ@MrjQ;6JF%1s5xUiJd^GOL54Ds5=c61GNue>dqjGLDii_h>5_|okJFb zsymMmQ-P_wfGh@8cM&0G0#kPhSq!S~DpU;YH>lV(s2HeDf%yZp2Sy6Iew-jW@v%%pU!kn{x0nfPM;ybE18^~@9UygjFm+J(#W5UdfU5fhN|P`< z@)%k`c4&aa1e8@&)fgBU&VkMvXJ*hu5>tSR>4EZ~2t=I&R7@L`PHmM{RJj-!8qR^v zIc8=MU}m-gZR=xTkY`{hlxJx8&%hzT%z_a62o?jKMU4NSop!1*MVjsa`;Pap1VufHa4h{w;F9rrC zMFtQMU|?XF&%nTmEH(imHkk>0<~L}+t_(vkXg@In!xV&=4NPn*6BFoMage$ihs$7f z0@D!cWEh0OVhqy}Vm2_b8OVAkgVhNLGcYmPLc;G4$UM-w@xly@jCK&Q8j!sQ{xdL$ zAd3lu$`X(mlHSQ+F@bglMpp&~7AJ5zD3S-AL(lP%5hTXs1Ud_y!RP@q$h>w2CWN|A zkU0Oy2oi&;+w_3B;Xi|b4g(VtlPwbqI~N1PfytnB3KC;vWQ2+}2!q8KL?P}=No8PQ zXb=XaNd^W{h~L0s2PT8X1h^QO8C@BeKn`SJ5CWag%D@0R#~LnH1Qz4qK~`r37GvN= z77K!i2|?^-Ndm=hFiZ>*F3F(t^e=ihl|z2#a_V0_QS#a_Y1)>MZm0;@D!^Q4H?PXxt z02i}|tJ??{i-(JCLWrqA%;RR*3>TXZ7uy0CyAKyT2p60Gf&-ck4#CCb;bLzPVudhu zZxLdpFtOhVv38i)AB0#lOpKiw7N+uWbsPvWxH?XRSUV5YeOw5!W|$Z^Ladz+s*VRC z)(jK-$Kc2SDp4316O2!o?Ec>X;B>aCOXZu?28-EC?~UI##&Y1GqXi zgcw|1FoO*&zbP1XLOsTxDSR z@SlMpl);&afk6ZmfD8gqF(ZZ$4+aJyd5}7W5CH~;{|ro%m|$W83@|Zc21XAC24;vl z69%w4V+JOK*cPyukO{KbR+t!)UQ@6blP-fh0|SE`*jfgVEB`Ps>LH6w0iQ6!Xb4dO zx($dq{u;PGXN`l4Jz$;>75fAi`_Bzg$Hn>?A;u3A`-2eUhUn#D{fiLehl%MkfYKTZ zSVsPu{Gb2-8CVUF#O$GBhDc)ZP_b`tF?kM%UM|+}2r(X**e`?_2gE!s*53#*9+=n{ z1|}8;1{RQmIOMN`+QnR~UlC$FFtHy9F%EmEx}OL!9+;RZ1CyO61GAC>$aiK83=H)Q zOlHVp<`6Mr<7htOF0}*ue}LS_CNLjykJy3zJHTQL3y{SuAYu!V#VR0Ti@^69f$s-n zP}l()D`jO^1iljqD)s{`Ca@SuYyn&hem54w0;t|4NaiKL#X$EYLCi~l>RpPY?g3QY zQY1SbK-DcnhzTgb#o+b|z}&nXVV(fYEz6Pg!rZ(9Net$e6-atvZeEEb26Nv^B)u^A ztwN|%fVpKALY)H4&8v~bU~XBBq!;GqHArGGx2!?Z3v=^YBr%v<)*|VJxp^HzodL`( z>k#S;U~XQIBnETKdL+FtH*Y`^gSlk`l3tjbHzJ9_+_Di#FU-xG5b7LYZrOxT=Kyo_ zW+X9~TQ(!P_ah{F&CKF zV}w`>Ow62t$&Z17S%!gufg|Au0}seva|T9)*bcB5gE<4EF9QQJ=n6p=2ZWdp0|PVY z`avFq7!yJaZXOdtFI3C|$qogmc@_)^bqsKI2=^(##TemsFd+0I#1QJ>_QKRzG9dIi zSU~({iR?Fo7$OXyVpd4%7!YCzdl6!Ay$Vn~%nh!R>{K*&_Lk0jkaxNiUKZ!hKM6cF697hzZysx#a;wjKLmR9VF}pIw0*0(6x*V zuyoJ?X}>_kpz+a(qz)Dzok;3nao&Zb4i-nR@5j zha?6ImwqI%15p3=Bbx^i6PSQ31`PvN&=t81%wYc}+yuoNj{qA&j6(q`#*QSm04m0T zBnH#Vi6r&_s*W2X2D&bb0Vc+SBnC5&7fB3e?|dfky~AMlIm`sPkAY!6sJRApvjf-; z27v`gVhnIGgkA=y-i65KNkYt9ge1lQ6N$dbr?@}bUG(f}z zmLZEl^a?CP)(a71SdOd?;${IpW;@W`%iu6*fTqbV&=soCG7MC{EcnkQ&;`*e&cMLH z0u$>-5?k56A8X#hz@&)8yuz3d{VxaN`F6K}PG0zs+JgAr*vUw0OPj zggOS8Iwgc13@~-d2z5L#b;<~J958h%2z4wlbt(vTEHHJd2z4AVb=SasVz56L4ubu` zC2$=f#sU+&fe_<>iQPnq@xa9HA;bh=V)qeZA~3NB2r&tm*h7Sv3`}e;WNr+6H!njJ z_#R${xlG`&hlt$*iwVp_7W)MjlbDCBw+bxA0h$A1gxv9}a6k&wcLq%@fi#2fcvUzs z3oIr8npcCWQ-P@i&A&n0Ybr2xpt&}vIt`dQ5zsss#10LZI?((URId&~40Q1@*j^o& zUNO*p(Ga~H2r;<(IAD6k5$bqg>ckQD^1#%|A;fANW<&fYk0f>gD)x?ni3v1M%Fe)G z0MW}O@Sg$RwiSSg@dz+6GQrxrA}}##MkW@hUIv&L3$oZQki9$-e2j4aIzZga!oZIZ zbAgEoAjCXiVuFl}jL`7&f!M(!AcRmC08=N75DS5ci6F!xU}B;O^I~A;&18ayGXn!O z9n55cyP1IjnqFohs{{LuL1GrNIxCQW88~Jmi$#IO7-l2uy#*E%n1d|#3oIrv2U%|w zSd2r9fyvG(gvC%;kb%SDmjI~EFQLW2h!Cp+i*aZ%FfuxYu&{$}WpRLuF)_i#pnA2D z&D#amE1`{So)uV(LmSyVxEPXoP`zrPbQQwH!Va3pp9O9+2&jS5DNIZXEXJUY5Myb8 zi!m`VLDaD{K=o=Mn|BMWS3m=ym!TmFEXJUT5Mx1zA(;o&D*;l+$i%|V#=yWJ4VjCU z0NKF=6`Ktf6OcrxYk;YfM5t?EfU1*XU}9v1>Q#V>Nh8D>U}7=|F@^UVTF2=+I6H7zrg{gB;fUDzy zsdGqxiX|Z2ascL*1O{%H-UBeb2@G((2Vi;=5qcdSg3V)RNJQv$Py~xHG9)7OIwV5H zk`Q_i!1N{|)Ez*mL%0QIUJh6tIr%>i{xfpqfX#!5JphZbbL4>C0ufUHi!pNK z!u1L$!1U(A)d?sd)Pdp%q*p)zW?nG^4=mmeJOcZJouQb48z$y}5aWV}pE6t>4_r(M zEXD}Z3y+T^xEN?<6S$3ZAQ>#i&QQXDNE=De_$^`JhNl-LxEL2ay};a3f|Q0}_Lea4 zz}3O*EoDIHeGIj?6v^IXs2!z9dLiy(WGF?l1L9w>7~FlzP`zagjIgj`_yM(}jDZOj zE({h3bqF!AI!1;v21Zy|F;u|C5b3@Gs<#};j-Oz4p!-r0dMm+Vj11*S`N$G3hH#4| z+&qLGl~Az?1}3;ao`A*J87deM>QcaBj0_b>cBnw@s6g^Z3PKEF9#{-)9y|k}9MyfR!axNa;WUYF;&xn-dXYa5pO=#Ngrg5G)3|YZXyW z!pelxj6%&4(?_RusX0_ zcsOT3#cGl4(1hx(MRIc{Tphx1ng}s?7`z0Ff$nof#8D>PJVe@k2^M2#s6+Da2e=p_ zuYQ1XGa% zgql~6l&%aBV(>8d2o?jI2e-EnYF-1lt^k*@4$q+K8o>1eL@W&~#>mhBt`{I;u)4Mp zq4&UZusU{zMufTpuzI=?VcvmsusTMDCWJZ%Sbl3lsB?hjw&j3o91Y#uv9 zGm?3*@}(KcJXrbCf)G1^5JS|fFug4ZI}X6?Xhn!Q!2H{aWG~FWtq40DVE%1G=sf`Q zM;k)#0azHcA@m-Ag@F_!$bHHxpg9MPI8b|tnL!?LABzM`ObH>T0TVN4gx9|gkUENk zVKvx1a9sXa2sV$AVKpPXP4nX+Tntq2L)85Qi-Fr_HVh0*#taM$0ts>tkKdax+xy0a%QkArIs?s8|A6jFBM&B*p{j*E-09`n4c2Zf;o*Up*8npw6XZUKc?~f0vXJae0Gr3ikcCjkpa2&`*!uu1#?Fw9 SWG_MtVK2