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Fix register width test for risc-v, and improve operand slot type inference for risc-v

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This commit is contained in:
gingerBill
2026-08-21 00:38:34 +01:00
parent 09204e8982
commit de8c0dc4fe
5 changed files with 54 additions and 14 deletions
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10
core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -260,8 +260,8 @@ main :: proc() {
AliasSrc_ARG0, // user's 1st operand
AliasSrc_ARG1, // user's 2nd operand
AliasSrc_ARG2, // user's 3rd operand
AliasSrc_X0, // hardwired zero (x0)
AliasSrc_X1, // link register (ra / x1)
AliasSrc_ZERO, // hardwired zero (x0)
AliasSrc_LINK, // link register (ra / x1)
AliasSrc_LIT, // the `lit` field below (immediate literal)
AliasSrc_CSR_LIT, // the `csr` field below (fixed 12-bit CSR address)
};
@@ -425,7 +425,7 @@ main :: proc() {
string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m);
}
string_map_init(&mnemonic_map, PSEUDO_MNEMONIC_COUNT*2);
string_map_init(&pseudo_mnemonic_map, PSEUDO_MNEMONIC_COUNT*2);
for (u16 m = PM_INVALID+1; m < PSEUDO_MNEMONIC_COUNT; m++) {
string_map_set(&pseudo_mnemonic_map, pseudo_mnemonic_strings[m], cast(PseudoMnemonic)m);
}
@@ -484,6 +484,10 @@ main :: proc() {
}
return 0;
}
bool integer_reg_width_is_exact() const {
return false;
}
""")
strings.write_string(&sb, "\n\n")

12
core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -341,7 +341,13 @@ main :: proc() {
strings.write_string(&sb, "\n");
strings.write_string(&sb, """
enum AliasSrc : u8 {
AliasSrc_NONE, // slot unused
AliasSrc_NONE, // slot unused
AliasSrc_ARG0, // user's 1st operand
AliasSrc_ARG1, // user's 2nd operand
AliasSrc_ARG2, // user's 3rd operand
AliasSrc_ZERO, // hardwired zero
AliasSrc_LINK, // link register
AliasSrc_LIT,
};
struct PseudoAlias {
@@ -520,6 +526,10 @@ main :: proc() {
}
return 0;
}
bool integer_reg_width_is_exact() const {
return true;
}
""")
strings.write_string(&sb, "\n\n")