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asm named slots

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kalsprite
2026-08-23 21:34:31 -07:00
parent 965970af71
commit deb45f3e6a
8 changed files with 162 additions and 2 deletions
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16
core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -663,6 +663,22 @@ main :: proc() {
""")
strings.write_string(&sb, "\n\n")
strings.write_string(&sb, """
// RISC-V has no slot that only one named hardware register can fill.
u16 operand_type_named_reg_class(OperandType t) const {
gb_unused(t);
return REG_CLASS_NONE;
}
String named_reg_class_string(u16 reg_class) const {
gb_unused(reg_class);
return str_lit("hardware");
}
""")
strings.write_string(&sb, "\n\n")
strings.write_string(&sb, """

30
core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -682,6 +682,36 @@ main :: proc() {
""")
strings.write_string(&sb, "\n\n")
strings.write_string(&sb, """
// Slots only a specific named hardware register can fill. They carry no GPR/vector
// class and, apart from OP_MM, no width either. Nothing else in the size/class
// check constrains them and a template parameter would otherwise slip through.
u16 operand_type_named_reg_class(OperandType t) const {
switch (t) {
case OP_SREG: return REG_CLASS_SEG;
case OP_CR: return REG_CLASS_CR;
case OP_DR: return REG_CLASS_DR;
case OP_STI: return REG_CLASS_ST;
case OP_MM: return REG_CLASS_MM;
}
return REG_CLASS_NONE;
}
String named_reg_class_string(u16 reg_class) const {
switch (reg_class) {
case REG_CLASS_SEG: return str_lit("segment");
case REG_CLASS_CR: return str_lit("control");
case REG_CLASS_DR: return str_lit("debug");
case REG_CLASS_ST: return str_lit("x87 stack");
case REG_CLASS_MM: return str_lit("MMX");
}
return str_lit("hardware");
}
""")
strings.write_string(&sb, "\n\n")
strings.write_string(&sb, """