diff --git a/core/rexcode/mips/decoder.odin b/core/rexcode/mips/decoder.odin index 254256d04..48b8b4b9e 100644 --- a/core/rexcode/mips/decoder.odin +++ b/core/rexcode/mips/decoder.odin @@ -267,6 +267,18 @@ extract_operand_inline :: #force_inline proc "contextless" ( if rel26 & (1 << 25) != 0 { rel26 |= ~i32(0x3FFFFFF) } target := u32(i32(pc) + 4 + (rel26 << 2)) return Operand{relative = i64(target), kind = .RELATIVE, size = 4} + case .BRANCH_19: + // R6 PC-relative load: relative to this instruction (no +4), << 2. + rel19 := i32(word & 0x7FFFF) + if rel19 & (1 << 18) != 0 { rel19 |= ~i32(0x7FFFF) } + target := u32(i32(pc) + (rel19 << 2)) + return Operand{relative = i64(target), kind = .RELATIVE, size = 4} + case .BRANCH_18: + // LDPC: relative to this instruction aligned down to 8, << 3. + rel18 := i32(word & 0x3FFFF) + if rel18 & (1 << 17) != 0 { rel18 |= ~i32(0x3FFFF) } + target := u32((i32(pc) &~ i32(7)) + (rel18 << 3)) + return Operand{relative = i64(target), kind = .RELATIVE, size = 4} // Misc small immediates ------------------------------------------------- case .FCC_BC: diff --git a/core/rexcode/mips/encoder.odin b/core/rexcode/mips/encoder.odin index 7c98ff30f..ca38f3641 100644 --- a/core/rexcode/mips/encoder.odin +++ b/core/rexcode/mips/encoder.odin @@ -225,7 +225,7 @@ operand_matches_inline :: #force_inline proc "contextless" ( case .IMM5, .IMM16S, .IMM16U, .IMM20, .IMM26, .SEL, .FCC, .GTE_SF, .GTE_MX, .GTE_V, .GTE_CV, .GTE_LM: return op.kind == .IMMEDIATE - case .REL16, .REL21, .REL26, .REL_J26: + case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18: return op.kind == .RELATIVE case .MEM: return op.kind == .MEMORY @@ -310,6 +310,18 @@ pack_operand_inline :: #force_inline proc( type = .REL26, size = 4, inst_idx = inst_idx, }) return 0 + case .BRANCH_19: + append(relocs, Relocation{ + offset = pc, label_id = u32(op.relative), + type = .REL_PC19, size = 4, inst_idx = inst_idx, + }) + return 0 + case .BRANCH_18: + append(relocs, Relocation{ + offset = pc, label_id = u32(op.relative), + type = .REL_PC18, size = 4, inst_idx = inst_idx, + }) + return 0 // FP condition-code field (BC1*, MOVF/MOVT, C.cond.fmt). case .FCC_BC: @@ -492,6 +504,36 @@ resolve_relocation_inline :: #force_inline proc( } word = (word &~ 0x3FFFFFF) | (u32(rel) & 0x3FFFFFF) + case .REL_PC19: + // R6 PC-relative load: offset is relative to the instruction's own + // address (no delay-slot adjustment), scaled by 4, 19-bit signed. + rel := i32(target) - i32(relocation.offset) + if rel & 3 != 0 { + append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + rel >>= 2 + if rel < -(1<<18) || rel > (1<<18)-1 { + append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + word = (word &~ 0x7FFFF) | (u32(rel) & 0x7FFFF) + + case .REL_PC18: + // LDPC: relative to the instruction's address aligned down to 8, scaled + // by 8, 18-bit signed. + rel := i32(target) - (i32(relocation.offset) &~ i32(7)) + if rel & 7 != 0 { + append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + rel >>= 3 + if rel < -(1<<17) || rel > (1<<17)-1 { + append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + word = (word &~ 0x3FFFF) | (u32(rel) & 0x3FFFF) + case .J26: // J/JAL: target = ((PC+4)[31:28] << 28) | (encoded_field << 2) if target & 3 != 0 { diff --git a/core/rexcode/mips/encoding_types.odin b/core/rexcode/mips/encoding_types.odin index ce2954acc..ad9515987 100644 --- a/core/rexcode/mips/encoding_types.odin +++ b/core/rexcode/mips/encoding_types.odin @@ -125,6 +125,8 @@ Operand_Type :: enum u8 { REL_J26, // 26-bit region jump (J / JAL) REL21, // R6 21-bit compact branch (BC1EQZ/NEZ) REL26, // R6 26-bit compact branch (BC/BALC) + REL19, // R6 PC-relative load (LWPC/LWUPC, 19-bit << 2) + REL18, // R6 PC-relative load (LDPC, 18-bit << 3) // Memory: base GPR + 16-bit signed displacement MEM, @@ -164,6 +166,8 @@ Operand_Encoding :: enum u8 { BRANCH_16, // bits 15-0 as PC-relative word offset (delay-slot adjusted) BRANCH_21, // R6 compact branch: bits 20-0 BRANCH_26, // R6 compact branch: bits 25-0 + BRANCH_19, // R6 PC-relative load: bits 18-0 (LWPC/LWUPC) + BRANCH_18, // R6 PC-relative load: bits 17-0 (LDPC) // FP condition code FCC_BC, // bits 20-18 (FP branches, MOVF/MOVT) diff --git a/core/rexcode/mips/mnemonic_builders.odin b/core/rexcode/mips/mnemonic_builders.odin index df72e74af..a65cd6cc7 100644 --- a/core/rexcode/mips/mnemonic_builders.odin +++ b/core/rexcode/mips/mnemonic_builders.odin @@ -412,6 +412,12 @@ inst_lsa_r_r_r_i5 :: #force_inline proc "contextless" (dst: GPR, src: G emit_lsa_r_r_r_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) { append(instructions, inst_lsa_r_r_r_i5(dst, src, src2, imm)) } inst_dlsa_r_r_r_i5 :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR, imm: i64) -> Instruction { return Instruction{mnemonic = .DLSA, operand_count = 4, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), op_imm(imm, 1)}} } emit_dlsa_r_r_r_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) { append(instructions, inst_dlsa_r_r_r_i5(dst, src, src2, imm)) } +inst_lwpc_r_rel :: #force_inline proc "contextless" (dst: GPR, target: u32) -> Instruction { return Instruction{mnemonic = .LWPC, operand_count = 2, length = 4, ops = {op_gpr(dst), op_label(target), {}, {}}} } +emit_lwpc_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) { append(instructions, inst_lwpc_r_rel(dst, target)) } +inst_lwupc_r_rel :: #force_inline proc "contextless" (dst: GPR, target: u32) -> Instruction { return Instruction{mnemonic = .LWUPC, operand_count = 2, length = 4, ops = {op_gpr(dst), op_label(target), {}, {}}} } +emit_lwupc_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) { append(instructions, inst_lwupc_r_rel(dst, target)) } +inst_ldpc_r_rel :: #force_inline proc "contextless" (dst: GPR, target: u32) -> Instruction { return Instruction{mnemonic = .LDPC, operand_count = 2, length = 4, ops = {op_gpr(dst), op_label(target), {}, {}}} } +emit_ldpc_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) { append(instructions, inst_ldpc_r_rel(dst, target)) } inst_seleqz_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .SELEQZ, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_seleqz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_seleqz_r_r_r(dst, src, src2)) } inst_selnez_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .SELNEZ, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } @@ -2427,6 +2433,12 @@ inst_lsa :: inst_lsa_r_r_r_i5 emit_lsa :: emit_lsa_r_r_r_i5 inst_dlsa :: inst_dlsa_r_r_r_i5 emit_dlsa :: emit_dlsa_r_r_r_i5 +inst_lwpc :: inst_lwpc_r_rel +emit_lwpc :: emit_lwpc_r_rel +inst_lwupc :: inst_lwupc_r_rel +emit_lwupc :: emit_lwupc_r_rel +inst_ldpc :: inst_ldpc_r_rel +emit_ldpc :: emit_ldpc_r_rel inst_seleqz :: inst_seleqz_r_r_r emit_seleqz :: emit_seleqz_r_r_r inst_selnez :: inst_selnez_r_r_r diff --git a/core/rexcode/mips/reloc.odin b/core/rexcode/mips/reloc.odin index b408e779a..ac8a4eac3 100644 --- a/core/rexcode/mips/reloc.odin +++ b/core/rexcode/mips/reloc.odin @@ -17,6 +17,8 @@ Relocation_Type :: enum u8 { REL16, // 16-bit signed PC-rel branch offset (BEQ/BNE/BLEZ/BGTZ/...) REL21, // 21-bit signed PC-rel compact branch (R6 BEQZC/BNEZC) REL26, // 26-bit signed PC-rel compact branch (R6 BC/BALC) + REL_PC19, // 19-bit R6 PC-relative load offset ((target - PC) >> 2) (LWPC/LWUPC) + REL_PC18, // 18-bit R6 PC-relative load offset ((target - (PC & ~7)) >> 3) (LDPC) J26, // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF) HI16, // upper 16 of 32-bit absolute (LUI rt, %hi(sym)+0x8000 if LO16 paired) LO16, // lower 16 of 32-bit absolute (ADDIU rt, rt, %lo(sym)) diff --git a/core/rexcode/mips/tablegen/encoding_table.odin b/core/rexcode/mips/tablegen/encoding_table.odin index 226b7b910..94508f1c3 100644 --- a/core/rexcode/mips/tablegen/encoding_table.odin +++ b/core/rexcode/mips/tablegen/encoding_table.odin @@ -1680,5 +1680,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .BNZ_W = { {.BNZ_W, {.MSA_VEC,.REL16,.NONE,.NONE}, {.WT,.BRANCH_16,.NONE,.NONE}, 0x47C00000, 0xFFE00000, .MSA, {}} }, .BNZ_D = { {.BNZ_D, {.MSA_VEC,.REL16,.NONE,.NONE}, {.WT,.BRANCH_16,.NONE,.NONE}, 0x47E00000, 0xFFE00000, .MSA, {}} }, .BNZ_V = { {.BNZ_V, {.MSA_VEC,.REL16,.NONE,.NONE}, {.WT,.BRANCH_16,.NONE,.NONE}, 0x45E00000, 0xFFE00000, .MSA, {}} }, + .LWPC = { {.LWPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC080000, 0xFC180000, .MIPS32_R6, {}} }, + .LWUPC = { {.LWUPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC100000, 0xFC180000, .MIPS64_R6, {}} }, + .LDPC = { {.LDPC, {.GPR,.REL18,.NONE,.NONE}, {.RS,.BRANCH_18,.NONE,.NONE}, 0xEC180000, 0xFC1C0000, .MIPS64_R6, {}} }, // SPECGEN:END } diff --git a/core/rexcode/mips/tablegen/generated/decode_tables.odin b/core/rexcode/mips/tablegen/generated/decode_tables.odin index 4f4fd8775..7f4c0a5c7 100644 --- a/core/rexcode/mips/tablegen/generated/decode_tables.odin +++ b/core/rexcode/mips/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_mips_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1005]lib.Decode_Entry{ +DECODE_ENTRIES := [1008]lib.Decode_Entry{ { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000000, 0xFFFFFFFF, .MIPS_I, {} }, { .SSNOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000040, 0xFFFFFFFF, .MIPS32_R1, {} }, { .EHB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x000000C0, 0xFFFFFFFF, .MIPS32_R2, {} }, @@ -975,6 +975,9 @@ DECODE_ENTRIES := [1005]lib.Decode_Entry{ { .SV_S, {.VFPU_S,.MEM,.NONE,.NONE}, {.VFPU_VT_MEM,.VFPU_OFFSET_BASE,.NONE,.NONE}, 0xE8000000, 0xFC000000, .VFPU_PSP, {} }, { .AUIPC, {.GPR,.IMM16S,.NONE,.NONE}, {.RS,.IMM_16,.NONE,.NONE}, 0xEC1E0000, 0xFC1F0000, .MIPS32_R6, {} }, { .ALUIPC, {.GPR,.IMM16S,.NONE,.NONE}, {.RS,.IMM_16,.NONE,.NONE}, 0xEC1F0000, 0xFC1F0000, .MIPS32_R6, {} }, + { .LDPC, {.GPR,.REL18,.NONE,.NONE}, {.RS,.BRANCH_18,.NONE,.NONE}, 0xEC180000, 0xFC1C0000, .MIPS64_R6, {} }, + { .LWPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC080000, 0xFC180000, .MIPS32_R6, {} }, + { .LWUPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC100000, 0xFC180000, .MIPS64_R6, {} }, { .VMIDT_P, {.VFPU_M_P,.NONE,.NONE,.NONE}, {.VFPU_VD,.NONE,.NONE,.NONE}, 0xF3830080, 0xFFFFFF80, .VFPU_PSP, {} }, { .VMIDT_T, {.VFPU_M_T,.NONE,.NONE,.NONE}, {.VFPU_VD,.NONE,.NONE,.NONE}, 0xF3838000, 0xFFFFFF80, .VFPU_PSP, {} }, { .VMIDT_Q, {.VFPU_M_Q,.NONE,.NONE,.NONE}, {.VFPU_VD,.NONE,.NONE,.NONE}, 0xF3838080, 0xFFFFFF80, .VFPU_PSP, {} }, @@ -1077,11 +1080,11 @@ DECODE_INDEX_PRIMARY := [64]lib.Decode_Index{ 0x38 = { 959, 1}, 0x39 = { 960, 1}, 0x3A = { 961, 3}, - 0x3B = { 964, 2}, - 0x3C = { 966, 27}, - 0x3D = { 993, 3}, - 0x3E = { 996, 5}, - 0x3F = {1001, 4}, + 0x3B = { 964, 5}, + 0x3C = { 969, 27}, + 0x3D = { 996, 3}, + 0x3E = { 999, 5}, + 0x3F = {1004, 4}, } @(rodata) diff --git a/core/rexcode/mips/tablegen/generated/encode_tables.odin b/core/rexcode/mips/tablegen/generated/encode_tables.odin index ae8bf4633..ae27c1221 100644 --- a/core/rexcode/mips/tablegen/generated/encode_tables.odin +++ b/core/rexcode/mips/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_mips_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1005]lib.Encoding{ +ENCODE_FORMS := [1008]lib.Encoding{ // .ADD { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000020, 0xFC0007FF, .MIPS_I, {} }, // .ADDU @@ -393,6 +393,12 @@ ENCODE_FORMS := [1005]lib.Encoding{ { .LSA, {.GPR,.GPR,.GPR,.IMM5}, {.RD,.RS,.RT,.IMM_5}, 0x00000005, 0xFC00071F, .MIPS32_R6, {} }, // .DLSA { .DLSA, {.GPR,.GPR,.GPR,.IMM5}, {.RD,.RS,.RT,.IMM_5}, 0x00000015, 0xFC00071F, .MIPS64_R6, {only_64=true} }, + // .LWPC + { .LWPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC080000, 0xFC180000, .MIPS32_R6, {} }, + // .LWUPC + { .LWUPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC100000, 0xFC180000, .MIPS64_R6, {} }, + // .LDPC + { .LDPC, {.GPR,.REL18,.NONE,.NONE}, {.RS,.BRANCH_18,.NONE,.NONE}, 0xEC180000, 0xFC1C0000, .MIPS64_R6, {} }, // .SELEQZ { .SELEQZ, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000035, 0xFC0007FF, .MIPS32_R6, {} }, // .SELNEZ @@ -2228,827 +2234,827 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .DBITSWAP = { 189, 1}, .LSA = { 190, 1}, .DLSA = { 191, 1}, - .LWPC = { 192, 0}, - .LWUPC = { 192, 0}, - .LDPC = { 192, 0}, - .SELEQZ = { 192, 1}, - .SELNEZ = { 193, 1}, - .CRC32B = { 194, 1}, - .CRC32H = { 195, 1}, - .CRC32W = { 196, 1}, - .CRC32D = { 197, 1}, - .CRC32CB = { 198, 1}, - .CRC32CH = { 199, 1}, - .CRC32CW = { 200, 1}, - .CRC32CD = { 201, 1}, - .SIGRIE = { 202, 1}, - .MFC1 = { 203, 1}, - .MTC1 = { 204, 1}, - .DMFC1 = { 205, 1}, - .DMTC1 = { 206, 1}, - .CFC1 = { 207, 1}, - .CTC1 = { 208, 1}, - .MFHC1 = { 209, 1}, - .MTHC1 = { 210, 1}, - .LWC1 = { 211, 1}, - .SWC1 = { 212, 1}, - .LDC1 = { 213, 1}, - .SDC1 = { 214, 1}, - .ADD_S = { 215, 1}, - .ADD_D = { 216, 1}, - .ADD_PS = { 217, 1}, - .SUB_S = { 218, 1}, - .SUB_D = { 219, 1}, - .SUB_PS = { 220, 1}, - .MUL_S = { 221, 1}, - .MUL_D = { 222, 1}, - .MUL_PS = { 223, 1}, - .DIV_S = { 224, 1}, - .DIV_D = { 225, 1}, - .SQRT_S = { 226, 1}, - .SQRT_D = { 227, 1}, - .ABS_S = { 228, 1}, - .ABS_D = { 229, 1}, - .ABS_PS = { 230, 1}, - .NEG_S = { 231, 1}, - .NEG_D = { 232, 1}, - .NEG_PS = { 233, 1}, - .MOV_S = { 234, 1}, - .MOV_D = { 235, 1}, - .MOV_PS = { 236, 1}, - .RECIP_S = { 237, 1}, - .RECIP_D = { 238, 1}, - .RSQRT_S = { 239, 1}, - .RSQRT_D = { 240, 1}, - .MADD_S = { 241, 1}, - .MADD_D = { 242, 1}, - .MADD_PS = { 243, 1}, - .MSUB_S = { 244, 1}, - .MSUB_D = { 245, 1}, - .MSUB_PS = { 246, 1}, - .NMADD_S = { 247, 1}, - .NMADD_D = { 248, 1}, - .NMADD_PS = { 249, 1}, - .NMSUB_S = { 250, 1}, - .NMSUB_D = { 251, 1}, - .NMSUB_PS = { 252, 1}, - .MOVN_S = { 253, 1}, - .MOVN_D = { 254, 1}, - .MOVN_PS = { 255, 1}, - .MOVZ_S = { 256, 1}, - .MOVZ_D = { 257, 1}, - .MOVZ_PS = { 258, 1}, - .MOVF_S = { 259, 1}, - .MOVF_D = { 260, 1}, - .MOVF_PS = { 261, 1}, - .MOVT_S = { 262, 1}, - .MOVT_D = { 263, 1}, - .MOVT_PS = { 264, 1}, - .CVT_S_D = { 265, 1}, - .CVT_S_W = { 266, 1}, - .CVT_S_L = { 267, 1}, - .CVT_D_S = { 268, 1}, - .CVT_D_W = { 269, 1}, - .CVT_D_L = { 270, 1}, - .CVT_W_S = { 271, 1}, - .CVT_W_D = { 272, 1}, - .CVT_L_S = { 273, 1}, - .CVT_L_D = { 274, 1}, - .CVT_PS_S = { 275, 1}, - .CVT_S_PU = { 276, 1}, - .CVT_S_PL = { 277, 1}, - .PLL_PS = { 278, 1}, - .PLU_PS = { 279, 1}, - .PUL_PS = { 280, 1}, - .PUU_PS = { 281, 1}, - .ROUND_W_S = { 282, 1}, - .ROUND_W_D = { 283, 1}, - .ROUND_L_S = { 284, 1}, - .ROUND_L_D = { 285, 1}, - .TRUNC_W_S = { 286, 1}, - .TRUNC_W_D = { 287, 1}, - .TRUNC_L_S = { 288, 1}, - .TRUNC_L_D = { 289, 1}, - .CEIL_W_S = { 290, 1}, - .CEIL_W_D = { 291, 1}, - .CEIL_L_S = { 292, 1}, - .CEIL_L_D = { 293, 1}, - .FLOOR_W_S = { 294, 1}, - .FLOOR_W_D = { 295, 1}, - .FLOOR_L_S = { 296, 1}, - .FLOOR_L_D = { 297, 1}, - .C_F_S = { 298, 1}, - .C_F_D = { 299, 1}, - .C_F_PS = { 300, 1}, - .C_UN_S = { 301, 1}, - .C_UN_D = { 302, 1}, - .C_UN_PS = { 303, 1}, - .C_EQ_S = { 304, 1}, - .C_EQ_D = { 305, 1}, - .C_EQ_PS = { 306, 1}, - .C_UEQ_S = { 307, 1}, - .C_UEQ_D = { 308, 1}, - .C_UEQ_PS = { 309, 1}, - .C_OLT_S = { 310, 1}, - .C_OLT_D = { 311, 1}, - .C_OLT_PS = { 312, 1}, - .C_ULT_S = { 313, 1}, - .C_ULT_D = { 314, 1}, - .C_ULT_PS = { 315, 1}, - .C_OLE_S = { 316, 1}, - .C_OLE_D = { 317, 1}, - .C_OLE_PS = { 318, 1}, - .C_ULE_S = { 319, 1}, - .C_ULE_D = { 320, 1}, - .C_ULE_PS = { 321, 1}, - .C_SF_S = { 322, 1}, - .C_SF_D = { 323, 1}, - .C_SF_PS = { 324, 1}, - .C_NGLE_S = { 325, 1}, - .C_NGLE_D = { 326, 1}, - .C_NGLE_PS = { 327, 1}, - .C_SEQ_S = { 328, 1}, - .C_SEQ_D = { 329, 1}, - .C_SEQ_PS = { 330, 1}, - .C_NGL_S = { 331, 1}, - .C_NGL_D = { 332, 1}, - .C_NGL_PS = { 333, 1}, - .C_LT_S = { 334, 1}, - .C_LT_D = { 335, 1}, - .C_LT_PS = { 336, 1}, - .C_NGE_S = { 337, 1}, - .C_NGE_D = { 338, 1}, - .C_NGE_PS = { 339, 1}, - .C_LE_S = { 340, 1}, - .C_LE_D = { 341, 1}, - .C_LE_PS = { 342, 1}, - .C_NGT_S = { 343, 1}, - .C_NGT_D = { 344, 1}, - .C_NGT_PS = { 345, 1}, - .BC1F = { 346, 1}, - .BC1T = { 347, 1}, - .BC1FL = { 348, 1}, - .BC1TL = { 349, 1}, - .MFC0 = { 350, 1}, - .MTC0 = { 351, 1}, - .DMFC0 = { 352, 1}, - .DMTC0 = { 353, 1}, - .MFHC0 = { 354, 1}, - .MTHC0 = { 355, 1}, - .TLBP = { 356, 1}, - .TLBR = { 357, 1}, - .TLBWI = { 358, 1}, - .TLBWR = { 359, 1}, - .CACHE = { 360, 1}, - .MFC2 = { 361, 1}, - .MTC2 = { 362, 1}, - .CFC2 = { 363, 1}, - .CTC2 = { 364, 1}, - .LWC2 = { 365, 1}, - .SWC2 = { 366, 1}, - .LDC2 = { 367, 1}, - .SDC2 = { 368, 1}, - .RTPS = { 369, 1}, - .RTPT = { 370, 1}, - .DPCS = { 371, 1}, - .DPCT = { 372, 1}, - .INTPL = { 373, 1}, - .MVMVA = { 374, 1}, - .NCDS = { 375, 1}, - .NCDT = { 376, 1}, - .NCCS = { 377, 1}, - .NCCT = { 378, 1}, - .NCS = { 379, 1}, - .NCT = { 380, 1}, - .CDP = { 381, 1}, - .CC = { 382, 1}, - .NCLIP = { 383, 1}, - .AVSZ3 = { 384, 1}, - .AVSZ4 = { 385, 1}, - .OP_GTE = { 386, 1}, - .GPF = { 387, 1}, - .GPL = { 388, 1}, - .SQR_GTE = { 389, 1}, - .DCPL = { 390, 1}, - .LQ = { 391, 1}, - .SQ = { 392, 1}, - .LQC2 = { 393, 1}, - .SQC2 = { 394, 1}, - .MFHI1 = { 395, 1}, - .MFLO1 = { 396, 1}, - .MTHI1 = { 397, 1}, - .MTLO1 = { 398, 1}, - .MULT1 = { 399, 1}, - .MULTU1 = { 400, 1}, - .DIV1 = { 401, 1}, - .DIVU1 = { 402, 1}, - .MADD_EE = { 403, 0}, - .MADDU_EE = { 403, 0}, - .MSUB_EE = { 403, 0}, - .MSUBU_EE = { 403, 0}, - .MADD1 = { 403, 1}, - .MADDU1 = { 404, 1}, - .MSUB1 = { 405, 0}, - .MSUBU1 = { 405, 0}, - .PMFHL_LW = { 405, 1}, - .PMFHL_UW = { 406, 1}, - .PMFHL_LH = { 407, 1}, - .PMFHL_SH = { 408, 1}, - .PMFHL_SLW = { 409, 1}, - .PMTHL_LW = { 410, 1}, - .PADDB = { 411, 1}, - .PADDH = { 412, 1}, - .PADDW = { 413, 1}, - .PADDSB = { 414, 1}, - .PADDSH = { 415, 1}, - .PADDSW = { 416, 1}, - .PADDUB = { 417, 1}, - .PADDUH = { 418, 1}, - .PADDUW = { 419, 1}, - .PSUBB = { 420, 1}, - .PSUBH = { 421, 1}, - .PSUBW = { 422, 1}, - .PSUBSB = { 423, 1}, - .PSUBSH = { 424, 1}, - .PSUBSW = { 425, 1}, - .PSUBUB = { 426, 1}, - .PSUBUH = { 427, 1}, - .PSUBUW = { 428, 1}, - .PSLLH = { 429, 1}, - .PSRLH = { 430, 1}, - .PSRAH = { 431, 1}, - .PSLLW = { 432, 1}, - .PSRLW = { 433, 1}, - .PSRAW = { 434, 1}, - .PSLLVW = { 435, 1}, - .PSRLVW = { 436, 1}, - .PSRAVW = { 437, 1}, - .QFSRV = { 438, 1}, - .PAND = { 439, 1}, - .POR = { 440, 1}, - .PXOR = { 441, 1}, - .PNOR = { 442, 1}, - .PCEQB = { 443, 1}, - .PCEQH = { 444, 1}, - .PCEQW = { 445, 1}, - .PCGTB = { 446, 1}, - .PCGTH = { 447, 1}, - .PCGTW = { 448, 1}, - .PMULTW = { 449, 1}, - .PMULTUW = { 450, 1}, - .PMULTH = { 451, 1}, - .PMADDW = { 452, 1}, - .PMADDUW = { 453, 1}, - .PMADDH = { 454, 1}, - .PMSUBW = { 455, 1}, - .PMSUBH = { 456, 1}, - .PHMADH = { 457, 1}, - .PHMSBH = { 458, 1}, - .PDIVW = { 459, 1}, - .PDIVUW = { 460, 1}, - .PDIVBW = { 461, 1}, - .PCPYLD = { 462, 1}, - .PCPYUD = { 463, 1}, - .PCPYH = { 464, 1}, - .PINTH = { 465, 1}, - .PINTOH = { 466, 1}, - .PEXEH = { 467, 1}, - .PEXEW = { 468, 1}, - .PEXCH = { 469, 1}, - .PEXCW = { 470, 1}, - .PROT3W = { 471, 1}, - .PPACB = { 472, 1}, - .PPACH = { 473, 1}, - .PPACW = { 474, 1}, - .PPAC5 = { 475, 1}, - .PEXT5 = { 476, 1}, - .PEXTLB = { 477, 1}, - .PEXTLH = { 478, 1}, - .PEXTLW = { 479, 1}, - .PEXTUB = { 480, 1}, - .PEXTUH = { 481, 1}, - .PEXTUW = { 482, 1}, - .PMFHI = { 483, 1}, - .PMFLO = { 484, 1}, - .PMTHI = { 485, 1}, - .PMTLO = { 486, 1}, - .PLZCW = { 487, 1}, - .PABSH = { 488, 1}, - .PABSW = { 489, 1}, - .PMAXH = { 490, 1}, - .PMAXW = { 491, 1}, - .PMINH = { 492, 1}, - .PMINW = { 493, 1}, - .MFSA = { 494, 1}, - .MTSA = { 495, 1}, - .MTSAB = { 496, 1}, - .MTSAH = { 497, 1}, - .ADDQ_PH = { 498, 1}, - .ADDQ_S_PH = { 499, 1}, - .ADDQ_S_W = { 500, 1}, - .SUBQ_PH = { 501, 1}, - .SUBQ_S_PH = { 502, 1}, - .SUBQ_S_W = { 503, 1}, - .ADDU_QB = { 504, 1}, - .ADDU_S_QB = { 505, 1}, - .ADDU_PH = { 506, 1}, - .ADDU_S_PH = { 507, 1}, - .SUBU_QB = { 508, 1}, - .SUBU_S_QB = { 509, 1}, - .SUBU_PH = { 510, 1}, - .SUBU_S_PH = { 511, 1}, - .ADDSC = { 512, 1}, - .ADDWC = { 513, 1}, - .MULEU_S_PH_QBL = { 514, 1}, - .MULEU_S_PH_QBR = { 515, 1}, - .MULEQ_S_W_PHL = { 516, 1}, - .MULEQ_S_W_PHR = { 517, 1}, - .MULQ_RS_PH = { 518, 1}, - .MULQ_S_PH = { 519, 1}, - .MULSAQ_S_W_PH = { 520, 1}, - .DPAQ_S_W_PH = { 521, 1}, - .DPSQ_S_W_PH = { 522, 1}, - .DPAQ_SA_L_W = { 523, 1}, - .DPSQ_SA_L_W = { 524, 1}, - .DPAU_H_QBL = { 525, 1}, - .DPAU_H_QBR = { 526, 1}, - .DPSU_H_QBL = { 527, 1}, - .DPSU_H_QBR = { 528, 1}, - .DPA_W_PH = { 529, 1}, - .DPS_W_PH = { 530, 1}, - .DPAX_W_PH = { 531, 1}, - .DPSX_W_PH = { 532, 1}, - .MAQ_S_W_PHL = { 533, 1}, - .MAQ_S_W_PHR = { 534, 1}, - .MAQ_SA_W_PHL = { 535, 1}, - .MAQ_SA_W_PHR = { 536, 1}, - .EXTR_W = { 537, 1}, - .EXTR_R_W = { 538, 1}, - .EXTR_RS_W = { 539, 1}, - .EXTR_S_H = { 540, 1}, - .EXTRV_W = { 541, 1}, - .EXTRV_R_W = { 542, 1}, - .EXTRV_RS_W = { 543, 1}, - .EXTRV_S_H = { 544, 1}, - .EXTP = { 545, 1}, - .EXTPV = { 546, 1}, - .EXTPDP = { 547, 1}, - .EXTPDPV = { 548, 1}, - .SHILO = { 549, 1}, - .SHILOV = { 550, 1}, - .MTHLIP = { 551, 1}, - .WRDSP = { 552, 1}, - .RDDSP = { 553, 1}, - .PRECRQ_QB_PH = { 554, 1}, - .PRECRQ_PH_W = { 555, 1}, - .PRECRQU_S_QB_PH = { 556, 1}, - .PRECEQ_W_PHL = { 557, 1}, - .PRECEQ_W_PHR = { 558, 1}, - .PRECEQU_PH_QBL = { 559, 1}, - .PRECEQU_PH_QBR = { 560, 1}, - .PRECEQU_PH_QBLA = { 561, 1}, - .PRECEQU_PH_QBRA = { 562, 1}, - .PRECEU_PH_QBL = { 563, 1}, - .PRECEU_PH_QBR = { 564, 1}, - .PRECEU_PH_QBLA = { 565, 1}, - .PRECEU_PH_QBRA = { 566, 1}, - .PRECRQ_RS_PH_W = { 567, 1}, - .CMPU_EQ_QB = { 568, 1}, - .CMPU_LT_QB = { 569, 1}, - .CMPU_LE_QB = { 570, 1}, - .CMP_EQ_PH = { 571, 1}, - .CMP_LT_PH = { 572, 1}, - .CMP_LE_PH = { 573, 1}, - .CMPGU_EQ_QB = { 574, 1}, - .CMPGU_LT_QB = { 575, 1}, - .CMPGU_LE_QB = { 576, 1}, - .PICK_QB = { 577, 1}, - .PICK_PH = { 578, 1}, - .SHLL_QB = { 579, 1}, - .SHLL_PH = { 580, 1}, - .SHLL_S_PH = { 581, 1}, - .SHLL_S_W = { 582, 1}, - .SHLLV_QB = { 583, 1}, - .SHLLV_PH = { 584, 1}, - .SHLLV_S_PH = { 585, 1}, - .SHLLV_S_W = { 586, 1}, - .SHRL_QB = { 587, 1}, - .SHRL_PH = { 588, 1}, - .SHRLV_QB = { 589, 1}, - .SHRLV_PH = { 590, 1}, - .SHRA_QB = { 591, 1}, - .SHRA_R_QB = { 592, 1}, - .SHRA_PH = { 593, 1}, - .SHRA_R_PH = { 594, 1}, - .SHRA_R_W = { 595, 1}, - .SHRAV_QB = { 596, 1}, - .SHRAV_R_QB = { 597, 1}, - .SHRAV_PH = { 598, 1}, - .SHRAV_R_PH = { 599, 1}, - .SHRAV_R_W = { 600, 1}, - .LBUX = { 601, 1}, - .LHX = { 602, 1}, - .LWX = { 603, 1}, - .BPOSGE32 = { 604, 1}, - .BPOSGE64 = { 605, 0}, - .INSV = { 605, 1}, - .BITREV = { 606, 1}, - .ABSQ_S_PH = { 607, 1}, - .ABSQ_S_W = { 608, 1}, - .REPL_PH = { 609, 1}, - .REPLV_PH = { 610, 1}, - .REPL_QB = { 611, 1}, - .REPLV_QB = { 612, 1}, - .ADDV_B = { 613, 1}, - .ADDV_H = { 614, 1}, - .ADDV_W = { 615, 1}, - .ADDV_D = { 616, 1}, - .SUBV_B = { 617, 1}, - .SUBV_H = { 618, 1}, - .SUBV_W = { 619, 1}, - .SUBV_D = { 620, 1}, - .ADDS_S_B = { 621, 1}, - .ADDS_S_H = { 622, 1}, - .ADDS_S_W = { 623, 1}, - .ADDS_S_D = { 624, 1}, - .ADDS_U_B = { 625, 1}, - .ADDS_U_H = { 626, 1}, - .ADDS_U_W = { 627, 1}, - .ADDS_U_D = { 628, 1}, - .SUBS_S_B = { 629, 1}, - .SUBS_S_H = { 630, 1}, - .SUBS_S_W = { 631, 1}, - .SUBS_S_D = { 632, 1}, - .SUBS_U_B = { 633, 1}, - .SUBS_U_H = { 634, 1}, - .SUBS_U_W = { 635, 1}, - .SUBS_U_D = { 636, 1}, - .MULV_B = { 637, 1}, - .MULV_H = { 638, 1}, - .MULV_W = { 639, 1}, - .MULV_D = { 640, 1}, - .DIV_S_B = { 641, 1}, - .DIV_S_H = { 642, 1}, - .DIV_S_W = { 643, 1}, - .DIV_S_D = { 644, 1}, - .DIV_U_B = { 645, 1}, - .DIV_U_H = { 646, 1}, - .DIV_U_W = { 647, 1}, - .DIV_U_D = { 648, 1}, - .MOD_S_B = { 649, 1}, - .MOD_S_H = { 650, 1}, - .MOD_S_W = { 651, 1}, - .MOD_S_D = { 652, 1}, - .MOD_U_B = { 653, 1}, - .MOD_U_H = { 654, 1}, - .MOD_U_W = { 655, 1}, - .MOD_U_D = { 656, 1}, - .MADDV_B = { 657, 1}, - .MADDV_H = { 658, 1}, - .MADDV_W = { 659, 1}, - .MADDV_D = { 660, 1}, - .MSUBV_B = { 661, 1}, - .MSUBV_H = { 662, 1}, - .MSUBV_W = { 663, 1}, - .MSUBV_D = { 664, 1}, - .DOTP_S_H = { 665, 1}, - .DOTP_S_W = { 666, 1}, - .DOTP_S_D = { 667, 1}, - .DOTP_U_H = { 668, 1}, - .DOTP_U_W = { 669, 1}, - .DOTP_U_D = { 670, 1}, - .AND_V = { 671, 1}, - .OR_V = { 672, 1}, - .NOR_V = { 673, 1}, - .XOR_V = { 674, 1}, - .ANDI_B = { 675, 1}, - .ORI_B = { 676, 1}, - .NORI_B = { 677, 1}, - .XORI_B = { 678, 1}, - .BSEL_V = { 679, 1}, - .BSELI_B = { 680, 1}, - .BMNZ_V = { 681, 1}, - .BMNZI_B = { 682, 1}, - .BMZ_V = { 683, 1}, - .BMZI_B = { 684, 1}, - .CEQ_B = { 685, 1}, - .CEQ_H = { 686, 1}, - .CEQ_W = { 687, 1}, - .CEQ_D = { 688, 1}, - .CLT_S_B = { 689, 1}, - .CLT_S_H = { 690, 1}, - .CLT_S_W = { 691, 1}, - .CLT_S_D = { 692, 1}, - .CLT_U_B = { 693, 1}, - .CLT_U_H = { 694, 1}, - .CLT_U_W = { 695, 1}, - .CLT_U_D = { 696, 1}, - .CLE_S_B = { 697, 1}, - .CLE_S_H = { 698, 1}, - .CLE_S_W = { 699, 1}, - .CLE_S_D = { 700, 1}, - .CLE_U_B = { 701, 1}, - .CLE_U_H = { 702, 1}, - .CLE_U_W = { 703, 1}, - .CLE_U_D = { 704, 1}, - .MIN_S_B = { 705, 1}, - .MIN_S_H = { 706, 1}, - .MIN_S_W = { 707, 1}, - .MIN_S_D = { 708, 1}, - .MIN_U_B = { 709, 1}, - .MIN_U_H = { 710, 1}, - .MIN_U_W = { 711, 1}, - .MIN_U_D = { 712, 1}, - .MAX_S_B = { 713, 1}, - .MAX_S_H = { 714, 1}, - .MAX_S_W = { 715, 1}, - .MAX_S_D = { 716, 1}, - .MAX_U_B = { 717, 1}, - .MAX_U_H = { 718, 1}, - .MAX_U_W = { 719, 1}, - .MAX_U_D = { 720, 1}, - .SLL_B = { 721, 1}, - .SLL_H = { 722, 1}, - .SLL_W = { 723, 1}, - .SLL_D = { 724, 1}, - .SRL_B = { 725, 1}, - .SRL_H = { 726, 1}, - .SRL_W = { 727, 1}, - .SRL_D = { 728, 1}, - .SRA_B = { 729, 1}, - .SRA_H = { 730, 1}, - .SRA_W = { 731, 1}, - .SRA_D = { 732, 1}, - .SLLI_B = { 733, 1}, - .SLLI_H = { 734, 1}, - .SLLI_W = { 735, 1}, - .SLLI_D = { 736, 1}, - .SRLI_B = { 737, 1}, - .SRLI_H = { 738, 1}, - .SRLI_W = { 739, 1}, - .SRLI_D = { 740, 1}, - .SRAI_B = { 741, 1}, - .SRAI_H = { 742, 1}, - .SRAI_W = { 743, 1}, - .SRAI_D = { 744, 1}, - .FADD_W = { 745, 1}, - .FADD_D = { 746, 1}, - .FSUB_W = { 747, 1}, - .FSUB_D = { 748, 1}, - .FMUL_W = { 749, 1}, - .FMUL_D = { 750, 1}, - .FDIV_W = { 751, 1}, - .FDIV_D = { 752, 1}, - .FSQRT_W = { 753, 1}, - .FSQRT_D = { 754, 1}, - .FRSQRT_W = { 755, 1}, - .FRSQRT_D = { 756, 1}, - .FRCP_W = { 757, 1}, - .FRCP_D = { 758, 1}, - .FRINT_W = { 759, 1}, - .FRINT_D = { 760, 1}, - .FMAX_W = { 761, 1}, - .FMAX_D = { 762, 1}, - .FMIN_W = { 763, 1}, - .FMIN_D = { 764, 1}, - .FCEQ_W = { 765, 1}, - .FCEQ_D = { 766, 1}, - .FCNE_W = { 767, 1}, - .FCNE_D = { 768, 1}, - .FCLT_W = { 769, 1}, - .FCLT_D = { 770, 1}, - .FCLE_W = { 771, 1}, - .FCLE_D = { 772, 1}, - .FFINT_S_W = { 773, 1}, - .FFINT_S_D = { 774, 1}, - .FFINT_U_W = { 775, 1}, - .FFINT_U_D = { 776, 1}, - .FTRUNC_S_W = { 777, 1}, - .FTRUNC_S_D = { 778, 1}, - .FTRUNC_U_W = { 779, 1}, - .FTRUNC_U_D = { 780, 1}, - .FCVT_S_W = { 781, 1}, - .FCVT_S_D = { 782, 1}, - .FCVT_D_W = { 783, 1}, - .LD_B = { 784, 1}, - .LD_H = { 785, 1}, - .LD_W = { 786, 1}, - .LD_D = { 787, 1}, - .ST_B = { 788, 1}, - .ST_H = { 789, 1}, - .ST_W = { 790, 1}, - .ST_D = { 791, 1}, - .LDI_B = { 792, 1}, - .LDI_H = { 793, 1}, - .LDI_W = { 794, 1}, - .LDI_D = { 795, 1}, - .COPY_S_B = { 796, 1}, - .COPY_S_H = { 797, 1}, - .COPY_S_W = { 798, 1}, - .COPY_U_B = { 799, 1}, - .COPY_U_H = { 800, 1}, - .COPY_U_W = { 801, 1}, - .INSERT_B = { 802, 1}, - .INSERT_H = { 803, 1}, - .INSERT_W = { 804, 1}, - .INSERT_D = { 805, 1}, - .INSVE_B = { 806, 1}, - .INSVE_H = { 807, 1}, - .INSVE_W = { 808, 1}, - .INSVE_D = { 809, 1}, - .SHF_B = { 810, 1}, - .SHF_H = { 811, 1}, - .SHF_W = { 812, 1}, - .VSHF_B = { 813, 1}, - .VSHF_H = { 814, 1}, - .VSHF_W = { 815, 1}, - .VSHF_D = { 816, 1}, - .SLD_B = { 817, 1}, - .SLD_H = { 818, 1}, - .SLD_W = { 819, 1}, - .SLD_D = { 820, 1}, - .SLDI_B = { 821, 1}, - .SLDI_H = { 822, 1}, - .SLDI_W = { 823, 1}, - .SLDI_D = { 824, 1}, - .SPLAT_B = { 825, 1}, - .SPLAT_H = { 826, 1}, - .SPLAT_W = { 827, 1}, - .SPLAT_D = { 828, 1}, - .SPLATI_B = { 829, 1}, - .SPLATI_H = { 830, 1}, - .SPLATI_W = { 831, 1}, - .SPLATI_D = { 832, 1}, - .BZ_V = { 833, 1}, - .BNZ_V = { 834, 1}, - .BZ_B = { 835, 1}, - .BZ_H = { 836, 1}, - .BZ_W = { 837, 1}, - .BZ_D = { 838, 1}, - .BNZ_B = { 839, 1}, - .BNZ_H = { 840, 1}, - .BNZ_W = { 841, 1}, - .BNZ_D = { 842, 1}, - .NLOC_B = { 843, 1}, - .NLOC_H = { 844, 1}, - .NLOC_W = { 845, 1}, - .NLOC_D = { 846, 1}, - .NLZC_B = { 847, 1}, - .NLZC_H = { 848, 1}, - .NLZC_W = { 849, 1}, - .NLZC_D = { 850, 1}, - .PCNT_B = { 851, 1}, - .PCNT_H = { 852, 1}, - .PCNT_W = { 853, 1}, - .PCNT_D = { 854, 1}, - .VMOV_S = { 855, 1}, - .VMOV_P = { 856, 1}, - .VMOV_T = { 857, 1}, - .VMOV_Q = { 858, 1}, - .LV_S = { 859, 1}, - .LV_Q = { 860, 1}, - .SV_S = { 861, 1}, - .SV_Q = { 862, 1}, - .LVL_Q = { 863, 1}, - .LVR_Q = { 864, 1}, - .SVL_Q = { 865, 1}, - .SVR_Q = { 866, 1}, - .VIIM_S = { 867, 1}, - .VFIM_S = { 868, 1}, - .VADD_S = { 869, 1}, - .VADD_P = { 870, 1}, - .VADD_T = { 871, 1}, - .VADD_Q = { 872, 1}, - .VSUB_S = { 873, 1}, - .VSUB_P = { 874, 1}, - .VSUB_T = { 875, 1}, - .VSUB_Q = { 876, 1}, - .VMUL_S = { 877, 1}, - .VMUL_P = { 878, 1}, - .VMUL_T = { 879, 1}, - .VMUL_Q = { 880, 1}, - .VDIV_S = { 881, 1}, - .VDIV_P = { 882, 1}, - .VDIV_T = { 883, 1}, - .VDIV_Q = { 884, 1}, - .VABS_S = { 885, 1}, - .VABS_P = { 886, 1}, - .VABS_T = { 887, 1}, - .VABS_Q = { 888, 1}, - .VNEG_S = { 889, 1}, - .VNEG_P = { 890, 1}, - .VNEG_T = { 891, 1}, - .VNEG_Q = { 892, 1}, - .VSQRT_S = { 893, 1}, - .VRCP_S = { 894, 1}, - .VRCP_P = { 895, 1}, - .VRCP_T = { 896, 1}, - .VRCP_Q = { 897, 1}, - .VRSQ_S = { 898, 1}, - .VRSQ_P = { 899, 1}, - .VRSQ_T = { 900, 1}, - .VRSQ_Q = { 901, 1}, - .VDOT_P = { 902, 1}, - .VDOT_T = { 903, 1}, - .VDOT_Q = { 904, 1}, - .VSCL_P = { 905, 1}, - .VSCL_T = { 906, 1}, - .VSCL_Q = { 907, 1}, - .VHDP_P = { 908, 1}, - .VHDP_T = { 909, 1}, - .VHDP_Q = { 910, 1}, - .VAVG_P = { 911, 1}, - .VAVG_T = { 912, 1}, - .VAVG_Q = { 913, 1}, - .VFAD_P = { 914, 1}, - .VFAD_T = { 915, 1}, - .VFAD_Q = { 916, 1}, - .VMMUL_P = { 917, 1}, - .VMMUL_T = { 918, 1}, - .VMMUL_Q = { 919, 1}, - .VTFM2_P = { 920, 1}, - .VTFM3_T = { 921, 1}, - .VTFM4_Q = { 922, 1}, - .VHTFM2_P = { 923, 1}, - .VHTFM3_T = { 924, 1}, - .VHTFM4_Q = { 925, 1}, - .VMSCL_P = { 926, 1}, - .VMSCL_T = { 927, 1}, - .VMSCL_Q = { 928, 1}, - .VMMOV_P = { 929, 1}, - .VMMOV_T = { 930, 1}, - .VMMOV_Q = { 931, 1}, - .VMIDT_P = { 932, 1}, - .VMIDT_T = { 933, 1}, - .VMIDT_Q = { 934, 1}, - .VMZERO_P = { 935, 1}, - .VMZERO_T = { 936, 1}, - .VMZERO_Q = { 937, 1}, - .VMONE_P = { 938, 1}, - .VMONE_T = { 939, 1}, - .VMONE_Q = { 940, 1}, - .VCRS_T = { 941, 1}, - .VCRSP_T = { 942, 1}, - .VQMUL_Q = { 943, 1}, - .VCMP_S = { 944, 1}, - .VCMP_P = { 945, 1}, - .VCMP_T = { 946, 1}, - .VCMP_Q = { 947, 1}, - .VMIN_S = { 948, 1}, - .VMIN_P = { 949, 1}, - .VMIN_T = { 950, 1}, - .VMIN_Q = { 951, 1}, - .VMAX_S = { 952, 1}, - .VMAX_P = { 953, 1}, - .VMAX_T = { 954, 1}, - .VMAX_Q = { 955, 1}, - .VSIN_S = { 956, 1}, - .VCOS_S = { 957, 1}, - .VEXP2_S = { 958, 1}, - .VLOG2_S = { 959, 1}, - .VASIN_S = { 960, 1}, - .VNRCP_S = { 961, 1}, - .VNSIN_S = { 962, 1}, - .VREXP2_S = { 963, 1}, - .VSGN_S = { 964, 1}, - .VI2F_S = { 965, 1}, - .VI2F_P = { 966, 1}, - .VI2F_T = { 967, 1}, - .VI2F_Q = { 968, 1}, - .VF2IN_S = { 969, 1}, - .VF2IN_P = { 970, 1}, - .VF2IN_T = { 971, 1}, - .VF2IN_Q = { 972, 1}, - .VF2IZ_S = { 973, 1}, - .VF2IZ_P = { 974, 1}, - .VF2IZ_T = { 975, 1}, - .VF2IZ_Q = { 976, 1}, - .VF2IU_S = { 977, 1}, - .VF2IU_P = { 978, 1}, - .VF2IU_T = { 979, 1}, - .VF2IU_Q = { 980, 1}, - .VF2ID_S = { 981, 1}, - .VF2ID_P = { 982, 1}, - .VF2ID_T = { 983, 1}, - .VF2ID_Q = { 984, 1}, - .VF2H_P = { 985, 1}, - .VH2F_S = { 986, 1}, - .VFLUSH = { 987, 1}, - .VSYNC = { 988, 1}, - .VNOP = { 989, 1}, - .VPFXS = { 990, 1}, - .VPFXT = { 991, 1}, - .VPFXD = { 992, 1}, - .VCST_S = { 993, 1}, - .VCST_P = { 994, 1}, - .VCST_T = { 995, 1}, - .VCST_Q = { 996, 1}, - .MFV = { 997, 1}, - .MTV = { 998, 1}, - .MFVC = { 999, 1}, - .MTVC = { 1000, 1}, - .BVF = { 1001, 1}, - .BVT = { 1002, 1}, - .BVFL = { 1003, 1}, - .BVTL = { 1004, 1}, + .LWPC = { 192, 1}, + .LWUPC = { 193, 1}, + .LDPC = { 194, 1}, + .SELEQZ = { 195, 1}, + .SELNEZ = { 196, 1}, + .CRC32B = { 197, 1}, + .CRC32H = { 198, 1}, + .CRC32W = { 199, 1}, + .CRC32D = { 200, 1}, + .CRC32CB = { 201, 1}, + .CRC32CH = { 202, 1}, + .CRC32CW = { 203, 1}, + .CRC32CD = { 204, 1}, + .SIGRIE = { 205, 1}, + .MFC1 = { 206, 1}, + .MTC1 = { 207, 1}, + .DMFC1 = { 208, 1}, + .DMTC1 = { 209, 1}, + .CFC1 = { 210, 1}, + .CTC1 = { 211, 1}, + .MFHC1 = { 212, 1}, + .MTHC1 = { 213, 1}, + .LWC1 = { 214, 1}, + .SWC1 = { 215, 1}, + .LDC1 = { 216, 1}, + .SDC1 = { 217, 1}, + .ADD_S = { 218, 1}, + .ADD_D = { 219, 1}, + .ADD_PS = { 220, 1}, + .SUB_S = { 221, 1}, + .SUB_D = { 222, 1}, + .SUB_PS = { 223, 1}, + .MUL_S = { 224, 1}, + .MUL_D = { 225, 1}, + .MUL_PS = { 226, 1}, + .DIV_S = { 227, 1}, + .DIV_D = { 228, 1}, + .SQRT_S = { 229, 1}, + .SQRT_D = { 230, 1}, + .ABS_S = { 231, 1}, + .ABS_D = { 232, 1}, + .ABS_PS = { 233, 1}, + .NEG_S = { 234, 1}, + .NEG_D = { 235, 1}, + .NEG_PS = { 236, 1}, + .MOV_S = { 237, 1}, + .MOV_D = { 238, 1}, + .MOV_PS = { 239, 1}, + .RECIP_S = { 240, 1}, + .RECIP_D = { 241, 1}, + .RSQRT_S = { 242, 1}, + .RSQRT_D = { 243, 1}, + .MADD_S = { 244, 1}, + .MADD_D = { 245, 1}, + .MADD_PS = { 246, 1}, + .MSUB_S = { 247, 1}, + .MSUB_D = { 248, 1}, + .MSUB_PS = { 249, 1}, + .NMADD_S = { 250, 1}, + .NMADD_D = { 251, 1}, + .NMADD_PS = { 252, 1}, + .NMSUB_S = { 253, 1}, + .NMSUB_D = { 254, 1}, + .NMSUB_PS = { 255, 1}, + .MOVN_S = { 256, 1}, + .MOVN_D = { 257, 1}, + .MOVN_PS = { 258, 1}, + .MOVZ_S = { 259, 1}, + .MOVZ_D = { 260, 1}, + .MOVZ_PS = { 261, 1}, + .MOVF_S = { 262, 1}, + .MOVF_D = { 263, 1}, + .MOVF_PS = { 264, 1}, + .MOVT_S = { 265, 1}, + .MOVT_D = { 266, 1}, + .MOVT_PS = { 267, 1}, + .CVT_S_D = { 268, 1}, + .CVT_S_W = { 269, 1}, + .CVT_S_L = { 270, 1}, + .CVT_D_S = { 271, 1}, + .CVT_D_W = { 272, 1}, + .CVT_D_L = { 273, 1}, + .CVT_W_S = { 274, 1}, + .CVT_W_D = { 275, 1}, + .CVT_L_S = { 276, 1}, + .CVT_L_D = { 277, 1}, + .CVT_PS_S = { 278, 1}, + .CVT_S_PU = { 279, 1}, + .CVT_S_PL = { 280, 1}, + .PLL_PS = { 281, 1}, + .PLU_PS = { 282, 1}, + .PUL_PS = { 283, 1}, + .PUU_PS = { 284, 1}, + .ROUND_W_S = { 285, 1}, + .ROUND_W_D = { 286, 1}, + .ROUND_L_S = { 287, 1}, + .ROUND_L_D = { 288, 1}, + .TRUNC_W_S = { 289, 1}, + .TRUNC_W_D = { 290, 1}, + .TRUNC_L_S = { 291, 1}, + .TRUNC_L_D = { 292, 1}, + .CEIL_W_S = { 293, 1}, + .CEIL_W_D = { 294, 1}, + .CEIL_L_S = { 295, 1}, + .CEIL_L_D = { 296, 1}, + .FLOOR_W_S = { 297, 1}, + .FLOOR_W_D = { 298, 1}, + .FLOOR_L_S = { 299, 1}, + .FLOOR_L_D = { 300, 1}, + .C_F_S = { 301, 1}, + .C_F_D = { 302, 1}, + .C_F_PS = { 303, 1}, + .C_UN_S = { 304, 1}, + .C_UN_D = { 305, 1}, + .C_UN_PS = { 306, 1}, + .C_EQ_S = { 307, 1}, + .C_EQ_D = { 308, 1}, + .C_EQ_PS = { 309, 1}, + .C_UEQ_S = { 310, 1}, + .C_UEQ_D = { 311, 1}, + .C_UEQ_PS = { 312, 1}, + .C_OLT_S = { 313, 1}, + .C_OLT_D = { 314, 1}, + .C_OLT_PS = { 315, 1}, + .C_ULT_S = { 316, 1}, + .C_ULT_D = { 317, 1}, + .C_ULT_PS = { 318, 1}, + .C_OLE_S = { 319, 1}, + .C_OLE_D = { 320, 1}, + .C_OLE_PS = { 321, 1}, + .C_ULE_S = { 322, 1}, + .C_ULE_D = { 323, 1}, + .C_ULE_PS = { 324, 1}, + .C_SF_S = { 325, 1}, + .C_SF_D = { 326, 1}, + .C_SF_PS = { 327, 1}, + .C_NGLE_S = { 328, 1}, + .C_NGLE_D = { 329, 1}, + .C_NGLE_PS = { 330, 1}, + .C_SEQ_S = { 331, 1}, + .C_SEQ_D = { 332, 1}, + .C_SEQ_PS = { 333, 1}, + .C_NGL_S = { 334, 1}, + .C_NGL_D = { 335, 1}, + .C_NGL_PS = { 336, 1}, + .C_LT_S = { 337, 1}, + .C_LT_D = { 338, 1}, + .C_LT_PS = { 339, 1}, + .C_NGE_S = { 340, 1}, + .C_NGE_D = { 341, 1}, + .C_NGE_PS = { 342, 1}, + .C_LE_S = { 343, 1}, + .C_LE_D = { 344, 1}, + .C_LE_PS = { 345, 1}, + .C_NGT_S = { 346, 1}, + .C_NGT_D = { 347, 1}, + .C_NGT_PS = { 348, 1}, + .BC1F = { 349, 1}, + .BC1T = { 350, 1}, + .BC1FL = { 351, 1}, + .BC1TL = { 352, 1}, + .MFC0 = { 353, 1}, + .MTC0 = { 354, 1}, + .DMFC0 = { 355, 1}, + .DMTC0 = { 356, 1}, + .MFHC0 = { 357, 1}, + .MTHC0 = { 358, 1}, + .TLBP = { 359, 1}, + .TLBR = { 360, 1}, + .TLBWI = { 361, 1}, + .TLBWR = { 362, 1}, + .CACHE = { 363, 1}, + .MFC2 = { 364, 1}, + .MTC2 = { 365, 1}, + .CFC2 = { 366, 1}, + .CTC2 = { 367, 1}, + .LWC2 = { 368, 1}, + .SWC2 = { 369, 1}, + .LDC2 = { 370, 1}, + .SDC2 = { 371, 1}, + .RTPS = { 372, 1}, + .RTPT = { 373, 1}, + .DPCS = { 374, 1}, + .DPCT = { 375, 1}, + .INTPL = { 376, 1}, + .MVMVA = { 377, 1}, + .NCDS = { 378, 1}, + .NCDT = { 379, 1}, + .NCCS = { 380, 1}, + .NCCT = { 381, 1}, + .NCS = { 382, 1}, + .NCT = { 383, 1}, + .CDP = { 384, 1}, + .CC = { 385, 1}, + .NCLIP = { 386, 1}, + .AVSZ3 = { 387, 1}, + .AVSZ4 = { 388, 1}, + .OP_GTE = { 389, 1}, + .GPF = { 390, 1}, + .GPL = { 391, 1}, + .SQR_GTE = { 392, 1}, + .DCPL = { 393, 1}, + .LQ = { 394, 1}, + .SQ = { 395, 1}, + .LQC2 = { 396, 1}, + .SQC2 = { 397, 1}, + .MFHI1 = { 398, 1}, + .MFLO1 = { 399, 1}, + .MTHI1 = { 400, 1}, + .MTLO1 = { 401, 1}, + .MULT1 = { 402, 1}, + .MULTU1 = { 403, 1}, + .DIV1 = { 404, 1}, + .DIVU1 = { 405, 1}, + .MADD_EE = { 406, 0}, + .MADDU_EE = { 406, 0}, + .MSUB_EE = { 406, 0}, + .MSUBU_EE = { 406, 0}, + .MADD1 = { 406, 1}, + .MADDU1 = { 407, 1}, + .MSUB1 = { 408, 0}, + .MSUBU1 = { 408, 0}, + .PMFHL_LW = { 408, 1}, + .PMFHL_UW = { 409, 1}, + .PMFHL_LH = { 410, 1}, + .PMFHL_SH = { 411, 1}, + .PMFHL_SLW = { 412, 1}, + .PMTHL_LW = { 413, 1}, + .PADDB = { 414, 1}, + .PADDH = { 415, 1}, + .PADDW = { 416, 1}, + .PADDSB = { 417, 1}, + .PADDSH = { 418, 1}, + .PADDSW = { 419, 1}, + .PADDUB = { 420, 1}, + .PADDUH = { 421, 1}, + .PADDUW = { 422, 1}, + .PSUBB = { 423, 1}, + .PSUBH = { 424, 1}, + .PSUBW = { 425, 1}, + .PSUBSB = { 426, 1}, + .PSUBSH = { 427, 1}, + .PSUBSW = { 428, 1}, + .PSUBUB = { 429, 1}, + .PSUBUH = { 430, 1}, + .PSUBUW = { 431, 1}, + .PSLLH = { 432, 1}, + .PSRLH = { 433, 1}, + .PSRAH = { 434, 1}, + .PSLLW = { 435, 1}, + .PSRLW = { 436, 1}, + .PSRAW = { 437, 1}, + .PSLLVW = { 438, 1}, + .PSRLVW = { 439, 1}, + .PSRAVW = { 440, 1}, + .QFSRV = { 441, 1}, + .PAND = { 442, 1}, + .POR = { 443, 1}, + .PXOR = { 444, 1}, + .PNOR = { 445, 1}, + .PCEQB = { 446, 1}, + .PCEQH = { 447, 1}, + .PCEQW = { 448, 1}, + .PCGTB = { 449, 1}, + .PCGTH = { 450, 1}, + .PCGTW = { 451, 1}, + .PMULTW = { 452, 1}, + .PMULTUW = { 453, 1}, + .PMULTH = { 454, 1}, + .PMADDW = { 455, 1}, + .PMADDUW = { 456, 1}, + .PMADDH = { 457, 1}, + .PMSUBW = { 458, 1}, + .PMSUBH = { 459, 1}, + .PHMADH = { 460, 1}, + .PHMSBH = { 461, 1}, + .PDIVW = { 462, 1}, + .PDIVUW = { 463, 1}, + .PDIVBW = { 464, 1}, + .PCPYLD = { 465, 1}, + .PCPYUD = { 466, 1}, + .PCPYH = { 467, 1}, + .PINTH = { 468, 1}, + .PINTOH = { 469, 1}, + .PEXEH = { 470, 1}, + .PEXEW = { 471, 1}, + .PEXCH = { 472, 1}, + .PEXCW = { 473, 1}, + .PROT3W = { 474, 1}, + .PPACB = { 475, 1}, + .PPACH = { 476, 1}, + .PPACW = { 477, 1}, + .PPAC5 = { 478, 1}, + .PEXT5 = { 479, 1}, + .PEXTLB = { 480, 1}, + .PEXTLH = { 481, 1}, + .PEXTLW = { 482, 1}, + .PEXTUB = { 483, 1}, + .PEXTUH = { 484, 1}, + .PEXTUW = { 485, 1}, + .PMFHI = { 486, 1}, + .PMFLO = { 487, 1}, + .PMTHI = { 488, 1}, + .PMTLO = { 489, 1}, + .PLZCW = { 490, 1}, + .PABSH = { 491, 1}, + .PABSW = { 492, 1}, + .PMAXH = { 493, 1}, + .PMAXW = { 494, 1}, + .PMINH = { 495, 1}, + .PMINW = { 496, 1}, + .MFSA = { 497, 1}, + .MTSA = { 498, 1}, + .MTSAB = { 499, 1}, + .MTSAH = { 500, 1}, + .ADDQ_PH = { 501, 1}, + .ADDQ_S_PH = { 502, 1}, + .ADDQ_S_W = { 503, 1}, + .SUBQ_PH = { 504, 1}, + .SUBQ_S_PH = { 505, 1}, + .SUBQ_S_W = { 506, 1}, + .ADDU_QB = { 507, 1}, + .ADDU_S_QB = { 508, 1}, + .ADDU_PH = { 509, 1}, + .ADDU_S_PH = { 510, 1}, + .SUBU_QB = { 511, 1}, + .SUBU_S_QB = { 512, 1}, + .SUBU_PH = { 513, 1}, + .SUBU_S_PH = { 514, 1}, + .ADDSC = { 515, 1}, + .ADDWC = { 516, 1}, + .MULEU_S_PH_QBL = { 517, 1}, + .MULEU_S_PH_QBR = { 518, 1}, + .MULEQ_S_W_PHL = { 519, 1}, + .MULEQ_S_W_PHR = { 520, 1}, + .MULQ_RS_PH = { 521, 1}, + .MULQ_S_PH = { 522, 1}, + .MULSAQ_S_W_PH = { 523, 1}, + .DPAQ_S_W_PH = { 524, 1}, + .DPSQ_S_W_PH = { 525, 1}, + .DPAQ_SA_L_W = { 526, 1}, + .DPSQ_SA_L_W = { 527, 1}, + .DPAU_H_QBL = { 528, 1}, + .DPAU_H_QBR = { 529, 1}, + .DPSU_H_QBL = { 530, 1}, + .DPSU_H_QBR = { 531, 1}, + .DPA_W_PH = { 532, 1}, + .DPS_W_PH = { 533, 1}, + .DPAX_W_PH = { 534, 1}, + .DPSX_W_PH = { 535, 1}, + .MAQ_S_W_PHL = { 536, 1}, + .MAQ_S_W_PHR = { 537, 1}, + .MAQ_SA_W_PHL = { 538, 1}, + .MAQ_SA_W_PHR = { 539, 1}, + .EXTR_W = { 540, 1}, + .EXTR_R_W = { 541, 1}, + .EXTR_RS_W = { 542, 1}, + .EXTR_S_H = { 543, 1}, + .EXTRV_W = { 544, 1}, + .EXTRV_R_W = { 545, 1}, + .EXTRV_RS_W = { 546, 1}, + .EXTRV_S_H = { 547, 1}, + .EXTP = { 548, 1}, + .EXTPV = { 549, 1}, + .EXTPDP = { 550, 1}, + .EXTPDPV = { 551, 1}, + .SHILO = { 552, 1}, + .SHILOV = { 553, 1}, + .MTHLIP = { 554, 1}, + .WRDSP = { 555, 1}, + .RDDSP = { 556, 1}, + .PRECRQ_QB_PH = { 557, 1}, + .PRECRQ_PH_W = { 558, 1}, + .PRECRQU_S_QB_PH = { 559, 1}, + .PRECEQ_W_PHL = { 560, 1}, + .PRECEQ_W_PHR = { 561, 1}, + .PRECEQU_PH_QBL = { 562, 1}, + .PRECEQU_PH_QBR = { 563, 1}, + .PRECEQU_PH_QBLA = { 564, 1}, + .PRECEQU_PH_QBRA = { 565, 1}, + .PRECEU_PH_QBL = { 566, 1}, + .PRECEU_PH_QBR = { 567, 1}, + .PRECEU_PH_QBLA = { 568, 1}, + .PRECEU_PH_QBRA = { 569, 1}, + .PRECRQ_RS_PH_W = { 570, 1}, + .CMPU_EQ_QB = { 571, 1}, + .CMPU_LT_QB = { 572, 1}, + .CMPU_LE_QB = { 573, 1}, + .CMP_EQ_PH = { 574, 1}, + .CMP_LT_PH = { 575, 1}, + .CMP_LE_PH = { 576, 1}, + .CMPGU_EQ_QB = { 577, 1}, + .CMPGU_LT_QB = { 578, 1}, + .CMPGU_LE_QB = { 579, 1}, + .PICK_QB = { 580, 1}, + .PICK_PH = { 581, 1}, + .SHLL_QB = { 582, 1}, + .SHLL_PH = { 583, 1}, + .SHLL_S_PH = { 584, 1}, + .SHLL_S_W = { 585, 1}, + .SHLLV_QB = { 586, 1}, + .SHLLV_PH = { 587, 1}, + .SHLLV_S_PH = { 588, 1}, + .SHLLV_S_W = { 589, 1}, + .SHRL_QB = { 590, 1}, + .SHRL_PH = { 591, 1}, + .SHRLV_QB = { 592, 1}, + .SHRLV_PH = { 593, 1}, + .SHRA_QB = { 594, 1}, + .SHRA_R_QB = { 595, 1}, + .SHRA_PH = { 596, 1}, + .SHRA_R_PH = { 597, 1}, + .SHRA_R_W = { 598, 1}, + .SHRAV_QB = { 599, 1}, + .SHRAV_R_QB = { 600, 1}, + .SHRAV_PH = { 601, 1}, + .SHRAV_R_PH = { 602, 1}, + .SHRAV_R_W = { 603, 1}, + .LBUX = { 604, 1}, + .LHX = { 605, 1}, + .LWX = { 606, 1}, + .BPOSGE32 = { 607, 1}, + .BPOSGE64 = { 608, 0}, + .INSV = { 608, 1}, + .BITREV = { 609, 1}, + .ABSQ_S_PH = { 610, 1}, + .ABSQ_S_W = { 611, 1}, + .REPL_PH = { 612, 1}, + .REPLV_PH = { 613, 1}, + .REPL_QB = { 614, 1}, + .REPLV_QB = { 615, 1}, + .ADDV_B = { 616, 1}, + .ADDV_H = { 617, 1}, + .ADDV_W = { 618, 1}, + .ADDV_D = { 619, 1}, + .SUBV_B = { 620, 1}, + .SUBV_H = { 621, 1}, + .SUBV_W = { 622, 1}, + .SUBV_D = { 623, 1}, + .ADDS_S_B = { 624, 1}, + .ADDS_S_H = { 625, 1}, + .ADDS_S_W = { 626, 1}, + .ADDS_S_D = { 627, 1}, + .ADDS_U_B = { 628, 1}, + .ADDS_U_H = { 629, 1}, + .ADDS_U_W = { 630, 1}, + .ADDS_U_D = { 631, 1}, + .SUBS_S_B = { 632, 1}, + .SUBS_S_H = { 633, 1}, + .SUBS_S_W = { 634, 1}, + .SUBS_S_D = { 635, 1}, + .SUBS_U_B = { 636, 1}, + .SUBS_U_H = { 637, 1}, + .SUBS_U_W = { 638, 1}, + .SUBS_U_D = { 639, 1}, + .MULV_B = { 640, 1}, + .MULV_H = { 641, 1}, + .MULV_W = { 642, 1}, + .MULV_D = { 643, 1}, + .DIV_S_B = { 644, 1}, + .DIV_S_H = { 645, 1}, + .DIV_S_W = { 646, 1}, + .DIV_S_D = { 647, 1}, + .DIV_U_B = { 648, 1}, + .DIV_U_H = { 649, 1}, + .DIV_U_W = { 650, 1}, + .DIV_U_D = { 651, 1}, + .MOD_S_B = { 652, 1}, + .MOD_S_H = { 653, 1}, + .MOD_S_W = { 654, 1}, + .MOD_S_D = { 655, 1}, + .MOD_U_B = { 656, 1}, + .MOD_U_H = { 657, 1}, + .MOD_U_W = { 658, 1}, + .MOD_U_D = { 659, 1}, + .MADDV_B = { 660, 1}, + .MADDV_H = { 661, 1}, + .MADDV_W = { 662, 1}, + .MADDV_D = { 663, 1}, + .MSUBV_B = { 664, 1}, + .MSUBV_H = { 665, 1}, + .MSUBV_W = { 666, 1}, + .MSUBV_D = { 667, 1}, + .DOTP_S_H = { 668, 1}, + .DOTP_S_W = { 669, 1}, + .DOTP_S_D = { 670, 1}, + .DOTP_U_H = { 671, 1}, + .DOTP_U_W = { 672, 1}, + .DOTP_U_D = { 673, 1}, + .AND_V = { 674, 1}, + .OR_V = { 675, 1}, + .NOR_V = { 676, 1}, + .XOR_V = { 677, 1}, + .ANDI_B = { 678, 1}, + .ORI_B = { 679, 1}, + .NORI_B = { 680, 1}, + .XORI_B = { 681, 1}, + .BSEL_V = { 682, 1}, + .BSELI_B = { 683, 1}, + .BMNZ_V = { 684, 1}, + .BMNZI_B = { 685, 1}, + .BMZ_V = { 686, 1}, + .BMZI_B = { 687, 1}, + .CEQ_B = { 688, 1}, + .CEQ_H = { 689, 1}, + .CEQ_W = { 690, 1}, + .CEQ_D = { 691, 1}, + .CLT_S_B = { 692, 1}, + .CLT_S_H = { 693, 1}, + .CLT_S_W = { 694, 1}, + .CLT_S_D = { 695, 1}, + .CLT_U_B = { 696, 1}, + .CLT_U_H = { 697, 1}, + .CLT_U_W = { 698, 1}, + .CLT_U_D = { 699, 1}, + .CLE_S_B = { 700, 1}, + .CLE_S_H = { 701, 1}, + .CLE_S_W = { 702, 1}, + .CLE_S_D = { 703, 1}, + .CLE_U_B = { 704, 1}, + .CLE_U_H = { 705, 1}, + .CLE_U_W = { 706, 1}, + .CLE_U_D = { 707, 1}, + .MIN_S_B = { 708, 1}, + .MIN_S_H = { 709, 1}, + .MIN_S_W = { 710, 1}, + .MIN_S_D = { 711, 1}, + .MIN_U_B = { 712, 1}, + .MIN_U_H = { 713, 1}, + .MIN_U_W = { 714, 1}, + .MIN_U_D = { 715, 1}, + .MAX_S_B = { 716, 1}, + .MAX_S_H = { 717, 1}, + .MAX_S_W = { 718, 1}, + .MAX_S_D = { 719, 1}, + .MAX_U_B = { 720, 1}, + .MAX_U_H = { 721, 1}, + .MAX_U_W = { 722, 1}, + .MAX_U_D = { 723, 1}, + .SLL_B = { 724, 1}, + .SLL_H = { 725, 1}, + .SLL_W = { 726, 1}, + .SLL_D = { 727, 1}, + .SRL_B = { 728, 1}, + .SRL_H = { 729, 1}, + .SRL_W = { 730, 1}, + .SRL_D = { 731, 1}, + .SRA_B = { 732, 1}, + .SRA_H = { 733, 1}, + .SRA_W = { 734, 1}, + .SRA_D = { 735, 1}, + .SLLI_B = { 736, 1}, + .SLLI_H = { 737, 1}, + .SLLI_W = { 738, 1}, + .SLLI_D = { 739, 1}, + .SRLI_B = { 740, 1}, + .SRLI_H = { 741, 1}, + .SRLI_W = { 742, 1}, + .SRLI_D = { 743, 1}, + .SRAI_B = { 744, 1}, + .SRAI_H = { 745, 1}, + .SRAI_W = { 746, 1}, + .SRAI_D = { 747, 1}, + .FADD_W = { 748, 1}, + .FADD_D = { 749, 1}, + .FSUB_W = { 750, 1}, + .FSUB_D = { 751, 1}, + .FMUL_W = { 752, 1}, + .FMUL_D = { 753, 1}, + .FDIV_W = { 754, 1}, + .FDIV_D = { 755, 1}, + .FSQRT_W = { 756, 1}, + .FSQRT_D = { 757, 1}, + .FRSQRT_W = { 758, 1}, + .FRSQRT_D = { 759, 1}, + .FRCP_W = { 760, 1}, + .FRCP_D = { 761, 1}, + .FRINT_W = { 762, 1}, + .FRINT_D = { 763, 1}, + .FMAX_W = { 764, 1}, + .FMAX_D = { 765, 1}, + .FMIN_W = { 766, 1}, + .FMIN_D = { 767, 1}, + .FCEQ_W = { 768, 1}, + .FCEQ_D = { 769, 1}, + .FCNE_W = { 770, 1}, + .FCNE_D = { 771, 1}, + .FCLT_W = { 772, 1}, + .FCLT_D = { 773, 1}, + .FCLE_W = { 774, 1}, + .FCLE_D = { 775, 1}, + .FFINT_S_W = { 776, 1}, + .FFINT_S_D = { 777, 1}, + .FFINT_U_W = { 778, 1}, + .FFINT_U_D = { 779, 1}, + .FTRUNC_S_W = { 780, 1}, + .FTRUNC_S_D = { 781, 1}, + .FTRUNC_U_W = { 782, 1}, + .FTRUNC_U_D = { 783, 1}, + .FCVT_S_W = { 784, 1}, + .FCVT_S_D = { 785, 1}, + .FCVT_D_W = { 786, 1}, + .LD_B = { 787, 1}, + .LD_H = { 788, 1}, + .LD_W = { 789, 1}, + .LD_D = { 790, 1}, + .ST_B = { 791, 1}, + .ST_H = { 792, 1}, + .ST_W = { 793, 1}, + .ST_D = { 794, 1}, + .LDI_B = { 795, 1}, + .LDI_H = { 796, 1}, + .LDI_W = { 797, 1}, + .LDI_D = { 798, 1}, + .COPY_S_B = { 799, 1}, + .COPY_S_H = { 800, 1}, + .COPY_S_W = { 801, 1}, + .COPY_U_B = { 802, 1}, + .COPY_U_H = { 803, 1}, + .COPY_U_W = { 804, 1}, + .INSERT_B = { 805, 1}, + .INSERT_H = { 806, 1}, + .INSERT_W = { 807, 1}, + .INSERT_D = { 808, 1}, + .INSVE_B = { 809, 1}, + .INSVE_H = { 810, 1}, + .INSVE_W = { 811, 1}, + .INSVE_D = { 812, 1}, + .SHF_B = { 813, 1}, + .SHF_H = { 814, 1}, + .SHF_W = { 815, 1}, + .VSHF_B = { 816, 1}, + .VSHF_H = { 817, 1}, + .VSHF_W = { 818, 1}, + .VSHF_D = { 819, 1}, + .SLD_B = { 820, 1}, + .SLD_H = { 821, 1}, + .SLD_W = { 822, 1}, + .SLD_D = { 823, 1}, + .SLDI_B = { 824, 1}, + .SLDI_H = { 825, 1}, + .SLDI_W = { 826, 1}, + .SLDI_D = { 827, 1}, + .SPLAT_B = { 828, 1}, + .SPLAT_H = { 829, 1}, + .SPLAT_W = { 830, 1}, + .SPLAT_D = { 831, 1}, + .SPLATI_B = { 832, 1}, + .SPLATI_H = { 833, 1}, + .SPLATI_W = { 834, 1}, + .SPLATI_D = { 835, 1}, + .BZ_V = { 836, 1}, + .BNZ_V = { 837, 1}, + .BZ_B = { 838, 1}, + .BZ_H = { 839, 1}, + .BZ_W = { 840, 1}, + .BZ_D = { 841, 1}, + .BNZ_B = { 842, 1}, + .BNZ_H = { 843, 1}, + .BNZ_W = { 844, 1}, + .BNZ_D = { 845, 1}, + .NLOC_B = { 846, 1}, + .NLOC_H = { 847, 1}, + .NLOC_W = { 848, 1}, + .NLOC_D = { 849, 1}, + .NLZC_B = { 850, 1}, + .NLZC_H = { 851, 1}, + .NLZC_W = { 852, 1}, + .NLZC_D = { 853, 1}, + .PCNT_B = { 854, 1}, + .PCNT_H = { 855, 1}, + .PCNT_W = { 856, 1}, + .PCNT_D = { 857, 1}, + .VMOV_S = { 858, 1}, + .VMOV_P = { 859, 1}, + .VMOV_T = { 860, 1}, + .VMOV_Q = { 861, 1}, + .LV_S = { 862, 1}, + .LV_Q = { 863, 1}, + .SV_S = { 864, 1}, + .SV_Q = { 865, 1}, + .LVL_Q = { 866, 1}, + .LVR_Q = { 867, 1}, + .SVL_Q = { 868, 1}, + .SVR_Q = { 869, 1}, + .VIIM_S = { 870, 1}, + .VFIM_S = { 871, 1}, + .VADD_S = { 872, 1}, + .VADD_P = { 873, 1}, + .VADD_T = { 874, 1}, + .VADD_Q = { 875, 1}, + .VSUB_S = { 876, 1}, + .VSUB_P = { 877, 1}, + .VSUB_T = { 878, 1}, + .VSUB_Q = { 879, 1}, + .VMUL_S = { 880, 1}, + .VMUL_P = { 881, 1}, + .VMUL_T = { 882, 1}, + .VMUL_Q = { 883, 1}, + .VDIV_S = { 884, 1}, + .VDIV_P = { 885, 1}, + .VDIV_T = { 886, 1}, + .VDIV_Q = { 887, 1}, + .VABS_S = { 888, 1}, + .VABS_P = { 889, 1}, + .VABS_T = { 890, 1}, + .VABS_Q = { 891, 1}, + .VNEG_S = { 892, 1}, + .VNEG_P = { 893, 1}, + .VNEG_T = { 894, 1}, + .VNEG_Q = { 895, 1}, + .VSQRT_S = { 896, 1}, + .VRCP_S = { 897, 1}, + .VRCP_P = { 898, 1}, + .VRCP_T = { 899, 1}, + .VRCP_Q = { 900, 1}, + .VRSQ_S = { 901, 1}, + .VRSQ_P = { 902, 1}, + .VRSQ_T = { 903, 1}, + .VRSQ_Q = { 904, 1}, + .VDOT_P = { 905, 1}, + .VDOT_T = { 906, 1}, + .VDOT_Q = { 907, 1}, + .VSCL_P = { 908, 1}, + .VSCL_T = { 909, 1}, + .VSCL_Q = { 910, 1}, + .VHDP_P = { 911, 1}, + .VHDP_T = { 912, 1}, + .VHDP_Q = { 913, 1}, + .VAVG_P = { 914, 1}, + .VAVG_T = { 915, 1}, + .VAVG_Q = { 916, 1}, + .VFAD_P = { 917, 1}, + .VFAD_T = { 918, 1}, + .VFAD_Q = { 919, 1}, + .VMMUL_P = { 920, 1}, + .VMMUL_T = { 921, 1}, + .VMMUL_Q = { 922, 1}, + .VTFM2_P = { 923, 1}, + .VTFM3_T = { 924, 1}, + .VTFM4_Q = { 925, 1}, + .VHTFM2_P = { 926, 1}, + .VHTFM3_T = { 927, 1}, + .VHTFM4_Q = { 928, 1}, + .VMSCL_P = { 929, 1}, + .VMSCL_T = { 930, 1}, + .VMSCL_Q = { 931, 1}, + .VMMOV_P = { 932, 1}, + .VMMOV_T = { 933, 1}, + .VMMOV_Q = { 934, 1}, + .VMIDT_P = { 935, 1}, + .VMIDT_T = { 936, 1}, + .VMIDT_Q = { 937, 1}, + .VMZERO_P = { 938, 1}, + .VMZERO_T = { 939, 1}, + .VMZERO_Q = { 940, 1}, + .VMONE_P = { 941, 1}, + .VMONE_T = { 942, 1}, + .VMONE_Q = { 943, 1}, + .VCRS_T = { 944, 1}, + .VCRSP_T = { 945, 1}, + .VQMUL_Q = { 946, 1}, + .VCMP_S = { 947, 1}, + .VCMP_P = { 948, 1}, + .VCMP_T = { 949, 1}, + .VCMP_Q = { 950, 1}, + .VMIN_S = { 951, 1}, + .VMIN_P = { 952, 1}, + .VMIN_T = { 953, 1}, + .VMIN_Q = { 954, 1}, + .VMAX_S = { 955, 1}, + .VMAX_P = { 956, 1}, + .VMAX_T = { 957, 1}, + .VMAX_Q = { 958, 1}, + .VSIN_S = { 959, 1}, + .VCOS_S = { 960, 1}, + .VEXP2_S = { 961, 1}, + .VLOG2_S = { 962, 1}, + .VASIN_S = { 963, 1}, + .VNRCP_S = { 964, 1}, + .VNSIN_S = { 965, 1}, + .VREXP2_S = { 966, 1}, + .VSGN_S = { 967, 1}, + .VI2F_S = { 968, 1}, + .VI2F_P = { 969, 1}, + .VI2F_T = { 970, 1}, + .VI2F_Q = { 971, 1}, + .VF2IN_S = { 972, 1}, + .VF2IN_P = { 973, 1}, + .VF2IN_T = { 974, 1}, + .VF2IN_Q = { 975, 1}, + .VF2IZ_S = { 976, 1}, + .VF2IZ_P = { 977, 1}, + .VF2IZ_T = { 978, 1}, + .VF2IZ_Q = { 979, 1}, + .VF2IU_S = { 980, 1}, + .VF2IU_P = { 981, 1}, + .VF2IU_T = { 982, 1}, + .VF2IU_Q = { 983, 1}, + .VF2ID_S = { 984, 1}, + .VF2ID_P = { 985, 1}, + .VF2ID_T = { 986, 1}, + .VF2ID_Q = { 987, 1}, + .VF2H_P = { 988, 1}, + .VH2F_S = { 989, 1}, + .VFLUSH = { 990, 1}, + .VSYNC = { 991, 1}, + .VNOP = { 992, 1}, + .VPFXS = { 993, 1}, + .VPFXT = { 994, 1}, + .VPFXD = { 995, 1}, + .VCST_S = { 996, 1}, + .VCST_P = { 997, 1}, + .VCST_T = { 998, 1}, + .VCST_Q = { 999, 1}, + .MFV = { 1000, 1}, + .MTV = { 1001, 1}, + .MFVC = { 1002, 1}, + .MTVC = { 1003, 1}, + .BVF = { 1004, 1}, + .BVT = { 1005, 1}, + .BVFL = { 1006, 1}, + .BVTL = { 1007, 1}, } diff --git a/core/rexcode/mips/tablegen/specgen.lua b/core/rexcode/mips/tablegen/specgen.lua index d797376ac..6ed10233c 100644 --- a/core/rexcode/mips/tablegen/specgen.lua +++ b/core/rexcode/mips/tablegen/specgen.lua @@ -350,27 +350,23 @@ end -- ---- Branches: derive bits/regs, then mark the PC-relative offset variable. -- Compact (R6) branches need the r6 ISA, so each family passes its own mattr. -local function bword(line, mattr) - local p = io.popen(string.format("printf '%%s\\n' '%s' | llvm-mc --assemble --triple=mips --mattr=%s --show-encoding 2>/dev/null", line, mattr)) - local out = p:read("*a"); p:close() - local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)") - if not b1 then return nil end - return tonumber(b1..b2..b3..b4, 16) -end -local function branch_block(mnem, ops, enc, feat, asm, maxes, offbits, mattr) +local function branch_block(mnem, ops, enc, feat, asm, maxes, offbits, cmd) local zero={}; for i=1,#maxes do zero[i]=0 end - local b0 = bword(asm(zero), mattr) + local b0 = word(asm(zero), cmd) if not b0 then skips[#skips+1]=mnem; return end local vs={} for i=1,#maxes do local v={}; for j=1,#maxes do v[j]=0 end; v[i]=maxes[i] - local w=bword(asm(v), mattr); if not w then skips[#skips+1]=mnem; return end; vs[#vs+1]=w + local w=word(asm(v), cmd); if not w then skips[#skips+1]=mnem; return end; vs[#vs+1]=w end local m = bit.band(mask_of(b0,vs), bit.bnot((2^offbits)-1)) -- offset field = variable n_forms=n_forms+1 sections[#sections+1]=string.format(" .%s = { {.%s, %s, %s, 0x%s, 0x%s, .%s, {}} },", mnem, mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(m):upper(), feat) end +local LLVM_MSA = "llvm-mc --assemble --triple=mips --mattr=+msa --show-encoding" +local LLVM_R6 = "llvm-mc --assemble --triple=mips --mattr=+mips32r6 --show-encoding" +local LLVM_64R6 = "llvm-mc --assemble --triple=mips64 --mattr=+mips64r6 --show-encoding" -- NOTE: the R6 two-/one-register compact branches (BEQC/BNEC/BLTC/BGEC/BLTUC/ -- BGEUC/BLEZC/BGTZC/BGEZC/BLTZC) are intentionally NOT generated here. They @@ -381,10 +377,18 @@ end for _, b in ipairs({{"BZ","bz"},{"BNZ","bnz"}}) do for _, d in ipairs({{"B","b"},{"H","h"},{"W","w"},{"D","d"},{"V","v"}}) do branch_block(b[1].."_"..d[1], "{.MSA_VEC,.REL16,.NONE,.NONE}", "{.WT,.BRANCH_16,.NONE,.NONE}", "MSA", - function(v) return string.format("%s.%s $w%d,0", b[2], d[2], v[1]) end, {31}, 16, "+msa") + function(v) return string.format("%s.%s $w%d,0", b[2], d[2], v[1]) end, {31}, 16, LLVM_MSA) end end +-- ---- R6 PC-relative loads (offset is a 19-/18-bit PC-relative label) -------- +branch_block("LWPC", "{.GPR,.REL19,.NONE,.NONE}", "{.RS,.BRANCH_19,.NONE,.NONE}", "MIPS32_R6", + function(v) return string.format("lwpc $%d,0", v[1]) end, {31}, 19, LLVM_R6) +branch_block("LWUPC", "{.GPR,.REL19,.NONE,.NONE}", "{.RS,.BRANCH_19,.NONE,.NONE}", "MIPS64_R6", + function(v) return string.format("lwupc $%d,0", v[1]) end, {31}, 19, LLVM_64R6) +branch_block("LDPC", "{.GPR,.REL18,.NONE,.NONE}", "{.RS,.BRANCH_18,.NONE,.NONE}", "MIPS64_R6", + function(v) return string.format("ldpc $%d,0", v[1]) end, {31}, 18, LLVM_64R6) + -- ---- splice into the SoT --------------------------------------------------- local region = " // SPECGEN:BEGIN\n" .. table.concat(sections, "\n") .. "\n // SPECGEN:END" local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() diff --git a/core/rexcode/mips/tables/mips.encode_forms.bin b/core/rexcode/mips/tables/mips.encode_forms.bin index 5494d3e70..50798a046 100644 Binary files a/core/rexcode/mips/tables/mips.encode_forms.bin and b/core/rexcode/mips/tables/mips.encode_forms.bin differ diff --git a/core/rexcode/mips/tables/mips.encode_runs.bin b/core/rexcode/mips/tables/mips.encode_runs.bin index b939b523d..a3441384e 100644 Binary files a/core/rexcode/mips/tables/mips.encode_runs.bin and b/core/rexcode/mips/tables/mips.encode_runs.bin differ diff --git a/core/rexcode/mips/tables/mips.entries.bin b/core/rexcode/mips/tables/mips.entries.bin index a3f7c231e..2b65a5420 100644 Binary files a/core/rexcode/mips/tables/mips.entries.bin and b/core/rexcode/mips/tables/mips.entries.bin differ diff --git a/core/rexcode/mips/tables/mips.idx_primary.bin b/core/rexcode/mips/tables/mips.idx_primary.bin index 9f5a5a884..28845c1f5 100644 Binary files a/core/rexcode/mips/tables/mips.idx_primary.bin and b/core/rexcode/mips/tables/mips.idx_primary.bin differ diff --git a/core/rexcode/mips/tools/gen_mnemonic_builders.odin b/core/rexcode/mips/tools/gen_mnemonic_builders.odin index 1f4088a06..d177dac85 100644 --- a/core/rexcode/mips/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/mips/tools/gen_mnemonic_builders.odin @@ -277,7 +277,7 @@ can_generate_operand :: proc(op: mips.Operand_Type) -> bool { return true case .IMM5, .IMM16S, .IMM16U, .IMM20, .SEL, .FCC: return true - case .REL16, .REL21, .REL26, .REL_J26: + case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18: return true case .MEM: return true @@ -313,7 +313,7 @@ operand_suffix :: proc(op: mips.Operand_Type) -> string { case .IMM20: return "i20" case .SEL: return "sel" case .FCC: return "cc" - case .REL16: return "rel" + case .REL16, .REL19, .REL18: return "rel" case .REL21: return "rel21" case .REL26: return "rel26" case .REL_J26: return "j" @@ -338,7 +338,7 @@ operand_param_type :: proc(op: mips.Operand_Type) -> string { return "Register" case .IMM5, .IMM16S, .IMM16U, .IMM20, .SEL, .FCC: return "i64" - case .REL16, .REL21, .REL26, .REL_J26: + case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18: return "u32" case .MEM: return "Memory" } @@ -377,7 +377,7 @@ write_op_expr :: proc(sb: ^strings.Builder, op: mips.Operand_Type, name: string) fmt.sbprintf(sb, "op_reg(%s)", name) case .IMM5, .IMM16S, .IMM16U, .IMM20, .SEL, .FCC: fmt.sbprintf(sb, "op_imm(%s, %d)", name, operand_imm_size(op)) - case .REL16, .REL21, .REL26, .REL_J26: + case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18: fmt.sbprintf(sb, "op_label(%s)", name) case .MEM: fmt.sbprintf(sb, "op_mem(%s, 4)", name) @@ -403,7 +403,7 @@ param_names :: proc(sig: Operand_Signature) -> [4]string { case .IMM5, .IMM16S, .IMM16U, .IMM20, .SEL, .FCC: result[i] = imm_n == 0 ? "imm" : fmt.tprintf("imm%d", imm_n + 1) imm_n += 1 - case .REL16, .REL21, .REL26, .REL_J26: + case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18: result[i] = rel_n == 0 ? "target" : fmt.tprintf("target%d", rel_n + 1) rel_n += 1 case .MEM: