10 Commits

Author	SHA1	Message	Date
Jeroen van Rijn	27667ce36b	iff -> if and only if (⟺)	2026-03-13 11:54:15 +01:00
Jeroen van Rijn	af43e6851b	[core:sys/info] Remove , ok	2026-02-23 23:55:36 +01:00
Jeroen van Rijn	ea80eab75a	[core:sys/info] Remove @(init) where practical	2026-02-23 23:09:37 +01:00
Feoramund	45219f240e	Rename SIMD_IS_EMULATED to capability-affirmative HAS_HARDWARE_SIMD	2025-05-29 17:17:51 -04:00
Jeroen van Rijn	655fab7227	Add core/hyperthread count for Windows and Linux (#5216) ... Add core/hyperthread count to `core:sys/info` for Windows and Linux. TODO: Linux RISCV, Linux ARM, Darwin, and the BSDs.	2025-05-25 19:43:10 +02:00
Yawning Angel	6e8710fce4	core/crypto/chacha20: Misc Simd128 improvements ... - Detect the RISC-V `v` profile - Don't bother trying to process 4 blocks at a time if emulated	2025-03-23 19:14:33 +09:00
Antonino Simone Di Stefano	5a6f761535	Add missing package qualifier to Context	2024-09-22 23:15:36 +02:00
Laytan	ca6ef95b03	add support for linux_riscv64 and freestanding_riscv64	2024-08-20 14:06:40 +02:00
Yawning Angel	b381791f42	core/crypto/chacha20: Change API terminology to be consistent with AES	2024-08-10 18:32:37 +09:00
Yawning Angel	1f3107e693	core/crypto/chacha20: Use 128-bit/256-bit SIMD	2024-08-10 18:32:37 +09:00