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orca-dev
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62 Commits

Author SHA1 Message Date
gingerBill
3e7e779abf Replace core:* to base:* where appropriate 2024-01-28 22:18:51 +00:00
Yawning Angel
8d7c37e384 core/simd/x86: Use the none calling convention for intrinsics 
The LLVM intrinsics that live under `llvm.x86` are not actual functions,
so trying to invoke them as such using the platform's native C
calling convention causes incorrect types to be emitted in the IR.

Thanks to laytanl for assistance in testing.
 2024-01-07 20:04:40 +09:00
Yawning Angel
9235e82451 core/simd/x86: Correct a target feature name 2024-01-07 20:04:40 +09:00
jakubtomsu
b06583133a Fix the other bit_* intrinsic calls 2023-10-22 20:59:19 +02:00
jakubtomsu
a2e6fc5909 change and_not to bit_and_not 2023-10-22 20:52:35 +02:00
gingerBill
63f755554b Rename simd bitwise operations from intrinsics.simd_and to intrinsics.simd_bit_and etc 2023-09-28 16:42:08 +01:00
Jeroen van Rijn
d5f94d73ad [sys/info] Initial version. 2022-09-01 00:43:47 +02:00
gingerBill
bb7f291f5f Remove simd_rem; Disallow simd_div for integers 2022-06-02 12:10:43 +01:00
gingerBill
4e49d24df9 Add enable_target_feature to ABM 2022-05-30 16:08:06 +01:00
gingerBill
68222cb8ab Add SSE4.2 2022-05-30 16:06:31 +01:00
gingerBill
912d29af83 Add @(require_results) to all appropriate procedures 2022-05-30 15:59:48 +01:00
gingerBill
51707032d1 Add SSE4.1 2022-05-30 15:17:02 +01:00
gingerBill
f3aefbc443 @(require_target_feature=<string>) @(enable_target_feature=<string>) 
require_target_feature - required by the target micro-architecture
enable_target_feature - will be enabled for the specified procedure only
 2022-05-30 14:53:12 +01:00
gingerBill
cef022539e Rename to lanes_rotate_left, lanes_rotate_right, lanes_reverse 2022-05-29 15:13:14 +01:00
gingerBill
f6dfa33697 Use single line attributes 2022-05-29 15:11:15 +01:00
gingerBill
bc3bf939e0 Add sha.odin 2022-05-29 14:56:25 +01:00
gingerBill
f5e5eac3b9 Add cmpxchg16b 2022-05-29 14:46:05 +01:00
gingerBill
0ccbea17aa Add pclmulqdq.odin 2022-05-29 13:50:54 +01:00
gingerBill
babfba5e8f Add rdtsc.odin 2022-05-29 13:48:20 +01:00
gingerBill
846f8377b2 Add fxsr.odin 2022-05-29 13:44:00 +01:00
gingerBill
77d4409549 Add adx.odin 2022-05-29 13:40:16 +01:00
gingerBill
7f3540b7f5 Add abm.odin 2022-05-29 13:36:55 +01:00
gingerBill
3ad2cde833 Add amd64 specific instructions 2022-05-29 13:34:59 +01:00
gingerBill
910799cc5f Add cpu_features for core:simd/x86 2022-05-28 15:54:41 +01:00
gingerBill
d7eaf0f87b Add intrinsics.x86_cpuid and intrinsics.x86_xgetbv 2022-05-28 15:41:11 +01:00
gingerBill
4db533ff71 Add ssse3 support 2022-05-27 23:07:33 +01:00
gingerBill
026540040d Add SSE3 support 2022-05-27 23:00:52 +01:00
gingerBill
8518d3b232 Rename to non_temporaral_* 2022-05-27 22:57:16 +01:00
gingerBill
1c1f5e2231 Complete SSE2 2022-05-27 22:56:11 +01:00
gingerBill
20c5033b38 Add pack and unpack 2022-05-27 17:07:48 +01:00
gingerBill
20fe6d102a Add load and stores and sets 2022-05-27 16:58:35 +01:00
gingerBill
4e30a64d9f Add more sse2 intrinsics 2022-05-27 16:49:52 +01:00
gingerBill
c48ef7d70b Add shifts 2022-05-27 16:39:54 +01:00
gingerBill
e079a7009d Begin work on sse2.odin 2022-05-27 16:09:31 +01:00
gingerBill
f383bf3136 Add _mm_stream_ps 2022-05-27 14:59:09 +01:00
gingerBill
2185dada56 Change package name 2022-05-27 14:26:02 +01:00
gingerBill
0b08080119 Add core:simd/x86 SSE 
Proof of Concept to show intrinsics specific to a certain target platform
 2022-05-27 14:23:31 +01:00
gingerBill
952f294bce Add loads of aliases of vector types 2022-05-27 12:20:48 +01:00
gingerBill
1ff8b97dae Add prefix of lanes_ 2022-05-26 20:44:37 +01:00
gingerBill
70451f9335 Support reverse_bits for #simd 2022-05-26 20:40:48 +01:00
gingerBill
1f438d4e6c Merge intrinsics.simd_sqrt with intrinsics.sqrt 2022-05-26 18:09:59 +01:00
gingerBill
421d45a7a7 Add intrinsics.fused_mul_add 2022-05-26 18:06:26 +01:00
gingerBill
20e7b5c88a Support count_ones etc with #simd 2022-05-26 17:48:51 +01:00
gingerBill
7092273a8f Rename simd_eq etc to simd_lanes_eq 2022-05-26 17:36:13 +01:00
gingerBill
d0e8a735ba Add arithmetic operator support for simd vectors; Add intrinsics.simd_and_not 2022-05-26 17:09:46 +01:00
gingerBill
f308f37ba1 Remove need for simd.splat 2022-05-26 14:51:50 +01:00
gingerBill
c2610cb75e Keep -vet happy 2022-05-26 13:56:35 +01:00
gingerBill
59e9df2609 simd.bit_not; simd.copysign 2022-05-26 13:49:27 +01:00
gingerBill
f3f6c12a7c Add simd_clamp 2022-05-26 11:58:55 +01:00
gingerBill
e331b0647e Add simd_rotate_left simd_rotate_right` 2022-05-26 11:48:04 +01:00