11 Commits

Author	SHA1	Message	Date
gingerBill	648c418fc4	Restrict riscv to only allow [base + disp] (i.e. disallow index*scale style things)	2026-08-21 14:31:58 +01:00
gingerBill	4a4a5045f8	Check for float register width exactly for risc-v frontend	2026-08-21 12:19:02 +01:00
gingerBill	a604ddceb1	Support pseudo macro mnemonics (for RISC-V) in the frontend	2026-08-21 11:47:41 +01:00
gingerBill	d0fb380c20	Support riscv _aq _rl _aqrl suffixes for mnemonics	2026-08-21 01:05:47 +01:00
gingerBill	de8c0dc4fe	Fix register width test for risc-v, and improve operand slot type inference for risc-v	2026-08-21 00:38:34 +01:00
gingerBill	7a7bfea0bd	Begin work on pseudo mnemonics in the checker	2026-08-20 19:12:44 +01:00
gingerBill	cfb8a109b6	Begin work on pseudo-aliases	2026-08-20 17:51:47 +01:00
gingerBill	84f9bc76f9	Mockout inline asm for riscv	2026-08-20 14:42:42 +01:00
gingerBill	f3899c1825	rexcode: riscv INSTRUCTION_TABLE which includes the clobber information	2026-08-20 11:43:26 +01:00
gingerBill	2ebc25001d	Add missing risc-v instructions to rexcode	2026-08-20 11:08:03 +01:00
Brendan Punsky	95df04fbe1	rexcode: re-house ISA packages under core:rexcode/isa/<arch> ... Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.	2026-06-18 19:03:27 -04:00