mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 08:32:33 +00:00
06eb3de6a2
MOV_V (ORR alias: source feeds both Vn and Vm via a new VN_VM_DUP encoding), MVN_V (NOT alias, plain 2-register), DUP_V (element form Vd.T,Vn.Ts[i] and general form Vd.T,Wn/Xn), INS (element-to-element and from-GPR), EXT_V (imm4 byte index). Adds a VEC_INDEX operand type plus NEON_IDX5/NEON_IDX4/NEON_EXT_IDX encodings: the element-size marker rides in the entry bits, the lane index drives the bits above it, and the decoder recovers the element size from imm5's marker. Element size now rides in op.size (B=1/H=2/S=4/D=8) via op_v_elem_b/h/s/d so the matcher can disambiguate DUP/INS element forms; the builder generator maps V_ELEM_* to those constructors. specgen derives the mask by varying registers and each index field to its max -- the GPR-source forms vary Vd and Rn independently (Rn 31 = wzr/xzr) so the low bit of each field toggles. All 19 representative forms byte-exact vs llvm-mc and decode-clean; 461 tests green. (TBL/TBX register-list forms deferred.)
622 lines
21 KiB
Odin
622 lines
21 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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import "../isa"
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// =============================================================================
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// AArch64 DECODER
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// =============================================================================
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//
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// Two passes, mirroring riscv/decoder.odin. Specifics:
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//
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// * Single-level dispatch by op0 (bits[28:25], 4 bits = 16 slots);
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// linear scan within each bucket. Entries are sorted by mask-
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// popcount descending so the most-specific encoding form wins.
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//
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// * SP-vs-ZR reconstruction is contextual: the decoder reads hw 0-31
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// and emits an X / W register; if the form expects WSP_REG/XSP_REG
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// it emits a REG_WSP/REG_XSP at hw 31 instead of ZR.
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//
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// * .RM extraction is form-dependent: SHIFTED_REG and EXTENDED_REG
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// operand types pull both the register hw and the shift/extend bits.
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16,
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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endianness: Endianness = .LITTLE,
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) -> Result {
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n_bytes := u32(len(data)) & ~u32(3)
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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pc: u32 = 0
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for pc < n_bytes {
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word := read_u32(data, pc, endianness)
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inst: Instruction
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info: Instruction_Info
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entry_idx := decode_one_inline(word, pc, &inst, &info)
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if entry_idx < 0 {
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append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = 4}
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info = Instruction_Info{offset = pc}
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} else {
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inst_idx_for_branches := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx_for_branches,
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op_idx = slot,
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target = u32(op.relative),
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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pc += 4
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}
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isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs)
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return Result{byte_count = pc, success = u32(len(errors)) == errors_start}
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}
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// =============================================================================
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// Internal
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// =============================================================================
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@(private="file")
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decode_one_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, inst: ^Instruction, info: ^Instruction_Info,
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) -> int {
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op0 := (word >> 25) & 0xF
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range := DECODE_INDEX_OP0[op0]
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if range.count == 0 { return -1 }
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base := int(range.start)
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cnt := int(range.count)
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matched_idx := -1
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for i in 0..<cnt {
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e := &DECODE_ENTRIES[base + i]
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if (word & e.mask) == e.bits {
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matched_idx = base + i
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break
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}
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}
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if matched_idx < 0 { return -1 }
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entry := &DECODE_ENTRIES[matched_idx]
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inst.mnemonic = entry.mnemonic
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inst.length = 4
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inst.flags = {}
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cnt_used: u8 = 0
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if entry.ops[0] != .NONE {
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inst.ops[0] = extract_operand_inline(word, pc, entry.ops[0], entry.enc[0])
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cnt_used = 1
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if entry.ops[1] != .NONE {
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inst.ops[1] = extract_operand_inline(word, pc, entry.ops[1], entry.enc[1])
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cnt_used = 2
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if entry.ops[2] != .NONE {
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inst.ops[2] = extract_operand_inline(word, pc, entry.ops[2], entry.enc[2])
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cnt_used = 3
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if entry.ops[3] != .NONE {
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inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3])
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cnt_used = 4
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}
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}
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}
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}
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inst.operand_count = cnt_used
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info.offset = pc
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info.decode_entry = u16(matched_idx)
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return matched_idx
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}
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@(private="file")
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extract_operand_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, ot: Operand_Type, en: Operand_Encoding,
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) -> Operand {
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#partial switch en {
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case .NONE, .IMPL:
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// For IMPL on .COND_HI/etc. cases the operand stays NONE.
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return {}
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// ---- Register slots ----------------------------------------------------
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case .RD, .RT:
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return reg_from_field(word, 0, ot)
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case .RN:
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return reg_from_field(word, 5, ot)
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case .RT2, .RA:
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return reg_from_field(word, 10, ot)
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case .RM:
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// Three flavours per operand type: plain / shifted / extended.
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#partial switch ot {
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case .W_SHIFTED, .X_SHIFTED:
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hw := u8((word >> 16) & 0x1F)
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return Operand{
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shifted = Shifted_Reg{
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reg = ot == .X_SHIFTED ? Register(REG_X | u16(hw)) : Register(REG_W | u16(hw)),
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type = Shift_Type((word >> 22) & 0x3),
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amount = u8((word >> 10) & 0x3F),
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},
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kind = .SHIFTED_REG, size = 4,
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}
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case .W_EXTENDED, .X_EXTENDED:
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hw := u8((word >> 16) & 0x1F)
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return Operand{
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extended = Extended_Reg{
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reg = ot == .X_EXTENDED ? Register(REG_X | u16(hw)) : Register(REG_W | u16(hw)),
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extend = Extend((word >> 13) & 0x7),
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amount = u8((word >> 10) & 0x7),
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},
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kind = .EXTENDED_REG, size = 4,
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}
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case:
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return reg_from_field(word, 16, ot)
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}
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// ---- Immediates --------------------------------------------------------
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case .IMM12: return Operand{immediate = i64((word >> 10) & 0xFFF), kind = .IMMEDIATE, size = 2}
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case .IMM16: return Operand{immediate = i64((word >> 5) & 0xFFFF), kind = .IMMEDIATE, size = 2}
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case .IMM6: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1}
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case .IMM9:
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v := i32((word >> 12) & 0x1FF)
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if v & (1 << 8) != 0 { v |= ~i32(0x1FF) } // sign-extend from bit 8
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .IMM_HW: return Operand{immediate = i64((word >> 21) & 0x3), kind = .IMMEDIATE, size = 1}
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case .IMM_SH12: return Operand{immediate = i64((word >> 22) & 0x1), kind = .IMMEDIATE, size = 1}
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case .SHIFT_TYPE: return Operand{immediate = i64((word >> 22) & 0x3), kind = .IMMEDIATE, size = 1}
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case .EXT_OPT: return Operand{immediate = i64((word >> 13) & 0x7), kind = .IMMEDIATE, size = 1}
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case .EXT_IMM3: return Operand{immediate = i64((word >> 10) & 0x7), kind = .IMMEDIATE, size = 1}
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case .COND_HI:
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return Operand{cond = u8((word >> 12) & 0xF), kind = .COND, size = 1}
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case .COND_LO:
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return Operand{cond = u8(word & 0xF), kind = .COND, size = 1}
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case .NZCV_FIELD:
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return Operand{immediate = i64(word & 0xF), kind = .IMMEDIATE, size = 1}
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case .SYS_FIELD:
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return Operand{immediate = i64((word >> 5) & 0x7FFF), kind = .IMMEDIATE, size = 2}
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case .HINT_FIELD:
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return Operand{immediate = i64((word >> 5) & 0x7F), kind = .IMMEDIATE, size = 1}
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case .BARRIER_FIELD:
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return Operand{immediate = i64((word >> 8) & 0xF), kind = .IMMEDIATE, size = 1}
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// ---- NEON shift-by-immediate: recover the amount from immh:immb ---------
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case .NEON_SHL_IMM, .NEON_SHR_IMM:
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immh := (word >> 19) & 0xF
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esize: i64 = 8
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if immh >= 8 { esize = 64 }
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else if immh >= 4 { esize = 32 }
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else if immh >= 2 { esize = 16 }
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val := i64((word >> 16) & 0x7F)
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amt := val - esize
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if en == .NEON_SHR_IMM { amt = 2 * esize - val }
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return Operand{immediate = amt, kind = .IMMEDIATE, size = 1}
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// ---- NEON copy/permute index fields ------------------------------------
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case .VN_VM_DUP:
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return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4}
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case .NEON_IDX5:
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// imm5 = index << (markerbit+1) | (1 << markerbit); marker = lowest set bit.
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imm5 := (word >> 16) & 0x1F
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mb: u32 = 0
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if imm5 & 0x1 != 0 { mb = 0 }
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else if imm5 & 0x2 != 0 { mb = 1 }
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else if imm5 & 0x4 != 0 { mb = 2 }
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else { mb = 3 }
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return Operand{immediate = i64(imm5 >> (mb + 1)), kind = .IMMEDIATE, size = 1}
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case .NEON_IDX4:
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// imm4 = index << markerbit; recover markerbit from imm5 in the word.
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imm5 := (word >> 16) & 0x1F
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mb: u32 = 0
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if imm5 & 0x1 != 0 { mb = 0 }
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else if imm5 & 0x2 != 0 { mb = 1 }
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else if imm5 & 0x4 != 0 { mb = 2 }
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else { mb = 3 }
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return Operand{immediate = i64(((word >> 11) & 0xF) >> mb), kind = .IMMEDIATE, size = 1}
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case .NEON_EXT_IDX:
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return Operand{immediate = i64((word >> 11) & 0xF), kind = .IMMEDIATE, size = 1}
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// ---- Memory operand variants ------------------------------------------
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case .OFFSET_BASE_U12:
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size := u32(1) << ((word >> 30) & 0x3)
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base_hw := u8((word >> 5) & 0x1F)
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imm12 := u32((word >> 10) & 0xFFF)
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = NONE,
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disp = i32(imm12 * size),
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mode = .OFFSET,
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},
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kind = .MEMORY, size = 4,
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}
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case .OFFSET_BASE_S9:
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base_hw := u8((word >> 5) & 0x1F)
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imm9 := i32((word >> 12) & 0x1FF)
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if imm9 & (1 << 8) != 0 { imm9 |= ~i32(0x1FF) }
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = NONE,
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disp = imm9,
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mode = .OFFSET,
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},
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kind = .MEMORY, size = 4,
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}
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case .OFFSET_BASE_PRE:
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base_hw := u8((word >> 5) & 0x1F)
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imm9 := i32((word >> 12) & 0x1FF)
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if imm9 & (1 << 8) != 0 { imm9 |= ~i32(0x1FF) }
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = NONE,
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disp = imm9,
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mode = .PRE_INDEXED,
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},
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kind = .MEMORY, size = 4,
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}
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case .OFFSET_BASE_POST:
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base_hw := u8((word >> 5) & 0x1F)
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imm9 := i32((word >> 12) & 0x1FF)
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if imm9 & (1 << 8) != 0 { imm9 |= ~i32(0x1FF) }
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = NONE,
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disp = imm9,
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mode = .POST_INDEXED,
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},
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kind = .MEMORY, size = 4,
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}
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case .OFFSET_BASE_A:
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// [Xn] only: no displacement, no index.
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base_hw := u8((word >> 5) & 0x1F)
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = NONE,
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mode = .OFFSET,
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},
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kind = .MEMORY, size = 4,
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}
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case .OFFSET_REG, .OFFSET_EXT:
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base_hw := u8((word >> 5) & 0x1F)
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idx_hw := u8((word >> 16) & 0x1F)
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option := Extend((word >> 13) & 0x7)
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s := u8((word >> 12) & 0x1)
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idx_cls := u16(REG_X)
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if option == .UXTW || option == .SXTW { idx_cls = REG_W }
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return Operand{
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mem = Memory{
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base = Register(REG_X | u16(base_hw)),
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index = Register(idx_cls | u16(idx_hw)),
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extend = option,
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shift = s,
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mode = en == .OFFSET_EXT ? .EXT_REG_OFFSET : .REG_OFFSET,
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},
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kind = .MEMORY, size = 4,
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}
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// ---- PC-relative branches ---------------------------------------------
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case .BRANCH_26:
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v := i32(word & 0x03FFFFFF)
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if v & (1 << 25) != 0 { v |= ~i32(0x03FFFFFF) }
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target := u32(i32(pc) + (v << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_19:
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v := i32((word >> 5) & 0x7FFFF)
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if v & (1 << 18) != 0 { v |= ~i32(0x7FFFF) }
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target := u32(i32(pc) + (v << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_14:
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v := i32((word >> 5) & 0x3FFF)
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if v & (1 << 13) != 0 { v |= ~i32(0x3FFF) }
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target := u32(i32(pc) + (v << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_PG21:
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// Sign-extended 21-bit value reassembled from immlo/immhi.
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lo := (word >> 29) & 0x3
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hi := (word >> 5) & 0x7FFFF
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v := i32((hi << 2) | lo)
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if v & (1 << 20) != 0 { v |= ~i32(0x1FFFFF) }
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// For ADR (op=0 bit 31) target = PC + imm21.
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// For ADRP (op=1) target = (PC & ~0xFFF) + (imm21 << 12).
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if (word >> 31) & 1 != 0 {
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// ADRP
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target := (i64(pc) & ~i64(0xFFF)) + (i64(v) << 12)
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return Operand{relative = target, kind = .RELATIVE, size = 4}
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} else {
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target := u32(i32(pc) + v)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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}
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case .TBZ_BIT:
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// Reassemble bit position: b5 at bit 31, b40 at bits 23-19.
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b5 := (word >> 31) & 0x1
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b40 := (word >> 19) & 0x1F
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return Operand{immediate = i64((b5 << 5) | b40), kind = .IMMEDIATE, size = 1}
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// ---- Bitmask logical immediate (round-trip back to the raw mask) ----
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case .BITMASK_FIELD:
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is_64 := (word >> 31) & 1 != 0
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n_bit := u8((word >> 22) & 1)
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immr := u8((word >> 16) & 0x3F)
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imms := u8((word >> 10) & 0x3F)
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value, ok := decode_bitmask_imm(n_bit, immr, imms, is_64)
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if !ok { return {} }
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return Operand{immediate = i64(value), kind = .IMMEDIATE, size = is_64 ? 8 : 4}
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// ---- NEON / SIMD register slots ----
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case .VD:
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hw := u16(word & 0x1F)
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return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4}
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case .VN:
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hw := u16((word >> 5) & 0x1F)
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return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4}
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case .VM:
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hw := u16((word >> 16) & 0x1F)
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return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4}
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case .VA:
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hw := u16((word >> 10) & 0x1F)
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return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4}
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// ---- NEON / SVE indexed/immediate fields ----
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case .NEON_IMM8_FMOV:
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v := ((word >> 16) & 0x7) << 5 | ((word >> 5) & 0x1F)
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .NEON_INDEX_H:
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return Operand{immediate = i64((word >> 19) & 0x3), kind = .IMMEDIATE, size = 1}
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case .NEON_INDEX_S:
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v := ((word >> 21) & 0x1) | ((word >> 11) & 0x1) << 1
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .NEON_INDEX_D:
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return Operand{immediate = i64((word >> 11) & 0x1), kind = .IMMEDIATE, size = 1}
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// ---- LSE atomic register slots ----
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case .ATOMIC_RS:
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return reg_from_field(word, 16, ot)
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case .ATOMIC_RT:
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return reg_from_field(word, 0, ot)
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case .ATOMIC_RN:
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// Memory operand: only the base register is encoded in the word,
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// displacement is always zero (atomic addressing).
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base_hw := u8((word >> 5) & 0x1F)
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return Operand{
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mem = Memory{
|
|
base = Register(REG_X | u16(base_hw)),
|
|
index = NONE,
|
|
mode = .OFFSET,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
|
|
// ---- SVE predicate slots ----
|
|
case .PD:
|
|
return Operand{reg = Register(REG_P | u16(word & 0xF)), kind = .REGISTER, size = 4}
|
|
case .PN:
|
|
return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4}
|
|
case .PM:
|
|
return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = 4}
|
|
case .PG:
|
|
return Operand{reg = Register(REG_P | u16((word >> 10) & 0x7)), kind = .REGISTER, size = 4}
|
|
case .PG4:
|
|
return Operand{reg = Register(REG_P | u16((word >> 10) & 0xF)), kind = .REGISTER, size = 4}
|
|
case .PM3:
|
|
return Operand{reg = Register(REG_P | u16((word >> 13) & 0x7)), kind = .REGISTER, size = 4}
|
|
|
|
// ---- SVE immediates ----
|
|
case .SVE_IMM8:
|
|
v := i32((word >> 5) & 0xFF)
|
|
if v & 0x80 != 0 { v |= ~i32(0xFF) }
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
|
|
case .SVE_IMM5:
|
|
return Operand{immediate = i64((word >> 16) & 0x1F), kind = .IMMEDIATE, size = 1}
|
|
case .SVE_SHIFT_TSZ_IMM:
|
|
return Operand{immediate = i64((word >> 16) & 0x7F), kind = .IMMEDIATE, size = 1}
|
|
case .SVE_PATTERN:
|
|
return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = 1}
|
|
|
|
// ---- SVE memory operands ----
|
|
case .SVE_OFFSET_BASE_SS:
|
|
base_hw := u8((word >> 5) & 0x1F)
|
|
idx_hw := u8((word >> 16) & 0x1F)
|
|
return Operand{
|
|
mem = Memory{
|
|
base = Register(REG_X | u16(base_hw)),
|
|
index = Register(REG_X | u16(idx_hw)),
|
|
mode = .REG_OFFSET,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
case .SVE_OFFSET_BASE_SI:
|
|
base_hw := u8((word >> 5) & 0x1F)
|
|
imm := i32((word >> 16) & 0xF)
|
|
if imm & 0x8 != 0 { imm |= ~i32(0xF) }
|
|
return Operand{
|
|
mem = Memory{
|
|
base = Register(REG_X | u16(base_hw)),
|
|
index = NONE,
|
|
disp = imm,
|
|
mode = .OFFSET,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
|
|
// ---- SME ZA tile fields ----
|
|
case .ZA_TILE_NUM_B:
|
|
return Operand{immediate = 0, kind = .IMMEDIATE, size = 1}
|
|
case .ZA_TILE_NUM_H:
|
|
return Operand{immediate = i64((word >> 22) & 0x1), kind = .IMMEDIATE, size = 1}
|
|
case .ZA_TILE_NUM_S:
|
|
return Operand{immediate = i64((word >> 22) & 0x3), kind = .IMMEDIATE, size = 1}
|
|
case .ZA_TILE_NUM_D:
|
|
return Operand{immediate = i64((word >> 21) & 0x7), kind = .IMMEDIATE, size = 1}
|
|
case .SME_PATTERN_FIELD:
|
|
return Operand{immediate = i64((word >> 5) & 0xF), kind = .IMMEDIATE, size = 1}
|
|
|
|
// ---- SVE gather/scatter + vector-base memory ----
|
|
case .SVE_OFFSET_BASE_VEC:
|
|
base_hw := u8((word >> 5) & 0x1F)
|
|
idx_hw := u8((word >> 16) & 0x1F)
|
|
return Operand{
|
|
mem = Memory{
|
|
base = Register(REG_X | u16(base_hw)),
|
|
index = Register(REG_Z | u16(idx_hw)),
|
|
mode = .REG_OFFSET,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
case .SVE_OFFSET_VEC_BASE:
|
|
base_hw := u8((word >> 5) & 0x1F)
|
|
imm := i32((word >> 16) & 0x1F)
|
|
return Operand{
|
|
mem = Memory{
|
|
base = Register(REG_Z | u16(base_hw)),
|
|
disp = imm,
|
|
mode = .OFFSET,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
|
|
// ---- SVE indexed lane field ----
|
|
case .SVE_FMLA_IDX_H:
|
|
v := ((word >> 22) & 0x1) << 2 | ((word >> 19) & 0x3)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
|
|
case .SVE_FMLA_IDX_S:
|
|
v := (word >> 19) & 0x3
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
|
|
case .SVE_FMLA_IDX_D:
|
|
v := (word >> 20) & 0x1
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
|
|
|
|
// ---- SME tile slice descriptor (round-trip back to the packed form) ----
|
|
//
|
|
// Decode is the inverse of the packer: tile_num and imm bits live in
|
|
// instruction bits 3:0 (packed per element size), Ws at bits 14:13,
|
|
// V flag at bit 15.
|
|
case .SME_SLICE_B:
|
|
vflag := (word >> 15) & 0x1
|
|
ws := (word >> 13) & 0x3
|
|
imm := word & 0xF
|
|
v := imm | (vflag << 4) | (ws << 5)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
|
|
case .SME_SLICE_H:
|
|
vflag := (word >> 15) & 0x1
|
|
ws := (word >> 13) & 0x3
|
|
imm := word & 0x7
|
|
tile := (word >> 3) & 0x1
|
|
v := imm | (vflag << 4) | (ws << 5) | (tile << 7)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
|
|
case .SME_SLICE_W:
|
|
vflag := (word >> 15) & 0x1
|
|
ws := (word >> 13) & 0x3
|
|
imm := word & 0x3
|
|
tile := (word >> 2) & 0x3
|
|
v := imm | (vflag << 4) | (ws << 5) | (tile << 7)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
|
|
case .SME_SLICE_D:
|
|
vflag := (word >> 15) & 0x1
|
|
ws := (word >> 13) & 0x3
|
|
imm := word & 0x1
|
|
tile := (word >> 1) & 0x7
|
|
v := imm | (vflag << 4) | (ws << 5) | (tile << 7)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
|
|
case .SME_SLICE_Q:
|
|
vflag := (word >> 15) & 0x1
|
|
ws := (word >> 13) & 0x3
|
|
tile := word & 0xF
|
|
v := (vflag << 4) | (ws << 5) | (tile << 7)
|
|
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
|
|
|
|
// ---- Batch 3 misc immediates ----
|
|
case .ENC_FCMLA_ROT:
|
|
return Operand{immediate = i64((word >> 12) & 0x3), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_FCADD_ROT:
|
|
return Operand{immediate = i64((word >> 12) & 0x1), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_SVE_PRFOP:
|
|
return Operand{immediate = i64(word & 0xF), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_LDRAA_IMM10:
|
|
v := i32((word >> 12) & 0x3FF)
|
|
if v & 0x200 != 0 { v |= ~i32(0x3FF) }
|
|
return Operand{immediate = i64(v << 3), kind = .IMMEDIATE, size = 2}
|
|
|
|
// ---- Batch 5 ----
|
|
case .ENC_LSL_IMM_W:
|
|
// Recover shift from imms: imms = 31 - imm.
|
|
imms := (word >> 10) & 0x1F
|
|
return Operand{immediate = i64((31 - imms) & 0x1F), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_LSL_IMM_X:
|
|
imms := (word >> 10) & 0x3F
|
|
return Operand{immediate = i64((63 - imms) & 0x3F), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_DUAL_RN_RM:
|
|
// Take the Rn slot (9:5) as the source register.
|
|
return Operand{reg = Register(REG_X | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4}
|
|
case .ENC_ROR_SHIFT:
|
|
return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1}
|
|
case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD:
|
|
return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4}
|
|
case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN:
|
|
return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4}
|
|
case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM:
|
|
return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = 4}
|
|
}
|
|
return {}
|
|
}
|
|
|
|
// reg_from_field reconstructs a Register from a 5-bit hw field at `shift`,
|
|
// choosing the right class per the form's Operand_Type. SP/WSP variants
|
|
// use the REG_XSP/REG_WSP class at hw=31; everything else uses REG_X/REG_W.
|
|
@(private="file")
|
|
reg_from_field :: #force_inline proc "contextless" (
|
|
word: u32, shift: u8, ot: Operand_Type,
|
|
) -> Operand {
|
|
hw := u16((word >> shift) & 0x1F)
|
|
cls: u16 = REG_X
|
|
#partial switch ot {
|
|
case .W_REG: cls = REG_W
|
|
case .X_REG: cls = REG_X
|
|
case .WSP_REG: cls = hw == 31 ? REG_WSP : REG_W
|
|
case .XSP_REG: cls = hw == 31 ? REG_XSP : REG_X
|
|
case .B_REG: cls = REG_B
|
|
case .H_REG: cls = REG_H
|
|
case .S_REG: cls = REG_S
|
|
case .D_REG: cls = REG_D
|
|
case .Q_REG: cls = REG_Q
|
|
case .V_REG,
|
|
.V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D,
|
|
.V_4H_FP16, .V_8H_FP16,
|
|
.V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D:
|
|
cls = REG_V
|
|
case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D:
|
|
cls = REG_Z
|
|
case .P_REG, .P_REG_MERGE, .P_REG_ZERO:
|
|
cls = REG_P
|
|
}
|
|
// SP class needs the special hw=31 marker; everything else uses the
|
|
// raw hw with the chosen class.
|
|
if (ot == .WSP_REG && hw == 31) || (ot == .XSP_REG && hw == 31) {
|
|
return Operand{reg = Register(cls | 31), kind = .REGISTER, size = 4}
|
|
}
|
|
return Operand{reg = Register(cls | hw), kind = .REGISTER, size = 4}
|
|
}
|