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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
37 lines
1.3 KiB
Odin
37 lines
1.3 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc
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// =============================================================================
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// PowerPC RELOCATIONS
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// =============================================================================
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//
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// PowerPC has two PC-relative branch forms in the base ISA:
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//
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// * I-form b/bl/ba/bla: 24-bit signed << 2 (±32MB)
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// * B-form bc/bca/bcl/bcla: 14-bit signed << 2 (±32KB) with BO/BI fixed
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//
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// Power ISA 3.1 prefixed PC-relative loads/stores extend the displacement
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// to 34 bits via the prefix word's R=1 form, but those are normally encoded
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// via the prefixed-immediate path, not via relocations.
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//
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// PC for PowerPC is the address of the current instruction (not pc+8 like
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// ARM). The resolver subtracts the current offset.
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Relocation_Type :: enum u8 {
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NONE = 0,
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BRANCH_I_24, // I-form: LI (24-bit signed << 2 at bits 2..25 LSB)
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BRANCH_B_14, // B-form: BD (14-bit signed << 2 at bits 2..15 LSB)
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PREFIXED_34, // Power ISA 3.1: 34-bit signed at IMM18(prefix)||D(suffix)
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}
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Relocation :: struct #packed {
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offset: u32, // byte offset into code buffer
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label_id: u32,
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addend: i32,
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type: Relocation_Type,
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size: u8, // 4 (base) or 8 (prefixed)
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inst_idx: u16,
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}
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#assert(size_of(Relocation) == 16)
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