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https://github.com/odin-lang/Odin.git
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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
141 lines
6.2 KiB
Odin
141 lines
6.2 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// AArch32 INSTRUCTION
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// =============================================================================
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//
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// Variable-length: A32 is always 4 bytes, T16 is 2 bytes, T32 is 4 bytes (two
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// halfwords). The `length` field is filled in by the encoder from the matched
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// Encoding entry's `bits` field via `inst_size_from_bits`.
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//
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// The `mode` field tells the encoder whether to dispatch to A32 or T32
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// encoding entries; for VFP/NEON entries the encoder applies bit-28 swap as
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// documented in encoding_types.odin.
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Instruction_Flags :: bit_field u8 {
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sets_flags: bool | 1, // S bit (writes APSR.NZCV)
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wide: bool | 1, // force T32 wide form when both T16 + T32 exist
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_: u8 | 6,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 18 = 68
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mnemonic: Mnemonic, // 2
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cond: u8, // 0..15 (AL=14)
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operand_count: u8, // 0..4
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flags: Instruction_Flags, // 1
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mode: Mode, // 1 (A32 or T32)
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length: u8, // 2 or 4 bytes
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// Form-id hint: when non-zero, this is (1 + the index into
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// ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder
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// uses it as a tie-breaker for shape-ambiguous entries (NEON size variants
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// share an operand shape but live in distinct entries with different fixed
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// bits). User-constructed instructions leave it at 0; the encoder then
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// falls back to first-shape-match. Stored as u16 over the two padding bytes.
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form_id: u16,
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_: [7]u8,
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}
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#assert(size_of(Instruction) == 88)
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// =============================================================================
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// Builders
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = mode == .A32 ? 4 : 2, mode = mode, cond = 14}
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}
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// 1-operand
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(r), {}, {}, {}}}
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}
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@(require_results)
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inst_i :: #force_inline proc "contextless" (m: Mnemonic, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_imm(v), {}, {}, {}}}
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}
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// 2-operand
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rm: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rm), {}, {}}}
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}
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_imm(v), {}, {}}}
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}
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// 3-operand data-proc (ADD/SUB/AND/etc.)
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}}}
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}
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_imm(v), {}}}
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}
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@(require_results)
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inst_r_r_r_shifted :: #force_inline proc "contextless" (
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m: Mnemonic, rd, rn, rm: Register, st: Shift_Type, amt: u8, mode: Mode = .A32,
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) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg_shifted(rm, st, amt), {}}}
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}
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// 4-operand MLA / MLS / SMLAL etc.
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@(require_results)
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inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra)}}
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}
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// Memory load/store
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_mem(mm), {}, {}}}
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}
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@(require_results)
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inst_store :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory, mode: Mode = .A32) -> Instruction {
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return inst_load(m, rd, mm, mode)
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}
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// LDM/STM/PUSH/POP block move
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@(require_results)
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inst_block :: #force_inline proc "contextless" (m: Mnemonic, base: Register, mask: u16, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(base), op_reg_list(mask), {}, {}}}
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}
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// Branches with label
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_label(label_id), {}, {}, {}}}
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}
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// Set condition code on any builder
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@(require_results)
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inst_set_cond :: #force_inline proc "contextless" (inst: Instruction, cond: u8) -> Instruction {
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out := inst
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out.cond = cond
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return out
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}
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// Set S flag (sets APSR.NZCV)
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@(require_results)
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inst_set_flags :: #force_inline proc "contextless" (inst: Instruction) -> Instruction {
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out := inst
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out.flags.sets_flags = true
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return out
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}
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