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https://github.com/odin-lang/Odin.git
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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
70 lines
2.5 KiB
Odin
70 lines
2.5 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// AArch32 RELOCATIONS
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// =============================================================================
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//
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// AArch32 has many PC-relative forms because both A32 and T32 modes encode
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// branches with varying displacement widths:
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//
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// * A32 B/BL: 24-bit signed << 2 (-32MB..+32MB)
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// * A32 BLX imm: 24-bit signed << 2 + H bit (half-word align for arm->thumb)
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// * T32 unconditional B: 25-bit signed (S/J1/J2/imm10/imm11 scattered, ±16MB)
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// * T32 conditional B: 21-bit signed (cond + S/J1/J2/imm6/imm11 scattered, ±1MB)
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// * T16 unconditional B: 12-bit signed << 1 (±2KB)
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// * T16 conditional B: 9-bit signed << 1 (±256B)
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// * T16 CBZ/CBNZ: 7-bit unsigned << 1 (forward only)
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// * ADR/LDR-literal: PC-relative literal pool access
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//
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// PC for arm32 is always (current_inst_addr + 8) in A32 / (+4) in T32.
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// The relocation resolver bakes this in.
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Relocation_Type :: enum u8 {
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NONE = 0,
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// A32 branches
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BRANCH_A32_24, // B / BL, 24-bit signed << 2
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BLX_A32, // BLX imm, 24-bit signed << 2 + H bit at bit 24
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// T32 branches
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BRANCH_T32_25, // T32 B unconditional (J1/J2 + imm10 + imm11)
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BRANCH_T32_21, // T32 B<cond> (S + cond + imm6 + J1/J2 + imm11)
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// T16 branches
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BRANCH_T16_11, // T16 B unconditional (signed 11-bit << 1)
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BRANCH_T16_8, // T16 B<cond> (signed 8-bit << 1)
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BRANCH_T16_CBZ, // T16 CBZ/CBNZ (i + imm5 + Rn)
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// T32 low-overhead loops (ARMv8.1-M)
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BRANCH_T32_WLS, // WLS / WLSTP imm11
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BRANCH_T32_LE, // LE / LETP imm11
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// T32 Branch Future (ARMv8.1-M)
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BF_BOFF_T32, // bf-point: imm4 at hw0[10:7] = (label - (PC+4))/2
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BF_BLOC_T32, // branch target: J at hw1[11] + imm10 at hw1[10:1]
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// Literal load (ADR / LDR PC-rel)
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LDR_LITERAL_A32, // signed 12-bit (U bit + imm12)
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LDR_LITERAL_T32, // signed 12-bit (U bit + imm12) Thumb-2
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LDR_LITERAL_T16, // unsigned 8-bit << 2 (Thumb-1 PC-rel)
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ADR_A32, // ADR encoded as ADD/SUB to PC
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ADR_T32,
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ADR_T16, // Thumb-1 ADR (imm8 << 2)
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// Absolute forms via MOVW + MOVT pair
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MOVW_ABS, // imm16 low half
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MOVT_ABS, // imm16 high half
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}
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Relocation :: struct #packed {
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offset: u32,
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label_id: u32,
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addend: i32,
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type: Relocation_Type,
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size: u8, // 2 (T16) or 4 (A32/T32)
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inst_idx: u16,
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}
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#assert(size_of(Relocation) == 16)
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