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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
76 lines
2.6 KiB
Odin
76 lines
2.6 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos65816
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// =============================================================================
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// INSTRUCTION
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// =============================================================================
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Instruction_Flags :: bit_field u8 {
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_: u8 | 8,
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}
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Instruction :: struct #packed {
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ops: [2]Operand `fmt:"v,operand_count"`, // 20 bytes (only MVN/MVP use 2; rest use 0 or 1)
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mnemonic: Mnemonic, // 2
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operand_count: u8, // 1
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flags: Instruction_Flags, // 1
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length: u8, // 1
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_: [7]u8, // 3
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}
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#assert(size_of(Instruction) == 32)
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 1}
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}
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@(require_results)
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inst_a :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 1,
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ops = {op_reg(A), {}}}
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}
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@(require_results)
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inst_i8 :: #force_inline proc "contextless" (m: Mnemonic, v: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 2,
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ops = {op_imm8(v), {}}}
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}
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@(require_results)
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inst_i16 :: #force_inline proc "contextless" (m: Mnemonic, v: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 3,
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ops = {op_imm16(v), {}}}
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}
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@(require_results)
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inst_m :: #force_inline proc "contextless" (m: Mnemonic, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 0,
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ops = {op_mem(mm), {}}}
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}
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@(require_results)
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inst_rel :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 2,
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ops = {op_label(label_id, 1), {}}}
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}
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@(require_results)
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inst_rel_long :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 3,
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ops = {op_label(label_id, 2), {}}}
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}
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// MVN/MVP src, dst -- caller writes "natural" order; encoder reverses to
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// the WDC-specified opcode | dst_bank | src_bank byte layout.
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@(require_results)
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inst_block_move :: #force_inline proc "contextless" (m: Mnemonic, src_bank, dst_bank: u8) -> Instruction {
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return Instruction{
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mnemonic = m, operand_count = 2, length = 3,
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ops = {
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Operand{immediate = i64(src_bank), kind = .IMMEDIATE, size = 1},
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Operand{immediate = i64(dst_bank), kind = .IMMEDIATE, size = 1},
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},
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}
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}
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