mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-20 00:52:33 +00:00
95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
74 lines
2.5 KiB
Odin
74 lines
2.5 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
|
|
|
|
package rexcode_riscv
|
|
|
|
// =============================================================================
|
|
// RISC-V OPERANDS
|
|
// =============================================================================
|
|
//
|
|
// Same kind-tagged shape as the other arches. Memory is a single
|
|
// `(base GPR, signed 12-bit displacement)` pair -- RISC-V's only
|
|
// addressing mode is `disp12(base)`, with no index register, no scale,
|
|
// and no PC-relative form (PC-rel work is done by AUIPC + add/load pairs).
|
|
//
|
|
// RELATIVE operands cover both 13-bit branches (B-type) and 21-bit
|
|
// jumps (J-type); the encoding form's Operand_Encoding tells the
|
|
// encoder which scatter pattern to apply.
|
|
|
|
Operand_Kind :: enum u8 {
|
|
NONE,
|
|
REGISTER,
|
|
IMMEDIATE,
|
|
MEMORY,
|
|
RELATIVE,
|
|
}
|
|
|
|
Memory :: struct #packed {
|
|
base: Register, // GPR base
|
|
_: u16,
|
|
disp: i32, // sign-extended 12-bit displacement
|
|
}
|
|
#assert(size_of(Memory) == 8)
|
|
|
|
@(require_results)
|
|
mem :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory {
|
|
return Memory{base = base, disp = disp}
|
|
}
|
|
|
|
Operand :: struct #packed {
|
|
using _: struct #raw_union {
|
|
reg: Register, // REGISTER (int or FP)
|
|
mem: Memory,
|
|
immediate: i64,
|
|
relative: i64, // label id pre-resolution; byte offset post
|
|
},
|
|
kind: Operand_Kind,
|
|
size: u8,
|
|
}
|
|
#assert(size_of(Operand) == 10)
|
|
|
|
@(require_results)
|
|
op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { return Operand{reg = r, kind = .REGISTER, size = 4} }
|
|
@(require_results)
|
|
op_imm :: #force_inline proc "contextless" (v: i64, size: u8) -> Operand { return Operand{immediate = v, kind = .IMMEDIATE, size = size} }
|
|
@(require_results)
|
|
op_mem :: #force_inline proc "contextless" (m: Memory) -> Operand { return Operand{mem = m, kind = .MEMORY, size = 4} }
|
|
@(require_results)
|
|
op_label :: #force_inline proc "contextless" (label_id: u32, size: u8 = 2) -> Operand {
|
|
return Operand{relative = i64(label_id), kind = .RELATIVE, size = size}
|
|
}
|
|
@(require_results)
|
|
op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand {
|
|
return Operand{relative = off, kind = .RELATIVE, size = 2}
|
|
}
|
|
|
|
// Typed constructors
|
|
@(require_results)
|
|
op_gpr :: #force_inline proc "contextless" (g: GPR) -> Operand {
|
|
return Operand{reg = Register(REG_GPR | u16(g)), kind = .REGISTER, size = 4}
|
|
}
|
|
@(require_results)
|
|
op_fpr :: #force_inline proc "contextless" (f: FPR) -> Operand {
|
|
return Operand{reg = Register(REG_FPR | u16(f)), kind = .REGISTER, size = 4}
|
|
}
|