mirror of
https://github.com/odin-lang/Odin.git
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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
92 lines
3.9 KiB
Odin
92 lines
3.9 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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// =============================================================================
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// RSP INSTRUCTION
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// =============================================================================
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Instruction_Flags :: bit_field u8 {
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_: u8 | 8,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 48 bytes
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mnemonic: Mnemonic, // 2 bytes
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operand_count: u8, // 1 byte
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flags: Instruction_Flags, // 1 byte
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length: u8, // 1 byte (always 4)
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_: [11]u8, // 11 bytes
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}
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#assert(size_of(Instruction) == 64)
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// =============================================================================
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// Builders (mirror x86/mips conventions)
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 4}
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}
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, a: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4,
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ops = {op_reg(a), {}, {}, {}}}
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}
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, d, s: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(d), op_reg(s), {}, {}}}
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}
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, d, s1, s2: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(d), op_reg(s1), op_reg(s2), {}}}
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}
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rt, rs: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rt), op_reg(rs), op_imm(imm, 2), {}}}
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}
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rt), op_imm(imm, 2), {}, {}}}
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}
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@(require_results)
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inst_r_m :: #force_inline proc "contextless" (m: Mnemonic, r: Register, mm: Memory, size: u8 = 4) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(r), op_mem(mm, size), {}, {}}}
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}
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// Vector ALU: 3-operand vector op with optional element selector on vt.
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@(require_results)
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inst_v_v_v :: #force_inline proc "contextless" (m: Mnemonic, vd, vs, vt: Register, vt_element: u8 = 0) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_vr(vd), op_vr(vs), op_vr(vt, vt_element), {}}}
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}
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// Vector load/store: $vt[element], offset(base).
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@(require_results)
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inst_v_vmem :: #force_inline proc "contextless" (m: Mnemonic, vt: Register, vmem_op: Vector_Mem) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_vr(vt, vmem_op.element), op_vmem(vmem_op, 16), {}, {}}}
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}
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// Branch helpers
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@(require_results)
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inst_branch1 :: #force_inline proc "contextless" (m: Mnemonic, rs: Register, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rs), op_label(label_id), {}, {}}}
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}
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@(require_results)
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inst_branch2 :: #force_inline proc "contextless" (m: Mnemonic, rs, rt: Register, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rs), op_reg(rt), op_label(label_id), {}}}
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}
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@(require_results)
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inst_jump :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4,
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ops = {op_label(label_id), {}, {}, {}}}
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}
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