mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-20 00:52:33 +00:00
95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
84 lines
2.2 KiB
Odin
84 lines
2.2 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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// =============================================================================
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// N64 RSP MNEMONICS
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// =============================================================================
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//
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// Two halves: a strict MIPS I subset for the scalar core (no
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// MULT/DIV/HI/LO/SYNC/LWL/LWR/SWL/SWR/64-bit), and the vector unit
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// (VMULF.../VLT.../VRCP.../etc. + LBV..LTV loads, SBV..STV stores).
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Mnemonic :: enum u16 {
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INVALID = 0,
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// -------------------------------------------------------------------------
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// Scalar core — MIPS I subset
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// -------------------------------------------------------------------------
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// R-type arithmetic / logical / shift
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ADD, ADDU, SUB, SUBU,
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AND, OR, XOR, NOR,
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SLT, SLTU,
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SLL, SRL, SRA,
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SLLV, SRLV, SRAV,
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// I-type
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ADDI, ADDIU,
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SLTI, SLTIU,
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ANDI, ORI, XORI,
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LUI,
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// Branches (with delay slot)
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BEQ, BNE, BLEZ, BGTZ,
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BLTZ, BGEZ, BLTZAL, BGEZAL,
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// Jumps
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J, JAL, JR, JALR,
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// Load / Store (no LWL/LWR/SWL/SWR on the RSP).
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LB, LH, LW, LBU, LHU,
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SB, SH, SW,
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// System
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BREAK, NOP,
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// Coprocessor moves
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MFC0, MTC0,
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MFC2, MTC2, CFC2, CTC2,
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// -------------------------------------------------------------------------
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// Vector ALU (COP2, CO=1; opcode 0x12 with funct selecting)
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// -------------------------------------------------------------------------
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VMULF, VMULU,
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VMUDL, VMUDM, VMUDN, VMUDH,
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VMACF, VMACU,
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VMADL, VMADM, VMADN, VMADH,
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VADD, VSUB, VABS,
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VADDC, VSUBC,
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VSAR,
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VLT, VEQ, VNE, VGE,
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VCL, VCH, VCR, VMRG,
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VAND, VNAND, VOR, VNOR, VXOR, VNXOR,
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VRCP, VRCPL, VRCPH,
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VMOV,
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VRSQ, VRSQL, VRSQH,
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VNOP,
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// -------------------------------------------------------------------------
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// Vector loads (LWC2 = opcode 0x32 with op2 selector)
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// -------------------------------------------------------------------------
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LBV, LSV, LLV, LDV, LQV, LRV,
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LPV, LUV, LHV, LFV, LWV, LTV,
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// -------------------------------------------------------------------------
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// Vector stores (SWC2 = opcode 0x3A with op2 selector)
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// -------------------------------------------------------------------------
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SBV, SSV, SLV, SDV, SQV, SRV,
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SPV, SUV, SHV, SFV, SWV, STV,
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}
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