mirror of
https://github.com/odin-lang/Odin.git
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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
93 lines
2.7 KiB
Odin
93 lines
2.7 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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// =============================================================================
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// RSP OPERANDS
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// =============================================================================
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//
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// Same shape as mips/operands.odin; the addition for the RSP is that
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// vector operands carry an element selector. Memory comes in two
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// flavours: scalar (base + 16-bit signed disp; standard MIPS) and
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// vector (base + 7-bit element-scaled offset + element selector).
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Operand_Kind :: enum u8 {
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NONE,
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REGISTER,
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VECTOR_REG, // vector register with element selector
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MEMORY,
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VECTOR_MEM, // vector memory: base + 7-bit offset + element selector
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IMMEDIATE,
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RELATIVE,
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}
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Memory :: struct #packed {
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base: Register, // GPR base
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_: u16,
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disp: i32,
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}
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#assert(size_of(Memory) == 8)
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Vector_Mem :: struct #packed {
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base: Register, // GPR base
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element: u8, // element selector (0-15; restricted by op)
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_: u8,
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offset: i32, // -64..63 after element-size scaling
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}
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#assert(size_of(Vector_Mem) == 8)
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@(require_results)
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mem :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory {
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return Memory{base = base, disp = disp}
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}
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@(require_results)
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vmem :: #force_inline proc "contextless" (base: Register, element: u8, offset: i32) -> Vector_Mem {
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return Vector_Mem{base = base, element = element, offset = offset}
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}
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Operand :: struct #packed {
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using _: struct #raw_union {
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reg: Register, // for REGISTER and VECTOR_REG
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mem: Memory,
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vmem: Vector_Mem,
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immediate: i64,
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relative: i64,
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},
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kind: Operand_Kind, // 1 byte
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size: u8, // 1 byte
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element: u8, // 1 byte — for VECTOR_REG
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_: [1]u8,
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}
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#assert(size_of(Operand) == 12)
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@(require_results)
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op_reg :: #force_inline proc "contextless" (r: Register) -> Operand {
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return Operand{reg = r, kind = .REGISTER, size = 4}
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}
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@(require_results)
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op_vr :: #force_inline proc "contextless" (r: Register, element: u8 = 0) -> Operand {
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return Operand{reg = r, kind = .VECTOR_REG, size = 16, element = element}
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}
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@(require_results)
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op_mem :: #force_inline proc "contextless" (m: Memory, size: u8) -> Operand {
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return Operand{mem = m, kind = .MEMORY, size = size}
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}
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@(require_results)
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op_vmem :: #force_inline proc "contextless" (m: Vector_Mem, size: u8) -> Operand {
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return Operand{vmem = m, kind = .VECTOR_MEM, size = size}
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}
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@(require_results)
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op_imm :: #force_inline proc "contextless" (v: i64, size: u8) -> Operand {
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return Operand{immediate = v, kind = .IMMEDIATE, size = size}
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}
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@(require_results)
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op_label :: #force_inline proc "contextless" (label_id: u32) -> Operand {
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return Operand{relative = i64(label_id), kind = .RELATIVE, size = 4}
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}
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