mirror of
https://github.com/odin-lang/Odin.git
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078015bc34
Targeted branchless revert + the pre-matched form fast path, and a fix
for a pre-existing bug the latter surfaced.
(a) Revert the two speculative-write spots from the prior branchless pass
(legacy-prefix emission, widened displacement store, ENCODE_TAIL_SLACK)
back to predicted branches. In real streams a legacy prefix is almost
always absent and disp size is stable, so those branches are ~free and
the unconditional stores only added work. Every class got faster
(RET 19->17.5, MOV r,r 52->46.6, VADDPS 42.8->39.3 ns).
(b) Pre-matched form hint. Instruction.enc_hint (in the existing 11-byte
padding, idx+1 biased; 0 = matcher path) lets a typed builder that maps
to a single value-independent form bake the global form index, so
encode() skips the O(forms) match scan -- and, in a varied stream, its
unpredictable branches. Generated for non-immediate forms only (value-
dependent imm8/imm32 selection stays on the matcher). On a 100k mixed
typed-builder stream: 47.3 -> 30.2 ns/inst (-36%), byte-identical to the
matcher path -- ~2x the original baseline for codegen.
Repair the typed inst_/emit_ builders. They were non-functional: the
generator cast the hw-only typed enum straight to Register
(Register(GPR64.RAX) -> class 0), so every typed-builder operand was
rejected by the matcher (encode returned empty). Untested because the
suite builds via the generic constructors. Now they build through the
class-correct op_gpr64/op_xmm/... path (op_* already used by 3+ operand
builders), emit_ reuses inst_, and a new 30-case consistency suite
asserts typed == generic (llvm-verified) and hint == matcher.
gen/builders/check/test/idempotent all green; 2276 cases.
262 lines
10 KiB
Odin
262 lines
10 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_x86
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// =============================================================================
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// SECTION: 3. INSTRUCTION
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// =============================================================================
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// -----------------------------------------------------------------------------
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// SECTION: 3.1 Instruction Flags and Rep Prefix
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// -----------------------------------------------------------------------------
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// Instruction flags for prefixes and modifiers
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Instruction_Flags :: bit_field u8 {
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lock: bool | 1,
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rep: Rep | 2,
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segment: u8 | 3, // 0=none, 1=ES, 2=CS, 3=SS, 4=DS, 5=FS, 6=GS
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addr32: bool | 1, // address size override (32-bit in 64-bit mode)
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data16: bool | 1, // operand size override (for 16-bit operands)
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}
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Rep :: enum u8 {
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NONE,
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REP, // REP/REPE/REPZ
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REPNE, // REPNE/REPNZ
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}
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// -----------------------------------------------------------------------------
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// SECTION: 3.2 Instruction STruct
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// -----------------------------------------------------------------------------
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count`, // 48 bytes
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mnemonic: Mnemonic, // 2 bytes
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operand_count: u8, // 1 byte
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flags: Instruction_Flags, // 1 byte
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length: u8, // 1 byte (filled by decoder, used for iteration)
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enc_hint: u16, // 2 bytes (pre-matched form, +1 biased; 0 = none)
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_: [9]u8, // 9 bytes
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}
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#assert(size_of(Instruction) == 64)
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// Pre-matched encoding hint: a typed builder that maps to exactly one encoding
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// form (no value-dependent immediate selection) stores `global_form_index + 1`
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// in `Instruction.enc_hint`, letting encode() skip the form-match scan. 0 means
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// "no hint" -- the zero value, so every hand-built / generic-builder / decoded
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// instruction stays on the matching path unchanged.
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ENC_HINT_NONE :: u16(0)
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@(require_results)
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with_hint :: #force_inline proc "contextless" (inst: Instruction, hint: u16) -> Instruction {
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inst := inst
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inst.enc_hint = hint
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return inst
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}
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// -----------------------------------------------------------------------------
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// SECTION: 7.9 Instruction Builder Helpers
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// -----------------------------------------------------------------------------
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// Convenient instruction builders for common patterns
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 2,
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ops = {op_reg(destination), op_reg(source), {}, {}},
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}
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}
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@(require_results)
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inst_r_m :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Register, source: Memory, size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 2,
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ops = {op_reg(destination), op_mem(source, size), {}, {}},
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}
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}
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@(require_results)
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inst_m_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Memory, size: u8, source: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 2,
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ops = {op_mem(destination, size), op_reg(source), {}, {}},
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}
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}
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Register, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 2,
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ops = {op_reg(destination), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}, {}},
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}
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}
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@(require_results)
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inst_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, r: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 1,
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ops = {op_reg(r), {}, {}, {}},
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}
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}
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@(require_results)
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inst_m :: #force_inline proc "contextless" (mnemonic: Mnemonic, m: Memory, size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 1,
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ops = {op_mem(m, size), {}, {}, {}},
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}
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}
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@(require_results)
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inst_none :: #force_inline proc "contextless" (mnemonic: Mnemonic) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 0,
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}
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}
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@(require_results)
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inst_rel :: #force_inline proc "contextless" (mnemonic: Mnemonic, label_id: u32, size: u8 = 4) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 1,
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ops = {op_label(label_id, size), {}, {}, {}},
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}
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}
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// 3-operand register instructions (VEX/EVEX: VADDPS xmm0, xmm1, xmm2)
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1, source2: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_reg(destination), op_reg(source1), op_reg(source2), {}},
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}
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}
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// 3-operand register-register-memory (VEX/EVEX: VADDPS xmm0, xmm1, [mem])
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@(require_results)
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inst_r_r_m :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1: Register, source2: Memory, size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_reg(destination), op_reg(source1), op_mem(source2, size), {}},
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}
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}
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// 3-operand register-register-immediate (e.g., SHLD r64, r64, imm8)
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source: Register, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_reg(destination), op_reg(source), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}},
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}
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}
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// Memoryory-immediate (MOV [mem], imm32)
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@(require_results)
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inst_m_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Memory, size: u8, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 2,
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ops = {op_mem(destination, size), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}, {}},
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}
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}
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// Single immediate (PUSH imm32, RET imm16, INT imm8, etc.)
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@(require_results)
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inst_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 1,
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ops = {Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}, {}, {}},
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}
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}
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// 3-operand register-memory-immediate (IMUL r64, m64, imm32)
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@(require_results)
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inst_r_m_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Register, source: Memory, mem_size: u8, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_reg(destination), op_mem(source, mem_size), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}},
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}
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}
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// 3-operand memory-register-immediate (SHLD m64, r64, imm8)
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@(require_results)
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inst_m_r_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Memory, mem_size: u8, source: Register, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_mem(destination, mem_size), op_reg(source), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}, {}},
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}
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}
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// Relative offset (JMP rel8, JCC rel32, etc.) - uses raw offset, not label
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@(require_results)
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inst_rel_offset :: #force_inline proc "contextless" (mnemonic: Mnemonic, offset: i64, offset_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 1,
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ops = {Operand{immediate = offset, kind = .RELATIVE, size = offset_size}, {}, {}, {}},
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}
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}
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// 3-operand register-memory-register (BEXTR r64, m64, r64)
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@(require_results)
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inst_r_m_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination: Register, source1: Memory, mem_size: u8, source2: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 3,
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ops = {op_reg(destination), op_mem(source1, mem_size), op_reg(source2), {}},
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}
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}
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// 4-operand register instructions (EVEX with 4 operands)
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@(require_results)
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inst_r_r_r_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1, source2, source3: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 4,
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ops = {op_reg(destination), op_reg(source1), op_reg(source2), op_reg(source3)},
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}
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}
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// 4-operand: 3 registers + immediate (VCMPPS xmm, xmm, xmm, imm8)
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@(require_results)
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inst_r_r_r_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1, source2: Register, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 4,
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ops = {op_reg(destination), op_reg(source1), op_reg(source2), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}},
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}
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}
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// 4-operand: 2 registers + memory + immediate (VCMPPS xmm, xmm, m128, imm8)
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@(require_results)
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inst_r_r_m_i :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1: Register, source2: Memory, mem_size: u8, immediate: i64, immediate_size: u8) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 4,
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ops = {op_reg(destination), op_reg(source1), op_mem(source2, mem_size), Operand{immediate = immediate, kind = .IMMEDIATE, size = immediate_size}},
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}
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}
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// 4-operand: 2 registers + memory + register (VBLENDVPS xmm, xmm, m128, xmm)
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@(require_results)
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inst_r_r_m_r :: #force_inline proc "contextless" (mnemonic: Mnemonic, destination, source1: Register, source2: Memory, mem_size: u8, source3: Register) -> Instruction {
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return Instruction{
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mnemonic = mnemonic,
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operand_count = 4,
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ops = {op_reg(destination), op_reg(source1), op_mem(source2, mem_size), op_reg(source3)},
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}
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}
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