gingerBill 7dd33b5e48 Implement #pre/#post` memory operand forms

2026-08-31 18:31:37 +01:00

..

tablegen

Implement #pre/#post` memory operand forms

2026-08-31 18:31:37 +01:00

tables

Implement #pre/#post` memory operand forms

2026-08-31 18:31:37 +01:00

tests

rexcode/arm64: FP/SIMD pre/post-indexed loads and stores

2026-08-30 19:11:20 -04:00

tools

rexcode/arm64: merge system registers into Register

2026-08-30 18:23:06 -04:00

bitmask.odin

rexcode: re-house ISA packages under core:rexcode/isa/<arch>

2026-06-18 19:03:27 -04:00

clobber_types.odin

rexcode/arm64: an instruction can hold five operands

2026-08-28 19:29:20 -04:00

decoder.odin

rexcode/arm64: extended-register addressing, and the shift that printed its S bit

2026-08-30 18:36:34 -04:00

encoder.odin

rexcode/arm64: extended-register addressing, and the shift that printed its S bit

2026-08-30 18:36:34 -04:00

encoding_types.odin

rexcode/arm64: extended-register addressing, and the shift that printed its S bit

2026-08-30 18:36:34 -04:00

instructions.odin

rexcode/arm64: an instruction can hold five operands

2026-08-28 19:29:20 -04:00

mnemonic_builders.odin

rexcode/arm64: merge system registers into Register

2026-08-30 18:23:06 -04:00

mnemonics.odin

rexcode/arm64: the last of the SVE and SME gaps

2026-08-28 19:36:08 -04:00

operands.odin

rexcode/arm64: merge system registers into Register

2026-08-30 18:23:06 -04:00

printer.odin

rexcode/arm64: merge system registers into Register

2026-08-30 18:23:06 -04:00

registers.odin

rexcode/arm64: merge system registers into Register

2026-08-30 18:23:06 -04:00

reloc.odin

rexcode: re-house ISA packages under core:rexcode/isa/<arch>

2026-06-18 19:03:27 -04:00

tables.odin

rexcode/arm64: an instruction can hold five operands

2026-08-28 19:29:20 -04:00