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https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
126 lines
5.0 KiB
Odin
126 lines
5.0 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_riscv
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// =============================================================================
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// INSTRUCTION
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// =============================================================================
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//
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// All non-C base instructions are 4 bytes. The `length` field is
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// preserved for shape parity with arches that have variable-length
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// (mos65816, mos6502) -- here it's always 4.
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Instruction_Flags :: bit_field u8 {
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_: u8 | 8,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 64 bytes
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mnemonic: Mnemonic, // 2
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operand_count: u8, // 1
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flags: Instruction_Flags, // 1
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length: u8, // 1 -- always 4 for non-C
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_: [3]u8, // 3
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}
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#assert(size_of(Instruction) == 72)
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// =============================================================================
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// Builders (shape spelled out, comma-separated)
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 4}
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}
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// R-type: rd, rs1, rs2
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1, rs2: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_reg(rs2), {}}}
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}
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// I-type (ALU): rd, rs1, imm12
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_imm(imm, 2), {}}}
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}
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// I-type (shift): rd, rs1, shamt
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@(require_results)
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inst_shift :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register, shamt: u8) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_imm(i64(shamt), 1), {}}}
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}
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// I-type load: rd, disp(base)
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_mem(mm), {}, {}}}
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}
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// S-type store: rs2 (data), disp(base)
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@(require_results)
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inst_store :: #force_inline proc "contextless" (m: Mnemonic, rs2: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rs2), op_mem(mm), {}, {}}}
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}
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// U-type: rd, imm20
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@(require_results)
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inst_u :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_imm(imm, 4), {}, {}}}
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}
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// J-type: rd, label
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@(require_results)
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inst_jal :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_label(label_id, 4), {}, {}}}
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}
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// B-type branch: rs1, rs2, label
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, rs1, rs2: Register, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rs1), op_reg(rs2), op_label(label_id, 2), {}}}
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}
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// JALR: rd, rs1, imm12 (indirect jump with offset)
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@(require_results)
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inst_jalr :: #force_inline proc "contextless" (rd, rs1: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = .JALR, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_imm(imm, 2), {}}}
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}
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// CSR ops: rd, csr, rs1
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@(require_results)
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inst_csr :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, csr: u16, rs1: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_imm(i64(csr), 2), op_reg(rs1), {}}}
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}
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// CSR immediate ops: rd, csr, zimm5
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@(require_results)
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inst_csr_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, csr: u16, zimm5: u8) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_imm(i64(csr), 2), op_imm(i64(zimm5), 1), {}}}
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}
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// FP R4-type: rd, rs1, rs2, rs3 (FMADD/FMSUB/FNMADD/FNMSUB)
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@(require_results)
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inst_r4 :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1, rs2, rs3: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_reg(rs2), op_reg(rs3)}}
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}
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// FP R-type with 2 regs: rd, rs1 (FSQRT, FCVT, FMV, FCLASS, ...)
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_reg(rs1), {}, {}}}
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}
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