mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 16:42:33 +00:00
3684 lines
403 KiB
Odin
3684 lines
403 KiB
Odin
package rexcode_x86
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Generated by gen_decode_tables.odin from ENC_TABLE
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// Regenerate with: odin run tools/gen_decode_tables.odin -file && mv decoding_tables.odin
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//
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// =============================================================================
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// ModR/M Lookup Table
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// =============================================================================
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// Precomputed extraction of mod, reg, rm fields from ModR/M byte
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ModRM_Info :: struct #packed {
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mod: u8, // bits [7:6] - addressing mode
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reg: u8, // bits [5:3] - register or opcode extension
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rm: u8, // bits [2:0] - register or memory
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has_sib: bool, // rm==4 && mod!=3 (SIB byte follows)
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disp_size: u8, // displacement size: 0, 1, or 4 bytes
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}
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@(rodata)
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MODRM_TABLE := [256]ModRM_Info{
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{0, 0, 0, false, 0}, {0, 0, 1, false, 0}, {0, 0, 2, false, 0}, {0, 0, 3, false, 0},
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{0, 0, 4, true, 0}, {0, 0, 5, false, 4}, {0, 0, 6, false, 0}, {0, 0, 7, false, 0},
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{0, 1, 0, false, 0}, {0, 1, 1, false, 0}, {0, 1, 2, false, 0}, {0, 1, 3, false, 0},
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{0, 1, 4, true, 0}, {0, 1, 5, false, 4}, {0, 1, 6, false, 0}, {0, 1, 7, false, 0},
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{0, 2, 0, false, 0}, {0, 2, 1, false, 0}, {0, 2, 2, false, 0}, {0, 2, 3, false, 0},
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{0, 2, 4, true, 0}, {0, 2, 5, false, 4}, {0, 2, 6, false, 0}, {0, 2, 7, false, 0},
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{0, 3, 0, false, 0}, {0, 3, 1, false, 0}, {0, 3, 2, false, 0}, {0, 3, 3, false, 0},
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{0, 3, 4, true, 0}, {0, 3, 5, false, 4}, {0, 3, 6, false, 0}, {0, 3, 7, false, 0},
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{0, 4, 0, false, 0}, {0, 4, 1, false, 0}, {0, 4, 2, false, 0}, {0, 4, 3, false, 0},
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{0, 4, 4, true, 0}, {0, 4, 5, false, 4}, {0, 4, 6, false, 0}, {0, 4, 7, false, 0},
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{0, 5, 0, false, 0}, {0, 5, 1, false, 0}, {0, 5, 2, false, 0}, {0, 5, 3, false, 0},
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{0, 5, 4, true, 0}, {0, 5, 5, false, 4}, {0, 5, 6, false, 0}, {0, 5, 7, false, 0},
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{0, 6, 0, false, 0}, {0, 6, 1, false, 0}, {0, 6, 2, false, 0}, {0, 6, 3, false, 0},
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{0, 6, 4, true, 0}, {0, 6, 5, false, 4}, {0, 6, 6, false, 0}, {0, 6, 7, false, 0},
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{0, 7, 0, false, 0}, {0, 7, 1, false, 0}, {0, 7, 2, false, 0}, {0, 7, 3, false, 0},
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{0, 7, 4, true, 0}, {0, 7, 5, false, 4}, {0, 7, 6, false, 0}, {0, 7, 7, false, 0},
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{1, 0, 0, false, 1}, {1, 0, 1, false, 1}, {1, 0, 2, false, 1}, {1, 0, 3, false, 1},
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{1, 0, 4, true, 1}, {1, 0, 5, false, 1}, {1, 0, 6, false, 1}, {1, 0, 7, false, 1},
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{1, 1, 0, false, 1}, {1, 1, 1, false, 1}, {1, 1, 2, false, 1}, {1, 1, 3, false, 1},
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{1, 1, 4, true, 1}, {1, 1, 5, false, 1}, {1, 1, 6, false, 1}, {1, 1, 7, false, 1},
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{1, 2, 0, false, 1}, {1, 2, 1, false, 1}, {1, 2, 2, false, 1}, {1, 2, 3, false, 1},
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{1, 2, 4, true, 1}, {1, 2, 5, false, 1}, {1, 2, 6, false, 1}, {1, 2, 7, false, 1},
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{1, 3, 0, false, 1}, {1, 3, 1, false, 1}, {1, 3, 2, false, 1}, {1, 3, 3, false, 1},
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{1, 3, 4, true, 1}, {1, 3, 5, false, 1}, {1, 3, 6, false, 1}, {1, 3, 7, false, 1},
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{1, 4, 0, false, 1}, {1, 4, 1, false, 1}, {1, 4, 2, false, 1}, {1, 4, 3, false, 1},
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{1, 4, 4, true, 1}, {1, 4, 5, false, 1}, {1, 4, 6, false, 1}, {1, 4, 7, false, 1},
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{1, 5, 0, false, 1}, {1, 5, 1, false, 1}, {1, 5, 2, false, 1}, {1, 5, 3, false, 1},
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{1, 5, 4, true, 1}, {1, 5, 5, false, 1}, {1, 5, 6, false, 1}, {1, 5, 7, false, 1},
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{1, 6, 0, false, 1}, {1, 6, 1, false, 1}, {1, 6, 2, false, 1}, {1, 6, 3, false, 1},
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{1, 6, 4, true, 1}, {1, 6, 5, false, 1}, {1, 6, 6, false, 1}, {1, 6, 7, false, 1},
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{1, 7, 0, false, 1}, {1, 7, 1, false, 1}, {1, 7, 2, false, 1}, {1, 7, 3, false, 1},
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{1, 7, 4, true, 1}, {1, 7, 5, false, 1}, {1, 7, 6, false, 1}, {1, 7, 7, false, 1},
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{2, 0, 0, false, 4}, {2, 0, 1, false, 4}, {2, 0, 2, false, 4}, {2, 0, 3, false, 4},
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{2, 0, 4, true, 4}, {2, 0, 5, false, 4}, {2, 0, 6, false, 4}, {2, 0, 7, false, 4},
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{2, 1, 0, false, 4}, {2, 1, 1, false, 4}, {2, 1, 2, false, 4}, {2, 1, 3, false, 4},
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{2, 1, 4, true, 4}, {2, 1, 5, false, 4}, {2, 1, 6, false, 4}, {2, 1, 7, false, 4},
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{2, 2, 0, false, 4}, {2, 2, 1, false, 4}, {2, 2, 2, false, 4}, {2, 2, 3, false, 4},
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{2, 2, 4, true, 4}, {2, 2, 5, false, 4}, {2, 2, 6, false, 4}, {2, 2, 7, false, 4},
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{2, 3, 0, false, 4}, {2, 3, 1, false, 4}, {2, 3, 2, false, 4}, {2, 3, 3, false, 4},
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{2, 3, 4, true, 4}, {2, 3, 5, false, 4}, {2, 3, 6, false, 4}, {2, 3, 7, false, 4},
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{2, 4, 0, false, 4}, {2, 4, 1, false, 4}, {2, 4, 2, false, 4}, {2, 4, 3, false, 4},
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{2, 4, 4, true, 4}, {2, 4, 5, false, 4}, {2, 4, 6, false, 4}, {2, 4, 7, false, 4},
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{2, 5, 0, false, 4}, {2, 5, 1, false, 4}, {2, 5, 2, false, 4}, {2, 5, 3, false, 4},
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{2, 5, 4, true, 4}, {2, 5, 5, false, 4}, {2, 5, 6, false, 4}, {2, 5, 7, false, 4},
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{2, 6, 0, false, 4}, {2, 6, 1, false, 4}, {2, 6, 2, false, 4}, {2, 6, 3, false, 4},
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{2, 6, 4, true, 4}, {2, 6, 5, false, 4}, {2, 6, 6, false, 4}, {2, 6, 7, false, 4},
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{2, 7, 0, false, 4}, {2, 7, 1, false, 4}, {2, 7, 2, false, 4}, {2, 7, 3, false, 4},
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{2, 7, 4, true, 4}, {2, 7, 5, false, 4}, {2, 7, 6, false, 4}, {2, 7, 7, false, 4},
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{3, 0, 0, false, 0}, {3, 0, 1, false, 0}, {3, 0, 2, false, 0}, {3, 0, 3, false, 0},
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{3, 0, 4, false, 0}, {3, 0, 5, false, 0}, {3, 0, 6, false, 0}, {3, 0, 7, false, 0},
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{3, 1, 0, false, 0}, {3, 1, 1, false, 0}, {3, 1, 2, false, 0}, {3, 1, 3, false, 0},
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{3, 1, 4, false, 0}, {3, 1, 5, false, 0}, {3, 1, 6, false, 0}, {3, 1, 7, false, 0},
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{3, 2, 0, false, 0}, {3, 2, 1, false, 0}, {3, 2, 2, false, 0}, {3, 2, 3, false, 0},
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{3, 2, 4, false, 0}, {3, 2, 5, false, 0}, {3, 2, 6, false, 0}, {3, 2, 7, false, 0},
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{3, 3, 0, false, 0}, {3, 3, 1, false, 0}, {3, 3, 2, false, 0}, {3, 3, 3, false, 0},
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{3, 3, 4, false, 0}, {3, 3, 5, false, 0}, {3, 3, 6, false, 0}, {3, 3, 7, false, 0},
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{3, 4, 0, false, 0}, {3, 4, 1, false, 0}, {3, 4, 2, false, 0}, {3, 4, 3, false, 0},
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{3, 4, 4, false, 0}, {3, 4, 5, false, 0}, {3, 4, 6, false, 0}, {3, 4, 7, false, 0},
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{3, 5, 0, false, 0}, {3, 5, 1, false, 0}, {3, 5, 2, false, 0}, {3, 5, 3, false, 0},
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{3, 5, 4, false, 0}, {3, 5, 5, false, 0}, {3, 5, 6, false, 0}, {3, 5, 7, false, 0},
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{3, 6, 0, false, 0}, {3, 6, 1, false, 0}, {3, 6, 2, false, 0}, {3, 6, 3, false, 0},
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{3, 6, 4, false, 0}, {3, 6, 5, false, 0}, {3, 6, 6, false, 0}, {3, 6, 7, false, 0},
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{3, 7, 0, false, 0}, {3, 7, 1, false, 0}, {3, 7, 2, false, 0}, {3, 7, 3, false, 0},
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{3, 7, 4, false, 0}, {3, 7, 5, false, 0}, {3, 7, 6, false, 0}, {3, 7, 7, false, 0},
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}
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// =============================================================================
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// SIB Lookup Table
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// =============================================================================
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// Precomputed extraction of scale, index, base fields from SIB byte
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SIB_Info :: struct #packed {
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scale: u8, // 1, 2, 4, or 8
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index: u8, // index register (0-7, or 0xFF if none when index==4)
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base: u8, // base register (0-7, or 0xFF for special cases)
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}
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@(rodata)
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SIB_TABLE := [256]SIB_Info{
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{1, 0, 0}, {1, 0, 1}, {1, 0, 2}, {1, 0, 3},
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{1, 0, 4}, {1, 0, 5}, {1, 0, 6}, {1, 0, 7},
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{1, 1, 0}, {1, 1, 1}, {1, 1, 2}, {1, 1, 3},
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{1, 1, 4}, {1, 1, 5}, {1, 1, 6}, {1, 1, 7},
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{1, 2, 0}, {1, 2, 1}, {1, 2, 2}, {1, 2, 3},
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{1, 2, 4}, {1, 2, 5}, {1, 2, 6}, {1, 2, 7},
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{1, 3, 0}, {1, 3, 1}, {1, 3, 2}, {1, 3, 3},
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{1, 3, 4}, {1, 3, 5}, {1, 3, 6}, {1, 3, 7},
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{1, 255, 0}, {1, 255, 1}, {1, 255, 2}, {1, 255, 3},
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{1, 255, 4}, {1, 255, 5}, {1, 255, 6}, {1, 255, 7},
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{1, 5, 0}, {1, 5, 1}, {1, 5, 2}, {1, 5, 3},
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{1, 5, 4}, {1, 5, 5}, {1, 5, 6}, {1, 5, 7},
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{1, 6, 0}, {1, 6, 1}, {1, 6, 2}, {1, 6, 3},
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{1, 6, 4}, {1, 6, 5}, {1, 6, 6}, {1, 6, 7},
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{1, 7, 0}, {1, 7, 1}, {1, 7, 2}, {1, 7, 3},
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{1, 7, 4}, {1, 7, 5}, {1, 7, 6}, {1, 7, 7},
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{2, 0, 0}, {2, 0, 1}, {2, 0, 2}, {2, 0, 3},
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{2, 0, 4}, {2, 0, 5}, {2, 0, 6}, {2, 0, 7},
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{2, 1, 0}, {2, 1, 1}, {2, 1, 2}, {2, 1, 3},
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{2, 1, 4}, {2, 1, 5}, {2, 1, 6}, {2, 1, 7},
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{2, 2, 0}, {2, 2, 1}, {2, 2, 2}, {2, 2, 3},
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{2, 2, 4}, {2, 2, 5}, {2, 2, 6}, {2, 2, 7},
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{2, 3, 0}, {2, 3, 1}, {2, 3, 2}, {2, 3, 3},
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{2, 3, 4}, {2, 3, 5}, {2, 3, 6}, {2, 3, 7},
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{2, 255, 0}, {2, 255, 1}, {2, 255, 2}, {2, 255, 3},
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{2, 255, 4}, {2, 255, 5}, {2, 255, 6}, {2, 255, 7},
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{2, 5, 0}, {2, 5, 1}, {2, 5, 2}, {2, 5, 3},
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{2, 5, 4}, {2, 5, 5}, {2, 5, 6}, {2, 5, 7},
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{2, 6, 0}, {2, 6, 1}, {2, 6, 2}, {2, 6, 3},
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{2, 6, 4}, {2, 6, 5}, {2, 6, 6}, {2, 6, 7},
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{2, 7, 0}, {2, 7, 1}, {2, 7, 2}, {2, 7, 3},
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{2, 7, 4}, {2, 7, 5}, {2, 7, 6}, {2, 7, 7},
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{4, 0, 0}, {4, 0, 1}, {4, 0, 2}, {4, 0, 3},
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{4, 0, 4}, {4, 0, 5}, {4, 0, 6}, {4, 0, 7},
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{4, 1, 0}, {4, 1, 1}, {4, 1, 2}, {4, 1, 3},
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{4, 1, 4}, {4, 1, 5}, {4, 1, 6}, {4, 1, 7},
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{4, 2, 0}, {4, 2, 1}, {4, 2, 2}, {4, 2, 3},
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{4, 2, 4}, {4, 2, 5}, {4, 2, 6}, {4, 2, 7},
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{4, 3, 0}, {4, 3, 1}, {4, 3, 2}, {4, 3, 3},
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{4, 3, 4}, {4, 3, 5}, {4, 3, 6}, {4, 3, 7},
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{4, 255, 0}, {4, 255, 1}, {4, 255, 2}, {4, 255, 3},
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{4, 255, 4}, {4, 255, 5}, {4, 255, 6}, {4, 255, 7},
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{4, 5, 0}, {4, 5, 1}, {4, 5, 2}, {4, 5, 3},
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{4, 5, 4}, {4, 5, 5}, {4, 5, 6}, {4, 5, 7},
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{4, 6, 0}, {4, 6, 1}, {4, 6, 2}, {4, 6, 3},
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{4, 6, 4}, {4, 6, 5}, {4, 6, 6}, {4, 6, 7},
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{4, 7, 0}, {4, 7, 1}, {4, 7, 2}, {4, 7, 3},
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{4, 7, 4}, {4, 7, 5}, {4, 7, 6}, {4, 7, 7},
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{8, 0, 0}, {8, 0, 1}, {8, 0, 2}, {8, 0, 3},
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{8, 0, 4}, {8, 0, 5}, {8, 0, 6}, {8, 0, 7},
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{8, 1, 0}, {8, 1, 1}, {8, 1, 2}, {8, 1, 3},
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{8, 1, 4}, {8, 1, 5}, {8, 1, 6}, {8, 1, 7},
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{8, 2, 0}, {8, 2, 1}, {8, 2, 2}, {8, 2, 3},
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{8, 2, 4}, {8, 2, 5}, {8, 2, 6}, {8, 2, 7},
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{8, 3, 0}, {8, 3, 1}, {8, 3, 2}, {8, 3, 3},
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{8, 3, 4}, {8, 3, 5}, {8, 3, 6}, {8, 3, 7},
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{8, 255, 0}, {8, 255, 1}, {8, 255, 2}, {8, 255, 3},
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{8, 255, 4}, {8, 255, 5}, {8, 255, 6}, {8, 255, 7},
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{8, 5, 0}, {8, 5, 1}, {8, 5, 2}, {8, 5, 3},
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{8, 5, 4}, {8, 5, 5}, {8, 5, 6}, {8, 5, 7},
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{8, 6, 0}, {8, 6, 1}, {8, 6, 2}, {8, 6, 3},
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{8, 6, 4}, {8, 6, 5}, {8, 6, 6}, {8, 6, 7},
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{8, 7, 0}, {8, 7, 1}, {8, 7, 2}, {8, 7, 3},
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{8, 7, 4}, {8, 7, 5}, {8, 7, 6}, {8, 7, 7},
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}
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// =============================================================================
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// Decode Entry
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// =============================================================================
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// Information needed to decode an instruction given its opcode bytes
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Decode_Entry :: struct {
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esc: Escape, // escape sequence used to find this entry
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prefix: u8, // mandatory prefix (0=none, 1=66, 2=F3, 3=F2)
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opcode: u8, // primary opcode byte
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ext: u8, // ModR/M reg extension (0-7) or 0xFF if not used
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mnemonic: Mnemonic,
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ops: [4]Operand_Type, // operand types
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enc: [4]Operand_Encoding, // operand encodings
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flags: Encoding_Flags,
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}
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// Legacy decode entries: 1270
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@(rodata)
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LEGACY_DECODE_ENTRIES := [1270]Decode_Entry{
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{.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
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{.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
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{.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
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{.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
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{.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
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{.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
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{.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
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{.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
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{.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
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{.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
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{.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
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{.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
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{.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
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{.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
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{.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}},
|
|
{.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}},
|
|
{.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {}},
|
|
{.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {}},
|
|
{.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {}},
|
|
{.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {}},
|
|
{.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x03, .SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x04, .AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x05, .SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x06, .XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x80, 0x07, .CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}},
|
|
{.NONE, 0, 0x87, 0xFF, .XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
|
|
{.NONE, 0, 0x88, 0xFF, .MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x89, 0xFF, .MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x89, 0xFF, .MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x89, 0xFF, .MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8A, 0xFF, .MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8B, 0xFF, .MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8B, 0xFF, .MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8B, 0xFF, .MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x8C, 0xFF, .MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x8C, 0xFF, .MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8D, 0xFF, .LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x8D, 0xFF, .LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8D, 0xFF, .LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA0, 0xFF, .MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA1, 0xFF, .MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xA2, 0xFF, .MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA2, 0xFF, .MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
|
|
{.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
|
|
{.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
|
|
{.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
|
|
{.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
|
|
{.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
|
|
{.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xB8, 0xFF, .MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xB8, 0xFF, .MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xC0, 0x00, .ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x01, .ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xC3, 0xFF, .RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC7, 0x00, .MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC7, 0x00, .MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xC8, 0xFF, .ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xC9, 0xFF, .LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xCC, 0xFF, .INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x05, .SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x05, .SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD1, 0x07, .SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x00, .ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x05, .SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x05, .SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x05, .SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x07, .SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x07, .SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD7, 0xFF, .XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD7, 0xFF, .XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0x01, .FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x02, .FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x03, .FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x04, .FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x05, .FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x06, .FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0x07, .FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD8, 0xFF, .FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0x02, .FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x03, .FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FYL2X, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDL2E, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FYL2XP1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FPATAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FXTRACT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLD1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FINCSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FSINCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDPI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDLN2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .F2XM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FCHS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FPREM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FABS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FTST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FXAM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FPREM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDZ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FPTAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FSQRT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDL2T, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FLDLG2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xD9, 0xFF, .FDECSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x04, .FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x05, .FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x06, .FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0x07, .FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FUCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDA, 0xFF, .FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0x01, .FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDB, 0x02, .FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDB, 0x03, .FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDB, 0x05, .FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDB, 0x07, .FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDB, 0xFF, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0x01, .FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x02, .FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x03, .FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x04, .FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x05, .FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x06, .FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0x07, .FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDC, 0xFF, .FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0x01, .FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x02, .FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FUCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDD, 0xFF, .FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0x01, .FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x02, .FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x03, .FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x04, .FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x05, .FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x06, .FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0x07, .FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDE, 0xFF, .FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0x01, .FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x02, .FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x03, .FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x04, .FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x05, .FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x06, .FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xDF, 0xFF, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true}},
|
|
{.NONE, 0, 0xE8, 0xFF, .CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xF0, 0xFF, .LOCK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xF4, 0xFF, .HLT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xF5, 0xFF, .CMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xF6, 0x00, .TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x02, .NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x03, .NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x04, .MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x05, .IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x06, .DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF6, 0x07, .IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x00, .TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x00, .TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x02, .NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x03, .NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x03, .NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x04, .MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x04, .MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x05, .IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x05, .IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x05, .IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x06, .DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x06, .DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x06, .DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x07, .IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x07, .IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF7, 0x07, .IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xF8, 0xFF, .CLC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xF9, 0xFF, .STC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xFA, 0xFF, .CLI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xFB, 0xFF, .STI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xFC, 0xFF, .CLD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xFD, 0xFF, .STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
|
|
{.NONE, 0, 0xFE, 0x00, .INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFE, 0x01, .DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x00, .INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x01, .DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x05, .JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x06, .PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
|
|
{.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
|
|
{.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}},
|
|
{._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x00, 0x05, .VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x01, 0xFF, .ENCLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .VMLAUNCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .ENCLS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .VMXOFF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .VMRESUME, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .VMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x01, 0xFF, .XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x08, 0xFF, .INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x09, 0xFF, .WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x0B, 0xFF, .UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x23, 0xFF, .MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x28, 0xFF, .MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x29, 0xFF, .MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x2B, 0xFF, .MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x2E, 0xFF, .UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x2F, 0xFF, .COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x30, 0xFF, .WRMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x31, 0xFF, .RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x32, 0xFF, .RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x33, 0xFF, .RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x34, 0xFF, .SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x35, 0xFF, .SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x52, 0xFF, .RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x53, 0xFF, .RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x54, 0xFF, .ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x55, 0xFF, .ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x56, 0xFF, .ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x57, 0xFF, .XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x58, 0xFF, .ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x59, 0xFF, .MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5A, 0xFF, .CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5B, 0xFF, .CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5C, 0xFF, .SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5D, 0xFF, .MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5E, 0xFF, .DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x5F, 0xFF, .MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x6E, 0xFF, .MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x6F, 0xFF, .MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x70, 0xFF, .PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x78, 0xFF, .VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x79, 0xFF, .VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x7E, 0xFF, .MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x89, 0xFF, .JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8A, 0xFF, .JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8A, 0xFF, .JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8B, 0xFF, .JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8B, 0xFF, .JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8C, 0xFF, .JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x94, 0xFF, .SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x94, 0xFF, .SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x95, 0xFF, .SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x95, 0xFF, .SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x96, 0xFF, .SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x96, 0xFF, .SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x97, 0xFF, .SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9C, 0xFF, .SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9D, 0xFF, .SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9D, 0xFF, .SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9E, 0xFF, .SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9E, 0xFF, .SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9F, 0xFF, .SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0x9F, 0xFF, .SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA0, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA1, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA2, 0xFF, .CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA3, 0xFF, .BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA3, 0xFF, .BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAA, 0xFF, .RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
|
|
{._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x04, .XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xAE, 0xFF, .MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAE, 0xFF, .SFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAE, 0xFF, .LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAF, 0xFF, .IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAF, 0xFF, .IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
|
|
{._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
|
|
{._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xB6, 0xFF, .MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
|
|
{._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
|
|
{._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}},
|
|
{._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
|
|
{._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
|
|
{._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}},
|
|
{._0F, 1, 0x10, 0xFF, .MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x11, 0xFF, .MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x12, 0xFF, .MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x13, 0xFF, .MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x14, 0xFF, .UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x15, 0xFF, .UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x16, 0xFF, .MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x17, 0xFF, .MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x28, 0xFF, .MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x29, 0xFF, .MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x2B, 0xFF, .MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x2E, 0xFF, .UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x2F, 0xFF, .COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
|
|
{._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x51, 0xFF, .SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x54, 0xFF, .ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x55, 0xFF, .ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x56, 0xFF, .ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x57, 0xFF, .XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x58, 0xFF, .ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x59, 0xFF, .MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5A, 0xFF, .CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5B, 0xFF, .CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5C, 0xFF, .SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5D, 0xFF, .MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5E, 0xFF, .DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x5F, 0xFF, .MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x60, 0xFF, .PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x61, 0xFF, .PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x62, 0xFF, .PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x63, 0xFF, .PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x64, 0xFF, .PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x65, 0xFF, .PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x66, 0xFF, .PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x67, 0xFF, .PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x68, 0xFF, .PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x69, 0xFF, .PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6A, 0xFF, .PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
|
|
{._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x04, .PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x06, .PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x02, .PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x04, .PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x06, .PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x02, .PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x06, .PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x74, 0xFF, .PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x75, 0xFF, .PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
|
|
{._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0xAE, 0x07, .CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
|
|
{._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xC7, 0x06, .VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0xD0, 0xFF, .ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD1, 0xFF, .PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD2, 0xFF, .PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD3, 0xFF, .PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD4, 0xFF, .PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD5, 0xFF, .PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD6, 0xFF, .MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
|
|
{._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD8, 0xFF, .PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xD9, 0xFF, .PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDA, 0xFF, .PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDB, 0xFF, .PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDC, 0xFF, .PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDD, 0xFF, .PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDE, 0xFF, .PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xDF, 0xFF, .PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE0, 0xFF, .PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE1, 0xFF, .PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE2, 0xFF, .PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE3, 0xFF, .PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE4, 0xFF, .PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE5, 0xFF, .PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE6, 0xFF, .CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE7, 0xFF, .MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE8, 0xFF, .PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xE9, 0xFF, .PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xEA, 0xFF, .PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xEB, 0xFF, .POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xEC, 0xFF, .PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xED, 0xFF, .PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xEE, 0xFF, .PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xEF, 0xFF, .PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF1, 0xFF, .PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF2, 0xFF, .PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF3, 0xFF, .PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF4, 0xFF, .PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF5, 0xFF, .PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF6, 0xFF, .PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF7, 0xFF, .MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF8, 0xFF, .PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xF9, 0xFF, .PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xFA, 0xFF, .PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xFB, 0xFF, .PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xFC, 0xFF, .PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xFD, 0xFF, .PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 1, 0xFE, 0xFF, .PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}},
|
|
{._0F, 2, 0x01, 0x05, .RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
|
|
{._0F, 2, 0x01, 0xFF, .SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x01, 0xFF, .SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x10, 0xFF, .MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
|
|
{._0F, 2, 0x1E, 0xFF, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x1E, 0xFF, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x52, 0xFF, .RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x53, 0xFF, .RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x58, 0xFF, .ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x59, 0xFF, .MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5A, 0xFF, .CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5B, 0xFF, .CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5C, 0xFF, .SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5D, 0xFF, .MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5E, 0xFF, .DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x5F, 0xFF, .MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x6F, 0xFF, .MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x70, 0xFF, .PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x7E, 0xFF, .MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0x7F, 0xFF, .MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
|
|
{._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}},
|
|
{._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
|
|
{._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
|
|
{._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
|
|
{._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}},
|
|
{._0F, 3, 0x10, 0xFF, .MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x11, 0xFF, .MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
|
|
{._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
|
|
{._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
|
|
{._0F, 3, 0x51, 0xFF, .SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x58, 0xFF, .ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x59, 0xFF, .MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x5A, 0xFF, .CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x5C, 0xFF, .SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x5D, 0xFF, .MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x5E, 0xFF, .DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x5F, 0xFF, .MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0xC2, 0xFF, .CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F, 3, 0xF0, 0xFF, .LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}},
|
|
{._0F38, 0, 0xC8, 0xFF, .SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xC9, 0xFF, .SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xCA, 0xFF, .SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xCB, 0xFF, .SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xCC, 0xFF, .SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xCD, 0xFF, .SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
|
|
{._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
|
|
{._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
|
|
{._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}},
|
|
{._0F38, 1, 0x00, 0xFF, .PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x01, 0xFF, .PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x02, 0xFF, .PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x03, 0xFF, .PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x04, 0xFF, .PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x05, 0xFF, .PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x06, 0xFF, .PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x07, 0xFF, .PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x08, 0xFF, .PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x09, 0xFF, .PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x0A, 0xFF, .PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x0B, 0xFF, .PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x10, 0xFF, .PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x14, 0xFF, .BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x15, 0xFF, .BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x17, 0xFF, .PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x1C, 0xFF, .PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x1D, 0xFF, .PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x1E, 0xFF, .PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x20, 0xFF, .PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x21, 0xFF, .PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x22, 0xFF, .PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x23, 0xFF, .PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x24, 0xFF, .PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x25, 0xFF, .PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x28, 0xFF, .PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x29, 0xFF, .PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x2A, 0xFF, .MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x2B, 0xFF, .PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x30, 0xFF, .PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x31, 0xFF, .PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x32, 0xFF, .PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x33, 0xFF, .PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x34, 0xFF, .PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x35, 0xFF, .PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x37, 0xFF, .PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x38, 0xFF, .PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x39, 0xFF, .PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3A, 0xFF, .PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3B, 0xFF, .PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3C, 0xFF, .PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3D, 0xFF, .PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3E, 0xFF, .PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x3F, 0xFF, .PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x40, 0xFF, .PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x41, 0xFF, .PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x80, 0xFF, .INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x81, 0xFF, .INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0x82, 0xFF, .INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xDB, 0xFF, .AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xDC, 0xFF, .AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xDE, 0xFF, .AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}},
|
|
{._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}},
|
|
{._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}},
|
|
{._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true}},
|
|
{._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2}},
|
|
{._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}},
|
|
{._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}},
|
|
{._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}},
|
|
{._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}},
|
|
{._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}},
|
|
{._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A}},
|
|
{._0F3A, 1, 0x08, 0xFF, .ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x09, 0xFF, .ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0A, 0xFF, .ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0B, 0xFF, .ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0C, 0xFF, .BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0D, 0xFF, .BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0E, 0xFF, .PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x0F, 0xFF, .PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x14, 0xFF, .PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x16, 0xFF, .PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x16, 0xFF, .PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}},
|
|
{._0F3A, 1, 0x17, 0xFF, .EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x20, 0xFF, .PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x21, 0xFF, .INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x22, 0xFF, .PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x22, 0xFF, .PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}},
|
|
{._0F3A, 1, 0x40, 0xFF, .DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x41, 0xFF, .DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x42, 0xFF, .MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x44, 0xFF, .PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x60, 0xFF, .PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x61, 0xFF, .PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x62, 0xFF, .PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0x63, 0xFF, .PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
{._0F3A, 1, 0xDF, 0xFF, .AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}},
|
|
}
|
|
|
|
// =============================================================================
|
|
// VEX Decode Entry
|
|
// =============================================================================
|
|
|
|
VEX_Decode_Entry :: struct {
|
|
esc: Escape,
|
|
prefix: u8,
|
|
opcode: u8,
|
|
ext: u8,
|
|
vex_w: VEX_W,
|
|
vex_l: VEX_L,
|
|
mnemonic: Mnemonic,
|
|
ops: [4]Operand_Type,
|
|
enc: [4]Operand_Encoding,
|
|
flags: Encoding_Flags,
|
|
}
|
|
|
|
// VEX decode entries: 667
|
|
@(rodata)
|
|
VEX_DECODE_ENTRIES := [667]VEX_Decode_Entry{
|
|
{._0F, 0, 0x10, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x10, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x11, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x11, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x13, 0xFF, .WIG, .L0, .VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x17, 0xFF, .WIG, .L0, .VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x28, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x28, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x29, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x29, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX}},
|
|
{._0F, 0, 0x2F, 0xFF, .WIG, .LIG, .VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX}},
|
|
{._0F, 0, 0x41, 0xFF, .W0, .L1, .KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x41, 0xFF, .W1, .L1, .KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x42, 0xFF, .W1, .L1, .KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x42, 0xFF, .W0, .L1, .KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x44, 0xFF, .W1, .L0, .KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 0, 0x44, 0xFF, .W0, .L0, .KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x45, 0xFF, .W0, .L1, .KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x45, 0xFF, .W1, .L1, .KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x46, 0xFF, .W1, .L1, .KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x46, 0xFF, .W0, .L1, .KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x47, 0xFF, .W1, .L1, .KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x47, 0xFF, .W0, .L1, .KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x4A, 0xFF, .W0, .L1, .KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x4A, 0xFF, .W1, .L1, .KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x4B, 0xFF, .W1, .L1, .KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 0, 0x4B, 0xFF, .W0, .L1, .KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 0, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x51, 0xFF, .WIG, .L1, .VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x51, 0xFF, .WIG, .L0, .VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x52, 0xFF, .WIG, .L1, .VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x52, 0xFF, .WIG, .L0, .VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x53, 0xFF, .WIG, .L0, .VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x53, 0xFF, .WIG, .L1, .VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x54, 0xFF, .WIG, .L0, .VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x54, 0xFF, .WIG, .L1, .VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x55, 0xFF, .WIG, .L0, .VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x55, 0xFF, .WIG, .L1, .VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x56, 0xFF, .WIG, .L0, .VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x56, 0xFF, .WIG, .L1, .VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x57, 0xFF, .WIG, .L0, .VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x57, 0xFF, .WIG, .L1, .VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x58, 0xFF, .WIG, .L0, .VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x58, 0xFF, .WIG, .L1, .VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x59, 0xFF, .WIG, .L0, .VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x59, 0xFF, .WIG, .L1, .VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5A, 0xFF, .WIG, .L1, .VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5A, 0xFF, .WIG, .L0, .VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5B, 0xFF, .WIG, .L1, .VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5B, 0xFF, .WIG, .L0, .VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5C, 0xFF, .WIG, .L0, .VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5C, 0xFF, .WIG, .L1, .VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5D, 0xFF, .WIG, .L1, .VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5D, 0xFF, .WIG, .L0, .VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5E, 0xFF, .WIG, .L0, .VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5E, 0xFF, .WIG, .L1, .VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x5F, 0xFF, .WIG, .L0, .VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x5F, 0xFF, .WIG, .L1, .VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x77, 0xFF, .WIG, .L1, .VZEROALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0x77, 0xFF, .WIG, .L0, .VZEROUPPER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0x90, 0xFF, .W1, .L0, .KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 0, 0x90, 0xFF, .W0, .L0, .KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x91, 0xFF, .W1, .L0, .KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 0, 0x91, 0xFF, .W0, .L0, .KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x92, 0xFF, .W0, .L0, .KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x93, 0xFF, .W0, .L0, .KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x98, 0xFF, .W0, .L0, .KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0x98, 0xFF, .W1, .L0, .KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 0, 0x99, 0xFF, .W1, .L0, .KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 0, 0x99, 0xFF, .W0, .L0, .KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 0, 0xC2, 0xFF, .WIG, .L0, .VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 0, 0xC2, 0xFF, .WIG, .L1, .VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0xC6, 0xFF, .WIG, .L1, .VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 0, 0xC6, 0xFF, .WIG, .L0, .VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x10, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x10, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x11, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x11, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x12, 0xFF, .WIG, .L0, .VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x13, 0xFF, .WIG, .L0, .VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x16, 0xFF, .WIG, .L0, .VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x17, 0xFF, .WIG, .L0, .VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x28, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x28, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x29, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x29, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}},
|
|
{._0F, 1, 0x2F, 0xFF, .WIG, .LIG, .VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}},
|
|
{._0F, 1, 0x41, 0xFF, .W1, .L1, .KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x41, 0xFF, .W0, .L1, .KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x42, 0xFF, .W0, .L1, .KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x42, 0xFF, .W1, .L1, .KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x44, 0xFF, .W1, .L0, .KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x44, 0xFF, .W0, .L0, .KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x45, 0xFF, .W0, .L1, .KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x45, 0xFF, .W1, .L1, .KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x46, 0xFF, .W1, .L1, .KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x46, 0xFF, .W0, .L1, .KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x47, 0xFF, .W1, .L1, .KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x47, 0xFF, .W0, .L1, .KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x4A, 0xFF, .W0, .L1, .KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x4A, 0xFF, .W1, .L1, .KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x4B, 0xFF, .W0, .L1, .KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x51, 0xFF, .WIG, .L1, .VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x51, 0xFF, .WIG, .L0, .VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x54, 0xFF, .WIG, .L1, .VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x54, 0xFF, .WIG, .L0, .VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x55, 0xFF, .WIG, .L0, .VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x55, 0xFF, .WIG, .L1, .VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x56, 0xFF, .WIG, .L1, .VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x56, 0xFF, .WIG, .L0, .VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x57, 0xFF, .WIG, .L0, .VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x57, 0xFF, .WIG, .L1, .VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x58, 0xFF, .WIG, .L0, .VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x58, 0xFF, .WIG, .L1, .VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x59, 0xFF, .WIG, .L1, .VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x59, 0xFF, .WIG, .L0, .VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5A, 0xFF, .WIG, .L0, .VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5A, 0xFF, .WIG, .L1, .VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x5B, 0xFF, .WIG, .L0, .VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5B, 0xFF, .WIG, .L1, .VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x5C, 0xFF, .WIG, .L1, .VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x5C, 0xFF, .WIG, .L0, .VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5D, 0xFF, .WIG, .L0, .VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5D, 0xFF, .WIG, .L1, .VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x5E, 0xFF, .WIG, .L1, .VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x5E, 0xFF, .WIG, .L0, .VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5F, 0xFF, .WIG, .L0, .VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x5F, 0xFF, .WIG, .L1, .VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x60, 0xFF, .WIG, .L1, .VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x60, 0xFF, .WIG, .L0, .VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x61, 0xFF, .WIG, .L0, .VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x61, 0xFF, .WIG, .L1, .VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x62, 0xFF, .WIG, .L1, .VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x62, 0xFF, .WIG, .L0, .VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x63, 0xFF, .WIG, .L0, .VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x63, 0xFF, .WIG, .L1, .VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x64, 0xFF, .WIG, .L1, .VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x64, 0xFF, .WIG, .L0, .VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x65, 0xFF, .WIG, .L1, .VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x65, 0xFF, .WIG, .L0, .VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x66, 0xFF, .WIG, .L1, .VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x66, 0xFF, .WIG, .L0, .VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x67, 0xFF, .WIG, .L0, .VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x67, 0xFF, .WIG, .L1, .VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x68, 0xFF, .WIG, .L1, .VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x68, 0xFF, .WIG, .L0, .VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x69, 0xFF, .WIG, .L1, .VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x69, 0xFF, .WIG, .L0, .VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6A, 0xFF, .WIG, .L0, .VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6A, 0xFF, .WIG, .L1, .VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x6B, 0xFF, .WIG, .L0, .VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6B, 0xFF, .WIG, .L1, .VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x6C, 0xFF, .WIG, .L0, .VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6C, 0xFF, .WIG, .L1, .VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x6D, 0xFF, .WIG, .L0, .VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6D, 0xFF, .WIG, .L1, .VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x6E, 0xFF, .WIG, .L0, .VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x6E, 0xFF, .W1, .L0, .VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x6F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x6F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x70, 0xFF, .WIG, .L0, .VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x70, 0xFF, .WIG, .L1, .VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x71, 0x02, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x02, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x04, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x04, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x06, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x71, 0x06, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x02, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x02, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x04, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x04, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x06, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x72, 0x06, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x02, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x02, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x06, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x73, 0x06, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F, 1, 0x74, 0xFF, .WIG, .L0, .VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x74, 0xFF, .WIG, .L1, .VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x75, 0xFF, .WIG, .L0, .VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x75, 0xFF, .WIG, .L1, .VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x76, 0xFF, .WIG, .L0, .VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x76, 0xFF, .WIG, .L1, .VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x7E, 0xFF, .WIG, .L0, .VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x7E, 0xFF, .W1, .L0, .VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x7F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0x7F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0x90, 0xFF, .W1, .L0, .KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x90, 0xFF, .W0, .L0, .KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x91, 0xFF, .W0, .L0, .KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x91, 0xFF, .W1, .L0, .KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x92, 0xFF, .W0, .L0, .KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x93, 0xFF, .W0, .L0, .KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x98, 0xFF, .W0, .L0, .KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x98, 0xFF, .W1, .L0, .KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x99, 0xFF, .W1, .L0, .KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x99, 0xFF, .W0, .L0, .KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0xC2, 0xFF, .WIG, .L1, .VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
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|
{._0F, 1, 0xC2, 0xFF, .WIG, .L0, .VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xC4, 0xFF, .WIG, .L0, .VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xC5, 0xFF, .WIG, .L0, .VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
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|
{._0F, 1, 0xC6, 0xFF, .WIG, .L0, .VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
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|
{._0F, 1, 0xC6, 0xFF, .WIG, .L1, .VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
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|
{._0F, 1, 0xD1, 0xFF, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
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|
{._0F, 1, 0xD1, 0xFF, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
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|
{._0F, 1, 0xD2, 0xFF, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xD2, 0xFF, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
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|
{._0F, 1, 0xD3, 0xFF, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xD3, 0xFF, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
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|
{._0F, 1, 0xD4, 0xFF, .WIG, .L0, .VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
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|
{._0F, 1, 0xD4, 0xFF, .WIG, .L1, .VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
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|
{._0F, 1, 0xD5, 0xFF, .WIG, .L0, .VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xD5, 0xFF, .WIG, .L1, .VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xD6, 0xFF, .WIG, .L0, .VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xD7, 0xFF, .WIG, .L0, .VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xD7, 0xFF, .WIG, .L1, .VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xDB, 0xFF, .WIG, .L1, .VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xDB, 0xFF, .WIG, .L0, .VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xDF, 0xFF, .WIG, .L1, .VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xDF, 0xFF, .WIG, .L0, .VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE1, 0xFF, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE1, 0xFF, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE2, 0xFF, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE2, 0xFF, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE4, 0xFF, .WIG, .L0, .VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE4, 0xFF, .WIG, .L1, .VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE5, 0xFF, .WIG, .L1, .VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE5, 0xFF, .WIG, .L0, .VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE6, 0xFF, .WIG, .L1, .VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE6, 0xFF, .WIG, .L0, .VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xE7, 0xFF, .WIG, .L1, .VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xE7, 0xFF, .WIG, .L0, .VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xEB, 0xFF, .WIG, .L1, .VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xEB, 0xFF, .WIG, .L0, .VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xEF, 0xFF, .WIG, .L0, .VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xEF, 0xFF, .WIG, .L1, .VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF1, 0xFF, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF1, 0xFF, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF2, 0xFF, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF2, 0xFF, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF3, 0xFF, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF3, 0xFF, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF4, 0xFF, .WIG, .L0, .VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF4, 0xFF, .WIG, .L1, .VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF5, 0xFF, .WIG, .L1, .VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF5, 0xFF, .WIG, .L0, .VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF7, 0xFF, .WIG, .L0, .VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF8, 0xFF, .WIG, .L1, .VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF8, 0xFF, .WIG, .L0, .VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xF9, 0xFF, .WIG, .L1, .VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xF9, 0xFF, .WIG, .L0, .VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFA, 0xFF, .WIG, .L0, .VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFA, 0xFF, .WIG, .L1, .VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xFB, 0xFF, .WIG, .L1, .VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xFB, 0xFF, .WIG, .L0, .VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFC, 0xFF, .WIG, .L0, .VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFC, 0xFF, .WIG, .L1, .VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xFD, 0xFF, .WIG, .L0, .VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFD, 0xFF, .WIG, .L1, .VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 1, 0xFE, 0xFF, .WIG, .L0, .VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 1, 0xFE, 0xFF, .WIG, .L1, .VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x11, 0xFF, .WIG, .LIG, .VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 2, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x2C, 0xFF, .W1, .LIG, .VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 2, 0x2D, 0xFF, .WIG, .LIG, .VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x2D, 0xFF, .W1, .LIG, .VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 2, 0x51, 0xFF, .WIG, .LIG, .VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x52, 0xFF, .WIG, .LIG, .VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x53, 0xFF, .WIG, .LIG, .VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x58, 0xFF, .WIG, .LIG, .VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x59, 0xFF, .WIG, .LIG, .VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x5A, 0xFF, .WIG, .LIG, .VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x5B, 0xFF, .WIG, .L1, .VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0x5B, 0xFF, .WIG, .L0, .VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 2, 0x5C, 0xFF, .WIG, .LIG, .VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x5D, 0xFF, .WIG, .LIG, .VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x5E, 0xFF, .WIG, .LIG, .VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x5F, 0xFF, .WIG, .LIG, .VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0x6F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0x6F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 2, 0x70, 0xFF, .WIG, .L1, .VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0x70, 0xFF, .WIG, .L0, .VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 2, 0x7E, 0xFF, .WIG, .L0, .VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 2, 0x7F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0x7F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 2, 0xC2, 0xFF, .WIG, .LIG, .VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=2, vex_type=.VEX}},
|
|
{._0F, 2, 0xE6, 0xFF, .WIG, .L1, .VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 2, 0xE6, 0xFF, .WIG, .L0, .VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x11, 0xFF, .WIG, .LIG, .VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 3, 0x2C, 0xFF, .W1, .LIG, .VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 3, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x2D, 0xFF, .WIG, .LIG, .VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x2D, 0xFF, .W1, .LIG, .VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F, 3, 0x51, 0xFF, .WIG, .LIG, .VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x58, 0xFF, .WIG, .LIG, .VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x59, 0xFF, .WIG, .LIG, .VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x5A, 0xFF, .WIG, .LIG, .VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x5C, 0xFF, .WIG, .LIG, .VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x5D, 0xFF, .WIG, .LIG, .VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x5E, 0xFF, .WIG, .LIG, .VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x5F, 0xFF, .WIG, .LIG, .VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0x70, 0xFF, .WIG, .L1, .VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 3, 0x70, 0xFF, .WIG, .L0, .VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F, 3, 0x92, 0xFF, .W1, .L0, .KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 3, 0x92, 0xFF, .W0, .L0, .KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 3, 0x93, 0xFF, .W0, .L0, .KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 3, 0x93, 0xFF, .W1, .L0, .KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 3, 0xC2, 0xFF, .WIG, .LIG, .VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=3, vex_type=.VEX}},
|
|
{._0F, 3, 0xE6, 0xFF, .WIG, .L1, .VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F, 3, 0xE6, 0xFF, .WIG, .L0, .VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 0, 0xF2, 0xFF, .W1, .L0, .ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 0, 0xF2, 0xFF, .W0, .L0, .ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 0, 0xF3, 0x01, .W1, .L0, .BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF3, 0x01, .W0, .L0, .BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF3, 0x02, .W0, .L0, .BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF3, 0x02, .W1, .L0, .BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF3, 0x03, .W1, .L0, .BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF3, 0x03, .W0, .L0, .BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
|
|
{._0F38, 0, 0xF5, 0xFF, .W0, .L0, .BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 0, 0xF5, 0xFF, .W1, .L0, .BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 0, 0xF7, 0xFF, .W1, .L0, .BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 0, 0xF7, 0xFF, .W0, .L0, .BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x00, 0xFF, .WIG, .L0, .VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x00, 0xFF, .WIG, .L1, .VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x01, 0xFF, .WIG, .L0, .VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x01, 0xFF, .WIG, .L1, .VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x02, 0xFF, .WIG, .L1, .VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x02, 0xFF, .WIG, .L0, .VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x03, 0xFF, .WIG, .L0, .VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x03, 0xFF, .WIG, .L1, .VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x04, 0xFF, .WIG, .L0, .VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x04, 0xFF, .WIG, .L1, .VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x05, 0xFF, .WIG, .L0, .VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x05, 0xFF, .WIG, .L1, .VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x06, 0xFF, .WIG, .L1, .VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x06, 0xFF, .WIG, .L0, .VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x07, 0xFF, .WIG, .L1, .VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x07, 0xFF, .WIG, .L0, .VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x08, 0xFF, .WIG, .L1, .VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x08, 0xFF, .WIG, .L0, .VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x09, 0xFF, .WIG, .L0, .VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x09, 0xFF, .WIG, .L1, .VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x0A, 0xFF, .WIG, .L0, .VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x0A, 0xFF, .WIG, .L1, .VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x0B, 0xFF, .WIG, .L1, .VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x0B, 0xFF, .WIG, .L0, .VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x0E, 0xFF, .WIG, .L1, .VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x0E, 0xFF, .WIG, .L0, .VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x0F, 0xFF, .WIG, .L0, .VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x0F, 0xFF, .WIG, .L1, .VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x13, 0xFF, .WIG, .L0, .VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x13, 0xFF, .WIG, .L1, .VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x16, 0xFF, .W0, .L1, .VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x17, 0xFF, .WIG, .L0, .VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x17, 0xFF, .WIG, .L1, .VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x1A, 0xFF, .WIG, .L1, .VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x1C, 0xFF, .WIG, .L1, .VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x1C, 0xFF, .WIG, .L0, .VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x1D, 0xFF, .WIG, .L0, .VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x1D, 0xFF, .WIG, .L1, .VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x1E, 0xFF, .WIG, .L0, .VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x1E, 0xFF, .WIG, .L1, .VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x20, 0xFF, .WIG, .L1, .VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x20, 0xFF, .WIG, .L0, .VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x21, 0xFF, .WIG, .L0, .VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x21, 0xFF, .WIG, .L1, .VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x22, 0xFF, .WIG, .L1, .VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x22, 0xFF, .WIG, .L0, .VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x23, 0xFF, .WIG, .L0, .VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x23, 0xFF, .WIG, .L1, .VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x24, 0xFF, .WIG, .L0, .VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x24, 0xFF, .WIG, .L1, .VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x25, 0xFF, .WIG, .L1, .VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x25, 0xFF, .WIG, .L0, .VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x28, 0xFF, .WIG, .L1, .VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x28, 0xFF, .WIG, .L0, .VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x29, 0xFF, .WIG, .L1, .VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x29, 0xFF, .WIG, .L0, .VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2A, 0xFF, .WIG, .L0, .VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2A, 0xFF, .WIG, .L1, .VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2B, 0xFF, .WIG, .L1, .VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2B, 0xFF, .WIG, .L0, .VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2C, 0xFF, .WIG, .L0, .VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2C, 0xFF, .WIG, .L1, .VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2D, 0xFF, .WIG, .L1, .VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2D, 0xFF, .WIG, .L0, .VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2E, 0xFF, .WIG, .L0, .VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x2E, 0xFF, .WIG, .L1, .VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2F, 0xFF, .WIG, .L1, .VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x2F, 0xFF, .WIG, .L0, .VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x30, 0xFF, .WIG, .L1, .VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x30, 0xFF, .WIG, .L0, .VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x31, 0xFF, .WIG, .L1, .VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x31, 0xFF, .WIG, .L0, .VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x32, 0xFF, .WIG, .L1, .VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x32, 0xFF, .WIG, .L0, .VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x33, 0xFF, .WIG, .L0, .VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x33, 0xFF, .WIG, .L1, .VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x34, 0xFF, .WIG, .L0, .VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x34, 0xFF, .WIG, .L1, .VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x35, 0xFF, .WIG, .L1, .VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x35, 0xFF, .WIG, .L0, .VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x36, 0xFF, .W0, .L1, .VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x37, 0xFF, .WIG, .L0, .VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x37, 0xFF, .WIG, .L1, .VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x38, 0xFF, .WIG, .L0, .VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x38, 0xFF, .WIG, .L1, .VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x39, 0xFF, .WIG, .L0, .VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x39, 0xFF, .WIG, .L1, .VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3A, 0xFF, .WIG, .L0, .VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3A, 0xFF, .WIG, .L1, .VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3B, 0xFF, .WIG, .L0, .VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3B, 0xFF, .WIG, .L1, .VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3C, 0xFF, .WIG, .L1, .VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3C, 0xFF, .WIG, .L0, .VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3D, 0xFF, .WIG, .L0, .VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3D, 0xFF, .WIG, .L1, .VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3E, 0xFF, .WIG, .L1, .VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x3E, 0xFF, .WIG, .L0, .VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3F, 0xFF, .WIG, .L0, .VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x3F, 0xFF, .WIG, .L1, .VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x40, 0xFF, .WIG, .L1, .VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x40, 0xFF, .WIG, .L0, .VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x41, 0xFF, .WIG, .L0, .VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0x45, 0xFF, .W1, .L0, .VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x45, 0xFF, .W0, .L1, .VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x45, 0xFF, .W1, .L1, .VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x45, 0xFF, .W0, .L0, .VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x46, 0xFF, .W0, .L0, .VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x46, 0xFF, .W0, .L1, .VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x47, 0xFF, .W1, .L1, .VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x47, 0xFF, .W1, .L0, .VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x47, 0xFF, .W0, .L0, .VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x47, 0xFF, .W0, .L1, .VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x5A, 0xFF, .WIG, .L1, .VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
|
|
{._0F38, 1, 0x8C, 0xFF, .W1, .L1, .VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x8C, 0xFF, .W0, .L0, .VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x8C, 0xFF, .W0, .L1, .VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x8C, 0xFF, .W1, .L0, .VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x8E, 0xFF, .W0, .L0, .VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x8E, 0xFF, .W1, .L1, .VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x8E, 0xFF, .W1, .L0, .VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x8E, 0xFF, .W0, .L1, .VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x90, 0xFF, .W0, .L1, .VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x90, 0xFF, .W0, .L0, .VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x90, 0xFF, .W1, .L1, .VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x90, 0xFF, .W1, .L0, .VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x91, 0xFF, .W1, .L1, .VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x91, 0xFF, .W0, .L1, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x91, 0xFF, .W1, .L0, .VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x91, 0xFF, .W0, .L0, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x92, 0xFF, .W1, .L0, .VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x92, 0xFF, .W0, .L0, .VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x92, 0xFF, .W0, .L1, .VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x92, 0xFF, .W1, .L1, .VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x93, 0xFF, .W1, .L0, .VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x93, 0xFF, .W0, .L0, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x93, 0xFF, .W1, .L1, .VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x93, 0xFF, .W0, .L1, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x96, 0xFF, .W1, .L0, .VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x96, 0xFF, .W0, .L1, .VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x96, 0xFF, .W1, .L1, .VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x96, 0xFF, .W0, .L0, .VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x97, 0xFF, .W1, .L0, .VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x97, 0xFF, .W1, .L1, .VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x97, 0xFF, .W0, .L1, .VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x97, 0xFF, .W0, .L0, .VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x98, 0xFF, .W1, .L0, .VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x98, 0xFF, .W1, .L1, .VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x98, 0xFF, .W0, .L0, .VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x98, 0xFF, .W0, .L1, .VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x99, 0xFF, .W1, .LIG, .VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x99, 0xFF, .W0, .LIG, .VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x9A, 0xFF, .W1, .L0, .VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x9A, 0xFF, .W0, .L1, .VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x9A, 0xFF, .W1, .L1, .VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x9A, 0xFF, .W0, .L0, .VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x9B, 0xFF, .W0, .LIG, .VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x9B, 0xFF, .W1, .LIG, .VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x9C, 0xFF, .W0, .L0, .VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x9C, 0xFF, .W1, .L1, .VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x9C, 0xFF, .W0, .L1, .VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x9C, 0xFF, .W1, .L0, .VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x9D, 0xFF, .W1, .LIG, .VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x9D, 0xFF, .W0, .LIG, .VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x9E, 0xFF, .W0, .L1, .VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x9E, 0xFF, .W0, .L0, .VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x9E, 0xFF, .W1, .L0, .VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x9E, 0xFF, .W1, .L1, .VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x9F, 0xFF, .W0, .LIG, .VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x9F, 0xFF, .W1, .LIG, .VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xA6, 0xFF, .W1, .L1, .VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA6, 0xFF, .W0, .L0, .VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA6, 0xFF, .W1, .L0, .VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA6, 0xFF, .W0, .L1, .VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA7, 0xFF, .W1, .L0, .VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA7, 0xFF, .W1, .L1, .VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA7, 0xFF, .W0, .L0, .VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA7, 0xFF, .W0, .L1, .VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA8, 0xFF, .W1, .L0, .VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA8, 0xFF, .W1, .L1, .VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA8, 0xFF, .W0, .L1, .VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA8, 0xFF, .W0, .L0, .VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA9, 0xFF, .W0, .LIG, .VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xA9, 0xFF, .W1, .LIG, .VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xAA, 0xFF, .W1, .L0, .VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xAA, 0xFF, .W0, .L0, .VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xAA, 0xFF, .W0, .L1, .VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xAA, 0xFF, .W1, .L1, .VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xAB, 0xFF, .W1, .LIG, .VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xAB, 0xFF, .W0, .LIG, .VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xAC, 0xFF, .W0, .L1, .VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xAC, 0xFF, .W1, .L1, .VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xAC, 0xFF, .W0, .L0, .VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xAC, 0xFF, .W1, .L0, .VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xAD, 0xFF, .W1, .LIG, .VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xAD, 0xFF, .W0, .LIG, .VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xAE, 0xFF, .W0, .L1, .VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xAE, 0xFF, .W1, .L0, .VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xAE, 0xFF, .W1, .L1, .VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xAE, 0xFF, .W0, .L0, .VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xAF, 0xFF, .W0, .LIG, .VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xAF, 0xFF, .W1, .LIG, .VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xB6, 0xFF, .W0, .L1, .VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xB6, 0xFF, .W0, .L0, .VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xB6, 0xFF, .W1, .L0, .VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xB6, 0xFF, .W1, .L1, .VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xB7, 0xFF, .W1, .L0, .VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xB7, 0xFF, .W0, .L1, .VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xB7, 0xFF, .W0, .L0, .VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xB7, 0xFF, .W1, .L1, .VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xB8, 0xFF, .W1, .L1, .VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xB8, 0xFF, .W0, .L1, .VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xB8, 0xFF, .W0, .L0, .VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xB8, 0xFF, .W1, .L0, .VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xB9, 0xFF, .W1, .LIG, .VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xB9, 0xFF, .W0, .LIG, .VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xBA, 0xFF, .W1, .L1, .VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xBA, 0xFF, .W1, .L0, .VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xBA, 0xFF, .W0, .L1, .VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xBA, 0xFF, .W0, .L0, .VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xBB, 0xFF, .W1, .LIG, .VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xBB, 0xFF, .W0, .LIG, .VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xBC, 0xFF, .W1, .L0, .VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xBC, 0xFF, .W1, .L1, .VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xBC, 0xFF, .W0, .L0, .VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xBC, 0xFF, .W0, .L1, .VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xBD, 0xFF, .W1, .LIG, .VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xBD, 0xFF, .W0, .LIG, .VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xBE, 0xFF, .W1, .L1, .VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xBE, 0xFF, .W1, .L0, .VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xBE, 0xFF, .W0, .L1, .VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xBE, 0xFF, .W0, .L0, .VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xBF, 0xFF, .W1, .LIG, .VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
|
|
{._0F38, 1, 0xBF, 0xFF, .W0, .LIG, .VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
|
|
{._0F38, 1, 0xDB, 0xFF, .WIG, .L0, .VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0xDC, 0xFF, .WIG, .L0, .VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0xDD, 0xFF, .WIG, .L0, .VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0xDE, 0xFF, .WIG, .L0, .VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0xDF, 0xFF, .WIG, .L0, .VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
|
|
{._0F38, 1, 0xF7, 0xFF, .W1, .L0, .SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xF7, 0xFF, .W0, .L0, .SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0xF5, 0xFF, .W1, .L0, .PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 2, 0xF5, 0xFF, .W0, .L0, .PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0xF7, 0xFF, .W0, .L0, .SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0xF7, 0xFF, .W1, .L0, .SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 3, 0xF5, 0xFF, .W0, .L0, .PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 3, 0xF5, 0xFF, .W1, .L0, .PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F38, 3, 0xF6, 0xFF, .W1, .L0, .MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F38, 3, 0xF6, 0xFF, .W0, .L0, .MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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|
{._0F38, 3, 0xF7, 0xFF, .W0, .L0, .SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F38, 3, 0xF7, 0xFF, .W1, .L0, .SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x00, 0xFF, .W1, .L1, .VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
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{._0F3A, 1, 0x01, 0xFF, .W1, .L1, .VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
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{._0F3A, 1, 0x02, 0xFF, .W0, .L1, .VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
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{._0F3A, 1, 0x02, 0xFF, .W0, .L0, .VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x06, 0xFF, .WIG, .L1, .VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x08, 0xFF, .WIG, .L1, .VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x08, 0xFF, .WIG, .L0, .VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x09, 0xFF, .WIG, .L0, .VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x09, 0xFF, .WIG, .L1, .VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x0A, 0xFF, .WIG, .LIG, .VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}},
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{._0F3A, 1, 0x0B, 0xFF, .WIG, .LIG, .VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}},
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{._0F3A, 1, 0x0C, 0xFF, .WIG, .L0, .VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x0C, 0xFF, .WIG, .L1, .VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x0D, 0xFF, .WIG, .L1, .VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x0D, 0xFF, .WIG, .L0, .VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x0E, 0xFF, .WIG, .L1, .VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x0E, 0xFF, .WIG, .L0, .VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x0F, 0xFF, .WIG, .L1, .VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x0F, 0xFF, .WIG, .L0, .VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x14, 0xFF, .WIG, .L0, .VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x15, 0xFF, .WIG, .L0, .VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x16, 0xFF, .WIG, .L0, .VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x16, 0xFF, .W1, .L0, .VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x17, 0xFF, .WIG, .L0, .VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x18, 0xFF, .WIG, .L1, .VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x19, 0xFF, .WIG, .L1, .VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x1D, 0xFF, .WIG, .L1, .VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x1D, 0xFF, .WIG, .L0, .VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x20, 0xFF, .WIG, .L0, .VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x21, 0xFF, .WIG, .L0, .VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x22, 0xFF, .WIG, .L0, .VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x22, 0xFF, .W1, .L0, .VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x30, 0xFF, .W0, .L0, .KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x30, 0xFF, .W1, .L0, .KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x31, 0xFF, .W0, .L0, .KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x31, 0xFF, .W1, .L0, .KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x32, 0xFF, .W1, .L0, .KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x32, 0xFF, .W0, .L0, .KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x33, 0xFF, .W0, .L0, .KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x33, 0xFF, .W1, .L0, .KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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{._0F3A, 1, 0x38, 0xFF, .WIG, .L1, .VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x39, 0xFF, .WIG, .L1, .VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x40, 0xFF, .WIG, .L1, .VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x40, 0xFF, .WIG, .L0, .VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x41, 0xFF, .WIG, .L0, .VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x42, 0xFF, .WIG, .L0, .VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x42, 0xFF, .WIG, .L1, .VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x44, 0xFF, .WIG, .L0, .VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 1, 0x44, 0xFF, .WIG, .L1, .VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x46, 0xFF, .WIG, .L1, .VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
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{._0F3A, 1, 0x4A, 0xFF, .W0, .L0, .VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x4A, 0xFF, .W0, .L1, .VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
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{._0F3A, 1, 0x4B, 0xFF, .W0, .L1, .VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
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{._0F3A, 1, 0x4B, 0xFF, .W0, .L0, .VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0x4C, 0xFF, .W0, .L1, .VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
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{._0F3A, 1, 0x4C, 0xFF, .W0, .L0, .VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 1, 0xDF, 0xFF, .WIG, .L0, .VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
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{._0F3A, 3, 0xF0, 0xFF, .W0, .L0, .RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
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{._0F3A, 3, 0xF0, 0xFF, .W1, .L0, .RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
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}
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// EVEX decode entries: 418
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@(rodata)
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EVEX_DECODE_ENTRIES := [418]VEX_Decode_Entry{
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{._0F, 1, 0x6F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
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{._0F, 1, 0x6F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
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{._0F, 1, 0x6F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
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{._0F, 1, 0x6F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
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{._0F, 1, 0x6F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
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{._0F, 1, 0x6F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
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{._0F, 1, 0x72, 0x01, .W0, .L2, .VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0x01, .W0, .L0, .VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0x01, .W0, .L1, .VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0x01, .W1, .L2, .VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0x01, .W1, .L0, .VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0x01, .W1, .L1, .VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true}},
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{._0F, 1, 0x72, 0xFF, .W0, .L2, .VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
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{._0F, 1, 0x72, 0xFF, .W1, .L0, .VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
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{._0F, 1, 0x72, 0xFF, .W1, .L2, .VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
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|
{._0F, 1, 0x72, 0xFF, .W0, .L0, .VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 1, 0x72, 0xFF, .W0, .L1, .VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x72, 0xFF, .W1, .L1, .VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x7F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 1, 0x7F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 1, 0x7F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F, 1, 0x7F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 1, 0x7F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F, 1, 0x7F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 2, 0x6F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 2, 0x6F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 2, 0x6F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F, 2, 0x6F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F, 2, 0x6F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 2, 0x6F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 2, 0x7F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 2, 0x7F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 2, 0x7F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 2, 0x7F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F, 2, 0x7F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 2, 0x7F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F, 3, 0x6F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F, 3, 0x6F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 3, 0x6F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F, 3, 0x6F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 3, 0x6F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 3, 0x6F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F, 3, 0x7F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F, 3, 0x7F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F, 3, 0x7F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F, 3, 0x7F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F, 3, 0x7F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F, 3, 0x7F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x10, 0xFF, .W1, .L2, .VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x10, 0xFF, .W1, .L0, .VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x10, 0xFF, .W1, .L1, .VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x11, 0xFF, .W1, .L2, .VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x11, 0xFF, .W1, .L0, .VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x11, 0xFF, .W1, .L1, .VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x12, 0xFF, .W1, .L1, .VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x12, 0xFF, .W1, .L2, .VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x12, 0xFF, .W1, .L0, .VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x13, 0xFF, .WIG, .L2, .VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2}},
|
|
{._0F38, 1, 0x14, 0xFF, .W0, .L0, .VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x14, 0xFF, .W1, .L0, .VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x14, 0xFF, .W0, .L2, .VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x14, 0xFF, .W1, .L2, .VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x14, 0xFF, .W0, .L1, .VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x14, 0xFF, .W1, .L1, .VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x15, 0xFF, .W0, .L1, .VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x15, 0xFF, .W1, .L1, .VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x15, 0xFF, .W1, .L0, .VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x15, 0xFF, .W0, .L0, .VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x15, 0xFF, .W0, .L2, .VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x15, 0xFF, .W1, .L2, .VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x26, 0xFF, .W1, .L1, .VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x26, 0xFF, .W1, .L2, .VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x26, 0xFF, .W0, .L2, .VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x26, 0xFF, .W0, .L1, .VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x26, 0xFF, .W1, .L0, .VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x26, 0xFF, .W0, .L0, .VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x27, 0xFF, .W0, .L0, .VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x27, 0xFF, .W0, .L2, .VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x27, 0xFF, .W1, .L2, .VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x27, 0xFF, .W1, .L0, .VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x27, 0xFF, .W1, .L1, .VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x27, 0xFF, .W0, .L1, .VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W0, .L1, .VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W1, .L1, .VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W0, .L0, .VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W1, .L0, .VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W1, .L2, .VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x2C, 0xFF, .W0, .L2, .VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x2D, 0xFF, .W1, .LIG, .VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x2D, 0xFF, .W0, .LIG, .VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x42, 0xFF, .W0, .L2, .VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x42, 0xFF, .W0, .L0, .VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x42, 0xFF, .W1, .L1, .VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x42, 0xFF, .W0, .L1, .VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x42, 0xFF, .W1, .L0, .VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x42, 0xFF, .W1, .L2, .VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x43, 0xFF, .W1, .LIG, .VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x43, 0xFF, .W0, .LIG, .VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x44, 0xFF, .W0, .L0, .VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x44, 0xFF, .W0, .L2, .VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x44, 0xFF, .W1, .L0, .VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x44, 0xFF, .W0, .L1, .VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x44, 0xFF, .W1, .L1, .VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x44, 0xFF, .W1, .L2, .VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x46, 0xFF, .W1, .L0, .VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x46, 0xFF, .W1, .L2, .VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x46, 0xFF, .W1, .L1, .VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W1, .L0, .VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W0, .L2, .VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W1, .L2, .VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W0, .L1, .VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W0, .L0, .VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x4C, 0xFF, .W1, .L1, .VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x4D, 0xFF, .W0, .LIG, .VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x4D, 0xFF, .W1, .LIG, .VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W1, .L0, .VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W1, .L2, .VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W1, .L1, .VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W0, .L1, .VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W0, .L2, .VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x4E, 0xFF, .W0, .L0, .VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x4F, 0xFF, .W1, .LIG, .VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F38, 1, 0x4F, 0xFF, .W0, .LIG, .VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F38, 1, 0x64, 0xFF, .W1, .L0, .VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x64, 0xFF, .W0, .L2, .VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x64, 0xFF, .W1, .L1, .VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x64, 0xFF, .W0, .L0, .VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x64, 0xFF, .W1, .L2, .VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x64, 0xFF, .W0, .L1, .VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x65, 0xFF, .W1, .L0, .VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x65, 0xFF, .W0, .L1, .VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x65, 0xFF, .W0, .L0, .VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x65, 0xFF, .W0, .L2, .VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x65, 0xFF, .W1, .L1, .VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x65, 0xFF, .W1, .L2, .VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x66, 0xFF, .W1, .L1, .VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x66, 0xFF, .W1, .L0, .VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x66, 0xFF, .W1, .L2, .VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x66, 0xFF, .W0, .L0, .VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x66, 0xFF, .W0, .L1, .VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x66, 0xFF, .W0, .L2, .VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x75, 0xFF, .W0, .L0, .VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x75, 0xFF, .W0, .L1, .VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x75, 0xFF, .W0, .L2, .VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x75, 0xFF, .W1, .L1, .VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x75, 0xFF, .W1, .L0, .VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x75, 0xFF, .W1, .L2, .VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x76, 0xFF, .W0, .L0, .VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x76, 0xFF, .W0, .L1, .VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x76, 0xFF, .W0, .L2, .VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x76, 0xFF, .W1, .L0, .VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x76, 0xFF, .W1, .L2, .VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x76, 0xFF, .W1, .L1, .VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x77, 0xFF, .W0, .L1, .VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x77, 0xFF, .W0, .L0, .VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x77, 0xFF, .W1, .L0, .VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x77, 0xFF, .W1, .L1, .VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x77, 0xFF, .W1, .L2, .VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x77, 0xFF, .W0, .L2, .VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W0, .L1, .VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W0, .L2, .VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W1, .L0, .VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W1, .L1, .VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W1, .L2, .VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x7D, 0xFF, .W0, .L0, .VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W0, .L0, .VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W0, .L2, .VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W0, .L1, .VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W1, .L1, .VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W1, .L0, .VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x7E, 0xFF, .W1, .L2, .VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W0, .L1, .VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W0, .L0, .VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W0, .L2, .VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W1, .L0, .VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W1, .L1, .VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x7F, 0xFF, .W1, .L2, .VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x83, 0xFF, .W1, .L1, .VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x83, 0xFF, .W1, .L0, .VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x83, 0xFF, .W1, .L2, .VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x88, 0xFF, .W1, .L2, .VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x88, 0xFF, .W1, .L0, .VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x88, 0xFF, .W0, .L2, .VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x88, 0xFF, .W1, .L1, .VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x88, 0xFF, .W0, .L0, .VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x88, 0xFF, .W0, .L1, .VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x89, 0xFF, .W1, .L2, .VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x89, 0xFF, .W1, .L0, .VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x89, 0xFF, .W0, .L2, .VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x89, 0xFF, .W1, .L1, .VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x89, 0xFF, .W0, .L0, .VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x89, 0xFF, .W0, .L1, .VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W1, .L2, .VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W1, .L1, .VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W0, .L2, .VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W0, .L0, .VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W0, .L1, .VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x8A, 0xFF, .W1, .L0, .VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W1, .L2, .VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W0, .L0, .VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W0, .L1, .VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W0, .L2, .VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W1, .L0, .VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x8B, 0xFF, .W1, .L1, .VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W0, .L0, .VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W1, .L1, .VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W0, .L2, .VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W0, .L1, .VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W1, .L0, .VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0x8D, 0xFF, .W1, .L2, .VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W1, .L2, .VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W1, .L0, .VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W1, .L1, .VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W0, .L2, .VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W0, .L1, .VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA0, 0xFF, .W0, .L0, .VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W0, .L0, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W1, .L0, .VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W0, .L1, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W1, .L1, .VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W1, .L2, .VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0xA1, 0xFF, .W0, .L2, .VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W1, .L2, .VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W0, .L1, .VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W0, .L0, .VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W0, .L2, .VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W1, .L0, .VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA2, 0xFF, .W1, .L1, .VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W0, .L0, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W1, .L2, .VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W0, .L1, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W1, .L0, .VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W1, .L1, .VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xA3, 0xFF, .W0, .L2, .VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W0, .L2, .VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W0, .L1, .VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W1, .L0, .VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W0, .L0, .VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W1, .L1, .VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 1, 0xC4, 0xFF, .W1, .L2, .VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x10, 0xFF, .W0, .L2, .VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x10, 0xFF, .W0, .L1, .VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x10, 0xFF, .W0, .L0, .VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x11, 0xFF, .W0, .L0, .VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x11, 0xFF, .W0, .L1, .VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x11, 0xFF, .W0, .L2, .VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x12, 0xFF, .W0, .L2, .VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x12, 0xFF, .W0, .L0, .VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x12, 0xFF, .W0, .L1, .VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x13, 0xFF, .W0, .L0, .VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x13, 0xFF, .W0, .L2, .VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x13, 0xFF, .W0, .L1, .VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x14, 0xFF, .W0, .L2, .VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x14, 0xFF, .W0, .L0, .VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x14, 0xFF, .W0, .L1, .VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x15, 0xFF, .W0, .L0, .VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x15, 0xFF, .W0, .L1, .VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x15, 0xFF, .W0, .L2, .VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x20, 0xFF, .W0, .L1, .VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x20, 0xFF, .W0, .L2, .VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x20, 0xFF, .W0, .L0, .VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x21, 0xFF, .W0, .L2, .VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x21, 0xFF, .W0, .L0, .VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x21, 0xFF, .W0, .L1, .VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x22, 0xFF, .W0, .L2, .VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x22, 0xFF, .W0, .L0, .VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x22, 0xFF, .W0, .L1, .VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x23, 0xFF, .W0, .L1, .VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x23, 0xFF, .W0, .L0, .VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x23, 0xFF, .W0, .L2, .VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x24, 0xFF, .W0, .L1, .VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x24, 0xFF, .W0, .L0, .VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x24, 0xFF, .W0, .L2, .VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x25, 0xFF, .W0, .L2, .VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x25, 0xFF, .W0, .L0, .VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x25, 0xFF, .W0, .L1, .VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x26, 0xFF, .W1, .L2, .VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x26, 0xFF, .W1, .L0, .VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 2, 0x26, 0xFF, .W0, .L1, .VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x26, 0xFF, .W0, .L0, .VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x26, 0xFF, .W0, .L2, .VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x26, 0xFF, .W1, .L1, .VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x27, 0xFF, .W1, .L1, .VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x27, 0xFF, .W1, .L0, .VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 2, 0x27, 0xFF, .W1, .L2, .VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x27, 0xFF, .W0, .L0, .VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x27, 0xFF, .W0, .L1, .VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x27, 0xFF, .W0, .L2, .VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
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|
{._0F38, 2, 0x28, 0xFF, .W1, .L1, .VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x28, 0xFF, .W1, .L0, .VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
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|
{._0F38, 2, 0x28, 0xFF, .W1, .L2, .VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x28, 0xFF, .W0, .L1, .VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x28, 0xFF, .W0, .L2, .VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x28, 0xFF, .W0, .L0, .VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x29, 0xFF, .W1, .L2, .VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x29, 0xFF, .W1, .L1, .VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x29, 0xFF, .W0, .L1, .VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x29, 0xFF, .W0, .L0, .VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x29, 0xFF, .W0, .L2, .VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x29, 0xFF, .W1, .L0, .VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 2, 0x30, 0xFF, .W0, .L2, .VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x30, 0xFF, .W0, .L0, .VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
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|
{._0F38, 2, 0x30, 0xFF, .W0, .L1, .VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x31, 0xFF, .W0, .L1, .VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x31, 0xFF, .W0, .L0, .VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x31, 0xFF, .W0, .L2, .VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x32, 0xFF, .W0, .L2, .VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x32, 0xFF, .W0, .L1, .VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x32, 0xFF, .W0, .L0, .VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x33, 0xFF, .W0, .L2, .VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x33, 0xFF, .W0, .L0, .VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x33, 0xFF, .W0, .L1, .VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x34, 0xFF, .W0, .L0, .VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x34, 0xFF, .W0, .L1, .VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x34, 0xFF, .W0, .L2, .VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x35, 0xFF, .W0, .L0, .VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x35, 0xFF, .W0, .L1, .VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x35, 0xFF, .W0, .L2, .VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x38, 0xFF, .W1, .L2, .VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x38, 0xFF, .W1, .L0, .VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F38, 2, 0x38, 0xFF, .W0, .L2, .VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x38, 0xFF, .W1, .L1, .VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x38, 0xFF, .W0, .L0, .VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x38, 0xFF, .W0, .L1, .VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x39, 0xFF, .W1, .L2, .VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F38, 2, 0x39, 0xFF, .W1, .L1, .VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F38, 2, 0x39, 0xFF, .W0, .L1, .VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F38, 2, 0x39, 0xFF, .W0, .L0, .VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F38, 2, 0x39, 0xFF, .W0, .L2, .VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F38, 2, 0x39, 0xFF, .W1, .L0, .VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W1, .L0, .VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W0, .L0, .VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W1, .L1, .VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W0, .L1, .VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W0, .L2, .VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x03, 0xFF, .W1, .L2, .VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x08, 0xFF, .W0, .L0, .VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x08, 0xFF, .W0, .L1, .VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x08, 0xFF, .W0, .L2, .VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x09, 0xFF, .W1, .L0, .VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x09, 0xFF, .W1, .L1, .VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x09, 0xFF, .W1, .L2, .VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x0A, 0xFF, .W0, .LIG, .VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F3A, 1, 0x0B, 0xFF, .W1, .LIG, .VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x1D, 0xFF, .WIG, .L2, .VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W1, .L2, .VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W1, .L0, .VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W1, .L1, .VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W0, .L2, .VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W0, .L1, .VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x1E, 0xFF, .W0, .L0, .VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W1, .L2, .VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W1, .L0, .VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W0, .L2, .VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W0, .L0, .VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W0, .L1, .VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x1F, 0xFF, .W1, .L1, .VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W0, .L0, .VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W0, .L1, .VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W1, .L0, .VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W1, .L1, .VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W0, .L2, .VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x25, 0xFF, .W1, .L2, .VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W1, .L0, .VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W1, .L1, .VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W0, .L1, .VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W0, .L0, .VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W1, .L2, .VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x26, 0xFF, .W0, .L2, .VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x27, 0xFF, .W1, .LIG, .VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x27, 0xFF, .W0, .LIG, .VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W1, .L2, .VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W0, .L2, .VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W0, .L0, .VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W1, .L0, .VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W0, .L1, .VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x3E, 0xFF, .W1, .L1, .VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W1, .L0, .VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W1, .L1, .VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W0, .L1, .VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W0, .L0, .VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W0, .L2, .VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x3F, 0xFF, .W1, .L2, .VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x42, 0xFF, .W0, .L0, .VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x42, 0xFF, .W0, .L1, .VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x42, 0xFF, .W0, .L2, .VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W1, .L1, .VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W0, .L2, .VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W0, .L1, .VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W1, .L0, .VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W1, .L2, .VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x50, 0xFF, .W0, .L0, .VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x51, 0xFF, .W0, .LIG, .VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F3A, 1, 0x51, 0xFF, .W1, .LIG, .VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W1, .L2, .VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W1, .L1, .VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W0, .L1, .VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W0, .L0, .VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W0, .L2, .VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x54, 0xFF, .W1, .L0, .VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x55, 0xFF, .W1, .LIG, .VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x55, 0xFF, .W0, .LIG, .VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W1, .L2, .VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W1, .L0, .VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W0, .L1, .VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W0, .L0, .VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W0, .L2, .VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x56, 0xFF, .W1, .L1, .VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x57, 0xFF, .W0, .LIG, .VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
{._0F3A, 1, 0x57, 0xFF, .W1, .LIG, .VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W0, .L0, .VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W0, .L1, .VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W0, .L2, .VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W1, .L0, .VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W1, .L2, .VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
|
|
{._0F3A, 1, 0x66, 0xFF, .W1, .L1, .VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
|
|
{._0F3A, 1, 0x67, 0xFF, .W1, .LIG, .VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
|
|
{._0F3A, 1, 0x67, 0xFF, .W0, .LIG, .VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
|
|
}
|
|
|
|
// =============================================================================
|
|
// Index Tables for O(1) Opcode Lookup
|
|
// =============================================================================
|
|
|
|
// Each entry contains (start_index, count) into LEGACY_DECODE_ENTRIES
|
|
// Indexed by [esc][prefix][opcode]
|
|
Decode_Index :: struct {
|
|
start: u16, // start index in LEGACY_DECODE_ENTRIES
|
|
count: u8, // number of entries
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_INDEX_LEGACY := [4][256]Decode_Index{
|
|
{ // prefix = none
|
|
0x00 = { 0, 1},
|
|
0x01 = { 1, 3},
|
|
0x02 = { 4, 1},
|
|
0x03 = { 5, 3},
|
|
0x04 = { 8, 1},
|
|
0x05 = { 9, 3},
|
|
0x08 = { 12, 1},
|
|
0x09 = { 13, 3},
|
|
0x0A = { 16, 1},
|
|
0x0B = { 17, 3},
|
|
0x0C = { 20, 1},
|
|
0x0D = { 21, 3},
|
|
0x10 = { 24, 1},
|
|
0x11 = { 25, 3},
|
|
0x12 = { 28, 1},
|
|
0x13 = { 29, 3},
|
|
0x14 = { 32, 1},
|
|
0x15 = { 33, 3},
|
|
0x18 = { 36, 1},
|
|
0x19 = { 37, 3},
|
|
0x1A = { 40, 1},
|
|
0x1B = { 41, 3},
|
|
0x1C = { 44, 1},
|
|
0x1D = { 45, 3},
|
|
0x20 = { 48, 1},
|
|
0x21 = { 49, 3},
|
|
0x22 = { 52, 1},
|
|
0x23 = { 53, 3},
|
|
0x24 = { 56, 1},
|
|
0x25 = { 57, 3},
|
|
0x28 = { 60, 1},
|
|
0x29 = { 61, 3},
|
|
0x2A = { 64, 1},
|
|
0x2B = { 65, 3},
|
|
0x2C = { 68, 1},
|
|
0x2D = { 69, 3},
|
|
0x30 = { 72, 1},
|
|
0x31 = { 73, 3},
|
|
0x32 = { 76, 1},
|
|
0x33 = { 77, 3},
|
|
0x34 = { 80, 1},
|
|
0x35 = { 81, 3},
|
|
0x38 = { 84, 1},
|
|
0x39 = { 85, 3},
|
|
0x3A = { 88, 1},
|
|
0x3B = { 89, 3},
|
|
0x3C = { 92, 1},
|
|
0x3D = { 93, 3},
|
|
0x40 = { 96, 2},
|
|
0x48 = { 98, 2},
|
|
0x50 = { 100, 2},
|
|
0x58 = { 102, 2},
|
|
0x62 = { 104, 2},
|
|
0x63 = { 106, 2},
|
|
0x68 = { 108, 2},
|
|
0x69 = { 110, 3},
|
|
0x6A = { 113, 1},
|
|
0x6B = { 114, 3},
|
|
0x70 = { 117, 1},
|
|
0x71 = { 118, 1},
|
|
0x72 = { 119, 3},
|
|
0x73 = { 122, 3},
|
|
0x74 = { 125, 2},
|
|
0x75 = { 127, 2},
|
|
0x76 = { 129, 2},
|
|
0x77 = { 131, 2},
|
|
0x78 = { 133, 1},
|
|
0x79 = { 134, 1},
|
|
0x7A = { 135, 2},
|
|
0x7B = { 137, 2},
|
|
0x7C = { 139, 2},
|
|
0x7D = { 141, 2},
|
|
0x7E = { 143, 2},
|
|
0x7F = { 145, 2},
|
|
0x80 = { 147, 8},
|
|
0x81 = { 155, 24},
|
|
0x83 = { 179, 24},
|
|
0x84 = { 203, 1},
|
|
0x85 = { 204, 3},
|
|
0x86 = { 207, 1},
|
|
0x87 = { 208, 3},
|
|
0x88 = { 211, 1},
|
|
0x89 = { 212, 3},
|
|
0x8A = { 215, 1},
|
|
0x8B = { 216, 3},
|
|
0x8C = { 219, 2},
|
|
0x8D = { 221, 3},
|
|
0x8E = { 224, 2},
|
|
0x8F = { 226, 2},
|
|
0x90 = { 228, 4},
|
|
0x98 = { 232, 3},
|
|
0x99 = { 235, 3},
|
|
0x9B = { 238, 2},
|
|
0x9C = { 240, 3},
|
|
0x9D = { 243, 3},
|
|
0x9E = { 246, 1},
|
|
0x9F = { 247, 1},
|
|
0xA0 = { 248, 2},
|
|
0xA1 = { 250, 6},
|
|
0xA2 = { 256, 2},
|
|
0xA3 = { 258, 6},
|
|
0xA4 = { 264, 2},
|
|
0xA5 = { 266, 3},
|
|
0xA6 = { 269, 2},
|
|
0xA7 = { 271, 3},
|
|
0xA8 = { 274, 1},
|
|
0xA9 = { 275, 3},
|
|
0xAA = { 278, 2},
|
|
0xAB = { 280, 3},
|
|
0xAC = { 283, 2},
|
|
0xAD = { 285, 3},
|
|
0xAE = { 288, 2},
|
|
0xAF = { 290, 3},
|
|
0xB0 = { 293, 1},
|
|
0xB8 = { 294, 4},
|
|
0xC0 = { 298, 7},
|
|
0xC1 = { 305, 21},
|
|
0xC2 = { 326, 1},
|
|
0xC3 = { 327, 1},
|
|
0xC6 = { 328, 1},
|
|
0xC7 = { 329, 3},
|
|
0xC8 = { 332, 1},
|
|
0xC9 = { 333, 1},
|
|
0xCC = { 334, 1},
|
|
0xCD = { 335, 1},
|
|
0xCE = { 336, 1},
|
|
0xCF = { 337, 3},
|
|
0xD0 = { 340, 7},
|
|
0xD1 = { 347, 21},
|
|
0xD2 = { 368, 7},
|
|
0xD3 = { 375, 21},
|
|
0xD7 = { 396, 2},
|
|
0xD8 = { 398, 18},
|
|
0xD9 = { 416, 40},
|
|
0xDA = { 456, 13},
|
|
0xDB = { 469, 16},
|
|
0xDC = { 485, 14},
|
|
0xDD = { 499, 16},
|
|
0xDE = { 515, 21},
|
|
0xDF = { 536, 13},
|
|
0xE0 = { 549, 1},
|
|
0xE1 = { 550, 1},
|
|
0xE2 = { 551, 1},
|
|
0xE3 = { 552, 3},
|
|
0xE8 = { 555, 1},
|
|
0xE9 = { 556, 1},
|
|
0xEB = { 557, 1},
|
|
0xF0 = { 558, 1},
|
|
0xF4 = { 559, 1},
|
|
0xF5 = { 560, 1},
|
|
0xF6 = { 561, 7},
|
|
0xF7 = { 568, 21},
|
|
0xF8 = { 589, 1},
|
|
0xF9 = { 590, 1},
|
|
0xFA = { 591, 1},
|
|
0xFB = { 592, 1},
|
|
0xFC = { 593, 1},
|
|
0xFD = { 594, 1},
|
|
0xFE = { 595, 2},
|
|
0xFF = { 597, 16},
|
|
},
|
|
{ // prefix = 66
|
|
},
|
|
{ // prefix = F3
|
|
0x90 = { 613, 1},
|
|
},
|
|
{ // prefix = F2
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_INDEX_ESC_0F := [4][256]Decode_Index{
|
|
{ // prefix = none
|
|
0x00 = { 614, 10},
|
|
0x01 = { 624, 26},
|
|
0x02 = { 650, 3},
|
|
0x03 = { 653, 3},
|
|
0x05 = { 656, 1},
|
|
0x06 = { 657, 1},
|
|
0x07 = { 658, 1},
|
|
0x08 = { 659, 1},
|
|
0x09 = { 660, 1},
|
|
0x0B = { 661, 1},
|
|
0x0D = { 662, 1},
|
|
0x10 = { 663, 1},
|
|
0x11 = { 664, 1},
|
|
0x12 = { 665, 2},
|
|
0x13 = { 667, 1},
|
|
0x14 = { 668, 1},
|
|
0x15 = { 669, 1},
|
|
0x16 = { 670, 2},
|
|
0x17 = { 672, 1},
|
|
0x18 = { 673, 4},
|
|
0x1C = { 677, 1},
|
|
0x1F = { 678, 3},
|
|
0x20 = { 681, 1},
|
|
0x21 = { 682, 1},
|
|
0x22 = { 683, 1},
|
|
0x23 = { 684, 1},
|
|
0x28 = { 685, 1},
|
|
0x29 = { 686, 1},
|
|
0x2B = { 687, 1},
|
|
0x2E = { 688, 1},
|
|
0x2F = { 689, 1},
|
|
0x30 = { 690, 1},
|
|
0x31 = { 691, 1},
|
|
0x32 = { 692, 1},
|
|
0x33 = { 693, 1},
|
|
0x34 = { 694, 1},
|
|
0x35 = { 695, 1},
|
|
0x40 = { 696, 3},
|
|
0x41 = { 699, 3},
|
|
0x42 = { 702, 9},
|
|
0x43 = { 711, 9},
|
|
0x44 = { 720, 6},
|
|
0x45 = { 726, 6},
|
|
0x46 = { 732, 6},
|
|
0x47 = { 738, 6},
|
|
0x48 = { 744, 3},
|
|
0x49 = { 747, 3},
|
|
0x4A = { 750, 6},
|
|
0x4B = { 756, 6},
|
|
0x4C = { 762, 6},
|
|
0x4D = { 768, 6},
|
|
0x4E = { 774, 6},
|
|
0x4F = { 780, 6},
|
|
0x50 = { 786, 2},
|
|
0x51 = { 788, 1},
|
|
0x52 = { 789, 1},
|
|
0x53 = { 790, 1},
|
|
0x54 = { 791, 1},
|
|
0x55 = { 792, 1},
|
|
0x56 = { 793, 1},
|
|
0x57 = { 794, 1},
|
|
0x58 = { 795, 1},
|
|
0x59 = { 796, 1},
|
|
0x5A = { 797, 1},
|
|
0x5B = { 798, 1},
|
|
0x5C = { 799, 1},
|
|
0x5D = { 800, 1},
|
|
0x5E = { 801, 1},
|
|
0x5F = { 802, 1},
|
|
0x6E = { 803, 1},
|
|
0x6F = { 804, 1},
|
|
0x70 = { 805, 1},
|
|
0x78 = { 806, 1},
|
|
0x79 = { 807, 1},
|
|
0x7E = { 808, 1},
|
|
0x7F = { 809, 1},
|
|
0x80 = { 810, 1},
|
|
0x81 = { 811, 1},
|
|
0x82 = { 812, 3},
|
|
0x83 = { 815, 3},
|
|
0x84 = { 818, 2},
|
|
0x85 = { 820, 2},
|
|
0x86 = { 822, 2},
|
|
0x87 = { 824, 2},
|
|
0x88 = { 826, 1},
|
|
0x89 = { 827, 1},
|
|
0x8A = { 828, 2},
|
|
0x8B = { 830, 2},
|
|
0x8C = { 832, 2},
|
|
0x8D = { 834, 2},
|
|
0x8E = { 836, 2},
|
|
0x8F = { 838, 2},
|
|
0x90 = { 840, 1},
|
|
0x91 = { 841, 1},
|
|
0x92 = { 842, 3},
|
|
0x93 = { 845, 3},
|
|
0x94 = { 848, 2},
|
|
0x95 = { 850, 2},
|
|
0x96 = { 852, 2},
|
|
0x97 = { 854, 2},
|
|
0x98 = { 856, 1},
|
|
0x99 = { 857, 1},
|
|
0x9A = { 858, 2},
|
|
0x9B = { 860, 2},
|
|
0x9C = { 862, 2},
|
|
0x9D = { 864, 2},
|
|
0x9E = { 866, 2},
|
|
0x9F = { 868, 2},
|
|
0xA0 = { 870, 1},
|
|
0xA1 = { 871, 1},
|
|
0xA2 = { 872, 1},
|
|
0xA3 = { 873, 3},
|
|
0xA4 = { 876, 3},
|
|
0xA5 = { 879, 3},
|
|
0xA8 = { 882, 1},
|
|
0xA9 = { 883, 1},
|
|
0xAA = { 884, 1},
|
|
0xAB = { 885, 3},
|
|
0xAC = { 888, 3},
|
|
0xAD = { 891, 3},
|
|
0xAE = { 894, 14},
|
|
0xAF = { 908, 3},
|
|
0xB0 = { 911, 1},
|
|
0xB1 = { 912, 3},
|
|
0xB3 = { 915, 3},
|
|
0xB6 = { 918, 3},
|
|
0xB7 = { 921, 2},
|
|
0xB9 = { 923, 1},
|
|
0xBA = { 924, 12},
|
|
0xBB = { 936, 3},
|
|
0xBC = { 939, 3},
|
|
0xBD = { 942, 3},
|
|
0xBE = { 945, 3},
|
|
0xBF = { 948, 2},
|
|
0xC0 = { 950, 1},
|
|
0xC1 = { 951, 3},
|
|
0xC2 = { 954, 1},
|
|
0xC6 = { 955, 1},
|
|
0xC7 = { 956, 16},
|
|
0xC8 = { 972, 2},
|
|
0xFF = { 974, 1},
|
|
},
|
|
{ // prefix = 66
|
|
0x10 = { 975, 1},
|
|
0x11 = { 976, 1},
|
|
0x12 = { 977, 1},
|
|
0x13 = { 978, 1},
|
|
0x14 = { 979, 1},
|
|
0x15 = { 980, 1},
|
|
0x16 = { 981, 1},
|
|
0x17 = { 982, 1},
|
|
0x28 = { 983, 1},
|
|
0x29 = { 984, 1},
|
|
0x2B = { 985, 1},
|
|
0x2E = { 986, 1},
|
|
0x2F = { 987, 1},
|
|
0x50 = { 988, 2},
|
|
0x51 = { 990, 1},
|
|
0x54 = { 991, 1},
|
|
0x55 = { 992, 1},
|
|
0x56 = { 993, 1},
|
|
0x57 = { 994, 1},
|
|
0x58 = { 995, 1},
|
|
0x59 = { 996, 1},
|
|
0x5A = { 997, 1},
|
|
0x5B = { 998, 1},
|
|
0x5C = { 999, 1},
|
|
0x5D = {1000, 1},
|
|
0x5E = {1001, 1},
|
|
0x5F = {1002, 1},
|
|
0x60 = {1003, 1},
|
|
0x61 = {1004, 1},
|
|
0x62 = {1005, 1},
|
|
0x63 = {1006, 1},
|
|
0x64 = {1007, 1},
|
|
0x65 = {1008, 1},
|
|
0x66 = {1009, 1},
|
|
0x67 = {1010, 1},
|
|
0x68 = {1011, 1},
|
|
0x69 = {1012, 1},
|
|
0x6A = {1013, 1},
|
|
0x6B = {1014, 1},
|
|
0x6C = {1015, 1},
|
|
0x6D = {1016, 1},
|
|
0x6E = {1017, 2},
|
|
0x6F = {1019, 1},
|
|
0x70 = {1020, 1},
|
|
0x71 = {1021, 3},
|
|
0x72 = {1024, 3},
|
|
0x73 = {1027, 2},
|
|
0x74 = {1029, 1},
|
|
0x75 = {1030, 1},
|
|
0x76 = {1031, 1},
|
|
0x7C = {1032, 1},
|
|
0x7D = {1033, 1},
|
|
0x7E = {1034, 2},
|
|
0x7F = {1036, 1},
|
|
0xAE = {1037, 2},
|
|
0xC2 = {1039, 1},
|
|
0xC4 = {1040, 2},
|
|
0xC5 = {1042, 2},
|
|
0xC6 = {1044, 1},
|
|
0xC7 = {1045, 1},
|
|
0xD0 = {1046, 1},
|
|
0xD1 = {1047, 1},
|
|
0xD2 = {1048, 1},
|
|
0xD3 = {1049, 1},
|
|
0xD4 = {1050, 1},
|
|
0xD5 = {1051, 1},
|
|
0xD6 = {1052, 1},
|
|
0xD7 = {1053, 2},
|
|
0xD8 = {1055, 1},
|
|
0xD9 = {1056, 1},
|
|
0xDA = {1057, 1},
|
|
0xDB = {1058, 1},
|
|
0xDC = {1059, 1},
|
|
0xDD = {1060, 1},
|
|
0xDE = {1061, 1},
|
|
0xDF = {1062, 1},
|
|
0xE0 = {1063, 1},
|
|
0xE1 = {1064, 1},
|
|
0xE2 = {1065, 1},
|
|
0xE3 = {1066, 1},
|
|
0xE4 = {1067, 1},
|
|
0xE5 = {1068, 1},
|
|
0xE6 = {1069, 1},
|
|
0xE7 = {1070, 1},
|
|
0xE8 = {1071, 1},
|
|
0xE9 = {1072, 1},
|
|
0xEA = {1073, 1},
|
|
0xEB = {1074, 1},
|
|
0xEC = {1075, 1},
|
|
0xED = {1076, 1},
|
|
0xEE = {1077, 1},
|
|
0xEF = {1078, 1},
|
|
0xF1 = {1079, 1},
|
|
0xF2 = {1080, 1},
|
|
0xF3 = {1081, 1},
|
|
0xF4 = {1082, 1},
|
|
0xF5 = {1083, 1},
|
|
0xF6 = {1084, 1},
|
|
0xF7 = {1085, 1},
|
|
0xF8 = {1086, 1},
|
|
0xF9 = {1087, 1},
|
|
0xFA = {1088, 1},
|
|
0xFB = {1089, 1},
|
|
0xFC = {1090, 1},
|
|
0xFD = {1091, 1},
|
|
0xFE = {1092, 1},
|
|
},
|
|
{ // prefix = F3
|
|
0x01 = {1093, 3},
|
|
0x10 = {1096, 1},
|
|
0x11 = {1097, 1},
|
|
0x12 = {1098, 1},
|
|
0x16 = {1099, 1},
|
|
0x1E = {1100, 4},
|
|
0x2A = {1104, 2},
|
|
0x2C = {1106, 2},
|
|
0x2D = {1108, 2},
|
|
0x51 = {1110, 1},
|
|
0x52 = {1111, 1},
|
|
0x53 = {1112, 1},
|
|
0x58 = {1113, 1},
|
|
0x59 = {1114, 1},
|
|
0x5A = {1115, 1},
|
|
0x5B = {1116, 1},
|
|
0x5C = {1117, 1},
|
|
0x5D = {1118, 1},
|
|
0x5E = {1119, 1},
|
|
0x5F = {1120, 1},
|
|
0x6F = {1121, 1},
|
|
0x70 = {1122, 1},
|
|
0x7E = {1123, 1},
|
|
0x7F = {1124, 1},
|
|
0xAE = {1125, 3},
|
|
0xB8 = {1128, 3},
|
|
0xBC = {1131, 3},
|
|
0xBD = {1134, 3},
|
|
0xC2 = {1137, 1},
|
|
0xC7 = {1138, 1},
|
|
0xE6 = {1139, 1},
|
|
},
|
|
{ // prefix = F2
|
|
0x10 = {1140, 1},
|
|
0x11 = {1141, 1},
|
|
0x12 = {1142, 1},
|
|
0x2A = {1143, 2},
|
|
0x2C = {1145, 2},
|
|
0x2D = {1147, 2},
|
|
0x51 = {1149, 1},
|
|
0x58 = {1150, 1},
|
|
0x59 = {1151, 1},
|
|
0x5A = {1152, 1},
|
|
0x5C = {1153, 1},
|
|
0x5D = {1154, 1},
|
|
0x5E = {1155, 1},
|
|
0x5F = {1156, 1},
|
|
0x70 = {1157, 1},
|
|
0x7C = {1158, 1},
|
|
0x7D = {1159, 1},
|
|
0xC2 = {1160, 1},
|
|
0xD0 = {1161, 1},
|
|
0xE6 = {1162, 1},
|
|
0xF0 = {1163, 1},
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_INDEX_ESC_0F38 := [4][256]Decode_Index{
|
|
{ // prefix = none
|
|
0xC8 = {1164, 1},
|
|
0xC9 = {1165, 1},
|
|
0xCA = {1166, 1},
|
|
0xCB = {1167, 1},
|
|
0xCC = {1168, 1},
|
|
0xCD = {1169, 1},
|
|
0xF0 = {1170, 3},
|
|
0xF1 = {1173, 3},
|
|
0xF6 = {1176, 2},
|
|
},
|
|
{ // prefix = 66
|
|
0x00 = {1178, 1},
|
|
0x01 = {1179, 1},
|
|
0x02 = {1180, 1},
|
|
0x03 = {1181, 1},
|
|
0x04 = {1182, 1},
|
|
0x05 = {1183, 1},
|
|
0x06 = {1184, 1},
|
|
0x07 = {1185, 1},
|
|
0x08 = {1186, 1},
|
|
0x09 = {1187, 1},
|
|
0x0A = {1188, 1},
|
|
0x0B = {1189, 1},
|
|
0x10 = {1190, 1},
|
|
0x14 = {1191, 1},
|
|
0x15 = {1192, 1},
|
|
0x17 = {1193, 1},
|
|
0x1C = {1194, 1},
|
|
0x1D = {1195, 1},
|
|
0x1E = {1196, 1},
|
|
0x20 = {1197, 1},
|
|
0x21 = {1198, 1},
|
|
0x22 = {1199, 1},
|
|
0x23 = {1200, 1},
|
|
0x24 = {1201, 1},
|
|
0x25 = {1202, 1},
|
|
0x28 = {1203, 1},
|
|
0x29 = {1204, 1},
|
|
0x2A = {1205, 1},
|
|
0x2B = {1206, 1},
|
|
0x30 = {1207, 1},
|
|
0x31 = {1208, 1},
|
|
0x32 = {1209, 1},
|
|
0x33 = {1210, 1},
|
|
0x34 = {1211, 1},
|
|
0x35 = {1212, 1},
|
|
0x37 = {1213, 1},
|
|
0x38 = {1214, 1},
|
|
0x39 = {1215, 1},
|
|
0x3A = {1216, 1},
|
|
0x3B = {1217, 1},
|
|
0x3C = {1218, 1},
|
|
0x3D = {1219, 1},
|
|
0x3E = {1220, 1},
|
|
0x3F = {1221, 1},
|
|
0x40 = {1222, 1},
|
|
0x41 = {1223, 1},
|
|
0x80 = {1224, 1},
|
|
0x81 = {1225, 1},
|
|
0x82 = {1226, 2},
|
|
0xDB = {1228, 1},
|
|
0xDC = {1229, 1},
|
|
0xDD = {1230, 1},
|
|
0xDE = {1231, 1},
|
|
0xDF = {1232, 1},
|
|
0xF5 = {1233, 2},
|
|
0xF6 = {1235, 2},
|
|
},
|
|
{ // prefix = F3
|
|
0xF6 = {1237, 2},
|
|
},
|
|
{ // prefix = F2
|
|
0xF0 = {1239, 2},
|
|
0xF1 = {1241, 3},
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_INDEX_ESC_0F3A := [4][256]Decode_Index{
|
|
{ // prefix = none
|
|
0xCC = {1244, 1},
|
|
},
|
|
{ // prefix = 66
|
|
0x08 = {1245, 1},
|
|
0x09 = {1246, 1},
|
|
0x0A = {1247, 1},
|
|
0x0B = {1248, 1},
|
|
0x0C = {1249, 1},
|
|
0x0D = {1250, 1},
|
|
0x0E = {1251, 1},
|
|
0x0F = {1252, 1},
|
|
0x14 = {1253, 1},
|
|
0x16 = {1254, 2},
|
|
0x17 = {1256, 1},
|
|
0x20 = {1257, 1},
|
|
0x21 = {1258, 1},
|
|
0x22 = {1259, 2},
|
|
0x40 = {1261, 1},
|
|
0x41 = {1262, 1},
|
|
0x42 = {1263, 1},
|
|
0x44 = {1264, 1},
|
|
0x60 = {1265, 1},
|
|
0x61 = {1266, 1},
|
|
0x62 = {1267, 1},
|
|
0x63 = {1268, 1},
|
|
0xDF = {1269, 1},
|
|
},
|
|
{ // prefix = F3
|
|
},
|
|
{ // prefix = F2
|
|
},
|
|
}
|
|
|
|
// =============================================================================
|
|
// VEX Index Tables for O(1) Opcode Lookup
|
|
// =============================================================================
|
|
|
|
// Indexed by [esc_idx][prefix][opcode] where esc_idx: 0=0F, 1=0F38, 2=0F3A
|
|
@(rodata)
|
|
VEX_INDEX_0F := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */
|
|
0x10 = { 0, 2},
|
|
0x11 = { 2, 2},
|
|
0x12 = { 4, 2},
|
|
0x13 = { 6, 1},
|
|
0x14 = { 7, 2},
|
|
0x15 = { 9, 2},
|
|
0x16 = { 11, 2},
|
|
0x17 = { 13, 1},
|
|
0x28 = { 14, 2},
|
|
0x29 = { 16, 2},
|
|
0x2B = { 18, 2},
|
|
0x2E = { 20, 1},
|
|
0x2F = { 21, 1},
|
|
0x41 = { 22, 2},
|
|
0x42 = { 24, 2},
|
|
0x44 = { 26, 2},
|
|
0x45 = { 28, 2},
|
|
0x46 = { 30, 2},
|
|
0x47 = { 32, 2},
|
|
0x4A = { 34, 2},
|
|
0x4B = { 36, 2},
|
|
0x50 = { 38, 2},
|
|
0x51 = { 40, 2},
|
|
0x52 = { 42, 2},
|
|
0x53 = { 44, 2},
|
|
0x54 = { 46, 2},
|
|
0x55 = { 48, 2},
|
|
0x56 = { 50, 2},
|
|
0x57 = { 52, 2},
|
|
0x58 = { 54, 2},
|
|
0x59 = { 56, 2},
|
|
0x5A = { 58, 2},
|
|
0x5B = { 60, 2},
|
|
0x5C = { 62, 2},
|
|
0x5D = { 64, 2},
|
|
0x5E = { 66, 2},
|
|
0x5F = { 68, 2},
|
|
0x77 = { 70, 2},
|
|
0x90 = { 72, 2},
|
|
0x91 = { 74, 2},
|
|
0x92 = { 76, 1},
|
|
0x93 = { 77, 1},
|
|
0x98 = { 78, 2},
|
|
0x99 = { 80, 2},
|
|
0xC2 = { 82, 2},
|
|
0xC6 = { 84, 2},
|
|
},
|
|
1 = { /* prefix = 66 */
|
|
0x10 = { 86, 2},
|
|
0x11 = { 88, 2},
|
|
0x12 = { 90, 1},
|
|
0x13 = { 91, 1},
|
|
0x14 = { 92, 2},
|
|
0x15 = { 94, 2},
|
|
0x16 = { 96, 1},
|
|
0x17 = { 97, 1},
|
|
0x28 = { 98, 2},
|
|
0x29 = {100, 2},
|
|
0x2B = {102, 2},
|
|
0x2E = {104, 1},
|
|
0x2F = {105, 1},
|
|
0x41 = {106, 2},
|
|
0x42 = {108, 2},
|
|
0x44 = {110, 2},
|
|
0x45 = {112, 2},
|
|
0x46 = {114, 2},
|
|
0x47 = {116, 2},
|
|
0x4A = {118, 2},
|
|
0x4B = {120, 1},
|
|
0x50 = {121, 2},
|
|
0x51 = {123, 2},
|
|
0x54 = {125, 2},
|
|
0x55 = {127, 2},
|
|
0x56 = {129, 2},
|
|
0x57 = {131, 2},
|
|
0x58 = {133, 2},
|
|
0x59 = {135, 2},
|
|
0x5A = {137, 2},
|
|
0x5B = {139, 2},
|
|
0x5C = {141, 2},
|
|
0x5D = {143, 2},
|
|
0x5E = {145, 2},
|
|
0x5F = {147, 2},
|
|
0x60 = {149, 2},
|
|
0x61 = {151, 2},
|
|
0x62 = {153, 2},
|
|
0x63 = {155, 2},
|
|
0x64 = {157, 2},
|
|
0x65 = {159, 2},
|
|
0x66 = {161, 2},
|
|
0x67 = {163, 2},
|
|
0x68 = {165, 2},
|
|
0x69 = {167, 2},
|
|
0x6A = {169, 2},
|
|
0x6B = {171, 2},
|
|
0x6C = {173, 2},
|
|
0x6D = {175, 2},
|
|
0x6E = {177, 2},
|
|
0x6F = {179, 2},
|
|
0x70 = {181, 2},
|
|
0x71 = {183, 6},
|
|
0x72 = {189, 6},
|
|
0x73 = {195, 4},
|
|
0x74 = {199, 2},
|
|
0x75 = {201, 2},
|
|
0x76 = {203, 2},
|
|
0x7E = {205, 2},
|
|
0x7F = {207, 2},
|
|
0x90 = {209, 2},
|
|
0x91 = {211, 2},
|
|
0x92 = {213, 1},
|
|
0x93 = {214, 1},
|
|
0x98 = {215, 2},
|
|
0x99 = {217, 2},
|
|
0xC2 = {219, 2},
|
|
0xC4 = {221, 1},
|
|
0xC5 = {222, 1},
|
|
0xC6 = {223, 2},
|
|
0xD1 = {225, 2},
|
|
0xD2 = {227, 2},
|
|
0xD3 = {229, 2},
|
|
0xD4 = {231, 2},
|
|
0xD5 = {233, 2},
|
|
0xD6 = {235, 1},
|
|
0xD7 = {236, 2},
|
|
0xDB = {238, 2},
|
|
0xDF = {240, 2},
|
|
0xE1 = {242, 2},
|
|
0xE2 = {244, 2},
|
|
0xE4 = {246, 2},
|
|
0xE5 = {248, 2},
|
|
0xE6 = {250, 2},
|
|
0xE7 = {252, 2},
|
|
0xEB = {254, 2},
|
|
0xEF = {256, 2},
|
|
0xF1 = {258, 2},
|
|
0xF2 = {260, 2},
|
|
0xF3 = {262, 2},
|
|
0xF4 = {264, 2},
|
|
0xF5 = {266, 2},
|
|
0xF7 = {268, 1},
|
|
0xF8 = {269, 2},
|
|
0xF9 = {271, 2},
|
|
0xFA = {273, 2},
|
|
0xFB = {275, 2},
|
|
0xFC = {277, 2},
|
|
0xFD = {279, 2},
|
|
0xFE = {281, 2},
|
|
},
|
|
2 = { /* prefix = F3 */
|
|
0x10 = {283, 2},
|
|
0x11 = {285, 1},
|
|
0x2A = {286, 2},
|
|
0x2C = {288, 2},
|
|
0x2D = {290, 2},
|
|
0x51 = {292, 1},
|
|
0x52 = {293, 1},
|
|
0x53 = {294, 1},
|
|
0x58 = {295, 1},
|
|
0x59 = {296, 1},
|
|
0x5A = {297, 1},
|
|
0x5B = {298, 2},
|
|
0x5C = {300, 1},
|
|
0x5D = {301, 1},
|
|
0x5E = {302, 1},
|
|
0x5F = {303, 1},
|
|
0x6F = {304, 2},
|
|
0x70 = {306, 2},
|
|
0x7E = {308, 1},
|
|
0x7F = {309, 2},
|
|
0xC2 = {311, 1},
|
|
0xE6 = {312, 2},
|
|
},
|
|
3 = { /* prefix = F2 */
|
|
0x10 = {314, 2},
|
|
0x11 = {316, 1},
|
|
0x2A = {317, 2},
|
|
0x2C = {319, 2},
|
|
0x2D = {321, 2},
|
|
0x51 = {323, 1},
|
|
0x58 = {324, 1},
|
|
0x59 = {325, 1},
|
|
0x5A = {326, 1},
|
|
0x5C = {327, 1},
|
|
0x5D = {328, 1},
|
|
0x5E = {329, 1},
|
|
0x5F = {330, 1},
|
|
0x70 = {331, 2},
|
|
0x92 = {333, 2},
|
|
0x93 = {335, 2},
|
|
0xC2 = {337, 1},
|
|
0xE6 = {338, 2},
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
VEX_INDEX_0F38 := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */
|
|
0xF2 = {340, 2},
|
|
0xF3 = {342, 6},
|
|
0xF5 = {348, 2},
|
|
0xF7 = {350, 2},
|
|
},
|
|
1 = { /* prefix = 66 */
|
|
0x00 = {352, 2},
|
|
0x01 = {354, 2},
|
|
0x02 = {356, 2},
|
|
0x03 = {358, 2},
|
|
0x04 = {360, 2},
|
|
0x05 = {362, 2},
|
|
0x06 = {364, 2},
|
|
0x07 = {366, 2},
|
|
0x08 = {368, 2},
|
|
0x09 = {370, 2},
|
|
0x0A = {372, 2},
|
|
0x0B = {374, 2},
|
|
0x0E = {376, 2},
|
|
0x0F = {378, 2},
|
|
0x13 = {380, 2},
|
|
0x16 = {382, 1},
|
|
0x17 = {383, 2},
|
|
0x18 = {385, 4},
|
|
0x19 = {389, 2},
|
|
0x1A = {391, 1},
|
|
0x1C = {392, 2},
|
|
0x1D = {394, 2},
|
|
0x1E = {396, 2},
|
|
0x20 = {398, 2},
|
|
0x21 = {400, 2},
|
|
0x22 = {402, 2},
|
|
0x23 = {404, 2},
|
|
0x24 = {406, 2},
|
|
0x25 = {408, 2},
|
|
0x28 = {410, 2},
|
|
0x29 = {412, 2},
|
|
0x2A = {414, 2},
|
|
0x2B = {416, 2},
|
|
0x2C = {418, 2},
|
|
0x2D = {420, 2},
|
|
0x2E = {422, 2},
|
|
0x2F = {424, 2},
|
|
0x30 = {426, 2},
|
|
0x31 = {428, 2},
|
|
0x32 = {430, 2},
|
|
0x33 = {432, 2},
|
|
0x34 = {434, 2},
|
|
0x35 = {436, 2},
|
|
0x36 = {438, 1},
|
|
0x37 = {439, 2},
|
|
0x38 = {441, 2},
|
|
0x39 = {443, 2},
|
|
0x3A = {445, 2},
|
|
0x3B = {447, 2},
|
|
0x3C = {449, 2},
|
|
0x3D = {451, 2},
|
|
0x3E = {453, 2},
|
|
0x3F = {455, 2},
|
|
0x40 = {457, 2},
|
|
0x41 = {459, 1},
|
|
0x45 = {460, 4},
|
|
0x46 = {464, 2},
|
|
0x47 = {466, 4},
|
|
0x5A = {470, 1},
|
|
0x8C = {471, 4},
|
|
0x8E = {475, 4},
|
|
0x90 = {479, 4},
|
|
0x91 = {483, 4},
|
|
0x92 = {487, 4},
|
|
0x93 = {491, 4},
|
|
0x96 = {495, 4},
|
|
0x97 = {499, 4},
|
|
0x98 = {503, 4},
|
|
0x99 = {507, 2},
|
|
0x9A = {509, 4},
|
|
0x9B = {513, 2},
|
|
0x9C = {515, 4},
|
|
0x9D = {519, 2},
|
|
0x9E = {521, 4},
|
|
0x9F = {525, 2},
|
|
0xA6 = {527, 4},
|
|
0xA7 = {531, 4},
|
|
0xA8 = {535, 4},
|
|
0xA9 = {539, 2},
|
|
0xAA = {541, 4},
|
|
0xAB = {545, 2},
|
|
0xAC = {547, 4},
|
|
0xAD = {551, 2},
|
|
0xAE = {553, 4},
|
|
0xAF = {557, 2},
|
|
0xB6 = {559, 4},
|
|
0xB7 = {563, 4},
|
|
0xB8 = {567, 4},
|
|
0xB9 = {571, 2},
|
|
0xBA = {573, 4},
|
|
0xBB = {577, 2},
|
|
0xBC = {579, 4},
|
|
0xBD = {583, 2},
|
|
0xBE = {585, 4},
|
|
0xBF = {589, 2},
|
|
0xDB = {591, 1},
|
|
0xDC = {592, 1},
|
|
0xDD = {593, 1},
|
|
0xDE = {594, 1},
|
|
0xDF = {595, 1},
|
|
0xF7 = {596, 2},
|
|
},
|
|
2 = { /* prefix = F3 */
|
|
0xF5 = {598, 2},
|
|
0xF7 = {600, 2},
|
|
},
|
|
3 = { /* prefix = F2 */
|
|
0xF5 = {602, 2},
|
|
0xF6 = {604, 2},
|
|
0xF7 = {606, 2},
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
VEX_INDEX_0F3A := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */ },
|
|
1 = { /* prefix = 66 */
|
|
0x00 = {608, 1},
|
|
0x01 = {609, 1},
|
|
0x02 = {610, 2},
|
|
0x06 = {612, 1},
|
|
0x08 = {613, 2},
|
|
0x09 = {615, 2},
|
|
0x0A = {617, 1},
|
|
0x0B = {618, 1},
|
|
0x0C = {619, 2},
|
|
0x0D = {621, 2},
|
|
0x0E = {623, 2},
|
|
0x0F = {625, 2},
|
|
0x14 = {627, 1},
|
|
0x15 = {628, 1},
|
|
0x16 = {629, 2},
|
|
0x17 = {631, 1},
|
|
0x18 = {632, 1},
|
|
0x19 = {633, 1},
|
|
0x1D = {634, 2},
|
|
0x20 = {636, 1},
|
|
0x21 = {637, 1},
|
|
0x22 = {638, 2},
|
|
0x30 = {640, 2},
|
|
0x31 = {642, 2},
|
|
0x32 = {644, 2},
|
|
0x33 = {646, 2},
|
|
0x38 = {648, 1},
|
|
0x39 = {649, 1},
|
|
0x40 = {650, 2},
|
|
0x41 = {652, 1},
|
|
0x42 = {653, 2},
|
|
0x44 = {655, 2},
|
|
0x46 = {657, 1},
|
|
0x4A = {658, 2},
|
|
0x4B = {660, 2},
|
|
0x4C = {662, 2},
|
|
0xDF = {664, 1},
|
|
},
|
|
2 = { /* prefix = F3 */ },
|
|
3 = { /* prefix = F2 */
|
|
0xF0 = {665, 2},
|
|
},
|
|
}
|
|
|
|
// =============================================================================
|
|
// EVEX Index Tables for O(1) Opcode Lookup
|
|
// =============================================================================
|
|
|
|
// Indexed by [esc_idx][prefix][opcode] where esc_idx: 0=0F, 1=0F38, 2=0F3A
|
|
@(rodata)
|
|
EVEX_INDEX_0F := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */ },
|
|
1 = { /* prefix = 66 */
|
|
0x6F = { 0, 6},
|
|
0x72 = { 6, 12},
|
|
0x7F = { 18, 6},
|
|
},
|
|
2 = { /* prefix = F3 */
|
|
0x6F = { 24, 6},
|
|
0x7F = { 30, 6},
|
|
},
|
|
3 = { /* prefix = F2 */
|
|
0x6F = { 36, 6},
|
|
0x7F = { 42, 6},
|
|
},
|
|
}
|
|
|
|
@(rodata)
|
|
EVEX_INDEX_0F38 := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */ },
|
|
1 = { /* prefix = 66 */
|
|
0x10 = { 48, 3},
|
|
0x11 = { 51, 3},
|
|
0x12 = { 54, 3},
|
|
0x13 = { 57, 1},
|
|
0x14 = { 58, 6},
|
|
0x15 = { 64, 6},
|
|
0x26 = { 70, 6},
|
|
0x27 = { 76, 6},
|
|
0x2C = { 82, 6},
|
|
0x2D = { 88, 2},
|
|
0x42 = { 90, 6},
|
|
0x43 = { 96, 2},
|
|
0x44 = { 98, 6},
|
|
0x46 = {104, 3},
|
|
0x4C = {107, 6},
|
|
0x4D = {113, 2},
|
|
0x4E = {115, 6},
|
|
0x4F = {121, 2},
|
|
0x64 = {123, 6},
|
|
0x65 = {129, 6},
|
|
0x66 = {135, 6},
|
|
0x75 = {141, 6},
|
|
0x76 = {147, 6},
|
|
0x77 = {153, 6},
|
|
0x7D = {159, 6},
|
|
0x7E = {165, 6},
|
|
0x7F = {171, 6},
|
|
0x83 = {177, 3},
|
|
0x88 = {180, 6},
|
|
0x89 = {186, 6},
|
|
0x8A = {192, 6},
|
|
0x8B = {198, 6},
|
|
0x8D = {204, 6},
|
|
0xA0 = {210, 6},
|
|
0xA1 = {216, 6},
|
|
0xA2 = {222, 6},
|
|
0xA3 = {228, 6},
|
|
0xC4 = {234, 6},
|
|
},
|
|
2 = { /* prefix = F3 */
|
|
0x10 = {240, 3},
|
|
0x11 = {243, 3},
|
|
0x12 = {246, 3},
|
|
0x13 = {249, 3},
|
|
0x14 = {252, 3},
|
|
0x15 = {255, 3},
|
|
0x20 = {258, 3},
|
|
0x21 = {261, 3},
|
|
0x22 = {264, 3},
|
|
0x23 = {267, 3},
|
|
0x24 = {270, 3},
|
|
0x25 = {273, 3},
|
|
0x26 = {276, 6},
|
|
0x27 = {282, 6},
|
|
0x28 = {288, 6},
|
|
0x29 = {294, 6},
|
|
0x30 = {300, 3},
|
|
0x31 = {303, 3},
|
|
0x32 = {306, 3},
|
|
0x33 = {309, 3},
|
|
0x34 = {312, 3},
|
|
0x35 = {315, 3},
|
|
0x38 = {318, 6},
|
|
0x39 = {324, 6},
|
|
},
|
|
3 = { /* prefix = F2 */ },
|
|
}
|
|
|
|
@(rodata)
|
|
EVEX_INDEX_0F3A := [4][256]Decode_Index{
|
|
0 = { /* prefix = none */ },
|
|
1 = { /* prefix = 66 */
|
|
0x03 = {330, 6},
|
|
0x08 = {336, 3},
|
|
0x09 = {339, 3},
|
|
0x0A = {342, 1},
|
|
0x0B = {343, 1},
|
|
0x1D = {344, 1},
|
|
0x1E = {345, 6},
|
|
0x1F = {351, 6},
|
|
0x25 = {357, 6},
|
|
0x26 = {363, 6},
|
|
0x27 = {369, 2},
|
|
0x3E = {371, 6},
|
|
0x3F = {377, 6},
|
|
0x42 = {383, 3},
|
|
0x50 = {386, 6},
|
|
0x51 = {392, 2},
|
|
0x54 = {394, 6},
|
|
0x55 = {400, 2},
|
|
0x56 = {402, 6},
|
|
0x57 = {408, 2},
|
|
0x66 = {410, 6},
|
|
0x67 = {416, 2},
|
|
},
|
|
2 = { /* prefix = F3 */ },
|
|
3 = { /* prefix = F2 */ },
|
|
}
|
|
|