mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-20 00:52:33 +00:00
179 lines
15 KiB
Odin
179 lines
15 KiB
Odin
package rexcode_rsp
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// =============================================================================
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// N64 RSP ENCODING_TABLE
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// =============================================================================
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//
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// Two encoding families:
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//
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// Scalar — reuse standard MIPS I bit layouts.
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// Vector ALU — opcode 0x12 with CO=1 (bit 25); element in bits 24-21;
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// vt/vs/vd at the usual rs/rt/rd-equivalent positions; funct at 5-0.
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// Vector L/S — opcode 0x32 (LWC2) or 0x3A (SWC2) with op2 selector
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// at bits 15-11 and 7-bit signed offset at 6-0.
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@(rodata)
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ENCODING_TABLE:= #partial [Mnemonic][]Encoding{
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.INVALID = {},
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// =========================================================================
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// Scalar core
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// =========================================================================
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// R-type arithmetic (SPECIAL, op=0)
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.ADD = { {.ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000020, 0xFC0007FF, .RSP_SCALAR, {}} },
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.ADDU = { {.ADDU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000021, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SUB = { {.SUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000022, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SUBU = { {.SUBU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000023, 0xFC0007FF, .RSP_SCALAR, {}} },
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.AND = { {.AND, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000024, 0xFC0007FF, .RSP_SCALAR, {}} },
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.OR = { {.OR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000025, 0xFC0007FF, .RSP_SCALAR, {}} },
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.XOR = { {.XOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000026, 0xFC0007FF, .RSP_SCALAR, {}} },
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.NOR = { {.NOR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000027, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SLT = { {.SLT, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000002A, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SLTU = { {.SLTU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000002B, 0xFC0007FF, .RSP_SCALAR, {}} },
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// Shifts
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.SLL = { {.SLL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x00000000, 0xFFE0003F, .RSP_SCALAR, {}} },
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.SRL = { {.SRL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x00000002, 0xFFE0003F, .RSP_SCALAR, {}} },
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.SRA = { {.SRA, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x00000003, 0xFFE0003F, .RSP_SCALAR, {}} },
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.SLLV = { {.SLLV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RT,.RS,.NONE}, 0x00000004, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SRLV = { {.SRLV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RT,.RS,.NONE}, 0x00000006, 0xFC0007FF, .RSP_SCALAR, {}} },
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.SRAV = { {.SRAV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RT,.RS,.NONE}, 0x00000007, 0xFC0007FF, .RSP_SCALAR, {}} },
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// I-type
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.ADDI = { {.ADDI, {.GPR,.GPR,.IMM16S,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x20000000, 0xFC000000, .RSP_SCALAR, {}} },
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.ADDIU = { {.ADDIU, {.GPR,.GPR,.IMM16S,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x24000000, 0xFC000000, .RSP_SCALAR, {}} },
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.SLTI = { {.SLTI, {.GPR,.GPR,.IMM16S,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x28000000, 0xFC000000, .RSP_SCALAR, {}} },
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.SLTIU = { {.SLTIU, {.GPR,.GPR,.IMM16S,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x2C000000, 0xFC000000, .RSP_SCALAR, {}} },
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.ANDI = { {.ANDI, {.GPR,.GPR,.IMM16U,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x30000000, 0xFC000000, .RSP_SCALAR, {}} },
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.ORI = { {.ORI, {.GPR,.GPR,.IMM16U,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x34000000, 0xFC000000, .RSP_SCALAR, {}} },
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.XORI = { {.XORI, {.GPR,.GPR,.IMM16U,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x38000000, 0xFC000000, .RSP_SCALAR, {}} },
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.LUI = { {.LUI, {.GPR,.IMM16U,.NONE,.NONE}, {.RT,.IMM_16,.NONE,.NONE}, 0x3C000000, 0xFFE00000, .RSP_SCALAR, {}} },
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// Branches
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.BEQ = { {.BEQ, {.GPR,.GPR,.REL16,.NONE}, {.RS,.RT,.BRANCH_16,.NONE}, 0x10000000, 0xFC000000, .RSP_SCALAR, {delay_slot=true}} },
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.BNE = { {.BNE, {.GPR,.GPR,.REL16,.NONE}, {.RS,.RT,.BRANCH_16,.NONE}, 0x14000000, 0xFC000000, .RSP_SCALAR, {delay_slot=true}} },
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.BLEZ = { {.BLEZ, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x18000000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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.BGTZ = { {.BGTZ, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x1C000000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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.BLTZ = { {.BLTZ, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x04000000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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.BGEZ = { {.BGEZ, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x04010000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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.BLTZAL = { {.BLTZAL, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x04100000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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.BGEZAL = { {.BGEZAL, {.GPR,.REL16,.NONE,.NONE}, {.RS,.BRANCH_16,.NONE,.NONE}, 0x04110000, 0xFC1F0000, .RSP_SCALAR, {delay_slot=true}} },
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// Jumps
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.J = { {.J, {.REL_J26,.NONE,.NONE,.NONE}, {.IMM_26,.NONE,.NONE,.NONE}, 0x08000000, 0xFC000000, .RSP_SCALAR, {delay_slot=true}} },
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.JAL = { {.JAL, {.REL_J26,.NONE,.NONE,.NONE}, {.IMM_26,.NONE,.NONE,.NONE}, 0x0C000000, 0xFC000000, .RSP_SCALAR, {delay_slot=true}} },
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.JR = { {.JR, {.GPR,.NONE,.NONE,.NONE}, {.RS,.NONE,.NONE,.NONE}, 0x00000008, 0xFC1FFFFF, .RSP_SCALAR, {delay_slot=true}} },
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.JALR = { {.JALR, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x00000009, 0xFC1F07FF, .RSP_SCALAR, {delay_slot=true}} },
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// Loads / Stores
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.LB = { {.LB, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x80000000, 0xFC000000, .RSP_SCALAR, {}} },
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.LH = { {.LH, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x84000000, 0xFC000000, .RSP_SCALAR, {}} },
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.LW = { {.LW, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x8C000000, 0xFC000000, .RSP_SCALAR, {}} },
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.LBU = { {.LBU, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x90000000, 0xFC000000, .RSP_SCALAR, {}} },
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.LHU = { {.LHU, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x94000000, 0xFC000000, .RSP_SCALAR, {}} },
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.SB = { {.SB, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0xA0000000, 0xFC000000, .RSP_SCALAR, {}} },
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.SH = { {.SH, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0xA4000000, 0xFC000000, .RSP_SCALAR, {}} },
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.SW = { {.SW, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0xAC000000, 0xFC000000, .RSP_SCALAR, {}} },
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// System
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.BREAK = { {.BREAK, {.IMM20,.NONE,.NONE,.NONE}, {.IMM_20,.NONE,.NONE,.NONE}, 0x0000000D, 0xFC00003F, .RSP_SCALAR, {}} },
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.NOP = { {.NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000000, 0xFFFFFFFF, .RSP_SCALAR, {}} },
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// CP0 / CP2 moves
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.MFC0 = { {.MFC0, {.GPR,.CP0_REG,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x40000000, 0xFFE007FF, .RSP_SCALAR, {}} },
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.MTC0 = { {.MTC0, {.GPR,.CP0_REG,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x40800000, 0xFFE007FF, .RSP_SCALAR, {}} },
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// MFC2/MTC2/CFC2/CTC2 use the RD slot for vector register number + the
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// element field in bits 10-7 of the standard COP2 layout.
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.MFC2 = { {.MFC2, {.GPR,.VR,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x48000000, 0xFFE0007F, .RSP_SCALAR, {}} },
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.MTC2 = { {.MTC2, {.GPR,.VR,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x48800000, 0xFFE0007F, .RSP_SCALAR, {}} },
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.CFC2 = { {.CFC2, {.GPR,.CP2_CTRL,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x48400000, 0xFFE007FF, .RSP_SCALAR, {}} },
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.CTC2 = { {.CTC2, {.GPR,.CP2_CTRL,.NONE,.NONE}, {.RT,.RD,.NONE,.NONE}, 0x48C00000, 0xFFE007FF, .RSP_SCALAR, {}} },
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// =========================================================================
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// Vector ALU (COP2 with CO=1; opcode 0x12). Layout:
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// [op=0x12 6][1=CO][element 4][vt 5][vs 5][vd 5][funct 6]
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// bits = 0x4A000000 | funct;
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// mask = OPCODE | CO | FUNCT = 0xFE00003F
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// (element/vt/vs/vd are all operand-driven)
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// =========================================================================
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.VMULF = { {.VMULF, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000000, 0xFE00003F, .RSP_VU, {}} },
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.VMULU = { {.VMULU, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000001, 0xFE00003F, .RSP_VU, {}} },
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.VMUDL = { {.VMUDL, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000004, 0xFE00003F, .RSP_VU, {}} },
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.VMUDM = { {.VMUDM, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000005, 0xFE00003F, .RSP_VU, {}} },
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.VMUDN = { {.VMUDN, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000006, 0xFE00003F, .RSP_VU, {}} },
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.VMUDH = { {.VMUDH, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000007, 0xFE00003F, .RSP_VU, {}} },
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.VMACF = { {.VMACF, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000008, 0xFE00003F, .RSP_VU, {}} },
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.VMACU = { {.VMACU, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000009, 0xFE00003F, .RSP_VU, {}} },
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.VMADL = { {.VMADL, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00000C, 0xFE00003F, .RSP_VU, {}} },
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.VMADM = { {.VMADM, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00000D, 0xFE00003F, .RSP_VU, {}} },
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.VMADN = { {.VMADN, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00000E, 0xFE00003F, .RSP_VU, {}} },
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.VMADH = { {.VMADH, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00000F, 0xFE00003F, .RSP_VU, {}} },
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.VADD = { {.VADD, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000010, 0xFE00003F, .RSP_VU, {}} },
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.VSUB = { {.VSUB, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000011, 0xFE00003F, .RSP_VU, {}} },
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.VABS = { {.VABS, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000013, 0xFE00003F, .RSP_VU, {}} },
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.VADDC = { {.VADDC, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000014, 0xFE00003F, .RSP_VU, {}} },
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.VSUBC = { {.VSUBC, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000015, 0xFE00003F, .RSP_VU, {}} },
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.VSAR = { {.VSAR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00001D, 0xFE00003F, .RSP_VU, {}} },
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.VLT = { {.VLT, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000020, 0xFE00003F, .RSP_VU, {}} },
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.VEQ = { {.VEQ, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000021, 0xFE00003F, .RSP_VU, {}} },
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.VNE = { {.VNE, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000022, 0xFE00003F, .RSP_VU, {}} },
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.VGE = { {.VGE, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000023, 0xFE00003F, .RSP_VU, {}} },
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.VCL = { {.VCL, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000024, 0xFE00003F, .RSP_VU, {}} },
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.VCH = { {.VCH, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000025, 0xFE00003F, .RSP_VU, {}} },
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.VCR = { {.VCR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000026, 0xFE00003F, .RSP_VU, {}} },
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.VMRG = { {.VMRG, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000027, 0xFE00003F, .RSP_VU, {}} },
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.VAND = { {.VAND, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000028, 0xFE00003F, .RSP_VU, {}} },
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.VNAND = { {.VNAND, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000029, 0xFE00003F, .RSP_VU, {}} },
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.VOR = { {.VOR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00002A, 0xFE00003F, .RSP_VU, {}} },
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.VNOR = { {.VNOR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00002B, 0xFE00003F, .RSP_VU, {}} },
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.VXOR = { {.VXOR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00002C, 0xFE00003F, .RSP_VU, {}} },
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.VNXOR = { {.VNXOR, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A00002D, 0xFE00003F, .RSP_VU, {}} },
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.VRCP = { {.VRCP, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000030, 0xFE00003F, .RSP_VU, {}} },
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.VRCPL = { {.VRCPL, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000031, 0xFE00003F, .RSP_VU, {}} },
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.VRCPH = { {.VRCPH, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000032, 0xFE00003F, .RSP_VU, {}} },
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.VMOV = { {.VMOV, {.VR,.VR_ELEM,.NONE,.NONE}, {.VD,.VT,.NONE,.NONE}, 0x4A000033, 0xFE00003F, .RSP_VU, {}} },
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.VRSQ = { {.VRSQ, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000034, 0xFE00003F, .RSP_VU, {}} },
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.VRSQL = { {.VRSQL, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000035, 0xFE00003F, .RSP_VU, {}} },
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.VRSQH = { {.VRSQH, {.VR,.VR,.VR_ELEM,.NONE}, {.VD,.VS,.VT,.NONE}, 0x4A000036, 0xFE00003F, .RSP_VU, {}} },
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.VNOP = { {.VNOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000037, 0xFE00003F, .RSP_VU, {}} },
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// =========================================================================
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// Vector loads (LWC2 = opcode 0x32). Layout:
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// [op=0x32 6][base 5][vt 5][op2 5][element 4][offset 7]
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// bits = 0xC8000000 | (op2 << 11);
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// mask = OPCODE | (op2 field, bits 15-11) = 0xFC00F800
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// (vt/base/element/offset are operand-driven)
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// =========================================================================
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.LBV = { {.LBV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8000000, 0xFC00F800, .RSP_VLS, {}} },
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.LSV = { {.LSV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8000800, 0xFC00F800, .RSP_VLS, {}} },
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.LLV = { {.LLV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8001000, 0xFC00F800, .RSP_VLS, {}} },
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.LDV = { {.LDV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8001800, 0xFC00F800, .RSP_VLS, {}} },
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.LQV = { {.LQV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8002000, 0xFC00F800, .RSP_VLS, {}} },
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.LRV = { {.LRV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8002800, 0xFC00F800, .RSP_VLS, {}} },
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.LPV = { {.LPV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8003000, 0xFC00F800, .RSP_VLS, {}} },
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.LUV = { {.LUV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8003800, 0xFC00F800, .RSP_VLS, {}} },
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.LHV = { {.LHV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8004000, 0xFC00F800, .RSP_VLS, {}} },
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.LFV = { {.LFV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8004800, 0xFC00F800, .RSP_VLS, {}} },
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.LWV = { {.LWV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8005000, 0xFC00F800, .RSP_VLS, {}} },
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.LTV = { {.LTV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xC8005800, 0xFC00F800, .RSP_VLS, {}} },
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// =========================================================================
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// Vector stores (SWC2 = opcode 0x3A). Same layout as loads.
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// =========================================================================
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.SBV = { {.SBV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8000000, 0xFC00F800, .RSP_VLS, {}} },
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.SSV = { {.SSV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8000800, 0xFC00F800, .RSP_VLS, {}} },
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.SLV = { {.SLV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8001000, 0xFC00F800, .RSP_VLS, {}} },
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.SDV = { {.SDV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8001800, 0xFC00F800, .RSP_VLS, {}} },
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.SQV = { {.SQV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8002000, 0xFC00F800, .RSP_VLS, {}} },
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.SRV = { {.SRV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8002800, 0xFC00F800, .RSP_VLS, {}} },
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.SPV = { {.SPV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8003000, 0xFC00F800, .RSP_VLS, {}} },
|
|
.SUV = { {.SUV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8003800, 0xFC00F800, .RSP_VLS, {}} },
|
|
.SHV = { {.SHV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8004000, 0xFC00F800, .RSP_VLS, {}} },
|
|
.SFV = { {.SFV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8004800, 0xFC00F800, .RSP_VLS, {}} },
|
|
.SWV = { {.SWV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8005000, 0xFC00F800, .RSP_VLS, {}} },
|
|
.STV = { {.STV, {.VR,.VMEM,.NONE,.NONE}, {.VT_LS,.VBASE,.NONE,.NONE}, 0xE8005800, 0xFC00F800, .RSP_VLS, {}} },
|
|
}
|