mirror of
https://github.com/odin-lang/Odin.git
synced 2026-09-03 10:40:20 +00:00
582 lines
17 KiB
C++
582 lines
17 KiB
C++
struct AsmBlock {
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i32 first, last;
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Array<i32> succs;
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u16 in_defs;
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u16 out_defs;
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PtrSet<Entity *> in_params;
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PtrSet<Entity *> out_params;
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bool reachable;
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};
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struct AsmInstructionFacts {
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AstAsmInstruction *node;
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String name;
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u16 gen_regs;
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u16 read_regs;
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Array<Entity *> gen_params;
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Array<Entity *> read_params;
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bool is_control;
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bool is_conditional;
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bool is_terminal;
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Entity *branch_target;
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i32 block_id;
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};
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struct AsmCfg {
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// Union of registers implicitly clobbered by matched forms (for redundant-#clobber hints).
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u16 implicit_clobbered_regs;
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u16 explicitly_produced_regs;
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u16 stale_outputs;
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bool saw_any_instructions; // NOTE(bill): An empty diverging body cannot diverge.
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// NOTE(bill): Related to #align_stack
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// any call/branch (CONTROL) or memory effect that could require the stack
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// to be realigned. If none occurred, #align_stack is redundant.
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bool saw_call_or_mem;
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// Purity test
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bool can_be_pure;
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char const *impure_reason;
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Ast * impure_reason_node;
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PtrMap<AstAsmInstruction *, AsmInstructionFacts> instruction_facts;
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Array<AstAsmInstruction *> insts; // program-order (only for fact-carrying instrs)
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Array<AsmBlock> blocks;
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PtrMap<Entity *, i32> label_block; // key: Entity_Label*
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PtrMap<Entity *, i32> entity_to_index;
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Array<u16> decl_pin_bit;
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u64 universe_pm;
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};
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gb_internal void asm_cfg_init(AsmCfg *cfg) {
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map_init(&cfg->instruction_facts);
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map_init(&cfg->entity_to_index);
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cfg->decl_pin_bit.allocator = heap_allocator();
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cfg->can_be_pure = true;
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};
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gb_internal void asm_cfg_destroy(AsmCfg *cfg) {
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for (auto &block : cfg->blocks) {
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array_free(&block.succs);
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ptr_set_destroy(&block.in_params);
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ptr_set_destroy(&block.out_params);
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}
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array_free(&cfg->blocks);
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array_free(&cfg->insts);
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map_destroy(&cfg->label_block);
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map_destroy(&cfg->instruction_facts);
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map_destroy(&cfg->entity_to_index);
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array_free(&cfg->decl_pin_bit);
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}
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// The physical-register bit a decl is pinned to. A width-view carries no pin of
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// its own; it inherits its source decl's pin. Returns 0 for unpinned decls.
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template <typename AsmCtx>
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gb_internal u16 asm_decl_resolve_pin_bit(AsmCtx *asm_ctx, Array<AsmTemplateEntityDecl> const &decls, i32 di) {
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if (di < 0 || di >= cast(i32)decls.count) {
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return 0;
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}
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auto const &ed = decls[di];
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if (ed.pin.len != 0) {
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return asm_ctx->clobber_bit_for_reg_name(ed.pin);
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}
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if (ed.view_of >= 0 && ed.view_of < cast(i32)decls.count) {
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String src_pin = decls[ed.view_of].pin;
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if (src_pin.len != 0) {
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return asm_ctx->clobber_bit_for_reg_name(src_pin);
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}
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}
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return 0;
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}
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template <typename AsmCtx>
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gb_internal void asm_cfg_populate_decls(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *entity) {
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auto const &decls = entity->AsmTemplate.decls;
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cfg->universe_pm = 0;
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if (decls.count > 64) {
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// NOTE(bill): check_asm_cfg_analyse will err on this since this is exceed the maximum number of declarations
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return;
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}
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array_resize(&cfg->decl_pin_bit, decls.count);
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for_array(i, decls) {
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Entity *e = decls[i].entity;
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cfg->decl_pin_bit[i] = asm_decl_resolve_pin_bit(asm_ctx, decls, cast(i32)i);
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if (e != nullptr) {
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map_set(&cfg->entity_to_index, e, cast(i32)i);
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cfg->universe_pm |= (cast(u64)1 << i);
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}
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}
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_build(AsmCtx *asm_ctx, AsmCfg *cfg, Ast *at_node, Entity *entity) {
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ast_node(at, AsmTemplate, at_node);
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asm_cfg_populate_decls(asm_ctx, cfg, entity);
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cfg->insts.allocator = heap_allocator();
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cfg->blocks.allocator = heap_allocator();
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map_init(&cfg->label_block);
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bool need_leader = true;
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// Build basic blocks over the template body. A leader is: the first instruction, any
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// instruction preceded by a label, and any instruction following a control transfer.
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for (Ast *node : at->instructions) {
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if (node->kind == Ast_AsmLabelDecl) {
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// Every label between two instructions names the block the *next* instruction
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// opens; consecutive labels share it. A trailing label maps to blocks.count.
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Entity *le = node->AsmLabelDecl.name->Ident.entity;
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if (le != nullptr) {
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map_set(&cfg->label_block, le, cast(i32)cfg->blocks.count);
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}
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need_leader = true;
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continue;
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}
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if (node->kind != Ast_AsmInstruction) {
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continue; // directives are straight-line filler; no CFG effect
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}
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AstAsmInstruction *instr = &node->AsmInstruction;
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AsmInstructionFacts *facts = map_get(&cfg->instruction_facts, instr);
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// Prefixes and pseudo-macro ops (li/la) carry no facts and never branch.
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if (need_leader || cfg->blocks.count == 0) {
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AsmBlock b = {};
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b.first = cast(i32)cfg->insts.count;
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b.last = cast(i32)cfg->insts.count;
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b.succs.allocator = heap_allocator();
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array_add(&cfg->blocks, b);
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need_leader = false;
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}
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i32 bi = cast(i32)cfg->blocks.count - 1;
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i32 ii = cast(i32)cfg->insts.count;
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array_add(&cfg->insts, instr);
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cfg->blocks[bi].last = ii;
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if (facts != nullptr) {
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facts->block_id = bi;
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if (facts->is_control) {
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need_leader = true; // the fall-through after a branch starts a new block
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}
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}
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}
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for_array(bi, cfg->blocks) { // Calculate the edges for the blocks
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AsmBlock *b = &cfg->blocks[bi];
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AstAsmInstruction *last = cfg->insts[b->last];
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AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last);
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i32 branch_succ = -1;
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bool fallthrough = true;
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if (lf != nullptr && lf->is_control) {
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if (lf->branch_target != nullptr) {
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i32 *t = map_get(&cfg->label_block, lf->branch_target);
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if (t != nullptr && *t < cast(i32)cfg->blocks.count) {
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branch_succ = *t; // in-range internal target ('jmp .l' / 'jz .l')
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}
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// For `t == blocks.count`, this implies a jump to the implicit end, and is handled as "leaves" below
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}
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// e.g. jmp/ret/hlt (and, conservatively, call) do not fall through in this model.
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if (lf->is_terminal) {
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fallthrough = false;
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}
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}
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if (branch_succ >= 0) {
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array_add(&b->succs, branch_succ);
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}
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if (fallthrough) {
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i32 next = cast(i32)bi + 1;
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if (next < cast(i32)cfg->blocks.count) {
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array_add(&b->succs, next);
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}
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}
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}
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if (cfg->blocks.count != 0) { // Reachability determination
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Array<i32> stack = {};
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stack.allocator = heap_allocator();
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defer (array_free(&stack));
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cfg->blocks[0].reachable = true;
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array_add(&stack, cast(i32)0);
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while (stack.count > 0) {
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i32 bi = stack[stack.count-1];
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stack.count -= 1;
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for (i32 s : cfg->blocks[bi].succs) {
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if (s >= 0 && s < cast(i32)cfg->blocks.count && !cfg->blocks[s].reachable) {
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cfg->blocks[s].reachable = true;
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array_add(&stack, s);
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}
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}
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}
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}
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}
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gb_internal bool check_asm_cfg_block_leaves(AsmCfg *cfg, i32 bi) {
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AsmBlock const *b = &cfg->blocks[bi];
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AstAsmInstruction *last = cfg->insts[b->last];
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AsmInstructionFacts *lf = map_get(&cfg->instruction_facts, last);
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if (lf != nullptr && lf->branch_target != nullptr) {
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i32 *t = map_get(&cfg->label_block, lf->branch_target);
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if (t != nullptr && *t >= cast(i32)cfg->blocks.count) {
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return true; // 'jmp .end' — falls into the implicit return
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}
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}
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bool terminal = (lf != nullptr) && lf->is_terminal;
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if (!terminal && (bi+1 >= cast(i32)cfg->blocks.count)) {
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return true; // straight-line / conditional tail with nothing after it
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}
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return false;
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_report_undef_reg(AsmCtx *asm_ctx, AsmCfg *cfg, Entity *tmpl_entity,
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AstAsmInstruction *instr, String name, u16 bit) {
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char const *rname = asm_ctx->clobber_reg_bit_name(bit);
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String owner = {};
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char const *role = nullptr;
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auto const &decls = tmpl_entity->AsmTemplate.decls;
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for_array(i, decls) {
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auto const &ed = decls[i];
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if (ed.entity == nullptr || cfg->decl_pin_bit[i] != bit) {
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continue;
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}
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if (ed.param_group == AsmTemplateEntityDeclParamGroup_Output && ed.tie < 0) {
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owner = ed.entity->token.string;
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role = "output";
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break;
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}
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if (ed.param_group == AsmTemplateEntityDeclParamGroup_Scratch && ed.view_of < 0) {
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owner = ed.entity->token.string;
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role = "scratch";
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break;
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}
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}
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if (role != nullptr) {
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error(instr->name,
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"'%.*s' implicitly reads %%%s, which is bound to the %s parameter '%.*s', "
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"but nothing writes %%%s on all paths reaching here; write to it (e.g. into '%.*s') first",
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LIT(name), rname, role, LIT(owner), rname, LIT(owner));
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} else {
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error(instr->name,
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"'%.*s' implicitly reads %%%s, but nothing in this template produces a value for it "
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"on all paths reaching here; pin an input to %%%s, or write %%%s first",
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LIT(name), rname, rname, rname);
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}
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}
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template <typename AsmCtx>
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gb_internal void check_asm_cfg_analyse(AsmCtx *asm_ctx, AsmCfg *cfg, CheckerContext *ctx, Entity *entity) {
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GB_ASSERT(entity->kind == Entity_AsmTemplate);
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auto const &decls = entity->AsmTemplate.decls;
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bool diverging = entity->type->Proc.diverging;
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if (cfg->blocks.count == 0) {
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// With an empty body, the CFG cannot really do nothing
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if (diverging && !cfg->saw_any_instructions) {
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error(entity->token, "This asm template is declared as diverging (-> !) but its body is empty and cannot diverge");
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}
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return;
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}
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if (decls.count > 64) {
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error(entity->token, "'asm' templates cannot have more than 64 total parameter declarations, got %td", decls.count);
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return;
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}
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u16 const REG_TOP = asm_ctx->CLOBBER_REGS_NAMED;
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u64 const universe_pm = cfg->universe_pm;
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auto bit_of = [&](Entity *e) -> u64 {
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i32 *ix = map_get(&cfg->entity_to_index, e);
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return ix ? (cast(u64)1 << *ix) : cast(u64)0;
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};
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// NOTE(bill): entry seed intiailization which mirrors the linear seeding of defined_regs
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u16 seed_regs = 0;
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u64 seed_pm = 0;
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for_array(i, decls) {
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auto const &ed = decls[i];
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u16 pin_bit = cfg->decl_pin_bit[i];
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if (ed.no_init) {
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seed_pm |= bit_of(ed.entity);
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seed_regs |= pin_bit;
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}
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switch (ed.param_group) {
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case AsmTemplateEntityDeclParamGroup_Input:
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seed_pm |= bit_of(ed.entity);
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seed_regs |= pin_bit;
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break;
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case AsmTemplateEntityDeclParamGroup_Output:
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if (ed.tie >= 0) {
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seed_pm |= bit_of(ed.entity);
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}
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break;
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}
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}
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isize const n = cfg->blocks.count;
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auto in_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&in_regs, heap_allocator()));
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auto out_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&out_regs, heap_allocator()));
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auto gen_regs = slice_make<u16>(heap_allocator(), n); defer (slice_free(&gen_regs, heap_allocator()));
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auto in_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&in_pm, heap_allocator()));
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auto out_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&out_pm, heap_allocator()));
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auto gen_pm = slice_make<u64>(heap_allocator(), n); defer (slice_free(&gen_pm, heap_allocator()));
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// predecessors, restricted to reachable blocks
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auto preds = slice_make<Array<i32>>(heap_allocator(), n);
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for_array(i, preds) {
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preds[i].allocator = heap_allocator();
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}
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defer ({
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for_array(i, preds) {
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array_free(&preds[i]);
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}
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slice_free(&preds, heap_allocator());
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});
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for_array(bi, cfg->blocks) {
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AsmBlock *block = &cfg->blocks[bi];
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if (!block->reachable) {
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continue;
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}
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for (i32 s : block->succs) {
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if (0 <= s && s < cast(i32)n &&
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cfg->blocks[s].reachable) {
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array_add(&preds[s], cast(i32)bi);
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}
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}
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}
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for_array(bi, cfg->blocks) {
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u16 gr = 0;
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u64 gp = 0;
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AsmBlock const &b = cfg->blocks[bi];
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for (i32 ii = b.first; ii <= b.last; ii++) {
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AsmInstructionFacts *f = map_get(&cfg->instruction_facts, cfg->insts[ii]);
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if (f == nullptr) {
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continue;
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}
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gr |= f->gen_regs;
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for (Entity *pe : f->gen_params) {
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gp |= bit_of(pe);
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}
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}
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gen_regs[bi] = gr;
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gen_pm[bi] = gp;
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}
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// NOTE(bill): initialize the blocks
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// entry is from the seeds and every other reachable block from TOP (intersection)
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for_array(bi, cfg->blocks) {
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if (!cfg->blocks[bi].reachable) {
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continue;
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}
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if (bi == 0) {
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in_regs[bi] = seed_regs;
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in_pm[bi] = seed_pm;
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} else {
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in_regs[bi] = REG_TOP;
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in_pm[bi] = universe_pm;
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}
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out_regs[bi] = in_regs[bi] | gen_regs[bi];
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out_pm[bi] = in_pm[bi] | gen_pm[bi];
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}
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// forward must-analysis: in = AND(preds.out); out = in | gen. Iterate to fixpoint.
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bool changed = true;
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while (changed) {
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changed = false;
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for_array(bi, cfg->blocks) {
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if (!cfg->blocks[bi].reachable) {
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continue;
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}
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u16 nin_r = seed_regs;
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u64 nin_p = seed_pm;
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if (bi != 0) {
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nin_r = REG_TOP;
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nin_p = universe_pm;
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for (i32 p : preds[bi]) {
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nin_r &= out_regs[p];
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nin_p &= out_pm[p];
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}
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}
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u16 nout_r = nin_r | gen_regs[bi];
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u64 nout_p = nin_p | gen_pm[bi];
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if (nin_r != in_regs[bi] ||
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nin_p != in_pm[bi] ||
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nout_r != out_regs[bi] ||
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nout_p != out_pm[bi]) {
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in_regs[bi] = nin_r;
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in_pm[bi] = nin_p;
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out_regs[bi] = nout_r;
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out_pm[bi] = nout_p;
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changed = true;
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}
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}
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}
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// NOTE(bill): publish the register masks and materialise the parameter sets onto the blocks
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for_array(bi, cfg->blocks) {
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AsmBlock *b = &cfg->blocks[bi];
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b->in_defs = in_regs[bi];
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b->out_defs = out_regs[bi];
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if (!b->reachable) {
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continue;
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}
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for_array(i, decls) {
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Entity *e = decls[i].entity;
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if (e == nullptr) {
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continue;
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}
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if (((in_pm[bi] >> i) & 1) != 0) {
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ptr_set_add(&b->in_params, e);
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}
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if (((out_pm[bi] >> i) & 1) != 0) {
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ptr_set_add(&b->out_params, e);
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}
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}
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}
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// NOTE(bill): unreachable code
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for (AsmBlock &block : cfg->blocks) {
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if (block.reachable) {
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continue;
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}
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AstAsmInstruction *first = cfg->insts[block.first];
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if (block.first == block.last) {
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warning(first->name, "The asm instruction is unreachable within this block");
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} else {
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warning(first->name, "The asm instructions are unreachable within this block");
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}
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}
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{ // NOTE(bill): read-before-write, definite-assignment across the whole CFG
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PtrSet<Entity *> reported_params = {};
|
|
defer (ptr_set_destroy(&reported_params));
|
|
|
|
u16 reported_regs = 0;
|
|
|
|
for_array(bi, cfg->blocks) {
|
|
AsmBlock const &b = cfg->blocks[bi];
|
|
if (!b.reachable) {
|
|
continue;
|
|
}
|
|
|
|
u16 run_regs = in_regs[bi];
|
|
u64 run_pm = in_pm[bi];
|
|
|
|
for (i32 ii = b.first; ii <= b.last; ii++) {
|
|
AstAsmInstruction *instr = cfg->insts[ii];
|
|
AsmInstructionFacts *f = map_get(&cfg->instruction_facts, instr);
|
|
if (f == nullptr) {
|
|
continue;
|
|
}
|
|
|
|
u16 undef = f->read_regs & REG_TOP & ~run_regs & ~reported_regs;
|
|
for (u16 bit = 1; bit != 0; bit <<= 1) {
|
|
if ((undef & bit) == 0) {
|
|
continue;
|
|
}
|
|
check_asm_cfg_report_undef_reg(asm_ctx, cfg, entity, instr, f->name, bit);
|
|
reported_regs |= bit;
|
|
}
|
|
|
|
for (Entity *pe : f->read_params) {
|
|
i32 *ix = map_get(&cfg->entity_to_index, pe);
|
|
if (ix == nullptr) {
|
|
continue;
|
|
}
|
|
if (((run_pm >> *ix) & 1) == 0 && !ptr_set_exists(&reported_params, pe)) {
|
|
Ast *loc = instr->name;
|
|
for (Ast *op : instr->operands) {
|
|
if (entity_of_node(op) == pe) { loc = op; break; }
|
|
}
|
|
error(loc, "'%.*s' reads '%.*s' before it is assigned; its initial value is undefined", LIT(f->name), LIT(pe->token.string));
|
|
ptr_set_add(&reported_params, pe);
|
|
}
|
|
}
|
|
|
|
run_regs |= f->gen_regs;
|
|
for (Entity *pe : f->gen_params) {
|
|
run_pm |= bit_of(pe);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
{ // NOTE(bill): Collect the template's return points reachable blocks that leave via the end
|
|
u16 exit_regs = REG_TOP;
|
|
u64 exit_pm = universe_pm;
|
|
bool any_exit = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (!cfg->blocks[bi].reachable) {
|
|
continue;
|
|
}
|
|
if (!check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
continue;
|
|
}
|
|
any_exit = true;
|
|
exit_regs &= out_regs[bi];
|
|
exit_pm &= out_pm[bi];
|
|
}
|
|
|
|
// NOTE(bill): Outputs must be assigned on every path that returns
|
|
if (any_exit && !diverging) {
|
|
for_array(i, decls) {
|
|
auto const &ed = decls[i];
|
|
if (ed.param_group != AsmTemplateEntityDeclParamGroup_Output) {
|
|
continue;
|
|
}
|
|
if (ed.tie >= 0 || ed.no_init) {
|
|
continue;
|
|
}
|
|
|
|
bool written = false;
|
|
u16 bit = cfg->decl_pin_bit[i];
|
|
if (bit != 0) {
|
|
written = (exit_regs & bit) != 0;
|
|
} else {
|
|
written = (exit_pm & bit_of(ed.entity)) != 0;
|
|
}
|
|
if (!written) {
|
|
error(ed.entity->token,
|
|
"'asm' output parameter '%.*s' is not assigned on all paths through this template; "
|
|
"its value is undefined",
|
|
LIT(ed.entity->token.string));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (diverging) { // No reachable path may return / fall off the end
|
|
bool any_leak = false;
|
|
for_array(bi, cfg->blocks) {
|
|
if (cfg->blocks[bi].reachable && check_asm_cfg_block_leaves(cfg, cast(i32)bi)) {
|
|
any_leak = true;
|
|
break;
|
|
}
|
|
}
|
|
if (any_leak) {
|
|
error(entity->token,
|
|
"This asm template is declared diverging (-> !) but a reachable path can fall through the end; "
|
|
"end every path with an unconditional jump, return, or halt");
|
|
}
|
|
}
|
|
} |