mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 16:42:33 +00:00
561 lines
14 KiB
Odin
561 lines
14 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
|
|
// Ginger Bill (gingerBill@github)
|
|
|
|
package rexcode_wasm
|
|
|
|
// =============================================================================
|
|
// WebAssembly DECODE DISPATCH TABLES
|
|
// =============================================================================
|
|
//
|
|
// Reverse maps from wire opcode to Mnemonic. Dispatch is two-level:
|
|
//
|
|
// * core opcodes (prefix 0x00): DECODE_MAIN[opcode_byte]
|
|
// * 0xFC misc group: DECODE_MISC[sub_opcode]
|
|
//
|
|
// These mirror ENCODING_TABLE (the single source of truth) entry-for-entry;
|
|
// unlisted slots default to .INVALID. Four dispatch arrays cover the four
|
|
// opcode spaces: core (DECODE_MAIN), 0xFC misc (DECODE_MISC), 0xFD SIMD
|
|
// (DECODE_SIMD), and 0xFE threads/atomics (DECODE_ATOMIC).
|
|
|
|
DECODE_MAIN_COUNT :: 256 // (0..=0xD2)
|
|
DECODE_MISC_COUNT :: 32 // 0xFC sub-opcodes (0..=17)
|
|
DECODE_SIMD_COUNT :: 0x114 // 0xFD sub-opcodes (0..=0x113)
|
|
DECODE_ATOMIC_COUNT :: 0x4F // 0xFE sub-opcodes (0..=0x4E)
|
|
|
|
@(rodata)
|
|
DECODE_MAIN := [DECODE_MAIN_COUNT]Mnemonic{
|
|
0x00 = .UNREACHABLE,
|
|
0x01 = .NOP,
|
|
0x02 = .BLOCK,
|
|
0x03 = .LOOP,
|
|
0x04 = .IF,
|
|
0x05 = .ELSE,
|
|
0x0B = .END,
|
|
0x0C = .BR,
|
|
0x0D = .BR_IF,
|
|
0x0E = .BR_TABLE,
|
|
0x0F = .RETURN,
|
|
0x10 = .CALL,
|
|
0x11 = .CALL_INDIRECT,
|
|
0x1A = .DROP,
|
|
0x1B = .SELECT,
|
|
0x20 = .LOCAL_GET,
|
|
0x21 = .LOCAL_SET,
|
|
0x22 = .LOCAL_TEE,
|
|
0x23 = .GLOBAL_GET,
|
|
0x24 = .GLOBAL_SET,
|
|
0x28 = .I32_LOAD,
|
|
0x29 = .I64_LOAD,
|
|
0x2A = .F32_LOAD,
|
|
0x2B = .F64_LOAD,
|
|
0x2C = .I32_LOAD8_S,
|
|
0x2D = .I32_LOAD8_U,
|
|
0x2E = .I32_LOAD16_S,
|
|
0x2F = .I32_LOAD16_U,
|
|
0x30 = .I64_LOAD8_S,
|
|
0x31 = .I64_LOAD8_U,
|
|
0x32 = .I64_LOAD16_S,
|
|
0x33 = .I64_LOAD16_U,
|
|
0x34 = .I64_LOAD32_S,
|
|
0x35 = .I64_LOAD32_U,
|
|
0x36 = .I32_STORE,
|
|
0x37 = .I64_STORE,
|
|
0x38 = .F32_STORE,
|
|
0x39 = .F64_STORE,
|
|
0x3A = .I32_STORE8,
|
|
0x3B = .I32_STORE16,
|
|
0x3C = .I64_STORE8,
|
|
0x3D = .I64_STORE16,
|
|
0x3E = .I64_STORE32,
|
|
0x3F = .MEMORY_SIZE,
|
|
0x40 = .MEMORY_GROW,
|
|
0x41 = .I32_CONST,
|
|
0x42 = .I64_CONST,
|
|
0x43 = .F32_CONST,
|
|
0x44 = .F64_CONST,
|
|
0x45 = .I32_EQZ,
|
|
0x46 = .I32_EQ,
|
|
0x47 = .I32_NE,
|
|
0x48 = .I32_LT_S,
|
|
0x49 = .I32_LT_U,
|
|
0x4A = .I32_GT_S,
|
|
0x4B = .I32_GT_U,
|
|
0x4C = .I32_LE_S,
|
|
0x4D = .I32_LE_U,
|
|
0x4E = .I32_GE_S,
|
|
0x4F = .I32_GE_U,
|
|
0x50 = .I64_EQZ,
|
|
0x51 = .I64_EQ,
|
|
0x52 = .I64_NE,
|
|
0x53 = .I64_LT_S,
|
|
0x54 = .I64_LT_U,
|
|
0x55 = .I64_GT_S,
|
|
0x56 = .I64_GT_U,
|
|
0x57 = .I64_LE_S,
|
|
0x58 = .I64_LE_U,
|
|
0x59 = .I64_GE_S,
|
|
0x5A = .I64_GE_U,
|
|
0x5B = .F32_EQ,
|
|
0x5C = .F32_NE,
|
|
0x5D = .F32_LT,
|
|
0x5E = .F32_GT,
|
|
0x5F = .F32_LE,
|
|
0x60 = .F32_GE,
|
|
0x61 = .F64_EQ,
|
|
0x62 = .F64_NE,
|
|
0x63 = .F64_LT,
|
|
0x64 = .F64_GT,
|
|
0x65 = .F64_LE,
|
|
0x66 = .F64_GE,
|
|
0x67 = .I32_CLZ,
|
|
0x68 = .I32_CTZ,
|
|
0x69 = .I32_POPCNT,
|
|
0x6A = .I32_ADD,
|
|
0x6B = .I32_SUB,
|
|
0x6C = .I32_MUL,
|
|
0x6D = .I32_DIV_S,
|
|
0x6E = .I32_DIV_U,
|
|
0x6F = .I32_REM_S,
|
|
0x70 = .I32_REM_U,
|
|
0x71 = .I32_AND,
|
|
0x72 = .I32_OR,
|
|
0x73 = .I32_XOR,
|
|
0x74 = .I32_SHL,
|
|
0x75 = .I32_SHR_S,
|
|
0x76 = .I32_SHR_U,
|
|
0x77 = .I32_ROTL,
|
|
0x78 = .I32_ROTR,
|
|
0x79 = .I64_CLZ,
|
|
0x7A = .I64_CTZ,
|
|
0x7B = .I64_POPCNT,
|
|
0x7C = .I64_ADD,
|
|
0x7D = .I64_SUB,
|
|
0x7E = .I64_MUL,
|
|
0x7F = .I64_DIV_S,
|
|
0x80 = .I64_DIV_U,
|
|
0x81 = .I64_REM_S,
|
|
0x82 = .I64_REM_U,
|
|
0x83 = .I64_AND,
|
|
0x84 = .I64_OR,
|
|
0x85 = .I64_XOR,
|
|
0x86 = .I64_SHL,
|
|
0x87 = .I64_SHR_S,
|
|
0x88 = .I64_SHR_U,
|
|
0x89 = .I64_ROTL,
|
|
0x8A = .I64_ROTR,
|
|
0x8B = .F32_ABS,
|
|
0x8C = .F32_NEG,
|
|
0x8D = .F32_CEIL,
|
|
0x8E = .F32_FLOOR,
|
|
0x8F = .F32_TRUNC,
|
|
0x90 = .F32_NEAREST,
|
|
0x91 = .F32_SQRT,
|
|
0x92 = .F32_ADD,
|
|
0x93 = .F32_SUB,
|
|
0x94 = .F32_MUL,
|
|
0x95 = .F32_DIV,
|
|
0x96 = .F32_MIN,
|
|
0x97 = .F32_MAX,
|
|
0x98 = .F32_COPYSIGN,
|
|
0x99 = .F64_ABS,
|
|
0x9A = .F64_NEG,
|
|
0x9B = .F64_CEIL,
|
|
0x9C = .F64_FLOOR,
|
|
0x9D = .F64_TRUNC,
|
|
0x9E = .F64_NEAREST,
|
|
0x9F = .F64_SQRT,
|
|
0xA0 = .F64_ADD,
|
|
0xA1 = .F64_SUB,
|
|
0xA2 = .F64_MUL,
|
|
0xA3 = .F64_DIV,
|
|
0xA4 = .F64_MIN,
|
|
0xA5 = .F64_MAX,
|
|
0xA6 = .F64_COPYSIGN,
|
|
0xA7 = .I32_WRAP_I64,
|
|
0xA8 = .I32_TRUNC_F32_S,
|
|
0xA9 = .I32_TRUNC_F32_U,
|
|
0xAA = .I32_TRUNC_F64_S,
|
|
0xAB = .I32_TRUNC_F64_U,
|
|
0xAC = .I64_EXTEND_I32_S,
|
|
0xAD = .I64_EXTEND_I32_U,
|
|
0xAE = .I64_TRUNC_F32_S,
|
|
0xAF = .I64_TRUNC_F32_U,
|
|
0xB0 = .I64_TRUNC_F64_S,
|
|
0xB1 = .I64_TRUNC_F64_U,
|
|
0xB2 = .F32_CONVERT_I32_S,
|
|
0xB3 = .F32_CONVERT_I32_U,
|
|
0xB4 = .F32_CONVERT_I64_S,
|
|
0xB5 = .F32_CONVERT_I64_U,
|
|
0xB6 = .F32_DEMOTE_F64,
|
|
0xB7 = .F64_CONVERT_I32_S,
|
|
0xB8 = .F64_CONVERT_I32_U,
|
|
0xB9 = .F64_CONVERT_I64_S,
|
|
0xBA = .F64_CONVERT_I64_U,
|
|
0xBB = .F64_PROMOTE_F32,
|
|
0xBC = .I32_REINTERPRET_F32,
|
|
0xBD = .I64_REINTERPRET_F64,
|
|
0xBE = .F32_REINTERPRET_I32,
|
|
0xBF = .F64_REINTERPRET_I64,
|
|
0xC0 = .I32_EXTEND8_S,
|
|
0xC1 = .I32_EXTEND16_S,
|
|
0xC2 = .I64_EXTEND8_S,
|
|
0xC3 = .I64_EXTEND16_S,
|
|
0xC4 = .I64_EXTEND32_S,
|
|
0xD0 = .REF_NULL,
|
|
0xD1 = .REF_IS_NULL,
|
|
0xD2 = .REF_FUNC,
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_MISC := [DECODE_MISC_COUNT]Mnemonic{
|
|
0 = .I32_TRUNC_SAT_F32_S,
|
|
1 = .I32_TRUNC_SAT_F32_U,
|
|
2 = .I32_TRUNC_SAT_F64_S,
|
|
3 = .I32_TRUNC_SAT_F64_U,
|
|
4 = .I64_TRUNC_SAT_F32_S,
|
|
5 = .I64_TRUNC_SAT_F32_U,
|
|
6 = .I64_TRUNC_SAT_F64_S,
|
|
7 = .I64_TRUNC_SAT_F64_U,
|
|
8 = .MEMORY_INIT,
|
|
9 = .DATA_DROP,
|
|
10 = .MEMORY_COPY,
|
|
11 = .MEMORY_FILL,
|
|
12 = .TABLE_INIT,
|
|
13 = .ELEM_DROP,
|
|
14 = .TABLE_COPY,
|
|
15 = .TABLE_GROW,
|
|
16 = .TABLE_SIZE,
|
|
17 = .TABLE_FILL,
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_SIMD := [DECODE_SIMD_COUNT]Mnemonic{
|
|
0x00 = .V128_LOAD,
|
|
0x01 = .V128_LOAD8X8_S,
|
|
0x02 = .V128_LOAD8X8_U,
|
|
0x03 = .V128_LOAD16X4_S,
|
|
0x04 = .V128_LOAD16X4_U,
|
|
0x05 = .V128_LOAD32X2_S,
|
|
0x06 = .V128_LOAD32X2_U,
|
|
0x07 = .V128_LOAD8_SPLAT,
|
|
0x08 = .V128_LOAD16_SPLAT,
|
|
0x09 = .V128_LOAD32_SPLAT,
|
|
0x0A = .V128_LOAD64_SPLAT,
|
|
0x0B = .V128_STORE,
|
|
0x0C = .V128_CONST,
|
|
0x0D = .I8X16_SHUFFLE,
|
|
0x0E = .I8X16_SWIZZLE,
|
|
0x0F = .I8X16_SPLAT,
|
|
0x10 = .I16X8_SPLAT,
|
|
0x11 = .I32X4_SPLAT,
|
|
0x12 = .I64X2_SPLAT,
|
|
0x13 = .F32X4_SPLAT,
|
|
0x14 = .F64X2_SPLAT,
|
|
0x15 = .I8X16_EXTRACT_LANE_S,
|
|
0x16 = .I8X16_EXTRACT_LANE_U,
|
|
0x17 = .I8X16_REPLACE_LANE,
|
|
0x18 = .I16X8_EXTRACT_LANE_S,
|
|
0x19 = .I16X8_EXTRACT_LANE_U,
|
|
0x1A = .I16X8_REPLACE_LANE,
|
|
0x1B = .I32X4_EXTRACT_LANE,
|
|
0x1C = .I32X4_REPLACE_LANE,
|
|
0x1D = .I64X2_EXTRACT_LANE,
|
|
0x1E = .I64X2_REPLACE_LANE,
|
|
0x1F = .F32X4_EXTRACT_LANE,
|
|
0x20 = .F32X4_REPLACE_LANE,
|
|
0x21 = .F64X2_EXTRACT_LANE,
|
|
0x22 = .F64X2_REPLACE_LANE,
|
|
0x23 = .I8X16_EQ,
|
|
0x24 = .I8X16_NE,
|
|
0x25 = .I8X16_LT_S,
|
|
0x26 = .I8X16_LT_U,
|
|
0x27 = .I8X16_GT_S,
|
|
0x28 = .I8X16_GT_U,
|
|
0x29 = .I8X16_LE_S,
|
|
0x2A = .I8X16_LE_U,
|
|
0x2B = .I8X16_GE_S,
|
|
0x2C = .I8X16_GE_U,
|
|
0x2D = .I16X8_EQ,
|
|
0x2E = .I16X8_NE,
|
|
0x2F = .I16X8_LT_S,
|
|
0x30 = .I16X8_LT_U,
|
|
0x31 = .I16X8_GT_S,
|
|
0x32 = .I16X8_GT_U,
|
|
0x33 = .I16X8_LE_S,
|
|
0x34 = .I16X8_LE_U,
|
|
0x35 = .I16X8_GE_S,
|
|
0x36 = .I16X8_GE_U,
|
|
0x37 = .I32X4_EQ,
|
|
0x38 = .I32X4_NE,
|
|
0x39 = .I32X4_LT_S,
|
|
0x3A = .I32X4_LT_U,
|
|
0x3B = .I32X4_GT_S,
|
|
0x3C = .I32X4_GT_U,
|
|
0x3D = .I32X4_LE_S,
|
|
0x3E = .I32X4_LE_U,
|
|
0x3F = .I32X4_GE_S,
|
|
0x40 = .I32X4_GE_U,
|
|
0x41 = .F32X4_EQ,
|
|
0x42 = .F32X4_NE,
|
|
0x43 = .F32X4_LT,
|
|
0x44 = .F32X4_GT,
|
|
0x45 = .F32X4_LE,
|
|
0x46 = .F32X4_GE,
|
|
0x47 = .F64X2_EQ,
|
|
0x48 = .F64X2_NE,
|
|
0x49 = .F64X2_LT,
|
|
0x4A = .F64X2_GT,
|
|
0x4B = .F64X2_LE,
|
|
0x4C = .F64X2_GE,
|
|
0x4D = .V128_NOT,
|
|
0x4E = .V128_AND,
|
|
0x4F = .V128_ANDNOT,
|
|
0x50 = .V128_OR,
|
|
0x51 = .V128_XOR,
|
|
0x52 = .V128_BITSELECT,
|
|
0x53 = .V128_ANY_TRUE,
|
|
0x54 = .V128_LOAD8_LANE,
|
|
0x55 = .V128_LOAD16_LANE,
|
|
0x56 = .V128_LOAD32_LANE,
|
|
0x57 = .V128_LOAD64_LANE,
|
|
0x58 = .V128_STORE8_LANE,
|
|
0x59 = .V128_STORE16_LANE,
|
|
0x5A = .V128_STORE32_LANE,
|
|
0x5B = .V128_STORE64_LANE,
|
|
0x5C = .V128_LOAD32_ZERO,
|
|
0x5D = .V128_LOAD64_ZERO,
|
|
0x5E = .F32X4_DEMOTE_F64X2_ZERO,
|
|
0x5F = .F64X2_PROMOTE_LOW_F32X4,
|
|
0x60 = .I8X16_ABS,
|
|
0x61 = .I8X16_NEG,
|
|
0x62 = .I8X16_POPCNT,
|
|
0x63 = .I8X16_ALL_TRUE,
|
|
0x64 = .I8X16_BITMASK,
|
|
0x65 = .I8X16_NARROW_I16X8_S,
|
|
0x66 = .I8X16_NARROW_I16X8_U,
|
|
0x67 = .F32X4_CEIL,
|
|
0x68 = .F32X4_FLOOR,
|
|
0x69 = .F32X4_TRUNC,
|
|
0x6A = .F32X4_NEAREST,
|
|
0x6B = .I8X16_SHL,
|
|
0x6C = .I8X16_SHR_S,
|
|
0x6D = .I8X16_SHR_U,
|
|
0x6E = .I8X16_ADD,
|
|
0x6F = .I8X16_ADD_SAT_S,
|
|
0x70 = .I8X16_ADD_SAT_U,
|
|
0x71 = .I8X16_SUB,
|
|
0x72 = .I8X16_SUB_SAT_S,
|
|
0x73 = .I8X16_SUB_SAT_U,
|
|
0x74 = .F64X2_CEIL,
|
|
0x75 = .F64X2_FLOOR,
|
|
0x76 = .I8X16_MIN_S,
|
|
0x77 = .I8X16_MIN_U,
|
|
0x78 = .I8X16_MAX_S,
|
|
0x79 = .I8X16_MAX_U,
|
|
0x7A = .F64X2_TRUNC,
|
|
0x7B = .I8X16_AVGR_U,
|
|
0x7C = .I16X8_EXTADD_PAIRWISE_I8X16_S,
|
|
0x7D = .I16X8_EXTADD_PAIRWISE_I8X16_U,
|
|
0x7E = .I32X4_EXTADD_PAIRWISE_I16X8_S,
|
|
0x7F = .I32X4_EXTADD_PAIRWISE_I16X8_U,
|
|
0x80 = .I16X8_ABS,
|
|
0x81 = .I16X8_NEG,
|
|
0x82 = .I16X8_Q15MULR_SAT_S,
|
|
0x83 = .I16X8_ALL_TRUE,
|
|
0x84 = .I16X8_BITMASK,
|
|
0x85 = .I16X8_NARROW_I32X4_S,
|
|
0x86 = .I16X8_NARROW_I32X4_U,
|
|
0x87 = .I16X8_EXTEND_LOW_I8X16_S,
|
|
0x88 = .I16X8_EXTEND_HIGH_I8X16_S,
|
|
0x89 = .I16X8_EXTEND_LOW_I8X16_U,
|
|
0x8A = .I16X8_EXTEND_HIGH_I8X16_U,
|
|
0x8B = .I16X8_SHL,
|
|
0x8C = .I16X8_SHR_S,
|
|
0x8D = .I16X8_SHR_U,
|
|
0x8E = .I16X8_ADD,
|
|
0x8F = .I16X8_ADD_SAT_S,
|
|
0x90 = .I16X8_ADD_SAT_U,
|
|
0x91 = .I16X8_SUB,
|
|
0x92 = .I16X8_SUB_SAT_S,
|
|
0x93 = .I16X8_SUB_SAT_U,
|
|
0x94 = .F64X2_NEAREST,
|
|
0x95 = .I16X8_MUL,
|
|
0x96 = .I16X8_MIN_S,
|
|
0x97 = .I16X8_MIN_U,
|
|
0x98 = .I16X8_MAX_S,
|
|
0x99 = .I16X8_MAX_U,
|
|
0x9B = .I16X8_AVGR_U,
|
|
0x9C = .I16X8_EXTMUL_LOW_I8X16_S,
|
|
0x9D = .I16X8_EXTMUL_HIGH_I8X16_S,
|
|
0x9E = .I16X8_EXTMUL_LOW_I8X16_U,
|
|
0x9F = .I16X8_EXTMUL_HIGH_I8X16_U,
|
|
0xA0 = .I32X4_ABS,
|
|
0xA1 = .I32X4_NEG,
|
|
0xA3 = .I32X4_ALL_TRUE,
|
|
0xA4 = .I32X4_BITMASK,
|
|
0xA7 = .I32X4_EXTEND_LOW_I16X8_S,
|
|
0xA8 = .I32X4_EXTEND_HIGH_I16X8_S,
|
|
0xA9 = .I32X4_EXTEND_LOW_I16X8_U,
|
|
0xAA = .I32X4_EXTEND_HIGH_I16X8_U,
|
|
0xAB = .I32X4_SHL,
|
|
0xAC = .I32X4_SHR_S,
|
|
0xAD = .I32X4_SHR_U,
|
|
0xAE = .I32X4_ADD,
|
|
0xB1 = .I32X4_SUB,
|
|
0xB5 = .I32X4_MUL,
|
|
0xB6 = .I32X4_MIN_S,
|
|
0xB7 = .I32X4_MIN_U,
|
|
0xB8 = .I32X4_MAX_S,
|
|
0xB9 = .I32X4_MAX_U,
|
|
0xBA = .I32X4_DOT_I16X8_S,
|
|
0xBC = .I32X4_EXTMUL_LOW_I16X8_S,
|
|
0xBD = .I32X4_EXTMUL_HIGH_I16X8_S,
|
|
0xBE = .I32X4_EXTMUL_LOW_I16X8_U,
|
|
0xBF = .I32X4_EXTMUL_HIGH_I16X8_U,
|
|
0xC0 = .I64X2_ABS,
|
|
0xC1 = .I64X2_NEG,
|
|
0xC3 = .I64X2_ALL_TRUE,
|
|
0xC4 = .I64X2_BITMASK,
|
|
0xC7 = .I64X2_EXTEND_LOW_I32X4_S,
|
|
0xC8 = .I64X2_EXTEND_HIGH_I32X4_S,
|
|
0xC9 = .I64X2_EXTEND_LOW_I32X4_U,
|
|
0xCA = .I64X2_EXTEND_HIGH_I32X4_U,
|
|
0xCB = .I64X2_SHL,
|
|
0xCC = .I64X2_SHR_S,
|
|
0xCD = .I64X2_SHR_U,
|
|
0xCE = .I64X2_ADD,
|
|
0xD1 = .I64X2_SUB,
|
|
0xD5 = .I64X2_MUL,
|
|
0xD6 = .I64X2_EQ,
|
|
0xD7 = .I64X2_NE,
|
|
0xD8 = .I64X2_LT_S,
|
|
0xD9 = .I64X2_GT_S,
|
|
0xDA = .I64X2_LE_S,
|
|
0xDB = .I64X2_GE_S,
|
|
0xDC = .I64X2_EXTMUL_LOW_I32X4_S,
|
|
0xDD = .I64X2_EXTMUL_HIGH_I32X4_S,
|
|
0xDE = .I64X2_EXTMUL_LOW_I32X4_U,
|
|
0xDF = .I64X2_EXTMUL_HIGH_I32X4_U,
|
|
0xE0 = .F32X4_ABS,
|
|
0xE1 = .F32X4_NEG,
|
|
0xE3 = .F32X4_SQRT,
|
|
0xE4 = .F32X4_ADD,
|
|
0xE5 = .F32X4_SUB,
|
|
0xE6 = .F32X4_MUL,
|
|
0xE7 = .F32X4_DIV,
|
|
0xE8 = .F32X4_MIN,
|
|
0xE9 = .F32X4_MAX,
|
|
0xEA = .F32X4_PMIN,
|
|
0xEB = .F32X4_PMAX,
|
|
0xEC = .F64X2_ABS,
|
|
0xED = .F64X2_NEG,
|
|
0xEF = .F64X2_SQRT,
|
|
0xF0 = .F64X2_ADD,
|
|
0xF1 = .F64X2_SUB,
|
|
0xF2 = .F64X2_MUL,
|
|
0xF3 = .F64X2_DIV,
|
|
0xF4 = .F64X2_MIN,
|
|
0xF5 = .F64X2_MAX,
|
|
0xF6 = .F64X2_PMIN,
|
|
0xF7 = .F64X2_PMAX,
|
|
0xF8 = .I32X4_TRUNC_SAT_F32X4_S,
|
|
0xF9 = .I32X4_TRUNC_SAT_F32X4_U,
|
|
0xFA = .F32X4_CONVERT_I32X4_S,
|
|
0xFB = .F32X4_CONVERT_I32X4_U,
|
|
0xFC = .I32X4_TRUNC_SAT_F64X2_S_ZERO,
|
|
0xFD = .I32X4_TRUNC_SAT_F64X2_U_ZERO,
|
|
0xFE = .F64X2_CONVERT_LOW_I32X4_S,
|
|
0xFF = .F64X2_CONVERT_LOW_I32X4_U,
|
|
0x100 = .I8X16_RELAXED_SWIZZLE,
|
|
0x101 = .I32X4_RELAXED_TRUNC_F32X4_S,
|
|
0x102 = .I32X4_RELAXED_TRUNC_F32X4_U,
|
|
0x103 = .I32X4_RELAXED_TRUNC_F64X2_S_ZERO,
|
|
0x104 = .I32X4_RELAXED_TRUNC_F64X2_U_ZERO,
|
|
0x105 = .F32X4_RELAXED_MADD,
|
|
0x106 = .F32X4_RELAXED_NMADD,
|
|
0x107 = .F64X2_RELAXED_MADD,
|
|
0x108 = .F64X2_RELAXED_NMADD,
|
|
0x109 = .I8X16_RELAXED_LANESELECT,
|
|
0x10A = .I16X8_RELAXED_LANESELECT,
|
|
0x10B = .I32X4_RELAXED_LANESELECT,
|
|
0x10C = .I64X2_RELAXED_LANESELECT,
|
|
0x10D = .F32X4_RELAXED_MIN,
|
|
0x10E = .F32X4_RELAXED_MAX,
|
|
0x10F = .F64X2_RELAXED_MIN,
|
|
0x110 = .F64X2_RELAXED_MAX,
|
|
0x111 = .I16X8_RELAXED_Q15MULR_S,
|
|
0x112 = .I16X8_RELAXED_DOT_I8X16_I7X16_S,
|
|
0x113 = .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S,
|
|
}
|
|
|
|
@(rodata)
|
|
DECODE_ATOMIC := [DECODE_ATOMIC_COUNT]Mnemonic{
|
|
0x00 = .MEMORY_ATOMIC_NOTIFY,
|
|
0x01 = .MEMORY_ATOMIC_WAIT32,
|
|
0x02 = .MEMORY_ATOMIC_WAIT64,
|
|
0x03 = .ATOMIC_FENCE,
|
|
0x10 = .I32_ATOMIC_LOAD,
|
|
0x11 = .I64_ATOMIC_LOAD,
|
|
0x12 = .I32_ATOMIC_LOAD8_U,
|
|
0x13 = .I32_ATOMIC_LOAD16_U,
|
|
0x14 = .I64_ATOMIC_LOAD8_U,
|
|
0x15 = .I64_ATOMIC_LOAD16_U,
|
|
0x16 = .I64_ATOMIC_LOAD32_U,
|
|
0x17 = .I32_ATOMIC_STORE,
|
|
0x18 = .I64_ATOMIC_STORE,
|
|
0x19 = .I32_ATOMIC_STORE8,
|
|
0x1A = .I32_ATOMIC_STORE16,
|
|
0x1B = .I64_ATOMIC_STORE8,
|
|
0x1C = .I64_ATOMIC_STORE16,
|
|
0x1D = .I64_ATOMIC_STORE32,
|
|
0x1E = .I32_ATOMIC_RMW_ADD,
|
|
0x1F = .I64_ATOMIC_RMW_ADD,
|
|
0x20 = .I32_ATOMIC_RMW8_ADD_U,
|
|
0x21 = .I32_ATOMIC_RMW16_ADD_U,
|
|
0x22 = .I64_ATOMIC_RMW8_ADD_U,
|
|
0x23 = .I64_ATOMIC_RMW16_ADD_U,
|
|
0x24 = .I64_ATOMIC_RMW32_ADD_U,
|
|
0x25 = .I32_ATOMIC_RMW_SUB,
|
|
0x26 = .I64_ATOMIC_RMW_SUB,
|
|
0x27 = .I32_ATOMIC_RMW8_SUB_U,
|
|
0x28 = .I32_ATOMIC_RMW16_SUB_U,
|
|
0x29 = .I64_ATOMIC_RMW8_SUB_U,
|
|
0x2A = .I64_ATOMIC_RMW16_SUB_U,
|
|
0x2B = .I64_ATOMIC_RMW32_SUB_U,
|
|
0x2C = .I32_ATOMIC_RMW_AND,
|
|
0x2D = .I64_ATOMIC_RMW_AND,
|
|
0x2E = .I32_ATOMIC_RMW8_AND_U,
|
|
0x2F = .I32_ATOMIC_RMW16_AND_U,
|
|
0x30 = .I64_ATOMIC_RMW8_AND_U,
|
|
0x31 = .I64_ATOMIC_RMW16_AND_U,
|
|
0x32 = .I64_ATOMIC_RMW32_AND_U,
|
|
0x33 = .I32_ATOMIC_RMW_OR,
|
|
0x34 = .I64_ATOMIC_RMW_OR,
|
|
0x35 = .I32_ATOMIC_RMW8_OR_U,
|
|
0x36 = .I32_ATOMIC_RMW16_OR_U,
|
|
0x37 = .I64_ATOMIC_RMW8_OR_U,
|
|
0x38 = .I64_ATOMIC_RMW16_OR_U,
|
|
0x39 = .I64_ATOMIC_RMW32_OR_U,
|
|
0x3A = .I32_ATOMIC_RMW_XOR,
|
|
0x3B = .I64_ATOMIC_RMW_XOR,
|
|
0x3C = .I32_ATOMIC_RMW8_XOR_U,
|
|
0x3D = .I32_ATOMIC_RMW16_XOR_U,
|
|
0x3E = .I64_ATOMIC_RMW8_XOR_U,
|
|
0x3F = .I64_ATOMIC_RMW16_XOR_U,
|
|
0x40 = .I64_ATOMIC_RMW32_XOR_U,
|
|
0x41 = .I32_ATOMIC_RMW_XCHG,
|
|
0x42 = .I64_ATOMIC_RMW_XCHG,
|
|
0x43 = .I32_ATOMIC_RMW8_XCHG_U,
|
|
0x44 = .I32_ATOMIC_RMW16_XCHG_U,
|
|
0x45 = .I64_ATOMIC_RMW8_XCHG_U,
|
|
0x46 = .I64_ATOMIC_RMW16_XCHG_U,
|
|
0x47 = .I64_ATOMIC_RMW32_XCHG_U,
|
|
0x48 = .I32_ATOMIC_RMW_CMPXCHG,
|
|
0x49 = .I64_ATOMIC_RMW_CMPXCHG,
|
|
0x4A = .I32_ATOMIC_RMW8_CMPXCHG_U,
|
|
0x4B = .I32_ATOMIC_RMW16_CMPXCHG_U,
|
|
0x4C = .I64_ATOMIC_RMW8_CMPXCHG_U,
|
|
0x4D = .I64_ATOMIC_RMW16_CMPXCHG_U,
|
|
0x4E = .I64_ATOMIC_RMW32_CMPXCHG_U,
|
|
}
|