mirror of
https://github.com/odin-lang/Odin.git
synced 2026-09-05 11:50:44 +00:00
4406ce69db
B_COND was a straight contradiction of the rule the rest of the enum follows.
No assembler has a mnemonic called `b.cond`; it has `b.eq`, `b.le`, `b.ne` and
thirteen more, and x86 in this same library already models exactly this shape
the right way -- JE, JNE, JG, JLE are sixteen separate mnemonics with the
condition in the opcode.
Two things were wrong with folding it into an operand.
The condition is not an operand. It is four bits of the opcode, no different
from x86 putting Jcc's condition in the low nibble of 0x7_. Modelling it as
one has to be papered over everywhere: the printer special-cased B_COND to
rebuild `b.eq` out of operand 0, sbprint had to skip that operand so it did
not print twice, and the public mnemonic_to_string -- which has no instruction
to read the operand from -- returned "b_cond", a string no assembler takes.
All three of those are now gone; the name prints itself.
More importantly it destroyed the flag data. x86 records per condition which
status bits it consults: JE reads {ZF}, JLE reads {ZF, SF, OF}. One B_COND
entry could not say that, so it claimed nzcv_rd = {N, Z, C, V} -- all four
flags, for every condition. Every entry was wrong. Split apart they carry what
they actually read:
b.eq/b.ne Z b.hi/b.ls Z, C
b.cs/b.cc C b.ge/b.lt N, V
b.mi/b.pl N b.gt/b.le N, Z, V
b.vs/b.vc V b.al/b.nv none
which is the data the compiler's asm checker reads for flag liveness, now that
arm64 feeds it.
The mask also covers the condition field for the first time (0xFF000010 ->
0xFF00001F): with the condition in an operand, four opcode bits sat outside
the mask.
BC.cond gets the same treatment. Builders come out per condition, so `b.le` is
`inst_b_le(label)` rather than `inst_b_cond(.LE, label)`. Cond stays exactly as
it is -- CSEL, CSINC, CSINV, CSNEG, CCMP, CCMN and FCSEL take a real condition
operand, and the compiler's OP_COND handling is untouched.
All sixteen verified by disassembling our own output with llvm-mc: b.eq, b.ne,
b.hs, b.lo, b.mi, b.pl, b.vs, b.vc, b.hi, b.ls, b.ge, b.lt, b.gt, b.le, b.al,
b.nv. Rows follow the table's current column formatting. All rexcode suites
pass and the generators stay idempotent.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
600 lines
23 KiB
Odin
600 lines
23 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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// =============================================================================
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// AArch64 MNEMONICS
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// =============================================================================
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//
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// One member per ASSEMBLER mnemonic -- the name an A64 assembler actually
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// accepts, and nothing finer. An instruction's variants are not separate
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// mnemonics: ADD covers the immediate, shifted-register, extended-register
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// and NEON forms, LDR covers every addressing mode, and the encoder picks
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// between them by matching the operands against that mnemonic's run of
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// forms in INSTRUCTION_TABLE (see tablegen/instruction_table.odin).
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//
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// Names holding an underscore are the ones an assembler writes with a
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// separator: the two-token system instructions -- `dc zva`, `tlbi vae1`,
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// `at s1e1r`, `bti j`, `psb csync` -- and the conditional branches, where
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// the underscore is a dot: B_LE prints `b.le`, BC_NE prints `bc.ne`. The
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// AMX_* pseudo-ops keep theirs literally; Apple's undocumented coprocessor
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// has no assembler spelling at all.
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//
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// Architectural aliases that share an encoding (MOV/MVN of ORR/ORN, NEG of
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// SUB, CMP of SUBS, TST of ANDS, ...) are listed as the mnemonics they are:
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// each is a name assemblers accept, so each gets its own member and forms.
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Mnemonic :: enum u16 {
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INVALID = 0,
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// -------------------------------------------------------------------------
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// Data processing -- immediate
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// -------------------------------------------------------------------------
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ADD, ADDS, SUB, SUBS, // optional LSL #12 carried in shift field
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MOVZ, MOVN, MOVK, // 16-bit imm + 2-bit hw
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ADR, ADRP, // PC-relative address
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// -------------------------------------------------------------------------
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// Data processing -- register (shifted register)
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// -------------------------------------------------------------------------
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AND, ANDS, ORR, EOR,
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BIC, BICS, ORN, EON,
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// -------------------------------------------------------------------------
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// Data processing -- register (variable shifts / 2-source)
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// -------------------------------------------------------------------------
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LSL, LSR, ASR, ROR, // register and immediate forms both
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UDIV, SDIV,
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// -------------------------------------------------------------------------
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// Data processing -- register (3-source)
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// -------------------------------------------------------------------------
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MADD, MSUB, // 64x64+64 -> 64 (or 32 variant)
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SMADDL, SMSUBL, UMADDL, UMSUBL, // 32x32+64 -> 64
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SMULH, UMULH, // 64x64 -> high 64
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// -------------------------------------------------------------------------
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// Data processing -- register (1-source bit-twiddling)
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// -------------------------------------------------------------------------
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CLZ, CLS, RBIT, REV, REV16, REV32,
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// -------------------------------------------------------------------------
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// Conditional select / compare
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// -------------------------------------------------------------------------
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CSEL, CSINC, CSINV, CSNEG,
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CCMP, CCMN,
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// -------------------------------------------------------------------------
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// Extract
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// -------------------------------------------------------------------------
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EXTR,
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// -------------------------------------------------------------------------
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// Branches
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// -------------------------------------------------------------------------
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B, BL, // 26-bit PC-rel
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BR, BLR, RET, // register indirect
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// One member per condition, the way an assembler spells them and the way
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// x86 does its Jcc. The condition is not an operand: it is four bits of
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// the opcode, and splitting it lets each entry record the flags it
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// actually reads -- b.eq consults Z alone, b.le consults N, Z and V --
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// where a single B_COND had to claim all four for every condition.
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B_EQ, B_NE, B_CS, B_CC, // B.cond -- 19-bit PC-rel
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B_MI, B_PL, B_VS, B_VC,
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B_HI, B_LS, B_GE, B_LT,
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B_GT, B_LE, B_AL, B_NV,
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CBZ, CBNZ, // 19-bit PC-rel + Rt
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TBZ, TBNZ, // 14-bit PC-rel + bit position
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// -------------------------------------------------------------------------
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// Loads / stores
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// -------------------------------------------------------------------------
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// Plain (unsigned offset / signed unscaled / pre / post)
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LDR, STR, // X/W variants (matched by reg width)
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LDRB, STRB, LDRSB,
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LDRH, STRH, LDRSH,
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LDRSW,
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// Pair
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LDP, STP, LDPSW,
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// PC-relative literal
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// Acquire / release
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LDAR, STLR,
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LDARB, STLRB, LDARH, STLRH,
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// Exclusive (load-linked / store-conditional)
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LDXR, STXR, LDAXR, STLXR,
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// -------------------------------------------------------------------------
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// System
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// -------------------------------------------------------------------------
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NOP, YIELD, WFE, WFI, SEV, SEVL,
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HINT,
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MRS, MSR,
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ISB, DSB, DMB,
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SVC, HVC, SMC, BRK, HLT,
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ERET,
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// -------------------------------------------------------------------------
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// FP scalar (single / double)
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// -------------------------------------------------------------------------
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FMOV, // reg-reg / imm / between int/FP
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FABS, FNEG, FSQRT,
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FADD, FSUB, FMUL, FDIV, FNMUL,
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FMADD, FMSUB, FNMADD, FNMSUB,
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FCMP, FCMPE,
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FCSEL,
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FMAX, FMIN, FMAXNM, FMINNM,
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FCVT, // between single/double/half
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SCVTF, UCVTF,
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FCVTZS, FCVTZU,
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FCVTAS, FCVTAU,
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FCVTNS, FCVTNU,
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FCVTPS, FCVTPU,
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FCVTMS, FCVTMU,
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FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, FRINTZ,
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// -------------------------------------------------------------------------
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// Logical immediate (bitmask-encoded; N:imms:immr)
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// -------------------------------------------------------------------------
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TST, // ANDS with Rd=ZR
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// -------------------------------------------------------------------------
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// Additional load/store addressing modes
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// -------------------------------------------------------------------------
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LDUR, STUR, LDURB, STURB, LDURSB, LDURH, STURH, LDURSH, LDURSW,
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LDNP, STNP, // non-temporal pair
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LDXP, STXP, LDAXP, STLXP, // exclusive pair
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LDXRB, STXRB, LDAXRB, STLXRB, // exclusive byte
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LDXRH, STXRH, LDAXRH, STLXRH, // exclusive halfword
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LDAPR, LDAPRB, LDAPRH, // load-acquire RCpc
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// -------------------------------------------------------------------------
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// LSE atomics (8 ops x 4 acq/rel x 2 width = 64 forms, named by op only;
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// size and acq/rel encoded in the bits + flags)
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// -------------------------------------------------------------------------
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LDADD, LDADDA, LDADDL, LDADDAL,
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LDCLR, LDCLRA, LDCLRL, LDCLRAL,
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LDEOR, LDEORA, LDEORL, LDEORAL,
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LDSET, LDSETA, LDSETL, LDSETAL,
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LDSMAX, LDSMAXA, LDSMAXL, LDSMAXAL,
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LDSMIN, LDSMINA, LDSMINL, LDSMINAL,
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LDUMAX, LDUMAXA, LDUMAXL, LDUMAXAL,
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LDUMIN, LDUMINA, LDUMINL, LDUMINAL,
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SWP, SWPA, SWPL, SWPAL,
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CAS, CASA, CASL, CASAL, // 32/64
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CASB, CASAB, CASLB, CASALB, // byte
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CASH, CASAH, CASLH, CASALH, // half
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CASP, CASPA, CASPL, CASPAL, // pair (W,W)/(X,X)
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// -------------------------------------------------------------------------
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// Pointer Authentication (PAC v8.3-A)
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// -------------------------------------------------------------------------
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PACIA, PACIB, PACDA, PACDB,
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PACIZA, PACIZB, PACDZA, PACDZB, // implicit-zero variants
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AUTIA, AUTIB, AUTDA, AUTDB,
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AUTIZA, AUTIZB, AUTDZA, AUTDZB,
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PACIASP, PACIBSP, AUTIASP, AUTIBSP, // hint-encoded SP variants
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PACIA1716, PACIB1716, AUTIA1716, AUTIB1716,
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PACGA,
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XPACI, XPACD, XPACLRI,
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RETAA, RETAB,
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BRAA, BRAB, BRAAZ, BRABZ,
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BLRAA, BLRAB, BLRAAZ, BLRABZ,
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ERETAA, ERETAB,
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// -------------------------------------------------------------------------
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// Branch Target Identification (BTI v8.5-A)
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// -------------------------------------------------------------------------
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BTI, // single mnemonic; modifier (c/j/jc) in operand
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// -------------------------------------------------------------------------
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// Memory Tagging Extension (MTE v8.5-A)
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// -------------------------------------------------------------------------
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IRG, ADDG, SUBG, GMI, SUBP, SUBPS,
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LDG, STG, ST2G, STZG, STZ2G, STGP,
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LDGM, STGM, STZGM,
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// -------------------------------------------------------------------------
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// CRC32 (v8.0-A optional, mandatory v8.1+)
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// -------------------------------------------------------------------------
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CRC32B, CRC32H, CRC32W, CRC32X,
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CRC32CB, CRC32CH, CRC32CW, CRC32CX,
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// -------------------------------------------------------------------------
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// Crypto: AES / SHA / SM3 / SM4 / polynomial multiply
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// -------------------------------------------------------------------------
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AESE, AESD, AESMC, AESIMC,
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SHA1H, SHA1C, SHA1P, SHA1M, SHA1SU0, SHA1SU1,
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SHA256H, SHA256H2, SHA256SU0, SHA256SU1,
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SHA512H, SHA512H2, SHA512SU0, SHA512SU1, // v8.2-A
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EOR3, BCAX, RAX1, XAR, // SHA3 v8.2-A
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SM3PARTW1, SM3PARTW2, SM3SS1, SM3TT1A, SM3TT1B, SM3TT2A, SM3TT2B,
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SM4E, SM4EKEY,
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PMULL, PMULL2,
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// -------------------------------------------------------------------------
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// BFloat16 (BF16; v8.6-A)
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// -------------------------------------------------------------------------
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BFCVT, // BFloat16 from single
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BFDOT, BFMMLA, BFMLALB, BFMLALT, BFCVTN, BFCVTN2,
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// -------------------------------------------------------------------------
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// NEON Advanced SIMD
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// -------------------------------------------------------------------------
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// Vector forms. A name that also has a scalar form above (ADD/SUB/MUL/
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// AND/ORR/EOR/MVN/...) is the SAME mnemonic -- the vector forms simply
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// join that mnemonic's run, selected by the V-register operand types.
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// Only names with no scalar counterpart appear below.
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// 3-same arithmetic
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MUL, MLA, MLS, NEG, ABS,
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SHADD, UHADD, SHSUB, UHSUB, SRHADD, URHADD,
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SQADD, UQADD, SQSUB, UQSUB,
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SMAX, UMAX, SMIN, UMIN,
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SABD, UABD, SABA, UABA,
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ADDP, ADDV,
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SADDLP, UADDLP, SADALP, UADALP,
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SADDLV, UADDLV, SMAXV, UMAXV, SMINV, UMINV,
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SMAXP, UMAXP, SMINP, UMINP,
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// long / wide / narrowing
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SADDL, SADDL2, UADDL, UADDL2,
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SSUBL, SSUBL2, USUBL, USUBL2,
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SADDW, SADDW2, UADDW, UADDW2,
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SSUBW, SSUBW2, USUBW, USUBW2,
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RADDHN, RADDHN2, RSUBHN, RSUBHN2,
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ADDHN, ADDHN2, SUBHN, SUBHN2,
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XTN, XTN2, SQXTN, SQXTN2, UQXTN, UQXTN2, SQXTUN, SQXTUN2,
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// multiply long / multiply-accumulate long
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SMULL, SMULL2, UMULL, UMULL2,
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SMLAL, SMLAL2, UMLAL, UMLAL2,
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SMLSL, SMLSL2, UMLSL, UMLSL2,
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SQDMULL, SQDMULL2, SQDMLAL, SQDMLAL2, SQDMLSL, SQDMLSL2,
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SQDMULH, SQRDMULH,
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// dot product
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SDOT, UDOT, USDOT,
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// FP vector
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FMLA, FMLS, FMULX,
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FMAXP, FMINP, FMAXNMP, FMINNMP,
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FMAXV, FMINV, FMAXNMV, FMINNMV,
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FRECPE, FRSQRTE, FRECPS, FRSQRTS, FRECPX,
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FADDP,
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FCVTL, FCVTL2, FCVTN, FCVTN2, FCVTXN, FCVTXN2,
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// FP compare (vector)
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FCMEQ, FCMGE, FCMGT, FCMLE, FCMLT,
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FACGE, FACGT,
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// Integer compare (vector)
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CMEQ, CMGE, CMGT, CMHI, CMHS, CMLE, CMLT, CMTST,
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// Logical (vector)
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MVN,
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BIT, BIF, BSL,
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// Shifts
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SHL, SQSHL, SQSHLU, SRSHL, URSHL,
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SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA,
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SSHL, USHL,
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SLI, SRI,
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SSHLL, SSHLL2, USHLL, USHLL2,
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SXTL, SXTL2, UXTL, UXTL2, // aliases of SSHLL/USHLL with imm=0
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SHRN, SHRN2, RSHRN, RSHRN2,
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SQSHRN, SQSHRN2, UQSHRN, UQSHRN2,
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SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2,
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SQSHRUN, SQSHRUN2, SQRSHRUN, SQRSHRUN2,
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// Misc / permute / bit
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DUP, INS, MOV,
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EXT,
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TBL, TBX,
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ZIP1, ZIP2, UZP1, UZP2, TRN1, TRN2,
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NOT, REV64,
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CNT,
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URECPE, URSQRTE,
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// Vector immediate
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MOVI, MVNI,
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// NEON load/store
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LD1, LD2, LD3, LD4, // multiple structures
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ST1, ST2, ST3, ST4,
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LD1R, LD2R, LD3R, LD4R, // load-and-replicate to all lanes
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// FP/SIMD load/store using V/D/S/H/B/Q registers
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// -------------------------------------------------------------------------
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// SVE / SVE2 base
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// -------------------------------------------------------------------------
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//
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// SVE reuses the base integer / NEON mnemonics: `add z0.s, z1.s, z2.s`
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// and `add z0.s, p0/m, z0.s, z1.s` are both ADD, and land in ADD's run
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// as forms taking Z / predicate operands. Only SVE-only names are listed.
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// Integer arithmetic (vectors, unpredicated)
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// Integer arithmetic (predicated, destructive merging)
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SUBR,
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ASRR, LSLR, LSRR,
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// FP arithmetic (unpredicated)
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FTSMUL,
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// FP arithmetic (predicated, destructive merging)
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FSUBR,
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FDIVR,
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FNMLA, FNMLS,
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// Predicate logical / move
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NAND, NOR, SEL,
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ORRS, EORS,
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NANDS, NORS, ORNS,
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MOVS,
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PTRUE, PTRUES, PFALSE, PFIRST, PNEXT,
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BRKA, BRKB, BRKAS, BRKBS,
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BRKPA, BRKPB, BRKN,
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RDFFR, WRFFR, SETFFR,
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// Integer compare and set predicate
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CMPEQ, CMPNE, CMPGE, CMPGT, CMPLE, CMPLT,
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CMPHI, CMPHS, CMPLO, CMPLS,
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// FP compare and set predicate
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FCMNE, FCMUO,
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// Permute / move / replicate
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INSR,
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CPY, COMPACT,
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// Loads / stores (contiguous)
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LD1B, LD1H, LD1W, LD1D,
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LD1SB, LD1SH, LD1SW,
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ST1B, ST1H, ST1W, ST1D,
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LDFF1B, LDFF1H, LDFF1W, LDFF1D, // first-faulting
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// SVE2 additions
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WHILEGE, WHILEGT, WHILELE, WHILELT,
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WHILEHI, WHILEHS, WHILELO, WHILELS,
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SQRDMLAH, SQRDMLSH,
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ADCLB, ADCLT, SBCLB, SBCLT,
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TBL2,
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MATCH, NMATCH,
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HISTCNT, HISTSEG,
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// -------------------------------------------------------------------------
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// SME (Scalable Matrix Extension)
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// -------------------------------------------------------------------------
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SMSTART, SMSTOP,
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RDSVL, ADDHA, ADDVA,
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ZERO,
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FMOPA, FMOPS,
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BFMOPA, BFMOPS,
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SMOPA, SMOPS, UMOPA, UMOPS,
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USMOPA, SUMOPA,
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// -------------------------------------------------------------------------
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// SME tile slice load/store (LD1B/H/W/D/Q to ZA tile slice; ST1 reverse)
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// -------------------------------------------------------------------------
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LD1Q,
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ST1Q,
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// MOVA between Z register and tile slice (both directions)
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MOVA,
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// -------------------------------------------------------------------------
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// NEON complex FP multiply-add (v8.3-A FCMA extension)
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// -------------------------------------------------------------------------
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FCMLA,
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FCADD,
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// -------------------------------------------------------------------------
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// SVE prefetch, non-temporal load/store, EXT/SPLICE/INDEX
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// -------------------------------------------------------------------------
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PRFB, PRFH, PRFW, PRFD,
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LDNT1B, LDNT1H, LDNT1W, LDNT1D,
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STNT1B, STNT1H, STNT1W, STNT1D,
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SPLICE,
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INDEX,
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// -------------------------------------------------------------------------
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// SVE2 bitwise select family + polynomial multiply
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// -------------------------------------------------------------------------
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BSL1N, BSL2N, NBSL,
|
|
PMUL, PMULLB, PMULLT,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// SVE BF16 conversions (BFCVT in SVE form)
|
|
// -------------------------------------------------------------------------
|
|
BFCVTNT,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// PAC-authenticated loads (v8.3-A)
|
|
// -------------------------------------------------------------------------
|
|
LDRAA, LDRAB,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Transactional Memory Extension (TME, v9.0-A)
|
|
// -------------------------------------------------------------------------
|
|
TSTART, TCOMMIT, TCANCEL, TTEST,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Wait with timeout (v8.7-A)
|
|
// -------------------------------------------------------------------------
|
|
WFET, WFIT,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Branch consistency hint (v8.8-A BC.cond)
|
|
// -------------------------------------------------------------------------
|
|
// BC.cond: the consistent-branch form, same 16 conditions.
|
|
BC_EQ, BC_NE, BC_CS, BC_CC,
|
|
BC_MI, BC_PL, BC_VS, BC_VC,
|
|
BC_HI, BC_LS, BC_GE, BC_LT,
|
|
BC_GT, BC_LE, BC_AL, BC_NV,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Sign/zero extend aliases (canonical names for SBFM/UBFM specific cases)
|
|
// -------------------------------------------------------------------------
|
|
UXTB, UXTH, UXTW, // unsigned extends (UBFM aliases)
|
|
SXTB, SXTH, SXTW, // signed extends (SBFM aliases)
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Carry arithmetic (add/sub with carry)
|
|
// -------------------------------------------------------------------------
|
|
ADC, ADCS, SBC, SBCS,
|
|
NGC, NGCS, // NGC Rd, Rm = SBC Rd, ZR, Rm; NGCS similar
|
|
|
|
// -------------------------------------------------------------------------
|
|
// RCpc / LDAPUR / STLUR (v8.4-A unscaled release-consistency loads/stores)
|
|
// -------------------------------------------------------------------------
|
|
LDAPUR, STLUR, // 32/64-bit word
|
|
LDAPURB, STLURB, LDAPURH, STLURH, // byte / half
|
|
LDAPURSB, LDAPURSH, LDAPURSW, // signed extending
|
|
|
|
// -------------------------------------------------------------------------
|
|
// SVE BF16 predicated arithmetic (3-same)
|
|
// -------------------------------------------------------------------------
|
|
BFADD, BFSUB, BFMUL,
|
|
BFMLA, BFMLS,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Speculation / profiling barriers + speculation hints
|
|
// -------------------------------------------------------------------------
|
|
SB, // Speculation Barrier (v8.0)
|
|
CSDB, // Consumption of Speculative Data Barrier
|
|
DGH, // Data Gathering Hint (v8.5-A)
|
|
PSB_CSYNC, // Profile Synchronization Barrier
|
|
TSB_CSYNC, // Trace Synchronization Barrier
|
|
BTI_J, BTI_C, BTI_JC, // explicit BTI variants
|
|
|
|
// -------------------------------------------------------------------------
|
|
// SVE2.1 / SME2 -- BF16 unpredicated + clamp/min/max + multi-vector
|
|
// -------------------------------------------------------------------------
|
|
BFCLAMP, // BFCLAMP Zd.H, Zn.H, Zm.H
|
|
BFMAXNM, BFMINNM, // BF16 min/max-num predicated
|
|
|
|
// SME2 multi-vector: contiguous LD/ST and select-table lookup
|
|
LUTI2, LUTI4, // LUTI2/4 table lookup (byte)
|
|
|
|
// SME2 ZIP / UZP multi-way (3-vector and 4-vector forms)
|
|
ZIP,
|
|
UZP,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// RME (Realm Management Extension, ARMv9-A)
|
|
// -------------------------------------------------------------------------
|
|
TLBI_RPALOS, TLBI_RPAOS, // Realm physical address space
|
|
AT_S1E1A, // stage-1 translate with implicit authority
|
|
DC_CIPAPA, DC_CIGDPAPA, // physical-address cache mgmt
|
|
TLBI_PAALL, TLBI_PAALLOS,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Apple AMX (undocumented vendor coprocessor; A13+/M1+)
|
|
// -------------------------------------------------------------------------
|
|
//
|
|
// All AMX instructions share the encoding 0x00201000 | (op << 5) | xn,
|
|
// where xn is a 5-bit operand (typically a GPR holding pointer +
|
|
// control word). The reserved bit pattern lives in the system-
|
|
// instruction space (op0 = 0b0000) so it doesn't collide with any
|
|
// standard A64 mnemonic. Reverse-engineered ops:
|
|
//
|
|
// 00 LDX load X register set (16 input rows)
|
|
// 01 LDY load Y register set (16 input rows)
|
|
// 02 STX store X
|
|
// 03 STY store Y
|
|
// 04 LDZ load Z accumulator (64 rows)
|
|
// 05 STZ store Z
|
|
// 06 LDZI load Z interleaved
|
|
// 07 STZI store Z interleaved
|
|
// 08 EXTRX extract from X
|
|
// 09 EXTRY extract from Y
|
|
// 10 FMA64 FP64 fused multiply-add
|
|
// 11 FMS64 FP64 fused multiply-subtract
|
|
// 12 FMA32 FP32 fused multiply-add
|
|
// 13 FMS32 FP32 fused multiply-subtract
|
|
// 14 MAC16 int16 multiply-accumulate
|
|
// 15 FMA16 FP16 fused multiply-add
|
|
// 16 FMS16 FP16 fused multiply-subtract
|
|
// 17 SET enable AMX (operand=0)
|
|
// 18 CLR disable AMX
|
|
// 19 VECINT integer vector ops
|
|
// 20 VECFP FP vector ops
|
|
// 21 MATINT integer matrix ops
|
|
// 22 MATFP FP matrix ops
|
|
// 23 GENLUT general lookup table (A14+)
|
|
AMX_LDX, AMX_LDY, AMX_STX, AMX_STY,
|
|
AMX_LDZ, AMX_STZ, AMX_LDZI, AMX_STZI,
|
|
AMX_EXTRX, AMX_EXTRY,
|
|
AMX_FMA64, AMX_FMS64,
|
|
AMX_FMA32, AMX_FMS32,
|
|
AMX_MAC16, AMX_FMA16, AMX_FMS16,
|
|
AMX_SET, AMX_CLR,
|
|
AMX_VECINT, AMX_VECFP, AMX_MATINT, AMX_MATFP,
|
|
AMX_GENLUT,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// MOPS (Memory Operations, v8.8-A)
|
|
// -------------------------------------------------------------------------
|
|
//
|
|
// Each operation is split into a 3-instruction Prologue/Main/Epilogue
|
|
// sequence that all share the same {Xd, Xs, Xn} destructive operands.
|
|
// CPY* : general memcpy (may overlap)
|
|
// CPYF* : forward-only memcpy
|
|
// SET* : memset (Xs holds the byte value)
|
|
CPYP, CPYM, CPYE,
|
|
CPYFP, CPYFM, CPYFE,
|
|
SETP, SETM, SETE,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Cache management (SYS-encoded under op0=3 or op0=0)
|
|
// -------------------------------------------------------------------------
|
|
//
|
|
// Data cache:
|
|
DC_IVAC, DC_ISW, DC_CSW, DC_CISW,
|
|
DC_ZVA, DC_CVAC, DC_CVAU, DC_CIVAC,
|
|
// Instruction cache:
|
|
IC_IALLUIS, IC_IALLU, IC_IVAU,
|
|
// Address translate (PE current EL):
|
|
AT_S1E1R, AT_S1E1W, AT_S1E0R, AT_S1E0W,
|
|
AT_S1E2R, AT_S1E2W, AT_S1E3R, AT_S1E3W,
|
|
AT_S12E1R, AT_S12E1W, AT_S12E0R, AT_S12E0W,
|
|
// TLB invalidate (the practical subset):
|
|
TLBI_VMALLE1, TLBI_VMALLE1IS,
|
|
TLBI_VAE1, TLBI_VAE1IS,
|
|
TLBI_ASIDE1, TLBI_ASIDE1IS,
|
|
TLBI_VAAE1, TLBI_VAAE1IS,
|
|
TLBI_VALE1, TLBI_VALE1IS,
|
|
TLBI_VAALE1, TLBI_VAALE1IS,
|
|
TLBI_ALLE1, TLBI_ALLE1IS,
|
|
TLBI_ALLE2, TLBI_ALLE2IS, TLBI_ALLE3, TLBI_ALLE3IS,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Prefetch
|
|
// -------------------------------------------------------------------------
|
|
PRFM, PRFUM,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Aliases (printed canonically; encode the underlying operation with
|
|
// Rd=ZR or Rn=ZR fixed).
|
|
// -------------------------------------------------------------------------
|
|
NEGS, // NEGS Rd, Rm{,shift} = SUBS Rd, ZR, Rm{,shift}
|
|
CMP, // CMP Rn, Rm{,shift} = SUBS ZR, Rn, Rm{,shift}
|
|
CMN, // CMN Rn, Rm{,shift} = ADDS ZR, Rn, Rm{,shift}
|
|
}
|