mirror of
https://github.com/odin-lang/Odin.git
synced 2026-09-02 02:03:35 +00:00
eda4921c65
An instruction carried four operands. The coprocessor transfers need six -- `mcr p15, #0, r0, c0, c0, #0` -- and dropping the tail is not merely printing short: an opc2 that is not zero encoded as zero, which is a different instruction. Six operands do not fit alongside the rest in 64 bytes, since Operand is 11 and Memory cannot go below 8, so Instruction is 128 now and straddles two cache lines rather than one. With room for them, the block itself turns out to have been wrong throughout. CDP, MCR and MRC took CRd from bits 19:16, which is CRn; CRd is 15:12. MCR and MRC read a four-bit opc1 where theirs is the three bits at 23:21. Neither they nor CDP read opc2 at all. MCRR and MRRC dropped CRm. LDC and STC were worse: they took CRd from the base register's field, read the offset with the halfword-load encoding rather than as an imm8 counting words, and their base pattern named P=0 W=0, which is the unindexed form whose syntax is `{option}` and not what they printed. They now have the offset, pre-indexed and post-indexed forms, with U left out of the mask because it is the offset's sign and belongs to the memory operand. The N bit asks the coprocessor for the long transfer and the syntax spells that as an L, so LDCL, STCL, LDC2L and STC2L are mnemonics of their own. None of this is reachable from the table sweep, which decodes each form's canonical word with every variable field zero -- for these that means p0, which ARMv8 reserves and no assembler will take. So twelve hand-picked words go in the pipeline test instead, checked against the text an assembler accepts for them, including a p15 system-register read. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
518 lines
22 KiB
Odin
518 lines
22 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// AArch32 MNEMONICS (ARMv4-ARMv8 AArch32 + Thumb-1/Thumb-2 + VFP + NEON)
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// =============================================================================
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//
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// Single Mnemonic enum shared between A32 (32-bit ARM) and T32 (Thumb). Each
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// entry in ENCODING_TABLE carries a Mode tag (A32 vs T32) so the same mnemonic
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// can have multiple encodings (one per mode, sometimes more for different
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// operand-shape variants).
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//
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// Mnemonic naming convention:
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// * No size/condition suffix in the enum name -- conditions are runtime
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// parameters (cond field, 4 bits) and sizes are operand-derived.
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// * Variant suffixes describe operand shape, not condition:
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// _IMM = immediate operand
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// _REG = pure register form
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// _RSR = register-shifted-register
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// _LSL/_LSR/_ASR/_ROR/_RRX = immediate shift type
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// _D = 64-bit double-register form (LDRD/STRD/VFPv2 D-reg)
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// _F32/_F64/_F16 = VFP float width
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// _I8/_I16/_I32/_I64 = NEON integer element width
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// _S8/_S16/_S32/_S64 = NEON signed integer
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// _U8/_U16/_U32/_U64 = NEON unsigned integer
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// _P8/_P64 = NEON polynomial (for VMULL etc.)
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//
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// We use the canonical UAL spelling so the printer can reconstruct
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// assembly-style output (`VADD.F32 D0, D1, D2`) by combining mnemonic +
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// data-type suffix from the entry's operand kinds.
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Mnemonic :: enum u16 {
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INVALID = 0,
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// -------------------------------------------------------------------------
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// Data processing -- core 16 ops (A32 + T32)
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// -------------------------------------------------------------------------
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AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC,
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TST, TEQ, CMP, CMN, ORR, MOV, BIC, MVN,
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// Shift mnemonics (in A32 these are MOV aliases with shift, but in Thumb
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// they are first-class encodings, so they have their own Mnemonic entries)
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LSL, LSR, ASR, ROR, RRX,
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// Thumb-1 specific: ADR is an alias for ADD Rd, PC, #imm (also exists in
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// A32 as an ADD/SUB imm to PC alias)
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ADR,
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NEG, // Thumb-1 only: NEG Rd, Rm = RSB Rd, Rm, #0
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// ARMv6T2: 16-bit immediate moves
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MOVW, // MOV with 16-bit immediate (low half)
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MOVT, // MOV-Top (high half, preserves low)
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// ARMv6T2: bit field manipulation
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BFC, BFI, SBFX, UBFX,
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// ARMv6: register operand sign/zero extends with optional rotation
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SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH,
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SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH,
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// ARMv6: bit reverse / byte swap / count leading zeros
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CLZ, RBIT, REV, REV16, REVSH,
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SEL, // select bytes per APSR.GE flags
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// ARMv6T2/v7: PKHBT/PKHTB (pack halfword)
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PKHBT, PKHTB,
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// ARMv6: USAD8 (sum of absolute differences)
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USAD8, USADA8,
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// ARMv6: saturating arithmetic
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SSAT, USAT, SSAT16, USAT16,
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QADD, QSUB, QDADD, QDSUB,
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// ARMv6: SIMD on GPRs (8/16-bit lanes packed in 32-bit reg)
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SADD8, SADD16, SASX, SSAX, SSUB8, SSUB16,
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UADD8, UADD16, UASX, USAX, USUB8, USUB16,
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QADD8, QADD16, QASX, QSAX, QSUB8, QSUB16,
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UQADD8, UQADD16, UQASX, UQSAX, UQSUB8, UQSUB16,
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SHADD8, SHADD16, SHASX, SHSAX, SHSUB8, SHSUB16,
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UHADD8, UHADD16, UHASX, UHSAX, UHSUB8, UHSUB16,
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// ARMv6: dual multiply-accumulate
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SMUAD, SMUADX, SMUSD, SMUSDX,
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SMLAD, SMLADX, SMLSD, SMLSDX,
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SMLALD, SMLALDX, SMLSLD, SMLSLDX,
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// Most-significant-word multiply
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SMMUL, SMMULR, SMMLA, SMMLAR, SMMLS, SMMLSR,
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// Multiply / multiply-accumulate (ARMv4+ core)
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MUL, MLA,
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MLS, // ARMv6T2: multiply-subtract
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UMULL, UMLAL, SMULL, SMLAL,
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UMAAL, // ARMv6: unsigned long multiply-acc-acc
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// Halfword multiply (ARMv5TE / ARMv6 DSP):
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// SMLA{x}{y}, SMLAW{y}, SMUL{x}{y}, SMULW{y}, SMLAL{x}{y}
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SMLABB, SMLABT, SMLATB, SMLATT,
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SMLAWB, SMLAWT,
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SMULBB, SMULBT, SMULTB, SMULTT,
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SMULWB, SMULWT,
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SMLALBB, SMLALBT, SMLALTB, SMLALTT,
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// Integer division (ARMv7-A optional, ARMv7-R/M mandatory; v7VE adds A-profile)
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SDIV, UDIV,
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// -------------------------------------------------------------------------
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// Branches
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// -------------------------------------------------------------------------
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B, // signed 24/26-bit branch
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BL, // branch + link
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BX, // branch and exchange (to ARM/Thumb)
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BLX, // branch+link+exchange (reg or imm)
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BXJ, // branch and exchange to Jazelle (deprecated)
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// ARMv6T2+: compare and branch (Thumb-only)
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CBZ, CBNZ,
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// ARMv6T2+: table branch (Thumb-only)
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TBB, TBH,
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// -------------------------------------------------------------------------
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// Status register access / hint instructions
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// -------------------------------------------------------------------------
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MSR, MRS,
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CPS, // change processor state
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SETEND, // set endianness (deprecated in v8)
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NOP, YIELD, WFE, WFI, SEV,
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SEVL, // ARMv8: sev local
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DBG, HINT, // generic hint with imm
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DMB, DSB, ISB, // ARMv7 barriers
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CLREX, // clear exclusive monitor
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PLD, PLDW, PLI, // preload
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// ARMv8 AArch32 additions
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HLT, // halt instruction (debug)
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DCPS1, DCPS2, DCPS3, // debug change processor state
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ERET, // exception return (PL2+)
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// ARMv8 security/profiling/trace barriers (FEAT_RAS, FEAT_SB, FEAT_SPE, FEAT_TRF)
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ESB, // error synchronization barrier (HINT #16)
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PSB_CSYNC, // profile sync barrier (HINT #17)
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TSB_CSYNC, // trace sync barrier (HINT #18)
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CSDB, // consumption of speculative data barrier (HINT #20)
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SB, // synchronization barrier (ARMv8.5, dedicated encoding)
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// ARMv8.1 PAN (Privileged Access Never) bit toggle
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SETPAN,
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// -------------------------------------------------------------------------
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// Exception generation
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// -------------------------------------------------------------------------
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SVC, // supervisor call (was SWI)
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BKPT, // breakpoint
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HVC, // hypervisor call (ARMv7VE)
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SMC, // secure monitor call (TrustZone)
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UDF, // permanently undefined
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// -------------------------------------------------------------------------
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// Load / Store
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// -------------------------------------------------------------------------
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LDR, STR, // word
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LDRB, STRB, // byte
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LDRH, STRH, // halfword
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LDRSB, LDRSH, // signed loads
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LDRD, STRD, // doubleword (Rt/Rt+1 pair)
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LDRT, STRT, // user-mode (privileged-mode pretend)
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LDRBT, STRBT,
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LDRHT, STRHT,
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LDRSBT, LDRSHT,
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// ARMv6+ acquire/release
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LDA, STL, // word acquire/release
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LDAB, STLB, // byte
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LDAH, STLH, // halfword
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// ARMv6 exclusive load/store
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LDREX, STREX,
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LDREXB, STREXB,
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LDREXH, STREXH,
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LDREXD, STREXD,
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LDAEX, STLEX, // ARMv8 acquire/release exclusive
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LDAEXB, STLEXB,
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LDAEXH, STLEXH,
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LDAEXD, STLEXD,
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// Block move
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LDM, STM, // IA order (the default spelling)
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// The other three increment/decrement orders are their own mnemonics --
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// that is how an assembler spells them, and it is the only way to reach
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// their encodings: all four share one operand shape, so nothing else
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// tells them apart.
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LDMIB, LDMDA, LDMDB,
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STMIB, STMDA, STMDB,
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// Stack convenience aliases
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PUSH, POP,
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// Swap (deprecated since ARMv6 but still encoded)
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SWP, SWPB,
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// -------------------------------------------------------------------------
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// ARMv6 / Return-from-Exception
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// -------------------------------------------------------------------------
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// The addressing mode is part of the name, as it is for LDM and STM.
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RFEDA, RFEDB, RFEIA, RFEIB, // return from exception
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SRSDA, SRSDB, SRSIA, SRSIB, // store return state
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// -------------------------------------------------------------------------
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// Coprocessor (legacy CP-space; many subsumed by VFP/NEON)
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// -------------------------------------------------------------------------
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CDP, CDP2,
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MCR, MCR2, MRC, MRC2,
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MCRR, MCRR2, MRRC, MRRC2,
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LDC, LDC2, STC, STC2,
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// The N bit asks the coprocessor for the long transfer, and the syntax
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// spells that on the mnemonic.
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LDCL, LDC2L, STCL, STC2L,
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// -------------------------------------------------------------------------
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// ARMv8 AArch32 CRC32 (FEAT_CRC32)
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// -------------------------------------------------------------------------
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CRC32B, CRC32H, CRC32W,
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CRC32CB, CRC32CH, CRC32CW,
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// -------------------------------------------------------------------------
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// VFP / Advanced SIMD shared opcodes
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// -------------------------------------------------------------------------
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// -- Scalar FP arithmetic (operates on S<n>, D<n>) -------------------------
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VADD, VSUB, VMUL, VDIV,
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VMLA, VMLS, VNMUL, VNMLA, VNMLS,
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VFMA, VFMS, VFNMA, VFNMS,
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// The bfloat16 multiply-accumulates name which half of each pair they
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// take, bottom or top, on the mnemonic.
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VFMAB, VFMAT,
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VABS, VNEG, VSQRT,
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VCMP, VCMPE,
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VCVT, // cross-format conversion (encoded via cmode bits)
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VCVTB, VCVTT, // half-precision conversion (bottom/top lane)
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VCVTA, VCVTN, VCVTP, VCVTM, // ARMv8: rounding-mode FP-to-int
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VCVTR, // FP-to-int using FPSCR rounding
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VMOV, // many forms (reg-reg, reg-imm, GPR-FPR)
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VMRS, VMSR, // FPSCR/coprocessor access
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VLDR, VSTR,
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// The addressing mode is part of the name, as it is for LDM and STM.
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VLDMIA, VLDMDB, VSTMIA, VSTMDB,
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VPUSH, VPOP,
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VSEL, // ARMv8 conditional select
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VMAXNM, VMINNM, // ARMv8 IEEE 754-2008 min/max
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VRINTA, VRINTN, VRINTP, VRINTM, // ARMv8 round-to-int by mode
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VRINTR, VRINTZ, VRINTX, // round to int per current/zero/exact
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// -- NEON-specific (vector D/Q reg) -----------------------------------------
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VADDL, VADDW, VSUBL, VSUBW,
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VHADD, VHSUB, VRHADD,
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VQADD, VQSUB,
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VMULL, VMLAL, VMLSL,
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VQDMULL,VQDMLAL,VQDMLSL,
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VQDMULH,VQRDMULH,
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// indexed variants
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// ARMv8.1 FEAT_RDM: rounding doubling multiply-accumulate
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VQRDMLAH, VQRDMLSH,
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VABA, VABAL,
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VABD, VABDL,
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VAND, VBIC, VORR, VORN, VEOR,
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VBSL, VBIT, VBIF,
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VMVN,
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VMOVN, VQMOVN, VQMOVUN,
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VMOVL, // extend halve-width to full-width
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VTST,
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VCEQ, VCGE, VCGT, VCLE, VCLT,
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VACGE, VACGT, // absolute compare for FP
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VACLE, VACLT,
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VMAX, VMIN,
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VPMAX, VPMIN,
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VPADD, VPADDL, VPADAL,
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VRECPE, VRECPS, // reciprocal estimate / step
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VRSQRTE,VRSQRTS,
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VSHL, VSHR, VSRA, VRSHL, VRSHR, VRSRA,
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VSLI, VSRI,
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VQSHL, VQSHRN, VQSHRUN,
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VQRSHL, VQRSHRN, VQRSHRUN,
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VSHRN, VRSHRN,
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VSHLL, // shift-left long
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VCLS, VCLZ, VCNT,
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// (placeholders; canonical via operand types)
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VREV16, VREV32, VREV64,
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VEXT, // vector extract
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VTBL, VTBX, // table lookup
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VTRN, VUZP, VZIP,
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VDUP, // duplicate scalar to vector
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VSWP, // swap
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// Lane access
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// VMOV.<dt> R, D[i] / VMOV.<dt> D[i], R
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// Load/Store structures (NEON)
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VLD1, VLD2, VLD3, VLD4,
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VST1, VST2, VST3, VST4,
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// -- Advanced SIMD / NEON crypto (ARMv8 AArch32 FEAT_AES + FEAT_SHA1/2) ---
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AESE, AESD, AESMC, AESIMC,
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SHA1H, SHA1SU0, SHA1SU1, SHA1C, SHA1M, SHA1P,
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SHA256H, SHA256H2, SHA256SU0, SHA256SU1,
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// -- VFP rounding (ARMv8 FEAT_FP) ----------------------------------------
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VJCVT, // VJCVT: F64-to-S32 with FPSCR.RM rounding
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// -- Dot Product (FEAT_DotProd) ------------------------------------------
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VSDOT, VUDOT,
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// -- BF16 (FEAT_BF16) ----------------------------------------------------
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// BF16<->F32
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VDOT,
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VMMLA,
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// -- FHM (FEAT_FHM) FP16 matrix mul/acc ----------------------------------
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VFMAL, VFMSL, // F16 fused multiply-add long
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// -- ComplexNum (FEAT_FCMA) ----------------------------------------------
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VCMLA, VCADD,
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// VCMLA by indexed scalar
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// -- I8MM (FEAT_I8MM, ARMv8.6) integer matrix multiply + mixed-sign dot --
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VSMMLA, // signed-signed 8x8 matrix mul
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VUMMLA, // unsigned-unsigned
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VUSMMLA, // unsigned-signed
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VSUDOT, // signed-unsigned dot product
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VUSDOT, // unsigned-signed dot product
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// -- Lane-indexed NEON multiply / MAC forms (heavily used in DSP/codec) --
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// -- MVE saturating unary -----------------------------------------------
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VQABS, VQNEG,
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// -- MVE FP lane manipulation (F16 packing) -----------------------------
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VMOVX, // extract high F16 lane from S-reg
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VINS, // insert F16 into high lane of S-reg
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// -- MVE gather/scatter (vector offset addressing) ----------------------
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// -- NEON compare-with-zero (distinct encodings from reg-vs-reg) --------
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// -- NEON replicate loads (broadcast one element to all lanes) ----------
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// The broadcast structure loads are VLD2/VLD3/VLD4 with an all-lanes
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// list, not mnemonics of their own -- that is how they are written.
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// -- NEON single-element-lane load/store (lane form, not multi-vec) -----
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// -- VFP fixed-point conversions (with #fbits operand) ------------------
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// VCVT.<dt> Sd, Sd, #fbits family
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// -------------------------------------------------------------------------
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// Thumb-only mnemonics (extra ones not shared with A32)
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// -------------------------------------------------------------------------
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IT, // if-then block (Thumb-2)
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// ARMv6: change endianness in Thumb
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// SETEND already covers both A32 and T32
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// -------------------------------------------------------------------------
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// ARMv8-M Security Extensions (TrustZone-M)
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// -------------------------------------------------------------------------
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TT, // test target
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TTT, // test target unprivileged
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TTA, // test target alternate domain
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TTAT, // test target alternate domain unprivileged
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SG, // secure gateway (enter secure state)
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BXNS, // branch and exchange non-secure
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BLXNS, // branch with link and exchange non-secure
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// -------------------------------------------------------------------------
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// PACBTI for ARMv8.1-M (Cortex-M85)
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// -------------------------------------------------------------------------
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PAC, // PAC R12, LR, SP
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PACBTI, // PACBTI R12, LR, SP (combined PAC + BTI marker)
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AUT, // AUT R12, LR, SP
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AUTG, // AUTG Rd, Rn, Rm (general form)
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BTI, // M-profile branch target identification
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// -------------------------------------------------------------------------
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// ARMv8.1-M low-overhead loops (Helium prerequisite, but useful even without MVE)
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// -------------------------------------------------------------------------
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WLS, // while loop start
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WLSTP, // while loop start with tail predication
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DLS, // do loop start
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DLSTP, // do loop start with tail predication
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LE, // loop end
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LETP, // loop end with tail predication
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LCTP, // loop clear tail predication
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// Branch Future (ARMv8.1-M). T32, encoded via REL_BF + BF_BOFF/BF_BLOC/BF_RM
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// operand encodings and BF_BOFF_T32/BF_BLOC_T32 relocations (see encoder.odin).
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// bf-point imm4 at hw0[10:7]; branch target J:imm10 at hw1[11]:[10:1]; BFLX/BFX
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// use a register target Rm at hw0[3:0]; BFCSEL adds a 4-bit condition at
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// hw0[5:2] (its else-target is the implicit fall-through). Byte-exact vs llvm-mc.
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BF, // branch future
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BFX, // branch future indirect (bfx)
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BFL, // branch future and link
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BFLX, // branch future link and exchange
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BFCSEL, // branch future conditional select
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// -------------------------------------------------------------------------
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// Custom Datapath Extension (CDE)
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// -------------------------------------------------------------------------
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CX1, CX1A, // dual-coprocessor + GPR dest (32-bit)
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CX1D, CX1DA, // 64-bit GPR pair dest
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CX2, CX2A, // + Rn input
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CX2D, CX2DA,
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CX3, CX3A, // + two Rn inputs
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CX3D, CX3DA,
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VCX1, VCX1A, // VFP S/D-reg dest
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VCX2, VCX2A,
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VCX3, VCX3A,
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// -------------------------------------------------------------------------
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// MVE (Helium / M-profile Vector Extension) -- ARMv8.1-M
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// -------------------------------------------------------------------------
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//
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// Note: many MVE ops share mnemonics with NEON (VADD/VSUB/VMUL/VAND/etc).
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// Distinct MVE-only mnemonics are below. Shared ones get additional
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// MVE-mode entries in ENCODING_TABLE.
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// Predication block (then/else interleaved)
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VPT, // predicate-then block
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VPST, // predicate-then-set block (single)
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VPSEL, // predicate select (per-element)
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VPNOT, // invert VPR
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VCTP, // create tail predicate (.8/.16/.32/.64)
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|
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// Reductions (single-vector accumulate)
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VADDV, VADDVA, // accumulate sum across vector (signed/unsigned, +acc)
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VADDLV, VADDLVA, // long version (S64 accumulator)
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VMAXV, VMAXAV, // max (and absolute)
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|
VMINV, VMINAV,
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VMAXNMV, VMAXNMAV, // FP max-num
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|
VMINNMV, VMINNMAV,
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|
|
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// Dual MAC reductions (multiply-accumulate then sum)
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|
VABAV, // accumulate absolute difference
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|
VMLADAV, VMLADAVA, VMLADAVX, VMLADAVAX,
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VMLALDAV, VMLALDAVA, VMLALDAVX, VMLALDAVAX,
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|
VMLSDAV, VMLSDAVA, VMLSDAVX, VMLSDAVAX,
|
|
VMLSLDAV, VMLSLDAVA, VMLSLDAVX, VMLSLDAVAX,
|
|
VRMLALDAVH, VRMLALDAVHA, VRMLALDAVHX, VRMLALDAVHAX,
|
|
VRMLSLDAVH, VRMLSLDAVHA, VRMLSLDAVHX, VRMLSLDAVHAX,
|
|
VMLAV, VMLAVA, // simple MAC across vector
|
|
VMLSV, VMLSVA,
|
|
|
|
// Complex arithmetic (Q-register vector form)
|
|
VCMUL, // complex multiply (separate from VCMLA)
|
|
VHCADD, // halving complex add
|
|
|
|
// Bit reverse + shifts unique to MVE
|
|
VBRSR, // bit reverse with shift right
|
|
VSHLC, // shift left with carry
|
|
VDDUP, // decrement and duplicate
|
|
VIDUP, // increment and duplicate
|
|
VDWDUP, // decrement-wrap and duplicate
|
|
VIWDUP, // increment-wrap and duplicate
|
|
|
|
// Narrowing with B/T (bottom/top)
|
|
VMOVNB, VMOVNT, // narrow bottom/top
|
|
VQMOVNB, VQMOVNT, // saturating narrow B/T
|
|
VQMOVUNB, VQMOVUNT, // saturating-unsigned narrow B/T
|
|
|
|
// Widening with B/T
|
|
VSHLLB, VSHLLT, // shift left long bottom/top
|
|
VMULLB, VMULLT, // multiply long B/T
|
|
VMLALB, VMLALT, // multiply-accumulate long B/T
|
|
VMLSLB, VMLSLT,
|
|
|
|
VSHRNB, VSHRNT, // shift right narrow B/T
|
|
VRSHRNB, VRSHRNT,
|
|
VQSHRNB, VQSHRNT,
|
|
VQRSHRNB, VQRSHRNT,
|
|
VQSHRUNB, VQSHRUNT,
|
|
VQRSHRUNB, VQRSHRUNT,
|
|
|
|
// Move between Qd-lane and GPR (MVE-specific 4-element split forms)
|
|
// VMOV Qd[i], Rt -- single lane to GPR
|
|
// VMOV Rt, Qd[i]
|
|
// VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair
|
|
|
|
// Saturating doubling MAC reductions
|
|
VQDMLADH, VQDMLADHX,
|
|
VQDMLSDH, VQDMLSDHX,
|
|
VQRDMLADH, VQRDMLADHX,
|
|
VQRDMLSDH, VQRDMLSDHX,
|
|
|
|
// Misc
|
|
// (rarely used)
|
|
// (MVE form; VCMLA already exists)
|
|
|
|
// MVE load/store (mostly reuses VLDR/VSTR but distinct forms exist):
|
|
VLDRB, VLDRH, VLDRW, VLDRD, // MVE contiguous load (B/H/W/D)
|
|
VSTRB, VSTRH, VSTRW, VSTRD, // MVE contiguous store
|
|
VLD20, VLD21, // 2-vector interleaved (halves)
|
|
VLD40, VLD41, VLD42, VLD43, // 4-vector interleaved (quarters)
|
|
VST20, VST21,
|
|
VST40, VST41, VST42, VST43,
|
|
|
|
// -------------------------------------------------------------------------
|
|
// Sentinel
|
|
// -------------------------------------------------------------------------
|
|
_COUNT,
|
|
}
|