mirror of
https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
193 lines
6.6 KiB
Odin
193 lines
6.6 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// AArch32 REGISTERS
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// =============================================================================
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//
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// The Register type is a u8: high 3 bits encode the register class, low 5 bits
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// the hardware number. This keeps the encoder/decoder fast (single byte) and
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// trivially extractable via masks.
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//
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// Bits 7-5 Class Members
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// ----------------------------------------------------------------------
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// 000 GPR R0..R15 (R13=SP, R14=LR, R15=PC)
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// 001 SPR S0..S31 (VFP single-precision; aliases low D regs)
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// 010 DPR D0..D31 (VFP/NEON double-precision)
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// 011 QPR Q0..Q15 (NEON 128-bit; aliases D2n / D2n+1)
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// 100 SREG PSR/CPSR/SPSR/APSR (limited)
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// 101 FPSC FPSCR / FPSID / FPEXC / etc.
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// 110 BANKED Banked SPSR_*/R*_* registers (MSR/MRS specialised)
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// 111 COPROC Coprocessor register (CPx CRn / CRm) -- value stored as packed
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//
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// The hw number is masked to 5 bits, giving 32 possible regs per class
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// (sufficient for VFPv3+'s D0..D31 and NEON's S0..S31 / Q0..Q15).
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Register :: distinct u16
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REG_NONE :: u16(0x0000)
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REG_GPR :: u16(0x1000)
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REG_SPR :: u16(0x2000)
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REG_DPR :: u16(0x3000)
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REG_QPR :: u16(0x4000)
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REG_SREG :: u16(0x5000)
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REG_FPSC :: u16(0x6000)
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REG_BANKED :: u16(0x7000)
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REG_COPROC :: u16(0x8000)
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REG_CLASS_MASK :: u16(0xF000)
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REG_HW_MASK :: u16(0x0FFF)
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// ---- GPR ---------------------------------------------------------------------
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R0 :: Register(REG_GPR | 0)
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R1 :: Register(REG_GPR | 1)
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R2 :: Register(REG_GPR | 2)
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R3 :: Register(REG_GPR | 3)
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R4 :: Register(REG_GPR | 4)
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R5 :: Register(REG_GPR | 5)
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R6 :: Register(REG_GPR | 6)
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R7 :: Register(REG_GPR | 7)
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R8 :: Register(REG_GPR | 8)
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R9 :: Register(REG_GPR | 9)
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R10 :: Register(REG_GPR | 10)
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R11 :: Register(REG_GPR | 11)
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R12 :: Register(REG_GPR | 12)
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R13 :: Register(REG_GPR | 13)
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R14 :: Register(REG_GPR | 14)
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R15 :: Register(REG_GPR | 15)
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// Conventional aliases
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SB :: R9 // static base (PCS)
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SL :: R10 // stack limit
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FP :: R11 // frame pointer
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IP :: R12 // intra-procedure scratch
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SP :: R13 // stack pointer
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LR :: R14 // link register
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PC :: R15 // program counter
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// ---- VFP single-precision ---------------------------------------------------
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S0 :: Register(REG_SPR | 0)
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S1 :: Register(REG_SPR | 1)
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S2 :: Register(REG_SPR | 2)
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S3 :: Register(REG_SPR | 3)
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S4 :: Register(REG_SPR | 4)
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S5 :: Register(REG_SPR | 5)
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S6 :: Register(REG_SPR | 6)
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S7 :: Register(REG_SPR | 7)
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S8 :: Register(REG_SPR | 8)
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S9 :: Register(REG_SPR | 9)
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S10 :: Register(REG_SPR | 10)
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S11 :: Register(REG_SPR | 11)
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S12 :: Register(REG_SPR | 12)
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S13 :: Register(REG_SPR | 13)
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S14 :: Register(REG_SPR | 14)
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S15 :: Register(REG_SPR | 15)
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S16 :: Register(REG_SPR | 16)
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S17 :: Register(REG_SPR | 17)
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S18 :: Register(REG_SPR | 18)
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S19 :: Register(REG_SPR | 19)
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S20 :: Register(REG_SPR | 20)
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S21 :: Register(REG_SPR | 21)
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S22 :: Register(REG_SPR | 22)
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S23 :: Register(REG_SPR | 23)
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S24 :: Register(REG_SPR | 24)
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S25 :: Register(REG_SPR | 25)
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S26 :: Register(REG_SPR | 26)
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S27 :: Register(REG_SPR | 27)
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S28 :: Register(REG_SPR | 28)
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S29 :: Register(REG_SPR | 29)
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S30 :: Register(REG_SPR | 30)
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S31 :: Register(REG_SPR | 31)
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// ---- VFP/NEON double-precision (D0..D31) ------------------------------------
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D0 :: Register(REG_DPR | 0)
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D1 :: Register(REG_DPR | 1)
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D2 :: Register(REG_DPR | 2)
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D3 :: Register(REG_DPR | 3)
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D4 :: Register(REG_DPR | 4)
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D5 :: Register(REG_DPR | 5)
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D6 :: Register(REG_DPR | 6)
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D7 :: Register(REG_DPR | 7)
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D8 :: Register(REG_DPR | 8)
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D9 :: Register(REG_DPR | 9)
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D10 :: Register(REG_DPR | 10)
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D11 :: Register(REG_DPR | 11)
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D12 :: Register(REG_DPR | 12)
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D13 :: Register(REG_DPR | 13)
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D14 :: Register(REG_DPR | 14)
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D15 :: Register(REG_DPR | 15)
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D16 :: Register(REG_DPR | 16)
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D17 :: Register(REG_DPR | 17)
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D18 :: Register(REG_DPR | 18)
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D19 :: Register(REG_DPR | 19)
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D20 :: Register(REG_DPR | 20)
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D21 :: Register(REG_DPR | 21)
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D22 :: Register(REG_DPR | 22)
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D23 :: Register(REG_DPR | 23)
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D24 :: Register(REG_DPR | 24)
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D25 :: Register(REG_DPR | 25)
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D26 :: Register(REG_DPR | 26)
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D27 :: Register(REG_DPR | 27)
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D28 :: Register(REG_DPR | 28)
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D29 :: Register(REG_DPR | 29)
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D30 :: Register(REG_DPR | 30)
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D31 :: Register(REG_DPR | 31)
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// ---- NEON quad-word (Q0..Q15) -----------------------------------------------
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Q0 :: Register(REG_QPR | 0)
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Q1 :: Register(REG_QPR | 1)
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Q2 :: Register(REG_QPR | 2)
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Q3 :: Register(REG_QPR | 3)
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Q4 :: Register(REG_QPR | 4)
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Q5 :: Register(REG_QPR | 5)
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Q6 :: Register(REG_QPR | 6)
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Q7 :: Register(REG_QPR | 7)
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Q8 :: Register(REG_QPR | 8)
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Q9 :: Register(REG_QPR | 9)
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Q10 :: Register(REG_QPR | 10)
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Q11 :: Register(REG_QPR | 11)
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Q12 :: Register(REG_QPR | 12)
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Q13 :: Register(REG_QPR | 13)
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Q14 :: Register(REG_QPR | 14)
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Q15 :: Register(REG_QPR | 15)
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// ---- Status / control registers ---------------------------------------------
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APSR :: Register(REG_SREG | 0)
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CPSR :: Register(REG_SREG | 1)
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SPSR :: Register(REG_SREG | 2)
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// Field-selectors for MSR APSR_nzcvq, etc, are encoded as separate Operand_Type
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// values rather than expanding the Register set.
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// FPSCR / FPSID and friends
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FPSID :: Register(REG_FPSC | 0)
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FPSCR :: Register(REG_FPSC | 1)
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MVFR2 :: Register(REG_FPSC | 5)
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MVFR1 :: Register(REG_FPSC | 6)
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MVFR0 :: Register(REG_FPSC | 7)
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FPEXC :: Register(REG_FPSC | 8)
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// ---- Helpers ----------------------------------------------------------------
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@(require_results)
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reg_class :: #force_inline proc "contextless" (r: Register) -> u16 {
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return u16(r) & REG_CLASS_MASK
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}
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@(require_results)
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reg_hw :: #force_inline proc "contextless" (r: Register) -> u16 {
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return u16(r) & REG_HW_MASK
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}
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@(require_results) is_gpr :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_GPR }
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@(require_results) is_spr :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_SPR }
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@(require_results) is_dpr :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_DPR }
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@(require_results) is_qpr :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_QPR }
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@(require_results)
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is_fp_scalar :: #force_inline proc "contextless" (r: Register) -> bool {
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c := reg_class(r); return c == REG_SPR || c == REG_DPR
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}
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@(require_results)
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is_simd :: #force_inline proc "contextless" (r: Register) -> bool {
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c := reg_class(r); return c == REG_SPR || c == REG_DPR || c == REG_QPR
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}
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