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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
104 lines
6.8 KiB
Odin
104 lines
6.8 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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// =============================================================================
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// AArch64 REGISTERS
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// =============================================================================
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//
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// AArch64 has:
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// X0..X30 64-bit general-purpose
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// W0..W30 32-bit views of the same registers
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// XZR/WZR hardwired zero (encoded as register 31 in most instructions)
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// SP/WSP stack pointer (also encoded as register 31, but only some
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// instructions accept it -- the rest read register 31 as ZR)
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// V0..V31 128-bit SIMD/FP registers
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// B/H/S/D/Q same registers, viewed as 8/16/32/64/128-bit scalars
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//
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// The SP-vs-ZR ambiguity at hw=31 is resolved by giving SP/WSP their own
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// register *class*. An operand typed `XSP_REG` accepts X0..X30 OR SP;
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// X_REG accepts X0..X30 OR XZR. Both still encode hw=31 for SP/XZR.
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Register :: distinct u16
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REG_NONE :: 0x0000
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REG_X :: 0x0100 // X0..X30, XZR (X31 = ZR semantically)
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REG_W :: 0x0200 // W0..W30, WZR
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REG_XSP :: 0x0300 // SP (only -- distinct class from X to opt-in)
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REG_WSP :: 0x0400 // WSP
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REG_V :: 0x0500 // V0..V31 (full 128-bit; used in NEON vector form)
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REG_B :: 0x0600 // B0..B31 (byte view)
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REG_H :: 0x0700 // H0..H31 (half view)
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REG_S :: 0x0800 // S0..S31 (single view)
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REG_D :: 0x0900 // D0..D31 (double view)
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REG_Q :: 0x0A00 // Q0..Q31 (quad view)
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REG_Z :: 0x0B00 // Z0..Z31 SVE scalable vector (low 128 aliased with V)
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REG_P :: 0x0C00 // P0..P15 SVE predicate
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NONE :: Register(0xFFFF)
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@(require_results) reg_hw :: #force_inline proc "contextless" (r: Register) -> u8 { return u8(r) & 0x1F }
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@(require_results) reg_class :: #force_inline proc "contextless" (r: Register) -> u16 { return u16(r) & 0xFF00 }
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@(require_results) reg_is_x :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_X }
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@(require_results) reg_is_w :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_W }
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@(require_results) reg_is_xsp :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_XSP }
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@(require_results) reg_is_wsp :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_WSP }
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// -----------------------------------------------------------------------------
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// 64-bit GPRs (X0..X30, XZR, SP)
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// -----------------------------------------------------------------------------
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X0 :: Register(REG_X | 0); X1 :: Register(REG_X | 1); X2 :: Register(REG_X | 2); X3 :: Register(REG_X | 3)
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X4 :: Register(REG_X | 4); X5 :: Register(REG_X | 5); X6 :: Register(REG_X | 6); X7 :: Register(REG_X | 7)
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X8 :: Register(REG_X | 8); X9 :: Register(REG_X | 9); X10 :: Register(REG_X | 10); X11 :: Register(REG_X | 11)
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X12 :: Register(REG_X | 12); X13 :: Register(REG_X | 13); X14 :: Register(REG_X | 14); X15 :: Register(REG_X | 15)
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X16 :: Register(REG_X | 16); X17 :: Register(REG_X | 17); X18 :: Register(REG_X | 18); X19 :: Register(REG_X | 19)
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X20 :: Register(REG_X | 20); X21 :: Register(REG_X | 21); X22 :: Register(REG_X | 22); X23 :: Register(REG_X | 23)
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X24 :: Register(REG_X | 24); X25 :: Register(REG_X | 25); X26 :: Register(REG_X | 26); X27 :: Register(REG_X | 27)
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X28 :: Register(REG_X | 28); X29 :: Register(REG_X | 29); X30 :: Register(REG_X | 30)
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XZR :: Register(REG_X | 31)
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LR :: X30 // procedure call link register
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FP_REG :: X29 // frame pointer (avoid collision with `FP` if added later)
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SP :: Register(REG_XSP | 31)
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// -----------------------------------------------------------------------------
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// 32-bit GPRs (W0..W30, WZR, WSP)
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// -----------------------------------------------------------------------------
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W0 :: Register(REG_W | 0); W1 :: Register(REG_W | 1); W2 :: Register(REG_W | 2); W3 :: Register(REG_W | 3)
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W4 :: Register(REG_W | 4); W5 :: Register(REG_W | 5); W6 :: Register(REG_W | 6); W7 :: Register(REG_W | 7)
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W8 :: Register(REG_W | 8); W9 :: Register(REG_W | 9); W10 :: Register(REG_W | 10); W11 :: Register(REG_W | 11)
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W12 :: Register(REG_W | 12); W13 :: Register(REG_W | 13); W14 :: Register(REG_W | 14); W15 :: Register(REG_W | 15)
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W16 :: Register(REG_W | 16); W17 :: Register(REG_W | 17); W18 :: Register(REG_W | 18); W19 :: Register(REG_W | 19)
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W20 :: Register(REG_W | 20); W21 :: Register(REG_W | 21); W22 :: Register(REG_W | 22); W23 :: Register(REG_W | 23)
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W24 :: Register(REG_W | 24); W25 :: Register(REG_W | 25); W26 :: Register(REG_W | 26); W27 :: Register(REG_W | 27)
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W28 :: Register(REG_W | 28); W29 :: Register(REG_W | 29); W30 :: Register(REG_W | 30)
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WZR :: Register(REG_W | 31)
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WSP :: Register(REG_WSP | 31)
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// -----------------------------------------------------------------------------
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// SIMD/FP register views (full Vn or scalar Bn/Hn/Sn/Dn/Qn)
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// -----------------------------------------------------------------------------
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V0 :: Register(REG_V | 0); V1 :: Register(REG_V | 1); V2 :: Register(REG_V | 2); V3 :: Register(REG_V | 3)
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V4 :: Register(REG_V | 4); V5 :: Register(REG_V | 5); V6 :: Register(REG_V | 6); V7 :: Register(REG_V | 7)
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V8 :: Register(REG_V | 8); V9 :: Register(REG_V | 9); V10 :: Register(REG_V | 10); V11 :: Register(REG_V | 11)
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V12 :: Register(REG_V | 12); V13 :: Register(REG_V | 13); V14 :: Register(REG_V | 14); V15 :: Register(REG_V | 15)
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V16 :: Register(REG_V | 16); V17 :: Register(REG_V | 17); V18 :: Register(REG_V | 18); V19 :: Register(REG_V | 19)
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V20 :: Register(REG_V | 20); V21 :: Register(REG_V | 21); V22 :: Register(REG_V | 22); V23 :: Register(REG_V | 23)
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V24 :: Register(REG_V | 24); V25 :: Register(REG_V | 25); V26 :: Register(REG_V | 26); V27 :: Register(REG_V | 27)
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V28 :: Register(REG_V | 28); V29 :: Register(REG_V | 29); V30 :: Register(REG_V | 30); V31 :: Register(REG_V | 31)
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// Scalar view constructors -- the hw number is the same V register.
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@(require_results) b_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_B | u16(n & 0x1F)) }
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@(require_results) h_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_H | u16(n & 0x1F)) }
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@(require_results) s_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_S | u16(n & 0x1F)) }
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@(require_results) d_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_D | u16(n & 0x1F)) }
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@(require_results) q_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_Q | u16(n & 0x1F)) }
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@(require_results) v_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_V | u16(n & 0x1F)) }
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@(require_results) x_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_X | u16(n & 0x1F)) }
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@(require_results) w_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_W | u16(n & 0x1F)) }
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