mirror of
https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
75 lines
2.8 KiB
Odin
75 lines
2.8 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc_vle
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// =============================================================================
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// PowerPC VLE Instruction
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// =============================================================================
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//
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// Variable-length: 2 bytes for `se_*` short, 4 bytes for `e_*` long.
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// The encoder picks length from the matched form's flags.short bit.
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Instruction_Flags :: bit_field u8 {
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sets_cr0: bool | 1, // Rc=1 — "." suffix
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has_oe: bool | 1, // OE=1 — "o" suffix
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lk: bool | 1, // link bit (e_bl, se_bl, etc.)
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aa: bool | 1, // absolute-address flag
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_: u8 | 4,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`,
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mnemonic: Mnemonic,
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operand_count: u8,
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flags: Instruction_Flags,
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mode: Mode,
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length: u8, // 2 or 4
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form_id: u16,
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}
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 2, mode = .PPC32_VLE}
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}
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 2, mode = .PPC32_VLE,
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ops = {op_reg(r), {}, {}, {}}}
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}
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@(require_results)
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inst_i :: #force_inline proc "contextless" (m: Mnemonic, v: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4, mode = .PPC32_VLE,
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ops = {op_imm(v), {}, {}, {}}}
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}
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, ra: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 2, mode = .PPC32_VLE,
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ops = {op_reg(rd), op_reg(ra), {}, {}}}
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}
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, ra, rb: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4, mode = .PPC32_VLE,
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ops = {op_reg(rd), op_reg(ra), op_reg(rb), {}}}
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}
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, ra: Register, v: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4, mode = .PPC32_VLE,
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ops = {op_reg(rd), op_reg(ra), op_imm(v), {}}}
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}
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4, mode = .PPC32_VLE,
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ops = {op_reg(rt), op_mem(mm), {}, {}}}
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}
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4, mode = .PPC32_VLE,
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ops = {op_label(label_id), {}, {}, {}}}
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}
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