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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
75 lines
2.5 KiB
Odin
75 lines
2.5 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_riscv
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// =============================================================================
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// RISC-V OPERANDS
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// =============================================================================
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//
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// Same kind-tagged shape as the other arches. Memory is a single
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// `(base GPR, signed 12-bit displacement)` pair -- RISC-V's only
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// addressing mode is `disp12(base)`, with no index register, no scale,
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// and no PC-relative form (PC-rel work is done by AUIPC + add/load pairs).
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//
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// RELATIVE operands cover both 13-bit branches (B-type) and 21-bit
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// jumps (J-type); the encoding form's Operand_Encoding tells the
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// encoder which scatter pattern to apply.
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Operand_Kind :: enum u8 {
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NONE,
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REGISTER,
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IMMEDIATE,
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MEMORY,
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RELATIVE,
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}
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Memory :: struct #packed {
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base: Register, // GPR base
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_: u16,
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disp: i32, // sign-extended 12-bit displacement
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}
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#assert(size_of(Memory) == 8)
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@(require_results)
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mem :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory {
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return Memory{base = base, disp = disp}
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}
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Operand :: struct #packed {
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using _: struct #raw_union {
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reg: Register, // REGISTER (int or FP)
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mem: Memory,
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immediate: i64,
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relative: i64, // label id pre-resolution; byte offset post
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},
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kind: Operand_Kind,
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size: u8,
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_: [6]u8,
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}
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#assert(size_of(Operand) == 16)
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@(require_results)
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op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { return Operand{reg = r, kind = .REGISTER, size = 4} }
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@(require_results)
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op_imm :: #force_inline proc "contextless" (v: i64, size: u8) -> Operand { return Operand{immediate = v, kind = .IMMEDIATE, size = size} }
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@(require_results)
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op_mem :: #force_inline proc "contextless" (m: Memory) -> Operand { return Operand{mem = m, kind = .MEMORY, size = 4} }
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@(require_results)
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op_label :: #force_inline proc "contextless" (label_id: u32, size: u8 = 2) -> Operand {
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return Operand{relative = i64(label_id), kind = .RELATIVE, size = size}
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}
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@(require_results)
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op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand {
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return Operand{relative = off, kind = .RELATIVE, size = 2}
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}
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// Typed constructors
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@(require_results)
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op_gpr :: #force_inline proc "contextless" (g: GPR) -> Operand {
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return Operand{reg = Register(REG_GPR | u16(g)), kind = .REGISTER, size = 4}
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}
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@(require_results)
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op_fpr :: #force_inline proc "contextless" (f: FPR) -> Operand {
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return Operand{reg = Register(REG_FPR | u16(f)), kind = .REGISTER, size = 4}
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}
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