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ff2bf13121
New REL19/REL18 operand types + BRANCH_19/BRANCH_18 encodings + REL_PC19/ REL_PC18 relocations (R6 PC-relative semantics: offset is relative to the instruction's own address, no delay-slot adjustment; LDPC aligns the PC down to 8 and scales by 8). LWPC (mips32r6), LWUPC/LDPC (mips64r6). Byte-exact vs llvm-mc and decode-clean; 281 tests green.
36 lines
1.3 KiB
Odin
36 lines
1.3 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mips
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// =============================================================================
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// MIPS RELOCATIONS
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// =============================================================================
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//
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// Per the cross-arch design (§2.4): each arch owns its own Relocation_Type
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// enum and Relocation struct. The struct shape mirrors ELF rela so an
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// object emitter can consume it unchanged; the resolution semantics for
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// each `type` value are MIPS-specific and live in encoder.odin's pass-2
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// resolver.
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Relocation_Type :: enum u8 {
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NONE = 0,
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REL16, // 16-bit signed PC-rel branch offset (BEQ/BNE/BLEZ/BGTZ/...)
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REL21, // 21-bit signed PC-rel compact branch (R6 BEQZC/BNEZC)
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REL26, // 26-bit signed PC-rel compact branch (R6 BC/BALC)
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REL_PC19, // 19-bit R6 PC-relative load offset ((target - PC) >> 2) (LWPC/LWUPC)
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REL_PC18, // 18-bit R6 PC-relative load offset ((target - (PC & ~7)) >> 3) (LDPC)
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J26, // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF)
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HI16, // upper 16 of 32-bit absolute (LUI rt, %hi(sym)+0x8000 if LO16 paired)
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LO16, // lower 16 of 32-bit absolute (ADDIU rt, rt, %lo(sym))
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}
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Relocation :: struct #packed {
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offset: u32,
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label_id: u32,
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addend: i32,
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type: Relocation_Type,
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size: u8,
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inst_idx: u16,
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}
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#assert(size_of(Relocation) == 16)
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