mirror of
https://github.com/odin-lang/Odin.git
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248 lines
7.4 KiB
Odin
248 lines
7.4 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos6502
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import "../isa"
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// =============================================================================
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// MOS 6502 DECODER
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// =============================================================================
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//
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// Two passes, mirroring MIPS/RSP. The 6502-specific bits:
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//
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// - Variable length 1..7 bytes per instruction. The matched entry tells
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// us the byte count via `entry.length`.
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//
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// - CPU-tier filtering: the same opcode byte means different things on
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// NMOS vs 65C02 vs HuC6280 (e.g. $07 = SLO on NMOS-undoc, RMB0 on
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// 65C02). The caller passes a target `CPU` value and the matcher
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// skips entries above that tier.
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//
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// - Tier rule:
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// NMOS accepts NMOS only
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// NMOS_UNDOC accepts NMOS + NMOS_UNDOC
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// CMOS_65C02 accepts NMOS + CMOS_65C02 (NOT NMOS_UNDOC -- those
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// opcodes mean RMB/SMB/etc. on 65C02)
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// HUC6280 accepts NMOS + CMOS_65C02 + HUC6280 (also not undoc)
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//
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// - Operand extraction is the inverse of pack_operand_inline in
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// encoder.odin: pull each operand from its known offset+size in the
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// instruction byte stream.
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16,
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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cpu: CPU = .NMOS,
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) -> (byte_count: u32, ok: bool) {
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n_bytes := u32(len(data))
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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for byte_count < n_bytes {
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inst: Instruction
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info: Instruction_Info
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entry_idx, consumed := decode_one_inline(data, byte_count, n_bytes, cpu, &inst, &info)
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if entry_idx < 0 {
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append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = 1}
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info = Instruction_Info{offset = byte_count}
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consumed = 1
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} else {
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inst_idx_for_branches := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx_for_branches,
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op_idx = slot,
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target = u32(op.relative),
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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byte_count += consumed
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}
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isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs)
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal: decode one instruction starting at data[pc]
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// =============================================================================
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//
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// Returns the matched DECODE_ENTRIES index (or -1) and the number of bytes
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// consumed (always >= 1 to make forward progress).
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@(private="file")
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decode_one_inline :: #force_inline proc "contextless" (
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data: []u8, pc: u32, n_bytes: u32, cpu: CPU,
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inst: ^Instruction, info: ^Instruction_Info,
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) -> (entry_idx: int, consumed: u32) {
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opcode := data[pc]
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range := DECODE_INDEX_OPCODE[opcode]
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if range.count == 0 { return -1, 1 }
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base := int(range.start)
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cnt := int(range.count)
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matched_idx := -1
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for i in 0..<cnt {
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e := &DECODE_ENTRIES[base + i]
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if cpu_accepts(cpu, e.cpu) {
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matched_idx = base + i
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break
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}
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}
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if matched_idx < 0 { return -1, 1 }
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entry := &DECODE_ENTRIES[matched_idx]
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length := u32(entry.length)
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if pc + length > n_bytes {
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// Truncated instruction at end of buffer.
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return -1, 1
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}
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inst.mnemonic = entry.mnemonic
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inst.length = entry.length
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inst.flags = {}
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cnt_used: u8 = 0
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if entry.ops[0] != .NONE {
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inst.ops[0] = extract_operand_inline(data, pc, entry.ops[0], entry.enc[0])
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cnt_used = 1
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if entry.ops[1] != .NONE {
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inst.ops[1] = extract_operand_inline(data, pc, entry.ops[1], entry.enc[1])
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cnt_used = 2
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if entry.ops[2] != .NONE {
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inst.ops[2] = extract_operand_inline(data, pc, entry.ops[2], entry.enc[2])
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cnt_used = 3
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}
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}
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}
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inst.operand_count = cnt_used
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info.offset = pc
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info.decode_entry = u16(matched_idx)
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return matched_idx, length
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}
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// CPU tier acceptance check (see top-of-file docstring).
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@(private="file")
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cpu_accepts :: #force_inline proc "contextless" (target, entry: CPU) -> bool {
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switch target {
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case .NMOS:
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return entry == .NMOS
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case .NMOS_UNDOC:
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return entry == .NMOS || entry == .NMOS_UNDOC
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case .CMOS_65C02:
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return entry == .NMOS || entry == .CMOS_65C02
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case .HUC6280:
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return entry == .NMOS || entry == .CMOS_65C02 || entry == .HUC6280
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}
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return false
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}
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// -----------------------------------------------------------------------------
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// Operand extraction (inverse of pack_operand_inline)
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// -----------------------------------------------------------------------------
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@(private="file")
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extract_operand_inline :: #force_inline proc "contextless" (
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data: []u8, pc: u32, ot: Operand_Type, en: Operand_Encoding,
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) -> Operand {
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switch en {
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case .NONE:
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return {}
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case .IMPL:
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// The accumulator-implicit forms (ASL A, ROL A, ...) tag the
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// operand as REGISTER=A so the printer reproduces "A".
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if ot == .A_IMPL {
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return Operand{reg = A, kind = .REGISTER, size = 1}
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}
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return {}
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case .BYTE_1_IMM:
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return Operand{immediate = i64(data[pc+1]), kind = .IMMEDIATE, size = 1}
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case .BYTE_1_ADDR:
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return mem_operand(u16(data[pc+1]), ot)
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case .BYTE_1_REL:
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// PC-relative branch: target = (PC + 2) + signed_imm8
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rel := i32(i8(data[pc+1]))
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target := u32(i32(pc) + 2 + rel)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 1}
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case .WORD_1_ADDR:
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addr := u16(data[pc+1]) | (u16(data[pc+2]) << 8)
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return mem_operand(addr, ot)
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case .BYTE_2_REL:
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// BBR/BBS rel byte at offset 2; instruction is 3 bytes long.
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rel := i32(i8(data[pc+2]))
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target := u32(i32(pc) + 3 + rel)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 1}
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case .WORD_1:
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v := u16(data[pc+1]) | (u16(data[pc+2]) << 8)
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
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case .WORD_3:
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v := u16(data[pc+3]) | (u16(data[pc+4]) << 8)
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
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case .WORD_5:
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v := u16(data[pc+5]) | (u16(data[pc+6]) << 8)
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
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case .BYTE_2_ADDR:
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return mem_operand(u16(data[pc+2]), ot)
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case .WORD_2_ADDR:
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addr := u16(data[pc+2]) | (u16(data[pc+3]) << 8)
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return mem_operand(addr, ot)
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}
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return {}
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}
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// Build a MEMORY operand with the addressing mode implied by Operand_Type.
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@(private="file")
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mem_operand :: #force_inline proc "contextless" (addr: u16, ot: Operand_Type) -> Operand {
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mode: Address_Mode
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size: u8 = 1
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#partial switch ot {
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case .MEM_ZP: mode = .ZP
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case .MEM_ZP_X: mode = .ZP_X
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case .MEM_ZP_Y: mode = .ZP_Y
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case .MEM_ABS: mode = .ABS; size = 2
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case .MEM_ABS_X: mode = .ABS_X; size = 2
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case .MEM_ABS_Y: mode = .ABS_Y; size = 2
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case .MEM_IND: mode = .IND; size = 2
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case .MEM_IND_X: mode = .IND_X
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case .MEM_IND_Y: mode = .IND_Y
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case .MEM_IND_ZP: mode = .IND_ZP
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case .MEM_IND_ABS_X: mode = .IND_ABS_X; size = 2
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}
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return Operand{
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mem = Memory{address = addr, mode = mode},
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kind = .MEMORY,
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size = size,
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}
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}
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