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49 lines
1.7 KiB
Odin
49 lines
1.7 KiB
Odin
package rexcode_riscv
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// =============================================================================
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// RISC-V RELOCATIONS
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// =============================================================================
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//
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// Per the cross-arch design (§2.4): each arch owns its own Relocation_Type
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// and Relocation struct. RISC-V's relocations are unusual because two of
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// the most common ones come in *pairs* -- PCREL_HI20 on an AUIPC plus
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// PCREL_LO12_I/S on the dependent ADDI / load / store, where the LO part
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// references the AUIPC's label-relative target rather than the symbol
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// directly. We expose the pair as two related entries; pairing the
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// resolution is up to the encoder pass-2.
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Relocation_Type :: enum u8 {
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NONE = 0,
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// PC-relative branches and jumps
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BRANCH, // 13-bit signed PC-rel, B-type scatter (BEQ/BNE/...)
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JAL, // 21-bit signed PC-rel, J-type scatter (JAL)
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// PC-relative paired (AUIPC + ADDI/load/store)
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PCREL_HI20, // upper 20 bits of (sym - pc), U-type
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PCREL_LO12_I, // lower 12 bits, I-type form
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PCREL_LO12_S, // lower 12 bits, S-type form
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// Absolute paired (LUI + ADDI/load/store)
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HI20, // upper 20 of absolute, U-type
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LO12_I, // lower 12, I-type
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LO12_S, // lower 12, S-type
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// Helpful aggregate forms (the assembler can expand)
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CALL, // AUIPC + JALR pair to call a far symbol
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// ---- C extension PC-relative ----
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C_BRANCH, // 9-bit signed PC-rel for C.BEQZ / C.BNEZ
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C_JUMP, // 12-bit signed PC-rel for C.J / C.JAL
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}
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Relocation :: struct #packed {
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offset: u32,
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label_id: u32,
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addend: i32,
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type: Relocation_Type,
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size: u8,
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inst_idx: u16,
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}
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#assert(size_of(Relocation) == 16)
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