mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 08:32:33 +00:00
fae15847a3
Roll the encode/decode buffer-sizing helpers (added for x86 in 49787b7de) out
to every other ISA, and document them in the cross-arch naming contract.
Per arch (arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816):
- encode_max_code_size / encode_max_relocation_count now key off the
[]Instruction slice (were int counts); bodies unchanged (* MAX_INST_SIZE).
- encode_reserve(code, relocs, instructions): grows the caller's code []u8 by
length and reserves relocs by capacity; allocates no new buffers.
- decode_max_instruction_count / decode_estimate_instruction_count: exact
ceiling and typical estimate, keyed off the min/avg instruction size per
arch (fixed-4: arm64/mips/ppc/rsp; min-2: arm32/riscv/ppc_vle; min-1: mos).
- decode_reserve(instructions, inst_info, label_defs, data, exact=false).
docs/cross_arch_design.md: helpers added to the naming contract.
No behavior change to the existing size helpers (signature only). All 10 ISAs
check + test green (x86 2282, arm32 600, arm64 461, mips 281, riscv 154, ppc 31,
ppc_vle 281, rsp 70, mos6502 148, mos65816 53).
457 lines
17 KiB
Odin
457 lines
17 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mips
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import "core:rexcode/isa"
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// =============================================================================
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// MIPS DECODER
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// =============================================================================
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//
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// Fixed-width 4-byte decoding pipeline. Two passes (parallel to x86):
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//
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// PASS 1 - read each instruction word in the given endianness, dispatch
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// via the generated tables (DECODE_INDEX_PRIMARY plus the five
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// sub-tables in tables.odin), and emit one Instruction
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// + one Instruction_Info. Branch/jump operands are emitted as
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// RELATIVE-kind operands carrying the *absolute* target byte
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// offset within the decoded region.
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//
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// PASS 2 - call isa.infer_labels_from_branches to materialise label
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// definitions at every in-range branch target, reusing IDs from
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// `relocs` when available so symbolic names survive the round
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// trip with the encoder.
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//
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// Performance: the table dispatch is O(1) primary lookup -> O(1) sub-bucket
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// (where applicable) -> linear scan within a bucket that holds at most ~3
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// entries for normal opcodes and ~37 for COP1 single-precision (the
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// densest cell). Each candidate check is `(word & mask) == bits`, two
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// dependent ALU ops; modern cores retire the comparison in <2 cycles.
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//
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// Style mirrors `encoder.odin`: hot inner procs are `#force_inline`, the
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// per-instruction body collapses to one straight-line block.
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// -----------------------------------------------------------------------------
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// Per-decoded-instruction metadata (parallel to []Instruction).
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// -----------------------------------------------------------------------------
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//
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// `offset` -- byte offset within `data` where this instruction starts.
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// `decode_entry` -- index into DECODE_ENTRIES of the matched form; lets a
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// printer query the Feature tag / flags without re-scanning.
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16,
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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// =============================================================================
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// decode()
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// =============================================================================
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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endianness: Endianness = .BIG,
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) -> (byte_count: u32, ok: bool) {
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n_bytes := u32(len(data))
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if n_bytes & 3 != 0 {
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n_bytes &= ~u32(3) // ignore the dangling tail
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}
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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// ---- PASS 1 -----------------------------------------------------------
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for byte_count < n_bytes {
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word := read_u32(data, byte_count, endianness)
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inst: Instruction
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info: Instruction_Info
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entry_idx := decode_one_inline(word, byte_count, &inst, &info)
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if entry_idx < 0 {
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append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = 4}
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info = Instruction_Info{offset = byte_count}
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} else {
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inst_idx_for_branches := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx_for_branches,
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op_idx = slot,
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target = u32(op.relative),
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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byte_count += 4
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}
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// ---- PASS 2: label inference -----------------------------------------
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isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs)
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal: decode one 32-bit word into Instruction + Instruction_Info
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// =============================================================================
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//
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// Returns the matched DECODE_ENTRIES index on success, or -1 if no encoding
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// form matches (caller emits INVALID_OPCODE).
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@(private="file")
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decode_one_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, inst: ^Instruction, info: ^Instruction_Info,
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) -> int {
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primary := (word >> 26) & 0x3F
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range: Decode_Index
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switch primary {
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case 0x00: range = DECODE_INDEX_SPECIAL [word & 0x3F]
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case 0x01: range = DECODE_INDEX_REGIMM [(word >> 16) & 0x1F]
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case 0x11: range = DECODE_INDEX_COP1 [(word >> 21) & 0x1F]
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case 0x1C: range = DECODE_INDEX_SPECIAL2[word & 0x3F]
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case 0x1F: range = DECODE_INDEX_SPECIAL3[word & 0x3F]
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case: range = DECODE_INDEX_PRIMARY [primary]
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}
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if range.count == 0 { return -1 }
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base := int(range.start)
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cnt := int(range.count)
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matched_idx := -1
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for i in 0..<cnt {
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e := &DECODE_ENTRIES[base + i]
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if (word & e.mask) == e.bits {
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matched_idx = base + i
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break
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}
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}
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if matched_idx < 0 { return -1 }
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entry := &DECODE_ENTRIES[matched_idx]
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inst.mnemonic = entry.mnemonic
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inst.length = 4
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inst.flags = {}
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// R6 POP26/POP27 compact branches share opcodes 22/23 and are distinguished
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// only by the rs/rt relationship. The more-specific pre-R6 (rt=0) and the
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// rs=0 forms already matched earlier; here we refine the remaining group so
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// rs==rt decodes as BGEZC/BLTZC rather than the general BGEC/BLTC.
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#partial switch inst.mnemonic {
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case .BGEC, .BLEZC, .BGEZC:
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rs := (word >> 21) & 0x1F; rt := (word >> 16) & 0x1F
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inst.mnemonic = rs == 0 ? .BLEZC : (rs == rt ? .BGEZC : .BGEC)
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case .BLTC, .BGTZC, .BLTZC:
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rs := (word >> 21) & 0x1F; rt := (word >> 16) & 0x1F
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inst.mnemonic = rs == 0 ? .BGTZC : (rs == rt ? .BLTZC : .BLTC)
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}
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cnt_used: u8 = 0
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if entry.ops[0] != .NONE {
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inst.ops[0] = extract_operand_inline(word, pc, entry.ops[0], entry.enc[0])
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cnt_used = 1
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if entry.ops[1] != .NONE {
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inst.ops[1] = extract_operand_inline(word, pc, entry.ops[1], entry.enc[1])
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cnt_used = 2
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if entry.ops[2] != .NONE {
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inst.ops[2] = extract_operand_inline(word, pc, entry.ops[2], entry.enc[2])
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cnt_used = 3
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if entry.ops[3] != .NONE {
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inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3])
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cnt_used = 4
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}
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}
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}
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}
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inst.operand_count = cnt_used
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info.offset = pc
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info.decode_entry = u16(matched_idx)
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return matched_idx
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}
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// -----------------------------------------------------------------------------
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// Operand extractor -- inverse of pack_operand_inline in encoder.odin.
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// -----------------------------------------------------------------------------
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@(private="file")
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extract_operand_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, ot: Operand_Type, en: Operand_Encoding,
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) -> Operand {
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switch en {
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case .NONE:
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return {}
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// Integer / typed register slots ----------------------------------------
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case .RS:
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return reg_operand(decode_reg(word, 21, ot), ot)
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case .RT:
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return reg_operand(decode_reg(word, 16, ot), ot)
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case .RD:
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return reg_operand(decode_reg(word, 11, ot), ot)
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case .SHAMT:
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return Operand{immediate = i64((word >> 6) & 0x1F), kind = .IMMEDIATE, size = 1}
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// FPU register slots ----------------------------------------------------
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case .FT:
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return reg_operand(decode_reg(word, 16, ot), ot)
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case .FS:
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return reg_operand(decode_reg(word, 11, ot), ot)
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case .FD:
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return reg_operand(decode_reg(word, 6, ot), ot)
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case .FR:
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return reg_operand(decode_reg(word, 21, ot), ot)
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case .GPR_AT_6:
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return reg_operand(decode_reg(word, 6, ot), ot)
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case .GPR_AT_11:
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return reg_operand(decode_reg(word, 11, ot), ot)
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case .DSP_SA:
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return Operand{immediate = i64((word >> 21) & 0xF), kind = .IMMEDIATE, size = 1}
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case .RS_RT:
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return reg_operand(decode_reg(word, 16, ot), ot)
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case .AC_NUM:
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return Operand{immediate = i64((word >> 11) & 0x3), kind = .IMMEDIATE, size = 1}
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case .SHILO_IMM:
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v := i32((word >> 20) & 0x3F)
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if v & 0x20 != 0 { v |= ~i32(0x3F) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .EXT_SIZE:
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return Operand{immediate = i64((word >> 21) & 0x1F), kind = .IMMEDIATE, size = 1}
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// Immediates ------------------------------------------------------------
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case .IMM_16:
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imm: i64
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if ot == .IMM16S {
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imm = i64(i16(word & 0xFFFF)) // sign-extend
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} else {
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imm = i64(word & 0xFFFF)
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}
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return Operand{immediate = imm, kind = .IMMEDIATE, size = 2}
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case .IMM_5:
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return Operand{immediate = i64((word >> 6) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .IMM_20:
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return Operand{immediate = i64((word >> 6) & 0xFFFFF), kind = .IMMEDIATE, size = 4}
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case .IMM_26:
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if ot == .REL_J26 {
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// J-type: target_addr = ((PC+4) & 0xF0000000) | (field << 2).
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// The high 4 bits come from PC; we don't have base_address
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// at decode time, so the target reflects the data buffer's
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// own region (top 4 bits derived from `pc`).
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field := word & 0x3FFFFFF
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target := ((pc + 4) & 0xF0000000) | (field << 2)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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}
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return Operand{immediate = i64(word & 0x3FFFFFF), kind = .IMMEDIATE, size = 4}
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// Memory: rs(base) + signed imm16(disp) --------------------------------
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case .OFFSET_BASE:
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base_hw := u16((word >> 21) & 0x1F)
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disp := i32(i16(word & 0xFFFF)) // sign-extend
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m := Memory{base = Register(REG_GPR | base_hw), disp = disp}
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size: u8 = 4
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return Operand{mem = m, kind = .MEMORY, size = size}
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// PC-relative branches --------------------------------------------------
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case .BRANCH_16:
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rel := i32(i16(word & 0xFFFF)) << 2
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target := u32(i32(pc) + 4 + rel)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_21:
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rel21 := i32(word & 0x1FFFFF)
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if rel21 & (1 << 20) != 0 { rel21 |= ~i32(0x1FFFFF) }
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target := u32(i32(pc) + 4 + (rel21 << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_26:
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rel26 := i32(word & 0x3FFFFFF)
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if rel26 & (1 << 25) != 0 { rel26 |= ~i32(0x3FFFFFF) }
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target := u32(i32(pc) + 4 + (rel26 << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_19:
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// R6 PC-relative load: relative to this instruction (no +4), << 2.
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rel19 := i32(word & 0x7FFFF)
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if rel19 & (1 << 18) != 0 { rel19 |= ~i32(0x7FFFF) }
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target := u32(i32(pc) + (rel19 << 2))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .BRANCH_18:
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// LDPC: relative to this instruction aligned down to 8, << 3.
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rel18 := i32(word & 0x3FFFF)
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if rel18 & (1 << 17) != 0 { rel18 |= ~i32(0x3FFFF) }
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target := u32((i32(pc) &~ i32(7)) + (rel18 << 3))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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// Misc small immediates -------------------------------------------------
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case .FCC_BC:
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return Operand{immediate = i64((word >> 18) & 0x7), kind = .IMMEDIATE, size = 1}
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case .FCC_CC:
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return Operand{immediate = i64((word >> 8) & 0x7), kind = .IMMEDIATE, size = 1}
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case .SEL:
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return Operand{immediate = i64(word & 0x7), kind = .IMMEDIATE, size = 1}
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case .IMPL:
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return {} // implicit operand -- bits already in static pattern
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// GTE cofun sub-fields --------------------------------------------------
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case .GTE_SF_BIT:
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return Operand{immediate = i64((word >> 19) & 0x1), kind = .IMMEDIATE, size = 1}
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case .GTE_MX_BITS:
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return Operand{immediate = i64((word >> 17) & 0x3), kind = .IMMEDIATE, size = 1}
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case .GTE_V_BITS:
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return Operand{immediate = i64((word >> 15) & 0x3), kind = .IMMEDIATE, size = 1}
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case .GTE_CV_BITS:
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return Operand{immediate = i64((word >> 13) & 0x3), kind = .IMMEDIATE, size = 1}
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case .GTE_LM_BIT:
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return Operand{immediate = i64((word >> 10) & 0x1), kind = .IMMEDIATE, size = 1}
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case .VFPU_VD:
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return Operand{reg = Register(REG_VFPU | u16(word & 0x7F)), kind = .REGISTER, size = 4}
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case .VFPU_VS:
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return Operand{reg = Register(REG_VFPU | u16((word >> 8) & 0x7F)), kind = .REGISTER, size = 4}
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case .VFPU_VT:
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return Operand{reg = Register(REG_VFPU | u16((word >> 16) & 0x7F)), kind = .REGISTER, size = 4}
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case .VFPU_VT_MEM:
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hw := ((word >> 16) & 0x1F) << 2 | (word & 0x3)
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return Operand{reg = Register(REG_VFPU | u16(hw)), kind = .REGISTER, size = 4}
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case .VFPU_OFFSET_BASE:
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base := Register(REG_GPR | u16((word >> 21) & 0x1F))
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disp := i32(word & 0xFFFC)
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if disp & 0x8000 != 0 { disp |= ~i32(0xFFFF) } // sign-extend from bit 15
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return Operand{mem = Memory{base = base, disp = disp}, kind = .MEMORY, size = 4}
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case .VFPU_PFX:
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return Operand{immediate = i64(word & 0xFFFFF), kind = .IMMEDIATE, size = 4}
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case .VFPU_CONST:
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return Operand{immediate = i64((word >> 16) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .VFPU_COND4:
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return Operand{immediate = i64(word & 0xF), kind = .IMMEDIATE, size = 1}
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case .VFPU_CC3:
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return Operand{immediate = i64((word >> 18) & 0x7), kind = .IMMEDIATE, size = 1}
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// MSA 3R-format register slots.
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case .WD:
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return Operand{reg = Register(REG_MSA | u16((word >> 6) & 0x1F)), kind = .REGISTER, size = 4}
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case .WS:
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return Operand{reg = Register(REG_MSA | u16((word >> 11) & 0x1F)), kind = .REGISTER, size = 4}
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case .WT:
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return Operand{reg = Register(REG_MSA | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = 4}
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// MSA immediates / displacements.
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case .MSA_I5:
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return Operand{immediate = i64((word >> 16) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .MSA_S10:
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v := i32((word >> 16) & 0x3FF)
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if v & 0x200 != 0 { v |= ~i32(0x3FF) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
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case .MSA_BIT5:
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return Operand{immediate = i64((word >> 11) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .MSA_BIT_SHIFT:
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// m at 22:16; df from the marker, shift = m - marker.
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m := (word >> 16) & 0x7F
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sh: u32
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if m >= 0x70 { sh = m & 0x07 }
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else if m >= 0x60 { sh = m & 0x0F }
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else if m >= 0x40 { sh = m & 0x1F }
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else { sh = m & 0x3F }
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return Operand{immediate = i64(sh), kind = .IMMEDIATE, size = 1}
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case .MSA_ELM_IDX:
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// n at 21:16; df from the marker, index = n - marker.
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n := (word >> 16) & 0x3F
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idx: u32
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if n >= 0x38 { idx = n & 0x01 }
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else if n >= 0x30 { idx = n & 0x03 }
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else if n >= 0x20 { idx = n & 0x07 }
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else { idx = n & 0x0F }
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return Operand{immediate = i64(idx), kind = .IMMEDIATE, size = 1}
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case .MSA_I8:
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return Operand{immediate = i64((word >> 16) & 0xFF), kind = .IMMEDIATE, size = 1}
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case .MSA_OFFSET_BASE_B, .MSA_OFFSET_BASE_H, .MSA_OFFSET_BASE_W, .MSA_OFFSET_BASE_D:
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shift: u32 = 0
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#partial switch en {
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case .MSA_OFFSET_BASE_H: shift = 1
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case .MSA_OFFSET_BASE_W: shift = 2
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case .MSA_OFFSET_BASE_D: shift = 3
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}
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base_hw := u8((word >> 11) & 0x1F)
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v := i32((word >> 16) & 0x3FF)
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if v & 0x200 != 0 { v |= ~i32(0x3FF) }
|
|
return Operand{
|
|
mem = Memory{
|
|
base = Register(REG_GPR | u16(base_hw)),
|
|
disp = v << shift,
|
|
},
|
|
kind = .MEMORY, size = 4,
|
|
}
|
|
}
|
|
return {}
|
|
}
|
|
|
|
@(private="file")
|
|
decode_reg :: #force_inline proc "contextless" (word: u32, shift: u8, ot: Operand_Type) -> Register {
|
|
hw: u16 = u16((word >> shift) & 0x1F)
|
|
class: u16 = REG_GPR
|
|
#partial switch ot {
|
|
case .FPR_S, .FPR_D, .FPR_W, .FPR_L, .FPR_PS:
|
|
class = REG_FPR
|
|
case .FCR:
|
|
class = REG_FCR
|
|
case .CP0_REG:
|
|
class = REG_CP0
|
|
case .CP2_REG:
|
|
class = REG_CP2D
|
|
case .CP2_CTRL:
|
|
class = REG_CP2C
|
|
case .VFPU_S, .VFPU_P, .VFPU_T, .VFPU_Q, .VFPU_M_P, .VFPU_M_T, .VFPU_M_Q:
|
|
class = REG_VFPU
|
|
}
|
|
return Register(class | hw)
|
|
}
|
|
|
|
@(private="file")
|
|
reg_operand :: #force_inline proc "contextless" (r: Register, ot: Operand_Type) -> Operand {
|
|
size: u8 = 4
|
|
if ot == .FPR_D || ot == .FPR_L || ot == .FPR_PS {
|
|
size = 8
|
|
}
|
|
return Operand{reg = r, kind = .REGISTER, size = size}
|
|
}
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Buffer-Sizing Helpers (let callers pre-size so the decode hot path never
|
|
// reallocates; allocates no new buffers -- only the caller's arrays grow).
|
|
// -----------------------------------------------------------------------------
|
|
|
|
// Instruction-count ceiling for `data` (MIPS instructions are 4 bytes).
|
|
@(require_results)
|
|
decode_max_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int {
|
|
return len(data) / 4
|
|
}
|
|
|
|
// Typical-case estimate of the instruction count for `data`.
|
|
@(require_results)
|
|
decode_estimate_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int {
|
|
return len(data) / 4 + 8
|
|
}
|
|
|
|
// Pre-size the caller's decode output arrays for `data` (reserves on top of any
|
|
// existing elements; nil to skip; exact=true for the ceiling, else the estimate).
|
|
decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]Label_Definition, data: []u8, exact: bool = false) {
|
|
n := exact ? decode_max_instruction_count(data) : decode_estimate_instruction_count(data)
|
|
if instructions != nil { reserve(instructions, len(instructions) + n) }
|
|
if inst_info != nil { reserve(inst_info, len(inst_info) + n) }
|
|
if label_defs != nil { reserve(label_defs, len(label_defs) + n) }
|
|
}
|